Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3344	1			T217	16		T240	41		T423	4
all_values[1]	3151	1			T217	19		T240	24		T423	6
all_values[2]	3304	1			T217	22		T240	25		T423	2
all_values[3]	3300	1			T217	29		T240	28		T423	5
all_values[4]	3345	1			T217	35		T240	33		T517	2
all_values[5]	3434	1			T217	21		T240	21		T517	1
all_values[6]	3362	1			T217	26		T240	41		T423	5
all_values[7]	3355	1			T217	18		T240	32		T423	4
all_values[8]	3307	1			T217	22		T240	23		T423	2
all_values[9]	3305	1			T217	13		T240	44		T423	5
all_values[10]	3283	1			T217	26		T240	25		T423	3
all_values[11]	3382	1			T217	23		T240	26		T423	9
all_values[12]	3448	1			T217	28		T240	28		T423	4
all_values[13]	3346	1			T217	32		T240	40		T423	8
all_values[14]	3321	1			T217	30		T240	31		T423	2
all_values[15]	3312	1			T217	21		T240	28		T423	4
all_values[16]	3339	1			T217	16		T240	27		T423	3
all_values[17]	3345	1			T217	21		T240	27		T423	4
all_values[18]	3178	1			T217	15		T240	28		T423	5
all_values[19]	3169	1			T217	25		T240	35		T423	3
all_values[20]	3393	1			T217	26		T240	32		T423	3
all_values[21]	3367	1			T217	30		T240	19		T423	4
all_values[22]	3328	1			T217	20		T240	19		T423	1
all_values[23]	3328	1			T217	30		T240	21		T423	1
all_values[24]	3289	1			T217	18		T240	21		T423	4
all_values[25]	3310	1			T217	17		T240	37		T423	4
all_values[26]	3206	1			T217	17		T240	30		T423	5
all_values[27]	3360	1			T217	16		T240	30		T423	3
all_values[28]	3308	1			T217	19		T240	27		T423	1
all_values[29]	3420	1			T217	24		T240	26		T517	1
all_values[30]	3226	1			T217	19		T240	28		T423	4
all_values[31]	3389	1			T217	16		T240	38		T423	3
all_values[32]	3324	1			T217	22		T240	30		T423	3
all_values[33]	3411	1			T217	27		T240	26		T517	1
all_values[34]	3316	1			T217	24		T240	27		T423	3
all_values[35]	3214	1			T217	17		T240	34		T423	7
all_values[36]	3302	1			T217	25		T240	41		T423	7
all_values[37]	3271	1			T217	17		T240	31		T423	2
all_values[38]	3426	1			T217	24		T240	35		T423	3
all_values[39]	3402	1			T217	27		T240	33		T423	1
all_values[40]	3378	1			T217	22		T240	30		T423	5
all_values[41]	3318	1			T217	27		T240	26		T423	4
all_values[42]	3429	1			T217	20		T240	35		T423	4
all_values[43]	3392	1			T217	18		T240	42		T517	2
all_values[44]	3285	1			T217	19		T240	23		T423	2
all_values[45]	3406	1			T217	22		T240	27		T423	2
all_values[46]	3318	1			T217	22		T240	27		T423	6
all_values[47]	3520	1			T217	22		T240	34		T423	5
all_values[48]	3423	1			T217	27		T240	32		T423	4
all_values[49]	3337	1			T217	21		T240	20		T423	7
all_values[50]	3267	1			T217	23		T240	26		T423	5
all_values[51]	3280	1			T217	21		T240	23		T423	5
all_values[52]	3331	1			T217	32		T240	26		T423	4
all_values[53]	3337	1			T217	24		T240	30		T423	6
all_values[54]	3373	1			T217	23		T240	33		T423	4
all_values[55]	3257	1			T217	18		T240	28		T423	5
all_values[56]	3235	1			T217	23		T240	27		T423	3
all_values[57]	3307	1			T217	25		T240	23		T517	1
all_values[58]	3226	1			T217	20		T240	34		T403	3
all_values[59]	3272	1			T217	36		T240	24		T423	4
all_values[60]	3304	1			T217	25		T240	21		T423	6
all_values[61]	3380	1			T217	21		T240	30		T423	3
all_values[62]	3380	1			T217	16		T240	25		T517	1
all_values[63]	3392	1			T217	30		T240	34		T517	1