Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136685	1			T102	6		T103	7		T104	25
values[2]	9178	1			T104	1		T187	1		T456	2
values[3]	3730	1			T573	1		T542	3		T589	94
values[4]	2242	1			T542	6		T589	50		T782	6
values[5]	1432	1			T542	4		T589	20		T782	3
values[6]	974	1			T542	7		T589	12		T782	2
values[7]	715	1			T542	9		T589	1		T782	20
values[8]	486	1			T542	5		T782	12		T790	4
values[9]	387	1			T542	3		T782	4		T790	6
values[10]	322	1			T542	8		T782	8		T790	15
values[11]	312	1			T542	3		T782	6		T790	4
values[12]	344	1			T542	9		T782	7		T790	6
values[13]	256	1			T542	7		T782	11		T790	12
values[14]	296	1			T542	4		T782	4		T790	9
values[15]	263	1			T542	8		T782	4		T790	8
values[16]	319	1			T542	5		T782	18		T790	6
values[17]	270	1			T542	5		T782	3		T790	5
values[18]	280	1			T542	7		T782	6		T790	9
values[19]	269	1			T542	11		T782	8		T790	13
values[20]	277	1			T542	9		T782	11		T790	5
values[21]	289	1			T542	3		T782	5		T790	9
values[22]	294	1			T542	5		T782	10		T790	10
values[23]	273	1			T542	10		T782	14		T790	18
values[24]	257	1			T542	7		T782	5		T790	4
values[25]	261	1			T542	3		T782	3		T790	7
values[26]	259	1			T542	2		T782	3		T790	8
values[27]	250	1			T542	3		T782	4		T790	5
values[28]	292	1			T542	9		T782	5		T790	10
values[29]	286	1			T542	8		T782	5		T790	7
values[30]	264	1			T542	3		T782	23		T790	6
values[31]	250	1			T542	5		T782	11		T790	5
values[32]	256	1			T542	3		T782	4		T790	5
values[33]	263	1			T542	3		T782	16		T790	8
values[34]	274	1			T542	5		T782	7		T790	6
values[35]	265	1			T542	4		T782	4		T790	7
values[36]	248	1			T542	5		T782	4		T790	4
values[37]	264	1			T542	5		T782	6		T811	3
values[38]	277	1			T542	4		T782	5		T811	3
values[39]	303	1			T542	8		T782	21		T811	8
values[40]	203	1			T542	5		T782	4		T811	3
values[41]	255	1			T542	6		T782	16		T811	5
values[42]	224	1			T542	5		T782	3		T811	2
values[43]	264	1			T542	2		T782	10		T811	8
values[44]	237	1			T542	7		T782	10		T811	4
values[45]	239	1			T542	10		T782	9		T811	4
values[46]	263	1			T542	11		T782	17		T811	3
values[47]	249	1			T542	7		T782	7		T811	3
values[48]	222	1			T542	12		T782	2		T811	10
values[49]	204	1			T542	5		T782	6		T811	8
values[50]	196	1			T542	3		T782	5		T811	5
values[51]	201	1			T542	3		T782	16		T811	3
values[52]	186	1			T542	4		T782	3		T811	4
values[53]	188	1			T542	3		T782	3		T811	8
values[54]	169	1			T542	2		T782	5		T811	3
values[55]	144	1			T542	6		T782	2		T811	5
values[56]	218	1			T542	10		T782	18		T811	8
values[57]	207	1			T542	6		T782	6		T811	4
values[58]	188	1			T542	5		T782	7		T811	2
values[59]	178	1			T542	4		T782	8		T811	6
values[60]	161	1			T542	7		T782	5		T811	5
values[61]	178	1			T542	8		T782	14		T811	8
values[62]	165	1			T542	7		T782	6		T811	5
values[63]	138	1			T542	3		T782	9		T811	7
values[64]	151	1			T542	4		T782	3		T811	3
values[65]	150	1			T542	6		T782	3		T811	7
values[66]	104	1			T542	6		T782	3		T811	3
values[67]	106	1			T542	7		T811	6		T486	2
values[68]	101	1			T542	6		T811	10		T486	2
values[69]	112	1			T542	10		T811	7		T486	2
values[70]	121	1			T542	9		T811	7		T486	2
values[71]	132	1			T542	11		T811	10		T486	2
values[72]	130	1			T542	11		T811	17		T486	2
values[73]	135	1			T542	5		T811	12		T486	2
values[74]	129	1			T542	5		T811	7		T486	2
values[75]	119	1			T542	2		T811	3		T486	2
values[76]	107	1			T542	2		T811	3		T486	2
values[77]	106	1			T542	3		T811	8		T486	2
values[78]	108	1			T542	4		T811	6		T486	2
values[79]	96	1			T542	6		T811	5		T486	2
values[80]	91	1			T542	3		T811	7		T486	2
values[81]	88	1			T542	7		T811	3		T486	2
values[82]	89	1			T542	7		T811	4		T486	2
values[83]	92	1			T542	8		T811	9		T486	2
values[84]	100	1			T542	10		T811	6		T486	2
values[85]	116	1			T542	6		T811	6		T486	2
values[86]	117	1			T542	5		T811	9		T486	3
values[87]	104	1			T542	6		T811	5		T486	2
values[88]	123	1			T542	3		T811	9		T486	2
values[89]	96	1			T542	2		T811	9		T486	2
values[90]	94	1			T542	9		T811	3		T486	2
values[91]	82	1			T542	6		T811	5		T486	2
values[92]	111	1			T542	6		T811	14		T486	2
values[93]	75	1			T542	5		T811	7		T486	2
values[94]	89	1			T542	5		T811	8		T486	2
values[95]	102	1			T542	8		T811	7		T486	2
values[96]	103	1			T542	11		T811	10		T486	2
values[97]	103	1			T542	12		T811	12		T486	2
values[98]	89	1			T542	9		T811	10		T486	3
values[99]	110	1			T542	9		T811	5		T486	5
values[100]	87	1			T542	6		T811	2		T486	7
values[101]	94	1			T542	5		T486	4		T788	13
values[102]	83	1			T542	4		T486	3		T788	8
values[103]	78	1			T542	10		T486	3		T788	2
values[104]	80	1			T542	8		T486	2		T788	3
values[105]	88	1			T542	12		T486	4		T788	3
values[106]	72	1			T542	11		T486	3		T788	3
values[107]	87	1			T542	11		T486	8		T788	4
values[108]	97	1			T542	9		T486	7		T788	11
values[109]	91	1			T542	13		T486	5		T788	2
values[110]	96	1			T542	10		T486	3		T788	2
values[111]	89	1			T542	9		T486	4		T788	4
values[112]	82	1			T542	8		T486	2		T788	4
values[113]	82	1			T542	8		T486	2		T788	7
values[114]	69	1			T542	5		T486	3		T788	5
values[115]	67	1			T542	9		T486	2		T788	7
values[116]	84	1			T542	11		T486	2		T788	7
values[117]	98	1			T542	13		T486	3		T788	7
values[118]	89	1			T542	8		T486	3		T788	2
values[119]	90	1			T542	9		T486	4		T788	1
values[120]	92	1			T542	10		T486	3		T788	8
values[121]	84	1			T542	5		T486	3		T788	8
values[122]	92	1			T542	4		T486	3		T788	6
values[123]	85	1			T542	12		T486	5		T788	4
values[124]	89	1			T542	16		T486	7		T788	3
values[125]	120	1			T542	19		T486	5		T788	2
values[126]	167	1			T542	33		T486	9		T788	3
values[127]	982	1			T542	76		T486	49		T788	4
values[128]	7779	1			T542	33		T486	581		T788	4