Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	160991	1			T102	2		T103	7		T104	13
values[2]	5068	1			T102	1		T104	1		T411	1
values[3]	2685	1			T542	8		T801	55		T475	1
values[4]	1910	1			T542	4		T801	57		T466	30
values[5]	1597	1			T542	5		T801	53		T466	42
values[6]	1276	1			T542	4		T801	49		T466	36
values[7]	1047	1			T542	5		T801	34		T466	22
values[8]	949	1			T542	6		T801	22		T466	12
values[9]	888	1			T542	9		T801	10		T466	37
values[10]	782	1			T542	6		T801	15		T466	47
values[11]	765	1			T542	4		T801	22		T466	75
values[12]	681	1			T542	5		T801	11		T466	49
values[13]	612	1			T542	4		T801	31		T466	39
values[14]	481	1			T542	5		T801	14		T466	9
values[15]	413	1			T542	4		T801	2		T466	5
values[16]	389	1			T542	2		T788	1		T813	5
values[17]	395	1			T542	3		T788	1		T813	1
values[18]	379	1			T542	2		T788	7		T822	1
values[19]	317	1			T542	6		T788	2		T822	1
values[20]	326	1			T542	3		T788	2		T822	3
values[21]	273	1			T542	3		T788	3		T822	1
values[22]	271	1			T542	3		T788	2		T822	1
values[23]	242	1			T542	2		T788	5		T822	2
values[24]	216	1			T542	7		T788	5		T822	4
values[25]	216	1			T542	5		T788	6		T822	5
values[26]	210	1			T542	4		T788	5		T822	1
values[27]	240	1			T542	6		T788	2		T822	1
values[28]	311	1			T542	6		T788	1		T822	4
values[29]	310	1			T542	6		T788	1		T822	5
values[30]	295	1			T542	5		T788	2		T822	4
values[31]	297	1			T542	4		T788	4		T822	2
values[32]	234	1			T542	5		T788	1		T822	1
values[33]	174	1			T542	5		T788	2		T822	1
values[34]	141	1			T542	6		T788	1		T822	2
values[35]	124	1			T542	3		T788	7		T822	2
values[36]	86	1			T542	2		T788	5		T822	1
values[37]	73	1			T542	4		T788	2		T822	4
values[38]	62	1			T542	5		T788	1		T822	3
values[39]	69	1			T542	8		T788	3		T822	2
values[40]	71	1			T542	6		T788	6		T822	4
values[41]	58	1			T542	3		T788	2		T822	1
values[42]	65	1			T542	4		T788	7		T822	3
values[43]	68	1			T542	10		T788	1		T822	1
values[44]	75	1			T542	3		T788	3		T822	7
values[45]	82	1			T542	6		T788	3		T822	4
values[46]	70	1			T542	3		T788	1		T822	2
values[47]	70	1			T542	5		T788	2		T822	3
values[48]	66	1			T542	4		T788	1		T822	2
values[49]	77	1			T542	7		T788	2		T822	3
values[50]	70	1			T542	5		T788	1		T822	1
values[51]	69	1			T542	5		T788	4		T822	4
values[52]	70	1			T542	2		T788	2		T822	5
values[53]	63	1			T542	3		T788	2		T822	6
values[54]	58	1			T542	4		T788	3		T822	4
values[55]	74	1			T542	6		T788	5		T822	2
values[56]	79	1			T542	6		T788	5		T822	1
values[57]	81	1			T542	4		T788	5		T822	2
values[58]	68	1			T542	8		T788	5		T822	2
values[59]	56	1			T542	5		T788	1		T822	3
values[60]	60	1			T542	3		T788	3		T822	4
values[61]	65	1			T542	4		T788	2		T822	3
values[62]	67	1			T542	4		T788	3		T822	1
values[63]	61	1			T542	7		T788	1		T822	2
values[64]	59	1			T542	5		T788	1		T822	1
values[65]	75	1			T542	6		T788	2		T822	3
values[66]	71	1			T542	7		T788	1		T822	2
values[67]	64	1			T542	4		T788	2		T822	5
values[68]	59	1			T542	6		T788	1		T822	5
values[69]	75	1			T542	4		T788	2		T822	6
values[70]	61	1			T542	2		T788	2		T822	3
values[71]	65	1			T542	6		T788	3		T822	1
values[72]	68	1			T542	9		T788	2		T822	1
values[73]	57	1			T542	3		T788	2		T822	3
values[74]	64	1			T542	3		T788	3		T822	6
values[75]	62	1			T542	5		T788	1		T822	2
values[76]	76	1			T542	3		T788	2		T822	1
values[77]	62	1			T542	2		T788	4		T822	1
values[78]	79	1			T542	2		T788	10		T822	1
values[79]	68	1			T542	3		T788	9		T822	3
values[80]	80	1			T542	5		T788	5		T822	3
values[81]	83	1			T542	6		T788	4		T822	2
values[82]	89	1			T542	4		T788	4		T822	2
values[83]	87	1			T542	4		T788	6		T822	1
values[84]	84	1			T542	4		T788	8		T822	2
values[85]	91	1			T542	4		T788	9		T822	4
values[86]	88	1			T542	6		T788	5		T822	5
values[87]	91	1			T542	6		T788	2		T822	4
values[88]	89	1			T542	4		T788	2		T822	2
values[89]	105	1			T542	12		T788	2		T822	7
values[90]	78	1			T542	7		T788	4		T822	1
values[91]	137	1			T542	9		T788	8		T822	4
values[92]	89	1			T542	4		T788	4		T822	3
values[93]	110	1			T542	6		T788	1		T822	10
values[94]	85	1			T542	7		T788	2		T822	4
values[95]	89	1			T542	6		T788	3		T822	1
values[96]	90	1			T542	7		T788	2		T822	2
values[97]	101	1			T542	7		T788	2		T822	3
values[98]	103	1			T542	11		T788	8		T822	1
values[99]	117	1			T542	10		T788	2		T822	1
values[100]	101	1			T542	7		T788	3		T822	3
values[101]	93	1			T542	7		T788	9		T822	3
values[102]	100	1			T542	10		T788	5		T822	1
values[103]	115	1			T542	6		T788	5		T822	6
values[104]	106	1			T542	10		T788	4		T822	6
values[105]	125	1			T542	7		T788	3		T822	2
values[106]	126	1			T542	6		T788	6		T822	2
values[107]	135	1			T542	10		T788	7		T822	8
values[108]	112	1			T542	10		T788	1		T822	7
values[109]	127	1			T542	10		T788	3		T822	4
values[110]	116	1			T542	6		T788	2		T822	9
values[111]	118	1			T542	5		T788	8		T822	4
values[112]	112	1			T542	8		T788	7		T822	4
values[113]	120	1			T542	8		T788	6		T822	3
values[114]	106	1			T542	3		T788	3		T822	1
values[115]	113	1			T542	5		T788	5		T822	2
values[116]	102	1			T542	3		T788	4		T822	2
values[117]	114	1			T542	3		T788	1		T822	4
values[118]	125	1			T542	10		T788	3		T822	5
values[119]	120	1			T542	11		T788	4		T822	2
values[120]	101	1			T542	11		T788	4		T822	2
values[121]	119	1			T542	10		T788	3		T822	7
values[122]	110	1			T542	8		T788	8		T822	3
values[123]	152	1			T542	20		T788	5		T822	5
values[124]	230	1			T542	34		T788	17		T822	9
values[125]	476	1			T542	66		T788	31		T822	31
values[126]	1136	1			T542	101		T788	42		T822	54
values[127]	3326	1			T542	69		T788	12		T822	23
values[128]	5249	1			T542	10		T788	2		T822	4