Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	152904	1			T102	3		T103	7		T104	15
values[2]	5694	1			T104	1		T187	1		T551	1
values[3]	2942	1			T542	4		T569	1		T525	17
values[4]	2081	1			T542	4		T525	13		T816	1
values[5]	1665	1			T542	3		T525	9		T816	1
values[6]	1518	1			T542	1		T525	14		T816	1
values[7]	1382	1			T542	1		T525	15		T816	1
values[8]	1297	1			T542	2		T525	27		T816	1
values[9]	1280	1			T542	3		T525	17		T816	1
values[10]	1080	1			T542	1		T525	26		T816	1
values[11]	840	1			T542	2		T525	18		T816	1
values[12]	717	1			T542	1		T525	8		T816	1
values[13]	656	1			T542	5		T525	8		T816	1
values[14]	641	1			T542	4		T525	12		T816	1
values[15]	551	1			T542	7		T525	10		T816	1
values[16]	537	1			T542	5		T525	6		T816	1
values[17]	498	1			T542	1		T525	4		T816	1
values[18]	350	1			T542	1		T525	7		T816	1
values[19]	303	1			T542	1		T525	42		T816	1
values[20]	293	1			T542	4		T525	33		T816	1
values[21]	291	1			T542	5		T525	33		T816	1
values[22]	252	1			T542	5		T525	19		T816	1
values[23]	175	1			T542	5		T525	7		T816	1
values[24]	130	1			T542	3		T525	13		T816	1
values[25]	156	1			T542	3		T525	15		T816	1
values[26]	164	1			T542	4		T525	10		T816	1
values[27]	220	1			T542	5		T525	20		T816	1
values[28]	203	1			T542	1		T525	24		T816	1
values[29]	167	1			T542	1		T525	11		T816	1
values[30]	186	1			T542	3		T525	7		T816	1
values[31]	179	1			T542	3		T525	9		T816	1
values[32]	183	1			T542	1		T525	5		T816	1
values[33]	181	1			T542	1		T525	11		T816	1
values[34]	134	1			T542	3		T525	9		T816	1
values[35]	81	1			T542	3		T525	3		T816	1
values[36]	68	1			T542	2		T525	1		T816	1
values[37]	66	1			T542	1		T525	5		T816	1
values[38]	54	1			T542	3		T525	5		T816	1
values[39]	54	1			T542	5		T525	5		T816	1
values[40]	53	1			T542	2		T525	2		T816	1
values[41]	44	1			T542	5		T816	1		T486	1
values[42]	41	1			T542	1		T816	1		T486	1
values[43]	48	1			T542	1		T816	1		T486	1
values[44]	44	1			T542	2		T816	1		T486	1
values[45]	56	1			T542	1		T816	1		T486	1
values[46]	50	1			T542	3		T816	1		T486	1
values[47]	51	1			T542	3		T816	1		T486	1
values[48]	68	1			T542	3		T816	1		T486	1
values[49]	66	1			T542	3		T816	1		T486	1
values[50]	57	1			T542	1		T816	1		T486	1
values[51]	62	1			T542	1		T816	1		T486	1
values[52]	39	1			T542	3		T816	1		T486	1
values[53]	35	1			T542	1		T816	1		T486	1
values[54]	33	1			T542	1		T816	1		T486	1
values[55]	51	1			T542	4		T816	1		T486	1
values[56]	40	1			T542	1		T816	1		T486	1
values[57]	39	1			T542	3		T816	1		T486	1
values[58]	37	1			T542	1		T816	1		T486	1
values[59]	40	1			T542	1		T816	1		T486	1
values[60]	49	1			T542	2		T816	1		T486	1
values[61]	43	1			T542	2		T816	1		T486	1
values[62]	40	1			T542	3		T816	1		T486	1
values[63]	41	1			T542	1		T816	1		T486	1
values[64]	38	1			T542	3		T816	1		T486	1
values[65]	37	1			T542	5		T816	1		T486	1
values[66]	36	1			T542	2		T816	1		T486	1
values[67]	42	1			T542	1		T816	1		T486	1
values[68]	36	1			T542	1		T816	1		T486	1
values[69]	37	1			T542	4		T816	1		T486	1
values[70]	48	1			T542	1		T816	1		T486	1
values[71]	39	1			T542	1		T816	1		T486	1
values[72]	34	1			T542	2		T816	1		T486	1
values[73]	46	1			T542	2		T816	1		T486	1
values[74]	40	1			T542	2		T816	1		T486	1
values[75]	39	1			T542	2		T816	1		T486	1
values[76]	48	1			T542	2		T816	1		T486	1
values[77]	50	1			T542	2		T816	1		T486	1
values[78]	45	1			T542	1		T816	1		T486	1
values[79]	48	1			T542	4		T816	1		T486	1
values[80]	53	1			T542	4		T816	1		T486	1
values[81]	53	1			T542	1		T816	1		T486	1
values[82]	58	1			T542	3		T816	1		T486	1
values[83]	45	1			T542	2		T816	2		T486	1
values[84]	42	1			T542	3		T816	1		T486	1
values[85]	43	1			T542	5		T816	1		T486	1
values[86]	58	1			T542	2		T816	1		T486	1
values[87]	71	1			T542	3		T816	1		T486	1
values[88]	57	1			T542	3		T816	1		T486	1
values[89]	57	1			T542	7		T816	1		T486	1
values[90]	52	1			T542	5		T816	1		T486	1
values[91]	67	1			T542	9		T816	1		T486	1
values[92]	70	1			T542	3		T816	1		T486	2
values[93]	56	1			T542	2		T816	1		T486	1
values[94]	55	1			T542	4		T816	1		T486	1
values[95]	56	1			T542	7		T816	1		T486	1
values[96]	59	1			T542	3		T816	1		T486	2
values[97]	71	1			T542	5		T816	1		T486	3
values[98]	68	1			T542	4		T816	1		T486	1
values[99]	67	1			T542	4		T816	1		T486	1
values[100]	62	1			T542	4		T816	1		T486	1
values[101]	73	1			T542	3		T816	1		T486	1
values[102]	59	1			T542	4		T816	1		T486	1
values[103]	61	1			T542	2		T816	1		T486	3
values[104]	69	1			T542	2		T816	1		T486	3
values[105]	74	1			T542	5		T816	1		T486	1
values[106]	57	1			T542	4		T816	1		T486	2
values[107]	73	1			T542	5		T816	1		T486	6
values[108]	73	1			T542	2		T816	1		T486	4
values[109]	84	1			T542	3		T816	1		T486	6
values[110]	68	1			T542	2		T816	1		T486	4
values[111]	56	1			T542	4		T816	1		T486	1
values[112]	70	1			T542	5		T816	1		T486	1
values[113]	86	1			T542	9		T816	1		T486	5
values[114]	76	1			T542	4		T816	1		T486	2
values[115]	74	1			T542	3		T816	1		T486	1
values[116]	74	1			T542	8		T816	1		T486	2
values[117]	70	1			T542	5		T816	1		T486	2
values[118]	72	1			T542	1		T816	1		T486	2
values[119]	75	1			T542	3		T816	1		T486	2
values[120]	86	1			T542	5		T816	1		T486	1
values[121]	75	1			T542	4		T816	1		T486	3
values[122]	94	1			T542	6		T816	1		T486	2
values[123]	120	1			T542	10		T816	1		T486	1
values[124]	182	1			T542	16		T816	3		T486	1
values[125]	374	1			T542	42		T816	2		T486	2
values[126]	705	1			T542	55		T816	7		T486	13
values[127]	2631	1			T542	35		T816	111		T486	103
values[128]	4690	1			T542	2		T816	204		T486	256