Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	461	1			T551	1		T549	2		T489	1
all_values[1]	465	1			T549	2		T589	6		T823	6
all_values[2]	481	1			T456	2		T440	2		T542	1
all_values[3]	518	1			T456	1		T549	1		T489	1
all_values[4]	467	1			T551	1		T440	1		T542	1
all_values[5]	465	1			T549	4		T589	3		T823	3
all_values[6]	470	1			T551	1		T677	1		T489	1
all_values[7]	458	1			T551	3		T549	4		T489	1
all_values[8]	495	1			T551	1		T549	4		T542	1
all_values[9]	491	1			T549	3		T677	1		T589	3
all_values[10]	424	1			T551	1		T549	1		T542	1
all_values[11]	453	1			T549	1		T589	5		T823	1
all_values[12]	468	1			T456	1		T549	3		T589	2
all_values[13]	483	1			T548	1		T551	1		T456	1
all_values[14]	475	1			T548	1		T551	2		T549	1
all_values[15]	418	1			T551	1		T456	1		T643	1
all_values[16]	453	1			T551	1		T456	1		T589	8
all_values[17]	419	1			T551	2		T677	1		T589	3
all_values[18]	513	1			T548	1		T551	1		T456	1
all_values[19]	444	1			T677	1		T589	4		T823	4
all_values[20]	505	1			T548	1		T551	2		T549	3
all_values[21]	492	1			T542	1		T589	3		T823	5
all_values[22]	471	1			T549	2		T589	4		T823	3
all_values[23]	505	1			T551	1		T549	3		T542	2
all_values[24]	483	1			T548	1		T551	2		T589	3
all_values[25]	481	1			T440	1		T549	1		T589	2
all_values[26]	450	1			T551	2		T549	1		T542	2
all_values[27]	488	1			T551	2		T549	3		T589	2
all_values[28]	491	1			T551	2		T549	4		T489	1
all_values[29]	507	1			T549	1		T542	1		T589	7
all_values[30]	479	1			T551	1		T440	1		T589	2
all_values[31]	480	1			T549	1		T542	1		T589	4
all_values[32]	487	1			T548	1		T551	2		T440	1
all_values[33]	471	1			T548	1		T440	1		T589	4
all_values[34]	446	1			T551	1		T549	2		T589	6
all_values[35]	498	1			T551	1		T440	1		T542	2
all_values[36]	485	1			T456	3		T677	1		T589	4
all_values[37]	488	1			T548	1		T551	1		T456	1
all_values[38]	488	1			T489	1		T589	6		T823	4
all_values[39]	499	1			T551	2		T549	2		T489	1
all_values[40]	475	1			T548	2		T551	1		T549	4
all_values[41]	489	1			T548	1		T551	1		T440	1
all_values[42]	440	1			T551	1		T549	1		T589	5
all_values[43]	511	1			T456	1		T440	1		T542	1
all_values[44]	472	1			T551	1		T456	1		T542	1
all_values[45]	459	1			T551	3		T440	1		T549	2
all_values[46]	465	1			T551	2		T549	2		T677	1
all_values[47]	476	1			T549	1		T489	1		T589	5
all_values[48]	467	1			T551	2		T456	1		T677	1
all_values[49]	512	1			T548	1		T551	2		T456	1