Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3414	1			T411	1		T551	4		T549	10
all_values[1]	3426	1			T551	3		T440	1		T549	23
all_values[2]	3468	1			T551	7		T440	1		T549	14
all_values[3]	3476	1			T411	2		T551	2		T440	3
all_values[4]	3478	1			T411	1		T551	6		T440	1
all_values[5]	3420	1			T411	2		T551	6		T440	2
all_values[6]	3486	1			T551	1		T549	14		T635	12
all_values[7]	3472	1			T551	2		T549	18		T635	5
all_values[8]	3519	1			T551	7		T549	8		T593	1
all_values[9]	3331	1			T411	1		T551	9		T549	12
all_values[10]	3591	1			T551	6		T549	12		T635	2
all_values[11]	3402	1			T551	6		T549	8		T635	5
all_values[12]	3491	1			T411	1		T551	4		T440	1
all_values[13]	3428	1			T551	5		T440	2		T549	17
all_values[14]	3417	1			T411	1		T551	12		T549	13
all_values[15]	3397	1			T551	5		T549	14		T635	5
all_values[16]	3507	1			T411	1		T551	4		T440	3
all_values[17]	3377	1			T411	1		T551	4		T549	16
all_values[18]	3516	1			T411	1		T551	6		T549	7
all_values[19]	3490	1			T551	6		T549	13		T593	1
all_values[20]	3465	1			T411	1		T551	4		T549	13
all_values[21]	3475	1			T551	10		T440	1		T549	13
all_values[22]	3455	1			T551	6		T549	13		T635	7
all_values[23]	3435	1			T551	9		T549	14		T635	8
all_values[24]	3477	1			T551	6		T549	9		T635	10
all_values[25]	3444	1			T551	3		T549	11		T635	5
all_values[26]	3401	1			T551	3		T549	11		T593	1
all_values[27]	3443	1			T551	7		T549	12		T635	6
all_values[28]	3446	1			T411	1		T551	3		T549	4
all_values[29]	3457	1			T411	1		T551	4		T549	17
all_values[30]	3465	1			T551	4		T549	7		T593	1
all_values[31]	3378	1			T411	1		T551	4		T549	14
all_values[32]	3485	1			T551	4		T549	13		T593	1
all_values[33]	3445	1			T551	8		T440	1		T549	15
all_values[34]	3534	1			T411	1		T551	8		T549	10
all_values[35]	3516	1			T551	3		T440	1		T549	13
all_values[36]	3389	1			T551	7		T549	13		T635	9
all_values[37]	3480	1			T411	1		T551	7		T440	1
all_values[38]	3526	1			T551	4		T440	1		T549	13
all_values[39]	3478	1			T551	7		T549	16		T635	15
all_values[40]	3444	1			T411	1		T551	5		T549	10
all_values[41]	3520	1			T551	6		T440	2		T549	13
all_values[42]	3430	1			T551	3		T549	14		T593	1
all_values[43]	3415	1			T551	4		T549	10		T635	7
all_values[44]	3442	1			T411	1		T551	4		T440	2
all_values[45]	3548	1			T551	5		T549	10		T593	1
all_values[46]	3410	1			T411	1		T551	4		T549	16
all_values[47]	3389	1			T411	1		T551	2		T549	13
all_values[48]	3502	1			T551	4		T549	17		T635	1
all_values[49]	3454	1			T551	4		T549	15		T593	1
all_values[50]	3496	1			T551	7		T440	2		T549	15
all_values[51]	3514	1			T551	6		T549	11		T635	5
all_values[52]	3486	1			T411	1		T551	4		T549	16
all_values[53]	3471	1			T551	4		T440	2		T549	11
all_values[54]	3616	1			T551	7		T440	2		T549	11
all_values[55]	3543	1			T411	2		T551	8		T440	1
all_values[56]	3475	1			T551	5		T549	11		T635	5
all_values[57]	3481	1			T411	2		T551	7		T549	14
all_values[58]	3551	1			T551	6		T549	10		T635	7
all_values[59]	3479	1			T551	7		T440	1		T549	14
all_values[60]	3481	1			T411	1		T549	11		T635	1
all_values[61]	3442	1			T411	1		T551	3		T440	2
all_values[62]	3445	1			T551	7		T549	14		T635	3
all_values[63]	3534	1			T551	3		T440	1		T549	10