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 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T48,T49,T50
1	0	1	Covered	T48,T49,T50
1	1	0	Covered	T643,T489,T542
1	1	1	Covered	T402,T86,T136

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T48,T49,T50
1	0	1	Covered	T50,T64,T282
1	1	0	Covered	T548,T551,T643
1	1	1	Covered	T64,T65,T548

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T64,T65,T105
1	1	0	Not Covered
1	1	1	Covered	T8,T5,T6

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T64,T65,T105
1	1	0	Covered	T604
1	1	1	Covered	T8,T5,T6

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T5,T6
1	0	1	Covered	T64,T65,T548
1	1	0	Covered	T644
1	1	1	Covered	T2,T3,T4