Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T126 T36 T333 | T126 T36 T333 | T126 T36 T333 | T126 T36 T333 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T126 T36 T333 | T131 T333 T132 | T131 T333 T132 | T131 T333 T132 | T131 T333 T132 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T131 T333 T132 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T32 T78 T79 | T31 T333 T80 | T31 T333 T80 | T31 T333 T80 | T31 T333 T80 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T31 T333 T80 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T13 T128 T239 | T128 T193 T194 | T128 T193 T194 | T128 T193 T194 | T128 T193 T194 | T17 T128 T55 | T128 T193 T194 | T128 T193 T194 | T73 T340 T74 | T73 T340 T74 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T73 T340 T74 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T75 T340 T138 | T75 T340 T138 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T35 T75 T340 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T76 T340 T139 | T76 T340 T139 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T76 T340 T77 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T6 T128 T193 | T128 T135 T193 | T128 T193 T194 | T128 T193 T194 | T128 T193 T194 | T49 T198 T343 | T50 T195 T198 | T48 T340 T344 | T198 T340 T345 | T128 T193 T194 | T128 T193 T194 | T128 T193 T194 | T128 T193 T194 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T7 T16 T199 | T82 T333 T247 | T140 T340 T141 | T280 T252 T340 | T251 T252 T198 | T181 T128 T346 | T128 T193 T194 | T5 T334 T146 | T5 T334 T146 | T334 T146 T340 | T334 T146 T340 | T5 T334 T146 | T340 T341 T342 | T335 T336 T340 | T340 T341 T342 | T340 T341 T342 | T128 T193 T194 | T128 T193 T194 | T128 T193 T194 | T159 T128 T185 | T128 T193 T194 | T340 T341 T342 | T337 T340 T347 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T337 T340 T347 | T340 T341 T342 | T337 T340 T347 | T340 T341 T342
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T268 T269 T332 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T17 T33 T13 | T17 T268 T128 | T17 T268 T128 | T17 T13 T14 | T17 T13 T14 | T17 T268 T128 | T268 T128 T333 | T268 T128 T333 | T73 T268 T128 | T73 T268 T128 | T268 T128 T333 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T268 T128 T333 | T73 T268 T128 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T75 T268 T128 | T75 T268 T128 | T268 T128 T333 | T75 T268 T128 | T75 T268 T128 | T75 T268 T128 | T75 T268 T128 | T75 T268 T128 | T268 T128 T333 | T35 T75 T268 | T35 T268 T128 | T268 T128 T333 | T35 T268 T128 | T35 T268 T128 | T35 T268 T128 | T76 T268 T128 | T76 T268 T128 | T268 T128 T333 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T268 T128 T333 | T76 T268 T128 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T6 T268 T128 | T6 T268 T128 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T48 T49 T50 | T48 T49 T50 | T48 T49 T50 | T48 T49 T50 | T13 T14 T268 | T13 T14 T268 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T7 T16 T280 | T82 T268 T128 | T140 T268 T128 | T48 T49 T50 | T48 T49 T50 | T181 T268 T128 | T268 T128 T333 | T5 T334 T146 | T5 T334 T146 | T5 T334 T146 | T5 T334 T146 | T5 T334 T146 | T268 T128 T333 | T335 T336 T268 | T335 T336 T268 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T159 T268 T128 | T268 T128 T333 | T268 T128 T333 | T337 T268 T128 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T337 T268 T128 | T268 T128 T333 | T337 T268 T128 | T268 T128 T333
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T5 T6 T7 | T6 T49 T31 | T31 T32 T126 | T6 T49 T17 | T5 T7 T48 | T31 T32 T126 | T31 T33 T268 | T17 T33 T13 | T6 T49 T35 | T7 T48 T49 | T5 T334 T146 | T126 T131 T36 | T31 T32 T131 | T31 T33 T268 | T33 T268 T128 | T17 T33 T13 | T75 T73 T268 | T35 T75 T76 | T6 T49 T76 | T48 T49 T50 | T7 T16 T251 | T5 T334 T146 | T337 T268 T128 | T126 T36 T268 | T126 T131 T36 | T32 T131 T78 | T31 T32 T78 | T31 T33 T268 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T13 T268 | T17 T13 T73 | T73 T268 T128 | T75 T268 T128 | T35 T75 T268 | T35 T76 T268 | T76 T268 T128 | T6 T49 T198 | T48 T49 T50 | T268 T128 T333 | T268 T128 T333 | T7 T48 T49 | T5 T334 T146 | T159 T337 T268 | T337 T268 T128 | T126 T36 T268 | T126 T36 T268 | T126 T131 T36 | T131 T268 T128 | T32 T131 T78 | T32 T78 T79 | T32 T78 T79 | T31 T268 T128 | T31 T268 T128 | T31 T33 T268 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T17 T33 T13 | T17 T13 T14 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T268 T128 T333 | T75 T268 T128 | T75 T268 T128 | T35 T75 T268 | T35 T76 T268 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T6 T268 T128 | T49 T198 T343 | T48 T49 T50 | T13 T14 T268 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T7 T16 T82 | T48 T49 T50 | T5 T334 T146 | T5 T334 T146 | T268 T128 T333 | T159 T337 T268 | T268 T128 T333 | T337 T268 T128 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T32 T131 T78 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T31 T33 T268 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T17 T33 T13 | T17 T268 T128 | T17 T13 T14 | T17 T268 T128 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T268 T128 T333 | T268 T128 T333 | T75 T268 T128 | T75 T268 T128 | T75 T268 T128 | T75 T268 T128 | T35 T75 T268 | T35 T268 T128 | T35 T268 T128 | T35 T76 T268 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T268 T128 T333 | T268 T128 T333 | T6 T268 T128 | T268 T128 T333 | T48 T49 T50 | T48 T49 T50 | T48 T49 T50 | T13 T14 T268 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T7 T16 T280 | T82 T140 T268 | T48 T49 T50 | T181 T268 T128 | T5 T334 T146 | T5 T334 T146 | T5 T334 T146 | T335 T336 T268 | T268 T128 T333 | T268 T128 T333 | T159 T268 T128 | T337 T268 T128 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T337 T268 T128 | T337 T268 T128
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T5 T6 T7 | T6 T49 T31 | T5 T7 T48 | T31 T32 T126 | T6 T49 T17 | T5 T7 T48 | T31 T32 T126 | T31 T33 T333 | T17 T33 T13 | T6 T49 T35 | T7 T48 T50 | T5 T334 T146 | T126 T131 T36 | T31 T32 T131 | T31 T33 T333 | T33 T340 T46 | T17 T33 T13 | T75 T73 T340 | T35 T75 T76 | T6 T49 T76 | T48 T50 T195 | T7 T16 T251 | T5 T334 T146 | T337 T340 T347 | T126 T36 T333 | T126 T131 T36 | T32 T131 T78 | T31 T32 T78 | T31 T33 T333 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T13 T128 | T17 T73 T128 | T73 T340 T74 | T75 T340 T138 | T35 T75 T340 | T76 T340 T139 | T76 T340 T77 | T6 T49 T198 | T48 T50 T195 | T333 T338 T339 | T333 T338 T339 | T7 T16 T251 | T5 T334 T146 | T159 T337 T128 | T337 T340 T347 | T337 T340 T347 | T126 T36 T333 | T126 T36 T333 | T126 T131 T36 | T131 T333 T132 | T32 T131 T78 | T32 T78 T79 | T32 T78 T79 | T31 T333 T80 | T333 T338 T339 | T31 T33 T333 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T13 T128 | T17 T128 T55 | T73 T128 T340 | T340 T341 T342 | T73 T340 T74 | T340 T341 T342 | T75 T340 T138 | T340 T341 T342 | T35 T75 T340 | T76 T340 T139 | T76 T340 T139 | T340 T341 T342 | T76 T340 T77 | T6 T128 T340 | T49 T198 T343 | T48 T50 T195 | T128 T333 T193 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T7 T16 T82 | T251 T280 T252 | T5 T334 T146 | T5 T334 T146 | T128 T340 T193 | T159 T337 T128 | T340 T341 T342 | T337 T340 T347 | T337 T340 T347 | T126 T36 T333 | T126 T36 T333 | T126 T36 T333 | T333 T338 T339 | T126 T36 T333 | T131 T333 T132 | T131 T333 T132 | T333 T338 T339 | T333 T338 T339 | T32 T131 T78 | T32 T78 T79 | T32 T78 T79 | T333 T338 T339 | T32 T78 T79 | T31 T333 T80 | T31 T333 T80 | T333 T338 T339 | T333 T338 T339 | T31 T33 T333 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T13 T128 | T128 T193 T194 | T128 T193 T194 | T17 T128 T55 | T73 T128 T340 | T73 T340 T74 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T73 T340 T74 | T340 T341 T342 | T340 T341 T342 | T75 T340 T138 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T35 T75 T340 | T340 T341 T342 | T340 T341 T342 | T76 T340 T139 | T76 T340 T139 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T76 T340 T77 | T340 T341 T342 | T340 T341 T342 | T6 T128 T135 | T128 T193 T194 | T49 T198 T343 | T48 T50 T195 | T198 T128 T340 | T128 T193 T194 | T128 T333 T193 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T7 T16 T199 | T82 T140 T333 | T251 T280 T252 | T181 T128 T346 | T5 T334 T146 | T334 T146 T340 | T5 T334 T146 | T335 T336 T340 | T128 T340 T193 | T128 T193 T194 | T159 T128 T185 | T337 T340 T347 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T337 T340 T347 | T337 T340 T347
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T5 T6 T7 | T6 T49 T31 | T5 T7 T48 | T31 T32 T126 | T6 T49 T17 | T5 T7 T48 | T31 T32 T126 | T31 T33 T333 | T17 T33 T13 | T6 T49 T35 | T7 T48 T16 | T5 T334 T146 | T126 T131 T36 | T31 T32 T131 | T31 T33 T333 | T33 T340 T46 | T17 T33 T13 | T75 T73 T340 | T35 T75 T76 | T6 T49 T76 | T48 T198 T128 | T7 T16 T251 | T5 T334 T146 | T337 T340 T347 | T126 T36 T333 | T126 T131 T36 | T32 T131 T78 | T31 T32 T78 | T31 T33 T333 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T13 T128 | T17 T73 T128 | T73 T340 T74 | T75 T340 T138 | T35 T75 T340 | T76 T340 T139 | T76 T340 T77 | T6 T49 T198 | T48 T198 T128 | T333 T338 T339 | T333 T338 T339 | T7 T16 T251 | T5 T334 T146 | T159 T337 T128 | T337 T340 T347 | T340 T341 T342 | T126 T36 T333 | T333 T338 T339 | T126 T131 T36 | T131 T333 T132 | T32 T131 T78 | T32 T78 T79 | T32 T78 T79 | T31 T333 T80 | T333 T338 T339 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T13 T128 T239 | T17 T128 T55 | T73 T340 T74 | T340 T341 T342 | T73 T340 T74 | T340 T341 T342 | T75 T340 T138 | T340 T341 T342 | T35 T75 T340 | T76 T340 T139 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T6 T128 T340 | T49 T198 T343 | T48 T198 T128 | T128 T333 T193 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T7 T16 T82 | T251 T252 T198 | T5 T334 T146 | T335 T336 T340 | T128 T193 T194 | T337 T128 T340 | T340 T341 T342 | T337 T340 T347 | T340 T341 T342 | T126 T36 T333 | T126 T36 T333 | T333 T338 T339 | T333 T338 T339 | T126 T36 T333 | T131 T333 T132 | T131 T333 T132 | T333 T338 T339 | T333 T338 T339 | T32 T78 T79 | T32 T78 T79 | T333 T338 T339 | T333 T338 T339 | T32 T78 T79 | T31 T333 T80 | T31 T333 T80 | T333 T338 T339 | T333 T338 T339 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T33 T340 T46 | T13 T128 T239 | T128 T193 T194 | T128 T193 T194 | T128 T193 T194 | T73 T340 T74 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T75 T340 T138 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T35 T75 T340 | T340 T341 T342 | T340 T341 T342 | T76 T340 T139 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T128 T135 T193 | T128 T193 T194 | T49 T198 T343 | T48 T340 T344 | T128 T193 T194 | T128 T193 T194 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T333 T338 T339 | T7 T16 T199 | T140 T340 T141 | T251 T252 T198 | T128 T193 T194 | T5 T334 T146 | T334 T146 T340 | T340 T341 T342 | T340 T341 T342 | T128 T193 T194 | T128 T193 T194 | T128 T193 T194 | T337 T340 T347 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T5 T6 T7 | T6 T49 T31 | T5 T7 T48 | T31 T32 T126 | T6 T49 T17 | T5 T7 T48 | T31 T32 T126 | T31 T33 T268 | T17 T33 T13 | T6 T49 T35 | T7 T48 T49 | T5 T334 T146 | T126 T131 T36 | T31 T32 T131 | T31 T33 T268 | T33 T268 T128 | T17 T33 T13 | T75 T73 T268 | T35 T75 T76 | T6 T49 T76 | T48 T49 T50 | T7 T16 T251 | T5 T334 T146 | T337 T268 T128 | T126 T36 T268 | T126 T131 T36 | T32 T131 T78 | T31 T32 T78 | T31 T33 T268 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T13 T268 | T17 T13 T73 | T73 T268 T128 | T75 T268 T128 | T35 T75 T268 | T35 T76 T268 | T76 T268 T128 | T6 T49 T198 | T48 T49 T50 | T268 T128 T333 | T268 T128 T333 | T7 T48 T49 | T5 T334 T146 | T159 T337 T268 | T337 T268 T128 | T337 T268 T128 | T126 T36 T268 | T126 T36 T268 | T126 T131 T36 | T131 T268 T128 | T32 T131 T78 | T32 T78 T79 | T32 T78 T79 | T31 T268 T128 | T31 T268 T128 | T31 T33 T268 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T17 T33 T13 | T17 T13 T14 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T268 T128 T333 | T75 T268 T128 | T75 T268 T128 | T35 T75 T268 | T35 T76 T268 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T6 T268 T128 | T49 T198 T343 | T48 T49 T50 | T13 T14 T268 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T7 T16 T82 | T48 T49 T50 | T5 T334 T146 | T5 T334 T146 | T268 T128 T333 | T159 T337 T268 | T268 T128 T333 | T337 T268 T128 | T337 T268 T128 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T126 T36 T268 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T131 T268 T128 | T32 T131 T78 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T32 T78 T79 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T31 T268 T128 | T31 T33 T268 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T33 T268 T128 | T17 T33 T13 | T17 T268 T128 | T17 T13 T14 | T17 T268 T128 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T73 T268 T128 | T268 T128 T333 | T268 T128 T333 | T75 T268 T128 | T75 T268 T128 | T75 T268 T128 | T75 T268 T128 | T35 T75 T268 | T35 T268 T128 | T35 T268 T128 | T35 T76 T268 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T76 T268 T128 | T268 T128 T333 | T268 T128 T333 | T6 T268 T128 | T268 T128 T333 | T48 T49 T50 | T48 T49 T50 | T48 T49 T50 | T13 T14 T268 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T7 T16 T280 | T82 T140 T268 | T48 T49 T50 | T181 T268 T128 | T5 T334 T146 | T5 T334 T146 | T5 T334 T146 | T335 T336 T268 | T268 T128 T333 | T268 T128 T333 | T159 T268 T128 | T337 T268 T128 | T268 T128 T333 | T268 T128 T333 | T268 T128 T333 | T337 T268 T128 | T337 T268 T128
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T5 T6 T7
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T5 T6 T7
101 1/1 assign max_value_o = max_tree[0];
Tests: T5 T6 T7
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);