Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146120	1			T94	3		T95	7		T96	25
values[2]	5209	1			T278	1		T443	1		T451	2
values[3]	2833	1			T451	1		T450	1		T446	39
values[4]	2322	1			T450	1		T446	53		T543	4
values[5]	1756	1			T450	3		T446	39		T543	1
values[6]	1374	1			T450	4		T446	51		T543	2
values[7]	1158	1			T450	3		T446	41		T543	4
values[8]	991	1			T450	4		T446	30		T543	1
values[9]	918	1			T450	1		T446	44		T543	4
values[10]	687	1			T450	1		T446	20		T543	2
values[11]	552	1			T450	2		T446	14		T543	2
values[12]	543	1			T450	1		T446	14		T543	3
values[13]	505	1			T450	1		T446	6		T543	3
values[14]	413	1			T450	2		T446	4		T543	1
values[15]	396	1			T450	6		T446	2		T543	3
values[16]	333	1			T450	6		T543	2		T641	4
values[17]	275	1			T450	3		T543	2		T641	8
values[18]	326	1			T450	1		T543	3		T641	18
values[19]	318	1			T450	4		T543	3		T641	11
values[20]	264	1			T450	1		T543	2		T641	10
values[21]	244	1			T450	4		T543	4		T641	6
values[22]	186	1			T450	10		T543	1		T641	8
values[23]	164	1			T450	3		T543	1		T641	13
values[24]	144	1			T450	2		T543	3		T641	16
values[25]	143	1			T450	1		T543	2		T641	21
values[26]	151	1			T450	4		T543	3		T641	27
values[27]	142	1			T450	1		T543	1		T641	5
values[28]	171	1			T450	2		T543	1		T641	2
values[29]	171	1			T450	3		T543	2		T641	1
values[30]	161	1			T450	2		T543	2		T477	8
values[31]	158	1			T450	3		T543	1		T477	9
values[32]	124	1			T450	4		T543	3		T477	7
values[33]	137	1			T450	4		T543	3		T477	7
values[34]	114	1			T450	3		T543	3		T477	4
values[35]	129	1			T450	1		T543	3		T477	7
values[36]	122	1			T450	1		T543	3		T477	4
values[37]	135	1			T450	2		T543	1		T477	4
values[38]	112	1			T450	2		T543	4		T477	8
values[39]	112	1			T450	4		T543	3		T477	7
values[40]	105	1			T450	5		T543	3		T477	4
values[41]	120	1			T450	4		T543	4		T477	6
values[42]	137	1			T450	2		T543	2		T477	5
values[43]	117	1			T450	4		T543	2		T477	4
values[44]	113	1			T450	6		T543	2		T477	2
values[45]	90	1			T450	4		T543	1		T477	5
values[46]	91	1			T450	1		T543	2		T477	5
values[47]	98	1			T450	2		T543	2		T477	17
values[48]	66	1			T450	1		T543	1		T477	12
values[49]	52	1			T450	1		T543	2		T477	8
values[50]	69	1			T450	1		T543	2		T477	10
values[51]	105	1			T450	2		T543	6		T477	12
values[52]	77	1			T450	3		T543	3		T477	5
values[53]	56	1			T450	2		T543	1		T477	2
values[54]	70	1			T450	1		T543	2		T477	7
values[55]	62	1			T450	3		T543	1		T477	3
values[56]	78	1			T450	5		T543	5		T477	2
values[57]	63	1			T450	1		T543	3		T477	1
values[58]	57	1			T450	3		T543	2		T477	2
values[59]	71	1			T450	4		T543	1		T477	1
values[60]	71	1			T450	1		T543	3		T477	2
values[61]	72	1			T450	1		T543	5		T477	4
values[62]	82	1			T450	5		T543	2		T477	9
values[63]	68	1			T450	4		T543	1		T477	5
values[64]	57	1			T450	5		T543	5		T477	3
values[65]	79	1			T450	5		T543	1		T477	4
values[66]	77	1			T450	4		T543	2		T477	6
values[67]	74	1			T450	1		T543	1		T477	3
values[68]	87	1			T450	2		T543	6		T477	1
values[69]	81	1			T450	7		T543	3		T477	3
values[70]	66	1			T450	3		T543	1		T477	1
values[71]	74	1			T450	2		T543	5		T477	3
values[72]	77	1			T450	2		T543	9		T477	3
values[73]	75	1			T450	3		T543	11		T477	1
values[74]	63	1			T450	3		T543	3		T477	3
values[75]	66	1			T450	2		T543	5		T477	2
values[76]	68	1			T450	1		T543	6		T477	1
values[77]	70	1			T450	2		T543	6		T477	7
values[78]	84	1			T450	1		T543	1		T477	1
values[79]	75	1			T450	9		T543	2		T477	2
values[80]	97	1			T450	8		T543	5		T477	2
values[81]	87	1			T450	4		T543	3		T477	6
values[82]	82	1			T450	1		T543	1		T477	4
values[83]	68	1			T450	1		T543	1		T477	7
values[84]	86	1			T450	3		T543	2		T477	3
values[85]	84	1			T450	3		T543	3		T477	3
values[86]	80	1			T450	2		T543	2		T477	8
values[87]	93	1			T450	1		T543	2		T477	2
values[88]	112	1			T450	2		T543	1		T477	10
values[89]	102	1			T450	6		T543	6		T477	5
values[90]	88	1			T450	3		T543	2		T477	5
values[91]	95	1			T450	11		T543	2		T477	6
values[92]	94	1			T450	2		T543	1		T477	8
values[93]	91	1			T450	5		T543	2		T477	4
values[94]	85	1			T450	6		T543	3		T477	1
values[95]	88	1			T450	4		T543	3		T477	4
values[96]	87	1			T450	1		T543	1		T477	5
values[97]	104	1			T450	5		T543	1		T477	3
values[98]	89	1			T450	5		T543	7		T477	4
values[99]	107	1			T450	6		T543	14		T477	1
values[100]	93	1			T450	2		T543	4		T477	4
values[101]	97	1			T450	2		T543	2		T477	5
values[102]	93	1			T450	1		T543	6		T477	5
values[103]	110	1			T450	1		T543	8		T477	6
values[104]	89	1			T450	2		T543	13		T477	6
values[105]	81	1			T450	2		T543	5		T477	7
values[106]	96	1			T450	1		T543	11		T477	4
values[107]	103	1			T450	1		T543	6		T477	7
values[108]	93	1			T450	2		T543	2		T477	3
values[109]	95	1			T450	3		T543	1		T477	7
values[110]	113	1			T450	1		T543	5		T477	3
values[111]	97	1			T450	2		T543	3		T477	2
values[112]	82	1			T450	1		T543	1		T477	5
values[113]	106	1			T450	2		T543	3		T477	3
values[114]	107	1			T450	3		T543	4		T477	9
values[115]	107	1			T450	3		T543	2		T477	3
values[116]	100	1			T450	5		T543	4		T477	5
values[117]	105	1			T450	7		T543	3		T477	6
values[118]	111	1			T450	9		T543	9		T477	2
values[119]	118	1			T450	3		T543	6		T477	4
values[120]	123	1			T450	7		T543	4		T477	2
values[121]	112	1			T450	2		T543	3		T477	7
values[122]	116	1			T450	5		T543	3		T477	6
values[123]	139	1			T450	4		T543	6		T477	10
values[124]	245	1			T450	5		T543	18		T477	12
values[125]	505	1			T450	37		T543	29		T477	28
values[126]	860	1			T450	41		T543	52		T477	39
values[127]	2263	1			T450	20		T543	21		T477	17
values[128]	3880	1			T450	1		T808	241		T467	199