Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136867	1			T94	3		T95	10		T96	35
values[2]	11180	1			T443	1		T452	2		T544	1
values[3]	4436	1			T543	87		T521	1		T592	1
values[4]	2449	1			T543	37		T576	12		T477	54
values[5]	1492	1			T543	2		T576	1		T477	44
values[6]	1038	1			T477	57		T796	1		T797	3
values[7]	640	1			T477	51		T796	1		T797	9
values[8]	445	1			T477	41		T796	1		T797	4
values[9]	391	1			T477	38		T796	1		T797	4
values[10]	325	1			T477	22		T796	1		T797	3
values[11]	305	1			T477	10		T796	1		T797	6
values[12]	273	1			T477	4		T796	1		T797	5
values[13]	240	1			T477	6		T796	1		T797	5
values[14]	282	1			T796	1		T797	20		T638	8
values[15]	255	1			T796	1		T797	9		T638	5
values[16]	256	1			T796	1		T797	15		T638	9
values[17]	218	1			T796	1		T797	10		T638	6
values[18]	245	1			T796	1		T797	2		T638	7
values[19]	241	1			T796	1		T797	3		T638	14
values[20]	218	1			T796	1		T797	3		T638	19
values[21]	232	1			T796	1		T797	6		T638	6
values[22]	214	1			T796	1		T797	5		T638	5
values[23]	227	1			T796	1		T797	16		T638	18
values[24]	234	1			T796	1		T797	9		T638	10
values[25]	200	1			T796	1		T797	7		T638	3
values[26]	215	1			T796	1		T797	4		T638	4
values[27]	208	1			T796	1		T797	18		T638	7
values[28]	193	1			T796	1		T797	8		T638	4
values[29]	222	1			T796	1		T797	12		T638	6
values[30]	233	1			T796	1		T797	4		T638	11
values[31]	210	1			T796	1		T797	4		T638	13
values[32]	207	1			T796	1		T797	4		T638	5
values[33]	201	1			T796	1		T797	9		T638	11
values[34]	241	1			T796	1		T797	10		T638	5
values[35]	181	1			T796	1		T797	7		T638	4
values[36]	195	1			T796	1		T797	14		T638	6
values[37]	215	1			T796	1		T797	12		T638	6
values[38]	200	1			T796	1		T797	4		T638	8
values[39]	218	1			T796	1		T797	5		T638	17
values[40]	200	1			T796	1		T797	5		T638	6
values[41]	165	1			T796	1		T797	8		T638	2
values[42]	177	1			T796	1		T797	7		T638	9
values[43]	207	1			T796	1		T797	9		T638	5
values[44]	184	1			T796	1		T797	2		T638	8
values[45]	182	1			T796	1		T797	10		T638	5
values[46]	173	1			T796	1		T797	5		T638	13
values[47]	192	1			T796	1		T797	9		T638	7
values[48]	224	1			T796	1		T797	11		T638	19
values[49]	153	1			T796	1		T797	5		T638	5
values[50]	152	1			T796	1		T797	6		T638	7
values[51]	188	1			T796	1		T797	10		T638	5
values[52]	184	1			T796	1		T797	15		T638	5
values[53]	159	1			T796	1		T797	10		T638	16
values[54]	166	1			T796	1		T797	3		T638	10
values[55]	167	1			T796	1		T797	5		T638	26
values[56]	172	1			T796	1		T797	3		T638	13
values[57]	151	1			T796	1		T797	7		T638	7
values[58]	189	1			T796	1		T797	3		T638	12
values[59]	158	1			T796	1		T797	4		T638	5
values[60]	158	1			T796	1		T797	12		T638	3
values[61]	179	1			T796	1		T797	4		T638	5
values[62]	178	1			T796	1		T797	3		T638	3
values[63]	172	1			T796	1		T797	5		T638	4
values[64]	134	1			T796	1		T797	6		T513	5
values[65]	149	1			T796	1		T797	6		T513	5
values[66]	117	1			T796	1		T797	3		T513	7
values[67]	136	1			T796	1		T797	8		T513	5
values[68]	126	1			T796	1		T797	8		T513	7
values[69]	97	1			T796	1		T797	3		T513	3
values[70]	94	1			T796	1		T797	3		T513	14
values[71]	70	1			T796	1		T797	3		T513	4
values[72]	78	1			T796	1		T797	13		T794	1
values[73]	85	1			T796	1		T797	16		T794	1
values[74]	75	1			T796	1		T797	4		T794	1
values[75]	80	1			T796	1		T794	1		T534	1
values[76]	57	1			T796	1		T794	1		T534	1
values[77]	46	1			T796	1		T794	1		T534	1
values[78]	54	1			T796	1		T794	1		T534	1
values[79]	46	1			T796	1		T794	1		T534	1
values[80]	42	1			T796	1		T794	1		T534	1
values[81]	47	1			T796	1		T794	1		T534	2
values[82]	46	1			T796	2		T794	1		T534	1
values[83]	57	1			T796	1		T794	1		T534	1
values[84]	58	1			T796	1		T794	1		T534	1
values[85]	48	1			T796	1		T794	1		T534	1
values[86]	44	1			T796	1		T794	1		T534	1
values[87]	37	1			T796	1		T794	1		T534	1
values[88]	47	1			T796	1		T794	1		T534	1
values[89]	37	1			T796	1		T794	1		T534	1
values[90]	50	1			T796	1		T794	1		T534	1
values[91]	60	1			T796	1		T794	1		T534	1
values[92]	48	1			T796	1		T794	1		T534	2
values[93]	43	1			T796	2		T794	1		T534	1
values[94]	38	1			T796	1		T794	1		T534	1
values[95]	56	1			T796	6		T794	1		T534	1
values[96]	59	1			T796	4		T794	1		T534	1
values[97]	46	1			T796	2		T794	1		T534	1
values[98]	43	1			T796	2		T794	1		T534	1
values[99]	41	1			T796	1		T794	1		T534	1
values[100]	48	1			T796	3		T794	1		T534	1
values[101]	44	1			T796	2		T794	1		T534	1
values[102]	42	1			T796	2		T794	1		T534	1
values[103]	46	1			T796	3		T794	1		T534	1
values[104]	51	1			T796	2		T794	1		T534	1
values[105]	53	1			T796	1		T794	1		T534	1
values[106]	37	1			T796	5		T794	1		T534	1
values[107]	50	1			T796	5		T794	2		T534	1
values[108]	46	1			T796	5		T794	1		T534	1
values[109]	39	1			T796	1		T794	1		T534	1
values[110]	39	1			T796	4		T794	1		T534	1
values[111]	40	1			T796	3		T794	1		T534	2
values[112]	45	1			T796	1		T794	1		T534	6
values[113]	34	1			T796	1		T794	1		T534	3
values[114]	38	1			T796	4		T794	1		T534	1
values[115]	36	1			T796	2		T794	1		T534	3
values[116]	27	1			T796	1		T794	1		T534	3
values[117]	35	1			T796	3		T794	3		T534	3
values[118]	38	1			T796	4		T794	1		T534	2
values[119]	35	1			T796	1		T794	1		T534	1
values[120]	37	1			T796	2		T794	1		T534	1
values[121]	46	1			T796	1		T794	3		T534	8
values[122]	42	1			T796	2		T794	5		T534	1
values[123]	55	1			T796	2		T794	1		T534	1
values[124]	34	1			T796	1		T794	1		T534	1
values[125]	50	1			T796	1		T794	1		T534	3
values[126]	71	1			T796	2		T794	1		T534	2
values[127]	422	1			T796	36		T794	35		T534	38
values[128]	3384	1			T796	259		T794	248		T534	342