Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136925	1			T94	4		T95	10		T96	30
values[2]	10731	1			T443	1		T548	1		T450	81
values[3]	4382	1			T450	79		T446	30		T543	1
values[4]	2582	1			T450	68		T446	28		T543	3
values[5]	1657	1			T450	18		T446	17		T543	2
values[6]	1019	1			T450	3		T446	23		T543	3
values[7]	785	1			T450	1		T446	18		T543	4
values[8]	549	1			T446	22		T543	3		T782	17
values[9]	490	1			T446	9		T543	5		T641	1
values[10]	444	1			T446	5		T543	15		T783	4
values[11]	363	1			T446	4		T543	6		T455	9
values[12]	311	1			T446	6		T543	3		T455	2
values[13]	293	1			T446	1		T543	1		T455	4
values[14]	221	1			T543	2		T455	2		T499	3
values[15]	204	1			T543	1		T455	2		T499	1
values[16]	260	1			T543	2		T455	1		T499	4
values[17]	234	1			T543	3		T455	2		T499	2
values[18]	187	1			T543	1		T455	2		T499	1
values[19]	220	1			T543	2		T455	3		T499	2
values[20]	248	1			T543	1		T455	2		T499	1
values[21]	219	1			T543	1		T455	1		T499	3
values[22]	255	1			T543	2		T455	4		T499	1
values[23]	237	1			T543	4		T455	1		T499	5
values[24]	222	1			T543	9		T455	3		T499	4
values[25]	233	1			T543	5		T455	1		T499	1
values[26]	199	1			T543	5		T455	2		T499	2
values[27]	240	1			T543	7		T455	6		T499	2
values[28]	220	1			T543	4		T455	6		T499	1
values[29]	197	1			T543	3		T455	2		T456	7
values[30]	237	1			T543	2		T455	3		T456	3
values[31]	208	1			T543	2		T455	12		T456	3
values[32]	180	1			T543	1		T455	5		T456	7
values[33]	185	1			T543	1		T455	13		T456	10
values[34]	203	1			T543	5		T455	3		T456	8
values[35]	236	1			T543	2		T455	2		T456	5
values[36]	217	1			T543	1		T455	3		T456	10
values[37]	164	1			T543	4		T455	1		T456	4
values[38]	193	1			T543	2		T455	4		T456	6
values[39]	189	1			T543	2		T455	7		T456	3
values[40]	227	1			T543	4		T455	11		T456	4
values[41]	210	1			T543	9		T455	1		T456	5
values[42]	171	1			T543	3		T455	3		T456	12
values[43]	202	1			T543	7		T455	1		T456	15
values[44]	174	1			T543	5		T455	1		T456	21
values[45]	189	1			T543	2		T455	2		T456	3
values[46]	196	1			T543	5		T455	3		T456	6
values[47]	153	1			T543	5		T455	7		T456	4
values[48]	180	1			T543	6		T455	6		T456	4
values[49]	132	1			T543	4		T455	2		T456	4
values[50]	155	1			T543	1		T455	2		T456	11
values[51]	178	1			T543	3		T455	3		T456	4
values[52]	152	1			T543	2		T455	5		T456	6
values[53]	155	1			T543	1		T455	3		T456	7
values[54]	178	1			T543	3		T455	1		T456	15
values[55]	128	1			T543	4		T455	3		T456	7
values[56]	165	1			T543	3		T455	8		T456	13
values[57]	148	1			T543	3		T455	3		T456	10
values[58]	158	1			T543	2		T455	7		T456	10
values[59]	164	1			T543	1		T455	1		T796	2
values[60]	132	1			T543	4		T455	2		T796	2
values[61]	131	1			T543	1		T455	1		T796	3
values[62]	123	1			T543	4		T455	2		T796	2
values[63]	147	1			T543	5		T455	1		T796	2
values[64]	142	1			T543	7		T455	1		T796	2
values[65]	123	1			T543	2		T455	4		T796	2
values[66]	100	1			T543	4		T455	5		T796	2
values[67]	115	1			T543	2		T455	13		T796	2
values[68]	105	1			T543	11		T455	7		T796	2
values[69]	98	1			T543	9		T455	8		T796	2
values[70]	108	1			T543	20		T455	13		T796	2
values[71]	140	1			T543	25		T455	13		T796	2
values[72]	105	1			T543	9		T455	6		T796	2
values[73]	146	1			T543	18		T455	11		T796	2
values[74]	138	1			T543	21		T455	8		T796	2
values[75]	120	1			T543	13		T455	2		T796	2
values[76]	89	1			T543	9		T455	7		T796	2
values[77]	75	1			T543	16		T455	3		T796	2
values[78]	93	1			T543	19		T796	2		T846	2
values[79]	55	1			T543	7		T796	2		T846	3
values[80]	57	1			T543	11		T796	2		T846	12
values[81]	66	1			T543	12		T796	2		T846	4
values[82]	47	1			T543	5		T796	2		T846	7
values[83]	51	1			T543	8		T796	2		T846	10
values[84]	50	1			T543	3		T796	2		T846	5
values[85]	51	1			T543	6		T796	3		T846	6
values[86]	63	1			T543	3		T796	9		T846	8
values[87]	46	1			T543	4		T796	3		T846	11
values[88]	41	1			T543	1		T796	2		T846	12
values[89]	68	1			T796	4		T846	14		T529	1
values[90]	44	1			T796	6		T846	7		T529	1
values[91]	40	1			T796	3		T846	4		T529	1
values[92]	41	1			T796	5		T846	9		T529	1
values[93]	48	1			T796	3		T846	5		T529	1
values[94]	54	1			T796	3		T846	3		T529	1
values[95]	48	1			T796	5		T846	2		T529	1
values[96]	45	1			T796	3		T846	3		T529	1
values[97]	59	1			T796	3		T846	10		T529	1
values[98]	57	1			T796	2		T846	9		T529	1
values[99]	48	1			T796	2		T846	5		T529	1
values[100]	43	1			T796	2		T846	6		T529	1
values[101]	48	1			T796	4		T846	2		T529	1
values[102]	42	1			T796	5		T846	2		T529	1
values[103]	41	1			T796	2		T846	3		T529	1
values[104]	40	1			T796	2		T529	1		T847	2
values[105]	43	1			T796	2		T529	1		T847	3
values[106]	28	1			T796	3		T529	2		T847	2
values[107]	34	1			T796	7		T529	1		T847	2
values[108]	40	1			T796	4		T529	1		T847	2
values[109]	45	1			T796	5		T529	1		T847	2
values[110]	48	1			T796	4		T529	1		T847	3
values[111]	50	1			T796	6		T529	1		T847	1
values[112]	31	1			T796	3		T529	1		T847	1
values[113]	37	1			T796	2		T529	1		T847	4
values[114]	44	1			T796	5		T529	1		T847	2
values[115]	55	1			T796	5		T529	1		T847	3
values[116]	40	1			T796	2		T529	1		T847	1
values[117]	45	1			T796	4		T529	1		T847	1
values[118]	31	1			T796	2		T529	1		T847	1
values[119]	30	1			T796	2		T529	1		T847	2
values[120]	43	1			T796	2		T529	1		T847	4
values[121]	39	1			T796	2		T529	1		T847	3
values[122]	31	1			T796	2		T529	1		T847	4
values[123]	44	1			T796	5		T529	1		T847	2
values[124]	36	1			T796	4		T529	7		T847	1
values[125]	56	1			T796	4		T529	3		T847	1
values[126]	108	1			T796	10		T529	1		T847	2
values[127]	454	1			T796	49		T529	31		T847	15
values[128]	3537	1			T796	606		T529	386		T847	226