CHIP Simulation Results

Saturday September 26 2020 02:00:05AM UTC

Revision: 93a30dcd on master

Testplan

Simulator: VCS

Milestone Name Tests Passing Total Pass Rate
V1 sanity chip_sanity 0 0 --
V1 csr_hw_reset chip_csr_hw_reset 11 20 55.00
V1 csr_rw chip_csr_rw 11 20 55.00
V1 csr_bit_bash chip_csr_bit_bash 20 20 100.00
V1 csr_aliasing chip_csr_aliasing 9 20 45.00
V1 csr_mem_rw_with_rand_reset chip_csr_mem_rw_with_rand_reset 10 20 50.00
V1 shadow_reg_errors chip_shadow_reg_errors 0 20 0.00
V1 mem_walk chip_mem_walk 20 20 100.00
V1 mem_partial_access chip_mem_partial_access 20 20 100.00
V1 xbar_sanity xbar_chip_sanity 50 50 100.00
V1 TOTAL 151 210 71.90
V2 tl_d_oob_addr_access chip_tl_errors 20 20 100.00
V2 tl_d_illegal_access chip_tl_errors 20 20 100.00
V2 tl_d_outstanding_access chip_csr_hw_reset 11 20 55.00
chip_csr_rw 11 20 55.00
chip_csr_aliasing 9 20 45.00
chip_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access chip_csr_hw_reset 11 20 55.00
chip_csr_rw 11 20 55.00
chip_csr_aliasing 9 20 45.00
chip_same_csr_outstanding 20 20 100.00
V2 xbar_base_random_sequence xbar_chip_random 50 50 100.00
V2 xbar_random_delay xbar_chip_sanity_zero_delays 50 50 100.00
xbar_chip_sanity_large_delays 50 50 100.00
xbar_chip_sanity_slow_rsp 50 50 100.00
xbar_chip_random_zero_delays 50 50 100.00
xbar_chip_random_large_delays 50 50 100.00
xbar_chip_random_slow_rsp 50 50 100.00
V2 xbar_unmapped_address xbar_chip_unmapped_addr 50 50 100.00
xbar_chip_error_and_unmapped_addr 50 50 100.00
V2 xbar_error_cases xbar_chip_error_random 50 50 100.00
xbar_chip_error_and_unmapped_addr 50 50 100.00
V2 xbar_all_access_same_device xbar_chip_access_same_device 50 50 100.00
xbar_chip_access_same_device_slow_rsp 50 50 100.00
V2 xbar_all_hosts_use_same_source_id xbar_chip_same_source 50 50 100.00
V2 xbar_stress_all xbar_chip_stress_all 50 50 100.00
xbar_chip_stress_all_with_error 50 50 100.00
V2 xbar_stress_with_reset xbar_chip_stress_all_with_rand_reset 50 50 100.00
xbar_chip_stress_all_with_reset_error 50 50 100.00
V2 TOTAL 1042 1100 94.73
Unmapped tests chip_uart_tx_rx 1 1 100.00
chip_aes_encr 1 1 100.00
chip_gpio 1 1 100.00
chip_dif_plic_sanitytest 1 1 100.00
chip_flash_ctrl_access 1 1 100.00
chip_hmac_sha256_encr 1 1 100.00
chip_rv_timer_irq 0 1 0.00
chip_coremark 1 1 100.00
chip_opentitan_tock 0 1 0.00
TOTAL 1200 1319 90.98

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
85.07 97.72 94.92 63.17 54.22 95.04 92.65 97.73

List of Failures

TEST: chip_rv_timer_irq, SEED: 504652097
LOG: $scratch_path/0.chip_rv_timer_irq/out/run.log

UVM_ERROR @ 12000352198 ps: (chip_sw_base_vseq.sv:79) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

UVM_INFO @ 12000352198 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

TEST: chip_opentitan_tock, SEED: 468475299
LOG: $scratch_path/0.chip_opentitan_tock/out/run.log

UVM_ERROR @ 463959888 ps: (uart_monitor.sv:179) uvm_test_top.env.m_uart_agent.monitor [uvm_test_top.env.m_uart_agent.monitor] Expect uart_tx stable from 25 to 75 of the period, but it's changed
UVM_INFO @ 463959888 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 4289148051
LOG: $scratch_path/0.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1082330000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1082330000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 1495906397
LOG: $scratch_path/0.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1042890000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1042890000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_rw, SEED: 730886080
LOG: $scratch_path/1.chip_csr_rw/out/run.log

UVM_ERROR @ 1033989103 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033989103 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 1304322276
LOG: $scratch_path/1.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1033985514 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033985514 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 1831048017
LOG: $scratch_path/1.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1711160000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1711160000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_hw_reset, SEED: 3028880158
LOG: $scratch_path/2.chip_csr_hw_reset/out/run.log

UVM_FATAL @ 1033982630 ps: (dv_utils_pkg.sv:106) [csr_utils::csr_wr] Timeout waiting to csr_wr ral.aes.ctrl_shadowed (addr=0x40110070)
UVM_INFO @ 1033982630 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count :     0 of     1

TEST: chip_csr_rw, SEED: 950362539
LOG: $scratch_path/2.chip_csr_rw/out/run.log

UVM_ERROR @ 1033980182 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033980182 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_aliasing, SEED: 842425364
LOG: $scratch_path/2.chip_csr_aliasing/out/run.log

UVM_ERROR @ 7936160000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 7936160000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 3816254665
LOG: $scratch_path/2.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1033987232 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033987232 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 2918817670
LOG: $scratch_path/2.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1089020000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1089020000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_hw_reset, SEED: 1337605352
LOG: $scratch_path/3.chip_csr_hw_reset/out/run.log

UVM_FATAL @ 1033986369 ps: (dv_utils_pkg.sv:106) [csr_utils::csr_wr] Timeout waiting to csr_wr ral.spi_device.intr_test (addr=0x40020008)
UVM_INFO @ 1033986369 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count :     0 of     1

TEST: chip_csr_aliasing, SEED: 3759158223
LOG: $scratch_path/3.chip_csr_aliasing/out/run.log

UVM_ERROR @ 4720520000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 4720520000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 83888984
LOG: $scratch_path/3.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 3471770000 ps: (csr_utils_pkg.sv:472) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: ral.alert_handler.loc_alert_cause 
UVM_INFO @ 3471770000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_rw, SEED: 1363535131
LOG: $scratch_path/4.chip_csr_rw/out/run.log

UVM_ERROR @ 1033991140 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033991140 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_aliasing, SEED: 3907110243
LOG: $scratch_path/4.chip_csr_aliasing/out/run.log

UVM_ERROR @ 15426780000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 15426780000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 2070414066
LOG: $scratch_path/4.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1033996685 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033996685 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 2996384
LOG: $scratch_path/4.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1084250000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1084250000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 2329134061
LOG: $scratch_path/5.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1033987929 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033987929 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 3065327816
LOG: $scratch_path/5.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 2556440000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 2556440000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_rw, SEED: 1551878341
LOG: $scratch_path/6.chip_csr_rw/out/run.log

UVM_ERROR @ 1033996843 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033996843 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_aliasing, SEED: 2729217389
LOG: $scratch_path/6.chip_csr_aliasing/out/run.log

UVM_ERROR @ 7528720000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 7528720000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 1568585791
LOG: $scratch_path/6.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1033990642 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033990642 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 164432453
LOG: $scratch_path/6.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 3404190000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 3404190000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_hw_reset, SEED: 2927868284
LOG: $scratch_path/7.chip_csr_hw_reset/out/run.log

UVM_FATAL @ 1206960000 ps: (dv_utils_pkg.sv:106) [csr_utils::csr_wr] Timeout waiting to csr_wr ral.aes.ctrl_shadowed (addr=0x40110070)
UVM_INFO @ 1206960000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count :     0 of     1

TEST: chip_csr_rw, SEED: 4083938397
LOG: $scratch_path/7.chip_csr_rw/out/run.log

UVM_ERROR @ 1033982970 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033982970 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 1049159443
LOG: $scratch_path/7.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1822610000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1822610000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_aliasing, SEED: 2549087675
LOG: $scratch_path/8.chip_csr_aliasing/out/run.log

UVM_ERROR @ 6407170000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 6407170000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 3998037226
LOG: $scratch_path/8.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 2345660000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 2345660000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_hw_reset, SEED: 2764699573
LOG: $scratch_path/9.chip_csr_hw_reset/out/run.log

UVM_FATAL @ 1033980618 ps: (dv_utils_pkg.sv:106) [csr_utils::csr_wr] Timeout waiting to csr_wr ral.aes.ctrl_shadowed (addr=0x40110070)
UVM_INFO @ 1033980618 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count :     0 of     1

TEST: chip_csr_aliasing, SEED: 248356117
LOG: $scratch_path/9.chip_csr_aliasing/out/run.log

UVM_ERROR @ 9270390000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 9270390000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 812209272
LOG: $scratch_path/9.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1744530000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1744530000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_rw, SEED: 875981697
LOG: $scratch_path/10.chip_csr_rw/out/run.log

UVM_ERROR @ 1033997710 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033997710 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_aliasing, SEED: 4187012088
LOG: $scratch_path/10.chip_csr_aliasing/out/run.log

UVM_ERROR @ 1785010000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1785010000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 1503041267
LOG: $scratch_path/10.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1100160000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1100160000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_aliasing, SEED: 1109715901
LOG: $scratch_path/11.chip_csr_aliasing/out/run.log

UVM_ERROR @ 1622240000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1622240000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 1592934413
LOG: $scratch_path/11.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1039720000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1039720000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 2875369291
LOG: $scratch_path/11.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1642323834 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1642323834 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_hw_reset, SEED: 3307350685
LOG: $scratch_path/12.chip_csr_hw_reset/out/run.log

UVM_FATAL @ 1205750000 ps: (dv_utils_pkg.sv:106) [csr_utils::csr_wr] Timeout waiting to csr_wr ral.spi_device.rxf_addr (addr=0x40020028)
UVM_INFO @ 1205750000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count :     0 of     1

TEST: chip_shadow_reg_errors, SEED: 3328478729
LOG: $scratch_path/12.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1074970000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1074970000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_hw_reset, SEED: 2771613242
LOG: $scratch_path/13.chip_csr_hw_reset/out/run.log

UVM_FATAL @ 1033996956 ps: (dv_utils_pkg.sv:106) [csr_utils::csr_wr] Timeout waiting to csr_wr ral.aes.ctrl_shadowed (addr=0x40110070)
UVM_INFO @ 1033996956 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count :     0 of     1

TEST: chip_shadow_reg_errors, SEED: 103916193
LOG: $scratch_path/13.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1170750000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1170750000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_rw, SEED: 2997815145
LOG: $scratch_path/14.chip_csr_rw/out/run.log

UVM_ERROR @ 1033998479 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033998479 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_aliasing, SEED: 2117778478
LOG: $scratch_path/14.chip_csr_aliasing/out/run.log

UVM_ERROR @ 6062160000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 6062160000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 83715392
LOG: $scratch_path/14.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1115220000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1115220000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_rw, SEED: 2594632986
LOG: $scratch_path/15.chip_csr_rw/out/run.log

UVM_ERROR @ 1033992105 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033992105 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_aliasing, SEED: 3447468886
LOG: $scratch_path/15.chip_csr_aliasing/out/run.log

UVM_ERROR @ 22153380000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 22153380000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 1053499575
LOG: $scratch_path/15.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1033990820 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033990820 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 1033117800
LOG: $scratch_path/15.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 1615810000 ps: (csr_utils_pkg.sv:472) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: ral.alert_handler.loc_alert_cause 
UVM_INFO @ 1615810000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 2180262691
LOG: $scratch_path/16.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 910096832 ps: (csr_utils_pkg.sv:472) [csr_utils::csr_rd_check] Check failed obs == exp (2 [0x2] vs 3 [0x3]) Regname: ral.sensor_ctrl.status.io_pok 
UVM_INFO @ 910096832 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_hw_reset, SEED: 3659700973
LOG: $scratch_path/17.chip_csr_hw_reset/out/run.log

UVM_FATAL @ 1033993931 ps: (dv_utils_pkg.sv:106) [csr_utils::csr_wr] Timeout waiting to csr_wr ral.spi_device.status (addr=0x4002001c)
UVM_INFO @ 1033993931 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count :     0 of     1

TEST: chip_csr_rw, SEED: 2204043692
LOG: $scratch_path/17.chip_csr_rw/out/run.log

UVM_ERROR @ 1033980760 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033980760 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 3426514739
LOG: $scratch_path/17.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 2596770000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 2596770000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_hw_reset, SEED: 2773103627
LOG: $scratch_path/18.chip_csr_hw_reset/out/run.log

UVM_FATAL @ 1033989285 ps: (dv_utils_pkg.sv:106) [csr_utils::csr_wr] Timeout waiting to csr_wr ral.aes.ctrl_shadowed (addr=0x40110070)
UVM_INFO @ 1033989285 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count :     0 of     1

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 204002786
LOG: $scratch_path/18.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1056130000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1056130000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 3578756194
LOG: $scratch_path/18.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 2573520000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 2573520000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_hw_reset, SEED: 1838426122
LOG: $scratch_path/19.chip_csr_hw_reset/out/run.log

UVM_FATAL @ 1033987885 ps: (dv_utils_pkg.sv:106) [csr_utils::csr_wr] Timeout waiting to csr_wr ral.aes.ctrl_shadowed (addr=0x40110070)
UVM_INFO @ 1033987885 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count :     0 of     1

TEST: chip_csr_aliasing, SEED: 2015472618
LOG: $scratch_path/19.chip_csr_aliasing/out/run.log

UVM_ERROR @ 2183070000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 2183070000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 3914466588
LOG: $scratch_path/19.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1033999594 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 1033999594 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_shadow_reg_errors, SEED: 365207735
LOG: $scratch_path/19.chip_shadow_reg_errors/out/run.log

UVM_ERROR @ 2277550000 ps: (prim_assert.sv:18) [ASSERT FAILED] [tb.dut.top_earlgrey.u_xbar_main.tlul_assert_host_cored.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A] noOutstandingReqsAtEndOfSim_A (../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:263)
UVM_INFO @ 2277550000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

Past Results