CHIP Simulation Results

Friday January 15 2021 03:00:49AM UTC

Revision: 123f4e1b7

Branch: master

Testplan

Simulator: VCS

Milestone Name Tests Passing Total Pass Rate
V1 chip_uart_tx_rx chip_uart_tx_rx 1 1 100.00
V1 chip_uart_rx_overflow chip_uart_tx_rx 1 1 100.00
V1 chip_gpio_out chip_gpio_out 0 0 --
V1 chip_gpio_in chip_gpio_in 0 0 --
V1 csr_hw_reset chip_tl_csr_hw_reset 0 0 --
chip_jtag_csr_hw_reset 0 0 --
V1 csr_rw chip_tl_csr_rw 0 0 --
chip_jtag_csr_rw 0 0 --
V1 csr_bit_bash chip_tl_csr_bit_bash 0 0 --
chip_jtag_csr_bit_bash 0 0 --
V1 csr_aliasing chip_tl_csr_aliasing 0 0 --
chip_jtag_csr_aliasing 0 0 --
V1 csr_mem_rw_with_rand_reset chip_tl_csr_mem_rw_with_rand_reset 0 0 --
chip_jtag_csr_mem_rw_with_rand_reset 0 0 --
V1 shadow_reg_errors chip_shadow_reg_errors 1 1 100.00
V1 mem_walk chip_tl_mem_walk 0 0 --
chip_jtag_mem_walk 0 0 --
V1 mem_partial_access chip_tl_mem_partial_access 0 0 --
chip_jtag_mem_partial_access 0 0 --
V1 xbar_smoke xbar_chip_smoke 100 100 100.00
V1 TOTAL 103 103 100.00
V2 chip_spi_device_tx_rx chip_spi_device_tx_rx 0 0 --
V2 chip_spi_device_eeprom chip_spi_device_eeprom 0 0 --
V2 chip_spi_host_tx_rx chip_spi_host_tx_rx 0 0 --
V2 chip_spi_pass_through chip_spi_pass_through 0 0 --
V2 chip_i2c_host_tx_rx chip_i2c_host_tx_rx 0 0 --
V2 chip_i2c_device_tx_rx chip_i2c_device_tx_rx 0 0 --
V2 chip_usb_fs_se_tx_rx chip_usb_fs_se_tx_rx 0 0 --
V2 chip_usb_fs_df_tx_rx chip_usb_fs_df_tx_rx 0 0 --
V2 chip_usb_vbus chip_usb_vbus 0 0 --
V2 chip_usb_suspend chip_usb_suspend 0 0 --
V2 chip_sleep_usb_suspend chip_sleep_usb_suspend 0 0 --
V2 chip_pin_mux chip_pin_mux 0 0 --
V2 chip_sleep_pin_mio_dio_val chip_sleep_pin_mio_dio_val 0 0 --
V2 chip_sleep_pin_wake chip_sleep_pin_wake 0 0 --
V2 chip_padctrl_attributes chip_padctrl_attributes 0 0 --
V2 chip_rv_dm_cpu_debug_mem chip_rv_dm_cpu_debug_mem 0 0 --
V2 chip_rv_dm_jtag_debug_mem chip_rv_dm_jtag_debug_mem 0 0 --
V2 chip_rv_dm_cpu_debug_req chip_rv_dm_cpu_debug_req 0 0 --
V2 chip_rv_dm_ndm_reset_req chip_rv_dm_ndm_reset_req 0 0 --
V2 chip_sleep_rv_dm_ndm_reset_req chip_sleep_rv_dm_ndm_reset_req 0 0 --
V2 chip_rv_dm_jtag_tap_sel chip_rv_dm_jtag_tap_sel 0 0 --
V2 chip_rv_dm_lc_disabled chip_rv_dm_lc_disabled 0 0 --
V2 chip_pattgen_ios chip_pattgen_ios 0 0 --
V2 chip_sleep_pwm_ios_val chip_sleep_pwm_ios_val 0 0 --
V2 chip_timer chip_timer 0 0 --
V2 chip_sleep_aon_timer_wake chip_sleep_aon_timer_wake 0 0 --
V2 chip_wdog_bark chip_wdog_bark 0 0 --
V2 chip_wdog_bite chip_wdog_bite 0 0 --
V2 chip_sleep_wdog_bark_wake chip_sleep_wdog_bark_wake 0 0 --
V2 chip_sleep_wdog_bite_wake chip_sleep_wdog_bite_wake 0 0 --
V2 chip_plic_all_irqs 0 0 --
V2 chip_plic_sw_irq 0 0 --
V2 chip_plic_nmi_irq 0 0 --
V2 chip_sw_clk_off_trans chip_sw_clk_off_trans 0 0 --
V2 chip_sw_clk_off_peri chip_sw_clk_off_peri 0 0 --
V2 chip_clk_div chip_clk_div 0 0 --
V2 chip_pwrmgr_cold_boot chip_pwrmgr_cold_boot 0 0 --
V2 chip_pwrmgr_sleep_all_wake_ups chip_pwrmgr_sleep_all_wake_ups 0 0 --
V2 chip_pwrmgr_sleep_all_reset_reqs chip_pwrmgr_sleep_all_reset_reqs 0 0 --
V2 chip_pwrmgr_deep_sleep_all_wake_ups chip_pwrmgr_deep_sleep_all_wake_ups 0 0 --
V2 chip_pwrmgr_deep_sleep_all_reset_reqs chip_pwrmgr_deep_sleep_all_reset_reqs 0 0 --
V2 chip_pwrmgr_all_reset_reqs chip_pwrmgr_all_reset_reqs 0 0 --
V2 chip_pwrmgr_bad_main_pok chip_pwrmgr_bad_main_pok 0 0 --
V2 chip_pwrmgr_b2b_sleep_reset_req chip_pwrmgr_b2b_sleep_reset_req 0 0 --
V2 chip_pwrmgr_debug_sleep chip_pwrmgr_debug_sleep 0 0 --
V2 chip_pwrmgr_sleep_wake_req_disabled chip_pwrmgr_sleep_wake_req_disabled 0 0 --
V2 chip_pwrmgr_reset_req_disabled chip_pwrmgr_reset_req_disabled 0 0 --
V2 chip_pwrmgr_sleep_reset_req_disabled chip_pwrmgr_sleep_reset_req_disabled 0 0 --
V2 chip_pwrmgr_sleep_disabled chip_pwrmgr_sleep_disabled 0 0 --
V2 chip_pwrmgr_sleep_wake_up_fall_through chip_pwrmgr_sleep_wake_up_fall_through 0 0 --
V2 chip_pwrmgr_sleep_abort chip_pwrmgr_sleep_abort 0 0 --
V2 chip_alert_handler_alerts chip_alert_handler_alerts 0 0 --
V2 chip_alert_handler_irqs chip_alert_handler_irqs 0 0 --
V2 chip_alert_handler_esc_irqs chip_alert_handler_esc_irqs 0 0 --
V2 chip_alert_handler_entropy chip_alert_handler_entropy 0 0 --
V2 chip_alert_handler_crashdump chip_alert_handler_crashdump 0 0 --
V2 chip_alert_handler_ping_fail chip_alert_handler_ping_fail 0 0 --
V2 chip_aes_enc chip_aes_enc 0 0 --
V2 chip_aes_shadow_reg_alert chip_aes_shadow_reg_alert 0 0 --
V2 chip_aes_idle chip_aes_idle 0 0 --
V2 chip_hmac_enc chip_hmac_enc 0 0 --
V2 chip_hmac_alert chip_hmac_alert 0 0 --
V2 chip_hmac_idle chip_hmac_idle 0 0 --
V2 chip_kmac_enc chip_kmac_enc 0 0 --
V2 chip_kmac_sram_uncorrectable_alert chip_kmac_sram_uncorrectable_alert 0 0 --
V2 chip_kmac_sram_data_parity_alert chip_kmac_sram_data_parity_alert 0 0 --
V2 chip_kmac_keymgr_key_data chip_kmac_keymgr_key_data 0 0 --
V2 chip_kmac_idle chip_kmac_idle 0 0 --
V2 chip_csrng_cmd chip_csrng_cmd 0 0 --
V2 chip_csrng_entropy_src chip_csrng_entropy_src 0 0 --
V2 chip_csrng_fuse chip_csrng_fuse 0 0 --
V2 chip_entropy_src_ast_rng_req chip_entropy_src_ast_rng_req 0 0 --
V2 chip_entropy_src_fuse chip_entropy_src_fuse 0 0 --
V2 chip_otbn_op chip_otbn_op 0 0 --
V2 chip_otbn_imem_uncorrectable_alert chip_otbn_imem_uncorrectable_alert 0 0 --
V2 chip_otbn_dmem_uncorrectable_alert chip_otbn_dmem_uncorrectable_alert 0 0 --
V2 chip_otbn_reg_uncorrectable_alert chip_otbn_reg_uncorrectable_alert 0 0 --
V2 chip_otbn_mem_encr chip_otbn_mem_encr 0 0 --
V2 chip_otbn_idle chip_otbn_idle 0 0 --
V2 chip_rom_access chip_rom_access 0 0 --
V2 chip_rom_security_features chip_rom_security_features 0 0 --
V2 chip_sram_access chip_sram_access 0 0 --
V2 chip_sram_scramble chip_sram_scramble 0 0 --
V2 chip_sram_ret_access chip_sram_ret_access 0 0 --
V2 chip_sram_ret_scramble chip_sram_ret_scramble 0 0 --
V2 chip_sleep_sram_ret_contents chip_sleep_sram_ret_contents 0 0 --
V2 chip_otp_init chip_otp_init 0 0 --
V2 chip_otp_keys chip_otp_keys 0 0 --
V2 chip_otp_lc_program chip_otp_lc_program 0 0 --
V2 chip_flash_host_access chip_flash_host_access 0 0 --
V2 chip_flash_ctrl_ops chip_flash_ctrl_ops 0 0 --
V2 chip_flash_ctrl_scramble chip_flash_ctrl_scramble 0 0 --
V2 chip_flash_scramble chip_flash_scramble 0 0 --
V2 chip_flash_ast_pwr_dwn chip_flash_ast_pwr_dwn 0 0 --
V2 chip_flash_test_mode chip_flash_test_mode 0 0 --
V2 chip_rbox_key_pass_through chip_rbox_key_pass_through 0 0 --
V2 chip_rbox_pwrb_pass_through chip_rbox_pwrb_pass_through 0 0 --
V2 chip_rbox_ac_present_in chip_rbox_ac_present_in 0 0 --
V2 chip_rbox_batt_en_out chip_rbox_batt_en_out 0 0 --
V2 chip_rbox_ec_entering_rw_in chip_rbox_ec_entering_rw_in 0 0 --
V2 chip_rbox_ec_in_rw_out chip_rbox_ec_in_rw_out 0 0 --
V2 chip_rbox_ec_reset_l_out chip_rbox_ec_reset_l_out 0 0 --
V2 chip_sleep_rbox_ios_val chip_sleep_rbox_ios_val 0 0 --
V2 chip_sleep_dcd_ast_adc_pd chip_sleep_dcd_ast_adc_pd 0 0 --
V2 chip_sleep_dcd_debug_cable_wake chip_sleep_dcd_debug_cable_wake 0 0 --
V2 chip_dcd_ast_adc chip_dcd_ast_adc 0 0 --
V2 chip_dcd_por_l chip_dcd_por_l 0 0 --
V2 chip_ast_clk_outputs chip_ast_clk_outputs 0 0 --
V2 chip_ast_clk_rst_inputs chip_ast_clk_rst_inputs 0 0 --
V2 chip_ast_sys_clk_jitter chip_ast_sys_clk_jitter 0 0 --
V2 chip_ast_usb_clk_calib chip_ast_usb_clk_calib 0 0 --
V2 chip_ast_alerts chip_ast_alerts 0 0 --
V2 chip_sensor_ctrl_ast_alerts chip_sensor_ctrl_ast_alerts 0 0 --
V2 chip_sensor_ctrl_ast_status chip_sensor_ctrl_ast_status 0 0 --
V2 chip_sw_boot chip_sw_boot 0 0 --
V2 chip_secure_boot chip_secure_boot 0 0 --
V2 chip_prod_os chip_opentitan_tock 0 1 0.00
V2 chip_lc_walkthrough chip_lc_walkthrough 0 0 --
V2 chip_device_ownership chip_device_ownership 0 0 --
V2 enable_reg chip_tl_csr_rw 0 0 --
chip_jtag_csr_rw 0 0 --
chip_tl_csr_bit_bash 0 0 --
chip_jtag_csr_bit_bash 0 0 --
chip_tl_csr_aliasing 0 0 --
chip_jtag_csr_aliasing 0 0 --
V2 intr_test chip_tl_intr_test 0 0 --
chip_jtag_intr_test 0 0 --
V2 tl_d_oob_addr_access chip_tl_errors 20 20 100.00
V2 tl_d_illegal_access chip_tl_errors 20 20 100.00
V2 tl_d_outstanding_access chip_csr_hw_reset 20 20 100.00
chip_csr_rw 20 20 100.00
chip_csr_aliasing 20 20 100.00
chip_same_csr_outstanding 19 20 95.00
V2 tl_d_partial_access chip_csr_hw_reset 20 20 100.00
chip_csr_rw 20 20 100.00
chip_csr_aliasing 20 20 100.00
chip_same_csr_outstanding 19 20 95.00
V2 xbar_base_random_sequence xbar_chip_random 100 100 100.00
V2 xbar_random_delay xbar_chip_smoke_zero_delays 100 100 100.00
xbar_chip_smoke_large_delays 100 100 100.00
xbar_chip_smoke_slow_rsp 100 100 100.00
xbar_chip_random_zero_delays 100 100 100.00
xbar_chip_random_large_delays 100 100 100.00
xbar_chip_random_slow_rsp 100 100 100.00
V2 xbar_unmapped_address xbar_chip_unmapped_addr 100 100 100.00
xbar_chip_error_and_unmapped_addr 100 100 100.00
V2 xbar_error_cases xbar_chip_error_random 100 100 100.00
xbar_chip_error_and_unmapped_addr 100 100 100.00
V2 xbar_all_access_same_device xbar_chip_access_same_device 100 100 100.00
xbar_chip_access_same_device_slow_rsp 100 100 100.00
V2 xbar_all_hosts_use_same_source_id xbar_chip_same_source 100 100 100.00
V2 xbar_stress_all xbar_chip_stress_all 100 100 100.00
xbar_chip_stress_all_with_error 100 100 100.00
V2 xbar_stress_with_reset xbar_chip_stress_all_with_rand_reset 100 100 100.00
xbar_chip_stress_all_with_reset_error 100 100 100.00
V2 TOTAL 1998 2001 99.85
Unmapped tests chip_uart_tx_rx_bootstrap 1 1 100.00
chip_spi_tx_rx 1 1 100.00
chip_aes_encr 1 1 100.00
chip_dif_gpio_smoketest 1 1 100.00
chip_gpio 1 1 100.00
chip_dif_plic_smoketest 1 1 100.00
chip_flash_ctrl_access 1 1 100.00
chip_dif_otbn_smoketest 0 1 0.00
chip_hmac_sha256_encr 1 1 100.00
chip_rv_timer_irq 1 1 100.00
chip_coremark 1 1 100.00
chip_mem_walk 0 20 0.00
chip_mem_partial_access 0 20 0.00
chip_csr_bit_bash 19 20 95.00
chip_csr_mem_rw_with_rand_reset 3 20 15.00
TOTAL 2133 2195 97.18

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
71.64 96.85 79.74 39.55 16.84 87.67 90.40 90.42

List of Failures

TEST: chip_dif_otbn_smoketest, SEED: 1600326346
LOG: $scratch_path/0.chip_dif_otbn_smoketest/out/run.log

UVM_ERROR @ 2465770000 ps: (otbn_lsu.sv:102) [ASSERT FAILED] DMemRValidAfterReq
UVM_INFO @ 2465770000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_opentitan_tock, SEED: 323925906
LOG: $scratch_path/0.chip_opentitan_tock/out/run.log

UVM_ERROR @ 50000436786 ps: (chip_sw_base_vseq.sv:84) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 50000000 ns

UVM_INFO @ 50000436786 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

TEST: chip_mem_walk, SEED: 1214071890
LOG: $scratch_path/0.chip_mem_walk/out/run.log

UVM_ERROR @ 4651820000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 4651820000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 3675758742
LOG: $scratch_path/0.chip_mem_partial_access/out/run.log

UVM_ERROR @ 414960000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 414960000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 1406951330
LOG: $scratch_path/0.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 966420000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 966420000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 1067504432
LOG: $scratch_path/1.chip_mem_walk/out/run.log

UVM_ERROR @ 1907300000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 1907300000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 2891027986
LOG: $scratch_path/1.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412870000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412870000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 3021601603
LOG: $scratch_path/2.chip_mem_walk/out/run.log

UVM_ERROR @ 6389110000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 6389110000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 2248194774
LOG: $scratch_path/2.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412260000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412260000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_same_csr_outstanding, SEED: 673025014
LOG: $scratch_path/2.chip_same_csr_outstanding/out/run.log

UVM_ERROR @ 22285460000 ps: (cip_base_vseq.sv:151) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed masked_data == exp_data (268435458 [0x10000002] vs 0 [0x0]) addr 0x4117002c read out mismatch
UVM_INFO @ 22285460000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 3189080650
LOG: $scratch_path/2.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412213173 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412213173 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 1132730910
LOG: $scratch_path/3.chip_mem_walk/out/run.log

UVM_ERROR @ 4656900000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 4656900000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 2431084950
LOG: $scratch_path/3.chip_mem_partial_access/out/run.log

UVM_ERROR @ 413590000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 413590000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 766936884
LOG: $scratch_path/4.chip_mem_walk/out/run.log

UVM_ERROR @ 1907300000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 1907300000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 2508504426
LOG: $scratch_path/4.chip_mem_partial_access/out/run.log

UVM_ERROR @ 413830000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 413830000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 4000798888
LOG: $scratch_path/4.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412212234 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412212234 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 508142255
LOG: $scratch_path/5.chip_mem_walk/out/run.log

UVM_ERROR @ 6389130000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 6389130000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 2435401308
LOG: $scratch_path/5.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412800000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412800000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 4113997148
LOG: $scratch_path/6.chip_mem_walk/out/run.log

UVM_ERROR @ 1907300000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 1907300000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 2274360330
LOG: $scratch_path/6.chip_mem_partial_access/out/run.log

UVM_ERROR @ 416200000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 416200000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 1140644348
LOG: $scratch_path/6.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412220769 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412220769 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 3323026036
LOG: $scratch_path/7.chip_mem_walk/out/run.log

UVM_ERROR @ 4661010000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 4661010000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 553626202
LOG: $scratch_path/7.chip_mem_partial_access/out/run.log

UVM_ERROR @ 413630000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 413630000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 3185036530
LOG: $scratch_path/7.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 945250000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 945250000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 1526585911
LOG: $scratch_path/8.chip_mem_walk/out/run.log

UVM_ERROR @ 6398590000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 6398590000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 1534636144
LOG: $scratch_path/8.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412710000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412710000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 3802360428
LOG: $scratch_path/8.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412218092 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412218092 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 4166135999
LOG: $scratch_path/9.chip_mem_walk/out/run.log

UVM_ERROR @ 1907300000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 1907300000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 1881258755
LOG: $scratch_path/9.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412610000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412610000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 1045591202
LOG: $scratch_path/9.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412228981 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412228981 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 269800682
LOG: $scratch_path/10.chip_mem_walk/out/run.log

UVM_ERROR @ 1907300000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 1907300000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 2561114250
LOG: $scratch_path/10.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412350000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412350000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 102330559
LOG: $scratch_path/10.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 412990000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412990000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 1739949547
LOG: $scratch_path/11.chip_mem_walk/out/run.log

UVM_ERROR @ 4658080000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 4658080000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 1279292461
LOG: $scratch_path/11.chip_mem_partial_access/out/run.log

UVM_ERROR @ 413170000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 413170000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 848419917
LOG: $scratch_path/11.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412227608 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412227608 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 2790962283
LOG: $scratch_path/12.chip_mem_walk/out/run.log

UVM_ERROR @ 6377270000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 6377270000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 3513661486
LOG: $scratch_path/12.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412530000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412530000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 3494542199
LOG: $scratch_path/12.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412229025 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412229025 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 3293175842
LOG: $scratch_path/13.chip_mem_walk/out/run.log

UVM_ERROR @ 1907300000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 1907300000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 2592709709
LOG: $scratch_path/13.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412710000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412710000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 3058918169
LOG: $scratch_path/13.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 412450000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412450000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 3950520007
LOG: $scratch_path/14.chip_mem_walk/out/run.log

UVM_ERROR @ 6375060000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 6375060000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 652081319
LOG: $scratch_path/14.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412650000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412650000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_bit_bash, SEED: 3925359322
LOG: $scratch_path/14.chip_csr_bit_bash/out/run.log

UVM_ERROR @ 3674770000 ps: (csr_utils_pkg.sv:489) [csr_utils::csr_rd_check] Check failed obs == exp (268435459 [0x10000003] vs 0 [0x0]) Regname: ral.edn0.err_code Wrote ral.edn0.err_code[0]: 1
UVM_INFO @ 3674770000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 2641980243
LOG: $scratch_path/14.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412228729 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412228729 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 4009131904
LOG: $scratch_path/15.chip_mem_walk/out/run.log

UVM_ERROR @ 1907300000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 1907300000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 4161300270
LOG: $scratch_path/15.chip_mem_partial_access/out/run.log

UVM_ERROR @ 414650000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 414650000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 4188979373
LOG: $scratch_path/15.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412212598 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412212598 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 1966183490
LOG: $scratch_path/16.chip_mem_walk/out/run.log

UVM_ERROR @ 1907300000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 1907300000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 822305054
LOG: $scratch_path/16.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412860000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412860000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 1182215446
LOG: $scratch_path/16.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 969500000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 969500000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 3091748783
LOG: $scratch_path/17.chip_mem_walk/out/run.log

UVM_ERROR @ 4655260000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 4655260000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 3381626997
LOG: $scratch_path/17.chip_mem_partial_access/out/run.log

UVM_ERROR @ 413690000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 413690000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 3921307186
LOG: $scratch_path/17.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412226339 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412226339 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 3971274795
LOG: $scratch_path/18.chip_mem_walk/out/run.log

UVM_ERROR @ 6382280000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 6382280000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 3425171042
LOG: $scratch_path/18.chip_mem_partial_access/out/run.log

UVM_ERROR @ 412450000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 412450000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 2652564083
LOG: $scratch_path/18.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 413470000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 413470000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_walk, SEED: 2662487012
LOG: $scratch_path/19.chip_mem_walk/out/run.log

UVM_ERROR @ 6392020000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 6392020000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_mem_partial_access, SEED: 3199425875
LOG: $scratch_path/19.chip_mem_partial_access/out/run.log

UVM_ERROR @ 413250000 ps: (cip_base_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed item.d_error == is_tl_err (1 [0x1] vs 0 [0x0]) unmapped: 0, mem_access_err: 0, csr_aligned_err: 0, csr_size_err: 0,                     item_err: 0
UVM_INFO @ 413250000 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

TEST: chip_csr_mem_rw_with_rand_reset, SEED: 342627842
LOG: $scratch_path/19.chip_csr_mem_rw_with_rand_reset/out/run.log

UVM_ERROR @ 1412216932 ps: (tlul_assert.sv:263) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 1412216932 ps: (uvm_report_server.svh:894) [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

Quit count reached!

Past Results