Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	4350	1			T4	5		T5	5		T12	35
all_values[1]	3400	1			T4	4		T5	4		T12	32
all_values[2]	3950	1			T4	1		T5	1		T12	35
all_values[3]	2650	1			T4	3		T5	3		T12	22
all_values[4]	3850	1			T4	1		T5	1		T12	30
all_values[5]	3150	1			T4	3		T5	3		T12	24
all_values[6]	2750	1			T4	3		T5	3		T12	21
all_values[7]	2600	1			T4	4		T5	4		T12	17
all_values[8]	3000	1			T4	2		T5	2		T12	26
all_values[9]	3400	1			T4	4		T5	4		T12	25
all_values[10]	2450	1			T4	3		T5	3		T12	21
all_values[11]	3050	1			T4	3		T5	3		T12	26
all_values[12]	2550	1			T4	1		T5	1		T12	24
all_values[13]	3650	1			T4	3		T5	3		T12	31
all_values[14]	3200	1			T4	6		T5	6		T12	27
all_values[15]	3200	1			T4	4		T5	4		T12	27
all_values[16]	2250	1			T4	3		T5	3		T12	15
all_values[17]	3050	1			T4	5		T5	5		T12	27
all_values[18]	3250	1			T4	1		T5	1		T12	26
all_values[19]	3550	1			T4	3		T5	3		T12	28
all_values[20]	2250	1			T4	1		T5	1		T12	21
all_values[21]	3550	1			T4	3		T5	3		T12	28
all_values[22]	2800	1			T4	2		T5	2		T12	20
all_values[23]	2750	1			T4	3		T5	3		T12	18
all_values[24]	2500	1			T4	4		T5	4		T12	20
all_values[25]	2850	1			T4	3		T5	3		T12	25
all_values[26]	2750	1			T4	3		T5	3		T12	22
all_values[27]	3050	1			T4	1		T5	1		T12	28
all_values[28]	2050	1			T4	1		T5	1		T12	18
all_values[29]	4150	1			T4	1		T5	1		T12	37
all_values[30]	3750	1			T4	5		T5	5		T12	31
all_values[31]	3150	1			T4	3		T5	3		T12	27
all_values[32]	3400	1			T4	4		T5	4		T12	27
all_values[33]	2450	1			T4	3		T5	3		T12	22
all_values[34]	3050	1			T4	1		T5	1		T12	24
all_values[35]	2550	1			T4	5		T5	5		T12	17
all_values[36]	2500	1			T4	2		T5	2		T12	23
all_values[37]	2500	1			T4	2		T5	2		T12	22
all_values[38]	2700	1			T4	4		T5	4		T12	19
all_values[39]	2900	1			T4	4		T5	4		T12	26
all_values[40]	2900	1			T4	2		T5	2		T12	24
all_values[41]	3550	1			T4	1		T5	1		T12	33
all_values[42]	3650	1			T4	3		T5	3		T12	26
all_values[43]	2150	1			T4	1		T5	1		T12	19
all_values[44]	2600	1			T4	2		T5	2		T12	20
all_values[45]	2700	1			T4	6		T5	6		T12	21
all_values[46]	2650	1			T4	3		T5	3		T12	23
all_values[47]	2950	1			T4	3		T5	3		T12	24
all_values[48]	3850	1			T4	7		T5	7		T12	32
all_values[49]	2600	1			T4	4		T5	4		T12	20
all_values[50]	2650	1			T4	1		T5	1		T12	22
all_values[51]	2450	1			T4	1		T5	1		T12	21
all_values[52]	3900	1			T4	6		T5	6		T12	27
all_values[53]	3250	1			T4	5		T5	5		T12	26
all_values[54]	1400	1			T12	12		T13	12		T14	12
all_values[55]	3750	1			T4	1		T5	1		T12	29
all_values[56]	3200	1			T12	25		T13	25		T14	25
all_values[57]	3250	1			T4	3		T5	3		T12	26
all_values[58]	2800	1			T4	4		T5	4		T12	22
all_values[59]	3000	1			T4	4		T5	4		T12	28
all_values[60]	3100	1			T4	2		T5	2		T12	27
all_values[61]	3450	1			T4	3		T5	3		T12	27
all_values[62]	3400	1			T4	4		T5	4		T12	27
all_values[63]	4250	1			T4	1		T5	1		T12	37