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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.51 98.51 89.34 98.70 93.62 98.57 58.30


Total test records in report: 900
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T751 /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.86127168758958937542238015223005135854337321135911385188731391616537819507016 Nov 22 01:58:07 PM PST 23 Nov 22 01:58:32 PM PST 23 766920935 ps
T752 /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.82764277655239233134287958946180091993918705007600713112509351844633114858139 Nov 22 01:58:32 PM PST 23 Nov 22 02:03:27 PM PST 23 5188549184 ps
T753 /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.59105127115688268613861166525863237187533142314395494408382062329636798300808 Nov 22 01:56:54 PM PST 23 Nov 22 01:57:44 PM PST 23 28419483435 ps
T754 /workspace/coverage/xbar_build_mode/12.xbar_random.15323307857486370528661307444414720832844931173649974934808753394717926043633 Nov 22 01:56:56 PM PST 23 Nov 22 01:57:36 PM PST 23 4402420935 ps
T755 /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.23833974457144417883066529747148738366787494797696058934759607200180627102965 Nov 22 01:57:56 PM PST 23 Nov 22 02:03:24 PM PST 23 126189108435 ps
T756 /workspace/coverage/xbar_build_mode/15.xbar_random.65967420207295845967760229798662031545993234830520618744216261533128913966423 Nov 22 01:56:51 PM PST 23 Nov 22 01:57:27 PM PST 23 4402420935 ps
T757 /workspace/coverage/xbar_build_mode/5.xbar_stress_all.54160907065305977678533069528459652702646453638876779683572745574631158109156 Nov 22 01:56:23 PM PST 23 Nov 22 01:58:37 PM PST 23 18904859184 ps
T758 /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1378768485856532714175094183883944095890767071252927647524636985662956025734 Nov 22 01:57:53 PM PST 23 Nov 22 02:03:09 PM PST 23 188793233435 ps
T759 /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.57795305007841566871949203054898101845611816311177477450262794424133840749196 Nov 22 01:59:29 PM PST 23 Nov 22 02:03:18 PM PST 23 5188549184 ps
T760 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.5954765221544935464081935528984587586663036869314194412123203551030523995029 Nov 22 01:59:34 PM PST 23 Nov 22 02:03:21 PM PST 23 5188549184 ps
T761 /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.37016085263902826185455786617084744618395543954734277036890407559944362990590 Nov 22 01:59:28 PM PST 23 Nov 22 01:59:55 PM PST 23 3310545935 ps
T762 /workspace/coverage/xbar_build_mode/5.xbar_same_source.64376559714457528803612092927354828818521395320615612429246470654904773319824 Nov 22 01:56:41 PM PST 23 Nov 22 01:57:20 PM PST 23 7116170935 ps
T763 /workspace/coverage/xbar_build_mode/49.xbar_stress_all.108269090839502998467372311535571291956909052294547990158758104079085561594620 Nov 22 01:59:29 PM PST 23 Nov 22 02:01:47 PM PST 23 18904859184 ps
T764 /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.26354708109231901782838952101731732130537430624108557613004612787207160576361 Nov 22 01:56:53 PM PST 23 Nov 22 01:57:54 PM PST 23 7399045935 ps
T765 /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.81744020172692813950122595086691477225693923840343296464876891713603743937718 Nov 22 01:56:52 PM PST 23 Nov 22 02:02:18 PM PST 23 126189108435 ps
T766 /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.73959896250919288314884116439821731724675767372538125740084359839687835978166 Nov 22 01:59:31 PM PST 23 Nov 22 01:59:57 PM PST 23 766920935 ps
T767 /workspace/coverage/xbar_build_mode/0.xbar_smoke.9147652306005777674925673655269014208162070882158715099270051063694474559371 Nov 22 01:55:56 PM PST 23 Nov 22 01:56:01 PM PST 23 669983435 ps
T768 /workspace/coverage/xbar_build_mode/40.xbar_same_source.104732415200060413099860571616498062398315925208339662024218051926413464575476 Nov 22 01:58:48 PM PST 23 Nov 22 01:59:30 PM PST 23 7116170935 ps
T769 /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.50757837858836594636045838165299299739595024980360521186744625149559176155979 Nov 22 01:59:28 PM PST 23 Nov 22 02:04:53 PM PST 23 126189108435 ps
T770 /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.69718051052823339281115588418969437146709599170022213037647867669128855014603 Nov 22 01:56:49 PM PST 23 Nov 22 01:57:50 PM PST 23 7399045935 ps
T771 /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.29986941869734533092890101442338969617275727186605800841406341219526949551934 Nov 22 01:56:58 PM PST 23 Nov 22 02:02:23 PM PST 23 126189108435 ps
T772 /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.30995276346675516784644048421628247085559140772387758293042700173967007392979 Nov 22 01:58:25 PM PST 23 Nov 22 01:59:13 PM PST 23 17662295935 ps
T773 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.63380121682986066472044723727662105394713999077655327663000699932874013125926 Nov 22 01:57:11 PM PST 23 Nov 22 02:01:05 PM PST 23 5188549184 ps
T774 /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.80802880724717385578299843581286118735055132749988638950622653209053557662489 Nov 22 01:55:57 PM PST 23 Nov 22 02:01:27 PM PST 23 188793233435 ps
T775 /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.35613952328072686074333952029899658036566250133698066651646954619830340870478 Nov 22 01:58:25 PM PST 23 Nov 22 01:58:56 PM PST 23 3307045935 ps
T776 /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.38417533205741918085401044437595929913365316872028922627929878136431680849338 Nov 22 01:56:42 PM PST 23 Nov 22 01:57:08 PM PST 23 766920935 ps
T777 /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.4484489712494645370777134697745763350046282050567534244024436031983957280501 Nov 22 01:59:11 PM PST 23 Nov 22 01:59:15 PM PST 23 116233435 ps
T778 /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.87268709572054278480847109009805193856920618972592027072214083252857948142615 Nov 22 01:59:26 PM PST 23 Nov 22 02:04:20 PM PST 23 5188549184 ps
T779 /workspace/coverage/xbar_build_mode/39.xbar_same_source.100680484955881242776361322078038221547352785779851720108305512715071468162048 Nov 22 01:58:44 PM PST 23 Nov 22 01:59:30 PM PST 23 7116170935 ps
T780 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.88166210607299285909185516515702187017582526613809470316294307708439154586466 Nov 22 01:58:51 PM PST 23 Nov 22 02:02:44 PM PST 23 5188549184 ps
T781 /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.15266716488310997514617817265388185094188976229320059296220526277199963975458 Nov 22 01:59:11 PM PST 23 Nov 22 02:04:01 PM PST 23 5188549184 ps
T782 /workspace/coverage/xbar_build_mode/10.xbar_error_random.40065284502547000215165541787751702629585345404914563728929331290398246616420 Nov 22 01:56:47 PM PST 23 Nov 22 01:57:23 PM PST 23 4402420935 ps
T783 /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.74692422036416517934584864010174666653393269437714078863994120885733021815326 Nov 22 01:58:09 PM PST 23 Nov 22 01:58:59 PM PST 23 28419483435 ps
T784 /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.94028873104371495913784088811478904460274735728575458149711207099415673741592 Nov 22 01:56:18 PM PST 23 Nov 22 02:01:45 PM PST 23 126189108435 ps
T785 /workspace/coverage/xbar_build_mode/11.xbar_stress_all.93414591420101753374637533739050422330486221605628220474838954622437196829825 Nov 22 01:56:51 PM PST 23 Nov 22 01:59:09 PM PST 23 18904859184 ps
T786 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.104552443968790423170363833247221037575127920211869359569516380853309626512359 Nov 22 01:58:41 PM PST 23 Nov 22 02:03:39 PM PST 23 5188549184 ps
T787 /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.43841032169521913652872898542418077364844946929473053451059935539661973297403 Nov 22 01:56:48 PM PST 23 Nov 22 02:02:15 PM PST 23 188793233435 ps
T788 /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.34070782073849867879618821594168878644176799804994134120106237481288934143069 Nov 22 01:58:12 PM PST 23 Nov 22 01:58:16 PM PST 23 116233435 ps
T789 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.73109237970501279612063467225330944893975178509496591981159077272037188362492 Nov 22 01:57:54 PM PST 23 Nov 22 02:02:49 PM PST 23 5188549184 ps
T790 /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.22456348743121377380234442651164575612126279034056263789489552532063721088994 Nov 22 01:56:17 PM PST 23 Nov 22 01:56:46 PM PST 23 3310545935 ps
T791 /workspace/coverage/xbar_build_mode/7.xbar_stress_all.62259677637245474281982901799518052766991926934557945035183380485805044071214 Nov 22 01:56:21 PM PST 23 Nov 22 01:58:44 PM PST 23 18904859184 ps
T792 /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.93312289607544323843658701217415944042952398808916944162972182447154102083789 Nov 22 01:59:41 PM PST 23 Nov 22 02:05:12 PM PST 23 126189108435 ps
T793 /workspace/coverage/xbar_build_mode/22.xbar_random.81846201814973035985666599100589233478787114282214881831540534844573467027056 Nov 22 01:57:41 PM PST 23 Nov 22 01:58:23 PM PST 23 4402420935 ps
T794 /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.56038759591834728429880100959670495292764810304385271199455943760526434386040 Nov 22 01:58:08 PM PST 23 Nov 22 02:01:53 PM PST 23 5188549184 ps
T795 /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.48209690045522830486989993068782667444684550054828607005662118946208760716268 Nov 22 01:56:49 PM PST 23 Nov 22 02:01:54 PM PST 23 5188549184 ps
T796 /workspace/coverage/xbar_build_mode/10.xbar_same_source.115357944198964072245359727347641968537358172570057477857783618661532812746071 Nov 22 01:56:53 PM PST 23 Nov 22 01:57:30 PM PST 23 7116170935 ps
T797 /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.53404342710124162108954825292610834679212794512682720692326853463428907582602 Nov 22 01:58:56 PM PST 23 Nov 22 02:04:22 PM PST 23 188793233435 ps
T798 /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.23721986079475719904549937338259850771284133211122023439136837032338503708797 Nov 22 01:56:42 PM PST 23 Nov 22 02:01:37 PM PST 23 5188549184 ps
T799 /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.44016875679582213511268544643310967157681297492054222109122874381771990392001 Nov 22 01:56:52 PM PST 23 Nov 22 01:57:41 PM PST 23 28419483435 ps
T800 /workspace/coverage/xbar_build_mode/8.xbar_random.73730091651516586587972952512603571804975674817580872349308025807728170638434 Nov 22 01:56:50 PM PST 23 Nov 22 01:57:29 PM PST 23 4402420935 ps
T801 /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.7632239199356167138728225800545137823079344906681265217686990613671002817467 Nov 22 01:56:21 PM PST 23 Nov 22 01:57:10 PM PST 23 28419483435 ps
T802 /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.72931871570324168975198657086625165212370929130271243691477665939577344307253 Nov 22 01:58:13 PM PST 23 Nov 22 01:58:58 PM PST 23 17662295935 ps
T803 /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.9935317967281861568926601702811689827146642489718963733827407744680587464620 Nov 22 01:57:44 PM PST 23 Nov 22 01:58:13 PM PST 23 766920935 ps
T804 /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.29025828551907524685422933967057042984420413240920745128906423903042456006503 Nov 22 01:56:13 PM PST 23 Nov 22 02:09:01 PM PST 23 304288045935 ps
T805 /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.562048886162943952805559118712243480149376563123162882806948745923684382850 Nov 22 01:59:33 PM PST 23 Nov 22 02:00:01 PM PST 23 3310545935 ps
T806 /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.92801415111354536189430070081421582748126309535942592837297676427886162893038 Nov 22 01:57:22 PM PST 23 Nov 22 02:02:44 PM PST 23 188793233435 ps
T807 /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.8067682493401338937038668425957286764133110385781387334336599164619962034909 Nov 22 01:56:45 PM PST 23 Nov 22 01:57:31 PM PST 23 17662295935 ps
T808 /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.29108922158359978401843758156668942959633586813063217583660154065766986945193 Nov 22 01:59:32 PM PST 23 Nov 22 02:01:33 PM PST 23 18894549184 ps
T809 /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.54216479164570301687942355075933785798197631199441102043048072955897457604404 Nov 22 01:58:52 PM PST 23 Nov 22 01:59:41 PM PST 23 17662295935 ps
T810 /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.83858242747227639361337815041551033962725685243075463580462593259813630714551 Nov 22 01:56:54 PM PST 23 Nov 22 02:09:55 PM PST 23 304288045935 ps
T811 /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.4538416094012273241368539252717409979122842038958670855183738120237668124694 Nov 22 01:56:18 PM PST 23 Nov 22 02:00:04 PM PST 23 5188549184 ps
T812 /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.49874236186100153323508889381051971729526607852459624633276231669132415039555 Nov 22 01:56:53 PM PST 23 Nov 22 01:56:57 PM PST 23 116233435 ps
T813 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.7867190486828829596552429440578943758030732060636472236823866180432623178737 Nov 22 01:58:09 PM PST 23 Nov 22 02:01:57 PM PST 23 5188549184 ps
T814 /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.57112404281087326735607283537541822462439143163466779523181455945297061050810 Nov 22 01:59:42 PM PST 23 Nov 22 02:03:25 PM PST 23 5188549184 ps
T815 /workspace/coverage/xbar_build_mode/41.xbar_stress_all.38591136280634380426481492983438460631036428042196077137492239932925629628318 Nov 22 01:58:52 PM PST 23 Nov 22 02:01:07 PM PST 23 18904859184 ps
T816 /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.13634744950835065828894642105091816885605207765290458560455822509728921254672 Nov 22 01:56:21 PM PST 23 Nov 22 01:56:25 PM PST 23 116233435 ps
T817 /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.47370949236537125621020985551475723683206367873085149452141460753042393452655 Nov 22 01:58:46 PM PST 23 Nov 22 02:02:38 PM PST 23 5188549184 ps
T818 /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.80838674473252137862680043017173151294082922101622932919788353172505235321212 Nov 22 01:59:14 PM PST 23 Nov 22 02:00:02 PM PST 23 28419483435 ps
T819 /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.61784516150035825269372193281200618488431602495479923809134434268056985306986 Nov 22 01:56:58 PM PST 23 Nov 22 02:01:57 PM PST 23 5188549184 ps
T820 /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.102600070833347950987269011911510341994960887100316496895295849556864341347848 Nov 22 01:58:55 PM PST 23 Nov 22 01:59:48 PM PST 23 28419483435 ps
T821 /workspace/coverage/xbar_build_mode/14.xbar_error_random.34682342655073822854888210928298762114022448874475791593379019066786330560305 Nov 22 01:56:53 PM PST 23 Nov 22 01:57:27 PM PST 23 4402420935 ps
T822 /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.41081125846342064498184587649346963982810047642842154210430816089373438158835 Nov 22 01:58:27 PM PST 23 Nov 22 01:59:30 PM PST 23 7399045935 ps
T823 /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.60875404126118125375185403435987865127556943116105029760348226729003207206512 Nov 22 01:56:20 PM PST 23 Nov 22 01:57:06 PM PST 23 17662295935 ps
T824 /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.77099357992659016857869449690560024151644051141857598988214443599816192654433 Nov 22 01:57:23 PM PST 23 Nov 22 02:01:15 PM PST 23 5188549184 ps
T825 /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.65284889576323709794229213409696974755652660932560974034320123551571278569995 Nov 22 01:59:25 PM PST 23 Nov 22 02:04:56 PM PST 23 188793233435 ps
T826 /workspace/coverage/xbar_build_mode/25.xbar_random.7554392071990937792540297638309433058732825137190560433027391939586228704402 Nov 22 01:57:51 PM PST 23 Nov 22 01:58:32 PM PST 23 4402420935 ps
T827 /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.87144518977228060809533824779261123900339763421634162171686626072299715983368 Nov 22 01:58:58 PM PST 23 Nov 22 02:00:03 PM PST 23 7399045935 ps
T828 /workspace/coverage/xbar_build_mode/43.xbar_smoke.44461963971334626322415728424972070052068152599246849697053166875873229580531 Nov 22 01:58:50 PM PST 23 Nov 22 01:58:59 PM PST 23 669983435 ps
T829 /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.94752590368404441812429805912168934571964901402096380507449387675842005350765 Nov 22 01:58:45 PM PST 23 Nov 22 02:11:27 PM PST 23 304288045935 ps
T830 /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.90074689899679291086251485051369828082804080588635822903328661492035631938922 Nov 22 01:56:48 PM PST 23 Nov 22 02:02:18 PM PST 23 126189108435 ps
T831 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.14016704970067949703437354802781016596356120097872003180963168785738957645411 Nov 22 01:58:53 PM PST 23 Nov 22 02:03:48 PM PST 23 5188549184 ps
T832 /workspace/coverage/xbar_build_mode/42.xbar_same_source.7613118661176632031761081779664812845382640343215028799199396318271267119092 Nov 22 01:58:58 PM PST 23 Nov 22 01:59:37 PM PST 23 7116170935 ps
T833 /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.109617460927999244534432923884477858138429640535153466439423784726058490989114 Nov 22 01:57:42 PM PST 23 Nov 22 02:01:26 PM PST 23 5188549184 ps
T834 /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.6370823308345896701708803081997339204647381937401402950239843347805917033904 Nov 22 01:56:52 PM PST 23 Nov 22 01:57:19 PM PST 23 766920935 ps
T835 /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.22080635048926627123884416941167146656048801567225105455835995864344299573153 Nov 22 01:57:25 PM PST 23 Nov 22 02:01:13 PM PST 23 5188549184 ps
T836 /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.21078788325836154564623505288075530138320262409240716094828879354778394159823 Nov 22 01:57:49 PM PST 23 Nov 22 01:58:17 PM PST 23 766920935 ps
T837 /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.37811218510546718090540880650005616918688372568931202316520355104071499014331 Nov 22 01:57:52 PM PST 23 Nov 22 01:57:56 PM PST 23 116233435 ps
T838 /workspace/coverage/xbar_build_mode/43.xbar_error_random.60794635425804136941785627191631749969206909807272783699026576021615365471772 Nov 22 01:59:14 PM PST 23 Nov 22 01:59:51 PM PST 23 4402420935 ps
T839 /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.99452061043641589298839469172365633619532988088554936807019520931084438110446 Nov 22 01:58:26 PM PST 23 Nov 22 01:58:56 PM PST 23 3310545935 ps
T840 /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.83168824691791314718142069036420287117158324550098556158224533547379349299304 Nov 22 01:59:53 PM PST 23 Nov 22 02:01:51 PM PST 23 18894549184 ps
T841 /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.70751198548631751151612814852426276485087691060089490726528930692726707605275 Nov 22 01:56:52 PM PST 23 Nov 22 01:57:18 PM PST 23 766920935 ps
T842 /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.594812922959669099248416522094515203877421772205962041488169017831569160759 Nov 22 01:56:40 PM PST 23 Nov 22 01:56:44 PM PST 23 116233435 ps
T843 /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.29078217159214922219871168864977021660303265964138414100005514967808658350147 Nov 22 01:56:51 PM PST 23 Nov 22 01:58:57 PM PST 23 18894549184 ps
T844 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.66909466692338966531795029582562305886378547158929832223324767372526894097656 Nov 22 01:58:27 PM PST 23 Nov 22 02:03:19 PM PST 23 5188549184 ps
T845 /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.59987283187735215154019404552229998020592186343868490794715122162844252712929 Nov 22 01:58:33 PM PST 23 Nov 22 02:03:59 PM PST 23 188793233435 ps
T846 /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.26470764864506861852378819580177906120995872883519682258173330503650307809410 Nov 22 01:57:24 PM PST 23 Nov 22 02:02:53 PM PST 23 188793233435 ps
T847 /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.77155824684318998161430542408697542745346860569514774619284678515238188990520 Nov 22 01:56:56 PM PST 23 Nov 22 01:57:43 PM PST 23 17662295935 ps
T848 /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.33979700169381826434668169864097558951370247208910953499212109049588198372948 Nov 22 01:57:52 PM PST 23 Nov 22 01:59:53 PM PST 23 18894549184 ps
T849 /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.115414561580485732242099269834130590267871108043145236789229527709674367269234 Nov 22 01:58:08 PM PST 23 Nov 22 01:59:14 PM PST 23 7399045935 ps
T850 /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.86335330567231344493349272114454625264948048430501251649524073572295835744003 Nov 22 01:57:21 PM PST 23 Nov 22 01:58:30 PM PST 23 7399045935 ps
T851 /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.49962800902239457239975936713043772085119026920280067558873230422039911599720 Nov 22 01:58:53 PM PST 23 Nov 22 02:11:39 PM PST 23 304288045935 ps
T852 /workspace/coverage/xbar_build_mode/17.xbar_random.4003176201612578365813536902031068371355076103830840762677132688455484969193 Nov 22 01:56:54 PM PST 23 Nov 22 01:57:37 PM PST 23 4402420935 ps
T853 /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.17471908497687680571557667672093705855577087922302953645765408933429161196378 Nov 22 01:56:20 PM PST 23 Nov 22 01:57:10 PM PST 23 28419483435 ps
T854 /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.47096051602614934553243049260945785653889472573716205112532687303190545699673 Nov 22 01:57:11 PM PST 23 Nov 22 01:58:03 PM PST 23 17662295935 ps
T855 /workspace/coverage/xbar_build_mode/4.xbar_error_random.2853805830412698263073521608287017606672615985813012820098005644025873962018 Nov 22 01:56:22 PM PST 23 Nov 22 01:56:56 PM PST 23 4402420935 ps
T856 /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.37674923560696201764228360838843996448384679524426268905936034768803878337062 Nov 22 01:57:50 PM PST 23 Nov 22 02:03:14 PM PST 23 188793233435 ps
T857 /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.107626075011078360555464519881136942134722206342754167821088589281400664052910 Nov 22 01:56:37 PM PST 23 Nov 22 01:57:03 PM PST 23 766920935 ps
T858 /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.82592738577964842684699644215596733227859032895703987529957151307552568275633 Nov 22 01:56:19 PM PST 23 Nov 22 02:09:19 PM PST 23 304288045935 ps
T859 /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.84434419352448267327016708687491479929967913995886075114831537835512771291241 Nov 22 01:56:56 PM PST 23 Nov 22 01:57:47 PM PST 23 28419483435 ps
T860 /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.61524108045871645603395422727619693406063355846618869615848695560634870616367 Nov 22 01:58:51 PM PST 23 Nov 22 02:02:42 PM PST 23 5188549184 ps
T861 /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.83644630036828641672172229539928078343189245847210876256193078312623321985430 Nov 22 01:59:25 PM PST 23 Nov 22 02:04:29 PM PST 23 5188549184 ps
T862 /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.9493106860651480628314528003015749481446640349584376411693490928788352301020 Nov 22 01:58:45 PM PST 23 Nov 22 01:59:40 PM PST 23 28419483435 ps
T863 /workspace/coverage/xbar_build_mode/14.xbar_random.17732852291298085292411020428456809874948328747374544567864619068171277763294 Nov 22 01:56:48 PM PST 23 Nov 22 01:57:25 PM PST 23 4402420935 ps
T864 /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.76786003066375784901254920989376961195492910821452427334612575764429051058557 Nov 22 01:58:27 PM PST 23 Nov 22 01:58:58 PM PST 23 3307045935 ps
T865 /workspace/coverage/xbar_build_mode/49.xbar_same_source.8899628720424381146592272580747073581188493714701377889009417728050200155510 Nov 22 01:59:27 PM PST 23 Nov 22 02:00:08 PM PST 23 7116170935 ps
T866 /workspace/coverage/xbar_build_mode/43.xbar_random.739490941654674767334846711469844473873887678893263086286363056111395265311 Nov 22 01:59:08 PM PST 23 Nov 22 01:59:47 PM PST 23 4402420935 ps
T867 /workspace/coverage/xbar_build_mode/14.xbar_stress_all.78910584591556405364508244673416404359194010791896456132833453137625384154507 Nov 22 01:56:51 PM PST 23 Nov 22 01:59:02 PM PST 23 18904859184 ps
T868 /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.94774520961057306706626831880496585896480412152579224295332044291283197606324 Nov 22 01:59:32 PM PST 23 Nov 22 02:00:45 PM PST 23 7399045935 ps
T869 /workspace/coverage/xbar_build_mode/0.xbar_stress_all.88256318151082469643759781782813921998468903491125765925592580865507799641800 Nov 22 01:56:06 PM PST 23 Nov 22 01:58:23 PM PST 23 18904859184 ps
T870 /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.46168818934696676562057653945424819043973822902545568305765418251367678056140 Nov 22 01:56:55 PM PST 23 Nov 22 01:57:25 PM PST 23 3310545935 ps
T871 /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.6214342100678946633421938069131654391828039112372914582914393064428898588554 Nov 22 01:56:53 PM PST 23 Nov 22 01:57:21 PM PST 23 766920935 ps
T872 /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.13806649431325183589717325482375895375778667139765185050710783378495802865579 Nov 22 01:58:58 PM PST 23 Nov 22 01:59:27 PM PST 23 3310545935 ps
T873 /workspace/coverage/xbar_build_mode/20.xbar_smoke.22822269862650570807332705281593969719760109797552800696871269105649900633715 Nov 22 01:57:22 PM PST 23 Nov 22 01:57:30 PM PST 23 669983435 ps
T874 /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.108259988687269675968505639314938844829245220481285287392913487002815769715053 Nov 22 01:56:24 PM PST 23 Nov 22 02:09:17 PM PST 23 304288045935 ps
T875 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.109921262673061018070528845926044134972523376535849364409994406920822989845868 Nov 22 01:56:11 PM PST 23 Nov 22 01:58:18 PM PST 23 18894549184 ps
T876 /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.24515304819431453564806997927113107715572083506985993485212196931366735853506 Nov 22 01:57:51 PM PST 23 Nov 22 01:59:01 PM PST 23 7399045935 ps
T877 /workspace/coverage/xbar_build_mode/7.xbar_error_random.99896241324684580186403792552610093203243371412667288929344127462815018167497 Nov 22 01:56:22 PM PST 23 Nov 22 01:56:58 PM PST 23 4402420935 ps
T878 /workspace/coverage/xbar_build_mode/40.xbar_smoke.67533268495567927756971911656650387969250158256172439768218396296717261534244 Nov 22 01:58:46 PM PST 23 Nov 22 01:58:57 PM PST 23 669983435 ps
T879 /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.72186039950228087858186799035106615953194374220124740464087073776407199870840 Nov 22 01:58:09 PM PST 23 Nov 22 02:00:16 PM PST 23 18894549184 ps
T880 /workspace/coverage/xbar_build_mode/5.xbar_random.58355571446340004197197597077413201901623338042455582633387295064788239964899 Nov 22 01:56:39 PM PST 23 Nov 22 01:57:16 PM PST 23 4402420935 ps
T881 /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.108697854022969176731059696296665877328664036754730568452007240968414388819530 Nov 22 01:57:51 PM PST 23 Nov 22 02:02:47 PM PST 23 5188549184 ps
T882 /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.31853093889079812574069645837801810912194124335196124187669319305008380944228 Nov 22 01:57:20 PM PST 23 Nov 22 01:57:55 PM PST 23 3307045935 ps
T883 /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.40719947677386964788619546997451603551588247921398959009542053644068199216331 Nov 22 01:58:35 PM PST 23 Nov 22 01:59:40 PM PST 23 7399045935 ps
T884 /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.114658824337720165410085028064698664479711571194662629394119546789278518102609 Nov 22 01:57:11 PM PST 23 Nov 22 01:58:02 PM PST 23 28419483435 ps
T885 /workspace/coverage/xbar_build_mode/25.xbar_same_source.14941293486410887575480906170791366104470010908574399081536498762128944197729 Nov 22 01:57:52 PM PST 23 Nov 22 01:58:32 PM PST 23 7116170935 ps
T886 /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.25863107253940503827477305709452809670984209347038276935435648363811654955728 Nov 22 01:58:36 PM PST 23 Nov 22 02:02:18 PM PST 23 5188549184 ps
T887 /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.33939367917622887037059226592402057228165906301939241606572196118498414636144 Nov 22 01:57:53 PM PST 23 Nov 22 01:58:20 PM PST 23 3310545935 ps
T888 /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.66941849701924031623534767547412659523741575547575473254013543916576553355118 Nov 22 01:58:11 PM PST 23 Nov 22 01:58:15 PM PST 23 116233435 ps
T889 /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.59039235693238368400551737937980673664922936301785901898428218532289857397974 Nov 22 01:58:40 PM PST 23 Nov 22 02:00:42 PM PST 23 18894549184 ps
T890 /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.62664176165282734711275747151033787922705606029504154013356970094794516006302 Nov 22 01:56:42 PM PST 23 Nov 22 01:57:13 PM PST 23 3307045935 ps
T891 /workspace/coverage/xbar_build_mode/48.xbar_random.74884753844040790324274442695159773943619774008614236810211191741388390294558 Nov 22 01:59:27 PM PST 23 Nov 22 02:00:04 PM PST 23 4402420935 ps
T892 /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.86756872274949387484837787074363800238453375508599930716743865716083542594596 Nov 22 01:58:09 PM PST 23 Nov 22 01:58:12 PM PST 23 116233435 ps
T893 /workspace/coverage/xbar_build_mode/7.xbar_smoke.69433826804863296442068265705516864584604801440468229462045883783864624495213 Nov 22 01:56:39 PM PST 23 Nov 22 01:56:44 PM PST 23 669983435 ps
T894 /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.84362495310378559491079735953814955672752502446272847097810796497333965691324 Nov 22 01:56:49 PM PST 23 Nov 22 01:57:58 PM PST 23 7399045935 ps
T895 /workspace/coverage/xbar_build_mode/23.xbar_random.18382398576934170359204735948847069054061538875349154585678899245306956802987 Nov 22 01:57:50 PM PST 23 Nov 22 01:58:29 PM PST 23 4402420935 ps
T896 /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.31509443101151392776709821201999091121940067915935648706781157673953793798263 Nov 22 01:58:11 PM PST 23 Nov 22 02:01:55 PM PST 23 5188549184 ps
T897 /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.23498116684110973181896055738887711701943271394133500500885925259772767652247 Nov 22 01:57:50 PM PST 23 Nov 22 01:58:39 PM PST 23 28419483435 ps
T898 /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.52741280240303355808819004926320366011017040032315331589373931241646230227895 Nov 22 01:56:52 PM PST 23 Nov 22 02:00:41 PM PST 23 5188549184 ps
T899 /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.61983114873724256750565319489659955326776652248133338969263472352285889749300 Nov 22 01:58:58 PM PST 23 Nov 22 01:59:26 PM PST 23 766920935 ps
T900 /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.115644343338442535129983246109113537457274592506154109503582455160199458792951 Nov 22 01:58:31 PM PST 23 Nov 22 01:59:35 PM PST 23 7399045935 ps

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.115574859231229387297236705393811297493641471930915799458494475163507703514056
Short name T9
Test name
Test status
Simulation time 188793233435 ps
CPU time 321.05 seconds
Started Nov 22 01:56:18 PM PST 23
Finished Nov 22 02:01:41 PM PST 23
Peak memory 204808 kb
Host smart-1de4b6a4-1eab-4758-893f-5244b4b8465e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=115574859231229387297236705393811297493641471930915799458494475163507703514056 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.115574859231229387297236705393811297493641471930915799458494475163507703514056
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1247594870698272399159368932965242101369899911983258598580742832433013530637
Short name T29
Test name
Test status
Simulation time 304288045935 ps
CPU time 779.35 seconds
Started Nov 22 01:58:48 PM PST 23
Finished Nov 22 02:11:54 PM PST 23
Peak memory 211284 kb
Host smart-b2b51314-a0d0-4d64-8f71-869706cfdb3e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1247594870698272399159368932965242101369899911983258598580742832433013530637 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build
_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.1247594870698272399159368932965242101369899911983258598580742832433013530637
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.81815072909650903690267852510405157445356052118305413809616123697082638718876
Short name T13
Test name
Test status
Simulation time 5188549184 ps
CPU time 234.22 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 02:00:47 PM PST 23
Peak memory 218964 kb
Host smart-126b978c-8a98-4d96-91c8-a40e4a1d529d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81815072909650903690267852510405157445356052118305413809616123697082638718876 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.81815072909650903690267852510405157445356052118305413809616123697082638718876
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.7153003688303071973427167022725689132717613084893188592321153961569602983351
Short name T6
Test name
Test status
Simulation time 766920935 ps
CPU time 25.09 seconds
Started Nov 22 01:58:43 PM PST 23
Finished Nov 22 01:59:11 PM PST 23
Peak memory 211232 kb
Host smart-40f5fab3-4933-4f4b-a131-4bf9e170a616
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7153003688303071973427167022725689132717613084893188592321153961569602983351 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.7153003688303071973427167022725689132717613084893188592321153961569602983351
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.76212997480375950639643088709260171585084016548955864719307681066678837833569
Short name T20
Test name
Test status
Simulation time 18904859184 ps
CPU time 144.15 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 02:01:35 PM PST 23
Peak memory 205804 kb
Host smart-608a1556-9bb6-47ac-9e34-e9198cd5d1d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76212997480375950639643088709260171585084016548955864719307681066678837833569 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 44.xbar_stress_all.76212997480375950639643088709260171585084016548955864719307681066678837833569
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.68280275657601916090318676249730818074784509710934413485680902476687983533894
Short name T1
Test name
Test status
Simulation time 126189108435 ps
CPU time 324.3 seconds
Started Nov 22 01:58:47 PM PST 23
Finished Nov 22 02:04:18 PM PST 23
Peak memory 211424 kb
Host smart-2ebe2ad0-f832-484e-be3c-cdb6ac574c9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=68280275657601916090318676249730818074784509710934413485680902476687983533894 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.68280275657601916090318676249730818074784509710934413485680902476687983533894
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.114682944197835695028603368439628601001027712487738454775173291684310515817559
Short name T16
Test name
Test status
Simulation time 18894549184 ps
CPU time 117.12 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:58:49 PM PST 23
Peak memory 211424 kb
Host smart-2fc92f0c-53e3-48e0-b82e-ee31f5dde8de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=114682944197835695028603368439628601001027712487738454775173291684310515817559 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.114682944197835695028603368439628601001027712487738454775173291684310515817559
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.55540881414075835327107314737042683472292737170713745437210585320971784058484
Short name T52
Test name
Test status
Simulation time 7399045935 ps
CPU time 61.86 seconds
Started Nov 22 01:57:56 PM PST 23
Finished Nov 22 01:59:00 PM PST 23
Peak memory 206340 kb
Host smart-7bf4b2bd-1c71-4cfe-8358-b6b09650e0e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55540881414075835327107314737042683472292737170713745437210585320971784058484 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.55540881414075835327107314737042683472292737170713745437210585320971784058484
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.40247508817201562427994421186737551551617464179524533389671559357829139467325
Short name T26
Test name
Test status
Simulation time 5188549184 ps
CPU time 297.48 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 02:01:53 PM PST 23
Peak memory 208364 kb
Host smart-d466d47d-dd77-402a-9166-6389ac7ae8a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40247508817201562427994421186737551551617464179524533389671559357829139467325 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.40247508817201562427994421186737551551617464179524533389671559357829139467325
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.91735923384444628725833195642127440347275688169651457590834583306689636453159
Short name T84
Test name
Test status
Simulation time 3307045935 ps
CPU time 27.91 seconds
Started Nov 22 01:57:11 PM PST 23
Finished Nov 22 01:57:45 PM PST 23
Peak memory 211276 kb
Host smart-f9fd5b08-72b7-46e5-b1f8-f67923d91fcc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91735923384444628725833195642127440347275688169651457590834583306689636453159 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 18.xbar_unmapped_addr.91735923384444628725833195642127440347275688169651457590834583306689636453159
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2109265341631309817616781298581430824194784697223220369056070433485132083876
Short name T726
Test name
Test status
Simulation time 7399045935 ps
CPU time 66.45 seconds
Started Nov 22 01:56:15 PM PST 23
Finished Nov 22 01:57:23 PM PST 23
Peak memory 211456 kb
Host smart-ea252779-4b17-4acd-8b1f-822e64b7a4a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2109265341631309817616781298581430824194784697223220369056070433485132083876 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2109265341631309817616781298581430824194784697223220369056070433485132083876
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2761069042983229808257807027921453033372364415218324679186252121463181922928
Short name T544
Test name
Test status
Simulation time 304288045935 ps
CPU time 775.05 seconds
Started Nov 22 01:55:56 PM PST 23
Finished Nov 22 02:08:53 PM PST 23
Peak memory 205664 kb
Host smart-6cbf3869-b0e4-4c39-b566-8a6a358b4842
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2761069042983229808257807027921453033372364415218324679186252121463181922928 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build
_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.2761069042983229808257807027921453033372364415218324679186252121463181922928
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.91842805434044634699980754650956112491192222038341636408256389680710852397227
Short name T652
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.22 seconds
Started Nov 22 01:56:15 PM PST 23
Finished Nov 22 01:56:43 PM PST 23
Peak memory 203308 kb
Host smart-84a6590f-d390-4d09-a348-3bcff5c2ba35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91842805434044634699980754650956112491192222038341636408256389680710852397227 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.91842805434044634699980754650956112491192222038341636408256389680710852397227
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.99235051063961322001573791798670782165081910409873111231170522046476794268500
Short name T103
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.17 seconds
Started Nov 22 01:55:53 PM PST 23
Finished Nov 22 01:56:29 PM PST 23
Peak memory 203280 kb
Host smart-fac9e549-8394-4bee-a835-90d0680e989b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99235051063961322001573791798670782165081910409873111231170522046476794268500 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 0.xbar_error_random.99235051063961322001573791798670782165081910409873111231170522046476794268500
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.15900174861175835010409122862187735475981550886952795086580783627817198524959
Short name T250
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.93 seconds
Started Nov 22 01:56:10 PM PST 23
Finished Nov 22 01:56:48 PM PST 23
Peak memory 211464 kb
Host smart-bd626498-1541-4a1d-ae18-57a79697dc1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15900174861175835010409122862187735475981550886952795086580783627817198524959 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 0.xbar_random.15900174861175835010409122862187735475981550886952795086580783627817198524959
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.80802880724717385578299843581286118735055132749988638950622653209053557662489
Short name T774
Test name
Test status
Simulation time 188793233435 ps
CPU time 328.3 seconds
Started Nov 22 01:55:57 PM PST 23
Finished Nov 22 02:01:27 PM PST 23
Peak memory 204740 kb
Host smart-4bcae5d3-08e3-4bb2-b7d7-0c7686ad30e4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=80802880724717385578299843581286118735055132749988638950622653209053557662489 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 0.xbar_random_large_delays.80802880724717385578299843581286118735055132749988638950622653209053557662489
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.51910016406638195294955171115711270929608599717948222551264266562965211278556
Short name T679
Test name
Test status
Simulation time 126189108435 ps
CPU time 327 seconds
Started Nov 22 01:56:07 PM PST 23
Finished Nov 22 02:01:35 PM PST 23
Peak memory 211472 kb
Host smart-c735c895-ba81-4441-9b5a-1b64ee75dab6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=51910016406638195294955171115711270929608599717948222551264266562965211278556 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.51910016406638195294955171115711270929608599717948222551264266562965211278556
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.17354425523254313680639701987168070463623058697588805791174996586046113876272
Short name T659
Test name
Test status
Simulation time 766920935 ps
CPU time 24.55 seconds
Started Nov 22 01:56:07 PM PST 23
Finished Nov 22 01:56:33 PM PST 23
Peak memory 211336 kb
Host smart-1b30edfa-8c70-44cc-81dc-a19b71e6f4c2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17354425523254313680639701987168070463623058697588805791174996586046113876272 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.17354425523254313680639701987168070463623058697588805791174996586046113876272
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.6096718338878212109353155676203096200417504722164042580884856913591896043595
Short name T392
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.89 seconds
Started Nov 22 01:56:09 PM PST 23
Finished Nov 22 01:56:48 PM PST 23
Peak memory 204224 kb
Host smart-7419fbab-f9c0-4ee3-85ff-fd426dbd618f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6096718338878212109353155676203096200417504722164042580884856913591896043595 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 0.xbar_same_source.6096718338878212109353155676203096200417504722164042580884856913591896043595
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.9147652306005777674925673655269014208162070882158715099270051063694474559371
Short name T767
Test name
Test status
Simulation time 669983435 ps
CPU time 4.04 seconds
Started Nov 22 01:55:56 PM PST 23
Finished Nov 22 01:56:01 PM PST 23
Peak memory 203088 kb
Host smart-94ea4671-fac6-4c32-bcee-fafc505355f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=9147652306005777674925673655269014208162070882158715099270051063694474559371 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 0.xbar_smoke.9147652306005777674925673655269014208162070882158715099270051063694474559371
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.54538539418180014677426144339181015436734925114706925032831557249122268466719
Short name T445
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.38 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:43 PM PST 23
Peak memory 203268 kb
Host smart-d889f9da-e254-4c1f-98a8-ed9f40fec311
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=54538539418180014677426144339181015436734925114706925032831557249122268466719 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.54538539418180014677426144339181015436734925114706925032831557249122268466719
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.82541060527220389925131225140856701929472942602120052066976862680144629003175
Short name T135
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.56 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 01:57:03 PM PST 23
Peak memory 203236 kb
Host smart-c577f6c1-0cc8-4349-8f8f-6f33e54aafff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=82541060527220389925131225140856701929472942602120052066976862680144629003175 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.82541060527220389925131225140856701929472942602120052066976862680144629003175
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.77188789917176370966551179237129306991945625815948011067737483449224440489356
Short name T114
Test name
Test status
Simulation time 116233435 ps
CPU time 2.4 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:56:54 PM PST 23
Peak memory 203036 kb
Host smart-98d0ee95-6adf-43dd-9ca4-338ff32e42db
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77188789917176370966551179237129306991945625815948011067737483449224440489356 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.77188789917176370966551179237129306991945625815948011067737483449224440489356
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.88256318151082469643759781782813921998468903491125765925592580865507799641800
Short name T869
Test name
Test status
Simulation time 18904859184 ps
CPU time 136.16 seconds
Started Nov 22 01:56:06 PM PST 23
Finished Nov 22 01:58:23 PM PST 23
Peak memory 205776 kb
Host smart-3abb76cc-8041-484e-99bd-0553cc9725bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88256318151082469643759781782813921998468903491125765925592580865507799641800 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 0.xbar_stress_all.88256318151082469643759781782813921998468903491125765925592580865507799641800
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.42287666413360801361332160492913268433610248013696536651762031742915458212331
Short name T736
Test name
Test status
Simulation time 18894549184 ps
CPU time 116.61 seconds
Started Nov 22 01:56:21 PM PST 23
Finished Nov 22 01:58:19 PM PST 23
Peak memory 211416 kb
Host smart-3e271409-7d43-4256-a615-d25ace58a305
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=42287666413360801361332160492913268433610248013696536651762031742915458212331 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 0.xbar_stress_all_with_error.42287666413360801361332160492913268433610248013696536651762031742915458212331
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.91025517618114728079433652780058058658342440006711923461719610168900029182110
Short name T644
Test name
Test status
Simulation time 5188549184 ps
CPU time 295.27 seconds
Started Nov 22 01:56:15 PM PST 23
Finished Nov 22 02:01:12 PM PST 23
Peak memory 208464 kb
Host smart-624250d5-dac1-4b04-8eaa-64fbd37567f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91025517618114728079433652780058058658342440006711923461719610168900029182110 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.91025517618114728079433652780058058658342440006711923461719610168900029182110
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.69764675906328748191770967363463863863993764052610421502558258094290760671346
Short name T555
Test name
Test status
Simulation time 5188549184 ps
CPU time 226.67 seconds
Started Nov 22 01:56:16 PM PST 23
Finished Nov 22 02:00:04 PM PST 23
Peak memory 219636 kb
Host smart-fd274edd-6708-4d73-af76-970489e3981b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69764675906328748191770967363463863863993764052610421502558258094290760671346 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.69764675906328748191770967363463863863993764052610421502558258094290760671346
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.31928582222422718426637681150726737963318316001315090284215209799932398752404
Short name T417
Test name
Test status
Simulation time 3307045935 ps
CPU time 30.09 seconds
Started Nov 22 01:56:15 PM PST 23
Finished Nov 22 01:56:47 PM PST 23
Peak memory 211328 kb
Host smart-d2ca05c0-afcd-49cc-ba15-02adbfe6da38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31928582222422718426637681150726737963318316001315090284215209799932398752404 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 0.xbar_unmapped_addr.31928582222422718426637681150726737963318316001315090284215209799932398752404
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.65435869388575685718989904964446347295376002973357452256794652890812223983638
Short name T700
Test name
Test status
Simulation time 7399045935 ps
CPU time 72.51 seconds
Started Nov 22 01:56:21 PM PST 23
Finished Nov 22 01:57:35 PM PST 23
Peak memory 211480 kb
Host smart-8af3330d-446f-4bf7-a281-c5fe43a8a177
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65435869388575685718989904964446347295376002973357452256794652890812223983638 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.65435869388575685718989904964446347295376002973357452256794652890812223983638
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.75361177520538845950107820757170915082594039133966370956220345710828227156908
Short name T534
Test name
Test status
Simulation time 304288045935 ps
CPU time 765.94 seconds
Started Nov 22 01:56:18 PM PST 23
Finished Nov 22 02:09:06 PM PST 23
Peak memory 211388 kb
Host smart-1eb63a12-86d9-4f49-9f0d-e4cdee63bbd0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=75361177520538845950107820757170915082594039133966370956220345710828227156908 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.75361177520538845950107820757170915082594039133966370956220345710828227156908
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.93978652643094364423690873758919005676358980013070379132476464495781791854029
Short name T105
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.92 seconds
Started Nov 22 01:56:14 PM PST 23
Finished Nov 22 01:56:41 PM PST 23
Peak memory 203312 kb
Host smart-7996b339-0bda-49dd-8d8d-9b000289a9a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93978652643094364423690873758919005676358980013070379132476464495781791854029 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.93978652643094364423690873758919005676358980013070379132476464495781791854029
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.113126329115030122485808078026831736155336860357803339732111438420349282043118
Short name T176
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.14 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 01:56:55 PM PST 23
Peak memory 203072 kb
Host smart-07a4fde4-f981-4a60-9d42-9300a47b4416
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=113126329115030122485808078026831736155336860357803339732111438420349282043118 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_l
og /dev/null -cm_name 1.xbar_error_random.113126329115030122485808078026831736155336860357803339732111438420349282043118
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.95129921823190708525934112153765418336438101839911548003231519876500693390623
Short name T456
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.22 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 01:57:00 PM PST 23
Peak memory 211456 kb
Host smart-e590fd13-cd24-441d-8553-dc8346084ec7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95129921823190708525934112153765418336438101839911548003231519876500693390623 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 1.xbar_random.95129921823190708525934112153765418336438101839911548003231519876500693390623
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.110123692388472934018625924039802337550886154694425424930519168100591568122695
Short name T341
Test name
Test status
Simulation time 188793233435 ps
CPU time 331.24 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 02:01:52 PM PST 23
Peak memory 204812 kb
Host smart-4dec01f1-60d0-4d7e-81ed-7684f043a444
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=110123692388472934018625924039802337550886154694425424930519168100591568122695 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.110123692388472934018625924039802337550886154694425424930519168100591568122695
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.100027723229565831346508007929903344961123850724918739604169615060680094336260
Short name T364
Test name
Test status
Simulation time 126189108435 ps
CPU time 323.1 seconds
Started Nov 22 01:56:37 PM PST 23
Finished Nov 22 02:02:01 PM PST 23
Peak memory 211408 kb
Host smart-457e3ec4-e658-4c9f-b8f2-54167d843d99
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=100027723229565831346508007929903344961123850724918739604169615060680094336260 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.100027723229565831346508007929903344961123850724918739604169615060680094336260
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.58875960661700863770070733950969485363865868701307509983640046544411038284633
Short name T384
Test name
Test status
Simulation time 766920935 ps
CPU time 26.34 seconds
Started Nov 22 01:56:18 PM PST 23
Finished Nov 22 01:56:46 PM PST 23
Peak memory 211340 kb
Host smart-344995ac-de43-4844-9f9b-c469a3cde09e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58875960661700863770070733950969485363865868701307509983640046544411038284633 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.58875960661700863770070733950969485363865868701307509983640046544411038284633
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.13655952157055722699333874940925313980217604604054926343986933827274324599992
Short name T245
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.38 seconds
Started Nov 22 01:56:18 PM PST 23
Finished Nov 22 01:56:57 PM PST 23
Peak memory 204256 kb
Host smart-03680c08-32b2-4705-8b65-3b6c7c4ff462
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13655952157055722699333874940925313980217604604054926343986933827274324599992 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 1.xbar_same_source.13655952157055722699333874940925313980217604604054926343986933827274324599992
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.1845255050000719568980921017017463569575579002354924273854171345929716159975
Short name T353
Test name
Test status
Simulation time 669983435 ps
CPU time 3.94 seconds
Started Nov 22 01:56:13 PM PST 23
Finished Nov 22 01:56:18 PM PST 23
Peak memory 203028 kb
Host smart-78edfc6f-9d30-45b1-a25f-9b222126042d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1845255050000719568980921017017463569575579002354924273854171345929716159975 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 1.xbar_smoke.1845255050000719568980921017017463569575579002354924273854171345929716159975
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.7632239199356167138728225800545137823079344906681265217686990613671002817467
Short name T801
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.74 seconds
Started Nov 22 01:56:21 PM PST 23
Finished Nov 22 01:57:10 PM PST 23
Peak memory 203268 kb
Host smart-400f9d93-2140-439a-b5e1-9b0a429c64f9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=7632239199356167138728225800545137823079344906681265217686990613671002817467 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.7632239199356167138728225800545137823079344906681265217686990613671002817467
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.60875404126118125375185403435987865127556943116105029760348226729003207206512
Short name T823
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.52 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:57:06 PM PST 23
Peak memory 203276 kb
Host smart-85c1f45f-9d29-4921-addf-c950d34c266b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=60875404126118125375185403435987865127556943116105029760348226729003207206512 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.60875404126118125375185403435987865127556943116105029760348226729003207206512
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.95860954902898541312278415231199403678891824230305455279370350830597889065070
Short name T168
Test name
Test status
Simulation time 116233435 ps
CPU time 2.65 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 01:56:25 PM PST 23
Peak memory 203108 kb
Host smart-05c1c3c6-30bb-4285-9bf5-589b76daba47
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95860954902898541312278415231199403678891824230305455279370350830597889065070 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.95860954902898541312278415231199403678891824230305455279370350830597889065070
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.24111631342470018473874364809225199206522588642255886946308698571783021716261
Short name T230
Test name
Test status
Simulation time 18904859184 ps
CPU time 134.02 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 01:58:34 PM PST 23
Peak memory 205764 kb
Host smart-bd8ef28e-93b9-4144-92b1-8eba00d0d23d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24111631342470018473874364809225199206522588642255886946308698571783021716261 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 1.xbar_stress_all.24111631342470018473874364809225199206522588642255886946308698571783021716261
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.109921262673061018070528845926044134972523376535849364409994406920822989845868
Short name T875
Test name
Test status
Simulation time 18894549184 ps
CPU time 126.91 seconds
Started Nov 22 01:56:11 PM PST 23
Finished Nov 22 01:58:18 PM PST 23
Peak memory 211412 kb
Host smart-4a433f93-8934-4623-8227-a49957d95820
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=109921262673061018070528845926044134972523376535849364409994406920822989845868 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.109921262673061018070528845926044134972523376535849364409994406920822989845868
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.83871431353471420553757707694997311270529978204759555660610204919793313003421
Short name T446
Test name
Test status
Simulation time 5188549184 ps
CPU time 295.04 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 02:01:15 PM PST 23
Peak memory 208392 kb
Host smart-9daffb0a-d2fc-4e3a-aef7-7e792b6125cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83871431353471420553757707694997311270529978204759555660610204919793313003421 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.83871431353471420553757707694997311270529978204759555660610204919793313003421
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.92806598333125587747236098493585378682109016917867334258841958485317479317487
Short name T319
Test name
Test status
Simulation time 5188549184 ps
CPU time 224.66 seconds
Started Nov 22 01:56:21 PM PST 23
Finished Nov 22 02:00:07 PM PST 23
Peak memory 219648 kb
Host smart-0b684187-a443-4d5a-85b7-9ff2fb2cc92e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92806598333125587747236098493585378682109016917867334258841958485317479317487 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.92806598333125587747236098493585378682109016917867334258841958485317479317487
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.95073369399840431244752025235142589521138615028304417370840712660245795706998
Short name T507
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.68 seconds
Started Nov 22 01:56:09 PM PST 23
Finished Nov 22 01:56:39 PM PST 23
Peak memory 211344 kb
Host smart-b41845f2-87ef-4fa9-a9c0-852cc2869b04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95073369399840431244752025235142589521138615028304417370840712660245795706998 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 1.xbar_unmapped_addr.95073369399840431244752025235142589521138615028304417370840712660245795706998
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.65851896885927624527047480599430379440848479406458531759000923111835454064408
Short name T290
Test name
Test status
Simulation time 7399045935 ps
CPU time 65.16 seconds
Started Nov 22 01:56:50 PM PST 23
Finished Nov 22 01:57:56 PM PST 23
Peak memory 206340 kb
Host smart-84bf3ca2-1efe-48ba-ba2e-5abd6d67a96f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65851896885927624527047480599430379440848479406458531759000923111835454064408 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.65851896885927624527047480599430379440848479406458531759000923111835454064408
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.91298067219790459977208026222410078262582376792108129278828912287387187846809
Short name T695
Test name
Test status
Simulation time 304288045935 ps
CPU time 775.43 seconds
Started Nov 22 01:56:50 PM PST 23
Finished Nov 22 02:09:46 PM PST 23
Peak memory 211408 kb
Host smart-ae9bb5f0-4f37-4d65-a988-a8ecb8ace11d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=91298067219790459977208026222410078262582376792108129278828912287387187846809 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.91298067219790459977208026222410078262582376792108129278828912287387187846809
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.12243994920335717522364422923496534238215796711681442307092802176191769572190
Short name T375
Test name
Test status
Simulation time 3310545935 ps
CPU time 28.39 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:21 PM PST 23
Peak memory 203356 kb
Host smart-2d45362b-9cd1-4d47-9ff1-4437d55db2ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12243994920335717522364422923496534238215796711681442307092802176191769572190 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.12243994920335717522364422923496534238215796711681442307092802176191769572190
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.40065284502547000215165541787751702629585345404914563728929331290398246616420
Short name T782
Test name
Test status
Simulation time 4402420935 ps
CPU time 34.28 seconds
Started Nov 22 01:56:47 PM PST 23
Finished Nov 22 01:57:23 PM PST 23
Peak memory 203160 kb
Host smart-40b42c7d-f99a-4a1a-83fc-65ef45adf316
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40065284502547000215165541787751702629585345404914563728929331290398246616420 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 10.xbar_error_random.40065284502547000215165541787751702629585345404914563728929331290398246616420
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.57740467250841643782965725079168670531232186015268636436160873819231776158019
Short name T621
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.06 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:57:30 PM PST 23
Peak memory 211452 kb
Host smart-1dc79c9b-a533-47e1-bfd6-01d34037b316
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57740467250841643782965725079168670531232186015268636436160873819231776158019 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 10.xbar_random.57740467250841643782965725079168670531232186015268636436160873819231776158019
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.43841032169521913652872898542418077364844946929473053451059935539661973297403
Short name T787
Test name
Test status
Simulation time 188793233435 ps
CPU time 325.21 seconds
Started Nov 22 01:56:48 PM PST 23
Finished Nov 22 02:02:15 PM PST 23
Peak memory 204820 kb
Host smart-beaaa40c-d9b9-45af-8dd5-9e447acf443d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=43841032169521913652872898542418077364844946929473053451059935539661973297403 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 10.xbar_random_large_delays.43841032169521913652872898542418077364844946929473053451059935539661973297403
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.90074689899679291086251485051369828082804080588635822903328661492035631938922
Short name T830
Test name
Test status
Simulation time 126189108435 ps
CPU time 328.34 seconds
Started Nov 22 01:56:48 PM PST 23
Finished Nov 22 02:02:18 PM PST 23
Peak memory 211456 kb
Host smart-8fccd4fc-1de0-4ee7-8141-e8341779cc93
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=90074689899679291086251485051369828082804080588635822903328661492035631938922 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.90074689899679291086251485051369828082804080588635822903328661492035631938922
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.32812999532519737131431252946886911148905704273525204736677498165079394627497
Short name T237
Test name
Test status
Simulation time 766920935 ps
CPU time 27.63 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 01:57:26 PM PST 23
Peak memory 203852 kb
Host smart-31ce843c-8b11-44a1-952e-0bac33337bf8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32812999532519737131431252946886911148905704273525204736677498165079394627497 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.32812999532519737131431252946886911148905704273525204736677498165079394627497
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.115357944198964072245359727347641968537358172570057477857783618661532812746071
Short name T796
Test name
Test status
Simulation time 7116170935 ps
CPU time 35.02 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:30 PM PST 23
Peak memory 204320 kb
Host smart-5a33b821-d3a7-403e-91fb-579d4de1bed9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115357944198964072245359727347641968537358172570057477857783618661532812746071 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 10.xbar_same_source.115357944198964072245359727347641968537358172570057477857783618661532812746071
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.95647901042941735217776118429409262827684568834765656532883142009255882104335
Short name T541
Test name
Test status
Simulation time 669983435 ps
CPU time 4.38 seconds
Started Nov 22 01:56:42 PM PST 23
Finished Nov 22 01:56:48 PM PST 23
Peak memory 203160 kb
Host smart-6fbfd15d-671a-4d75-aa63-2e2ccda579f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95647901042941735217776118429409262827684568834765656532883142009255882104335 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 10.xbar_smoke.95647901042941735217776118429409262827684568834765656532883142009255882104335
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.84434419352448267327016708687491479929967913995886075114831537835512771291241
Short name T859
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.01 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 01:57:47 PM PST 23
Peak memory 203256 kb
Host smart-2630d9f2-2882-4b08-865b-ca361d94fc98
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=84434419352448267327016708687491479929967913995886075114831537835512771291241 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.84434419352448267327016708687491479929967913995886075114831537835512771291241
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.98594405612109098036040124425785016832853133236647947607940991729762245402868
Short name T638
Test name
Test status
Simulation time 17662295935 ps
CPU time 43.69 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:57:35 PM PST 23
Peak memory 203232 kb
Host smart-1082f110-6856-4065-b5b9-7f79a235daa1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=98594405612109098036040124425785016832853133236647947607940991729762245402868 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.98594405612109098036040124425785016832853133236647947607940991729762245402868
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.108991147500053602407291186580357922560004510782410593968122353953255828843481
Short name T581
Test name
Test status
Simulation time 116233435 ps
CPU time 2.55 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:56:55 PM PST 23
Peak memory 203044 kb
Host smart-f38f2d18-bf61-40c7-bbee-0a628d6df8d9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108991147500053602407291186580357922560004510782410593968122353953255828843481 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.108991147500053602407291186580357922560004510782410593968122353953255828843481
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.93883424601192550766759339834100177575968680600280671103793835793478132434169
Short name T517
Test name
Test status
Simulation time 18904859184 ps
CPU time 132.38 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 01:59:10 PM PST 23
Peak memory 205848 kb
Host smart-a06ec19c-2779-4914-94c4-f2aa5fd20821
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93883424601192550766759339834100177575968680600280671103793835793478132434169 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 10.xbar_stress_all.93883424601192550766759339834100177575968680600280671103793835793478132434169
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.73793140738309013719342951180041694262169197554946308844989995367909635669657
Short name T357
Test name
Test status
Simulation time 18894549184 ps
CPU time 125.71 seconds
Started Nov 22 01:56:42 PM PST 23
Finished Nov 22 01:58:50 PM PST 23
Peak memory 211436 kb
Host smart-ca8e146c-d3ef-476e-927b-59472b30bd30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73793140738309013719342951180041694262169197554946308844989995367909635669657 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 10.xbar_stress_all_with_error.73793140738309013719342951180041694262169197554946308844989995367909635669657
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.48209690045522830486989993068782667444684550054828607005662118946208760716268
Short name T795
Test name
Test status
Simulation time 5188549184 ps
CPU time 303.49 seconds
Started Nov 22 01:56:49 PM PST 23
Finished Nov 22 02:01:54 PM PST 23
Peak memory 208496 kb
Host smart-e99e5b39-ace2-461f-8a72-78ecfc407d3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48209690045522830486989993068782667444684550054828607005662118946208760716268 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.48209690045522830486989993068782667444684550054828607005662118946208760716268
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.55275586647900454623736062267247290523524229535831313557224676371451706221192
Short name T745
Test name
Test status
Simulation time 5188549184 ps
CPU time 229.24 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 02:00:48 PM PST 23
Peak memory 219604 kb
Host smart-25d56265-184c-457c-893e-e918956460d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55275586647900454623736062267247290523524229535831313557224676371451706221192 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.55275586647900454623736062267247290523524229535831313557224676371451706221192
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.62664176165282734711275747151033787922705606029504154013356970094794516006302
Short name T890
Test name
Test status
Simulation time 3307045935 ps
CPU time 30.47 seconds
Started Nov 22 01:56:42 PM PST 23
Finished Nov 22 01:57:13 PM PST 23
Peak memory 211460 kb
Host smart-a30805ef-5a38-423a-a0a7-2c21e01783e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62664176165282734711275747151033787922705606029504154013356970094794516006302 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 10.xbar_unmapped_addr.62664176165282734711275747151033787922705606029504154013356970094794516006302
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.106719019116086318266113951804381000304703050954422196598685477026924200191346
Short name T224
Test name
Test status
Simulation time 7399045935 ps
CPU time 64.95 seconds
Started Nov 22 01:56:47 PM PST 23
Finished Nov 22 01:57:53 PM PST 23
Peak memory 206248 kb
Host smart-ed4963c7-114c-4204-855e-3f6a0236f668
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=106719019116086318266113951804381000304703050954422196598685477026924200191346 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.106719019116086318266113951804381000304703050954422196598685477026924200191346
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.103215232451875133521031011540685179441249137396493568493405428882069867573490
Short name T159
Test name
Test status
Simulation time 304288045935 ps
CPU time 772.92 seconds
Started Nov 22 01:56:43 PM PST 23
Finished Nov 22 02:09:37 PM PST 23
Peak memory 211384 kb
Host smart-ccf72199-2c5d-4012-86a6-05d7cfa51bd9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=103215232451875133521031011540685179441249137396493568493405428882069867573490 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.103215232451875133521031011540685179441249137396493568493405428882069867573490
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.90789445655476455156552423993480590009125286834786274779539520201677429916957
Short name T648
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.37 seconds
Started Nov 22 01:56:48 PM PST 23
Finished Nov 22 01:57:16 PM PST 23
Peak memory 203132 kb
Host smart-a3203db6-fccd-47b0-9814-134ecb58b013
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=90789445655476455156552423993480590009125286834786274779539520201677429916957 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.90789445655476455156552423993480590009125286834786274779539520201677429916957
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.36548750673129615911175357618222791790040895244665335894778246769143522202276
Short name T148
Test name
Test status
Simulation time 4402420935 ps
CPU time 34.05 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:28 PM PST 23
Peak memory 203244 kb
Host smart-806eb700-5935-4817-b3c2-261a8fc7e4c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36548750673129615911175357618222791790040895244665335894778246769143522202276 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 11.xbar_error_random.36548750673129615911175357618222791790040895244665335894778246769143522202276
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.40597861170332207630173986060680472695821760965470244638784094195585461559149
Short name T49
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.8 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:29 PM PST 23
Peak memory 211464 kb
Host smart-94bc25a8-95cd-45e0-8a64-28b5d617fc0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40597861170332207630173986060680472695821760965470244638784094195585461559149 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 11.xbar_random.40597861170332207630173986060680472695821760965470244638784094195585461559149
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.83972673490389999379722028163006236815656587619607435982857793330532303078726
Short name T187
Test name
Test status
Simulation time 188793233435 ps
CPU time 324.92 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 02:02:22 PM PST 23
Peak memory 204824 kb
Host smart-df844de0-d347-48e7-b0df-b839ce31da18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=83972673490389999379722028163006236815656587619607435982857793330532303078726 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 11.xbar_random_large_delays.83972673490389999379722028163006236815656587619607435982857793330532303078726
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.81744020172692813950122595086691477225693923840343296464876891713603743937718
Short name T765
Test name
Test status
Simulation time 126189108435 ps
CPU time 324.5 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 02:02:18 PM PST 23
Peak memory 211384 kb
Host smart-71c06e2b-5e35-4e2c-83b3-7dc7e956ee8d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=81744020172692813950122595086691477225693923840343296464876891713603743937718 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.81744020172692813950122595086691477225693923840343296464876891713603743937718
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.66514630093502432324352361782884813285350457764641858104721564506587316162151
Short name T690
Test name
Test status
Simulation time 766920935 ps
CPU time 26.46 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:21 PM PST 23
Peak memory 203780 kb
Host smart-d2ea2230-c2f3-4520-9b75-6cc104657929
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66514630093502432324352361782884813285350457764641858104721564506587316162151 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.66514630093502432324352361782884813285350457764641858104721564506587316162151
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.104993956318074517511890340319129476831437540565227733236477411490161255233075
Short name T557
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.12 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:32 PM PST 23
Peak memory 204304 kb
Host smart-7a3f8bd0-430b-4796-baee-ee39b589e544
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104993956318074517511890340319129476831437540565227733236477411490161255233075 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 11.xbar_same_source.104993956318074517511890340319129476831437540565227733236477411490161255233075
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.108483265683016896821863186824642527046250477977569741193922901468081687027631
Short name T599
Test name
Test status
Simulation time 669983435 ps
CPU time 4.14 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 01:57:03 PM PST 23
Peak memory 203120 kb
Host smart-0aeb27df-5976-49ca-90ce-e7644bb965b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=108483265683016896821863186824642527046250477977569741193922901468081687027631 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 11.xbar_smoke.108483265683016896821863186824642527046250477977569741193922901468081687027631
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.53632843217655968172232757061853482905781701677059949999735532423108890364463
Short name T238
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.02 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:42 PM PST 23
Peak memory 203252 kb
Host smart-5c073cb6-f9e5-4c44-8d43-ae8863032cbf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=53632843217655968172232757061853482905781701677059949999735532423108890364463 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.53632843217655968172232757061853482905781701677059949999735532423108890364463
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.8067682493401338937038668425957286764133110385781387334336599164619962034909
Short name T807
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.92 seconds
Started Nov 22 01:56:45 PM PST 23
Finished Nov 22 01:57:31 PM PST 23
Peak memory 203276 kb
Host smart-f2cdba99-4974-4c2d-a792-cead67384176
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=8067682493401338937038668425957286764133110385781387334336599164619962034909 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.8067682493401338937038668425957286764133110385781387334336599164619962034909
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.25786578058649348779242973786760878476836805665651195866684537817007159526244
Short name T37
Test name
Test status
Simulation time 116233435 ps
CPU time 2.39 seconds
Started Nov 22 01:56:46 PM PST 23
Finished Nov 22 01:56:50 PM PST 23
Peak memory 203052 kb
Host smart-37a09c18-dbad-403e-a04a-78bc693958b0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25786578058649348779242973786760878476836805665651195866684537817007159526244 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.25786578058649348779242973786760878476836805665651195866684537817007159526244
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.93414591420101753374637533739050422330486221605628220474838954622437196829825
Short name T785
Test name
Test status
Simulation time 18904859184 ps
CPU time 137.65 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:59:09 PM PST 23
Peak memory 205844 kb
Host smart-1dd963c4-cf5a-486c-823f-4a1bdef60ca8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93414591420101753374637533739050422330486221605628220474838954622437196829825 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 11.xbar_stress_all.93414591420101753374637533739050422330486221605628220474838954622437196829825
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.29078217159214922219871168864977021660303265964138414100005514967808658350147
Short name T843
Test name
Test status
Simulation time 18894549184 ps
CPU time 125.55 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:58:57 PM PST 23
Peak memory 211488 kb
Host smart-3050c49d-f44e-4d4d-bd87-a7ee97906a63
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29078217159214922219871168864977021660303265964138414100005514967808658350147 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 11.xbar_stress_all_with_error.29078217159214922219871168864977021660303265964138414100005514967808658350147
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.42119764054063040731315294960698401079625974275698269687085996269026221819452
Short name T428
Test name
Test status
Simulation time 5188549184 ps
CPU time 300.4 seconds
Started Nov 22 01:56:42 PM PST 23
Finished Nov 22 02:01:44 PM PST 23
Peak memory 208528 kb
Host smart-98220e3f-9ffa-4246-af13-6c021ef44020
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=42119764054063040731315294960698401079625974275698269687085996269026221819452 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.42119764054063040731315294960698401079625974275698269687085996269026221819452
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.37001589256306933949628821260007790525371014627886101581766045477748115239920
Short name T385
Test name
Test status
Simulation time 5188549184 ps
CPU time 216.71 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 02:00:31 PM PST 23
Peak memory 219628 kb
Host smart-cd524a55-f140-4d49-94a9-a6ff3c3bdaf0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=37001589256306933949628821260007790525371014627886101581766045477748115239920 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.37001589256306933949628821260007790525371014627886101581766045477748115239920
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.87745601878795406224913242488826097260291843611057969738912143180283849243215
Short name T711
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.63 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:57:21 PM PST 23
Peak memory 211396 kb
Host smart-bcb6d786-965b-49ed-939f-4d180ba8471c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87745601878795406224913242488826097260291843611057969738912143180283849243215 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 11.xbar_unmapped_addr.87745601878795406224913242488826097260291843611057969738912143180283849243215
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.107954423285219588155169983360030980106233541012051398867039000808272321664064
Short name T80
Test name
Test status
Simulation time 7399045935 ps
CPU time 60.93 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:55 PM PST 23
Peak memory 206272 kb
Host smart-04cd1638-5679-4d70-9cf1-45717557248a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=107954423285219588155169983360030980106233541012051398867039000808272321664064 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.107954423285219588155169983360030980106233541012051398867039000808272321664064
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.58350593980720601241463698579279378747331422644083800331359741253502310854754
Short name T336
Test name
Test status
Simulation time 304288045935 ps
CPU time 748.1 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 02:09:27 PM PST 23
Peak memory 211404 kb
Host smart-85c3439e-0c54-4b03-9129-039146158898
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=58350593980720601241463698579279378747331422644083800331359741253502310854754 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.58350593980720601241463698579279378747331422644083800331359741253502310854754
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.84704956465445833839698429430500928415544866524344882395945541735485807053808
Short name T459
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.96 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:20 PM PST 23
Peak memory 203256 kb
Host smart-5489f61a-988b-4aa3-994b-8eb1b5cb9d8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=84704956465445833839698429430500928415544866524344882395945541735485807053808 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.84704956465445833839698429430500928415544866524344882395945541735485807053808
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.32630100649905585876981470720425903444470132408201478955800326311109317153686
Short name T490
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.62 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:57:33 PM PST 23
Peak memory 203056 kb
Host smart-d90d0481-1ab7-4f03-b905-4c9b64f2dbeb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32630100649905585876981470720425903444470132408201478955800326311109317153686 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 12.xbar_error_random.32630100649905585876981470720425903444470132408201478955800326311109317153686
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.15323307857486370528661307444414720832844931173649974934808753394717926043633
Short name T754
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.46 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 01:57:36 PM PST 23
Peak memory 211456 kb
Host smart-724ae417-4e70-46ac-a3cc-bfd37200f55b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15323307857486370528661307444414720832844931173649974934808753394717926043633 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 12.xbar_random.15323307857486370528661307444414720832844931173649974934808753394717926043633
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.99819877860919567036901618504849768796988950678218920526828485900265882513059
Short name T304
Test name
Test status
Simulation time 188793233435 ps
CPU time 330.45 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 02:02:22 PM PST 23
Peak memory 204820 kb
Host smart-85ed3e8d-421e-410e-801b-8a1e55c00aaa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=99819877860919567036901618504849768796988950678218920526828485900265882513059 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 12.xbar_random_large_delays.99819877860919567036901618504849768796988950678218920526828485900265882513059
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2740126131270223207096247036026693246253183761871375823392996652012828490021
Short name T127
Test name
Test status
Simulation time 126189108435 ps
CPU time 321.63 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 02:02:18 PM PST 23
Peak memory 211404 kb
Host smart-7018dafe-c2be-4385-968d-e2c5adb0dfa7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2740126131270223207096247036026693246253183761871375823392996652012828490021 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 12.xbar_random_slow_rsp.2740126131270223207096247036026693246253183761871375823392996652012828490021
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.115107527100974872959076942727215923325660586742576119840491992622267023331582
Short name T313
Test name
Test status
Simulation time 766920935 ps
CPU time 26.25 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:22 PM PST 23
Peak memory 203884 kb
Host smart-8756f1c3-e499-4020-b0eb-03859bc1111d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115107527100974872959076942727215923325660586742576119840491992622267023331582 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.115107527100974872959076942727215923325660586742576119840491992622267023331582
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.102963653037643048589817954627464080049132860901800123679058768894204318577646
Short name T193
Test name
Test status
Simulation time 7116170935 ps
CPU time 36.68 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 01:57:35 PM PST 23
Peak memory 204280 kb
Host smart-269bca9b-3922-4e73-bf2f-cc60664f8ac9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102963653037643048589817954627464080049132860901800123679058768894204318577646 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 12.xbar_same_source.102963653037643048589817954627464080049132860901800123679058768894204318577646
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.4666917201640313177313978453011929996915106063285249434032920413679056106455
Short name T530
Test name
Test status
Simulation time 669983435 ps
CPU time 4.26 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:56:57 PM PST 23
Peak memory 203104 kb
Host smart-980954b5-7533-47d5-b918-0c77c424de3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4666917201640313177313978453011929996915106063285249434032920413679056106455 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 12.xbar_smoke.4666917201640313177313978453011929996915106063285249434032920413679056106455
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.14456560967990380824198752049975464005761558433516427959978542400127406892803
Short name T153
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.39 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:57:47 PM PST 23
Peak memory 203272 kb
Host smart-5dcac6bb-f242-4ef4-b736-37ceefd2a9f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=14456560967990380824198752049975464005761558433516427959978542400127406892803 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.14456560967990380824198752049975464005761558433516427959978542400127406892803
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.46926129319706285199873140977338740284074438832642587946463545829147640412940
Short name T570
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.18 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:57:44 PM PST 23
Peak memory 203276 kb
Host smart-5b291bf8-ef67-4291-93e9-bceab073e576
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=46926129319706285199873140977338740284074438832642587946463545829147640412940 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.46926129319706285199873140977338740284074438832642587946463545829147640412940
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.66614087214172072796149127049215757144552262827948753954723322733291900646763
Short name T645
Test name
Test status
Simulation time 116233435 ps
CPU time 2.43 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:56:58 PM PST 23
Peak memory 203136 kb
Host smart-090ea134-08b6-4724-a8e9-98848275b284
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66614087214172072796149127049215757144552262827948753954723322733291900646763 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.66614087214172072796149127049215757144552262827948753954723322733291900646763
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.65739725636282909451417186402110243129214412802593983106197676963690847100117
Short name T50
Test name
Test status
Simulation time 18904859184 ps
CPU time 125.79 seconds
Started Nov 22 01:56:58 PM PST 23
Finished Nov 22 01:59:05 PM PST 23
Peak memory 205640 kb
Host smart-d1f754eb-83bf-45a6-b40c-24703e4a2baf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65739725636282909451417186402110243129214412802593983106197676963690847100117 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 12.xbar_stress_all.65739725636282909451417186402110243129214412802593983106197676963690847100117
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.54709343416737497570223685878697863115828979125408413053130901415345419811739
Short name T164
Test name
Test status
Simulation time 18894549184 ps
CPU time 126.33 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 01:59:03 PM PST 23
Peak memory 211364 kb
Host smart-80153e0e-8a6a-44f8-93c7-323d166e86b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54709343416737497570223685878697863115828979125408413053130901415345419811739 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 12.xbar_stress_all_with_error.54709343416737497570223685878697863115828979125408413053130901415345419811739
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.27203723235755092273818456606026599859387628935951425408421358544688643327666
Short name T692
Test name
Test status
Simulation time 5188549184 ps
CPU time 290.43 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 02:01:49 PM PST 23
Peak memory 208292 kb
Host smart-c7d4cdee-80ac-4d07-83b1-e3c80df8a53f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27203723235755092273818456606026599859387628935951425408421358544688643327666 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.27203723235755092273818456606026599859387628935951425408421358544688643327666
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.50395621010205478136485256689804000797080857620950560282003812413985836361382
Short name T646
Test name
Test status
Simulation time 5188549184 ps
CPU time 231.16 seconds
Started Nov 22 01:56:50 PM PST 23
Finished Nov 22 02:00:42 PM PST 23
Peak memory 219628 kb
Host smart-4f3fa1ca-4028-44f6-be3d-82eae57dd045
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=50395621010205478136485256689804000797080857620950560282003812413985836361382 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.50395621010205478136485256689804000797080857620950560282003812413985836361382
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.47297846075754569099487059376923972327276764724304041354320656112956747524193
Short name T556
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.52 seconds
Started Nov 22 01:56:58 PM PST 23
Finished Nov 22 01:57:29 PM PST 23
Peak memory 211192 kb
Host smart-7b1e7d76-213e-4a14-bc04-b669284a303f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47297846075754569099487059376923972327276764724304041354320656112956747524193 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 12.xbar_unmapped_addr.47297846075754569099487059376923972327276764724304041354320656112956747524193
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.26354708109231901782838952101731732130537430624108557613004612787207160576361
Short name T764
Test name
Test status
Simulation time 7399045935 ps
CPU time 59.08 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:54 PM PST 23
Peak memory 206288 kb
Host smart-e2aa314d-f03d-4b25-b1fb-5c474d25ebea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=26354708109231901782838952101731732130537430624108557613004612787207160576361 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.26354708109231901782838952101731732130537430624108557613004612787207160576361
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.37236956948771429504244910890286313383936743428719844539452030182738900380626
Short name T491
Test name
Test status
Simulation time 304288045935 ps
CPU time 756.97 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 02:09:35 PM PST 23
Peak memory 211376 kb
Host smart-a2034a42-f823-4ca2-9464-0718a35d826e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=37236956948771429504244910890286313383936743428719844539452030182738900380626 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.37236956948771429504244910890286313383936743428719844539452030182738900380626
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.22420342779726069334639970998861467258162340077805004700621066360603521888690
Short name T678
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.68 seconds
Started Nov 22 01:57:19 PM PST 23
Finished Nov 22 01:57:53 PM PST 23
Peak memory 203312 kb
Host smart-836a3a12-1ab8-41fc-ae17-c6ce1725dde9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22420342779726069334639970998861467258162340077805004700621066360603521888690 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.22420342779726069334639970998861467258162340077805004700621066360603521888690
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.9477436610165772246427456017597413727097880032744738947478153676769254322484
Short name T536
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.36 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:32 PM PST 23
Peak memory 203204 kb
Host smart-c3ca01b7-57dc-4579-8fd0-98597bfcfa0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=9477436610165772246427456017597413727097880032744738947478153676769254322484 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 13.xbar_error_random.9477436610165772246427456017597413727097880032744738947478153676769254322484
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.85785448955084446496850146044407832015167235013225093641726321217499461120061
Short name T609
Test name
Test status
Simulation time 4402420935 ps
CPU time 39.68 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:33 PM PST 23
Peak memory 211404 kb
Host smart-d34393e2-81bb-40ca-a894-127f579c988c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85785448955084446496850146044407832015167235013225093641726321217499461120061 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 13.xbar_random.85785448955084446496850146044407832015167235013225093641726321217499461120061
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.85444980016969472144557378474456016574925013196443344586604141423911976219893
Short name T65
Test name
Test status
Simulation time 188793233435 ps
CPU time 321.84 seconds
Started Nov 22 01:57:02 PM PST 23
Finished Nov 22 02:02:25 PM PST 23
Peak memory 204716 kb
Host smart-2ed6e496-4475-444c-8d97-b66ed4ba635e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=85444980016969472144557378474456016574925013196443344586604141423911976219893 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 13.xbar_random_large_delays.85444980016969472144557378474456016574925013196443344586604141423911976219893
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.37148420544699530564115956676023508240856893344758960402307394258305121508101
Short name T470
Test name
Test status
Simulation time 126189108435 ps
CPU time 324.24 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 02:02:19 PM PST 23
Peak memory 211352 kb
Host smart-16486bb7-d8ec-4b60-8a9f-b4a47cf460f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=37148420544699530564115956676023508240856893344758960402307394258305121508101 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.37148420544699530564115956676023508240856893344758960402307394258305121508101
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.6214342100678946633421938069131654391828039112372914582914393064428898588554
Short name T871
Test name
Test status
Simulation time 766920935 ps
CPU time 27.23 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:21 PM PST 23
Peak memory 211280 kb
Host smart-35cbdede-a8dc-4ebc-8e9e-ce09df0c577e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6214342100678946633421938069131654391828039112372914582914393064428898588554 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.6214342100678946633421938069131654391828039112372914582914393064428898588554
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.43136866984383995292400241428920577215229106237154481838384588548336463954839
Short name T602
Test name
Test status
Simulation time 7116170935 ps
CPU time 36.81 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:32 PM PST 23
Peak memory 204244 kb
Host smart-88781807-08ec-4c26-9084-c5a076e98f17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=43136866984383995292400241428920577215229106237154481838384588548336463954839 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 13.xbar_same_source.43136866984383995292400241428920577215229106237154481838384588548336463954839
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.83819966175072844096790018076520804724247301815921964051973496149618165747788
Short name T724
Test name
Test status
Simulation time 669983435 ps
CPU time 4.09 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:01 PM PST 23
Peak memory 203140 kb
Host smart-b7e6db0f-2283-4dbd-89a5-8fe7401679b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83819966175072844096790018076520804724247301815921964051973496149618165747788 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 13.xbar_smoke.83819966175072844096790018076520804724247301815921964051973496149618165747788
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.58072042274145240697509778218712658573478632409515857204842002795612286333879
Short name T597
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.16 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:57:48 PM PST 23
Peak memory 203172 kb
Host smart-00a873c0-b9ad-4952-bc26-82e7b65ac53b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=58072042274145240697509778218712658573478632409515857204842002795612286333879 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.58072042274145240697509778218712658573478632409515857204842002795612286333879
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2688095021816456563839310687717512216652058728870783880339281261457129584457
Short name T706
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.51 seconds
Started Nov 22 01:56:58 PM PST 23
Finished Nov 22 01:57:44 PM PST 23
Peak memory 203172 kb
Host smart-d108b826-93f4-4fe1-993d-f05e357c327b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2688095021816456563839310687717512216652058728870783880339281261457129584457 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2688095021816456563839310687717512216652058728870783880339281261457129584457
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.61847784788896224101670781501416986235080523381087425526866991942069113946498
Short name T2
Test name
Test status
Simulation time 116233435 ps
CPU time 2.56 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:56:58 PM PST 23
Peak memory 203068 kb
Host smart-9abb822f-7fea-4d8d-b212-2c0320b58ae3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61847784788896224101670781501416986235080523381087425526866991942069113946498 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.61847784788896224101670781501416986235080523381087425526866991942069113946498
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.99991589506031370408473013130202027206800654715472589579798086998059497263188
Short name T633
Test name
Test status
Simulation time 18904859184 ps
CPU time 134.27 seconds
Started Nov 22 01:57:25 PM PST 23
Finished Nov 22 01:59:41 PM PST 23
Peak memory 205796 kb
Host smart-2e003d2a-68e2-4b30-b867-ff51372ee7df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99991589506031370408473013130202027206800654715472589579798086998059497263188 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 13.xbar_stress_all.99991589506031370408473013130202027206800654715472589579798086998059497263188
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.32685151451089604983081009426115576951301508772785432736528768844016452265664
Short name T624
Test name
Test status
Simulation time 18894549184 ps
CPU time 126.98 seconds
Started Nov 22 01:57:10 PM PST 23
Finished Nov 22 01:59:19 PM PST 23
Peak memory 211404 kb
Host smart-35e9e60a-3d68-4fba-9746-1d402f7b6e1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32685151451089604983081009426115576951301508772785432736528768844016452265664 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 13.xbar_stress_all_with_error.32685151451089604983081009426115576951301508772785432736528768844016452265664
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.28533201266073356091478849791503476152307323999857494588362329863703422611860
Short name T170
Test name
Test status
Simulation time 5188549184 ps
CPU time 291.5 seconds
Started Nov 22 01:57:06 PM PST 23
Finished Nov 22 02:01:58 PM PST 23
Peak memory 208508 kb
Host smart-186a4d29-3d2e-403a-9c59-dfcffe35bc3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28533201266073356091478849791503476152307323999857494588362329863703422611860 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.28533201266073356091478849791503476152307323999857494588362329863703422611860
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.63380121682986066472044723727662105394713999077655327663000699932874013125926
Short name T773
Test name
Test status
Simulation time 5188549184 ps
CPU time 232.7 seconds
Started Nov 22 01:57:11 PM PST 23
Finished Nov 22 02:01:05 PM PST 23
Peak memory 219516 kb
Host smart-b2fd1203-a726-476f-94c2-b0918db95664
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=63380121682986066472044723727662105394713999077655327663000699932874013125926 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.63380121682986066472044723727662105394713999077655327663000699932874013125926
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.36828621066659952159384150060982625602035433345175700913294276201734388874207
Short name T389
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.68 seconds
Started Nov 22 01:57:13 PM PST 23
Finished Nov 22 01:57:50 PM PST 23
Peak memory 211424 kb
Host smart-dce9068f-616e-4aaf-9091-a36345de6990
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36828621066659952159384150060982625602035433345175700913294276201734388874207 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 13.xbar_unmapped_addr.36828621066659952159384150060982625602035433345175700913294276201734388874207
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.113031515391818954326077712285403562053363239821674214214416368354888995789321
Short name T81
Test name
Test status
Simulation time 7399045935 ps
CPU time 61 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:57 PM PST 23
Peak memory 206404 kb
Host smart-9d007026-544e-4262-87aa-91ba9cafb533
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=113031515391818954326077712285403562053363239821674214214416368354888995789321 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.113031515391818954326077712285403562053363239821674214214416368354888995789321
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.13651816848958282404132800034399447461666914237956398975015818440489711134594
Short name T67
Test name
Test status
Simulation time 304288045935 ps
CPU time 773.31 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 02:09:46 PM PST 23
Peak memory 211432 kb
Host smart-eca7fd20-984e-4d88-9737-8d8314dfb793
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=13651816848958282404132800034399447461666914237956398975015818440489711134594 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.13651816848958282404132800034399447461666914237956398975015818440489711134594
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.81415958176557290259104554881615128611713702785506507207720306114759798095834
Short name T733
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.63 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:57:19 PM PST 23
Peak memory 203288 kb
Host smart-6570a127-e461-41e9-ad3e-3eb9cd74470d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81415958176557290259104554881615128611713702785506507207720306114759798095834 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.81415958176557290259104554881615128611713702785506507207720306114759798095834
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.34682342655073822854888210928298762114022448874475791593379019066786330560305
Short name T821
Test name
Test status
Simulation time 4402420935 ps
CPU time 32.99 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:27 PM PST 23
Peak memory 203276 kb
Host smart-b43b2b5c-b953-48f7-91e2-42abac95efc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34682342655073822854888210928298762114022448874475791593379019066786330560305 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 14.xbar_error_random.34682342655073822854888210928298762114022448874475791593379019066786330560305
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.17732852291298085292411020428456809874948328747374544567864619068171277763294
Short name T863
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.42 seconds
Started Nov 22 01:56:48 PM PST 23
Finished Nov 22 01:57:25 PM PST 23
Peak memory 211476 kb
Host smart-cce6a27e-4ddf-4a37-bb66-00a1f6b6b420
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=17732852291298085292411020428456809874948328747374544567864619068171277763294 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 14.xbar_random.17732852291298085292411020428456809874948328747374544567864619068171277763294
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.7605868567997318524665388995401467797957202233604644499717061780141913917424
Short name T66
Test name
Test status
Simulation time 188793233435 ps
CPU time 323.34 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 02:02:19 PM PST 23
Peak memory 204764 kb
Host smart-6d2c12f6-e8e9-40f6-8556-0cf77a9ccb14
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=7605868567997318524665388995401467797957202233604644499717061780141913917424 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 14.xbar_random_large_delays.7605868567997318524665388995401467797957202233604644499717061780141913917424
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.36014558890066552618135682639669850082196948303361599288731841887684229238836
Short name T203
Test name
Test status
Simulation time 126189108435 ps
CPU time 318.23 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 02:02:12 PM PST 23
Peak memory 211516 kb
Host smart-7f27e533-e52b-44ed-a4c0-0ead02056288
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=36014558890066552618135682639669850082196948303361599288731841887684229238836 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.36014558890066552618135682639669850082196948303361599288731841887684229238836
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.68066028832604567487356693916337492383393188060818034665662836482868828263747
Short name T448
Test name
Test status
Simulation time 766920935 ps
CPU time 25.14 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:18 PM PST 23
Peak memory 203816 kb
Host smart-5e3a7a91-9068-47e0-96fd-a950776705de
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68066028832604567487356693916337492383393188060818034665662836482868828263747 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.68066028832604567487356693916337492383393188060818034665662836482868828263747
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.100083042335552804081264096918347299245464985652789438891017438752986902206438
Short name T462
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.58 seconds
Started Nov 22 01:56:50 PM PST 23
Finished Nov 22 01:57:29 PM PST 23
Peak memory 204372 kb
Host smart-c77efbeb-5010-4b3e-8c47-72613ed2472e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100083042335552804081264096918347299245464985652789438891017438752986902206438 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 14.xbar_same_source.100083042335552804081264096918347299245464985652789438891017438752986902206438
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.28545685761903300034160883287178890533146060139861861485566318477642825131988
Short name T331
Test name
Test status
Simulation time 669983435 ps
CPU time 4.21 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:56:58 PM PST 23
Peak memory 203104 kb
Host smart-2d7c676a-1e02-4427-8d72-06a3a80417f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28545685761903300034160883287178890533146060139861861485566318477642825131988 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 14.xbar_smoke.28545685761903300034160883287178890533146060139861861485566318477642825131988
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.114658824337720165410085028064698664479711571194662629394119546789278518102609
Short name T884
Test name
Test status
Simulation time 28419483435 ps
CPU time 49.32 seconds
Started Nov 22 01:57:11 PM PST 23
Finished Nov 22 01:58:02 PM PST 23
Peak memory 203248 kb
Host smart-875af117-5d83-4cce-b4e6-e5889485ff64
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=114658824337720165410085028064698664479711571194662629394119546789278518102609 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.114658824337720165410085028064698664479711571194662629394119546789278518102609
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.47096051602614934553243049260945785653889472573716205112532687303190545699673
Short name T854
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.9 seconds
Started Nov 22 01:57:11 PM PST 23
Finished Nov 22 01:58:03 PM PST 23
Peak memory 203292 kb
Host smart-1edd457c-44de-44f5-9628-43aa6d307ee7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=47096051602614934553243049260945785653889472573716205112532687303190545699673 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.47096051602614934553243049260945785653889472573716205112532687303190545699673
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.37332301413028734692896445438501089643110159513247721449388366826652109619739
Short name T509
Test name
Test status
Simulation time 116233435 ps
CPU time 2.41 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:56:57 PM PST 23
Peak memory 202896 kb
Host smart-f7c5e2cc-7c8f-43ae-8d0e-310cd6a32f5e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37332301413028734692896445438501089643110159513247721449388366826652109619739 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.37332301413028734692896445438501089643110159513247721449388366826652109619739
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.78910584591556405364508244673416404359194010791896456132833453137625384154507
Short name T867
Test name
Test status
Simulation time 18904859184 ps
CPU time 129.75 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:59:02 PM PST 23
Peak memory 205804 kb
Host smart-93be3334-a722-4c75-97cb-bfe890d38557
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78910584591556405364508244673416404359194010791896456132833453137625384154507 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 14.xbar_stress_all.78910584591556405364508244673416404359194010791896456132833453137625384154507
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.91659134615519823446427685384604734035014727026579105890828515478368284934366
Short name T704
Test name
Test status
Simulation time 18894549184 ps
CPU time 127.68 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 01:59:05 PM PST 23
Peak memory 211444 kb
Host smart-a9033385-892c-4ff6-b479-f48fa2d76a88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91659134615519823446427685384604734035014727026579105890828515478368284934366 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 14.xbar_stress_all_with_error.91659134615519823446427685384604734035014727026579105890828515478368284934366
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.105181078477185941129920671126219644438299842024795715851637261028517968608415
Short name T492
Test name
Test status
Simulation time 5188549184 ps
CPU time 225.05 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 02:00:41 PM PST 23
Peak memory 219624 kb
Host smart-fc1d45b5-4b12-4880-97fc-51d1f28d8948
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105181078477185941129920671126219644438299842024795715851637261028517968608415 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.105181078477185941129920671126219644438299842024795715851637261028517968608415
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.62306733912783213747934532444838155313981092737222660186846907006359034234112
Short name T257
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.99 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:24 PM PST 23
Peak memory 211464 kb
Host smart-cd4f1ccd-b998-40f7-9a08-ab36525b3da7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62306733912783213747934532444838155313981092737222660186846907006359034234112 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 14.xbar_unmapped_addr.62306733912783213747934532444838155313981092737222660186846907006359034234112
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.102528570068318718468143666867071478820329635129186269029951804732693368082490
Short name T569
Test name
Test status
Simulation time 7399045935 ps
CPU time 62.15 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:58 PM PST 23
Peak memory 206284 kb
Host smart-fd0c1334-1f5b-4163-81dd-ca1f7cee73e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102528570068318718468143666867071478820329635129186269029951804732693368082490 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.102528570068318718468143666867071478820329635129186269029951804732693368082490
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.49065822608836542712917590479979152096790830886210655683743759984709534187657
Short name T227
Test name
Test status
Simulation time 304288045935 ps
CPU time 760.17 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 02:09:39 PM PST 23
Peak memory 211428 kb
Host smart-51246899-ed63-4a2b-9688-fd571365612e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=49065822608836542712917590479979152096790830886210655683743759984709534187657 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.49065822608836542712917590479979152096790830886210655683743759984709534187657
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.6914149910411011422978746796345605787445573543775791638151319054887678004302
Short name T282
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.76 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:20 PM PST 23
Peak memory 203216 kb
Host smart-7e552444-4136-4fe8-a960-22b76e579c5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6914149910411011422978746796345605787445573543775791638151319054887678004302 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.6914149910411011422978746796345605787445573543775791638151319054887678004302
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.73484946944877133837010274357923941512011813245877908615496621750126347602830
Short name T500
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.54 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:29 PM PST 23
Peak memory 203340 kb
Host smart-66efd1a5-e4d8-41b3-bcc9-c719a3d1e9ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73484946944877133837010274357923941512011813245877908615496621750126347602830 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 15.xbar_error_random.73484946944877133837010274357923941512011813245877908615496621750126347602830
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.65967420207295845967760229798662031545993234830520618744216261533128913966423
Short name T756
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.23 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:57:27 PM PST 23
Peak memory 211508 kb
Host smart-72da5530-6fa3-4a9f-99ee-6f861e9d2817
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65967420207295845967760229798662031545993234830520618744216261533128913966423 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 15.xbar_random.65967420207295845967760229798662031545993234830520618744216261533128913966423
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.72980296617240827406272736302501809145584179033805938519477617881648313208088
Short name T552
Test name
Test status
Simulation time 188793233435 ps
CPU time 326.28 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 02:02:22 PM PST 23
Peak memory 204812 kb
Host smart-25b3dd57-fd87-47cb-9fcd-5ad9f9e7f498
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=72980296617240827406272736302501809145584179033805938519477617881648313208088 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 15.xbar_random_large_delays.72980296617240827406272736302501809145584179033805938519477617881648313208088
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.18637320833247805558699519297832024204670745258010915005992024853730995871244
Short name T396
Test name
Test status
Simulation time 126189108435 ps
CPU time 318.3 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 02:02:16 PM PST 23
Peak memory 211448 kb
Host smart-81c65462-aa3f-4916-b208-b5485dc7f9ea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=18637320833247805558699519297832024204670745258010915005992024853730995871244 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.18637320833247805558699519297832024204670745258010915005992024853730995871244
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.70751198548631751151612814852426276485087691060089490726528930692726707605275
Short name T841
Test name
Test status
Simulation time 766920935 ps
CPU time 25.72 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:18 PM PST 23
Peak memory 203836 kb
Host smart-f6c9624d-adc2-4bfa-9461-554e27d30029
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70751198548631751151612814852426276485087691060089490726528930692726707605275 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.70751198548631751151612814852426276485087691060089490726528930692726707605275
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.35099298033485883651229757702084279530693783956040256710145065278983916653554
Short name T143
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.02 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:33 PM PST 23
Peak memory 204240 kb
Host smart-405b539a-1486-4d58-92ca-3d287824d070
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35099298033485883651229757702084279530693783956040256710145065278983916653554 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 15.xbar_same_source.35099298033485883651229757702084279530693783956040256710145065278983916653554
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.89508454545252253090821407009172108298215491227928557547445636121942658114873
Short name T173
Test name
Test status
Simulation time 669983435 ps
CPU time 4.14 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:00 PM PST 23
Peak memory 203204 kb
Host smart-b0a4d2c5-c5c4-46a0-b593-4143b5f84559
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89508454545252253090821407009172108298215491227928557547445636121942658114873 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 15.xbar_smoke.89508454545252253090821407009172108298215491227928557547445636121942658114873
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.59105127115688268613861166525863237187533142314395494408382062329636798300808
Short name T753
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.31 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:44 PM PST 23
Peak memory 203208 kb
Host smart-e3342518-d7e0-472e-81c1-e00b85b1c2fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=59105127115688268613861166525863237187533142314395494408382062329636798300808 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.59105127115688268613861166525863237187533142314395494408382062329636798300808
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.77450743148381157592074640481110675431643701219209079884847620792898472414150
Short name T242
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.56 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:57:37 PM PST 23
Peak memory 203176 kb
Host smart-055008ee-4182-40ca-8128-3f465c4fc50b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=77450743148381157592074640481110675431643701219209079884847620792898472414150 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.77450743148381157592074640481110675431643701219209079884847620792898472414150
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.95403270660602572907893706890345478578198577961584067877020036576064441525644
Short name T411
Test name
Test status
Simulation time 116233435 ps
CPU time 2.58 seconds
Started Nov 22 01:56:49 PM PST 23
Finished Nov 22 01:56:53 PM PST 23
Peak memory 203124 kb
Host smart-5a2943c5-08a2-43f3-8795-be1304cb83c8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95403270660602572907893706890345478578198577961584067877020036576064441525644 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.95403270660602572907893706890345478578198577961584067877020036576064441525644
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.5664031388044507506254130510497095692269090525451169116587560608276914149582
Short name T59
Test name
Test status
Simulation time 18904859184 ps
CPU time 129.21 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:59:01 PM PST 23
Peak memory 205808 kb
Host smart-9f7ac23f-d73a-4e18-8fa3-a0699a98e97f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5664031388044507506254130510497095692269090525451169116587560608276914149582 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_
log /dev/null -cm_name 15.xbar_stress_all.5664031388044507506254130510497095692269090525451169116587560608276914149582
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.32589517336843341551072943816369756934597146756086376859710437778259399332609
Short name T359
Test name
Test status
Simulation time 18894549184 ps
CPU time 115.73 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 01:58:54 PM PST 23
Peak memory 211436 kb
Host smart-8fa90bdb-a0ef-4855-bfd2-4da69df7446f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32589517336843341551072943816369756934597146756086376859710437778259399332609 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 15.xbar_stress_all_with_error.32589517336843341551072943816369756934597146756086376859710437778259399332609
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.102968612699943436391344751593917944966593094025010387311764051186949534595365
Short name T186
Test name
Test status
Simulation time 5188549184 ps
CPU time 290.62 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 02:01:45 PM PST 23
Peak memory 208536 kb
Host smart-b941dc85-bc9f-4613-8d3d-ca2c09995009
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102968612699943436391344751593917944966593094025010387311764051186949534595365 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.102968612699943436391344751593917944966593094025010387311764051186949534595365
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.52741280240303355808819004926320366011017040032315331589373931241646230227895
Short name T898
Test name
Test status
Simulation time 5188549184 ps
CPU time 227.61 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 02:00:41 PM PST 23
Peak memory 219420 kb
Host smart-a4be919e-efe6-47d8-8b46-a2dbe2ba9aff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=52741280240303355808819004926320366011017040032315331589373931241646230227895 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.52741280240303355808819004926320366011017040032315331589373931241646230227895
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.50615278803620643090074995910508976035327204742286286390664862563511063082108
Short name T504
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.56 seconds
Started Nov 22 01:56:49 PM PST 23
Finished Nov 22 01:57:18 PM PST 23
Peak memory 211384 kb
Host smart-485746e7-12eb-4e76-9a27-9df93988ec2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=50615278803620643090074995910508976035327204742286286390664862563511063082108 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 15.xbar_unmapped_addr.50615278803620643090074995910508976035327204742286286390664862563511063082108
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.84362495310378559491079735953814955672752502446272847097810796497333965691324
Short name T894
Test name
Test status
Simulation time 7399045935 ps
CPU time 68.32 seconds
Started Nov 22 01:56:49 PM PST 23
Finished Nov 22 01:57:58 PM PST 23
Peak memory 206292 kb
Host smart-2444faf7-4242-48e0-be8a-8ba119363d48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=84362495310378559491079735953814955672752502446272847097810796497333965691324 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.84362495310378559491079735953814955672752502446272847097810796497333965691324
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.8549008155829721071762266746066260060741346472804485683094058856087715045605
Short name T397
Test name
Test status
Simulation time 304288045935 ps
CPU time 778.22 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 02:09:55 PM PST 23
Peak memory 211360 kb
Host smart-fb1e0f21-caab-4e81-9c9b-f8a98b34a386
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=8549008155829721071762266746066260060741346472804485683094058856087715045605 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build
_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.8549008155829721071762266746066260060741346472804485683094058856087715045605
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.24938738140113170697044293697318923835496489333082176429343354405655278387394
Short name T158
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.16 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:57:18 PM PST 23
Peak memory 203320 kb
Host smart-1c69ee36-9676-4ae9-a5d8-f4aa9f4d07f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24938738140113170697044293697318923835496489333082176429343354405655278387394 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.24938738140113170697044293697318923835496489333082176429343354405655278387394
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.20524278529835652366636277029579754425371669984434983587600278105662054198629
Short name T239
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.98 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:29 PM PST 23
Peak memory 202644 kb
Host smart-acbcffe3-219e-4f78-a81f-a93d94472194
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20524278529835652366636277029579754425371669984434983587600278105662054198629 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 16.xbar_error_random.20524278529835652366636277029579754425371669984434983587600278105662054198629
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.57818929291764367280040138882920223714983985417200617451010595764916423670547
Short name T607
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.86 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:57:36 PM PST 23
Peak memory 211244 kb
Host smart-57d14c30-aba2-4153-b5a0-db8dd42799de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57818929291764367280040138882920223714983985417200617451010595764916423670547 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 16.xbar_random.57818929291764367280040138882920223714983985417200617451010595764916423670547
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.112967074384886276975205778764970832164625293079955348544701504725001610005122
Short name T608
Test name
Test status
Simulation time 188793233435 ps
CPU time 320.35 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 02:02:20 PM PST 23
Peak memory 204732 kb
Host smart-d99c685b-bae8-4c58-9977-16ce72e462e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=112967074384886276975205778764970832164625293079955348544701504725001610005122 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.112967074384886276975205778764970832164625293079955348544701504725001610005122
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.84654374078421760604818263570975264275648209030531212198150832643892144283080
Short name T699
Test name
Test status
Simulation time 126189108435 ps
CPU time 326.99 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 02:02:20 PM PST 23
Peak memory 211396 kb
Host smart-10a85167-202c-48cb-8d2f-01c8b8cd9a65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=84654374078421760604818263570975264275648209030531212198150832643892144283080 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.84654374078421760604818263570975264275648209030531212198150832643892144283080
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.115719263562496753835588685529192292086856091269084552637281333205480516006913
Short name T614
Test name
Test status
Simulation time 766920935 ps
CPU time 25.05 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:57:24 PM PST 23
Peak memory 203620 kb
Host smart-1829cde7-c852-427e-b5ee-62c3b1b77861
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115719263562496753835588685529192292086856091269084552637281333205480516006913 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.115719263562496753835588685529192292086856091269084552637281333205480516006913
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.23285932221630957898997442821236257695200366403213838594412857650522285463599
Short name T5
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.27 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:34 PM PST 23
Peak memory 204304 kb
Host smart-65db20a1-962b-4b5d-9ded-0fa34d20728a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23285932221630957898997442821236257695200366403213838594412857650522285463599 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 16.xbar_same_source.23285932221630957898997442821236257695200366403213838594412857650522285463599
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.64397626587734516029399051522005385608663757060754421525435295747685645034306
Short name T592
Test name
Test status
Simulation time 669983435 ps
CPU time 4.13 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:56:57 PM PST 23
Peak memory 202936 kb
Host smart-193a4198-05c8-479c-9cd9-333ccc249978
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64397626587734516029399051522005385608663757060754421525435295747685645034306 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 16.xbar_smoke.64397626587734516029399051522005385608663757060754421525435295747685645034306
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.21172470307239049292980424378773908304976223206748217358275484304577663998011
Short name T667
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.85 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:44 PM PST 23
Peak memory 203164 kb
Host smart-e4ab8cff-74b2-4abc-a187-fb2c82d1cf28
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=21172470307239049292980424378773908304976223206748217358275484304577663998011 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.21172470307239049292980424378773908304976223206748217358275484304577663998011
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.77155824684318998161430542408697542745346860569514774619284678515238188990520
Short name T847
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.89 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 01:57:43 PM PST 23
Peak memory 203236 kb
Host smart-8d6f102c-30f7-46bc-81f4-71d045c59f24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=77155824684318998161430542408697542745346860569514774619284678515238188990520 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.77155824684318998161430542408697542745346860569514774619284678515238188990520
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.48571243805167264976226904755817707085196638487673534518334004312767241135502
Short name T605
Test name
Test status
Simulation time 116233435 ps
CPU time 2.57 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:56:56 PM PST 23
Peak memory 203160 kb
Host smart-1148f189-9527-4a5c-b596-2ce7b747d74a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48571243805167264976226904755817707085196638487673534518334004312767241135502 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.48571243805167264976226904755817707085196638487673534518334004312767241135502
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.41873720189403324378834711737970048118461468784386910645926972788923199549987
Short name T317
Test name
Test status
Simulation time 18904859184 ps
CPU time 131.17 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:59:05 PM PST 23
Peak memory 205828 kb
Host smart-428b740f-8559-484f-8264-1508d3b600d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41873720189403324378834711737970048118461468784386910645926972788923199549987 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 16.xbar_stress_all.41873720189403324378834711737970048118461468784386910645926972788923199549987
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.49088047314907760775223641911257448982217675400673278431973146980675808485604
Short name T338
Test name
Test status
Simulation time 5188549184 ps
CPU time 299.54 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 02:01:55 PM PST 23
Peak memory 208300 kb
Host smart-4d3320a4-28b0-4f26-9a1c-afa93e4023b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49088047314907760775223641911257448982217675400673278431973146980675808485604 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.49088047314907760775223641911257448982217675400673278431973146980675808485604
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.66818705621720238470392882461656569560305560952909764421762556162585147145404
Short name T532
Test name
Test status
Simulation time 5188549184 ps
CPU time 226.16 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 02:00:38 PM PST 23
Peak memory 219624 kb
Host smart-4d7d8585-706d-4da8-9099-8e9e107e4733
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66818705621720238470392882461656569560305560952909764421762556162585147145404 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.66818705621720238470392882461656569560305560952909764421762556162585147145404
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.3444332943955850825688674205371553587281084967194339929927642624433303155816
Short name T591
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.49 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:23 PM PST 23
Peak memory 211344 kb
Host smart-c5422e6a-586a-4283-a3ff-796688a46a75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3444332943955850825688674205371553587281084967194339929927642624433303155816 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3444332943955850825688674205371553587281084967194339929927642624433303155816
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.69718051052823339281115588418969437146709599170022213037647867669128855014603
Short name T770
Test name
Test status
Simulation time 7399045935 ps
CPU time 59.63 seconds
Started Nov 22 01:56:49 PM PST 23
Finished Nov 22 01:57:50 PM PST 23
Peak memory 206284 kb
Host smart-706b04c3-1ea2-4461-9470-394c94b70cd0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69718051052823339281115588418969437146709599170022213037647867669128855014603 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.69718051052823339281115588418969437146709599170022213037647867669128855014603
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.5874677144381630370220890753721995107186265150277687493591406867560640027695
Short name T286
Test name
Test status
Simulation time 304288045935 ps
CPU time 794.98 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 02:10:12 PM PST 23
Peak memory 211484 kb
Host smart-be767529-41c0-48b5-994f-e8cc1585e365
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=5874677144381630370220890753721995107186265150277687493591406867560640027695 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build
_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.5874677144381630370220890753721995107186265150277687493591406867560640027695
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2676514492623535336015615357872799341876593937452482775323205904558297452581
Short name T606
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.91 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:19 PM PST 23
Peak memory 203356 kb
Host smart-e62aff95-79a8-4ed8-a00b-7b2c089895ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2676514492623535336015615357872799341876593937452482775323205904558297452581 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2676514492623535336015615357872799341876593937452482775323205904558297452581
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.110679144575207393137972831349875226969114517209916973446055439056610346248215
Short name T377
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.65 seconds
Started Nov 22 01:56:50 PM PST 23
Finished Nov 22 01:57:28 PM PST 23
Peak memory 203292 kb
Host smart-074d53a6-551a-46f3-a42b-02be34fb3bd9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110679144575207393137972831349875226969114517209916973446055439056610346248215 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_l
og /dev/null -cm_name 17.xbar_error_random.110679144575207393137972831349875226969114517209916973446055439056610346248215
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.4003176201612578365813536902031068371355076103830840762677132688455484969193
Short name T852
Test name
Test status
Simulation time 4402420935 ps
CPU time 40.66 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:37 PM PST 23
Peak memory 211452 kb
Host smart-2efd9a07-4c2d-463a-a532-a75d748e3d0a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4003176201612578365813536902031068371355076103830840762677132688455484969193 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 17.xbar_random.4003176201612578365813536902031068371355076103830840762677132688455484969193
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.52077542968109129290761497347397881387770945939661808549811058616323946154996
Short name T343
Test name
Test status
Simulation time 188793233435 ps
CPU time 326.7 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 02:02:22 PM PST 23
Peak memory 204748 kb
Host smart-bc1b1124-c91c-44d0-a7fa-25a839309d3a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=52077542968109129290761497347397881387770945939661808549811058616323946154996 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 17.xbar_random_large_delays.52077542968109129290761497347397881387770945939661808549811058616323946154996
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.29845429821340475148397844660540228285024912438872417272639282904674556947240
Short name T483
Test name
Test status
Simulation time 126189108435 ps
CPU time 311.29 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 02:02:06 PM PST 23
Peak memory 211212 kb
Host smart-67e7ed53-7188-4e8c-861c-59ce7138b931
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=29845429821340475148397844660540228285024912438872417272639282904674556947240 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.29845429821340475148397844660540228285024912438872417272639282904674556947240
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.44301896088951252754441213524339989067466792820485877376157926277551188188564
Short name T119
Test name
Test status
Simulation time 766920935 ps
CPU time 27.35 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 01:57:24 PM PST 23
Peak memory 203848 kb
Host smart-bb153fd6-3269-404a-b6a1-0d5048975c59
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44301896088951252754441213524339989067466792820485877376157926277551188188564 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.44301896088951252754441213524339989067466792820485877376157926277551188188564
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.100526017490954544759692372732152841788937232062105123365421828048876154458779
Short name T641
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.59 seconds
Started Nov 22 01:56:49 PM PST 23
Finished Nov 22 01:57:28 PM PST 23
Peak memory 204320 kb
Host smart-e2266ead-c973-4bec-aae9-dace8d81c2b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100526017490954544759692372732152841788937232062105123365421828048876154458779 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 17.xbar_same_source.100526017490954544759692372732152841788937232062105123365421828048876154458779
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.104363582854223894762883045618019141000912897400510007752981293675606815494344
Short name T3
Test name
Test status
Simulation time 669983435 ps
CPU time 4.15 seconds
Started Nov 22 01:56:51 PM PST 23
Finished Nov 22 01:56:56 PM PST 23
Peak memory 203096 kb
Host smart-646bc430-1d3e-4e93-8b0b-89bb0f32a680
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104363582854223894762883045618019141000912897400510007752981293675606815494344 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 17.xbar_smoke.104363582854223894762883045618019141000912897400510007752981293675606815494344
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.61817962605901303776577826320575914727745626205993927725533519527140537185974
Short name T472
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.45 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:43 PM PST 23
Peak memory 203280 kb
Host smart-f00a6878-b388-4e48-a54c-3b2561fcf618
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=61817962605901303776577826320575914727745626205993927725533519527140537185974 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.61817962605901303776577826320575914727745626205993927725533519527140537185974
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.17623597126250831023728067641409424336493664056289900104389011131316473702122
Short name T314
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.65 seconds
Started Nov 22 01:56:49 PM PST 23
Finished Nov 22 01:57:35 PM PST 23
Peak memory 203276 kb
Host smart-9be36071-baf3-4bc3-b8dc-132b501a9d9d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=17623597126250831023728067641409424336493664056289900104389011131316473702122 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.17623597126250831023728067641409424336493664056289900104389011131316473702122
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.49874236186100153323508889381051971729526607852459624633276231669132415039555
Short name T812
Test name
Test status
Simulation time 116233435 ps
CPU time 2.49 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:56:57 PM PST 23
Peak memory 203084 kb
Host smart-a9712718-68d3-4f67-8b5b-2a7287d7861e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49874236186100153323508889381051971729526607852459624633276231669132415039555 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.49874236186100153323508889381051971729526607852459624633276231669132415039555
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.60547236628125209814772619827616145557454231846389049782109472972129185245013
Short name T438
Test name
Test status
Simulation time 18904859184 ps
CPU time 126.6 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:59:06 PM PST 23
Peak memory 205848 kb
Host smart-1b7d2971-9ffd-4acb-98a6-c79e168b2809
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=60547236628125209814772619827616145557454231846389049782109472972129185245013 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 17.xbar_stress_all.60547236628125209814772619827616145557454231846389049782109472972129185245013
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.5033164788577980309733286061882910696844800551679328357189735898081444088547
Short name T657
Test name
Test status
Simulation time 18894549184 ps
CPU time 118.13 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 01:58:56 PM PST 23
Peak memory 211404 kb
Host smart-a70bf80d-0190-4b70-93d7-179bf47e138a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5033164788577980309733286061882910696844800551679328357189735898081444088547 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 17.xbar_stress_all_with_error.5033164788577980309733286061882910696844800551679328357189735898081444088547
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.105484455590009031595137646932277029320661879812438120548628156954978133502782
Short name T27
Test name
Test status
Simulation time 5188549184 ps
CPU time 284.83 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 02:01:42 PM PST 23
Peak memory 208496 kb
Host smart-0aca36d2-6681-4c4d-9a88-ad834f84367e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105484455590009031595137646932277029320661879812438120548628156954978133502782 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.105484455590009031595137646932277029320661879812438120548628156954978133502782
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.74687296488032183263021470078284001949441975983862656975517557748237064367499
Short name T144
Test name
Test status
Simulation time 5188549184 ps
CPU time 222.78 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 02:00:37 PM PST 23
Peak memory 219512 kb
Host smart-4328363f-ae34-4280-9d30-50e2b259f040
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74687296488032183263021470078284001949441975983862656975517557748237064367499 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.74687296488032183263021470078284001949441975983862656975517557748237064367499
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.93655904572638912862328147240563983121265315451671424682655813120242956033700
Short name T363
Test name
Test status
Simulation time 3307045935 ps
CPU time 27.46 seconds
Started Nov 22 01:56:58 PM PST 23
Finished Nov 22 01:57:27 PM PST 23
Peak memory 211396 kb
Host smart-11b813ee-f3fe-49d8-94ec-2e937599543e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93655904572638912862328147240563983121265315451671424682655813120242956033700 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 17.xbar_unmapped_addr.93655904572638912862328147240563983121265315451671424682655813120242956033700
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.65559684432785905208734472036933041223322243623153761337581362818784967438350
Short name T674
Test name
Test status
Simulation time 7399045935 ps
CPU time 58.64 seconds
Started Nov 22 01:57:18 PM PST 23
Finished Nov 22 01:58:23 PM PST 23
Peak memory 206228 kb
Host smart-6feeddce-6c73-4d70-a2bc-b75b244f58bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=65559684432785905208734472036933041223322243623153761337581362818784967438350 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.65559684432785905208734472036933041223322243623153761337581362818784967438350
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.60002991115188173753488236369447986861068529644300724674384926083610047961536
Short name T42
Test name
Test status
Simulation time 304288045935 ps
CPU time 758.93 seconds
Started Nov 22 01:57:29 PM PST 23
Finished Nov 22 02:10:09 PM PST 23
Peak memory 211340 kb
Host smart-ea52cc20-6b7a-44c3-af39-5cb2ddcda3da
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=60002991115188173753488236369447986861068529644300724674384926083610047961536 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.60002991115188173753488236369447986861068529644300724674384926083610047961536
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.72974401109299413798847955062949535082243947769905345858870042731776321669625
Short name T513
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.68 seconds
Started Nov 22 01:57:23 PM PST 23
Finished Nov 22 01:57:52 PM PST 23
Peak memory 203244 kb
Host smart-7602da9c-3958-4fb6-bbae-4ab0ed363849
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72974401109299413798847955062949535082243947769905345858870042731776321669625 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.72974401109299413798847955062949535082243947769905345858870042731776321669625
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.94099211610416718220687745348195420915326412802199789216495516762820587529812
Short name T549
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.3 seconds
Started Nov 22 01:57:12 PM PST 23
Finished Nov 22 01:57:54 PM PST 23
Peak memory 203196 kb
Host smart-a4012c3c-6b30-4300-86a1-6bc4a0ad4266
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94099211610416718220687745348195420915326412802199789216495516762820587529812 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 18.xbar_error_random.94099211610416718220687745348195420915326412802199789216495516762820587529812
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.78264706435771171850298270022484868176541148112278136462764816259719449119302
Short name T90
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.41 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 01:57:35 PM PST 23
Peak memory 211424 kb
Host smart-58741bae-4a4d-4ac7-abdc-da4a7889affe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78264706435771171850298270022484868176541148112278136462764816259719449119302 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 18.xbar_random.78264706435771171850298270022484868176541148112278136462764816259719449119302
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.92801415111354536189430070081421582748126309535942592837297676427886162893038
Short name T806
Test name
Test status
Simulation time 188793233435 ps
CPU time 317.04 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 02:02:44 PM PST 23
Peak memory 204820 kb
Host smart-430b9160-e7a9-4da0-a21a-7187833356db
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=92801415111354536189430070081421582748126309535942592837297676427886162893038 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 18.xbar_random_large_delays.92801415111354536189430070081421582748126309535942592837297676427886162893038
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.90364293046435968049157823874105522888852151944704793962955267848016129464515
Short name T610
Test name
Test status
Simulation time 126189108435 ps
CPU time 323.95 seconds
Started Nov 22 01:56:59 PM PST 23
Finished Nov 22 02:02:24 PM PST 23
Peak memory 211348 kb
Host smart-176e6c66-0759-4390-90c2-6d51b759823b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=90364293046435968049157823874105522888852151944704793962955267848016129464515 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.90364293046435968049157823874105522888852151944704793962955267848016129464515
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.22443995908404915463478715442704218481855020905345648366211854357005225135629
Short name T207
Test name
Test status
Simulation time 766920935 ps
CPU time 26.46 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:57:26 PM PST 23
Peak memory 203852 kb
Host smart-3449f0ad-74f4-4102-844f-f216e184e3a0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22443995908404915463478715442704218481855020905345648366211854357005225135629 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.22443995908404915463478715442704218481855020905345648366211854357005225135629
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.55772566309125836929285011031966638150558032272602663840828635244026585249902
Short name T122
Test name
Test status
Simulation time 7116170935 ps
CPU time 34.68 seconds
Started Nov 22 01:57:14 PM PST 23
Finished Nov 22 01:57:55 PM PST 23
Peak memory 204240 kb
Host smart-3e8cb132-a9ee-4264-82ec-494ac978ad88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55772566309125836929285011031966638150558032272602663840828635244026585249902 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 18.xbar_same_source.55772566309125836929285011031966638150558032272602663840828635244026585249902
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.48937875960892367293113292681399704949069621196967709426706460844517299262082
Short name T560
Test name
Test status
Simulation time 669983435 ps
CPU time 4.15 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:57:03 PM PST 23
Peak memory 203140 kb
Host smart-3fabfe2a-6c86-4997-b5d0-cd9236add403
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48937875960892367293113292681399704949069621196967709426706460844517299262082 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 18.xbar_smoke.48937875960892367293113292681399704949069621196967709426706460844517299262082
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.66649572645772057825062014266924397567133101283404694472772706868406475227399
Short name T345
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.17 seconds
Started Nov 22 01:56:58 PM PST 23
Finished Nov 22 01:57:48 PM PST 23
Peak memory 203276 kb
Host smart-b79a3b9b-9b3e-4fe4-bdd7-0d57fc088362
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=66649572645772057825062014266924397567133101283404694472772706868406475227399 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.66649572645772057825062014266924397567133101283404694472772706868406475227399
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.13165853256287921912315373365800970436794040590895792936042756907174059810115
Short name T276
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.25 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:40 PM PST 23
Peak memory 203276 kb
Host smart-b8e165ca-ed70-4fe1-ba72-79bf451a95d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=13165853256287921912315373365800970436794040590895792936042756907174059810115 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.13165853256287921912315373365800970436794040590895792936042756907174059810115
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.40019380438787384462778984981950599810141835517077991352373449341631963005088
Short name T435
Test name
Test status
Simulation time 116233435 ps
CPU time 2.64 seconds
Started Nov 22 01:56:58 PM PST 23
Finished Nov 22 01:57:02 PM PST 23
Peak memory 202932 kb
Host smart-0e16442a-caec-4d40-9810-ade40e63077e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40019380438787384462778984981950599810141835517077991352373449341631963005088 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.40019380438787384462778984981950599810141835517077991352373449341631963005088
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.54872377006574565338270616489643388399262228077545653483638204919236867571856
Short name T680
Test name
Test status
Simulation time 18904859184 ps
CPU time 132.86 seconds
Started Nov 22 01:57:12 PM PST 23
Finished Nov 22 01:59:31 PM PST 23
Peak memory 205816 kb
Host smart-f50ba672-6757-4e5a-b36a-c0c05903ade4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54872377006574565338270616489643388399262228077545653483638204919236867571856 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 18.xbar_stress_all.54872377006574565338270616489643388399262228077545653483638204919236867571856
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.13357269397177906888303203750504991841259460708612184808207063324444896306460
Short name T133
Test name
Test status
Simulation time 18894549184 ps
CPU time 119.32 seconds
Started Nov 22 01:57:26 PM PST 23
Finished Nov 22 01:59:27 PM PST 23
Peak memory 211352 kb
Host smart-01b81675-d416-4e0e-a2d5-85780dc980a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13357269397177906888303203750504991841259460708612184808207063324444896306460 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 18.xbar_stress_all_with_error.13357269397177906888303203750504991841259460708612184808207063324444896306460
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.5725393670315669172832314226224203194446170352930492498247615117041715718502
Short name T309
Test name
Test status
Simulation time 5188549184 ps
CPU time 292.96 seconds
Started Nov 22 01:57:23 PM PST 23
Finished Nov 22 02:02:20 PM PST 23
Peak memory 208464 kb
Host smart-6c40b0b4-863b-4f95-b275-6f4f32e5753a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5725393670315669172832314226224203194446170352930492498247615117041715718502 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.5725393670315669172832314226224203194446170352930492498247615117041715718502
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.27913918435937471968302060738608810067835005113675260630401370232291444958678
Short name T142
Test name
Test status
Simulation time 5188549184 ps
CPU time 230.54 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 02:01:17 PM PST 23
Peak memory 219596 kb
Host smart-602b06f0-eb0f-4250-bcd5-5c8a64db0663
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27913918435937471968302060738608810067835005113675260630401370232291444958678 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.27913918435937471968302060738608810067835005113675260630401370232291444958678
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.86335330567231344493349272114454625264948048430501251649524073572295835744003
Short name T850
Test name
Test status
Simulation time 7399045935 ps
CPU time 64.37 seconds
Started Nov 22 01:57:21 PM PST 23
Finished Nov 22 01:58:30 PM PST 23
Peak memory 206264 kb
Host smart-d66e1359-9498-4a31-9882-c460ad18cd24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86335330567231344493349272114454625264948048430501251649524073572295835744003 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.86335330567231344493349272114454625264948048430501251649524073572295835744003
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.44996409661323499885707677199708026134264583511354787330708071326012221664735
Short name T62
Test name
Test status
Simulation time 304288045935 ps
CPU time 776.27 seconds
Started Nov 22 01:57:08 PM PST 23
Finished Nov 22 02:10:07 PM PST 23
Peak memory 211444 kb
Host smart-71153f52-58ca-4253-8315-6c3e6fcee691
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=44996409661323499885707677199708026134264583511354787330708071326012221664735 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.44996409661323499885707677199708026134264583511354787330708071326012221664735
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.115298701786289039166213973161096489746890275317641628675499412290328050450505
Short name T584
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.72 seconds
Started Nov 22 01:56:59 PM PST 23
Finished Nov 22 01:57:28 PM PST 23
Peak memory 203252 kb
Host smart-2bbbad38-5ef9-42e0-9070-47f3ad9a6418
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115298701786289039166213973161096489746890275317641628675499412290328050450505 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.115298701786289039166213973161096489746890275317641628675499412290328050450505
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.16037791383510581793563685246201189378432908349011608407394922696820945391381
Short name T484
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.06 seconds
Started Nov 22 01:57:11 PM PST 23
Finished Nov 22 01:57:55 PM PST 23
Peak memory 203272 kb
Host smart-7e542d68-e6a5-45dc-88ae-820d0e4540bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16037791383510581793563685246201189378432908349011608407394922696820945391381 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 19.xbar_error_random.16037791383510581793563685246201189378432908349011608407394922696820945391381
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.35236708469211376358952165005648592352665953726296158499551425996569837367804
Short name T420
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.64 seconds
Started Nov 22 01:57:10 PM PST 23
Finished Nov 22 01:57:51 PM PST 23
Peak memory 211364 kb
Host smart-b3e68275-2fe2-44cd-a6d0-a48533cd8cc2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35236708469211376358952165005648592352665953726296158499551425996569837367804 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 19.xbar_random.35236708469211376358952165005648592352665953726296158499551425996569837367804
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2070942127424764329128730643906371356191349015398296215115443599237651279941
Short name T590
Test name
Test status
Simulation time 188793233435 ps
CPU time 332.57 seconds
Started Nov 22 01:57:23 PM PST 23
Finished Nov 22 02:02:59 PM PST 23
Peak memory 204832 kb
Host smart-ac964b07-8fc8-4153-95d3-60ac5f7102a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070942127424764329128730643906371356191349015398296215115443599237651279941 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2070942127424764329128730643906371356191349015398296215115443599237651279941
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.33913839445849549129556835471431056235537086789445205256591957863671754398552
Short name T38
Test name
Test status
Simulation time 126189108435 ps
CPU time 329.19 seconds
Started Nov 22 01:57:29 PM PST 23
Finished Nov 22 02:03:00 PM PST 23
Peak memory 211460 kb
Host smart-ee9430b5-2fb9-4fc2-8199-5c6448535e7b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=33913839445849549129556835471431056235537086789445205256591957863671754398552 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.33913839445849549129556835471431056235537086789445205256591957863671754398552
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.29758162227498096457226845023954317494769887594194080529064859622806955646820
Short name T589
Test name
Test status
Simulation time 766920935 ps
CPU time 23.88 seconds
Started Nov 22 01:57:28 PM PST 23
Finished Nov 22 01:57:53 PM PST 23
Peak memory 203744 kb
Host smart-3ae4a8dc-c56b-4fe2-8d2b-d6df2f710f01
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29758162227498096457226845023954317494769887594194080529064859622806955646820 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.29758162227498096457226845023954317494769887594194080529064859622806955646820
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.34600103659072413969465984381258408494774618000877918659364829074770921326774
Short name T283
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.64 seconds
Started Nov 22 01:57:10 PM PST 23
Finished Nov 22 01:57:51 PM PST 23
Peak memory 204320 kb
Host smart-51fd0c16-feaf-4977-b1fe-7e319acd8b59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34600103659072413969465984381258408494774618000877918659364829074770921326774 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 19.xbar_same_source.34600103659072413969465984381258408494774618000877918659364829074770921326774
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.46169939313782824708183320911176802580152256745512902807295259921680973952626
Short name T427
Test name
Test status
Simulation time 669983435 ps
CPU time 4.37 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 01:57:31 PM PST 23
Peak memory 203144 kb
Host smart-e9ede13d-24be-43ef-aa3e-51bb53114a40
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46169939313782824708183320911176802580152256745512902807295259921680973952626 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 19.xbar_smoke.46169939313782824708183320911176802580152256745512902807295259921680973952626
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.80056286531903870850442879725249844180531449402723664202217668623516511947483
Short name T681
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.08 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 01:58:14 PM PST 23
Peak memory 203124 kb
Host smart-28d0affa-0446-45e0-857e-01a4c6218cf6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=80056286531903870850442879725249844180531449402723664202217668623516511947483 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.80056286531903870850442879725249844180531449402723664202217668623516511947483
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.98165593506946725622597753214372235088495903452380139760186191046974491194904
Short name T279
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.05 seconds
Started Nov 22 01:57:12 PM PST 23
Finished Nov 22 01:58:03 PM PST 23
Peak memory 203236 kb
Host smart-d6b63648-c87a-48d5-bb50-5d72eab72b71
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=98165593506946725622597753214372235088495903452380139760186191046974491194904 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.98165593506946725622597753214372235088495903452380139760186191046974491194904
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.69206860698040448496129535499611859166824957667700967294113107834693798053971
Short name T625
Test name
Test status
Simulation time 116233435 ps
CPU time 2.57 seconds
Started Nov 22 01:57:00 PM PST 23
Finished Nov 22 01:57:03 PM PST 23
Peak memory 203068 kb
Host smart-76c786c1-ca7d-4960-9039-bd7657491454
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69206860698040448496129535499611859166824957667700967294113107834693798053971 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.69206860698040448496129535499611859166824957667700967294113107834693798053971
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.44480415041158017774209867357692089997886647154733541892724839221381072644165
Short name T182
Test name
Test status
Simulation time 18904859184 ps
CPU time 132.94 seconds
Started Nov 22 01:57:24 PM PST 23
Finished Nov 22 01:59:40 PM PST 23
Peak memory 205852 kb
Host smart-3bd4e1b3-aa8b-40a8-a0fe-6ae47fdc7b6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44480415041158017774209867357692089997886647154733541892724839221381072644165 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 19.xbar_stress_all.44480415041158017774209867357692089997886647154733541892724839221381072644165
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.91562038177133469512094532659539967396117337517618915461246740600610260040629
Short name T735
Test name
Test status
Simulation time 18894549184 ps
CPU time 127.91 seconds
Started Nov 22 01:57:02 PM PST 23
Finished Nov 22 01:59:11 PM PST 23
Peak memory 211424 kb
Host smart-d24c3351-4d40-4b48-974e-f304c25c6528
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91562038177133469512094532659539967396117337517618915461246740600610260040629 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 19.xbar_stress_all_with_error.91562038177133469512094532659539967396117337517618915461246740600610260040629
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.31632832797096089700867729582083571894953004431420490508644160212368587495323
Short name T388
Test name
Test status
Simulation time 5188549184 ps
CPU time 291.52 seconds
Started Nov 22 01:57:15 PM PST 23
Finished Nov 22 02:02:12 PM PST 23
Peak memory 208448 kb
Host smart-2bb6dcd2-5296-40d9-b846-ffaad6eac980
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31632832797096089700867729582083571894953004431420490508644160212368587495323 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.31632832797096089700867729582083571894953004431420490508644160212368587495323
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.77099357992659016857869449690560024151644051141857598988214443599816192654433
Short name T824
Test name
Test status
Simulation time 5188549184 ps
CPU time 228.19 seconds
Started Nov 22 01:57:23 PM PST 23
Finished Nov 22 02:01:15 PM PST 23
Peak memory 219608 kb
Host smart-3a73ce24-059a-4d32-8afd-9aa61dae20f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=77099357992659016857869449690560024151644051141857598988214443599816192654433 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.77099357992659016857869449690560024151644051141857598988214443599816192654433
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.97531177550199552655728118356501605217019786672756943301447530724546194247607
Short name T35
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.65 seconds
Started Nov 22 01:57:20 PM PST 23
Finished Nov 22 01:57:56 PM PST 23
Peak memory 211388 kb
Host smart-75b8b434-e795-4612-9eeb-f836a012e6ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=97531177550199552655728118356501605217019786672756943301447530724546194247607 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 19.xbar_unmapped_addr.97531177550199552655728118356501605217019786672756943301447530724546194247607
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.11249108496964162318786171423339361426590244920802796935768586336170376793057
Short name T538
Test name
Test status
Simulation time 7399045935 ps
CPU time 59.46 seconds
Started Nov 22 01:56:11 PM PST 23
Finished Nov 22 01:57:11 PM PST 23
Peak memory 211456 kb
Host smart-59a8d7b6-af5b-48db-87df-4caeeb95f383
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=11249108496964162318786171423339361426590244920802796935768586336170376793057 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.11249108496964162318786171423339361426590244920802796935768586336170376793057
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.98056060089243430313150182656020311016233556638054856806129954205546240990696
Short name T75
Test name
Test status
Simulation time 304288045935 ps
CPU time 769.87 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 02:09:09 PM PST 23
Peak memory 211508 kb
Host smart-21f6c1f9-06c9-4de2-a0b1-fd58d0e9da64
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=98056060089243430313150182656020311016233556638054856806129954205546240990696 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.98056060089243430313150182656020311016233556638054856806129954205546240990696
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.34082095946224300832150242929591106229719853302149772324947419020548213034230
Short name T466
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.69 seconds
Started Nov 22 01:56:21 PM PST 23
Finished Nov 22 01:56:48 PM PST 23
Peak memory 203304 kb
Host smart-f39dd167-cda1-4c5d-a722-60d2de53ec5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34082095946224300832150242929591106229719853302149772324947419020548213034230 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.34082095946224300832150242929591106229719853302149772324947419020548213034230
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.40939335712284330325651188976272793775703304296536556975219905551773045475349
Short name T121
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.33 seconds
Started Nov 22 01:56:21 PM PST 23
Finished Nov 22 01:56:59 PM PST 23
Peak memory 203260 kb
Host smart-7e05957a-b5cc-4560-a190-8680c64e773c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40939335712284330325651188976272793775703304296536556975219905551773045475349 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 2.xbar_error_random.40939335712284330325651188976272793775703304296536556975219905551773045475349
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.5457649490028957952315253080651873168003513540497112221245339237563854729798
Short name T45
Test name
Test status
Simulation time 4402420935 ps
CPU time 41.68 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 01:57:02 PM PST 23
Peak memory 211392 kb
Host smart-e11ae22d-dc8e-4736-a472-ebcf8d26ff46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5457649490028957952315253080651873168003513540497112221245339237563854729798 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 2.xbar_random.5457649490028957952315253080651873168003513540497112221245339237563854729798
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.75776820822066104187292868589081539592451326310351921853637388718730725997109
Short name T749
Test name
Test status
Simulation time 188793233435 ps
CPU time 333.33 seconds
Started Nov 22 01:56:16 PM PST 23
Finished Nov 22 02:01:51 PM PST 23
Peak memory 204812 kb
Host smart-5eff4ff9-05c5-4db7-92a4-7ee12240c69c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=75776820822066104187292868589081539592451326310351921853637388718730725997109 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 2.xbar_random_large_delays.75776820822066104187292868589081539592451326310351921853637388718730725997109
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.13689442085063794519903771433431172871570218180968942259194868967005199721460
Short name T439
Test name
Test status
Simulation time 126189108435 ps
CPU time 322.18 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 02:01:43 PM PST 23
Peak memory 211452 kb
Host smart-f83deeb5-b083-4545-8436-e14059634060
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=13689442085063794519903771433431172871570218180968942259194868967005199721460 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.13689442085063794519903771433431172871570218180968942259194868967005199721460
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.107626075011078360555464519881136942134722206342754167821088589281400664052910
Short name T857
Test name
Test status
Simulation time 766920935 ps
CPU time 25.45 seconds
Started Nov 22 01:56:37 PM PST 23
Finished Nov 22 01:57:03 PM PST 23
Peak memory 203788 kb
Host smart-ee0d590d-6ae0-4724-b132-3bf574c8cf5f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107626075011078360555464519881136942134722206342754167821088589281400664052910 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.107626075011078360555464519881136942134722206342754167821088589281400664052910
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.39492799464858833509874572050472785528093092276688616583631376950950577048088
Short name T727
Test name
Test status
Simulation time 7116170935 ps
CPU time 40.02 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 01:56:58 PM PST 23
Peak memory 204256 kb
Host smart-2e7d4381-6836-4099-ae43-f286fd35b492
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=39492799464858833509874572050472785528093092276688616583631376950950577048088 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 2.xbar_same_source.39492799464858833509874572050472785528093092276688616583631376950950577048088
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.13039613882196487377972733325854940022221083663981982825477193199584757669954
Short name T201
Test name
Test status
Simulation time 669983435 ps
CPU time 4.5 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:56:26 PM PST 23
Peak memory 203116 kb
Host smart-3a7ce33f-fe35-43be-8a88-4c4e223b17a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13039613882196487377972733325854940022221083663981982825477193199584757669954 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 2.xbar_smoke.13039613882196487377972733325854940022221083663981982825477193199584757669954
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.59521459968139263557787474168504817680951434136105002460874021155539655658012
Short name T126
Test name
Test status
Simulation time 28419483435 ps
CPU time 49.39 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 01:57:13 PM PST 23
Peak memory 203224 kb
Host smart-c1c4cff2-af4d-4aaa-9af4-8aa7a1431994
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=59521459968139263557787474168504817680951434136105002460874021155539655658012 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.59521459968139263557787474168504817680951434136105002460874021155539655658012
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.56835998763103219433029019533897021508612666100718875797400523439260993291763
Short name T563
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.91 seconds
Started Nov 22 01:56:10 PM PST 23
Finished Nov 22 01:56:56 PM PST 23
Peak memory 203276 kb
Host smart-d44ade82-d1af-4b75-b852-cebd9498f393
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=56835998763103219433029019533897021508612666100718875797400523439260993291763 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.56835998763103219433029019533897021508612666100718875797400523439260993291763
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.13634744950835065828894642105091816885605207765290458560455822509728921254672
Short name T816
Test name
Test status
Simulation time 116233435 ps
CPU time 2.5 seconds
Started Nov 22 01:56:21 PM PST 23
Finished Nov 22 01:56:25 PM PST 23
Peak memory 203120 kb
Host smart-122cb06f-7ddb-429c-9813-1772fb9c2301
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13634744950835065828894642105091816885605207765290458560455822509728921254672 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.13634744950835065828894642105091816885605207765290458560455822509728921254672
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.21353160631857145300921298455939605312019311371016789219184640579806939324775
Short name T60
Test name
Test status
Simulation time 18904859184 ps
CPU time 133.84 seconds
Started Nov 22 01:56:15 PM PST 23
Finished Nov 22 01:58:30 PM PST 23
Peak memory 205852 kb
Host smart-929d2264-0eb3-40d2-bd77-91a8bffbf97e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=21353160631857145300921298455939605312019311371016789219184640579806939324775 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 2.xbar_stress_all.21353160631857145300921298455939605312019311371016789219184640579806939324775
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3564659376442369769263972805203883157443792410179964705543426930823039379942
Short name T120
Test name
Test status
Simulation time 18894549184 ps
CPU time 124.84 seconds
Started Nov 22 01:56:16 PM PST 23
Finished Nov 22 01:58:22 PM PST 23
Peak memory 211420 kb
Host smart-4134a171-420b-43bf-a436-fe635b62af84
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3564659376442369769263972805203883157443792410179964705543426930823039379942 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 2.xbar_stress_all_with_error.3564659376442369769263972805203883157443792410179964705543426930823039379942
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.74928023027560930531843276625631699043014510549499185934388832949396963807613
Short name T481
Test name
Test status
Simulation time 5188549184 ps
CPU time 297.88 seconds
Started Nov 22 01:56:21 PM PST 23
Finished Nov 22 02:01:20 PM PST 23
Peak memory 208532 kb
Host smart-e1466896-09ed-4f2f-8222-6593a78a34c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74928023027560930531843276625631699043014510549499185934388832949396963807613 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.74928023027560930531843276625631699043014510549499185934388832949396963807613
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.113710846922828185240478598047281881682472150453333715931898926465011513461732
Short name T398
Test name
Test status
Simulation time 5188549184 ps
CPU time 224.73 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 02:00:03 PM PST 23
Peak memory 219524 kb
Host smart-7920215d-f042-4af9-a635-d5ce7766ce6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=113710846922828185240478598047281881682472150453333715931898926465011513461732 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.113710846922828185240478598047281881682472150453333715931898926465011513461732
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.27568839011208945970140413397446749284781590737547450082022777934789874354224
Short name T476
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.07 seconds
Started Nov 22 01:56:18 PM PST 23
Finished Nov 22 01:56:47 PM PST 23
Peak memory 211356 kb
Host smart-88d91765-af16-4f4c-b459-f6d0b6e5f6e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27568839011208945970140413397446749284781590737547450082022777934789874354224 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 2.xbar_unmapped_addr.27568839011208945970140413397446749284781590737547450082022777934789874354224
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.43387393123301164959763680631777981968973864787601197470738133321542350509064
Short name T408
Test name
Test status
Simulation time 7399045935 ps
CPU time 68.51 seconds
Started Nov 22 01:57:11 PM PST 23
Finished Nov 22 01:58:26 PM PST 23
Peak memory 206340 kb
Host smart-29dc6520-651f-4178-9ef6-5d5ffd26ccbf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=43387393123301164959763680631777981968973864787601197470738133321542350509064 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.43387393123301164959763680631777981968973864787601197470738133321542350509064
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.31486358801127052209253622528043590772728935218473459190498186675005347736446
Short name T693
Test name
Test status
Simulation time 304288045935 ps
CPU time 765.1 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 02:10:11 PM PST 23
Peak memory 211280 kb
Host smart-b6ea94a0-42a3-45f1-b7a8-94b614206cae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=31486358801127052209253622528043590772728935218473459190498186675005347736446 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.31486358801127052209253622528043590772728935218473459190498186675005347736446
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.86374000296116143465268076452307697147412190460483802248497093957251133886158
Short name T487
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.61 seconds
Started Nov 22 01:57:21 PM PST 23
Finished Nov 22 01:57:54 PM PST 23
Peak memory 203316 kb
Host smart-ddf1ddd6-2bb5-4902-b042-2ca4c2cffbd7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86374000296116143465268076452307697147412190460483802248497093957251133886158 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.86374000296116143465268076452307697147412190460483802248497093957251133886158
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.7557966662317521591659674614786851494789285644652830506626453780741240621146
Short name T732
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.54 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 01:58:02 PM PST 23
Peak memory 203236 kb
Host smart-34bda222-8dc0-4cb2-a7f6-ddcf310073ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=7557966662317521591659674614786851494789285644652830506626453780741240621146 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 20.xbar_error_random.7557966662317521591659674614786851494789285644652830506626453780741240621146
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.91680490886716449535214928743261101123992512186712302615472120810124633954153
Short name T537
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.32 seconds
Started Nov 22 01:57:23 PM PST 23
Finished Nov 22 01:58:05 PM PST 23
Peak memory 211428 kb
Host smart-2bb5a378-11c5-4443-ae47-6b21019bd61b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91680490886716449535214928743261101123992512186712302615472120810124633954153 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 20.xbar_random.91680490886716449535214928743261101123992512186712302615472120810124633954153
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.26470764864506861852378819580177906120995872883519682258173330503650307809410
Short name T846
Test name
Test status
Simulation time 188793233435 ps
CPU time 326.3 seconds
Started Nov 22 01:57:24 PM PST 23
Finished Nov 22 02:02:53 PM PST 23
Peak memory 204808 kb
Host smart-c84ff8aa-b547-4109-95c5-4f6dcb8e3afa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=26470764864506861852378819580177906120995872883519682258173330503650307809410 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 20.xbar_random_large_delays.26470764864506861852378819580177906120995872883519682258173330503650307809410
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.76168646820575428699224182413423026776413986753090448759166234943326284075022
Short name T531
Test name
Test status
Simulation time 126189108435 ps
CPU time 322.42 seconds
Started Nov 22 01:57:09 PM PST 23
Finished Nov 22 02:02:34 PM PST 23
Peak memory 211440 kb
Host smart-4345568a-3371-4624-919c-ecaa3a66935c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=76168646820575428699224182413423026776413986753090448759166234943326284075022 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.76168646820575428699224182413423026776413986753090448759166234943326284075022
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.39456305410160388664818355588138615938569437619481409947535123447104308060722
Short name T360
Test name
Test status
Simulation time 766920935 ps
CPU time 24.74 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 01:57:51 PM PST 23
Peak memory 203756 kb
Host smart-a7e98fc9-4827-4176-867b-c4308cff1a3b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39456305410160388664818355588138615938569437619481409947535123447104308060722 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.39456305410160388664818355588138615938569437619481409947535123447104308060722
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.53944230488150012486700796956985352292774410396152788901382795994529890355241
Short name T499
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.6 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 01:58:05 PM PST 23
Peak memory 204292 kb
Host smart-8be1e0d8-6b4a-4237-a613-37e45c8cef5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53944230488150012486700796956985352292774410396152788901382795994529890355241 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 20.xbar_same_source.53944230488150012486700796956985352292774410396152788901382795994529890355241
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.22822269862650570807332705281593969719760109797552800696871269105649900633715
Short name T873
Test name
Test status
Simulation time 669983435 ps
CPU time 4.17 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 01:57:30 PM PST 23
Peak memory 203196 kb
Host smart-5ffc672a-bea4-4f00-a52c-4bb8757af5af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22822269862650570807332705281593969719760109797552800696871269105649900633715 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 20.xbar_smoke.22822269862650570807332705281593969719760109797552800696871269105649900633715
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.95307491352305461639421827286111951391796051271177628062050608085139204916727
Short name T707
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.69 seconds
Started Nov 22 01:57:23 PM PST 23
Finished Nov 22 01:58:15 PM PST 23
Peak memory 203328 kb
Host smart-1fccc683-cead-4c85-9440-8a95cb87a6d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=95307491352305461639421827286111951391796051271177628062050608085139204916727 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.95307491352305461639421827286111951391796051271177628062050608085139204916727
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.62738646270344439473193757177504992862168887419170315271209713382084083015592
Short name T123
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.52 seconds
Started Nov 22 01:57:20 PM PST 23
Finished Nov 22 01:58:10 PM PST 23
Peak memory 203260 kb
Host smart-b94f57ca-4ade-42d4-9cfd-94c4247d0a68
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=62738646270344439473193757177504992862168887419170315271209713382084083015592 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.62738646270344439473193757177504992862168887419170315271209713382084083015592
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.104880564934441734912573479562379372482332112427920364033254200765339603371203
Short name T129
Test name
Test status
Simulation time 116233435 ps
CPU time 2.62 seconds
Started Nov 22 01:57:03 PM PST 23
Finished Nov 22 01:57:06 PM PST 23
Peak memory 203164 kb
Host smart-6e3c17da-b37e-4474-867d-098e864726e1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104880564934441734912573479562379372482332112427920364033254200765339603371203 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.104880564934441734912573479562379372482332112427920364033254200765339603371203
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.7682316992715502241597866240656497181370660733303868586566815384171715403046
Short name T51
Test name
Test status
Simulation time 18904859184 ps
CPU time 136.19 seconds
Started Nov 22 01:57:21 PM PST 23
Finished Nov 22 01:59:42 PM PST 23
Peak memory 205820 kb
Host smart-0ae72cf5-6f49-4f55-8529-641c1121f2ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=7682316992715502241597866240656497181370660733303868586566815384171715403046 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_
log /dev/null -cm_name 20.xbar_stress_all.7682316992715502241597866240656497181370660733303868586566815384171715403046
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.110363584824191659458757925636320236573686573771590814646601094057340690781988
Short name T285
Test name
Test status
Simulation time 18894549184 ps
CPU time 120.3 seconds
Started Nov 22 01:57:12 PM PST 23
Finished Nov 22 01:59:19 PM PST 23
Peak memory 211436 kb
Host smart-e6be7420-3fbd-4c12-ba99-be13ce3af707
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110363584824191659458757925636320236573686573771590814646601094057340690781988 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.110363584824191659458757925636320236573686573771590814646601094057340690781988
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.44425048920637237671049449537021562974237513425660544590894294520914099573516
Short name T665
Test name
Test status
Simulation time 5188549184 ps
CPU time 295.88 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 02:02:23 PM PST 23
Peak memory 208392 kb
Host smart-b71d2a20-4da6-4656-84af-c3a60758667d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44425048920637237671049449537021562974237513425660544590894294520914099573516 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.44425048920637237671049449537021562974237513425660544590894294520914099573516
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.30029522597657946791567300506884280974989948285118850543170604564152709311732
Short name T376
Test name
Test status
Simulation time 5188549184 ps
CPU time 223.03 seconds
Started Nov 22 01:57:11 PM PST 23
Finished Nov 22 02:01:00 PM PST 23
Peak memory 219508 kb
Host smart-45f6a9cd-b6e2-4509-8b82-3e849491a928
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30029522597657946791567300506884280974989948285118850543170604564152709311732 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.30029522597657946791567300506884280974989948285118850543170604564152709311732
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.24569702243297940144957144168468153802761480412046814460199999527604340644802
Short name T344
Test name
Test status
Simulation time 3307045935 ps
CPU time 31.31 seconds
Started Nov 22 01:57:12 PM PST 23
Finished Nov 22 01:57:49 PM PST 23
Peak memory 211432 kb
Host smart-01ce1bd7-ab27-4d4e-9acf-d196af2ce079
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24569702243297940144957144168468153802761480412046814460199999527604340644802 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 20.xbar_unmapped_addr.24569702243297940144957144168468153802761480412046814460199999527604340644802
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.58110539423264308294538162204919863122433911712707022938982152516026105526125
Short name T79
Test name
Test status
Simulation time 7399045935 ps
CPU time 68.02 seconds
Started Nov 22 01:57:10 PM PST 23
Finished Nov 22 01:58:20 PM PST 23
Peak memory 206296 kb
Host smart-dd106931-8968-4313-828b-c78ea7a33b99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=58110539423264308294538162204919863122433911712707022938982152516026105526125 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.58110539423264308294538162204919863122433911712707022938982152516026105526125
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.49050699670704259098143359814543167565607072772543569133964360993393833998459
Short name T654
Test name
Test status
Simulation time 304288045935 ps
CPU time 791.86 seconds
Started Nov 22 01:57:21 PM PST 23
Finished Nov 22 02:10:38 PM PST 23
Peak memory 211492 kb
Host smart-b0c342fb-9022-473c-9dc3-969be0eb86dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=49050699670704259098143359814543167565607072772543569133964360993393833998459 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.49050699670704259098143359814543167565607072772543569133964360993393833998459
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.42961673579239505938289634295745337970590435454439092406568013376354659214451
Short name T306
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.66 seconds
Started Nov 22 01:57:21 PM PST 23
Finished Nov 22 01:57:53 PM PST 23
Peak memory 203112 kb
Host smart-1028db19-55ba-4581-9312-b1d1d8ad857f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=42961673579239505938289634295745337970590435454439092406568013376354659214451 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.42961673579239505938289634295745337970590435454439092406568013376354659214451
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.40317376361661746662862209397626545881724120169046178700980612637653501493996
Short name T369
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.3 seconds
Started Nov 22 01:57:21 PM PST 23
Finished Nov 22 01:58:01 PM PST 23
Peak memory 203184 kb
Host smart-fba37acb-f1e1-4f9f-9eff-268692b5f4dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40317376361661746662862209397626545881724120169046178700980612637653501493996 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 21.xbar_error_random.40317376361661746662862209397626545881724120169046178700980612637653501493996
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.67552387401420263144474445784292122870109117508684714945831151113837456705632
Short name T292
Test name
Test status
Simulation time 4402420935 ps
CPU time 39.65 seconds
Started Nov 22 01:57:10 PM PST 23
Finished Nov 22 01:57:52 PM PST 23
Peak memory 211416 kb
Host smart-2456f31d-8e39-4c7c-9ad5-09c19adfbe03
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=67552387401420263144474445784292122870109117508684714945831151113837456705632 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 21.xbar_random.67552387401420263144474445784292122870109117508684714945831151113837456705632
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.71630673872934598232458433033289553628217125439026123864370472430790294922403
Short name T518
Test name
Test status
Simulation time 188793233435 ps
CPU time 325.64 seconds
Started Nov 22 01:57:24 PM PST 23
Finished Nov 22 02:02:53 PM PST 23
Peak memory 204808 kb
Host smart-d918ab30-e8d9-4b8c-8335-8d4538d5317a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=71630673872934598232458433033289553628217125439026123864370472430790294922403 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 21.xbar_random_large_delays.71630673872934598232458433033289553628217125439026123864370472430790294922403
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.76610426863408779362565519524490471934226910975444360101162488940607816597013
Short name T252
Test name
Test status
Simulation time 126189108435 ps
CPU time 331.9 seconds
Started Nov 22 01:57:12 PM PST 23
Finished Nov 22 02:02:50 PM PST 23
Peak memory 211476 kb
Host smart-b86f074b-ba80-41fa-98bc-f8fc109747fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=76610426863408779362565519524490471934226910975444360101162488940607816597013 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.76610426863408779362565519524490471934226910975444360101162488940607816597013
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.9451468764806414040555528573801495713622086299265470591813937806892147922636
Short name T299
Test name
Test status
Simulation time 766920935 ps
CPU time 23.99 seconds
Started Nov 22 01:57:23 PM PST 23
Finished Nov 22 01:57:51 PM PST 23
Peak memory 211340 kb
Host smart-dc1fd450-4fbb-434d-93f3-64e4f687e086
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9451468764806414040555528573801495713622086299265470591813937806892147922636 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.9451468764806414040555528573801495713622086299265470591813937806892147922636
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.96695307349721554364490715769177900812982561496533793453405941881216923853785
Short name T298
Test name
Test status
Simulation time 7116170935 ps
CPU time 35.58 seconds
Started Nov 22 01:57:19 PM PST 23
Finished Nov 22 01:58:01 PM PST 23
Peak memory 204320 kb
Host smart-066a19c8-b2ab-4cbb-aca9-295851d0cb91
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=96695307349721554364490715769177900812982561496533793453405941881216923853785 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 21.xbar_same_source.96695307349721554364490715769177900812982561496533793453405941881216923853785
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.100527142710640292176902963584254279163358503868607054297283566363553330984300
Short name T380
Test name
Test status
Simulation time 669983435 ps
CPU time 3.93 seconds
Started Nov 22 01:57:11 PM PST 23
Finished Nov 22 01:57:21 PM PST 23
Peak memory 203096 kb
Host smart-a163f8e3-a7af-4aff-975e-42e61ece1331
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100527142710640292176902963584254279163358503868607054297283566363553330984300 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 21.xbar_smoke.100527142710640292176902963584254279163358503868607054297283566363553330984300
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.92373498647112440969270031271212904536628329999891475324014543853898755752458
Short name T352
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.52 seconds
Started Nov 22 01:57:20 PM PST 23
Finished Nov 22 01:58:13 PM PST 23
Peak memory 203296 kb
Host smart-a0cbb40c-1dce-4a67-889d-eda0fd8de38a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=92373498647112440969270031271212904536628329999891475324014543853898755752458 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.92373498647112440969270031271212904536628329999891475324014543853898755752458
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.86120583020694026754514853369684143553347770099098370766034604696210723217042
Short name T211
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.08 seconds
Started Nov 22 01:57:24 PM PST 23
Finished Nov 22 01:58:12 PM PST 23
Peak memory 203220 kb
Host smart-fb8ea609-5560-45ac-ae08-c04de7c8f3e3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=86120583020694026754514853369684143553347770099098370766034604696210723217042 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.86120583020694026754514853369684143553347770099098370766034604696210723217042
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.95691762785594216250898353553133175382327081613408714302410766499267387308284
Short name T694
Test name
Test status
Simulation time 116233435 ps
CPU time 2.52 seconds
Started Nov 22 01:57:21 PM PST 23
Finished Nov 22 01:57:28 PM PST 23
Peak memory 203164 kb
Host smart-b08eb9b4-bbc4-4242-83e1-dc5f10b71c2a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95691762785594216250898353553133175382327081613408714302410766499267387308284 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.95691762785594216250898353553133175382327081613408714302410766499267387308284
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.79882336372191172588053204679027284495141299789724526065225337419269097015751
Short name T58
Test name
Test status
Simulation time 18904859184 ps
CPU time 138.42 seconds
Started Nov 22 01:57:12 PM PST 23
Finished Nov 22 01:59:37 PM PST 23
Peak memory 205840 kb
Host smart-93cc0265-ae70-45aa-92d6-6b4b55a58464
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=79882336372191172588053204679027284495141299789724526065225337419269097015751 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 21.xbar_stress_all.79882336372191172588053204679027284495141299789724526065225337419269097015751
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.54153082079359351065362565569515620270069181731796824089606197059906561365637
Short name T404
Test name
Test status
Simulation time 18894549184 ps
CPU time 116.77 seconds
Started Nov 22 01:57:22 PM PST 23
Finished Nov 22 01:59:24 PM PST 23
Peak memory 211496 kb
Host smart-ff861dda-0ba6-4c80-abb4-4ebb45fbceda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54153082079359351065362565569515620270069181731796824089606197059906561365637 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 21.xbar_stress_all_with_error.54153082079359351065362565569515620270069181731796824089606197059906561365637
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.90226367010176626957549674482965043264376257021362237378663061347242009158431
Short name T723
Test name
Test status
Simulation time 5188549184 ps
CPU time 295.88 seconds
Started Nov 22 01:57:21 PM PST 23
Finished Nov 22 02:02:22 PM PST 23
Peak memory 208544 kb
Host smart-898f8b28-6cc4-4401-b14f-c7db02fd1458
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=90226367010176626957549674482965043264376257021362237378663061347242009158431 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.90226367010176626957549674482965043264376257021362237378663061347242009158431
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.22080635048926627123884416941167146656048801567225105455835995864344299573153
Short name T835
Test name
Test status
Simulation time 5188549184 ps
CPU time 225.87 seconds
Started Nov 22 01:57:25 PM PST 23
Finished Nov 22 02:01:13 PM PST 23
Peak memory 219572 kb
Host smart-bb47a2f5-ac54-4cae-9ee8-8471226332d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22080635048926627123884416941167146656048801567225105455835995864344299573153 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.22080635048926627123884416941167146656048801567225105455835995864344299573153
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.31853093889079812574069645837801810912194124335196124187669319305008380944228
Short name T882
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.72 seconds
Started Nov 22 01:57:20 PM PST 23
Finished Nov 22 01:57:55 PM PST 23
Peak memory 211328 kb
Host smart-bb525b56-2132-4318-ac79-5ea63f05d6bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31853093889079812574069645837801810912194124335196124187669319305008380944228 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 21.xbar_unmapped_addr.31853093889079812574069645837801810912194124335196124187669319305008380944228
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.91416827117844255462758362143050267047094157990792147965525197092327774575242
Short name T262
Test name
Test status
Simulation time 7399045935 ps
CPU time 63.67 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:55 PM PST 23
Peak memory 206356 kb
Host smart-6afa61a5-bf2b-4685-88ec-518c67431b29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91416827117844255462758362143050267047094157990792147965525197092327774575242 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.91416827117844255462758362143050267047094157990792147965525197092327774575242
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.99351757395370764034498966033727778422857491910232790290975582738611838053324
Short name T410
Test name
Test status
Simulation time 304288045935 ps
CPU time 770.19 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 02:10:41 PM PST 23
Peak memory 211428 kb
Host smart-1a055819-5d38-419e-b77f-40a96ab4822b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=99351757395370764034498966033727778422857491910232790290975582738611838053324 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.99351757395370764034498966033727778422857491910232790290975582738611838053324
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.70374890565670005254806631358338177647849421665560168614024239525580069998731
Short name T132
Test name
Test status
Simulation time 3310545935 ps
CPU time 28.73 seconds
Started Nov 22 01:57:54 PM PST 23
Finished Nov 22 01:58:24 PM PST 23
Peak memory 203364 kb
Host smart-d581d2e5-3fa8-4d8e-918a-ac020264d29c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70374890565670005254806631358338177647849421665560168614024239525580069998731 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.70374890565670005254806631358338177647849421665560168614024239525580069998731
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.48167652248393126638806880554577112641731888792532091612376338352990749199202
Short name T264
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.39 seconds
Started Nov 22 01:57:43 PM PST 23
Finished Nov 22 01:58:22 PM PST 23
Peak memory 203220 kb
Host smart-9efa9aa5-23e9-480d-a843-68f116aaa988
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48167652248393126638806880554577112641731888792532091612376338352990749199202 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 22.xbar_error_random.48167652248393126638806880554577112641731888792532091612376338352990749199202
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.81846201814973035985666599100589233478787114282214881831540534844573467027056
Short name T793
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.01 seconds
Started Nov 22 01:57:41 PM PST 23
Finished Nov 22 01:58:23 PM PST 23
Peak memory 211452 kb
Host smart-e4e31607-578b-4ce0-8dbf-8a13dcbcd807
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81846201814973035985666599100589233478787114282214881831540534844573467027056 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 22.xbar_random.81846201814973035985666599100589233478787114282214881831540534844573467027056
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.37674923560696201764228360838843996448384679524426268905936034768803878337062
Short name T856
Test name
Test status
Simulation time 188793233435 ps
CPU time 321.55 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 02:03:14 PM PST 23
Peak memory 204820 kb
Host smart-0bb2cfc2-d0f5-4ace-86c5-5eccd75c5814
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=37674923560696201764228360838843996448384679524426268905936034768803878337062 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 22.xbar_random_large_delays.37674923560696201764228360838843996448384679524426268905936034768803878337062
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.29304829406513263479891819938403584389054120358937174130681669453937706067107
Short name T166
Test name
Test status
Simulation time 126189108435 ps
CPU time 326.89 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 02:03:21 PM PST 23
Peak memory 211436 kb
Host smart-7d0eea03-5e80-4194-90d7-8a3a1033b6cb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=29304829406513263479891819938403584389054120358937174130681669453937706067107 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.29304829406513263479891819938403584389054120358937174130681669453937706067107
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.9935317967281861568926601702811689827146642489718963733827407744680587464620
Short name T803
Test name
Test status
Simulation time 766920935 ps
CPU time 26.44 seconds
Started Nov 22 01:57:44 PM PST 23
Finished Nov 22 01:58:13 PM PST 23
Peak memory 211344 kb
Host smart-f7d214f3-b3bd-47c6-bcbf-9456ecc142e5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9935317967281861568926601702811689827146642489718963733827407744680587464620 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.9935317967281861568926601702811689827146642489718963733827407744680587464620
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.113238040132848251017562166336377248070885449437868726058151854469122649417358
Short name T21
Test name
Test status
Simulation time 7116170935 ps
CPU time 36.79 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:28 PM PST 23
Peak memory 204308 kb
Host smart-ba7f53d4-34b1-45df-bb50-70bb9506bf5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=113238040132848251017562166336377248070885449437868726058151854469122649417358 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 22.xbar_same_source.113238040132848251017562166336377248070885449437868726058151854469122649417358
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.71549576852517801803934953986038633917402463576929808132897391057611104797407
Short name T593
Test name
Test status
Simulation time 669983435 ps
CPU time 4.12 seconds
Started Nov 22 01:57:23 PM PST 23
Finished Nov 22 01:57:31 PM PST 23
Peak memory 203092 kb
Host smart-6de53ba0-69d2-499b-be91-07958c20fa9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71549576852517801803934953986038633917402463576929808132897391057611104797407 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 22.xbar_smoke.71549576852517801803934953986038633917402463576929808132897391057611104797407
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.19934776857549913687766747450762503077622989495782972441144974045579486315121
Short name T141
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.22 seconds
Started Nov 22 01:57:25 PM PST 23
Finished Nov 22 01:58:15 PM PST 23
Peak memory 203224 kb
Host smart-62ad9321-2f04-4c9f-aebc-1123cf3d0c59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=19934776857549913687766747450762503077622989495782972441144974045579486315121 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.19934776857549913687766747450762503077622989495782972441144974045579486315121
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.109676917731334485166405739643632893254504401332859941459449664113703772426967
Short name T415
Test name
Test status
Simulation time 17662295935 ps
CPU time 43.08 seconds
Started Nov 22 01:57:28 PM PST 23
Finished Nov 22 01:58:12 PM PST 23
Peak memory 203172 kb
Host smart-8d3df6b8-84ef-487e-ab76-f3ed96227689
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=109676917731334485166405739643632893254504401332859941459449664113703772426967 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.109676917731334485166405739643632893254504401332859941459449664113703772426967
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.84253881988132079635383172130619671499827490605256667965448250346988289940973
Short name T138
Test name
Test status
Simulation time 116233435 ps
CPU time 2.43 seconds
Started Nov 22 01:57:24 PM PST 23
Finished Nov 22 01:57:29 PM PST 23
Peak memory 203140 kb
Host smart-02c2c1f3-1151-4057-9ed9-e44dc6f744b1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84253881988132079635383172130619671499827490605256667965448250346988289940973 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.84253881988132079635383172130619671499827490605256667965448250346988289940973
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.111612365384903482235499123226306811541781196337871205387442358828657544944273
Short name T550
Test name
Test status
Simulation time 18904859184 ps
CPU time 134.81 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 02:00:05 PM PST 23
Peak memory 205824 kb
Host smart-fe21a24b-e14a-4457-904a-8425ab4ed92b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111612365384903482235499123226306811541781196337871205387442358828657544944273 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 22.xbar_stress_all.111612365384903482235499123226306811541781196337871205387442358828657544944273
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.19600285242690726788187754424814631938033561212072563148508587888174463070486
Short name T342
Test name
Test status
Simulation time 18894549184 ps
CPU time 119.26 seconds
Started Nov 22 01:57:42 PM PST 23
Finished Nov 22 01:59:45 PM PST 23
Peak memory 211496 kb
Host smart-6baf8a08-e3b5-45c5-8562-7106a2869f66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19600285242690726788187754424814631938033561212072563148508587888174463070486 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 22.xbar_stress_all_with_error.19600285242690726788187754424814631938033561212072563148508587888174463070486
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.49622338065195040761321155369928466211791940748555417557884616486705221251439
Short name T394
Test name
Test status
Simulation time 5188549184 ps
CPU time 294.42 seconds
Started Nov 22 01:57:42 PM PST 23
Finished Nov 22 02:02:41 PM PST 23
Peak memory 208452 kb
Host smart-7d11e76a-585e-4405-8317-eee2935ff8e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49622338065195040761321155369928466211791940748555417557884616486705221251439 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.49622338065195040761321155369928466211791940748555417557884616486705221251439
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.5294528833726834650670819220769022083400507422600582363279681851204994410740
Short name T442
Test name
Test status
Simulation time 5188549184 ps
CPU time 228.09 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 02:01:38 PM PST 23
Peak memory 219580 kb
Host smart-876183c2-dd3d-4ff7-afbd-32d9d74a5f98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5294528833726834650670819220769022083400507422600582363279681851204994410740 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.5294528833726834650670819220769022083400507422600582363279681851204994410740
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.115223109973419422355508548671344455255659080070367686106157995364007601751500
Short name T600
Test name
Test status
Simulation time 3307045935 ps
CPU time 32.31 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 01:58:26 PM PST 23
Peak memory 211368 kb
Host smart-673b9df3-3893-4a78-b5b6-b72ffb82a22b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115223109973419422355508548671344455255659080070367686106157995364007601751500 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 22.xbar_unmapped_addr.115223109973419422355508548671344455255659080070367686106157995364007601751500
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.63810713485356427948526764701687212839262525871867241016027074662032933876040
Short name T294
Test name
Test status
Simulation time 7399045935 ps
CPU time 68.44 seconds
Started Nov 22 01:57:55 PM PST 23
Finished Nov 22 01:59:05 PM PST 23
Peak memory 206240 kb
Host smart-9cc4b2f4-96a4-42f9-9dac-ef39ec85fc6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=63810713485356427948526764701687212839262525871867241016027074662032933876040 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.63810713485356427948526764701687212839262525871867241016027074662032933876040
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.7436111270941106102004626955626570194071954749955595700847823723908295059209
Short name T617
Test name
Test status
Simulation time 304288045935 ps
CPU time 763.27 seconds
Started Nov 22 01:57:42 PM PST 23
Finished Nov 22 02:10:29 PM PST 23
Peak memory 211412 kb
Host smart-c575866d-927d-4da2-91a9-cf4027906a36
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=7436111270941106102004626955626570194071954749955595700847823723908295059209 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build
_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.7436111270941106102004626955626570194071954749955595700847823723908295059209
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.51678593289119412012324501053588362346244560098491458882755458346722723950311
Short name T199
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.37 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 01:58:17 PM PST 23
Peak memory 203260 kb
Host smart-9f1128c3-df34-4c26-92ea-f554d2e36854
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=51678593289119412012324501053588362346244560098491458882755458346722723950311 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.51678593289119412012324501053588362346244560098491458882755458346722723950311
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.25415735431030924043288197959831930858476175231134174269396870612709097744045
Short name T713
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.25 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:28 PM PST 23
Peak memory 203272 kb
Host smart-f5c33b23-1605-4a60-9cad-5cdbc3c84196
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25415735431030924043288197959831930858476175231134174269396870612709097744045 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 23.xbar_error_random.25415735431030924043288197959831930858476175231134174269396870612709097744045
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.18382398576934170359204735948847069054061538875349154585678899245306956802987
Short name T895
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.62 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:29 PM PST 23
Peak memory 211416 kb
Host smart-1698bd5e-52cf-45b9-9c61-113937d0eb08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18382398576934170359204735948847069054061538875349154585678899245306956802987 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 23.xbar_random.18382398576934170359204735948847069054061538875349154585678899245306956802987
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.109948780136457931203513581388178149055280737891607373846571298281012160246955
Short name T453
Test name
Test status
Simulation time 188793233435 ps
CPU time 325.51 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 02:03:16 PM PST 23
Peak memory 204808 kb
Host smart-91fffbed-4cc0-4409-8527-32f3ea105820
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=109948780136457931203513581388178149055280737891607373846571298281012160246955 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.109948780136457931203513581388178149055280737891607373846571298281012160246955
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.24913268194906452902928760002575766172102733180699582540698116084109111625402
Short name T31
Test name
Test status
Simulation time 126189108435 ps
CPU time 318.5 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 02:03:11 PM PST 23
Peak memory 211380 kb
Host smart-24097820-49fa-404a-b1e6-d441dd869430
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=24913268194906452902928760002575766172102733180699582540698116084109111625402 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.24913268194906452902928760002575766172102733180699582540698116084109111625402
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.21078788325836154564623505288075530138320262409240716094828879354778394159823
Short name T836
Test name
Test status
Simulation time 766920935 ps
CPU time 26.85 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 01:58:17 PM PST 23
Peak memory 203828 kb
Host smart-717f924a-8c5c-437e-9d99-6a6736d190d4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21078788325836154564623505288075530138320262409240716094828879354778394159823 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.21078788325836154564623505288075530138320262409240716094828879354778394159823
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.48433879143902643598739073747651489899608780643324595851943654747601961690612
Short name T393
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.96 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:29 PM PST 23
Peak memory 204240 kb
Host smart-024db0ee-3a51-4991-84b7-ea82bba744c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48433879143902643598739073747651489899608780643324595851943654747601961690612 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 23.xbar_same_source.48433879143902643598739073747651489899608780643324595851943654747601961690612
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.24911111610061219855028543053827756834642652240024374890717028238741146218451
Short name T152
Test name
Test status
Simulation time 669983435 ps
CPU time 4.22 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 01:58:00 PM PST 23
Peak memory 203144 kb
Host smart-74d39134-92c4-48ac-b07e-27b550fde0f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24911111610061219855028543053827756834642652240024374890717028238741146218451 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 23.xbar_smoke.24911111610061219855028543053827756834642652240024374890717028238741146218451
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.105354509417631867847244448340526126416325455509299645220584849705226784920625
Short name T94
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.27 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:40 PM PST 23
Peak memory 203276 kb
Host smart-14a5e7e4-178a-40c3-9a53-c2f6deb68460
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=105354509417631867847244448340526126416325455509299645220584849705226784920625 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.105354509417631867847244448340526126416325455509299645220584849705226784920625
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.72339596849791259131569423452240202652041892381203066148296901973844102144567
Short name T240
Test name
Test status
Simulation time 17662295935 ps
CPU time 43.21 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 01:58:36 PM PST 23
Peak memory 203292 kb
Host smart-337e56e7-f7b4-4c32-9516-5876fccde5f0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=72339596849791259131569423452240202652041892381203066148296901973844102144567 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.72339596849791259131569423452240202652041892381203066148296901973844102144567
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.114921757444676801428991039096311361116478194147603229154499006371982750022636
Short name T379
Test name
Test status
Simulation time 116233435 ps
CPU time 2.65 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 01:57:53 PM PST 23
Peak memory 203068 kb
Host smart-5f2b2b42-39ac-4cb8-9016-58e265bb205d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114921757444676801428991039096311361116478194147603229154499006371982750022636 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.114921757444676801428991039096311361116478194147603229154499006371982750022636
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.86754581083367241027906735454051201557404075068826023278912707257079543263874
Short name T525
Test name
Test status
Simulation time 18904859184 ps
CPU time 135.81 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 02:00:11 PM PST 23
Peak memory 205808 kb
Host smart-79fdbc63-fdc7-432a-8dbf-018b56ebc7bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86754581083367241027906735454051201557404075068826023278912707257079543263874 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 23.xbar_stress_all.86754581083367241027906735454051201557404075068826023278912707257079543263874
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.33979700169381826434668169864097558951370247208910953499212109049588198372948
Short name T848
Test name
Test status
Simulation time 18894549184 ps
CPU time 118.66 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 01:59:53 PM PST 23
Peak memory 211420 kb
Host smart-74da6638-c73f-4085-b947-05a4f808d652
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33979700169381826434668169864097558951370247208910953499212109049588198372948 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 23.xbar_stress_all_with_error.33979700169381826434668169864097558951370247208910953499212109049588198372948
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.51992993733883825952955629335490513485717819056387126377108760485207969474211
Short name T205
Test name
Test status
Simulation time 5188549184 ps
CPU time 293.67 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 02:02:44 PM PST 23
Peak memory 208412 kb
Host smart-a05f8912-cd5c-4185-a8f6-2bac2f3a7b7f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=51992993733883825952955629335490513485717819056387126377108760485207969474211 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.51992993733883825952955629335490513485717819056387126377108760485207969474211
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.109617460927999244534432923884477858138429640535153466439423784726058490989114
Short name T833
Test name
Test status
Simulation time 5188549184 ps
CPU time 219.95 seconds
Started Nov 22 01:57:42 PM PST 23
Finished Nov 22 02:01:26 PM PST 23
Peak memory 219564 kb
Host smart-588113a5-9499-4253-8dd6-3546ebf05ee8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=109617460927999244534432923884477858138429640535153466439423784726058490989114 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.109617460927999244534432923884477858138429640535153466439423784726058490989114
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.79097307374779628812506051428289773791469892765073083740799053879090694276736
Short name T698
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.94 seconds
Started Nov 22 01:57:41 PM PST 23
Finished Nov 22 01:58:15 PM PST 23
Peak memory 211464 kb
Host smart-d4aed44c-6c65-406d-acd1-9325826deebd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=79097307374779628812506051428289773791469892765073083740799053879090694276736 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 23.xbar_unmapped_addr.79097307374779628812506051428289773791469892765073083740799053879090694276736
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.83569635565263666442736529658028729490108184988726061861553404361570666594156
Short name T424
Test name
Test status
Simulation time 7399045935 ps
CPU time 65.94 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 01:59:01 PM PST 23
Peak memory 206300 kb
Host smart-4435b52c-5504-40a9-98a5-dd2a2d9b3a34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83569635565263666442736529658028729490108184988726061861553404361570666594156 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.83569635565263666442736529658028729490108184988726061861553404361570666594156
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.35723829890461368775705575041147612541212536430569059871801951155062229595477
Short name T46
Test name
Test status
Simulation time 304288045935 ps
CPU time 780.62 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 02:10:56 PM PST 23
Peak memory 211360 kb
Host smart-ce3b0f34-4835-4816-baf1-8ef797162b92
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=35723829890461368775705575041147612541212536430569059871801951155062229595477 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.35723829890461368775705575041147612541212536430569059871801951155062229595477
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.114215572891329692974062366727299080121857397073792597456836899642154593305213
Short name T511
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.67 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 01:58:22 PM PST 23
Peak memory 203292 kb
Host smart-5c002d10-1b68-4544-8bbe-202f86e5c649
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=114215572891329692974062366727299080121857397073792597456836899642154593305213 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.114215572891329692974062366727299080121857397073792597456836899642154593305213
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.19727258027064510969462283688259560512474294938102435523561619471427443859877
Short name T248
Test name
Test status
Simulation time 4402420935 ps
CPU time 39.3 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:30 PM PST 23
Peak memory 203308 kb
Host smart-eccb78f8-6ff8-4d04-a893-2170b34bb79a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19727258027064510969462283688259560512474294938102435523561619471427443859877 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 24.xbar_error_random.19727258027064510969462283688259560512474294938102435523561619471427443859877
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.690902989624411984370364867187524311223305997081437035093707141394191513956
Short name T274
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.94 seconds
Started Nov 22 01:57:48 PM PST 23
Finished Nov 22 01:58:25 PM PST 23
Peak memory 211440 kb
Host smart-5a021aba-83a1-4940-8964-f50fda2a3e66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=690902989624411984370364867187524311223305997081437035093707141394191513956 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 24.xbar_random.690902989624411984370364867187524311223305997081437035093707141394191513956
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.39250156120255574177408688657608966378354397411461073008685297364867960075699
Short name T437
Test name
Test status
Simulation time 188793233435 ps
CPU time 329.06 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 02:03:19 PM PST 23
Peak memory 204804 kb
Host smart-df04b549-94ec-40f3-abcd-2c17eaace92d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=39250156120255574177408688657608966378354397411461073008685297364867960075699 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 24.xbar_random_large_delays.39250156120255574177408688657608966378354397411461073008685297364867960075699
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.114328579395546468174277852143850926090524138792467436702834986333096876334656
Short name T473
Test name
Test status
Simulation time 126189108435 ps
CPU time 328.91 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 02:03:19 PM PST 23
Peak memory 211456 kb
Host smart-4151fba1-2f3c-47b4-9032-8dbd2ef409ae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=114328579395546468174277852143850926090524138792467436702834986333096876334656 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.114328579395546468174277852143850926090524138792467436702834986333096876334656
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.20962744867619281064473227255839669658874427874285871112010689804143084933888
Short name T426
Test name
Test status
Simulation time 766920935 ps
CPU time 24.47 seconds
Started Nov 22 01:57:41 PM PST 23
Finished Nov 22 01:58:10 PM PST 23
Peak memory 203856 kb
Host smart-4120d300-d1fa-46f7-8770-a47853bc1165
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20962744867619281064473227255839669658874427874285871112010689804143084933888 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.20962744867619281064473227255839669658874427874285871112010689804143084933888
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.70975862930398002039832562465707322115016146323737931211956612002064275520162
Short name T622
Test name
Test status
Simulation time 7116170935 ps
CPU time 42.17 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 01:58:37 PM PST 23
Peak memory 204228 kb
Host smart-15c233b8-e73a-471d-ae65-43892e8047ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70975862930398002039832562465707322115016146323737931211956612002064275520162 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 24.xbar_same_source.70975862930398002039832562465707322115016146323737931211956612002064275520162
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.45378437283313035386995068564995832875230058346669856424928956962204411515739
Short name T308
Test name
Test status
Simulation time 669983435 ps
CPU time 4.05 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 01:57:58 PM PST 23
Peak memory 203064 kb
Host smart-dd157ba5-4132-4b0b-9a17-6edc41709f59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45378437283313035386995068564995832875230058346669856424928956962204411515739 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 24.xbar_smoke.45378437283313035386995068564995832875230058346669856424928956962204411515739
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.98986643708010449338495783587202432528143891437119391385201891325905845883536
Short name T70
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.28 seconds
Started Nov 22 01:57:42 PM PST 23
Finished Nov 22 01:58:33 PM PST 23
Peak memory 203116 kb
Host smart-381ff215-de7d-4f66-85f8-25d86291e250
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=98986643708010449338495783587202432528143891437119391385201891325905845883536 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.98986643708010449338495783587202432528143891437119391385201891325905845883536
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.22829250856927821127363421490227860752283444376557482322307691047313110648748
Short name T312
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.47 seconds
Started Nov 22 01:57:40 PM PST 23
Finished Nov 22 01:58:30 PM PST 23
Peak memory 203276 kb
Host smart-a042e58f-4da9-42fd-b5ad-68f5fd97fef6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=22829250856927821127363421490227860752283444376557482322307691047313110648748 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.22829250856927821127363421490227860752283444376557482322307691047313110648748
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.37811218510546718090540880650005616918688372568931202316520355104071499014331
Short name T837
Test name
Test status
Simulation time 116233435 ps
CPU time 2.48 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 01:57:56 PM PST 23
Peak memory 203092 kb
Host smart-063fcfd7-70f7-43ce-9fdd-a2d2657312a1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37811218510546718090540880650005616918688372568931202316520355104071499014331 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.37811218510546718090540880650005616918688372568931202316520355104071499014331
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.92445169043714420555795718915007162680067586907194217194139951071494365301561
Short name T303
Test name
Test status
Simulation time 18904859184 ps
CPU time 143.29 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 02:00:17 PM PST 23
Peak memory 205852 kb
Host smart-034773b7-14b5-4093-8729-0a9ccaf86098
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92445169043714420555795718915007162680067586907194217194139951071494365301561 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 24.xbar_stress_all.92445169043714420555795718915007162680067586907194217194139951071494365301561
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.56637535207552783253875891085900067868388331145337779471707505468100441578762
Short name T553
Test name
Test status
Simulation time 18894549184 ps
CPU time 118.24 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:59:50 PM PST 23
Peak memory 211352 kb
Host smart-1b200b59-359c-4047-87bf-0e3553075734
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56637535207552783253875891085900067868388331145337779471707505468100441578762 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 24.xbar_stress_all_with_error.56637535207552783253875891085900067868388331145337779471707505468100441578762
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.108697854022969176731059696296665877328664036754730568452007240968414388819530
Short name T881
Test name
Test status
Simulation time 5188549184 ps
CPU time 294.24 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 02:02:47 PM PST 23
Peak memory 208444 kb
Host smart-123a96bf-1a34-4e24-aaca-11c95cec441d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=108697854022969176731059696296665877328664036754730568452007240968414388819530 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.108697854022969176731059696296665877328664036754730568452007240968414388819530
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.8530128555743510089058157827184888210938747770819175876637891148629803260092
Short name T718
Test name
Test status
Simulation time 5188549184 ps
CPU time 221.63 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 02:01:35 PM PST 23
Peak memory 219624 kb
Host smart-9811f621-b1a7-4eb0-b055-eae7ed7427cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8530128555743510089058157827184888210938747770819175876637891148629803260092 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.8530128555743510089058157827184888210938747770819175876637891148629803260092
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.91856177926548391289446318373778262708114418636886831332524863883938606122107
Short name T233
Test name
Test status
Simulation time 3307045935 ps
CPU time 31.21 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 01:58:26 PM PST 23
Peak memory 211388 kb
Host smart-88de6f84-f88b-4bbb-a23e-21072412191b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91856177926548391289446318373778262708114418636886831332524863883938606122107 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 24.xbar_unmapped_addr.91856177926548391289446318373778262708114418636886831332524863883938606122107
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.24515304819431453564806997927113107715572083506985993485212196931366735853506
Short name T876
Test name
Test status
Simulation time 7399045935 ps
CPU time 68.26 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 01:59:01 PM PST 23
Peak memory 206144 kb
Host smart-6da46919-cb92-4fa6-8cd4-0c3ad449fc51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24515304819431453564806997927113107715572083506985993485212196931366735853506 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.24515304819431453564806997927113107715572083506985993485212196931366735853506
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.60035971529802597452608709004983590818661487082818307418537531341417328163127
Short name T451
Test name
Test status
Simulation time 304288045935 ps
CPU time 782.37 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 02:10:57 PM PST 23
Peak memory 211400 kb
Host smart-f2c9afb5-636b-4d5d-8368-3a652e8e7356
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=60035971529802597452608709004983590818661487082818307418537531341417328163127 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.60035971529802597452608709004983590818661487082818307418537531341417328163127
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.33939367917622887037059226592402057228165906301939241606572196118498414636144
Short name T887
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.07 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 01:58:20 PM PST 23
Peak memory 203312 kb
Host smart-80612ebd-48f1-4311-adaf-c383c50baacf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33939367917622887037059226592402057228165906301939241606572196118498414636144 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.33939367917622887037059226592402057228165906301939241606572196118498414636144
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.10233630743751799195232248156954860886323082869122556821785998977545168942342
Short name T454
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.9 seconds
Started Nov 22 01:57:56 PM PST 23
Finished Nov 22 01:58:34 PM PST 23
Peak memory 203296 kb
Host smart-b4f7d350-5402-4030-aa58-f0d401d7dc96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10233630743751799195232248156954860886323082869122556821785998977545168942342 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 25.xbar_error_random.10233630743751799195232248156954860886323082869122556821785998977545168942342
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.7554392071990937792540297638309433058732825137190560433027391939586228704402
Short name T826
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.31 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 01:58:32 PM PST 23
Peak memory 211424 kb
Host smart-4269d1a0-1ef7-4a10-ab70-b95618749b52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=7554392071990937792540297638309433058732825137190560433027391939586228704402 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 25.xbar_random.7554392071990937792540297638309433058732825137190560433027391939586228704402
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.106658771955674279278007343587046957500462351910886609284608676803229081561206
Short name T172
Test name
Test status
Simulation time 188793233435 ps
CPU time 324.09 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 02:03:15 PM PST 23
Peak memory 204796 kb
Host smart-11b9a641-9f2b-4bb6-854b-579ca137a5fb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=106658771955674279278007343587046957500462351910886609284608676803229081561206 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.106658771955674279278007343587046957500462351910886609284608676803229081561206
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.101483598465096342746140134785755143157358145785532517873455269968864846611692
Short name T444
Test name
Test status
Simulation time 126189108435 ps
CPU time 323.65 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 02:03:19 PM PST 23
Peak memory 211376 kb
Host smart-f222ae4c-68f6-42f2-a001-82afbbed1152
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=101483598465096342746140134785755143157358145785532517873455269968864846611692 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.101483598465096342746140134785755143157358145785532517873455269968864846611692
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.69681561288825119584451378801687841818030808718775544734280415319397806567627
Short name T598
Test name
Test status
Simulation time 766920935 ps
CPU time 26.9 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 01:58:17 PM PST 23
Peak memory 203932 kb
Host smart-97191954-b206-4f45-b8d1-7f46fa211e87
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69681561288825119584451378801687841818030808718775544734280415319397806567627 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.69681561288825119584451378801687841818030808718775544734280415319397806567627
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.14941293486410887575480906170791366104470010908574399081536498762128944197729
Short name T885
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.41 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 01:58:32 PM PST 23
Peak memory 204232 kb
Host smart-b51389d1-0275-4bbe-8c4d-96d8f0de4284
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14941293486410887575480906170791366104470010908574399081536498762128944197729 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 25.xbar_same_source.14941293486410887575480906170791366104470010908574399081536498762128944197729
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.100994085793063446996107114750818687892706241413482333402676875034252245755344
Short name T586
Test name
Test status
Simulation time 669983435 ps
CPU time 4.09 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:57:56 PM PST 23
Peak memory 203024 kb
Host smart-0e3be15a-730f-488d-b800-2b111e783cfa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100994085793063446996107114750818687892706241413482333402676875034252245755344 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 25.xbar_smoke.100994085793063446996107114750818687892706241413482333402676875034252245755344
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.23498116684110973181896055738887711701943271394133500500885925259772767652247
Short name T897
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.44 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:39 PM PST 23
Peak memory 203248 kb
Host smart-65cf9b9b-4cbf-477a-90ff-5d0532f447df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=23498116684110973181896055738887711701943271394133500500885925259772767652247 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.23498116684110973181896055738887711701943271394133500500885925259772767652247
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.83787249802212887090166024817473622009548346110375683362748813957330447308131
Short name T130
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.92 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 01:58:38 PM PST 23
Peak memory 203200 kb
Host smart-bc2f53b3-00f4-474d-89b0-74ab71bfdab7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=83787249802212887090166024817473622009548346110375683362748813957330447308131 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.83787249802212887090166024817473622009548346110375683362748813957330447308131
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.70268166382042548022835319933858317820562103249137466714254840539145095486150
Short name T235
Test name
Test status
Simulation time 116233435 ps
CPU time 2.4 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 01:57:53 PM PST 23
Peak memory 203172 kb
Host smart-beda45c4-2d2b-4e9b-afc3-715e9b6572bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70268166382042548022835319933858317820562103249137466714254840539145095486150 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.70268166382042548022835319933858317820562103249137466714254840539145095486150
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.64882020858568238141976122827028159054220973945441123069406449623693047761884
Short name T613
Test name
Test status
Simulation time 18904859184 ps
CPU time 129.14 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 02:00:03 PM PST 23
Peak memory 205656 kb
Host smart-3e4d3dd4-bf94-4534-abf5-9890107f8b6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64882020858568238141976122827028159054220973945441123069406449623693047761884 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 25.xbar_stress_all.64882020858568238141976122827028159054220973945441123069406449623693047761884
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.68403803257477232941340152616906630868413146082225415931154034605284264305267
Short name T469
Test name
Test status
Simulation time 18894549184 ps
CPU time 113.09 seconds
Started Nov 22 01:57:54 PM PST 23
Finished Nov 22 01:59:49 PM PST 23
Peak memory 211336 kb
Host smart-67631cc8-3e6c-46d5-a9eb-194a2c3cda46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68403803257477232941340152616906630868413146082225415931154034605284264305267 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 25.xbar_stress_all_with_error.68403803257477232941340152616906630868413146082225415931154034605284264305267
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.106799028315162395671929455652974325585792536042536741063370155531594151827906
Short name T311
Test name
Test status
Simulation time 5188549184 ps
CPU time 299.41 seconds
Started Nov 22 01:57:55 PM PST 23
Finished Nov 22 02:02:57 PM PST 23
Peak memory 208568 kb
Host smart-de036a2f-1983-4f9b-88e8-b72fe024151d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=106799028315162395671929455652974325585792536042536741063370155531594151827906 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.106799028315162395671929455652974325585792536042536741063370155531594151827906
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.94303649512197569043635536700236498163246358377532968592133859005463955758404
Short name T368
Test name
Test status
Simulation time 5188549184 ps
CPU time 224.96 seconds
Started Nov 22 01:57:54 PM PST 23
Finished Nov 22 02:01:41 PM PST 23
Peak memory 219516 kb
Host smart-aa58b089-2d2c-48aa-8ca0-6882ae95259d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94303649512197569043635536700236498163246358377532968592133859005463955758404 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.94303649512197569043635536700236498163246358377532968592133859005463955758404
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.33334007800492404150453570401208301250564502360817912091238537464802394369133
Short name T716
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.42 seconds
Started Nov 22 01:57:54 PM PST 23
Finished Nov 22 01:58:25 PM PST 23
Peak memory 211388 kb
Host smart-ba13b786-acb1-422a-bb88-2c6e82e7debc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33334007800492404150453570401208301250564502360817912091238537464802394369133 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 25.xbar_unmapped_addr.33334007800492404150453570401208301250564502360817912091238537464802394369133
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.113463438142146338300387102664693108997508745558694564391051032440098705219960
Short name T78
Test name
Test status
Simulation time 7399045935 ps
CPU time 58.89 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 01:58:52 PM PST 23
Peak memory 206304 kb
Host smart-5701d345-1431-49b2-ae2d-026454cc4cac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=113463438142146338300387102664693108997508745558694564391051032440098705219960 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.113463438142146338300387102664693108997508745558694564391051032440098705219960
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.6585053956860413599712528844557350031966856202311644078814653502603299779326
Short name T710
Test name
Test status
Simulation time 304288045935 ps
CPU time 779.33 seconds
Started Nov 22 01:57:54 PM PST 23
Finished Nov 22 02:10:55 PM PST 23
Peak memory 211348 kb
Host smart-49f9a1b5-507a-4a0e-8c2e-c6249684de1a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=6585053956860413599712528844557350031966856202311644078814653502603299779326 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build
_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.6585053956860413599712528844557350031966856202311644078814653502603299779326
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.81745132288713452315619738318025891874592606847231881656394965212620426926245
Short name T11
Test name
Test status
Simulation time 3310545935 ps
CPU time 29.38 seconds
Started Nov 22 01:57:56 PM PST 23
Finished Nov 22 01:58:27 PM PST 23
Peak memory 203356 kb
Host smart-0ed8c1bb-a348-49c1-aebd-9036224bcc41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81745132288713452315619738318025891874592606847231881656394965212620426926245 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.81745132288713452315619738318025891874592606847231881656394965212620426926245
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.102088694026729265670306345088920185887345817652027779319248456524383416619268
Short name T191
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.24 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 01:58:31 PM PST 23
Peak memory 203356 kb
Host smart-114556cc-bcb0-42d6-87ca-6d49a457b308
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102088694026729265670306345088920185887345817652027779319248456524383416619268 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_l
og /dev/null -cm_name 26.xbar_error_random.102088694026729265670306345088920185887345817652027779319248456524383416619268
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.53138158626422115680230971002573054605421059511686741110836219902088588116350
Short name T630
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.22 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:27 PM PST 23
Peak memory 211416 kb
Host smart-4a009455-7bc9-4f02-9fc7-bc7b7a88bc40
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53138158626422115680230971002573054605421059511686741110836219902088588116350 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 26.xbar_random.53138158626422115680230971002573054605421059511686741110836219902088588116350
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.99320219496700747745002044898843635960993539060939878384899912910539385269411
Short name T244
Test name
Test status
Simulation time 188793233435 ps
CPU time 329.43 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 02:03:23 PM PST 23
Peak memory 204744 kb
Host smart-82e4f65d-59e1-4995-aab4-31646230a39d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=99320219496700747745002044898843635960993539060939878384899912910539385269411 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 26.xbar_random_large_delays.99320219496700747745002044898843635960993539060939878384899912910539385269411
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.28093873370419371794282798190234319800857198661685849376488376334063066367356
Short name T154
Test name
Test status
Simulation time 126189108435 ps
CPU time 320.94 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 02:03:14 PM PST 23
Peak memory 211416 kb
Host smart-937230c2-15dc-42be-9318-1f0a172c0bc5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=28093873370419371794282798190234319800857198661685849376488376334063066367356 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.28093873370419371794282798190234319800857198661685849376488376334063066367356
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.50298055002811176855684321024489825926763776513832304298450541415193823714138
Short name T296
Test name
Test status
Simulation time 766920935 ps
CPU time 24.93 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 01:58:19 PM PST 23
Peak memory 203780 kb
Host smart-b63859ad-5238-4ee3-9d1f-ecc03f83e5fa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50298055002811176855684321024489825926763776513832304298450541415193823714138 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.50298055002811176855684321024489825926763776513832304298450541415193823714138
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.25746854359495384940178054594493364270244290472010951454155759646231958758128
Short name T4
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.61 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 01:58:29 PM PST 23
Peak memory 204276 kb
Host smart-8e5e5100-7389-4b2b-8f75-d11c6e8bed60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25746854359495384940178054594493364270244290472010951454155759646231958758128 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 26.xbar_same_source.25746854359495384940178054594493364270244290472010951454155759646231958758128
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.75072443392526453548180732457670453490944100579749190615354095058308759127592
Short name T458
Test name
Test status
Simulation time 669983435 ps
CPU time 4.17 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 01:57:59 PM PST 23
Peak memory 203144 kb
Host smart-554a18e9-df79-4175-ba76-e9bbc42210f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=75072443392526453548180732457670453490944100579749190615354095058308759127592 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 26.xbar_smoke.75072443392526453548180732457670453490944100579749190615354095058308759127592
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.38856355965621030941225669236876128946211143343152533452433091647843260873137
Short name T40
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.86 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 01:58:40 PM PST 23
Peak memory 203252 kb
Host smart-543b1b97-29aa-478a-9ade-6f369c2e2d72
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=38856355965621030941225669236876128946211143343152533452433091647843260873137 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.38856355965621030941225669236876128946211143343152533452433091647843260873137
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.69409419673016145957844713007713673528676453775727264603091575543494542904204
Short name T423
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.53 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 01:58:39 PM PST 23
Peak memory 203276 kb
Host smart-df696277-1461-4044-acfe-13a45b61e0f3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=69409419673016145957844713007713673528676453775727264603091575543494542904204 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.69409419673016145957844713007713673528676453775727264603091575543494542904204
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.99801574184442754613919396172851407008423855070097163449723527367472646900543
Short name T366
Test name
Test status
Simulation time 116233435 ps
CPU time 2.41 seconds
Started Nov 22 01:57:49 PM PST 23
Finished Nov 22 01:57:52 PM PST 23
Peak memory 202976 kb
Host smart-818ffc1f-5ecb-41ed-9b6e-169935d24372
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99801574184442754613919396172851407008423855070097163449723527367472646900543 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.99801574184442754613919396172851407008423855070097163449723527367472646900543
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.57057121182148683115719447566188712461400859670467012534218039834656042887972
Short name T57
Test name
Test status
Simulation time 18904859184 ps
CPU time 132.13 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 02:00:06 PM PST 23
Peak memory 205812 kb
Host smart-c84fe9a1-ce4a-4f84-94b0-fa9a1613b2c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57057121182148683115719447566188712461400859670467012534218039834656042887972 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 26.xbar_stress_all.57057121182148683115719447566188712461400859670467012534218039834656042887972
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.11561964313426094897214707528169020317846504375222707902547794938632852136772
Short name T151
Test name
Test status
Simulation time 18894549184 ps
CPU time 121.65 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 01:59:55 PM PST 23
Peak memory 211512 kb
Host smart-dd2911d0-dd90-4d47-9b15-9d724c4121fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=11561964313426094897214707528169020317846504375222707902547794938632852136772 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 26.xbar_stress_all_with_error.11561964313426094897214707528169020317846504375222707902547794938632852136772
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.73109237970501279612063467225330944893975178509496591981159077272037188362492
Short name T789
Test name
Test status
Simulation time 5188549184 ps
CPU time 292.66 seconds
Started Nov 22 01:57:54 PM PST 23
Finished Nov 22 02:02:49 PM PST 23
Peak memory 208404 kb
Host smart-5d771e8e-da4b-43b1-aeda-05d0540cd6fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73109237970501279612063467225330944893975178509496591981159077272037188362492 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.73109237970501279612063467225330944893975178509496591981159077272037188362492
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.110692525970628376290085012699994824636525375976560324243530753709840330524448
Short name T578
Test name
Test status
Simulation time 5188549184 ps
CPU time 221.73 seconds
Started Nov 22 01:57:55 PM PST 23
Finished Nov 22 02:01:38 PM PST 23
Peak memory 219352 kb
Host smart-c2b41dbf-4c0e-42c3-9d29-dbffaf012065
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110692525970628376290085012699994824636525375976560324243530753709840330524448 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.110692525970628376290085012699994824636525375976560324243530753709840330524448
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.107902808436500140632856787103546418185650590754322201893794904531661998304275
Short name T689
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.15 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:20 PM PST 23
Peak memory 211488 kb
Host smart-29006e4e-432b-4b82-b62f-8e46fd1c3183
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=107902808436500140632856787103546418185650590754322201893794904531661998304275 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 26.xbar_unmapped_addr.107902808436500140632856787103546418185650590754322201893794904531661998304275
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1149335775175699709788775895267033133778367828369217095534366815099429171522
Short name T686
Test name
Test status
Simulation time 7399045935 ps
CPU time 67.39 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 01:59:01 PM PST 23
Peak memory 211460 kb
Host smart-9fea3e1f-b1bf-4caf-8482-cce0ab2f0053
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1149335775175699709788775895267033133778367828369217095534366815099429171522 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1149335775175699709788775895267033133778367828369217095534366815099429171522
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.19036812009548658708489127676726491661670081234713392539047885322915717889605
Short name T673
Test name
Test status
Simulation time 304288045935 ps
CPU time 779.11 seconds
Started Nov 22 01:57:57 PM PST 23
Finished Nov 22 02:10:58 PM PST 23
Peak memory 211440 kb
Host smart-09be7f2f-9a07-4695-8394-dde0fe686fd8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=19036812009548658708489127676726491661670081234713392539047885322915717889605 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.19036812009548658708489127676726491661670081234713392539047885322915717889605
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.46983856335514818646725453759997055319054766437584069142254465580199789062537
Short name T340
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.73 seconds
Started Nov 22 01:57:57 PM PST 23
Finished Nov 22 01:58:26 PM PST 23
Peak memory 203308 kb
Host smart-ab542527-cacb-4ac0-aaee-75e3c54dd0d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46983856335514818646725453759997055319054766437584069142254465580199789062537 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.46983856335514818646725453759997055319054766437584069142254465580199789062537
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.83500882099293695555982512234007182741779892334615426209497552294104945401412
Short name T506
Test name
Test status
Simulation time 4402420935 ps
CPU time 39.59 seconds
Started Nov 22 01:57:57 PM PST 23
Finished Nov 22 01:58:38 PM PST 23
Peak memory 203264 kb
Host smart-ddd9deb0-6505-44cc-a9cd-35ae44f5dcd3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83500882099293695555982512234007182741779892334615426209497552294104945401412 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 27.xbar_error_random.83500882099293695555982512234007182741779892334615426209497552294104945401412
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.89122822731667959131002957053433546979751594827913545322586433120946271303235
Short name T190
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.95 seconds
Started Nov 22 01:57:55 PM PST 23
Finished Nov 22 01:58:34 PM PST 23
Peak memory 211384 kb
Host smart-3d83a306-631b-46c2-bec3-10f9fd842376
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89122822731667959131002957053433546979751594827913545322586433120946271303235 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 27.xbar_random.89122822731667959131002957053433546979751594827913545322586433120946271303235
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1378768485856532714175094183883944095890767071252927647524636985662956025734
Short name T758
Test name
Test status
Simulation time 188793233435 ps
CPU time 313.53 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 02:03:09 PM PST 23
Peak memory 204676 kb
Host smart-622097b4-95db-48c4-ac19-da5b6a867974
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378768485856532714175094183883944095890767071252927647524636985662956025734 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1378768485856532714175094183883944095890767071252927647524636985662956025734
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.13390145504314401725262475485466435535894667985245347192796031419391316087111
Short name T83
Test name
Test status
Simulation time 126189108435 ps
CPU time 323.96 seconds
Started Nov 22 01:57:55 PM PST 23
Finished Nov 22 02:03:21 PM PST 23
Peak memory 211476 kb
Host smart-da384bb1-5fc6-42bc-a7bf-d1c220bd5bd0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=13390145504314401725262475485466435535894667985245347192796031419391316087111 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.13390145504314401725262475485466435535894667985245347192796031419391316087111
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.79078461303123791243348826935490952595993658137881554925634180349143325689357
Short name T198
Test name
Test status
Simulation time 766920935 ps
CPU time 24.8 seconds
Started Nov 22 01:57:55 PM PST 23
Finished Nov 22 01:58:21 PM PST 23
Peak memory 203852 kb
Host smart-16858f09-68ba-475e-8e5a-0b478d19bd54
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79078461303123791243348826935490952595993658137881554925634180349143325689357 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.79078461303123791243348826935490952595993658137881554925634180349143325689357
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.9357393671194366869453854674065746126017487404466811375794276703292994074579
Short name T268
Test name
Test status
Simulation time 7116170935 ps
CPU time 39.49 seconds
Started Nov 22 01:57:56 PM PST 23
Finished Nov 22 01:58:37 PM PST 23
Peak memory 204296 kb
Host smart-271d8699-2303-4978-b47f-e24ab02af45e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=9357393671194366869453854674065746126017487404466811375794276703292994074579 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 27.xbar_same_source.9357393671194366869453854674065746126017487404466811375794276703292994074579
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.402893795107702007259769141614430784849604090289840118326018912095198579518
Short name T371
Test name
Test status
Simulation time 669983435 ps
CPU time 4.19 seconds
Started Nov 22 01:57:54 PM PST 23
Finished Nov 22 01:58:01 PM PST 23
Peak memory 203136 kb
Host smart-0684cdea-dd4f-42d9-9713-0e06c934a280
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=402893795107702007259769141614430784849604090289840118326018912095198579518 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /d
ev/null -cm_name 27.xbar_smoke.402893795107702007259769141614430784849604090289840118326018912095198579518
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.66842118211545037978061219630503420636908033952996443585583979600732312010708
Short name T501
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.44 seconds
Started Nov 22 01:57:51 PM PST 23
Finished Nov 22 01:58:41 PM PST 23
Peak memory 203248 kb
Host smart-4e1e3023-8b66-4bb5-8bcb-63b4f0eefe91
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=66842118211545037978061219630503420636908033952996443585583979600732312010708 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.66842118211545037978061219630503420636908033952996443585583979600732312010708
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.66397648843804797441726697062071686687671733503644320282545075029756022429007
Short name T567
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.45 seconds
Started Nov 22 01:57:52 PM PST 23
Finished Nov 22 01:58:40 PM PST 23
Peak memory 203280 kb
Host smart-0d7c2112-1b2d-4f0a-acdf-a2dc01b66349
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=66397648843804797441726697062071686687671733503644320282545075029756022429007 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.66397648843804797441726697062071686687671733503644320282545075029756022429007
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.40180863090144275300430812420050333122076799983536987445630835056879813563906
Short name T533
Test name
Test status
Simulation time 116233435 ps
CPU time 2.46 seconds
Started Nov 22 01:57:54 PM PST 23
Finished Nov 22 01:57:58 PM PST 23
Peak memory 203140 kb
Host smart-ea80206a-9ee0-4087-8f7c-dc4e177fb831
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40180863090144275300430812420050333122076799983536987445630835056879813563906 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.40180863090144275300430812420050333122076799983536987445630835056879813563906
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.89794400662649100378380409990198100890939789884467084374184279173368923492978
Short name T720
Test name
Test status
Simulation time 18904859184 ps
CPU time 133.19 seconds
Started Nov 22 01:57:55 PM PST 23
Finished Nov 22 02:00:10 PM PST 23
Peak memory 205788 kb
Host smart-660fb742-e7e2-491a-820b-c2130f32ce3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89794400662649100378380409990198100890939789884467084374184279173368923492978 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 27.xbar_stress_all.89794400662649100378380409990198100890939789884467084374184279173368923492978
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.72186039950228087858186799035106615953194374220124740464087073776407199870840
Short name T879
Test name
Test status
Simulation time 18894549184 ps
CPU time 126.67 seconds
Started Nov 22 01:58:09 PM PST 23
Finished Nov 22 02:00:16 PM PST 23
Peak memory 211396 kb
Host smart-9340849a-3462-4593-9073-a673edba281c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=72186039950228087858186799035106615953194374220124740464087073776407199870840 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 27.xbar_stress_all_with_error.72186039950228087858186799035106615953194374220124740464087073776407199870840
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.76616210095540153626114837272611060696261452346579748379258866290419095196629
Short name T640
Test name
Test status
Simulation time 5188549184 ps
CPU time 298.54 seconds
Started Nov 22 01:57:56 PM PST 23
Finished Nov 22 02:02:57 PM PST 23
Peak memory 208416 kb
Host smart-3bb21b20-e320-45f2-906a-e52897d07d11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76616210095540153626114837272611060696261452346579748379258866290419095196629 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.76616210095540153626114837272611060696261452346579748379258866290419095196629
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.31509443101151392776709821201999091121940067915935648706781157673953793798263
Short name T896
Test name
Test status
Simulation time 5188549184 ps
CPU time 222.61 seconds
Started Nov 22 01:58:11 PM PST 23
Finished Nov 22 02:01:55 PM PST 23
Peak memory 219624 kb
Host smart-c1f2f278-2053-443f-9ed9-915b8f17e1b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=31509443101151392776709821201999091121940067915935648706781157673953793798263 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.31509443101151392776709821201999091121940067915935648706781157673953793798263
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.81478234883691452651460774932405860420263690109054441894222792226160233686907
Short name T86
Test name
Test status
Simulation time 3307045935 ps
CPU time 30.18 seconds
Started Nov 22 01:57:50 PM PST 23
Finished Nov 22 01:58:22 PM PST 23
Peak memory 211460 kb
Host smart-26f4c210-31fb-4636-bc9d-df6a4df64c07
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81478234883691452651460774932405860420263690109054441894222792226160233686907 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 27.xbar_unmapped_addr.81478234883691452651460774932405860420263690109054441894222792226160233686907
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.34129767097791983766377059933439832214987098238868808620506602893017059290396
Short name T271
Test name
Test status
Simulation time 304288045935 ps
CPU time 766.01 seconds
Started Nov 22 01:57:55 PM PST 23
Finished Nov 22 02:10:43 PM PST 23
Peak memory 211344 kb
Host smart-6c050420-25eb-47ca-9fbd-b9e606280dea
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=34129767097791983766377059933439832214987098238868808620506602893017059290396 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.34129767097791983766377059933439832214987098238868808620506602893017059290396
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.92054330099471819741540939017398511702415059810875876228714126393120635266792
Short name T124
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.24 seconds
Started Nov 22 01:58:09 PM PST 23
Finished Nov 22 01:58:38 PM PST 23
Peak memory 203396 kb
Host smart-1163d933-4548-4169-b708-59a927010053
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92054330099471819741540939017398511702415059810875876228714126393120635266792 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.92054330099471819741540939017398511702415059810875876228714126393120635266792
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.20504766129371985553935658181484380622131363014939736945643429022349868772691
Short name T223
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.89 seconds
Started Nov 22 01:57:55 PM PST 23
Finished Nov 22 01:58:31 PM PST 23
Peak memory 203072 kb
Host smart-9ea0baa6-f57f-4bb4-808d-01b1f7181c3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20504766129371985553935658181484380622131363014939736945643429022349868772691 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 28.xbar_error_random.20504766129371985553935658181484380622131363014939736945643429022349868772691
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.97375155110597441562140498073403942147239792764860498386203217704160950763390
Short name T34
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.92 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 01:58:47 PM PST 23
Peak memory 211496 kb
Host smart-b1cd728f-3c60-4b61-9877-d682b616ff7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=97375155110597441562140498073403942147239792764860498386203217704160950763390 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 28.xbar_random.97375155110597441562140498073403942147239792764860498386203217704160950763390
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.32468285718109511518028049143188348224788944283294156125979338816890031207432
Short name T43
Test name
Test status
Simulation time 188793233435 ps
CPU time 321.99 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 02:03:17 PM PST 23
Peak memory 204676 kb
Host smart-48ca0162-59e5-4753-aefc-06d20082c761
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=32468285718109511518028049143188348224788944283294156125979338816890031207432 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 28.xbar_random_large_delays.32468285718109511518028049143188348224788944283294156125979338816890031207432
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.23833974457144417883066529747148738366787494797696058934759607200180627102965
Short name T755
Test name
Test status
Simulation time 126189108435 ps
CPU time 326.47 seconds
Started Nov 22 01:57:56 PM PST 23
Finished Nov 22 02:03:24 PM PST 23
Peak memory 211368 kb
Host smart-df86fe25-2cd1-47f1-82d1-4fafec831e95
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=23833974457144417883066529747148738366787494797696058934759607200180627102965 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.23833974457144417883066529747148738366787494797696058934759607200180627102965
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.108190110207252757617673846715785342476059415795085545400426012524437021949167
Short name T316
Test name
Test status
Simulation time 766920935 ps
CPU time 24.12 seconds
Started Nov 22 01:58:11 PM PST 23
Finished Nov 22 01:58:36 PM PST 23
Peak memory 203848 kb
Host smart-357ddebc-5855-4d69-ab2a-424ff342308d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108190110207252757617673846715785342476059415795085545400426012524437021949167 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.108190110207252757617673846715785342476059415795085545400426012524437021949167
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.87667531283220402813896866221456575320404883054195267878421575893621275619219
Short name T615
Test name
Test status
Simulation time 7116170935 ps
CPU time 35.94 seconds
Started Nov 22 01:57:53 PM PST 23
Finished Nov 22 01:58:31 PM PST 23
Peak memory 204180 kb
Host smart-66daa13d-e82a-4701-a3da-22400b1d3c1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87667531283220402813896866221456575320404883054195267878421575893621275619219 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 28.xbar_same_source.87667531283220402813896866221456575320404883054195267878421575893621275619219
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.13620398794611858348233329567122832572032793697523451502705746581302338368959
Short name T479
Test name
Test status
Simulation time 669983435 ps
CPU time 4.29 seconds
Started Nov 22 01:57:55 PM PST 23
Finished Nov 22 01:58:01 PM PST 23
Peak memory 203140 kb
Host smart-aab8671b-d618-4b02-a8ca-8b7951b8aff3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13620398794611858348233329567122832572032793697523451502705746581302338368959 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 28.xbar_smoke.13620398794611858348233329567122832572032793697523451502705746581302338368959
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.34719596907491629576870967004929084301365922296459899240808664889862569665909
Short name T416
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.89 seconds
Started Nov 22 01:58:07 PM PST 23
Finished Nov 22 01:58:56 PM PST 23
Peak memory 203160 kb
Host smart-19c1cd2f-f3f2-44fb-a03d-8aac64c60847
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=34719596907491629576870967004929084301365922296459899240808664889862569665909 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.34719596907491629576870967004929084301365922296459899240808664889862569665909
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.11348089072424461583485647957079377233325779258916342699535805216392554034889
Short name T231
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.02 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 01:58:53 PM PST 23
Peak memory 203264 kb
Host smart-25466bb5-0e7a-4a72-8495-cd52cc2087a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=11348089072424461583485647957079377233325779258916342699535805216392554034889 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.11348089072424461583485647957079377233325779258916342699535805216392554034889
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.83423127849455826919282873774132040139218814930733860077308825342749235287408
Short name T650
Test name
Test status
Simulation time 116233435 ps
CPU time 2.49 seconds
Started Nov 22 01:57:54 PM PST 23
Finished Nov 22 01:57:58 PM PST 23
Peak memory 203140 kb
Host smart-34988e35-ffdd-4206-8266-f97323931370
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83423127849455826919282873774132040139218814930733860077308825342749235287408 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.83423127849455826919282873774132040139218814930733860077308825342749235287408
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.33862617952544235352485301857289501982781900652327806553605931948069398653923
Short name T612
Test name
Test status
Simulation time 18904859184 ps
CPU time 136.16 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 02:00:25 PM PST 23
Peak memory 205852 kb
Host smart-78f171b7-62ca-4b4e-9b75-e4d067d74fce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33862617952544235352485301857289501982781900652327806553605931948069398653923 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 28.xbar_stress_all.33862617952544235352485301857289501982781900652327806553605931948069398653923
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.76410193982042326477063060684584888358506029720262516744297512683083068181896
Short name T117
Test name
Test status
Simulation time 18894549184 ps
CPU time 126.3 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 02:00:16 PM PST 23
Peak memory 211440 kb
Host smart-e0475906-34b2-460b-87d6-de53d42000a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76410193982042326477063060684584888358506029720262516744297512683083068181896 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 28.xbar_stress_all_with_error.76410193982042326477063060684584888358506029720262516744297512683083068181896
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.63985867807277634286434826500118781425598345623206879368798930774096680340423
Short name T443
Test name
Test status
Simulation time 5188549184 ps
CPU time 294.84 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 02:03:03 PM PST 23
Peak memory 208508 kb
Host smart-b375c64b-75c9-4433-bfcb-ba4e59413a0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=63985867807277634286434826500118781425598345623206879368798930774096680340423 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.63985867807277634286434826500118781425598345623206879368798930774096680340423
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.7867190486828829596552429440578943758030732060636472236823866180432623178737
Short name T813
Test name
Test status
Simulation time 5188549184 ps
CPU time 227.21 seconds
Started Nov 22 01:58:09 PM PST 23
Finished Nov 22 02:01:57 PM PST 23
Peak memory 219624 kb
Host smart-e69a9c04-89c2-4179-8cac-1e142e377eee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=7867190486828829596552429440578943758030732060636472236823866180432623178737 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.7867190486828829596552429440578943758030732060636472236823866180432623178737
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.85635458267523170933885667649487503621073460146291140209562966453433742209089
Short name T73
Test name
Test status
Simulation time 3307045935 ps
CPU time 30.21 seconds
Started Nov 22 01:57:56 PM PST 23
Finished Nov 22 01:58:28 PM PST 23
Peak memory 211388 kb
Host smart-47030b53-1af6-4169-93df-e29fc1329978
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85635458267523170933885667649487503621073460146291140209562966453433742209089 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 28.xbar_unmapped_addr.85635458267523170933885667649487503621073460146291140209562966453433742209089
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.111785852176206845546829202390963936495982819284362195307721456746194645277673
Short name T326
Test name
Test status
Simulation time 7399045935 ps
CPU time 64.17 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 01:59:15 PM PST 23
Peak memory 206232 kb
Host smart-7119b6d0-e73d-40a3-af88-338159029e9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111785852176206845546829202390963936495982819284362195307721456746194645277673 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.111785852176206845546829202390963936495982819284362195307721456746194645277673
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.48504607159908677973688575378940801631758211438512205747924283893291262373074
Short name T505
Test name
Test status
Simulation time 304288045935 ps
CPU time 780.76 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 02:11:10 PM PST 23
Peak memory 211492 kb
Host smart-376afe5e-24de-4cc9-b9e6-11c9c53e44c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=48504607159908677973688575378940801631758211438512205747924283893291262373074 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.48504607159908677973688575378940801631758211438512205747924283893291262373074
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.56741210049723493020235462093434245446492608989865007174307995753252845556465
Short name T629
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.38 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 01:58:38 PM PST 23
Peak memory 203300 kb
Host smart-f85b2c3c-16ef-4963-8c61-1614976b893f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56741210049723493020235462093434245446492608989865007174307995753252845556465 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.56741210049723493020235462093434245446492608989865007174307995753252845556465
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.112332342397009184464981565337554590737104092729323216531680251597698683020746
Short name T113
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.33 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 01:58:48 PM PST 23
Peak memory 203268 kb
Host smart-48958e6d-d92a-4cc0-8638-3b4851884b47
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112332342397009184464981565337554590737104092729323216531680251597698683020746 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_l
og /dev/null -cm_name 29.xbar_error_random.112332342397009184464981565337554590737104092729323216531680251597698683020746
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.11222975903765896910953928635458023928214761521531968414842791180266067304621
Short name T325
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.94 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 01:58:49 PM PST 23
Peak memory 211500 kb
Host smart-cf2c5cfb-a380-458c-8517-09e82717a69e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=11222975903765896910953928635458023928214761521531968414842791180266067304621 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 29.xbar_random.11222975903765896910953928635458023928214761521531968414842791180266067304621
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.58215821498928418265265026964337369857374993704749649845464459584029322893054
Short name T373
Test name
Test status
Simulation time 188793233435 ps
CPU time 326.61 seconds
Started Nov 22 01:58:11 PM PST 23
Finished Nov 22 02:03:39 PM PST 23
Peak memory 204764 kb
Host smart-7eb09118-2cf8-436f-94ed-069d7b131562
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=58215821498928418265265026964337369857374993704749649845464459584029322893054 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 29.xbar_random_large_delays.58215821498928418265265026964337369857374993704749649845464459584029322893054
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.65440950954613112822335552931561057905454308725493529238047412234267873225368
Short name T467
Test name
Test status
Simulation time 126189108435 ps
CPU time 330.88 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 02:03:40 PM PST 23
Peak memory 211452 kb
Host smart-c9d87ffc-a271-432f-83a1-332cb5c2055d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=65440950954613112822335552931561057905454308725493529238047412234267873225368 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.65440950954613112822335552931561057905454308725493529238047412234267873225368
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.80959074971680087666716995750051812180071921599148476127511243581423935827627
Short name T739
Test name
Test status
Simulation time 766920935 ps
CPU time 26.05 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 01:58:34 PM PST 23
Peak memory 203760 kb
Host smart-380e4c17-b673-441d-b2e9-4e3c5e4ae35e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80959074971680087666716995750051812180071921599148476127511243581423935827627 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.80959074971680087666716995750051812180071921599148476127511243581423935827627
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.115661832783345974192955439436306034867840180318774673912925318252577680316318
Short name T213
Test name
Test status
Simulation time 7116170935 ps
CPU time 36.32 seconds
Started Nov 22 01:58:19 PM PST 23
Finished Nov 22 01:58:56 PM PST 23
Peak memory 204316 kb
Host smart-bb1ea172-d3ee-4b73-b8c1-c5b0277574c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115661832783345974192955439436306034867840180318774673912925318252577680316318 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 29.xbar_same_source.115661832783345974192955439436306034867840180318774673912925318252577680316318
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.10160973443143528218370876067881496405419235338555934262911021540700835685067
Short name T647
Test name
Test status
Simulation time 669983435 ps
CPU time 4.21 seconds
Started Nov 22 01:58:06 PM PST 23
Finished Nov 22 01:58:11 PM PST 23
Peak memory 203084 kb
Host smart-67e3a553-5f92-4e2e-9729-ae4c514896f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10160973443143528218370876067881496405419235338555934262911021540700835685067 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 29.xbar_smoke.10160973443143528218370876067881496405419235338555934262911021540700835685067
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.63070390669190185190034705888842765082883509823411373343653081664292631721834
Short name T433
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.77 seconds
Started Nov 22 01:58:09 PM PST 23
Finished Nov 22 01:58:58 PM PST 23
Peak memory 203280 kb
Host smart-ea6dadc2-9bbc-44c9-835b-9b29c1d0ef3d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=63070390669190185190034705888842765082883509823411373343653081664292631721834 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.63070390669190185190034705888842765082883509823411373343653081664292631721834
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.47121310538499787540154172614547614662337499105355228075606581908061272346215
Short name T108
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.04 seconds
Started Nov 22 01:58:07 PM PST 23
Finished Nov 22 01:58:53 PM PST 23
Peak memory 203340 kb
Host smart-46ee1521-5249-4954-9ee4-5e4400d0aa43
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=47121310538499787540154172614547614662337499105355228075606581908061272346215 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.47121310538499787540154172614547614662337499105355228075606581908061272346215
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.66941849701924031623534767547412659523741575547575473254013543916576553355118
Short name T888
Test name
Test status
Simulation time 116233435 ps
CPU time 2.82 seconds
Started Nov 22 01:58:11 PM PST 23
Finished Nov 22 01:58:15 PM PST 23
Peak memory 203132 kb
Host smart-3de4fb5d-6e3b-4719-92e9-b4bc3655cd5b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66941849701924031623534767547412659523741575547575473254013543916576553355118 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.66941849701924031623534767547412659523741575547575473254013543916576553355118
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.53484191656315030664845233297191461366067801734346998579442549737574347966485
Short name T730
Test name
Test status
Simulation time 18904859184 ps
CPU time 133.58 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 02:00:24 PM PST 23
Peak memory 205740 kb
Host smart-7c28026f-981a-4b43-a778-f79dac4a02e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53484191656315030664845233297191461366067801734346998579442549737574347966485 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 29.xbar_stress_all.53484191656315030664845233297191461366067801734346998579442549737574347966485
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.90304766904206452306700823218651208241798851744429536860975898218979530736984
Short name T272
Test name
Test status
Simulation time 18894549184 ps
CPU time 124.68 seconds
Started Nov 22 01:58:12 PM PST 23
Finished Nov 22 02:00:18 PM PST 23
Peak memory 211400 kb
Host smart-470338ab-18de-472c-a603-15985c450127
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=90304766904206452306700823218651208241798851744429536860975898218979530736984 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 29.xbar_stress_all_with_error.90304766904206452306700823218651208241798851744429536860975898218979530736984
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.62306966518811436933422880160421035360946433668380895269362364488581060204832
Short name T547
Test name
Test status
Simulation time 5188549184 ps
CPU time 295.09 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 02:03:06 PM PST 23
Peak memory 208440 kb
Host smart-648403d5-8661-402a-ad1e-29dc924e8f5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62306966518811436933422880160421035360946433668380895269362364488581060204832 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.62306966518811436933422880160421035360946433668380895269362364488581060204832
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.55050689227605589776179833823291351427856785321083169734582224639822885004945
Short name T221
Test name
Test status
Simulation time 5188549184 ps
CPU time 224.8 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 02:01:54 PM PST 23
Peak memory 219628 kb
Host smart-dda1c83a-cd61-4c12-8056-2b67ec6a90c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55050689227605589776179833823291351427856785321083169734582224639822885004945 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.55050689227605589776179833823291351427856785321083169734582224639822885004945
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.62632917123250009773867260244698093872919108108025644372313401942109160484461
Short name T721
Test name
Test status
Simulation time 3307045935 ps
CPU time 27.13 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 01:58:35 PM PST 23
Peak memory 211348 kb
Host smart-3bb9dec5-59b2-49d2-acf5-c6fd21ee4704
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62632917123250009773867260244698093872919108108025644372313401942109160484461 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 29.xbar_unmapped_addr.62632917123250009773867260244698093872919108108025644372313401942109160484461
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.21305661258629294084943996628082883808857924254389032415154106456795033189073
Short name T320
Test name
Test status
Simulation time 7399045935 ps
CPU time 71.48 seconds
Started Nov 22 01:56:18 PM PST 23
Finished Nov 22 01:57:31 PM PST 23
Peak memory 211416 kb
Host smart-1d7043a6-8c67-4a00-b782-a53dc2638d24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=21305661258629294084943996628082883808857924254389032415154106456795033189073 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.21305661258629294084943996628082883808857924254389032415154106456795033189073
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.29025828551907524685422933967057042984420413240920745128906423903042456006503
Short name T804
Test name
Test status
Simulation time 304288045935 ps
CPU time 766.67 seconds
Started Nov 22 01:56:13 PM PST 23
Finished Nov 22 02:09:01 PM PST 23
Peak memory 211364 kb
Host smart-3af78166-1abf-41c2-9f9d-4f20d4ed0962
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=29025828551907524685422933967057042984420413240920745128906423903042456006503 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.29025828551907524685422933967057042984420413240920745128906423903042456006503
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.78990888260237356864816572434111757266640486863739232721905958131079080495264
Short name T192
Test name
Test status
Simulation time 3310545935 ps
CPU time 29.67 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 01:56:48 PM PST 23
Peak memory 203356 kb
Host smart-18ffd9e9-a697-4c36-a41a-a788eca5bf9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78990888260237356864816572434111757266640486863739232721905958131079080495264 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.78990888260237356864816572434111757266640486863739232721905958131079080495264
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.73295720901669806007347464369150151495807176144552527512698984170489978268612
Short name T725
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.51 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 01:56:58 PM PST 23
Peak memory 203308 kb
Host smart-1df8be88-01b0-418e-bf4f-2946a4449089
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73295720901669806007347464369150151495807176144552527512698984170489978268612 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 3.xbar_error_random.73295720901669806007347464369150151495807176144552527512698984170489978268612
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.61562741281887337216018971488303726849864944893222237047930062666579981276784
Short name T669
Test name
Test status
Simulation time 4402420935 ps
CPU time 41.14 seconds
Started Nov 22 01:56:15 PM PST 23
Finished Nov 22 01:56:57 PM PST 23
Peak memory 211468 kb
Host smart-5ac155e8-cd4a-4376-9281-75697d69f52f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=61562741281887337216018971488303726849864944893222237047930062666579981276784 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 3.xbar_random.61562741281887337216018971488303726849864944893222237047930062666579981276784
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.91764406055100009331115291310314386649437998687795135910130441015311779338572
Short name T662
Test name
Test status
Simulation time 188793233435 ps
CPU time 325.09 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 02:01:43 PM PST 23
Peak memory 204832 kb
Host smart-7b5ec655-1431-4a4f-b88b-75cbcfce836a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=91764406055100009331115291310314386649437998687795135910130441015311779338572 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 3.xbar_random_large_delays.91764406055100009331115291310314386649437998687795135910130441015311779338572
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.65318334816344853611909509782781171825172288200214890075994997304152105297964
Short name T347
Test name
Test status
Simulation time 126189108435 ps
CPU time 324.65 seconds
Started Nov 22 01:56:16 PM PST 23
Finished Nov 22 02:01:42 PM PST 23
Peak memory 211372 kb
Host smart-6592f994-c8e3-418b-8669-1429e1daa008
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=65318334816344853611909509782781171825172288200214890075994997304152105297964 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.65318334816344853611909509782781171825172288200214890075994997304152105297964
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.18541195521543060637594685490826321767661972567216633879526577138836960349226
Short name T740
Test name
Test status
Simulation time 766920935 ps
CPU time 26.12 seconds
Started Nov 22 01:56:18 PM PST 23
Finished Nov 22 01:56:46 PM PST 23
Peak memory 211248 kb
Host smart-5974f440-8397-4330-9a57-9a36086f6112
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18541195521543060637594685490826321767661972567216633879526577138836960349226 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.18541195521543060637594685490826321767661972567216633879526577138836960349226
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.86415857714811805127668264614765516749777683202692736140114783791529959244097
Short name T545
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.08 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 01:57:00 PM PST 23
Peak memory 204240 kb
Host smart-4a26030a-a569-439d-8e37-71e83f72cce0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86415857714811805127668264614765516749777683202692736140114783791529959244097 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 3.xbar_same_source.86415857714811805127668264614765516749777683202692736140114783791529959244097
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.40487815268777645371567420908218625060276634612991222229197036977657205263076
Short name T399
Test name
Test status
Simulation time 669983435 ps
CPU time 4.37 seconds
Started Nov 22 01:56:15 PM PST 23
Finished Nov 22 01:56:21 PM PST 23
Peak memory 203100 kb
Host smart-6582c40d-40cf-466e-b69e-8792a4bc9929
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40487815268777645371567420908218625060276634612991222229197036977657205263076 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 3.xbar_smoke.40487815268777645371567420908218625060276634612991222229197036977657205263076
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.108907770689444931357529162062912420889101853473839973264706324301100232662679
Short name T226
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.65 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:57:10 PM PST 23
Peak memory 203248 kb
Host smart-a86c9225-375a-4543-b426-5388801c49cb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=108907770689444931357529162062912420889101853473839973264706324301100232662679 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.108907770689444931357529162062912420889101853473839973264706324301100232662679
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.84698913389631319213636512691659427087851799159450510600725643140951232904247
Short name T202
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.47 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 01:57:05 PM PST 23
Peak memory 203232 kb
Host smart-0fdb201f-2349-4b54-b5bd-8a4cc4b1b6b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=84698913389631319213636512691659427087851799159450510600725643140951232904247 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.84698913389631319213636512691659427087851799159450510600725643140951232904247
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.74214099856101257926071167320393911761082250479968671900104203159955042511552
Short name T580
Test name
Test status
Simulation time 116233435 ps
CPU time 2.34 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 01:56:20 PM PST 23
Peak memory 203024 kb
Host smart-5246eb70-ced5-479a-9097-3e56a3d29cda
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74214099856101257926071167320393911761082250479968671900104203159955042511552 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.74214099856101257926071167320393911761082250479968671900104203159955042511552
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.28454676298205260645456928933601935652824631142915794401628656246140907042405
Short name T744
Test name
Test status
Simulation time 18904859184 ps
CPU time 138.98 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 01:58:40 PM PST 23
Peak memory 205812 kb
Host smart-0083e98d-3812-4a89-8f27-37cc90f2fa46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28454676298205260645456928933601935652824631142915794401628656246140907042405 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 3.xbar_stress_all.28454676298205260645456928933601935652824631142915794401628656246140907042405
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.91327527487787753871390819190654804064315940242829796006151247968359124320331
Short name T535
Test name
Test status
Simulation time 18894549184 ps
CPU time 123.47 seconds
Started Nov 22 01:56:16 PM PST 23
Finished Nov 22 01:58:20 PM PST 23
Peak memory 211352 kb
Host smart-8b11face-d258-428f-858e-b84c06ca5ecd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91327527487787753871390819190654804064315940242829796006151247968359124320331 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 3.xbar_stress_all_with_error.91327527487787753871390819190654804064315940242829796006151247968359124320331
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.113245666778594151999029786036226912757414211785508419514271528116193189666598
Short name T520
Test name
Test status
Simulation time 5188549184 ps
CPU time 299.85 seconds
Started Nov 22 01:56:14 PM PST 23
Finished Nov 22 02:01:15 PM PST 23
Peak memory 208500 kb
Host smart-30cc2982-99d6-4190-ab02-83c532de930f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=113245666778594151999029786036226912757414211785508419514271528116193189666598 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.113245666778594151999029786036226912757414211785508419514271528116193189666598
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.4538416094012273241368539252717409979122842038958670855183738120237668124694
Short name T811
Test name
Test status
Simulation time 5188549184 ps
CPU time 225.02 seconds
Started Nov 22 01:56:18 PM PST 23
Finished Nov 22 02:00:04 PM PST 23
Peak memory 219584 kb
Host smart-40df3df2-67a7-43f5-b25c-3a8f531b73e7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4538416094012273241368539252717409979122842038958670855183738120237668124694 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.4538416094012273241368539252717409979122842038958670855183738120237668124694
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.80932313429188396082064459180015411990938177787862349725510058834004659814511
Short name T683
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.71 seconds
Started Nov 22 01:56:14 PM PST 23
Finished Nov 22 01:56:45 PM PST 23
Peak memory 211288 kb
Host smart-f4cc2f52-c7ac-4a65-b410-293fd4c69e9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=80932313429188396082064459180015411990938177787862349725510058834004659814511 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 3.xbar_unmapped_addr.80932313429188396082064459180015411990938177787862349725510058834004659814511
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.115414561580485732242099269834130590267871108043145236789229527709674367269234
Short name T849
Test name
Test status
Simulation time 7399045935 ps
CPU time 65.32 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 01:59:14 PM PST 23
Peak memory 206344 kb
Host smart-905a63a8-32ab-4105-88b0-94a458c5b4f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115414561580485732242099269834130590267871108043145236789229527709674367269234 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.115414561580485732242099269834130590267871108043145236789229527709674367269234
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.99093890726197047362321961637629531798313172278721608836560488193338279743722
Short name T618
Test name
Test status
Simulation time 304288045935 ps
CPU time 774.71 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 02:11:06 PM PST 23
Peak memory 211380 kb
Host smart-01f24758-cfeb-4e00-b7b7-a01d7b677b07
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=99093890726197047362321961637629531798313172278721608836560488193338279743722 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.99093890726197047362321961637629531798313172278721608836560488193338279743722
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.26805966649718493545815321019082711115640628503168279857777521061765521779041
Short name T229
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.34 seconds
Started Nov 22 01:58:26 PM PST 23
Finished Nov 22 01:58:54 PM PST 23
Peak memory 203272 kb
Host smart-841d952f-7933-4eb7-b9ea-6e48bbf59d4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=26805966649718493545815321019082711115640628503168279857777521061765521779041 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.26805966649718493545815321019082711115640628503168279857777521061765521779041
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.34650470976624801686006784236634445883124635441114924490404010737555663268942
Short name T642
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.65 seconds
Started Nov 22 01:58:11 PM PST 23
Finished Nov 22 01:58:51 PM PST 23
Peak memory 203196 kb
Host smart-9f97b7e2-ae19-4eaf-9633-364438433c20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34650470976624801686006784236634445883124635441114924490404010737555663268942 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 30.xbar_error_random.34650470976624801686006784236634445883124635441114924490404010737555663268942
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.103748424276693580618720710587857498890848486910368349400063405534693869532206
Short name T401
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.78 seconds
Started Nov 22 01:58:18 PM PST 23
Finished Nov 22 01:58:55 PM PST 23
Peak memory 211500 kb
Host smart-c5ea3e09-dea3-461e-9ad7-65152c89b981
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103748424276693580618720710587857498890848486910368349400063405534693869532206 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 30.xbar_random.103748424276693580618720710587857498890848486910368349400063405534693869532206
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.76612312770198991269731025578323158374236363596579878298649016117751539646271
Short name T225
Test name
Test status
Simulation time 188793233435 ps
CPU time 326.6 seconds
Started Nov 22 01:58:06 PM PST 23
Finished Nov 22 02:03:34 PM PST 23
Peak memory 204796 kb
Host smart-47440b52-e706-44f3-ae25-55bc8f31ae48
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=76612312770198991269731025578323158374236363596579878298649016117751539646271 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 30.xbar_random_large_delays.76612312770198991269731025578323158374236363596579878298649016117751539646271
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.111498656663838254895668863792795042731655335408887386287471849990532069991211
Short name T425
Test name
Test status
Simulation time 126189108435 ps
CPU time 318.55 seconds
Started Nov 22 01:58:07 PM PST 23
Finished Nov 22 02:03:26 PM PST 23
Peak memory 211400 kb
Host smart-557a80a0-149d-4f17-a760-fbab313407c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=111498656663838254895668863792795042731655335408887386287471849990532069991211 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.111498656663838254895668863792795042731655335408887386287471849990532069991211
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.111785572424676535246332986896605578859757459837768053290187623137211937057527
Short name T302
Test name
Test status
Simulation time 766920935 ps
CPU time 25.2 seconds
Started Nov 22 01:58:06 PM PST 23
Finished Nov 22 01:58:32 PM PST 23
Peak memory 203816 kb
Host smart-c5fde7a7-228b-4429-8c2b-c665063ba8b1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111785572424676535246332986896605578859757459837768053290187623137211937057527 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.111785572424676535246332986896605578859757459837768053290187623137211937057527
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.92651383752234485917898502621872284357354212950121847255109328273181798472627
Short name T370
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.18 seconds
Started Nov 22 01:58:09 PM PST 23
Finished Nov 22 01:58:47 PM PST 23
Peak memory 204256 kb
Host smart-ccc4416c-2c7d-4539-b0cf-d464a03bf6ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92651383752234485917898502621872284357354212950121847255109328273181798472627 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 30.xbar_same_source.92651383752234485917898502621872284357354212950121847255109328273181798472627
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.98586911568770912962901142242760961283983554765382979794507506875270928839994
Short name T96
Test name
Test status
Simulation time 669983435 ps
CPU time 4.22 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 01:58:13 PM PST 23
Peak memory 203048 kb
Host smart-257e5248-936e-43c2-830f-a429ec25e7e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98586911568770912962901142242760961283983554765382979794507506875270928839994 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 30.xbar_smoke.98586911568770912962901142242760961283983554765382979794507506875270928839994
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.8692617325119320749509300468674965970896953300051833311612308594392394382679
Short name T157
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.32 seconds
Started Nov 22 01:58:12 PM PST 23
Finished Nov 22 01:59:01 PM PST 23
Peak memory 203264 kb
Host smart-70482737-3298-4c66-85a1-233664429ef5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=8692617325119320749509300468674965970896953300051833311612308594392394382679 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.8692617325119320749509300468674965970896953300051833311612308594392394382679
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.58466291259051657254538101844361180800552817536297498136460027757273840995955
Short name T546
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.65 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 01:58:55 PM PST 23
Peak memory 203300 kb
Host smart-80f88f54-45e9-47e1-a19c-eb6393c8e1d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=58466291259051657254538101844361180800552817536297498136460027757273840995955 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.58466291259051657254538101844361180800552817536297498136460027757273840995955
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.68517710125632556583946078330078601520581823529991213011748678808369706748923
Short name T574
Test name
Test status
Simulation time 116233435 ps
CPU time 2.61 seconds
Started Nov 22 01:58:09 PM PST 23
Finished Nov 22 01:58:12 PM PST 23
Peak memory 203112 kb
Host smart-629a14af-cfd4-41c9-8757-a39a1c6cce66
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68517710125632556583946078330078601520581823529991213011748678808369706748923 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.68517710125632556583946078330078601520581823529991213011748678808369706748923
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.112336826522597640416294517455257723146799134263584628890756826758167981858794
Short name T378
Test name
Test status
Simulation time 18904859184 ps
CPU time 130.67 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 02:00:21 PM PST 23
Peak memory 205912 kb
Host smart-c81bad6d-0ba3-4d96-a32a-a89206ad8635
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112336826522597640416294517455257723146799134263584628890756826758167981858794 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 30.xbar_stress_all.112336826522597640416294517455257723146799134263584628890756826758167981858794
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.18289922535297958830570827356509036736233959346726867182538329365685806715911
Short name T183
Test name
Test status
Simulation time 18894549184 ps
CPU time 118.46 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 02:00:09 PM PST 23
Peak memory 211336 kb
Host smart-2f50a0ad-9859-4f27-928f-a87376c00dc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18289922535297958830570827356509036736233959346726867182538329365685806715911 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 30.xbar_stress_all_with_error.18289922535297958830570827356509036736233959346726867182538329365685806715911
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.111531333640216053110660368005584041770064699677834728107539165659007399974426
Short name T147
Test name
Test status
Simulation time 5188549184 ps
CPU time 291.43 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 02:03:02 PM PST 23
Peak memory 208532 kb
Host smart-fa5686f2-86fc-4159-865f-ad9e2723338b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111531333640216053110660368005584041770064699677834728107539165659007399974426 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.111531333640216053110660368005584041770064699677834728107539165659007399974426
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.56038759591834728429880100959670495292764810304385271199455943760526434386040
Short name T794
Test name
Test status
Simulation time 5188549184 ps
CPU time 223.45 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 02:01:53 PM PST 23
Peak memory 219624 kb
Host smart-2dda9ac1-32bd-4ca5-a2e5-c400d8e8427b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56038759591834728429880100959670495292764810304385271199455943760526434386040 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.56038759591834728429880100959670495292764810304385271199455943760526434386040
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.114924475997624729726525938612634274776233575222227039313897004350709602671823
Short name T88
Test name
Test status
Simulation time 3307045935 ps
CPU time 31.83 seconds
Started Nov 22 01:58:11 PM PST 23
Finished Nov 22 01:58:44 PM PST 23
Peak memory 211376 kb
Host smart-0285ff56-9f04-446b-8208-6ab8fe90fee1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=114924475997624729726525938612634274776233575222227039313897004350709602671823 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 30.xbar_unmapped_addr.114924475997624729726525938612634274776233575222227039313897004350709602671823
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.41249486856873870797853984835573085200254471696578264733155341627376119326783
Short name T321
Test name
Test status
Simulation time 7399045935 ps
CPU time 67.16 seconds
Started Nov 22 01:58:06 PM PST 23
Finished Nov 22 01:59:14 PM PST 23
Peak memory 206324 kb
Host smart-d83fd2d7-a7ab-4ddc-8fef-d17781ddf2e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41249486856873870797853984835573085200254471696578264733155341627376119326783 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.41249486856873870797853984835573085200254471696578264733155341627376119326783
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.42482527863359946581614412737874026988088477225867983997571225073697039913283
Short name T194
Test name
Test status
Simulation time 304288045935 ps
CPU time 765.92 seconds
Started Nov 22 01:58:25 PM PST 23
Finished Nov 22 02:11:13 PM PST 23
Peak memory 211396 kb
Host smart-720c8866-1652-4521-bc55-99999622f8a0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=42482527863359946581614412737874026988088477225867983997571225073697039913283 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.42482527863359946581614412737874026988088477225867983997571225073697039913283
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.99452061043641589298839469172365633619532988088554936807019520931084438110446
Short name T839
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.73 seconds
Started Nov 22 01:58:26 PM PST 23
Finished Nov 22 01:58:56 PM PST 23
Peak memory 203316 kb
Host smart-c1bb9b32-219f-47f9-9456-a217ae762db9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99452061043641589298839469172365633619532988088554936807019520931084438110446 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.99452061043641589298839469172365633619532988088554936807019520931084438110446
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.99110448493937780922857196061155610379751718047269105257815450501025550800207
Short name T118
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.42 seconds
Started Nov 22 01:58:24 PM PST 23
Finished Nov 22 01:59:03 PM PST 23
Peak memory 203364 kb
Host smart-dd50e2cf-9206-42de-ab2b-d016a1182751
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99110448493937780922857196061155610379751718047269105257815450501025550800207 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 31.xbar_error_random.99110448493937780922857196061155610379751718047269105257815450501025550800207
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.110612388839187222358118559005086513195659617788323706525958734081667931696596
Short name T684
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.17 seconds
Started Nov 22 01:58:07 PM PST 23
Finished Nov 22 01:58:44 PM PST 23
Peak memory 211272 kb
Host smart-658964b3-cf36-435d-a513-14125445ff6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110612388839187222358118559005086513195659617788323706525958734081667931696596 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 31.xbar_random.110612388839187222358118559005086513195659617788323706525958734081667931696596
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.95013647731196114451960878045665270902714102083428793510549460869476457699997
Short name T189
Test name
Test status
Simulation time 188793233435 ps
CPU time 317.92 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 02:03:27 PM PST 23
Peak memory 204860 kb
Host smart-99151a51-ad9a-44c0-8d5e-0e8a7892141d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=95013647731196114451960878045665270902714102083428793510549460869476457699997 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 31.xbar_random_large_delays.95013647731196114451960878045665270902714102083428793510549460869476457699997
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.44753482880960241644713175463075467163593694005130947152027195349467613409852
Short name T328
Test name
Test status
Simulation time 126189108435 ps
CPU time 327.83 seconds
Started Nov 22 01:58:09 PM PST 23
Finished Nov 22 02:03:37 PM PST 23
Peak memory 211476 kb
Host smart-dce4ca86-f37c-4ad1-8170-f39b3d06167b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=44753482880960241644713175463075467163593694005130947152027195349467613409852 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.44753482880960241644713175463075467163593694005130947152027195349467613409852
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.53354398318126772133289625267570477589893838735047969987476577677730706894802
Short name T587
Test name
Test status
Simulation time 766920935 ps
CPU time 30.66 seconds
Started Nov 22 01:58:10 PM PST 23
Finished Nov 22 01:58:42 PM PST 23
Peak memory 203808 kb
Host smart-ef0ac9db-8c15-40d2-88fc-9b29a10d1c4d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53354398318126772133289625267570477589893838735047969987476577677730706894802 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.53354398318126772133289625267570477589893838735047969987476577677730706894802
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.30887529555189242479481153750641420274868399989230817399025203396435976791099
Short name T734
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.66 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 01:58:47 PM PST 23
Peak memory 204296 kb
Host smart-99df94e4-9e98-4c06-8ac6-78493580f003
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30887529555189242479481153750641420274868399989230817399025203396435976791099 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 31.xbar_same_source.30887529555189242479481153750641420274868399989230817399025203396435976791099
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.367959989031534807175928297172534682236951350058509799481872398257519878570
Short name T10
Test name
Test status
Simulation time 669983435 ps
CPU time 4.31 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 01:58:13 PM PST 23
Peak memory 202936 kb
Host smart-fcdddd39-b408-47a7-92fe-ef3a57f69bbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=367959989031534807175928297172534682236951350058509799481872398257519878570 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /d
ev/null -cm_name 31.xbar_smoke.367959989031534807175928297172534682236951350058509799481872398257519878570
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.74692422036416517934584864010174666653393269437714078863994120885733021815326
Short name T783
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.69 seconds
Started Nov 22 01:58:09 PM PST 23
Finished Nov 22 01:58:59 PM PST 23
Peak memory 203220 kb
Host smart-ed69decc-6f5c-45aa-a2ee-f45195a1b56b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=74692422036416517934584864010174666653393269437714078863994120885733021815326 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.74692422036416517934584864010174666653393269437714078863994120885733021815326
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.72931871570324168975198657086625165212370929130271243691477665939577344307253
Short name T802
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.39 seconds
Started Nov 22 01:58:13 PM PST 23
Finished Nov 22 01:58:58 PM PST 23
Peak memory 203060 kb
Host smart-3ef3f031-834e-4780-8e13-fd778df09ee6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=72931871570324168975198657086625165212370929130271243691477665939577344307253 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.72931871570324168975198657086625165212370929130271243691477665939577344307253
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.86756872274949387484837787074363800238453375508599930716743865716083542594596
Short name T892
Test name
Test status
Simulation time 116233435 ps
CPU time 2.42 seconds
Started Nov 22 01:58:09 PM PST 23
Finished Nov 22 01:58:12 PM PST 23
Peak memory 203200 kb
Host smart-23722ed6-cade-44de-9895-ba133c76abbb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86756872274949387484837787074363800238453375508599930716743865716083542594596 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.86756872274949387484837787074363800238453375508599930716743865716083542594596
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.30287857183131687151604136885377905948692545045113155691732652994813436294271
Short name T323
Test name
Test status
Simulation time 18904859184 ps
CPU time 126.33 seconds
Started Nov 22 01:58:30 PM PST 23
Finished Nov 22 02:00:39 PM PST 23
Peak memory 205852 kb
Host smart-9c142b7f-f8c1-46aa-8777-39d5ea94d8b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30287857183131687151604136885377905948692545045113155691732652994813436294271 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 31.xbar_stress_all.30287857183131687151604136885377905948692545045113155691732652994813436294271
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.112981389437111552165250630019018447348735093758524488238148883751566843461478
Short name T418
Test name
Test status
Simulation time 18894549184 ps
CPU time 124.42 seconds
Started Nov 22 01:58:32 PM PST 23
Finished Nov 22 02:00:38 PM PST 23
Peak memory 211396 kb
Host smart-c5a5fd24-a2d8-4346-b00f-7cd29d8effc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112981389437111552165250630019018447348735093758524488238148883751566843461478 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.112981389437111552165250630019018447348735093758524488238148883751566843461478
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.66909466692338966531795029582562305886378547158929832223324767372526894097656
Short name T844
Test name
Test status
Simulation time 5188549184 ps
CPU time 290.54 seconds
Started Nov 22 01:58:27 PM PST 23
Finished Nov 22 02:03:19 PM PST 23
Peak memory 208532 kb
Host smart-5f8671ea-396c-4b8d-9d3f-d931b15ef520
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66909466692338966531795029582562305886378547158929832223324767372526894097656 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.66909466692338966531795029582562305886378547158929832223324767372526894097656
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.99937679380714209711327050183254989433981243537573289443201048534976630550023
Short name T98
Test name
Test status
Simulation time 5188549184 ps
CPU time 221.18 seconds
Started Nov 22 01:58:27 PM PST 23
Finished Nov 22 02:02:11 PM PST 23
Peak memory 219532 kb
Host smart-877562f2-c036-4417-8513-b235986a5539
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99937679380714209711327050183254989433981243537573289443201048534976630550023 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.99937679380714209711327050183254989433981243537573289443201048534976630550023
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.48339998619919902601180543227927090640326497318949982938097485960048072879425
Short name T87
Test name
Test status
Simulation time 3307045935 ps
CPU time 31.38 seconds
Started Nov 22 01:58:12 PM PST 23
Finished Nov 22 01:58:44 PM PST 23
Peak memory 211336 kb
Host smart-9ed8f554-9686-4df7-85b7-f6561844c6a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48339998619919902601180543227927090640326497318949982938097485960048072879425 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 31.xbar_unmapped_addr.48339998619919902601180543227927090640326497318949982938097485960048072879425
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.41081125846342064498184587649346963982810047642842154210430816089373438158835
Short name T822
Test name
Test status
Simulation time 7399045935 ps
CPU time 60.94 seconds
Started Nov 22 01:58:27 PM PST 23
Finished Nov 22 01:59:30 PM PST 23
Peak memory 206344 kb
Host smart-30ad2f31-2aab-4146-9d76-eadf82a3ed2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41081125846342064498184587649346963982810047642842154210430816089373438158835 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.41081125846342064498184587649346963982810047642842154210430816089373438158835
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.89987914632415686947749832807546261728152874782830439724400009844435891388288
Short name T61
Test name
Test status
Simulation time 304288045935 ps
CPU time 764.22 seconds
Started Nov 22 01:58:17 PM PST 23
Finished Nov 22 02:11:02 PM PST 23
Peak memory 211460 kb
Host smart-1c918c1b-31ea-4bb9-87df-d1d8d2907aba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=89987914632415686947749832807546261728152874782830439724400009844435891388288 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.89987914632415686947749832807546261728152874782830439724400009844435891388288
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.68264012537637834084567630632414365506782021968147096602481274344781519712217
Short name T407
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.36 seconds
Started Nov 22 01:58:14 PM PST 23
Finished Nov 22 01:58:41 PM PST 23
Peak memory 203364 kb
Host smart-dfb01c0c-f176-458b-991b-466b1d67abef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68264012537637834084567630632414365506782021968147096602481274344781519712217 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.68264012537637834084567630632414365506782021968147096602481274344781519712217
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.25701430619714436498621029863796256179927024227137756832342923921219204267320
Short name T24
Test name
Test status
Simulation time 4402420935 ps
CPU time 34.47 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 01:59:05 PM PST 23
Peak memory 203224 kb
Host smart-32326e0c-ceca-4933-99ca-658bf6dfb305
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25701430619714436498621029863796256179927024227137756832342923921219204267320 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 32.xbar_error_random.25701430619714436498621029863796256179927024227137756832342923921219204267320
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.104364162855488819749283019403725412963917203766415061584374303429594853566425
Short name T566
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.06 seconds
Started Nov 22 01:58:08 PM PST 23
Finished Nov 22 01:58:47 PM PST 23
Peak memory 211412 kb
Host smart-8dac48f0-0596-4c72-9c16-a1963c667e01
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104364162855488819749283019403725412963917203766415061584374303429594853566425 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 32.xbar_random.104364162855488819749283019403725412963917203766415061584374303429594853566425
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.79413709484884579215871264005518466369879388202727121496841925845553124820207
Short name T409
Test name
Test status
Simulation time 188793233435 ps
CPU time 322.54 seconds
Started Nov 22 01:58:27 PM PST 23
Finished Nov 22 02:03:51 PM PST 23
Peak memory 204828 kb
Host smart-ba717d1f-9f34-4f6d-a26b-e4b6c1303589
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=79413709484884579215871264005518466369879388202727121496841925845553124820207 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 32.xbar_random_large_delays.79413709484884579215871264005518466369879388202727121496841925845553124820207
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.109333485105261231243948282716750051423351661568172064637741973295428534258182
Short name T475
Test name
Test status
Simulation time 126189108435 ps
CPU time 329.69 seconds
Started Nov 22 01:58:33 PM PST 23
Finished Nov 22 02:04:05 PM PST 23
Peak memory 211436 kb
Host smart-80f1cceb-4f59-4f69-932c-05737d531dc5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=109333485105261231243948282716750051423351661568172064637741973295428534258182 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.109333485105261231243948282716750051423351661568172064637741973295428534258182
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.86127168758958937542238015223005135854337321135911385188731391616537819507016
Short name T751
Test name
Test status
Simulation time 766920935 ps
CPU time 24.18 seconds
Started Nov 22 01:58:07 PM PST 23
Finished Nov 22 01:58:32 PM PST 23
Peak memory 203848 kb
Host smart-4a89154d-cc0b-4f32-a8e1-5b1af0373ca5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86127168758958937542238015223005135854337321135911385188731391616537819507016 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.86127168758958937542238015223005135854337321135911385188731391616537819507016
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.47639924059952944472967608026322888107607862246394478072799885313331367863534
Short name T318
Test name
Test status
Simulation time 7116170935 ps
CPU time 36.81 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 01:59:18 PM PST 23
Peak memory 204320 kb
Host smart-d388b688-c279-4136-a6a5-a9273d60f8dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47639924059952944472967608026322888107607862246394478072799885313331367863534 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 32.xbar_same_source.47639924059952944472967608026322888107607862246394478072799885313331367863534
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.5153972371106553963395589178055612969208983843250126863232839034792670975833
Short name T277
Test name
Test status
Simulation time 669983435 ps
CPU time 4.05 seconds
Started Nov 22 01:58:33 PM PST 23
Finished Nov 22 01:58:39 PM PST 23
Peak memory 203120 kb
Host smart-bc474f10-86ec-485d-89ec-957145cdcded
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5153972371106553963395589178055612969208983843250126863232839034792670975833 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 32.xbar_smoke.5153972371106553963395589178055612969208983843250126863232839034792670975833
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.26037389627038483107805730745231782570614269129115053164876521182064972555354
Short name T750
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.68 seconds
Started Nov 22 01:58:36 PM PST 23
Finished Nov 22 01:59:24 PM PST 23
Peak memory 203272 kb
Host smart-5adffa35-8674-4f75-8cf7-93b2229296a3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=26037389627038483107805730745231782570614269129115053164876521182064972555354 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.26037389627038483107805730745231782570614269129115053164876521182064972555354
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.55916545239387568618780799547335806109415716656023794838413523402725368783160
Short name T728
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.51 seconds
Started Nov 22 01:58:07 PM PST 23
Finished Nov 22 01:58:52 PM PST 23
Peak memory 203324 kb
Host smart-c1b1bd26-3a16-4759-99ae-177353fce5fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=55916545239387568618780799547335806109415716656023794838413523402725368783160 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.55916545239387568618780799547335806109415716656023794838413523402725368783160
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.73893540833766775879896316279805988913346025579020975235774925396943930936635
Short name T265
Test name
Test status
Simulation time 116233435 ps
CPU time 2.58 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 01:58:33 PM PST 23
Peak memory 203108 kb
Host smart-82139a7b-af63-4488-9e8b-cd65886c426a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73893540833766775879896316279805988913346025579020975235774925396943930936635 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.73893540833766775879896316279805988913346025579020975235774925396943930936635
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.58038859296101959048075680114061869660066263023934389493746950192481612822084
Short name T643
Test name
Test status
Simulation time 18904859184 ps
CPU time 131.76 seconds
Started Nov 22 01:58:26 PM PST 23
Finished Nov 22 02:00:40 PM PST 23
Peak memory 205812 kb
Host smart-69ff1674-d61f-4173-802c-ec4ab97a43bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=58038859296101959048075680114061869660066263023934389493746950192481612822084 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 32.xbar_stress_all.58038859296101959048075680114061869660066263023934389493746950192481612822084
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.8867345547879681934799825571714118527340800200016368567069689033054418247865
Short name T413
Test name
Test status
Simulation time 18894549184 ps
CPU time 121.37 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 02:00:31 PM PST 23
Peak memory 211412 kb
Host smart-12c4717a-69e6-4b4e-bc74-09300b3aaf5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8867345547879681934799825571714118527340800200016368567069689033054418247865 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 32.xbar_stress_all_with_error.8867345547879681934799825571714118527340800200016368567069689033054418247865
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.89187566446932814341969770657598586686041995271713003819274192523687133201571
Short name T163
Test name
Test status
Simulation time 5188549184 ps
CPU time 295.85 seconds
Started Nov 22 01:58:24 PM PST 23
Finished Nov 22 02:03:22 PM PST 23
Peak memory 208436 kb
Host smart-c622a408-dfd0-4d15-afd5-57d075f635d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89187566446932814341969770657598586686041995271713003819274192523687133201571 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.89187566446932814341969770657598586686041995271713003819274192523687133201571
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.62185757744292191498319864242832981706064658069645382985344588646982897025758
Short name T358
Test name
Test status
Simulation time 5188549184 ps
CPU time 228.36 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 02:02:19 PM PST 23
Peak memory 219624 kb
Host smart-e1df6d45-bc01-4e50-bbfb-bf4ef089c9b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62185757744292191498319864242832981706064658069645382985344588646982897025758 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.62185757744292191498319864242832981706064658069645382985344588646982897025758
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.35613952328072686074333952029899658036566250133698066651646954619830340870478
Short name T775
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.96 seconds
Started Nov 22 01:58:25 PM PST 23
Finished Nov 22 01:58:56 PM PST 23
Peak memory 211336 kb
Host smart-a6bd16de-3699-4e96-95fd-30b29ea7d5f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35613952328072686074333952029899658036566250133698066651646954619830340870478 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 32.xbar_unmapped_addr.35613952328072686074333952029899658036566250133698066651646954619830340870478
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.112790539886404908571259726929611763353057371008091935298891144683529792963087
Short name T702
Test name
Test status
Simulation time 7399045935 ps
CPU time 60.48 seconds
Started Nov 22 01:58:27 PM PST 23
Finished Nov 22 01:59:29 PM PST 23
Peak memory 206340 kb
Host smart-01fd43d9-7106-4788-85a7-6e48e55bef39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112790539886404908571259726929611763353057371008091935298891144683529792963087 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.112790539886404908571259726929611763353057371008091935298891144683529792963087
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.84732687521596128888659525206308796786988991849778419759991026064470253208195
Short name T457
Test name
Test status
Simulation time 304288045935 ps
CPU time 767.38 seconds
Started Nov 22 01:58:26 PM PST 23
Finished Nov 22 02:11:15 PM PST 23
Peak memory 211508 kb
Host smart-c9e4e8a8-5880-4e22-8844-45db02cf1e53
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=84732687521596128888659525206308796786988991849778419759991026064470253208195 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.84732687521596128888659525206308796786988991849778419759991026064470253208195
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.5815718908102789451554279924179596660851042800720564877537194361485410430969
Short name T649
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.7 seconds
Started Nov 22 01:58:27 PM PST 23
Finished Nov 22 01:58:55 PM PST 23
Peak memory 203324 kb
Host smart-c2259b7c-1b9a-4e29-8475-b583a21f311d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5815718908102789451554279924179596660851042800720564877537194361485410430969 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.5815718908102789451554279924179596660851042800720564877537194361485410430969
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.64225975367979103948429801331250876521868975109442530287022455603134097994962
Short name T246
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.77 seconds
Started Nov 22 01:58:26 PM PST 23
Finished Nov 22 01:59:02 PM PST 23
Peak memory 203220 kb
Host smart-8de65aa7-88c1-4abb-aa84-a991b9145c48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64225975367979103948429801331250876521868975109442530287022455603134097994962 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 33.xbar_error_random.64225975367979103948429801331250876521868975109442530287022455603134097994962
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.10169370697639589101651517381662907290930540834536381653901896473791094146804
Short name T335
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.11 seconds
Started Nov 22 01:58:13 PM PST 23
Finished Nov 22 01:58:52 PM PST 23
Peak memory 211464 kb
Host smart-4c118c1e-c379-47a4-bf1a-194c3d20903d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10169370697639589101651517381662907290930540834536381653901896473791094146804 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 33.xbar_random.10169370697639589101651517381662907290930540834536381653901896473791094146804
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.110818044004310705369197530075144047686119558272245529308513901132680589630317
Short name T419
Test name
Test status
Simulation time 188793233435 ps
CPU time 326.27 seconds
Started Nov 22 01:58:27 PM PST 23
Finished Nov 22 02:03:56 PM PST 23
Peak memory 204604 kb
Host smart-ac4fdc4c-6c87-4688-a348-16711482e2f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=110818044004310705369197530075144047686119558272245529308513901132680589630317 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.110818044004310705369197530075144047686119558272245529308513901132680589630317
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.92737714459492921477392309499937395952183959204844014936214452422193137475572
Short name T663
Test name
Test status
Simulation time 126189108435 ps
CPU time 320.28 seconds
Started Nov 22 01:58:33 PM PST 23
Finished Nov 22 02:03:56 PM PST 23
Peak memory 211416 kb
Host smart-0d611dc9-719b-4891-9a1c-59e708aebdb7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=92737714459492921477392309499937395952183959204844014936214452422193137475572 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.92737714459492921477392309499937395952183959204844014936214452422193137475572
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.102614211237687128701054897644364043178343584264539042741485829761443949617595
Short name T551
Test name
Test status
Simulation time 766920935 ps
CPU time 25.56 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 01:58:56 PM PST 23
Peak memory 203788 kb
Host smart-9a992bc8-8f66-4ba4-9697-593e07abd752
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102614211237687128701054897644364043178343584264539042741485829761443949617595 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_
mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.102614211237687128701054897644364043178343584264539042741485829761443949617595
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.34035683199793365714411355740861782393416065712310985124391541325865296132405
Short name T634
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.13 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 01:59:09 PM PST 23
Peak memory 204280 kb
Host smart-984a274b-196b-4ed1-bd14-e502a4b5bdb6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=34035683199793365714411355740861782393416065712310985124391541325865296132405 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 33.xbar_same_source.34035683199793365714411355740861782393416065712310985124391541325865296132405
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.88725447798263904816182852799351460450713973155467516087081340740182395273148
Short name T636
Test name
Test status
Simulation time 669983435 ps
CPU time 3.96 seconds
Started Nov 22 01:58:26 PM PST 23
Finished Nov 22 01:58:32 PM PST 23
Peak memory 203144 kb
Host smart-1b102f6f-8d9c-444f-851b-8b7a1f0b09a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88725447798263904816182852799351460450713973155467516087081340740182395273148 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 33.xbar_smoke.88725447798263904816182852799351460450713973155467516087081340740182395273148
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.98082899794570894220250614212951529110083054901480075632508554361235615605640
Short name T111
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.95 seconds
Started Nov 22 01:58:12 PM PST 23
Finished Nov 22 01:59:01 PM PST 23
Peak memory 203048 kb
Host smart-6dc4e566-4698-4e28-a6a4-710ea4693e13
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=98082899794570894220250614212951529110083054901480075632508554361235615605640 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.98082899794570894220250614212951529110083054901480075632508554361235615605640
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.60100519588646387292096622642470436956888820041987329234634346493350733400141
Short name T171
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.24 seconds
Started Nov 22 01:58:40 PM PST 23
Finished Nov 22 01:59:25 PM PST 23
Peak memory 203276 kb
Host smart-7a5d75ab-c042-44e7-8fd2-5c19b1aabd27
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=60100519588646387292096622642470436956888820041987329234634346493350733400141 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.60100519588646387292096622642470436956888820041987329234634346493350733400141
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.34070782073849867879618821594168878644176799804994134120106237481288934143069
Short name T788
Test name
Test status
Simulation time 116233435 ps
CPU time 2.55 seconds
Started Nov 22 01:58:12 PM PST 23
Finished Nov 22 01:58:16 PM PST 23
Peak memory 203132 kb
Host smart-36a70724-3946-40c8-b7af-74793069947e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34070782073849867879618821594168878644176799804994134120106237481288934143069 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.34070782073849867879618821594168878644176799804994134120106237481288934143069
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.15146772478424667397512554622374301223026180569825607015533228038356869600886
Short name T174
Test name
Test status
Simulation time 18904859184 ps
CPU time 126.81 seconds
Started Nov 22 01:58:14 PM PST 23
Finished Nov 22 02:00:21 PM PST 23
Peak memory 205904 kb
Host smart-ae81d9e3-fbff-41ec-8856-b9a78454824e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15146772478424667397512554622374301223026180569825607015533228038356869600886 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 33.xbar_stress_all.15146772478424667397512554622374301223026180569825607015533228038356869600886
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.59039235693238368400551737937980673664922936301785901898428218532289857397974
Short name T889
Test name
Test status
Simulation time 18894549184 ps
CPU time 120.33 seconds
Started Nov 22 01:58:40 PM PST 23
Finished Nov 22 02:00:42 PM PST 23
Peak memory 211380 kb
Host smart-8895c8c8-0ff4-4724-92b2-63cf646c59f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59039235693238368400551737937980673664922936301785901898428218532289857397974 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 33.xbar_stress_all_with_error.59039235693238368400551737937980673664922936301785901898428218532289857397974
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.9195348518250746135474590619482653523387520490049328217653226555620013983753
Short name T655
Test name
Test status
Simulation time 5188549184 ps
CPU time 283.85 seconds
Started Nov 22 01:58:35 PM PST 23
Finished Nov 22 02:03:20 PM PST 23
Peak memory 208508 kb
Host smart-5aec7f34-e940-4278-b526-f78bd50e0143
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=9195348518250746135474590619482653523387520490049328217653226555620013983753 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.9195348518250746135474590619482653523387520490049328217653226555620013983753
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.9767075147740006988102465065871279243333920217341617208579443933068914529413
Short name T160
Test name
Test status
Simulation time 5188549184 ps
CPU time 217.75 seconds
Started Nov 22 01:58:33 PM PST 23
Finished Nov 22 02:02:12 PM PST 23
Peak memory 219704 kb
Host smart-623d28cf-4daf-4b9b-a565-3243586f0ffe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=9767075147740006988102465065871279243333920217341617208579443933068914529413 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.9767075147740006988102465065871279243333920217341617208579443933068914529413
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.70706588294959365497091497155106920066527340787409272928468912713344458440742
Short name T635
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.96 seconds
Started Nov 22 01:58:30 PM PST 23
Finished Nov 22 01:59:01 PM PST 23
Peak memory 211420 kb
Host smart-6baeb64e-01e3-441d-8ff1-9f9dcafb7139
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70706588294959365497091497155106920066527340787409272928468912713344458440742 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 33.xbar_unmapped_addr.70706588294959365497091497155106920066527340787409272928468912713344458440742
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.47875774684709429384503407158638262716325576928281174359314929100281485043240
Short name T77
Test name
Test status
Simulation time 7399045935 ps
CPU time 64.94 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 01:59:47 PM PST 23
Peak memory 206340 kb
Host smart-8033be2a-1633-4ca7-970f-9b59133a9111
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47875774684709429384503407158638262716325576928281174359314929100281485043240 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.47875774684709429384503407158638262716325576928281174359314929100281485043240
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.44437916874294346873244235406819086552571649433989131986734131434242272849317
Short name T432
Test name
Test status
Simulation time 304288045935 ps
CPU time 764.8 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 02:11:16 PM PST 23
Peak memory 211328 kb
Host smart-e65407c6-cb1b-4907-ad10-4a0c990a6c49
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=44437916874294346873244235406819086552571649433989131986734131434242272849317 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.44437916874294346873244235406819086552571649433989131986734131434242272849317
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.95982839155901586881611853672510232093185048719235637654239326158422256608253
Short name T310
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.85 seconds
Started Nov 22 01:58:45 PM PST 23
Finished Nov 22 01:59:20 PM PST 23
Peak memory 203288 kb
Host smart-bbf20e7b-865f-42a2-be56-457157207810
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95982839155901586881611853672510232093185048719235637654239326158422256608253 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.95982839155901586881611853672510232093185048719235637654239326158422256608253
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.70241464262966806515583511813236899928248827792544785343335249921276158959001
Short name T181
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.54 seconds
Started Nov 22 01:58:42 PM PST 23
Finished Nov 22 01:59:20 PM PST 23
Peak memory 203272 kb
Host smart-9843661d-54bf-40cb-9d82-af352a8f95b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70241464262966806515583511813236899928248827792544785343335249921276158959001 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 34.xbar_error_random.70241464262966806515583511813236899928248827792544785343335249921276158959001
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.93465926191934824053989446232781878252618337758492607207091226600415034094294
Short name T422
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.64 seconds
Started Nov 22 01:58:25 PM PST 23
Finished Nov 22 01:59:03 PM PST 23
Peak memory 211364 kb
Host smart-eee5d207-5ef2-4499-9682-da37db9f914b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93465926191934824053989446232781878252618337758492607207091226600415034094294 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 34.xbar_random.93465926191934824053989446232781878252618337758492607207091226600415034094294
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.110509056970515671329889894312221874623207308128976666243922124046703516188282
Short name T688
Test name
Test status
Simulation time 188793233435 ps
CPU time 323.12 seconds
Started Nov 22 01:58:25 PM PST 23
Finished Nov 22 02:03:50 PM PST 23
Peak memory 204772 kb
Host smart-602b9589-cebc-432b-af83-050fd9f2a4d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=110509056970515671329889894312221874623207308128976666243922124046703516188282 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.110509056970515671329889894312221874623207308128976666243922124046703516188282
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.25270090597077300127234832059796208640816143120549853321274892810194094643871
Short name T539
Test name
Test status
Simulation time 126189108435 ps
CPU time 322.49 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 02:04:06 PM PST 23
Peak memory 211396 kb
Host smart-5d1013da-39be-4d92-a6f0-4b8ce5ebec96
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=25270090597077300127234832059796208640816143120549853321274892810194094643871 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.25270090597077300127234832059796208640816143120549853321274892810194094643871
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.31313006844430384944056136527754115396991349798902524330526704391464364786842
Short name T18
Test name
Test status
Simulation time 766920935 ps
CPU time 25.84 seconds
Started Nov 22 01:58:17 PM PST 23
Finished Nov 22 01:58:44 PM PST 23
Peak memory 203844 kb
Host smart-0a44e585-9495-4a99-b7af-546d58aa6a40
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31313006844430384944056136527754115396991349798902524330526704391464364786842 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.31313006844430384944056136527754115396991349798902524330526704391464364786842
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.83073196733998252533317328661781842695312644149023068140927601210401769454536
Short name T329
Test name
Test status
Simulation time 7116170935 ps
CPU time 37 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 01:59:08 PM PST 23
Peak memory 204296 kb
Host smart-06db6ab9-ea94-4954-9d8b-55bbace7816f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83073196733998252533317328661781842695312644149023068140927601210401769454536 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 34.xbar_same_source.83073196733998252533317328661781842695312644149023068140927601210401769454536
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.60461290576484343104117149459319011658854649965216515842520261684479344254523
Short name T421
Test name
Test status
Simulation time 669983435 ps
CPU time 4.19 seconds
Started Nov 22 01:58:12 PM PST 23
Finished Nov 22 01:58:17 PM PST 23
Peak memory 203080 kb
Host smart-059b5715-74e9-4ce9-914a-e25551a13dfe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=60461290576484343104117149459319011658854649965216515842520261684479344254523 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 34.xbar_smoke.60461290576484343104117149459319011658854649965216515842520261684479344254523
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.23509496308513872719548474245523709681855110721507295741145187714847939345954
Short name T234
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.76 seconds
Started Nov 22 01:58:39 PM PST 23
Finished Nov 22 01:59:29 PM PST 23
Peak memory 203204 kb
Host smart-c20ab23c-1ddf-4a72-8e2c-2d724ad6c196
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=23509496308513872719548474245523709681855110721507295741145187714847939345954 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.23509496308513872719548474245523709681855110721507295741145187714847939345954
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.30995276346675516784644048421628247085559140772387758293042700173967007392979
Short name T772
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.74 seconds
Started Nov 22 01:58:25 PM PST 23
Finished Nov 22 01:59:13 PM PST 23
Peak memory 203276 kb
Host smart-ed4a1b52-e643-4a50-8115-5775922fe26e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=30995276346675516784644048421628247085559140772387758293042700173967007392979 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.30995276346675516784644048421628247085559140772387758293042700173967007392979
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.51988546277987503289900691189463167314725935326845647491556024241415892046456
Short name T48
Test name
Test status
Simulation time 116233435 ps
CPU time 2.61 seconds
Started Nov 22 01:58:25 PM PST 23
Finished Nov 22 01:58:29 PM PST 23
Peak memory 203088 kb
Host smart-20744cbe-c697-436a-9788-7dc8bf49f0cf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51988546277987503289900691189463167314725935326845647491556024241415892046456 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.51988546277987503289900691189463167314725935326845647491556024241415892046456
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.67363086848592650166384710350502871935969792307941255491150363462617444054565
Short name T55
Test name
Test status
Simulation time 18904859184 ps
CPU time 128.77 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 02:00:40 PM PST 23
Peak memory 205824 kb
Host smart-c1fea3b8-3bdc-4053-9378-0a0318a535d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=67363086848592650166384710350502871935969792307941255491150363462617444054565 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 34.xbar_stress_all.67363086848592650166384710350502871935969792307941255491150363462617444054565
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.104387905380662338245326751168226232364279744192050470741130348750331068253437
Short name T516
Test name
Test status
Simulation time 18894549184 ps
CPU time 120.94 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 02:00:44 PM PST 23
Peak memory 211436 kb
Host smart-00a8ae03-a967-44eb-8d62-11fa1d299eea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104387905380662338245326751168226232364279744192050470741130348750331068253437 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.104387905380662338245326751168226232364279744192050470741130348750331068253437
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.74376162177749582443224227484183718653633733410319283290662534620841540467574
Short name T572
Test name
Test status
Simulation time 5188549184 ps
CPU time 295.68 seconds
Started Nov 22 01:58:30 PM PST 23
Finished Nov 22 02:03:28 PM PST 23
Peak memory 208492 kb
Host smart-52e4eaf0-3f0b-4401-b6f2-10b88aaf3f25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74376162177749582443224227484183718653633733410319283290662534620841540467574 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.74376162177749582443224227484183718653633733410319283290662534620841540467574
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.104884255303122902972095154055384788781272214450578544360169251858650382902403
Short name T495
Test name
Test status
Simulation time 5188549184 ps
CPU time 227.97 seconds
Started Nov 22 01:58:30 PM PST 23
Finished Nov 22 02:02:20 PM PST 23
Peak memory 219612 kb
Host smart-0cd82052-5cd0-4f7a-822f-f983d965d380
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104884255303122902972095154055384788781272214450578544360169251858650382902403 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.104884255303122902972095154055384788781272214450578544360169251858650382902403
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.103759825216030334625683741298617601300368089998729316750022377146796427483363
Short name T488
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.92 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 01:59:00 PM PST 23
Peak memory 211372 kb
Host smart-096f5bb2-fa06-4ba1-89b3-3822305a5610
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103759825216030334625683741298617601300368089998729316750022377146796427483363 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 34.xbar_unmapped_addr.103759825216030334625683741298617601300368089998729316750022377146796427483363
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.115644343338442535129983246109113537457274592506154109503582455160199458792951
Short name T900
Test name
Test status
Simulation time 7399045935 ps
CPU time 62.62 seconds
Started Nov 22 01:58:31 PM PST 23
Finished Nov 22 01:59:35 PM PST 23
Peak memory 206340 kb
Host smart-6cce8caf-1b64-4e4c-8b93-70250ad94354
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115644343338442535129983246109113537457274592506154109503582455160199458792951 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.115644343338442535129983246109113537457274592506154109503582455160199458792951
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.21182166599707902948111748290540954294269353810493875668458957491370350122845
Short name T281
Test name
Test status
Simulation time 304288045935 ps
CPU time 777.29 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 02:11:41 PM PST 23
Peak memory 211388 kb
Host smart-e91d1cbc-9e42-462b-8fb5-8c5e08410c9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=21182166599707902948111748290540954294269353810493875668458957491370350122845 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.21182166599707902948111748290540954294269353810493875668458957491370350122845
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.93009057409844016917307293234588677688185596573142812573596432607370870400751
Short name T17
Test name
Test status
Simulation time 3310545935 ps
CPU time 28.1 seconds
Started Nov 22 01:58:46 PM PST 23
Finished Nov 22 01:59:21 PM PST 23
Peak memory 203272 kb
Host smart-0f1d4594-2d9a-4439-83e1-0b1fbff7cf2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93009057409844016917307293234588677688185596573142812573596432607370870400751 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.93009057409844016917307293234588677688185596573142812573596432607370870400751
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.14603926005783285431369690017754800597813601713490122035801106724482947180833
Short name T253
Test name
Test status
Simulation time 4402420935 ps
CPU time 34.72 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 01:59:04 PM PST 23
Peak memory 203276 kb
Host smart-26a47985-23f5-44cd-8a10-8f026869dc3c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14603926005783285431369690017754800597813601713490122035801106724482947180833 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 35.xbar_error_random.14603926005783285431369690017754800597813601713490122035801106724482947180833
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.38594974477488640396950522277818987623235330983798041680759169681325752257635
Short name T218
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.76 seconds
Started Nov 22 01:58:30 PM PST 23
Finished Nov 22 01:59:11 PM PST 23
Peak memory 211420 kb
Host smart-42609004-0852-4aa1-8413-2c291aa925c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=38594974477488640396950522277818987623235330983798041680759169681325752257635 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 35.xbar_random.38594974477488640396950522277818987623235330983798041680759169681325752257635
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.23119710834309356201453031853591337731621900022505222477312097867540662988302
Short name T293
Test name
Test status
Simulation time 188793233435 ps
CPU time 328.86 seconds
Started Nov 22 01:58:36 PM PST 23
Finished Nov 22 02:04:06 PM PST 23
Peak memory 204824 kb
Host smart-b3850f8a-75b5-4569-ab69-5390802951d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=23119710834309356201453031853591337731621900022505222477312097867540662988302 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 35.xbar_random_large_delays.23119710834309356201453031853591337731621900022505222477312097867540662988302
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.34187752536782913827259469101448948399836691205515330197977765709753983129849
Short name T672
Test name
Test status
Simulation time 126189108435 ps
CPU time 314.93 seconds
Started Nov 22 01:58:30 PM PST 23
Finished Nov 22 02:03:47 PM PST 23
Peak memory 211396 kb
Host smart-45f62f5f-8c58-46fa-b456-7d75a0b5dae3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=34187752536782913827259469101448948399836691205515330197977765709753983129849 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.34187752536782913827259469101448948399836691205515330197977765709753983129849
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.11577795882027641733039676273952070518659815333728927785067751305788810996178
Short name T386
Test name
Test status
Simulation time 766920935 ps
CPU time 27.2 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 01:59:09 PM PST 23
Peak memory 203848 kb
Host smart-9eac5502-e52f-4021-a460-b658affcd988
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11577795882027641733039676273952070518659815333728927785067751305788810996178 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.11577795882027641733039676273952070518659815333728927785067751305788810996178
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.108417689356372257635225525362496275219189416420846612036581950299904564757737
Short name T573
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.07 seconds
Started Nov 22 01:58:42 PM PST 23
Finished Nov 22 01:59:23 PM PST 23
Peak memory 204216 kb
Host smart-f4b9ca8f-bb2b-4e4f-bb69-db336e74f149
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=108417689356372257635225525362496275219189416420846612036581950299904564757737 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 35.xbar_same_source.108417689356372257635225525362496275219189416420846612036581950299904564757737
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.29932853985610041104173917311389063734596435916588898954211109930473593691968
Short name T131
Test name
Test status
Simulation time 669983435 ps
CPU time 4.32 seconds
Started Nov 22 01:58:40 PM PST 23
Finished Nov 22 01:58:46 PM PST 23
Peak memory 203068 kb
Host smart-edca552e-d2e3-4061-b1d4-6687e0d7d232
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29932853985610041104173917311389063734596435916588898954211109930473593691968 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 35.xbar_smoke.29932853985610041104173917311389063734596435916588898954211109930473593691968
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.16278176366009827681504023781526809266859461607642364279486063160837804080674
Short name T295
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.37 seconds
Started Nov 22 01:58:43 PM PST 23
Finished Nov 22 01:59:35 PM PST 23
Peak memory 203292 kb
Host smart-66ff4a93-a857-4cd9-8e04-98ace923f91d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=16278176366009827681504023781526809266859461607642364279486063160837804080674 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.16278176366009827681504023781526809266859461607642364279486063160837804080674
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.80206717765042745522311605403660481933762552452919618095421114961206904602967
Short name T324
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.23 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 01:59:17 PM PST 23
Peak memory 203276 kb
Host smart-c634a409-02c7-4aa6-814a-8acc83ba1309
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=80206717765042745522311605403660481933762552452919618095421114961206904602967 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.80206717765042745522311605403660481933762552452919618095421114961206904602967
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.21258334946878872835086043464793810999448925865779940066563454099845600711276
Short name T180
Test name
Test status
Simulation time 116233435 ps
CPU time 2.52 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 01:58:32 PM PST 23
Peak memory 203132 kb
Host smart-d4e945dd-34c1-4fe0-baa9-df2c5aa4f810
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21258334946878872835086043464793810999448925865779940066563454099845600711276 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.21258334946878872835086043464793810999448925865779940066563454099845600711276
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.113450634628207415545049368111696690492504080763996695502862529528221374788705
Short name T254
Test name
Test status
Simulation time 18904859184 ps
CPU time 130.5 seconds
Started Nov 22 01:58:34 PM PST 23
Finished Nov 22 02:00:46 PM PST 23
Peak memory 205932 kb
Host smart-7fc1634c-1398-495d-a892-67e9c91fc727
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=113450634628207415545049368111696690492504080763996695502862529528221374788705 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 35.xbar_stress_all.113450634628207415545049368111696690492504080763996695502862529528221374788705
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.13314559105407150483793757093332010629948485607365702303522529997248811171231
Short name T220
Test name
Test status
Simulation time 18894549184 ps
CPU time 119.46 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 02:00:30 PM PST 23
Peak memory 211436 kb
Host smart-015eae1f-282d-4402-811d-9d90ad4662a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13314559105407150483793757093332010629948485607365702303522529997248811171231 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 35.xbar_stress_all_with_error.13314559105407150483793757093332010629948485607365702303522529997248811171231
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.27051110862548289011828748442654368508186241810303707576290531360026667081058
Short name T738
Test name
Test status
Simulation time 5188549184 ps
CPU time 286.86 seconds
Started Nov 22 01:58:32 PM PST 23
Finished Nov 22 02:03:20 PM PST 23
Peak memory 208512 kb
Host smart-5c3790ba-0768-4d5a-957f-aed6bc9f73b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27051110862548289011828748442654368508186241810303707576290531360026667081058 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.27051110862548289011828748442654368508186241810303707576290531360026667081058
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.25863107253940503827477305709452809670984209347038276935435648363811654955728
Short name T886
Test name
Test status
Simulation time 5188549184 ps
CPU time 220.79 seconds
Started Nov 22 01:58:36 PM PST 23
Finished Nov 22 02:02:18 PM PST 23
Peak memory 219616 kb
Host smart-4843fb87-879c-4379-a072-9ebcb6ee4d8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25863107253940503827477305709452809670984209347038276935435648363811654955728 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.25863107253940503827477305709452809670984209347038276935435648363811654955728
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.76786003066375784901254920989376961195492910821452427334612575764429051058557
Short name T864
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.94 seconds
Started Nov 22 01:58:27 PM PST 23
Finished Nov 22 01:58:58 PM PST 23
Peak memory 211304 kb
Host smart-f54be62c-b54c-4193-80f5-6eb39f14b1cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76786003066375784901254920989376961195492910821452427334612575764429051058557 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 35.xbar_unmapped_addr.76786003066375784901254920989376961195492910821452427334612575764429051058557
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.43165895953079116838050819857334021985943758458242343925483829253069120042071
Short name T365
Test name
Test status
Simulation time 7399045935 ps
CPU time 62.06 seconds
Started Nov 22 01:58:42 PM PST 23
Finished Nov 22 01:59:48 PM PST 23
Peak memory 206376 kb
Host smart-53f8c8e6-663b-4e38-a5b1-cf67304bc11e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=43165895953079116838050819857334021985943758458242343925483829253069120042071 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.43165895953079116838050819857334021985943758458242343925483829253069120042071
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.60773742483824863184711166645084652077869932394655800239714447909192421688277
Short name T390
Test name
Test status
Simulation time 304288045935 ps
CPU time 768.39 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 02:11:19 PM PST 23
Peak memory 211428 kb
Host smart-0e276f35-e993-46f7-95d8-98a207448aa9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=60773742483824863184711166645084652077869932394655800239714447909192421688277 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.60773742483824863184711166645084652077869932394655800239714447909192421688277
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.12411848752824808874681686609473750365490483560548815602632667815228974969958
Short name T494
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.75 seconds
Started Nov 22 01:58:32 PM PST 23
Finished Nov 22 01:58:59 PM PST 23
Peak memory 203316 kb
Host smart-8bb55be2-9194-4c4a-be96-e7b6c7a15e53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12411848752824808874681686609473750365490483560548815602632667815228974969958 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.12411848752824808874681686609473750365490483560548815602632667815228974969958
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.50008588292960912810066823646859308498650021637281385663357581902843753951918
Short name T300
Test name
Test status
Simulation time 4402420935 ps
CPU time 32.99 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 01:59:17 PM PST 23
Peak memory 203056 kb
Host smart-a1a35424-c6fa-4a57-bac8-d9b1d77327fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=50008588292960912810066823646859308498650021637281385663357581902843753951918 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 36.xbar_error_random.50008588292960912810066823646859308498650021637281385663357581902843753951918
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.26760156701708051206464566761842496945679980760573189448809490197910998270527
Short name T92
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.74 seconds
Started Nov 22 01:58:30 PM PST 23
Finished Nov 22 01:59:10 PM PST 23
Peak memory 211476 kb
Host smart-dccf2598-51cc-4905-9db5-947f33ba43a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=26760156701708051206464566761842496945679980760573189448809490197910998270527 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 36.xbar_random.26760156701708051206464566761842496945679980760573189448809490197910998270527
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.113671479564383568882307359996837531121197230747730639676278062562675540730843
Short name T68
Test name
Test status
Simulation time 188793233435 ps
CPU time 322.45 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 02:03:53 PM PST 23
Peak memory 204836 kb
Host smart-e10dc25e-aa60-407d-96d5-dd70f4a12885
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=113671479564383568882307359996837531121197230747730639676278062562675540730843 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.113671479564383568882307359996837531121197230747730639676278062562675540730843
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.67876229317467566947221315435857314853119260931878804006783529458649292685678
Short name T269
Test name
Test status
Simulation time 126189108435 ps
CPU time 317.28 seconds
Started Nov 22 01:58:27 PM PST 23
Finished Nov 22 02:03:47 PM PST 23
Peak memory 211344 kb
Host smart-eed6f166-232d-438a-94e0-390c0ac7ab8d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=67876229317467566947221315435857314853119260931878804006783529458649292685678 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.67876229317467566947221315435857314853119260931878804006783529458649292685678
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.37159888379824366590360304940609427311676885715558320912230833326583427357907
Short name T162
Test name
Test status
Simulation time 766920935 ps
CPU time 26.02 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 01:58:57 PM PST 23
Peak memory 203832 kb
Host smart-2c97f803-2211-4225-a8f2-bcba46e2d5e8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37159888379824366590360304940609427311676885715558320912230833326583427357907 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.37159888379824366590360304940609427311676885715558320912230833326583427357907
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.56369292963726198787452558678141939800221785041667881678213049051580554295978
Short name T558
Test name
Test status
Simulation time 7116170935 ps
CPU time 36.19 seconds
Started Nov 22 01:58:32 PM PST 23
Finished Nov 22 01:59:10 PM PST 23
Peak memory 204376 kb
Host smart-3e6ce258-a78f-4593-825d-c61865d030b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56369292963726198787452558678141939800221785041667881678213049051580554295978 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 36.xbar_same_source.56369292963726198787452558678141939800221785041667881678213049051580554295978
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.54129950180487116579216317938942647217487183152876330568793351493281567397172
Short name T668
Test name
Test status
Simulation time 669983435 ps
CPU time 4.15 seconds
Started Nov 22 01:58:45 PM PST 23
Finished Nov 22 01:58:56 PM PST 23
Peak memory 203120 kb
Host smart-bee818b6-e16d-4a97-9797-9ae34960a7fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54129950180487116579216317938942647217487183152876330568793351493281567397172 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 36.xbar_smoke.54129950180487116579216317938942647217487183152876330568793351493281567397172
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.59189643581410206878611250759166442656620887683489465101768568623447260318565
Short name T588
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.6 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 01:59:19 PM PST 23
Peak memory 203296 kb
Host smart-e2328a9f-c017-4447-a839-4d40afbb73de
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=59189643581410206878611250759166442656620887683489465101768568623447260318565 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.59189643581410206878611250759166442656620887683489465101768568623447260318565
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.78512469496337930725863361456543555653912962894732258733746485248201449815215
Short name T471
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.76 seconds
Started Nov 22 01:58:31 PM PST 23
Finished Nov 22 01:59:18 PM PST 23
Peak memory 203276 kb
Host smart-b5f6742f-46e4-4f60-952c-540a68abd76a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=78512469496337930725863361456543555653912962894732258733746485248201449815215 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.78512469496337930725863361456543555653912962894732258733746485248201449815215
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.24607056935464118137455051213471989628248868848682167759162212705568480642075
Short name T577
Test name
Test status
Simulation time 116233435 ps
CPU time 2.42 seconds
Started Nov 22 01:58:43 PM PST 23
Finished Nov 22 01:58:49 PM PST 23
Peak memory 203132 kb
Host smart-bcd1e2c3-82cc-4951-95be-53e96445872f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24607056935464118137455051213471989628248868848682167759162212705568480642075 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.24607056935464118137455051213471989628248868848682167759162212705568480642075
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.53206551820748305521529815123773613014376949501806356425326904626832774586510
Short name T523
Test name
Test status
Simulation time 18904859184 ps
CPU time 132.27 seconds
Started Nov 22 01:58:31 PM PST 23
Finished Nov 22 02:00:45 PM PST 23
Peak memory 205852 kb
Host smart-48b37e15-5da2-44a4-aa82-f129c5dc3dd4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53206551820748305521529815123773613014376949501806356425326904626832774586510 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 36.xbar_stress_all.53206551820748305521529815123773613014376949501806356425326904626832774586510
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.52169152277846591882419589661722595844736811508522947190570894112012522572378
Short name T97
Test name
Test status
Simulation time 18894549184 ps
CPU time 119.26 seconds
Started Nov 22 01:58:34 PM PST 23
Finished Nov 22 02:00:35 PM PST 23
Peak memory 211436 kb
Host smart-8de32066-dce1-4303-a70e-a8a3a971c4af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=52169152277846591882419589661722595844736811508522947190570894112012522572378 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 36.xbar_stress_all_with_error.52169152277846591882419589661722595844736811508522947190570894112012522572378
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.82764277655239233134287958946180091993918705007600713112509351844633114858139
Short name T752
Test name
Test status
Simulation time 5188549184 ps
CPU time 293.16 seconds
Started Nov 22 01:58:32 PM PST 23
Finished Nov 22 02:03:27 PM PST 23
Peak memory 208508 kb
Host smart-64132031-d542-4da3-a1e9-2ba93f8227fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=82764277655239233134287958946180091993918705007600713112509351844633114858139 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.82764277655239233134287958946180091993918705007600713112509351844633114858139
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.47370949236537125621020985551475723683206367873085149452141460753042393452655
Short name T817
Test name
Test status
Simulation time 5188549184 ps
CPU time 224.69 seconds
Started Nov 22 01:58:46 PM PST 23
Finished Nov 22 02:02:38 PM PST 23
Peak memory 219660 kb
Host smart-b541b647-ed1a-440a-9848-9f5943d9efab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47370949236537125621020985551475723683206367873085149452141460753042393452655 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.47370949236537125621020985551475723683206367873085149452141460753042393452655
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.79717661182822276777183903744180999362442013479632229079255828827571319369184
Short name T89
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.62 seconds
Started Nov 22 01:58:35 PM PST 23
Finished Nov 22 01:59:06 PM PST 23
Peak memory 211380 kb
Host smart-c8244d49-74d2-458c-a784-b5cb64687f42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=79717661182822276777183903744180999362442013479632229079255828827571319369184 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 36.xbar_unmapped_addr.79717661182822276777183903744180999362442013479632229079255828827571319369184
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.81999769604106964386497938613008746641718621715617546947662778632481501754151
Short name T307
Test name
Test status
Simulation time 7399045935 ps
CPU time 67.55 seconds
Started Nov 22 01:58:49 PM PST 23
Finished Nov 22 02:00:03 PM PST 23
Peak memory 206348 kb
Host smart-03a017c6-6b02-40b5-8de6-0c8fc0ef93d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81999769604106964386497938613008746641718621715617546947662778632481501754151 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.81999769604106964386497938613008746641718621715617546947662778632481501754151
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.30753563788709045713599767247787366510670745370258784977344192355273526192695
Short name T715
Test name
Test status
Simulation time 304288045935 ps
CPU time 757.19 seconds
Started Nov 22 01:58:58 PM PST 23
Finished Nov 22 02:11:38 PM PST 23
Peak memory 211444 kb
Host smart-ec57c7a0-214f-4fac-952c-2fedb989888c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=30753563788709045713599767247787366510670745370258784977344192355273526192695 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.30753563788709045713599767247787366510670745370258784977344192355273526192695
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.98796639053732919173122861971826915675357631808333934479007662210374560482561
Short name T528
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.38 seconds
Started Nov 22 01:58:47 PM PST 23
Finished Nov 22 01:59:21 PM PST 23
Peak memory 203312 kb
Host smart-30f757cf-0d74-4088-a6a2-6a7b23a8498e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98796639053732919173122861971826915675357631808333934479007662210374560482561 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.98796639053732919173122861971826915675357631808333934479007662210374560482561
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.77939530753502199117850338118761535230235046933718246879098464585240128037083
Short name T496
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.27 seconds
Started Nov 22 01:58:46 PM PST 23
Finished Nov 22 01:59:26 PM PST 23
Peak memory 203196 kb
Host smart-373a5b42-3025-44ab-8849-28c024aa39d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=77939530753502199117850338118761535230235046933718246879098464585240128037083 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 37.xbar_error_random.77939530753502199117850338118761535230235046933718246879098464585240128037083
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.42764261358066551273033958317880102250396904448505432701482812408267413157737
Short name T382
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.65 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 01:59:08 PM PST 23
Peak memory 211360 kb
Host smart-d165b7d2-6d55-4e29-8fe1-8301e0b9e980
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=42764261358066551273033958317880102250396904448505432701482812408267413157737 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 37.xbar_random.42764261358066551273033958317880102250396904448505432701482812408267413157737
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.33532882773542235313137812713383037276016156864366383743930055268763902676900
Short name T232
Test name
Test status
Simulation time 188793233435 ps
CPU time 324.03 seconds
Started Nov 22 01:58:40 PM PST 23
Finished Nov 22 02:04:05 PM PST 23
Peak memory 204744 kb
Host smart-9a7d162b-02f7-44ac-a822-8be63c389760
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=33532882773542235313137812713383037276016156864366383743930055268763902676900 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 37.xbar_random_large_delays.33532882773542235313137812713383037276016156864366383743930055268763902676900
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.97192698158022559426864325333887211056190938706936352254411472744508505301624
Short name T167
Test name
Test status
Simulation time 766920935 ps
CPU time 25.82 seconds
Started Nov 22 01:58:43 PM PST 23
Finished Nov 22 01:59:12 PM PST 23
Peak memory 203800 kb
Host smart-2ac66a46-b315-44c6-88e9-599755311ca9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97192698158022559426864325333887211056190938706936352254411472744508505301624 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.97192698158022559426864325333887211056190938706936352254411472744508505301624
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.2433520917179543390479235665249369149945401576828531149954594208819532466942
Short name T273
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.16 seconds
Started Nov 22 01:58:46 PM PST 23
Finished Nov 22 01:59:31 PM PST 23
Peak memory 204224 kb
Host smart-c39cf7ce-e8b2-4785-a7b7-d6bfe513a5d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2433520917179543390479235665249369149945401576828531149954594208819532466942 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 37.xbar_same_source.2433520917179543390479235665249369149945401576828531149954594208819532466942
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.86455982511795945351853808624452518950442776569643063927944011227485012685190
Short name T497
Test name
Test status
Simulation time 669983435 ps
CPU time 4.16 seconds
Started Nov 22 01:58:30 PM PST 23
Finished Nov 22 01:58:36 PM PST 23
Peak memory 203124 kb
Host smart-4fa42533-c40d-4289-8c0a-4fa1029e72a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86455982511795945351853808624452518950442776569643063927944011227485012685190 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 37.xbar_smoke.86455982511795945351853808624452518950442776569643063927944011227485012685190
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.67354893765275863387523554967303645614322768930309339551681190978599542640589
Short name T332
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.43 seconds
Started Nov 22 01:58:34 PM PST 23
Finished Nov 22 01:59:23 PM PST 23
Peak memory 203276 kb
Host smart-f736787e-d1ff-4bfa-9639-28985d8e4a61
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=67354893765275863387523554967303645614322768930309339551681190978599542640589 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.67354893765275863387523554967303645614322768930309339551681190978599542640589
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.15886002548962260587430790454153922532332453721484685099751504820888018861736
Short name T195
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.06 seconds
Started Nov 22 01:58:46 PM PST 23
Finished Nov 22 01:59:38 PM PST 23
Peak memory 203224 kb
Host smart-15e6fdfc-8138-46b3-82ab-47f25895b8e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=15886002548962260587430790454153922532332453721484685099751504820888018861736 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.15886002548962260587430790454153922532332453721484685099751504820888018861736
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.114574029192010057634964491017889095034932630692093950760967662259825138688569
Short name T178
Test name
Test status
Simulation time 116233435 ps
CPU time 2.38 seconds
Started Nov 22 01:58:34 PM PST 23
Finished Nov 22 01:58:38 PM PST 23
Peak memory 203144 kb
Host smart-89a84fdd-6d8d-4f95-bf1d-d51f2ef8760e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114574029192010057634964491017889095034932630692093950760967662259825138688569 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.114574029192010057634964491017889095034932630692093950760967662259825138688569
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.356381568639212288815917683590588999451223016143670316273666128297743046646
Short name T383
Test name
Test status
Simulation time 18904859184 ps
CPU time 125.17 seconds
Started Nov 22 01:58:58 PM PST 23
Finished Nov 22 02:01:06 PM PST 23
Peak memory 205848 kb
Host smart-ff91336c-5476-43ed-a57b-fa4cc20bb24b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=356381568639212288815917683590588999451223016143670316273666128297743046646 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_l
og /dev/null -cm_name 37.xbar_stress_all.356381568639212288815917683590588999451223016143670316273666128297743046646
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.69865996742171396324618291644861097437517875313564172354980645072801409270909
Short name T261
Test name
Test status
Simulation time 18894549184 ps
CPU time 127.44 seconds
Started Nov 22 01:58:35 PM PST 23
Finished Nov 22 02:00:44 PM PST 23
Peak memory 211436 kb
Host smart-159aa52c-4b33-443c-a04c-05a3991cdeb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69865996742171396324618291644861097437517875313564172354980645072801409270909 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 37.xbar_stress_all_with_error.69865996742171396324618291644861097437517875313564172354980645072801409270909
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.48348239200809620014263930295465779527255628697816634774896162848836911334794
Short name T498
Test name
Test status
Simulation time 5188549184 ps
CPU time 286.74 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 02:03:57 PM PST 23
Peak memory 208504 kb
Host smart-48520034-e935-42b6-96c5-f54771cdfa49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48348239200809620014263930295465779527255628697816634774896162848836911334794 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.48348239200809620014263930295465779527255628697816634774896162848836911334794
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.25928584950298000009097545349769618084220507530888423440882852821367419016881
Short name T611
Test name
Test status
Simulation time 5188549184 ps
CPU time 226.4 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 02:02:18 PM PST 23
Peak memory 219504 kb
Host smart-68dc46ed-3ce5-4cd3-b1f7-9d64d4d8b617
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25928584950298000009097545349769618084220507530888423440882852821367419016881 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.25928584950298000009097545349769618084220507530888423440882852821367419016881
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3379383542543996602690660056008378081402685789088903190372348688019337427688
Short name T637
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.21 seconds
Started Nov 22 01:58:53 PM PST 23
Finished Nov 22 01:59:26 PM PST 23
Peak memory 211344 kb
Host smart-0d91fa7b-3b9c-4a42-b3e1-9a3664364a87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3379383542543996602690660056008378081402685789088903190372348688019337427688 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3379383542543996602690660056008378081402685789088903190372348688019337427688
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.60654532007505218706807407445910793268382416766468347621728089850743291611636
Short name T56
Test name
Test status
Simulation time 7399045935 ps
CPU time 61.28 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 01:59:32 PM PST 23
Peak memory 206340 kb
Host smart-2394e603-e40a-4cb8-9490-b1206dabfbb8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=60654532007505218706807407445910793268382416766468347621728089850743291611636 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.60654532007505218706807407445910793268382416766468347621728089850743291611636
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.81357661888937463866461376448094015949525607039072869374189579914419366265603
Short name T64
Test name
Test status
Simulation time 304288045935 ps
CPU time 793.9 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 02:11:45 PM PST 23
Peak memory 211372 kb
Host smart-25e28041-09ca-4aea-801e-0ace1d75d343
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=81357661888937463866461376448094015949525607039072869374189579914419366265603 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.81357661888937463866461376448094015949525607039072869374189579914419366265603
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.81480620618233397702990709728121451323499547545117938188252643510340457453975
Short name T503
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.34 seconds
Started Nov 22 01:58:33 PM PST 23
Finished Nov 22 01:59:02 PM PST 23
Peak memory 203280 kb
Host smart-1c2bb4d0-7e8e-4361-b4ec-c29a6daeb0c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81480620618233397702990709728121451323499547545117938188252643510340457453975 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.81480620618233397702990709728121451323499547545117938188252643510340457453975
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.30918552591819695967975856541080416033655214465473082506966420070571856273687
Short name T548
Test name
Test status
Simulation time 4402420935 ps
CPU time 34.8 seconds
Started Nov 22 01:58:34 PM PST 23
Finished Nov 22 01:59:11 PM PST 23
Peak memory 203256 kb
Host smart-96b77be8-5df3-479e-9485-3b0552e444fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30918552591819695967975856541080416033655214465473082506966420070571856273687 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 38.xbar_error_random.30918552591819695967975856541080416033655214465473082506966420070571856273687
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.37485941222434777265935773308384782544331981310272427735700364739005213442588
Short name T406
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.4 seconds
Started Nov 22 01:58:33 PM PST 23
Finished Nov 22 01:59:12 PM PST 23
Peak memory 211420 kb
Host smart-7cd07e8f-f012-4bc3-ad5a-73d8ac2ebfa3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=37485941222434777265935773308384782544331981310272427735700364739005213442588 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 38.xbar_random.37485941222434777265935773308384782544331981310272427735700364739005213442588
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.102609258867386018026821620486302901436033567650493267747141673358509865074690
Short name T69
Test name
Test status
Simulation time 188793233435 ps
CPU time 324.23 seconds
Started Nov 22 01:58:30 PM PST 23
Finished Nov 22 02:03:56 PM PST 23
Peak memory 204816 kb
Host smart-a4e3d5dd-b2e2-4d16-87e8-72dccc6cc360
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=102609258867386018026821620486302901436033567650493267747141673358509865074690 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.102609258867386018026821620486302901436033567650493267747141673358509865074690
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.89862559267670228441224729943380155475502933236720844243123874118216682578064
Short name T354
Test name
Test status
Simulation time 126189108435 ps
CPU time 324.15 seconds
Started Nov 22 01:58:29 PM PST 23
Finished Nov 22 02:03:56 PM PST 23
Peak memory 211348 kb
Host smart-a0360ac4-c7bb-46ee-9f7c-5177da9a3ebe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=89862559267670228441224729943380155475502933236720844243123874118216682578064 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.89862559267670228441224729943380155475502933236720844243123874118216682578064
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.41260891499361258492378803872147199211756145773030113551761090823849771453653
Short name T19
Test name
Test status
Simulation time 766920935 ps
CPU time 25.04 seconds
Started Nov 22 01:58:40 PM PST 23
Finished Nov 22 01:59:06 PM PST 23
Peak memory 203900 kb
Host smart-252d4cd7-1a14-4e22-b5b3-34d00089d747
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41260891499361258492378803872147199211756145773030113551761090823849771453653 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.41260891499361258492378803872147199211756145773030113551761090823849771453653
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.95065949696484385889299953276047800612178433910735381343947619292208387304908
Short name T729
Test name
Test status
Simulation time 7116170935 ps
CPU time 36.58 seconds
Started Nov 22 01:58:33 PM PST 23
Finished Nov 22 01:59:12 PM PST 23
Peak memory 204376 kb
Host smart-c5c8b8bb-a6a3-4b0f-a962-c48685a34db2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95065949696484385889299953276047800612178433910735381343947619292208387304908 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 38.xbar_same_source.95065949696484385889299953276047800612178433910735381343947619292208387304908
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.102158613873754870501247246132816625609694032437192252369672942293796206858109
Short name T743
Test name
Test status
Simulation time 669983435 ps
CPU time 4.2 seconds
Started Nov 22 01:58:32 PM PST 23
Finished Nov 22 01:58:37 PM PST 23
Peak memory 203140 kb
Host smart-00119208-0517-46dc-9a1b-d83073c74559
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102158613873754870501247246132816625609694032437192252369672942293796206858109 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 38.xbar_smoke.102158613873754870501247246132816625609694032437192252369672942293796206858109
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.75830360464296069881517949189289073715198464904354142870069694230279697285515
Short name T664
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.93 seconds
Started Nov 22 01:58:43 PM PST 23
Finished Nov 22 01:59:35 PM PST 23
Peak memory 203228 kb
Host smart-997c5a8a-fa4b-4e40-b455-fa91128d835a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=75830360464296069881517949189289073715198464904354142870069694230279697285515 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.75830360464296069881517949189289073715198464904354142870069694230279697285515
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.5539225395960016933275205432217365101304707582176334245535277009765277421794
Short name T8
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.51 seconds
Started Nov 22 01:58:32 PM PST 23
Finished Nov 22 01:59:18 PM PST 23
Peak memory 203276 kb
Host smart-5c3a8b4a-5114-4b70-b50a-057ccec79361
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=5539225395960016933275205432217365101304707582176334245535277009765277421794 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.5539225395960016933275205432217365101304707582176334245535277009765277421794
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.95197541509481026543506495041618956002159599209901481252759533997214502337408
Short name T582
Test name
Test status
Simulation time 116233435 ps
CPU time 2.5 seconds
Started Nov 22 01:58:33 PM PST 23
Finished Nov 22 01:58:37 PM PST 23
Peak memory 203120 kb
Host smart-e7a8d226-8e36-44f4-bb71-24d41194a621
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95197541509481026543506495041618956002159599209901481252759533997214502337408 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.95197541509481026543506495041618956002159599209901481252759533997214502337408
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.97957454339468966868300441843090352395956246273758197440081641955181702041156
Short name T291
Test name
Test status
Simulation time 18904859184 ps
CPU time 135.7 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 02:00:45 PM PST 23
Peak memory 205852 kb
Host smart-8cd8131e-d513-48e7-b5e6-53336bb5e690
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=97957454339468966868300441843090352395956246273758197440081641955181702041156 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 38.xbar_stress_all.97957454339468966868300441843090352395956246273758197440081641955181702041156
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.55627383059733385754096187267757959162629707015712653904052418185897422644567
Short name T140
Test name
Test status
Simulation time 18894549184 ps
CPU time 118.5 seconds
Started Nov 22 01:58:39 PM PST 23
Finished Nov 22 02:00:39 PM PST 23
Peak memory 211400 kb
Host smart-21369df8-d3d8-456d-abb3-2981709651db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55627383059733385754096187267757959162629707015712653904052418185897422644567 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 38.xbar_stress_all_with_error.55627383059733385754096187267757959162629707015712653904052418185897422644567
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.104552443968790423170363833247221037575127920211869359569516380853309626512359
Short name T786
Test name
Test status
Simulation time 5188549184 ps
CPU time 297.47 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 02:03:39 PM PST 23
Peak memory 208536 kb
Host smart-c77b695f-c527-4cad-bdb6-82de200aada7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104552443968790423170363833247221037575127920211869359569516380853309626512359 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.104552443968790423170363833247221037575127920211869359569516380853309626512359
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.114176775398062596384315199857965336903366312704811129194059696310560472049199
Short name T447
Test name
Test status
Simulation time 5188549184 ps
CPU time 229.43 seconds
Started Nov 22 01:58:28 PM PST 23
Finished Nov 22 02:02:19 PM PST 23
Peak memory 219628 kb
Host smart-cc76625c-d17e-49ba-9db2-4c150435432a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=114176775398062596384315199857965336903366312704811129194059696310560472049199 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.114176775398062596384315199857965336903366312704811129194059696310560472049199
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.6813451554699462262133415282068366457381192592062269365117491943728372416672
Short name T155
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.77 seconds
Started Nov 22 01:58:27 PM PST 23
Finished Nov 22 01:58:58 PM PST 23
Peak memory 211304 kb
Host smart-c45ef0d1-5348-485c-8044-c39b4789669c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6813451554699462262133415282068366457381192592062269365117491943728372416672 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 38.xbar_unmapped_addr.6813451554699462262133415282068366457381192592062269365117491943728372416672
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.40719947677386964788619546997451603551588247921398959009542053644068199216331
Short name T883
Test name
Test status
Simulation time 7399045935 ps
CPU time 63.56 seconds
Started Nov 22 01:58:35 PM PST 23
Finished Nov 22 01:59:40 PM PST 23
Peak memory 206348 kb
Host smart-b71b3980-d6c3-453a-8b74-3bc6459d582c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40719947677386964788619546997451603551588247921398959009542053644068199216331 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.40719947677386964788619546997451603551588247921398959009542053644068199216331
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.94752590368404441812429805912168934571964901402096380507449387675842005350765
Short name T829
Test name
Test status
Simulation time 304288045935 ps
CPU time 755.18 seconds
Started Nov 22 01:58:45 PM PST 23
Finished Nov 22 02:11:27 PM PST 23
Peak memory 211288 kb
Host smart-2704a0b1-1771-477e-94b3-b42062e74ed7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=94752590368404441812429805912168934571964901402096380507449387675842005350765 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.94752590368404441812429805912168934571964901402096380507449387675842005350765
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.13806649431325183589717325482375895375778667139765185050710783378495802865579
Short name T872
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.53 seconds
Started Nov 22 01:58:58 PM PST 23
Finished Nov 22 01:59:27 PM PST 23
Peak memory 203312 kb
Host smart-01bac1d9-b5cc-46d3-a8a2-ce9f2b1c55cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13806649431325183589717325482375895375778667139765185050710783378495802865579 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.13806649431325183589717325482375895375778667139765185050710783378495802865579
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.94403353086482692676161141517203070094613992988217135376900821214775534009464
Short name T372
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.45 seconds
Started Nov 22 01:58:57 PM PST 23
Finished Nov 22 01:59:34 PM PST 23
Peak memory 203224 kb
Host smart-0d74733c-17ea-4f16-b77d-8c1e8fb04b5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94403353086482692676161141517203070094613992988217135376900821214775534009464 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 39.xbar_error_random.94403353086482692676161141517203070094613992988217135376900821214775534009464
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.42020019016435355180717791758891808736848970565210361933107687155246061812661
Short name T196
Test name
Test status
Simulation time 4402420935 ps
CPU time 40.22 seconds
Started Nov 22 01:58:40 PM PST 23
Finished Nov 22 01:59:21 PM PST 23
Peak memory 211368 kb
Host smart-af2e828a-0096-4299-8d63-bf68bae3c321
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=42020019016435355180717791758891808736848970565210361933107687155246061812661 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 39.xbar_random.42020019016435355180717791758891808736848970565210361933107687155246061812661
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.59987283187735215154019404552229998020592186343868490794715122162844252712929
Short name T845
Test name
Test status
Simulation time 188793233435 ps
CPU time 324.12 seconds
Started Nov 22 01:58:33 PM PST 23
Finished Nov 22 02:03:59 PM PST 23
Peak memory 204908 kb
Host smart-d10e1afc-4936-47bf-8976-1d38c821a9c0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=59987283187735215154019404552229998020592186343868490794715122162844252712929 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 39.xbar_random_large_delays.59987283187735215154019404552229998020592186343868490794715122162844252712929
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.18285588232417183666651030938846155465609436626957190944233654502800987154757
Short name T628
Test name
Test status
Simulation time 126189108435 ps
CPU time 320.39 seconds
Started Nov 22 01:58:40 PM PST 23
Finished Nov 22 02:04:02 PM PST 23
Peak memory 211360 kb
Host smart-9c31f495-eb83-4b2f-8a97-df3d6b1aa7e3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=18285588232417183666651030938846155465609436626957190944233654502800987154757 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.18285588232417183666651030938846155465609436626957190944233654502800987154757
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.70595313840789475767653415977335722912911672707936515988997688396979044221477
Short name T653
Test name
Test status
Simulation time 766920935 ps
CPU time 23.94 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 01:59:08 PM PST 23
Peak memory 203824 kb
Host smart-a4cc102e-47ae-4596-8c60-0680221904da
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70595313840789475767653415977335722912911672707936515988997688396979044221477 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.70595313840789475767653415977335722912911672707936515988997688396979044221477
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.100680484955881242776361322078038221547352785779851720108305512715071468162048
Short name T779
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.25 seconds
Started Nov 22 01:58:44 PM PST 23
Finished Nov 22 01:59:30 PM PST 23
Peak memory 204296 kb
Host smart-ff238781-7411-40c8-9e51-4cd4a5a97ee4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=100680484955881242776361322078038221547352785779851720108305512715071468162048 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 39.xbar_same_source.100680484955881242776361322078038221547352785779851720108305512715071468162048
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.73071909704027066390402604685292312931182747385136471799396320118262467145488
Short name T719
Test name
Test status
Simulation time 669983435 ps
CPU time 4.09 seconds
Started Nov 22 01:58:42 PM PST 23
Finished Nov 22 01:58:49 PM PST 23
Peak memory 203128 kb
Host smart-df5a1b26-c00e-4534-8de7-896667d01624
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73071909704027066390402604685292312931182747385136471799396320118262467145488 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 39.xbar_smoke.73071909704027066390402604685292312931182747385136471799396320118262467145488
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.9493106860651480628314528003015749481446640349584376411693490928788352301020
Short name T862
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.77 seconds
Started Nov 22 01:58:45 PM PST 23
Finished Nov 22 01:59:40 PM PST 23
Peak memory 203268 kb
Host smart-8b7a329f-d702-4ad9-a46c-496399d16760
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=9493106860651480628314528003015749481446640349584376411693490928788352301020 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.9493106860651480628314528003015749481446640349584376411693490928788352301020
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.96856841864081100032959652678367383705244511971416680292667645361083074796113
Short name T146
Test name
Test status
Simulation time 17662295935 ps
CPU time 43.49 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 01:59:26 PM PST 23
Peak memory 203276 kb
Host smart-b6204112-d0c4-40dd-bdbf-d40f2480b891
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=96856841864081100032959652678367383705244511971416680292667645361083074796113 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.96856841864081100032959652678367383705244511971416680292667645361083074796113
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.43173340015121975635174889236412955058765573060271869078830642880034192922325
Short name T104
Test name
Test status
Simulation time 116233435 ps
CPU time 2.46 seconds
Started Nov 22 01:58:34 PM PST 23
Finished Nov 22 01:58:38 PM PST 23
Peak memory 203104 kb
Host smart-16cfa7fb-175b-4e1a-822e-0ae91ef3d13e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43173340015121975635174889236412955058765573060271869078830642880034192922325 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.43173340015121975635174889236412955058765573060271869078830642880034192922325
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.30950575335193316037268373313941855619124370222808588920865995233258459307784
Short name T677
Test name
Test status
Simulation time 18904859184 ps
CPU time 131.29 seconds
Started Nov 22 01:58:44 PM PST 23
Finished Nov 22 02:01:03 PM PST 23
Peak memory 205828 kb
Host smart-537cad37-5127-4b1e-b704-d986b963d1f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=30950575335193316037268373313941855619124370222808588920865995233258459307784 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 39.xbar_stress_all.30950575335193316037268373313941855619124370222808588920865995233258459307784
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.20744430356196539858169384904035789801299487029343333890513218604089973494733
Short name T460
Test name
Test status
Simulation time 18894549184 ps
CPU time 117.89 seconds
Started Nov 22 01:58:52 PM PST 23
Finished Nov 22 02:00:53 PM PST 23
Peak memory 211440 kb
Host smart-eeb678cc-be6a-48e7-beb2-d07e18f4cc29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20744430356196539858169384904035789801299487029343333890513218604089973494733 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 39.xbar_stress_all_with_error.20744430356196539858169384904035789801299487029343333890513218604089973494733
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.33639706816358613907462475425714966509491671276228705069863943972801660703631
Short name T493
Test name
Test status
Simulation time 5188549184 ps
CPU time 289.9 seconds
Started Nov 22 01:58:57 PM PST 23
Finished Nov 22 02:03:50 PM PST 23
Peak memory 208508 kb
Host smart-9dfc22da-8252-43ba-9a2f-f42a929c1432
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33639706816358613907462475425714966509491671276228705069863943972801660703631 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.33639706816358613907462475425714966509491671276228705069863943972801660703631
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.61524108045871645603395422727619693406063355846618869615848695560634870616367
Short name T860
Test name
Test status
Simulation time 5188549184 ps
CPU time 226.9 seconds
Started Nov 22 01:58:51 PM PST 23
Finished Nov 22 02:02:42 PM PST 23
Peak memory 219624 kb
Host smart-3f6836a9-0d7b-4861-b303-163f5f260f02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=61524108045871645603395422727619693406063355846618869615848695560634870616367 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.61524108045871645603395422727619693406063355846618869615848695560634870616367
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.62090533706304405050292793579168588360133555710803048551230348766730962097203
Short name T486
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.88 seconds
Started Nov 22 01:58:45 PM PST 23
Finished Nov 22 01:59:22 PM PST 23
Peak memory 211388 kb
Host smart-8f995848-e9ed-4bb1-a161-bcd75f122805
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62090533706304405050292793579168588360133555710803048551230348766730962097203 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 39.xbar_unmapped_addr.62090533706304405050292793579168588360133555710803048551230348766730962097203
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.10312790533052578143628751316582078870387588521288545475726542152911268924350
Short name T747
Test name
Test status
Simulation time 7399045935 ps
CPU time 68.16 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:57:30 PM PST 23
Peak memory 211444 kb
Host smart-85bd1b18-a9ac-4cfd-97c2-d7c408a978c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10312790533052578143628751316582078870387588521288545475726542152911268924350 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.10312790533052578143628751316582078870387588521288545475726542152911268924350
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.82592738577964842684699644215596733227859032895703987529957151307552568275633
Short name T858
Test name
Test status
Simulation time 304288045935 ps
CPU time 778.27 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 02:09:19 PM PST 23
Peak memory 211264 kb
Host smart-b8053422-1ee3-4760-aa32-4f998c95ff45
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=82592738577964842684699644215596733227859032895703987529957151307552568275633 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.82592738577964842684699644215596733227859032895703987529957151307552568275633
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.22456348743121377380234442651164575612126279034056263789489552532063721088994
Short name T790
Test name
Test status
Simulation time 3310545935 ps
CPU time 28.05 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 01:56:46 PM PST 23
Peak memory 203312 kb
Host smart-1435bdc5-c4e4-4272-9eea-a5b91a00b249
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22456348743121377380234442651164575612126279034056263789489552532063721088994 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.22456348743121377380234442651164575612126279034056263789489552532063721088994
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.2853805830412698263073521608287017606672615985813012820098005644025873962018
Short name T855
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.67 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 01:56:56 PM PST 23
Peak memory 203176 kb
Host smart-2964b94b-b2ba-415c-b071-8ae34345b2c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2853805830412698263073521608287017606672615985813012820098005644025873962018 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 4.xbar_error_random.2853805830412698263073521608287017606672615985813012820098005644025873962018
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.33999458193378869352380837104479253236069915520431409574563692080876474899395
Short name T712
Test name
Test status
Simulation time 4402420935 ps
CPU time 39.28 seconds
Started Nov 22 01:56:15 PM PST 23
Finished Nov 22 01:56:56 PM PST 23
Peak memory 211440 kb
Host smart-8a5b191c-9e7e-4ad5-89ed-bda1a8e06a5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33999458193378869352380837104479253236069915520431409574563692080876474899395 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 4.xbar_random.33999458193378869352380837104479253236069915520431409574563692080876474899395
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.13390440013148973071202636651391227361019487619426684264386759396405737062951
Short name T30
Test name
Test status
Simulation time 188793233435 ps
CPU time 323.76 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 02:01:45 PM PST 23
Peak memory 204772 kb
Host smart-00a19a1f-5ae6-4aff-b7e0-fbf11d2096de
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=13390440013148973071202636651391227361019487619426684264386759396405737062951 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 4.xbar_random_large_delays.13390440013148973071202636651391227361019487619426684264386759396405737062951
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.94028873104371495913784088811478904460274735728575458149711207099415673741592
Short name T784
Test name
Test status
Simulation time 126189108435 ps
CPU time 325.49 seconds
Started Nov 22 01:56:18 PM PST 23
Finished Nov 22 02:01:45 PM PST 23
Peak memory 211540 kb
Host smart-43b9f54b-6186-47aa-b4d2-be3f035f9265
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=94028873104371495913784088811478904460274735728575458149711207099415673741592 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.94028873104371495913784088811478904460274735728575458149711207099415673741592
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2045330526946300130451648386032688456229144072346824892018271782551198166084
Short name T258
Test name
Test status
Simulation time 766920935 ps
CPU time 27.57 seconds
Started Nov 22 01:56:16 PM PST 23
Finished Nov 22 01:56:45 PM PST 23
Peak memory 211340 kb
Host smart-9f73f711-053e-437f-be26-bb2c4e262701
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045330526946300130451648386032688456229144072346824892018271782551198166084 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2045330526946300130451648386032688456229144072346824892018271782551198166084
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.33101456480475704659516845503345644606105379744173730625296638992664945313988
Short name T675
Test name
Test status
Simulation time 7116170935 ps
CPU time 36.84 seconds
Started Nov 22 01:56:15 PM PST 23
Finished Nov 22 01:56:53 PM PST 23
Peak memory 204288 kb
Host smart-0b0dcbe0-cc88-4c5d-8144-4ecbb56d3bf8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33101456480475704659516845503345644606105379744173730625296638992664945313988 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 4.xbar_same_source.33101456480475704659516845503345644606105379744173730625296638992664945313988
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.93950542237265022704205058354139167634695939235074132629927854734955816002397
Short name T703
Test name
Test status
Simulation time 669983435 ps
CPU time 4.09 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 01:56:22 PM PST 23
Peak memory 203100 kb
Host smart-4084d31e-b0dd-4894-8508-a40c6dc5274a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93950542237265022704205058354139167634695939235074132629927854734955816002397 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 4.xbar_smoke.93950542237265022704205058354139167634695939235074132629927854734955816002397
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.75720860470508276951589266076255372309541554086834022841294767016631794096125
Short name T455
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.15 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 01:57:07 PM PST 23
Peak memory 203224 kb
Host smart-fe75c45f-7b63-4284-8a7e-d17e07d69873
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=75720860470508276951589266076255372309541554086834022841294767016631794096125 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.75720860470508276951589266076255372309541554086834022841294767016631794096125
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.38211449263512929954552553667024852016714892975248346536484546713845584360432
Short name T243
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.32 seconds
Started Nov 22 01:56:18 PM PST 23
Finished Nov 22 01:57:04 PM PST 23
Peak memory 203236 kb
Host smart-636e74a3-aa38-4ff8-9bfa-06cacf172c45
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=38211449263512929954552553667024852016714892975248346536484546713845584360432 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.38211449263512929954552553667024852016714892975248346536484546713845584360432
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.69910344969146034818172944632995310889506510244297394384579064133774531121749
Short name T482
Test name
Test status
Simulation time 116233435 ps
CPU time 2.71 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:56:24 PM PST 23
Peak memory 203112 kb
Host smart-43f4c4ac-1cc6-45c0-ad41-c4db6ebaaba2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69910344969146034818172944632995310889506510244297394384579064133774531121749 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.69910344969146034818172944632995310889506510244297394384579064133774531121749
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.35206296539304323339408957486792417715516319277863936454922883844663397476203
Short name T391
Test name
Test status
Simulation time 18904859184 ps
CPU time 140.82 seconds
Started Nov 22 01:56:35 PM PST 23
Finished Nov 22 01:58:56 PM PST 23
Peak memory 205868 kb
Host smart-69462292-c92a-455d-ad13-c66a7e4f3a7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35206296539304323339408957486792417715516319277863936454922883844663397476203 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 4.xbar_stress_all.35206296539304323339408957486792417715516319277863936454922883844663397476203
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3809704680230429541465863634540483268447289956970798626231327690972607047987
Short name T128
Test name
Test status
Simulation time 18894549184 ps
CPU time 129.23 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 01:58:32 PM PST 23
Peak memory 211384 kb
Host smart-88e92146-65f3-4011-961c-b956dee54ca5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3809704680230429541465863634540483268447289956970798626231327690972607047987 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 4.xbar_stress_all_with_error.3809704680230429541465863634540483268447289956970798626231327690972607047987
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1932820323870070299462010668170221449084701139046458426464270569774146298538
Short name T12
Test name
Test status
Simulation time 5188549184 ps
CPU time 296.99 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 02:01:21 PM PST 23
Peak memory 208456 kb
Host smart-a9426b70-f74b-4d22-b45e-2382a275f8e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1932820323870070299462010668170221449084701139046458426464270569774146298538 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.1932820323870070299462010668170221449084701139046458426464270569774146298538
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.97056512615108567499747243583736542364652578977137214510625920537966681898254
Short name T687
Test name
Test status
Simulation time 5188549184 ps
CPU time 229.59 seconds
Started Nov 22 01:56:21 PM PST 23
Finished Nov 22 02:00:12 PM PST 23
Peak memory 219616 kb
Host smart-55dc6fde-e36e-43fd-80b4-ff4923d8c75a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=97056512615108567499747243583736542364652578977137214510625920537966681898254 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.97056512615108567499747243583736542364652578977137214510625920537966681898254
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.28230848782182397398782488820952292006319701779562552796142351909224189152756
Short name T660
Test name
Test status
Simulation time 3307045935 ps
CPU time 27.68 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 01:56:46 PM PST 23
Peak memory 211344 kb
Host smart-06ae7088-ae2b-4704-8e93-638b8d4ffa51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28230848782182397398782488820952292006319701779562552796142351909224189152756 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 4.xbar_unmapped_addr.28230848782182397398782488820952292006319701779562552796142351909224189152756
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.87144518977228060809533824779261123900339763421634162171686626072299715983368
Short name T827
Test name
Test status
Simulation time 7399045935 ps
CPU time 62.92 seconds
Started Nov 22 01:58:58 PM PST 23
Finished Nov 22 02:00:03 PM PST 23
Peak memory 206336 kb
Host smart-5345a576-b1ab-439e-9c49-350c9490c0bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87144518977228060809533824779261123900339763421634162171686626072299715983368 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.87144518977228060809533824779261123900339763421634162171686626072299715983368
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.49962800902239457239975936713043772085119026920280067558873230422039911599720
Short name T851
Test name
Test status
Simulation time 304288045935 ps
CPU time 763.85 seconds
Started Nov 22 01:58:53 PM PST 23
Finished Nov 22 02:11:39 PM PST 23
Peak memory 211400 kb
Host smart-12e3a6e8-9b72-42fb-9a05-5cb95a29e20f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=49962800902239457239975936713043772085119026920280067558873230422039911599720 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.49962800902239457239975936713043772085119026920280067558873230422039911599720
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.113817322504214137833064596913909621585814539606347110046179128190534116738672
Short name T595
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.6 seconds
Started Nov 22 01:58:44 PM PST 23
Finished Nov 22 01:59:15 PM PST 23
Peak memory 203324 kb
Host smart-7c114db2-9f97-42dc-9660-8add910433b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=113817322504214137833064596913909621585814539606347110046179128190534116738672 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.113817322504214137833064596913909621585814539606347110046179128190534116738672
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.35356575084967320367752734604811581082406342439078028995720077358228601147388
Short name T676
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.02 seconds
Started Nov 22 01:58:43 PM PST 23
Finished Nov 22 01:59:19 PM PST 23
Peak memory 203164 kb
Host smart-b90a0175-2e5c-476c-873d-509aa5bbe4ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=35356575084967320367752734604811581082406342439078028995720077358228601147388 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 40.xbar_error_random.35356575084967320367752734604811581082406342439078028995720077358228601147388
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.91202646871240212427167561538409670177309047181920111846409503661086599016618
Short name T165
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.19 seconds
Started Nov 22 01:58:42 PM PST 23
Finished Nov 22 01:59:22 PM PST 23
Peak memory 211352 kb
Host smart-a51df1a1-360b-4788-b785-3698e8c405f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91202646871240212427167561538409670177309047181920111846409503661086599016618 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 40.xbar_random.91202646871240212427167561538409670177309047181920111846409503661086599016618
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.9151741656127023567396125726427777225753346433846737191392615116788429368716
Short name T32
Test name
Test status
Simulation time 188793233435 ps
CPU time 332.5 seconds
Started Nov 22 01:58:45 PM PST 23
Finished Nov 22 02:04:25 PM PST 23
Peak memory 204756 kb
Host smart-2bb0434a-adc1-47a4-9735-e3714dd22707
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=9151741656127023567396125726427777225753346433846737191392615116788429368716 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 40.xbar_random_large_delays.9151741656127023567396125726427777225753346433846737191392615116788429368716
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.23703685122381072581950353630929392681764731179308493730426020270204548341649
Short name T266
Test name
Test status
Simulation time 126189108435 ps
CPU time 320.71 seconds
Started Nov 22 01:58:46 PM PST 23
Finished Nov 22 02:04:14 PM PST 23
Peak memory 211496 kb
Host smart-f7de525e-2aa1-41c6-94c9-bce2dee94743
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=23703685122381072581950353630929392681764731179308493730426020270204548341649 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.23703685122381072581950353630929392681764731179308493730426020270204548341649
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.104732415200060413099860571616498062398315925208339662024218051926413464575476
Short name T768
Test name
Test status
Simulation time 7116170935 ps
CPU time 35.69 seconds
Started Nov 22 01:58:48 PM PST 23
Finished Nov 22 01:59:30 PM PST 23
Peak memory 204280 kb
Host smart-9d1f921e-d071-49ce-98ea-34ed64fd9f43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=104732415200060413099860571616498062398315925208339662024218051926413464575476 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 40.xbar_same_source.104732415200060413099860571616498062398315925208339662024218051926413464575476
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.67533268495567927756971911656650387969250158256172439768218396296717261534244
Short name T878
Test name
Test status
Simulation time 669983435 ps
CPU time 4.3 seconds
Started Nov 22 01:58:46 PM PST 23
Finished Nov 22 01:58:57 PM PST 23
Peak memory 203104 kb
Host smart-d5210a8a-32db-4a16-abe5-adb326be9ea2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=67533268495567927756971911656650387969250158256172439768218396296717261534244 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 40.xbar_smoke.67533268495567927756971911656650387969250158256172439768218396296717261534244
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.52554329744211647674164473986597615290321483091147121522566732540532660376410
Short name T305
Test name
Test status
Simulation time 28419483435 ps
CPU time 46.76 seconds
Started Nov 22 01:58:50 PM PST 23
Finished Nov 22 01:59:42 PM PST 23
Peak memory 203264 kb
Host smart-40ca8972-ad0c-4d93-8bc2-9defa9e82452
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=52554329744211647674164473986597615290321483091147121522566732540532660376410 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.52554329744211647674164473986597615290321483091147121522566732540532660376410
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.54216479164570301687942355075933785798197631199441102043048072955897457604404
Short name T809
Test name
Test status
Simulation time 17662295935 ps
CPU time 46.01 seconds
Started Nov 22 01:58:52 PM PST 23
Finished Nov 22 01:59:41 PM PST 23
Peak memory 203276 kb
Host smart-b8e3b947-cc90-497c-8fc1-37661339fd2d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=54216479164570301687942355075933785798197631199441102043048072955897457604404 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.54216479164570301687942355075933785798197631199441102043048072955897457604404
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.12846925027727538892511710828673659669416375823086726566086123543926610324674
Short name T515
Test name
Test status
Simulation time 116233435 ps
CPU time 2.41 seconds
Started Nov 22 01:58:41 PM PST 23
Finished Nov 22 01:58:45 PM PST 23
Peak memory 203020 kb
Host smart-574649c1-eca5-47d8-9324-4a1231bd1841
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12846925027727538892511710828673659669416375823086726566086123543926610324674 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.12846925027727538892511710828673659669416375823086726566086123543926610324674
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.105567955219683680904364614820142847676073252708823338068710039442789609498328
Short name T381
Test name
Test status
Simulation time 18904859184 ps
CPU time 128.39 seconds
Started Nov 22 01:58:52 PM PST 23
Finished Nov 22 02:01:03 PM PST 23
Peak memory 205812 kb
Host smart-91763163-203c-4b2a-ab0d-2a475fde967d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105567955219683680904364614820142847676073252708823338068710039442789609498328 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 40.xbar_stress_all.105567955219683680904364614820142847676073252708823338068710039442789609498328
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.39937102150277249319800541551134866814230609585915937462421771445194541865579
Short name T620
Test name
Test status
Simulation time 18894549184 ps
CPU time 121.67 seconds
Started Nov 22 01:58:43 PM PST 23
Finished Nov 22 02:00:48 PM PST 23
Peak memory 211444 kb
Host smart-266c627d-5ccb-4f4d-86fd-bf449b831d71
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=39937102150277249319800541551134866814230609585915937462421771445194541865579 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 40.xbar_stress_all_with_error.39937102150277249319800541551134866814230609585915937462421771445194541865579
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.14016704970067949703437354802781016596356120097872003180963168785738957645411
Short name T831
Test name
Test status
Simulation time 5188549184 ps
CPU time 291.66 seconds
Started Nov 22 01:58:53 PM PST 23
Finished Nov 22 02:03:48 PM PST 23
Peak memory 208408 kb
Host smart-69c9c252-db9d-4cd9-8a34-e4acedd9e003
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14016704970067949703437354802781016596356120097872003180963168785738957645411 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.14016704970067949703437354802781016596356120097872003180963168785738957645411
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.15006553099773542783776392057790424168989611408644788508322079408022863616547
Short name T136
Test name
Test status
Simulation time 5188549184 ps
CPU time 228.39 seconds
Started Nov 22 01:58:45 PM PST 23
Finished Nov 22 02:02:41 PM PST 23
Peak memory 219660 kb
Host smart-39d7cf57-6ae5-41af-8f6c-7ecfe1ae224f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15006553099773542783776392057790424168989611408644788508322079408022863616547 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.15006553099773542783776392057790424168989611408644788508322079408022863616547
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.2717488120377267323580491495667478288927331299555494675419305829050523743363
Short name T508
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.38 seconds
Started Nov 22 01:58:57 PM PST 23
Finished Nov 22 01:59:30 PM PST 23
Peak memory 211388 kb
Host smart-4e903b6b-56fc-4a8a-9ae7-2f3c7d791d4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2717488120377267323580491495667478288927331299555494675419305829050523743363 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2717488120377267323580491495667478288927331299555494675419305829050523743363
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.42514145974214578817519713938363738687824888481272694895408971433062068096261
Short name T449
Test name
Test status
Simulation time 7399045935 ps
CPU time 65.03 seconds
Started Nov 22 01:59:08 PM PST 23
Finished Nov 22 02:00:15 PM PST 23
Peak memory 206284 kb
Host smart-12c6e0b3-26c7-406d-826c-3155b710805c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=42514145974214578817519713938363738687824888481272694895408971433062068096261 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.42514145974214578817519713938363738687824888481272694895408971433062068096261
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.85269106861977754521127419060320953969423315365680884841665302366103592114908
Short name T489
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.95 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 01:59:38 PM PST 23
Peak memory 203200 kb
Host smart-bfc81ee2-e89f-401c-b6d0-a8bd6755ed88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85269106861977754521127419060320953969423315365680884841665302366103592114908 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.85269106861977754521127419060320953969423315365680884841665302366103592114908
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.111919273358165592824298768730812124048343623249065514648685926830387964378415
Short name T139
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.59 seconds
Started Nov 22 01:58:52 PM PST 23
Finished Nov 22 01:59:29 PM PST 23
Peak memory 203224 kb
Host smart-76383d2f-c3e6-41d6-9103-b31d9286e9bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111919273358165592824298768730812124048343623249065514648685926830387964378415 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_l
og /dev/null -cm_name 41.xbar_error_random.111919273358165592824298768730812124048343623249065514648685926830387964378415
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.62781195152011180443259279351412357638829416983415944932539237581625905136323
Short name T210
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.82 seconds
Started Nov 22 01:59:10 PM PST 23
Finished Nov 22 01:59:48 PM PST 23
Peak memory 211360 kb
Host smart-44b5ee07-a265-4f47-869b-93479ddde34f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62781195152011180443259279351412357638829416983415944932539237581625905136323 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 41.xbar_random.62781195152011180443259279351412357638829416983415944932539237581625905136323
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.39330407313594164895396104119335767016251983844352424402793315618831996653298
Short name T742
Test name
Test status
Simulation time 188793233435 ps
CPU time 325.93 seconds
Started Nov 22 01:58:51 PM PST 23
Finished Nov 22 02:04:21 PM PST 23
Peak memory 204800 kb
Host smart-8842c129-ee85-481c-87ae-f62c83db1cf2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=39330407313594164895396104119335767016251983844352424402793315618831996653298 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 41.xbar_random_large_delays.39330407313594164895396104119335767016251983844352424402793315618831996653298
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.37096162268483204313493305487774296014901411974175724508495050157581689034418
Short name T188
Test name
Test status
Simulation time 126189108435 ps
CPU time 334.01 seconds
Started Nov 22 01:59:10 PM PST 23
Finished Nov 22 02:04:45 PM PST 23
Peak memory 211540 kb
Host smart-821ed640-ee34-4d4b-8479-47b34f4c8042
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=37096162268483204313493305487774296014901411974175724508495050157581689034418 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.37096162268483204313493305487774296014901411974175724508495050157581689034418
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.61983114873724256750565319489659955326776652248133338969263472352285889749300
Short name T899
Test name
Test status
Simulation time 766920935 ps
CPU time 25.41 seconds
Started Nov 22 01:58:58 PM PST 23
Finished Nov 22 01:59:26 PM PST 23
Peak memory 203828 kb
Host smart-57ba739b-7263-47a9-9d3c-a5cac9652e7f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61983114873724256750565319489659955326776652248133338969263472352285889749300 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.61983114873724256750565319489659955326776652248133338969263472352285889749300
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.105141228981564900700582437638118554263205573891819690045609823036477450458359
Short name T185
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.19 seconds
Started Nov 22 01:58:48 PM PST 23
Finished Nov 22 01:59:32 PM PST 23
Peak memory 204308 kb
Host smart-8f60530a-c763-40b1-b3c3-8edcbc39278c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105141228981564900700582437638118554263205573891819690045609823036477450458359 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 41.xbar_same_source.105141228981564900700582437638118554263205573891819690045609823036477450458359
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.22614738518797336544437601676999711542451100461057048458347005994627931567487
Short name T107
Test name
Test status
Simulation time 669983435 ps
CPU time 4.17 seconds
Started Nov 22 01:58:45 PM PST 23
Finished Nov 22 01:58:57 PM PST 23
Peak memory 203120 kb
Host smart-54efd63e-d8d3-4482-b4af-37e6a4e324d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22614738518797336544437601676999711542451100461057048458347005994627931567487 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 41.xbar_smoke.22614738518797336544437601676999711542451100461057048458347005994627931567487
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.49853735073627280087973920315901635166088570117938851723161386480899914671723
Short name T263
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.56 seconds
Started Nov 22 01:59:08 PM PST 23
Finished Nov 22 01:59:56 PM PST 23
Peak memory 203276 kb
Host smart-f39db31c-5785-4ab7-97c7-a0be3c442bfa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=49853735073627280087973920315901635166088570117938851723161386480899914671723 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.49853735073627280087973920315901635166088570117938851723161386480899914671723
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.17217123606547668082416481393910654420320838103989518743795299668090144679854
Short name T691
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.73 seconds
Started Nov 22 01:59:08 PM PST 23
Finished Nov 22 01:59:54 PM PST 23
Peak memory 203252 kb
Host smart-fb572908-9fd4-43a2-a101-5a565908f8b7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=17217123606547668082416481393910654420320838103989518743795299668090144679854 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.17217123606547668082416481393910654420320838103989518743795299668090144679854
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.86247036289277379381714581743529353034498938785666147772545396551301219031617
Short name T179
Test name
Test status
Simulation time 116233435 ps
CPU time 2.66 seconds
Started Nov 22 01:59:08 PM PST 23
Finished Nov 22 01:59:11 PM PST 23
Peak memory 203144 kb
Host smart-5912f200-6104-42f5-b107-742f0652a373
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86247036289277379381714581743529353034498938785666147772545396551301219031617 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.86247036289277379381714581743529353034498938785666147772545396551301219031617
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.38591136280634380426481492983438460631036428042196077137492239932925629628318
Short name T815
Test name
Test status
Simulation time 18904859184 ps
CPU time 131.74 seconds
Started Nov 22 01:58:52 PM PST 23
Finished Nov 22 02:01:07 PM PST 23
Peak memory 205852 kb
Host smart-86514871-6066-46ee-95db-12656ea77d7a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=38591136280634380426481492983438460631036428042196077137492239932925629628318 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 41.xbar_stress_all.38591136280634380426481492983438460631036428042196077137492239932925629628318
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.15729711179009213986294362631658580367017729228640281738217881587037721699510
Short name T575
Test name
Test status
Simulation time 18894549184 ps
CPU time 122.22 seconds
Started Nov 22 01:58:44 PM PST 23
Finished Nov 22 02:00:49 PM PST 23
Peak memory 211472 kb
Host smart-7e315561-a93e-4373-9cc8-a09d6be5b352
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15729711179009213986294362631658580367017729228640281738217881587037721699510 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 41.xbar_stress_all_with_error.15729711179009213986294362631658580367017729228640281738217881587037721699510
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.6569949682171984797939794957722000584653636086913982301758803351620961875000
Short name T249
Test name
Test status
Simulation time 5188549184 ps
CPU time 301.86 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 02:04:12 PM PST 23
Peak memory 208440 kb
Host smart-2240e0cb-0e98-4c5c-8a16-24e7399266be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=6569949682171984797939794957722000584653636086913982301758803351620961875000 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.6569949682171984797939794957722000584653636086913982301758803351620961875000
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.68628328574835665044721308966154716943415589594672598182661850134662556950060
Short name T666
Test name
Test status
Simulation time 5188549184 ps
CPU time 218.15 seconds
Started Nov 22 01:58:58 PM PST 23
Finished Nov 22 02:02:39 PM PST 23
Peak memory 219604 kb
Host smart-3455321c-8116-4cd4-a524-44ae508fe73d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68628328574835665044721308966154716943415589594672598182661850134662556950060 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.68628328574835665044721308966154716943415589594672598182661850134662556950060
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.29077739171175228078987744021457985715028051063348976679170634457798242236959
Short name T315
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.75 seconds
Started Nov 22 01:58:49 PM PST 23
Finished Nov 22 01:59:24 PM PST 23
Peak memory 211328 kb
Host smart-3932f17d-579f-4a37-bec4-fdaad7193756
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29077739171175228078987744021457985715028051063348976679170634457798242236959 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 41.xbar_unmapped_addr.29077739171175228078987744021457985715028051063348976679170634457798242236959
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.29553867178706601837351299691273133189324659389342199610259414518007925229597
Short name T463
Test name
Test status
Simulation time 7399045935 ps
CPU time 63.77 seconds
Started Nov 22 01:58:52 PM PST 23
Finished Nov 22 01:59:59 PM PST 23
Peak memory 206352 kb
Host smart-7a1c242b-53db-45aa-b748-f9d4c4365041
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29553867178706601837351299691273133189324659389342199610259414518007925229597 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.29553867178706601837351299691273133189324659389342199610259414518007925229597
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.72232784250352097068911255352345192979969149054848773027053652603720192515423
Short name T661
Test name
Test status
Simulation time 304288045935 ps
CPU time 776.82 seconds
Started Nov 22 01:58:53 PM PST 23
Finished Nov 22 02:11:53 PM PST 23
Peak memory 211332 kb
Host smart-ef438d7a-bc28-44b9-ac7b-66daf977669d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=72232784250352097068911255352345192979969149054848773027053652603720192515423 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.72232784250352097068911255352345192979969149054848773027053652603720192515423
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.16061668260964491745948597128744805597268551080803201256186431870953489705064
Short name T82
Test name
Test status
Simulation time 3310545935 ps
CPU time 28.12 seconds
Started Nov 22 01:59:08 PM PST 23
Finished Nov 22 01:59:37 PM PST 23
Peak memory 203396 kb
Host smart-2e6f7eb5-1496-4aea-bbdf-b9568eaff5d4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16061668260964491745948597128744805597268551080803201256186431870953489705064 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.16061668260964491745948597128744805597268551080803201256186431870953489705064
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.27800827389103073985955194498491075576835024541074187460541997278303369311607
Short name T631
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.4 seconds
Started Nov 22 01:58:54 PM PST 23
Finished Nov 22 01:59:33 PM PST 23
Peak memory 203244 kb
Host smart-9ce023cc-b7f8-45be-bec4-eccb934a9f41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27800827389103073985955194498491075576835024541074187460541997278303369311607 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 42.xbar_error_random.27800827389103073985955194498491075576835024541074187460541997278303369311607
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.78153965116407794469084359191153396996039282944556614644828726143701809911744
Short name T748
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.82 seconds
Started Nov 22 01:58:48 PM PST 23
Finished Nov 22 01:59:33 PM PST 23
Peak memory 211424 kb
Host smart-74c82581-c95a-48c6-9f1e-e4ac9baa1245
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78153965116407794469084359191153396996039282944556614644828726143701809911744 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 42.xbar_random.78153965116407794469084359191153396996039282944556614644828726143701809911744
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.28059496844771258941439088647331526237983780532059604755128689311850179346530
Short name T562
Test name
Test status
Simulation time 188793233435 ps
CPU time 319.46 seconds
Started Nov 22 01:58:54 PM PST 23
Finished Nov 22 02:04:19 PM PST 23
Peak memory 204792 kb
Host smart-25e582da-fbc0-4bab-a718-952a93dee191
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=28059496844771258941439088647331526237983780532059604755128689311850179346530 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 42.xbar_random_large_delays.28059496844771258941439088647331526237983780532059604755128689311850179346530
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.46394912160966705187211672033994400476467579736920298555673206834610746116904
Short name T696
Test name
Test status
Simulation time 126189108435 ps
CPU time 322.76 seconds
Started Nov 22 01:58:44 PM PST 23
Finished Nov 22 02:04:10 PM PST 23
Peak memory 211476 kb
Host smart-04310ec2-6ceb-4f3e-a380-c3f3cd852b91
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=46394912160966705187211672033994400476467579736920298555673206834610746116904 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.46394912160966705187211672033994400476467579736920298555673206834610746116904
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.81589654028332042763480266701436140662253598945460637341330450765301734990266
Short name T280
Test name
Test status
Simulation time 766920935 ps
CPU time 25.35 seconds
Started Nov 22 01:58:47 PM PST 23
Finished Nov 22 01:59:19 PM PST 23
Peak memory 203688 kb
Host smart-c1c78be4-ece9-475c-80cd-c52d59943f73
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81589654028332042763480266701436140662253598945460637341330450765301734990266 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.81589654028332042763480266701436140662253598945460637341330450765301734990266
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.7613118661176632031761081779664812845382640343215028799199396318271267119092
Short name T832
Test name
Test status
Simulation time 7116170935 ps
CPU time 36.94 seconds
Started Nov 22 01:58:58 PM PST 23
Finished Nov 22 01:59:37 PM PST 23
Peak memory 204296 kb
Host smart-ea6be6bc-eeab-42a9-883c-94aa5d038528
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=7613118661176632031761081779664812845382640343215028799199396318271267119092 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 42.xbar_same_source.7613118661176632031761081779664812845382640343215028799199396318271267119092
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.81973766967141804552454847782561275248169538374757667400495240826377891193720
Short name T682
Test name
Test status
Simulation time 669983435 ps
CPU time 4.32 seconds
Started Nov 22 01:58:48 PM PST 23
Finished Nov 22 01:58:59 PM PST 23
Peak memory 203112 kb
Host smart-79a5775d-d061-4b93-a2c6-78230a42d198
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81973766967141804552454847782561275248169538374757667400495240826377891193720 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 42.xbar_smoke.81973766967141804552454847782561275248169538374757667400495240826377891193720
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.32881095032296290160663662102306974360657301457514818784040774418227227430109
Short name T134
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.26 seconds
Started Nov 22 01:58:49 PM PST 23
Finished Nov 22 01:59:42 PM PST 23
Peak memory 203128 kb
Host smart-39b7eed5-4b40-46ab-8f01-b854fc3c904c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=32881095032296290160663662102306974360657301457514818784040774418227227430109 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.32881095032296290160663662102306974360657301457514818784040774418227227430109
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.54130831247020487567366192179784242314313769868930666973954655631713491403110
Short name T204
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.24 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 01:59:55 PM PST 23
Peak memory 203276 kb
Host smart-c4969c92-408f-416e-88b8-3f77deafd379
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=54130831247020487567366192179784242314313769868930666973954655631713491403110 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.54130831247020487567366192179784242314313769868930666973954655631713491403110
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.52447396638257178775318650912216929831116209645481030814694798152482438351620
Short name T112
Test name
Test status
Simulation time 116233435 ps
CPU time 2.47 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 01:59:13 PM PST 23
Peak memory 203116 kb
Host smart-f5fc0f42-d9d7-47f5-993c-94e5ccf4e12d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52447396638257178775318650912216929831116209645481030814694798152482438351620 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.52447396638257178775318650912216929831116209645481030814694798152482438351620
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.88470196858563665464435631799711432072345157160827183722372863633233116615183
Short name T402
Test name
Test status
Simulation time 18904859184 ps
CPU time 127.66 seconds
Started Nov 22 01:59:07 PM PST 23
Finished Nov 22 02:01:16 PM PST 23
Peak memory 205700 kb
Host smart-4b4a0253-cf07-4183-9c5b-70abe27ee6eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88470196858563665464435631799711432072345157160827183722372863633233116615183 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 42.xbar_stress_all.88470196858563665464435631799711432072345157160827183722372863633233116615183
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.46116376698343822946010106901448197224732824199126420147190773709724924754201
Short name T71
Test name
Test status
Simulation time 18894549184 ps
CPU time 113.45 seconds
Started Nov 22 01:58:55 PM PST 23
Finished Nov 22 02:00:53 PM PST 23
Peak memory 211412 kb
Host smart-d0f6ed59-61ae-47f6-86ce-56c2f6647333
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46116376698343822946010106901448197224732824199126420147190773709724924754201 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 42.xbar_stress_all_with_error.46116376698343822946010106901448197224732824199126420147190773709724924754201
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.15266716488310997514617817265388185094188976229320059296220526277199963975458
Short name T781
Test name
Test status
Simulation time 5188549184 ps
CPU time 289.11 seconds
Started Nov 22 01:59:11 PM PST 23
Finished Nov 22 02:04:01 PM PST 23
Peak memory 208508 kb
Host smart-25102ebb-8868-4630-a83f-c3dd2a7228c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15266716488310997514617817265388185094188976229320059296220526277199963975458 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.15266716488310997514617817265388185094188976229320059296220526277199963975458
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.88166210607299285909185516515702187017582526613809470316294307708439154586466
Short name T780
Test name
Test status
Simulation time 5188549184 ps
CPU time 228.81 seconds
Started Nov 22 01:58:51 PM PST 23
Finished Nov 22 02:02:44 PM PST 23
Peak memory 219612 kb
Host smart-06e2d04e-75de-4f98-b69f-438057ec8712
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88166210607299285909185516515702187017582526613809470316294307708439154586466 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.88166210607299285909185516515702187017582526613809470316294307708439154586466
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.88102384899035934512098940687872427819061978135514471373025361625429574136874
Short name T619
Test name
Test status
Simulation time 3307045935 ps
CPU time 27.76 seconds
Started Nov 22 01:58:54 PM PST 23
Finished Nov 22 01:59:27 PM PST 23
Peak memory 211368 kb
Host smart-b0f3c400-eec4-46da-be58-f957d486ab6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88102384899035934512098940687872427819061978135514471373025361625429574136874 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 42.xbar_unmapped_addr.88102384899035934512098940687872427819061978135514471373025361625429574136874
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.18966743391290237629076906876043063473496459678192027381286036840811585839001
Short name T465
Test name
Test status
Simulation time 7399045935 ps
CPU time 66.7 seconds
Started Nov 22 01:59:12 PM PST 23
Finished Nov 22 02:00:20 PM PST 23
Peak memory 206308 kb
Host smart-acba5946-7d5d-4328-978e-32144ddca373
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18966743391290237629076906876043063473496459678192027381286036840811585839001 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.18966743391290237629076906876043063473496459678192027381286036840811585839001
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.12083453300488294394632538400338846287311688312201573371697275550085501171676
Short name T350
Test name
Test status
Simulation time 304288045935 ps
CPU time 777.9 seconds
Started Nov 22 01:59:26 PM PST 23
Finished Nov 22 02:12:25 PM PST 23
Peak memory 211508 kb
Host smart-94f1940d-a65b-4eb7-9d39-48ce74038381
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=12083453300488294394632538400338846287311688312201573371697275550085501171676 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.12083453300488294394632538400338846287311688312201573371697275550085501171676
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.82713622811814752610786296747217616369251755692887077574686684123582294180795
Short name T106
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.75 seconds
Started Nov 22 01:59:11 PM PST 23
Finished Nov 22 01:59:39 PM PST 23
Peak memory 203200 kb
Host smart-117f34ca-d9d2-4cc2-ac58-2b570bb1c1c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=82713622811814752610786296747217616369251755692887077574686684123582294180795 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.82713622811814752610786296747217616369251755692887077574686684123582294180795
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.60794635425804136941785627191631749969206909807272783699026576021615365471772
Short name T838
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.37 seconds
Started Nov 22 01:59:14 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 203276 kb
Host smart-0d17cc79-b654-4262-b5e6-4828a1263b4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=60794635425804136941785627191631749969206909807272783699026576021615365471772 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 43.xbar_error_random.60794635425804136941785627191631749969206909807272783699026576021615365471772
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.739490941654674767334846711469844473873887678893263086286363056111395265311
Short name T866
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.14 seconds
Started Nov 22 01:59:08 PM PST 23
Finished Nov 22 01:59:47 PM PST 23
Peak memory 211460 kb
Host smart-db811085-4aa7-47b0-91fb-5b9bdc359f40
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=739490941654674767334846711469844473873887678893263086286363056111395265311 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /
dev/null -cm_name 43.xbar_random.739490941654674767334846711469844473873887678893263086286363056111395265311
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.48872027083899754841138737241341415478128938883531606918444326645531744478499
Short name T478
Test name
Test status
Simulation time 188793233435 ps
CPU time 337.28 seconds
Started Nov 22 01:59:12 PM PST 23
Finished Nov 22 02:04:50 PM PST 23
Peak memory 204776 kb
Host smart-fa7f185b-6afe-41b5-9dd4-d4cc41558c2d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=48872027083899754841138737241341415478128938883531606918444326645531744478499 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 43.xbar_random_large_delays.48872027083899754841138737241341415478128938883531606918444326645531744478499
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.17071511469557510507185481367440721031378485454984886874609345725823612348111
Short name T23
Test name
Test status
Simulation time 126189108435 ps
CPU time 328.26 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 02:04:39 PM PST 23
Peak memory 211396 kb
Host smart-f24522ac-2073-4d8b-a510-57cdb09ee0d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=17071511469557510507185481367440721031378485454984886874609345725823612348111 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.17071511469557510507185481367440721031378485454984886874609345725823612348111
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.69702734404942180534564128806907418148800149682072862677821149409706957119307
Short name T656
Test name
Test status
Simulation time 766920935 ps
CPU time 24.44 seconds
Started Nov 22 01:59:08 PM PST 23
Finished Nov 22 01:59:34 PM PST 23
Peak memory 203756 kb
Host smart-d932ee65-97ef-4147-b94c-551c7896ae50
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69702734404942180534564128806907418148800149682072862677821149409706957119307 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.69702734404942180534564128806907418148800149682072862677821149409706957119307
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.64600347092997252528344369522688910510790133169797292964499741253431615432885
Short name T616
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.67 seconds
Started Nov 22 01:59:25 PM PST 23
Finished Nov 22 02:00:05 PM PST 23
Peak memory 204296 kb
Host smart-5de45380-7627-47d0-9ffa-d2cb0fee45f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64600347092997252528344369522688910510790133169797292964499741253431615432885 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 43.xbar_same_source.64600347092997252528344369522688910510790133169797292964499741253431615432885
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.44461963971334626322415728424972070052068152599246849697053166875873229580531
Short name T828
Test name
Test status
Simulation time 669983435 ps
CPU time 4.09 seconds
Started Nov 22 01:58:50 PM PST 23
Finished Nov 22 01:58:59 PM PST 23
Peak memory 203188 kb
Host smart-4ea83738-631c-4001-8dfd-d4140b687aed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44461963971334626322415728424972070052068152599246849697053166875873229580531 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 43.xbar_smoke.44461963971334626322415728424972070052068152599246849697053166875873229580531
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.102600070833347950987269011911510341994960887100316496895295849556864341347848
Short name T820
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.07 seconds
Started Nov 22 01:58:55 PM PST 23
Finished Nov 22 01:59:48 PM PST 23
Peak memory 203240 kb
Host smart-ab4df550-94aa-4f07-876f-065edc37b3fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=102600070833347950987269011911510341994960887100316496895295849556864341347848 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.102600070833347950987269011911510341994960887100316496895295849556864341347848
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.75866202080297091997519652619340460236957113169578407111208584337087258985871
Short name T99
Test name
Test status
Simulation time 17662295935 ps
CPU time 43.97 seconds
Started Nov 22 01:58:54 PM PST 23
Finished Nov 22 01:59:44 PM PST 23
Peak memory 203248 kb
Host smart-2e55df8b-0837-4eff-b217-21431ca810b5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=75866202080297091997519652619340460236957113169578407111208584337087258985871 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.75866202080297091997519652619340460236957113169578407111208584337087258985871
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.90375645019883864888361484467376964480739603073411314419171877986699825898159
Short name T215
Test name
Test status
Simulation time 116233435 ps
CPU time 2.6 seconds
Started Nov 22 01:59:10 PM PST 23
Finished Nov 22 01:59:14 PM PST 23
Peak memory 203024 kb
Host smart-88a82dc3-a53e-4dcb-81f6-f41ded425e77
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90375645019883864888361484467376964480739603073411314419171877986699825898159 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.90375645019883864888361484467376964480739603073411314419171877986699825898159
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.107738716197982669011786859944852400857190263694268375511546570983147066136406
Short name T361
Test name
Test status
Simulation time 18904859184 ps
CPU time 128.31 seconds
Started Nov 22 01:59:10 PM PST 23
Finished Nov 22 02:01:20 PM PST 23
Peak memory 205792 kb
Host smart-b776c608-9ad6-4f49-9db5-8e4793256b1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=107738716197982669011786859944852400857190263694268375511546570983147066136406 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 43.xbar_stress_all.107738716197982669011786859944852400857190263694268375511546570983147066136406
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.81803938234014548108101455137629366631318259728985180152104665449970356742807
Short name T685
Test name
Test status
Simulation time 18894549184 ps
CPU time 118.07 seconds
Started Nov 22 01:59:12 PM PST 23
Finished Nov 22 02:01:11 PM PST 23
Peak memory 211524 kb
Host smart-85cff3a9-164a-46c5-accb-8f1c4e54f0b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=81803938234014548108101455137629366631318259728985180152104665449970356742807 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 43.xbar_stress_all_with_error.81803938234014548108101455137629366631318259728985180152104665449970356742807
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.40652448709425048253534606778132830100928480021873435261436765675029224703274
Short name T241
Test name
Test status
Simulation time 5188549184 ps
CPU time 290.89 seconds
Started Nov 22 01:59:10 PM PST 23
Finished Nov 22 02:04:02 PM PST 23
Peak memory 208508 kb
Host smart-952d007b-346d-4794-99ed-bbf920e64f7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40652448709425048253534606778132830100928480021873435261436765675029224703274 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.40652448709425048253534606778132830100928480021873435261436765675029224703274
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.18761619576607647374948151197214533066689265773068812700879249621958917917766
Short name T145
Test name
Test status
Simulation time 5188549184 ps
CPU time 232.42 seconds
Started Nov 22 01:59:10 PM PST 23
Finished Nov 22 02:03:04 PM PST 23
Peak memory 219548 kb
Host smart-b7425c9f-7369-4f77-9090-b123ba246ec3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18761619576607647374948151197214533066689265773068812700879249621958917917766 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.18761619576607647374948151197214533066689265773068812700879249621958917917766
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.49075936114139165530847949122258778015538423017548609938103476946854739331340
Short name T583
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.42 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 01:59:40 PM PST 23
Peak memory 211344 kb
Host smart-044306d6-6445-46ea-8a6d-275e3dd81594
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49075936114139165530847949122258778015538423017548609938103476946854739331340 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 43.xbar_unmapped_addr.49075936114139165530847949122258778015538423017548609938103476946854739331340
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.112008702188106624583440685540959143458634077507825993664576994287210569788887
Short name T53
Test name
Test status
Simulation time 7399045935 ps
CPU time 63.55 seconds
Started Nov 22 01:59:13 PM PST 23
Finished Nov 22 02:00:18 PM PST 23
Peak memory 206340 kb
Host smart-0a49a036-5935-42e3-8a92-262f371067c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=112008702188106624583440685540959143458634077507825993664576994287210569788887 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.112008702188106624583440685540959143458634077507825993664576994287210569788887
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.92165301306010081083483109969027135024458739697178482038001849629811100910329
Short name T348
Test name
Test status
Simulation time 304288045935 ps
CPU time 775.28 seconds
Started Nov 22 01:59:12 PM PST 23
Finished Nov 22 02:12:08 PM PST 23
Peak memory 211420 kb
Host smart-cf16d2a0-dbd8-467a-b77d-fb2178329fe0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=92165301306010081083483109969027135024458739697178482038001849629811100910329 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.92165301306010081083483109969027135024458739697178482038001849629811100910329
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.37016085263902826185455786617084744618395543954734277036890407559944362990590
Short name T761
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.71 seconds
Started Nov 22 01:59:28 PM PST 23
Finished Nov 22 01:59:55 PM PST 23
Peak memory 203320 kb
Host smart-2d1951ff-9524-4c6b-a425-8826df6a234e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=37016085263902826185455786617084744618395543954734277036890407559944362990590 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.37016085263902826185455786617084744618395543954734277036890407559944362990590
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.25160245629937993185546843717253928631522514362894720183127456851255931121543
Short name T278
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.66 seconds
Started Nov 22 01:59:08 PM PST 23
Finished Nov 22 01:59:45 PM PST 23
Peak memory 203248 kb
Host smart-1421622d-9553-4e96-a9f9-97741b3c4dd1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25160245629937993185546843717253928631522514362894720183127456851255931121543 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 44.xbar_error_random.25160245629937993185546843717253928631522514362894720183127456851255931121543
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.37374316069630302393878942545537313467523863504185710727197240631778678039075
Short name T576
Test name
Test status
Simulation time 4402420935 ps
CPU time 40.41 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 211452 kb
Host smart-ff1354bb-15d5-4f6a-b154-cc6b0cd842f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=37374316069630302393878942545537313467523863504185710727197240631778678039075 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 44.xbar_random.37374316069630302393878942545537313467523863504185710727197240631778678039075
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.53404342710124162108954825292610834679212794512682720692326853463428907582602
Short name T797
Test name
Test status
Simulation time 188793233435 ps
CPU time 322.56 seconds
Started Nov 22 01:58:56 PM PST 23
Finished Nov 22 02:04:22 PM PST 23
Peak memory 204772 kb
Host smart-7614fa05-9d70-41e7-8b5a-dcc52729a0b7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=53404342710124162108954825292610834679212794512682720692326853463428907582602 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 44.xbar_random_large_delays.53404342710124162108954825292610834679212794512682720692326853463428907582602
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.68819099808044091506436144450949384496883894209550506548725340983285619122339
Short name T468
Test name
Test status
Simulation time 126189108435 ps
CPU time 328.48 seconds
Started Nov 22 01:59:08 PM PST 23
Finished Nov 22 02:04:38 PM PST 23
Peak memory 211476 kb
Host smart-6356d046-7974-4f5f-a5b5-c656cc9a09c1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=68819099808044091506436144450949384496883894209550506548725340983285619122339 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.68819099808044091506436144450949384496883894209550506548725340983285619122339
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.25149229445114740125784546803075040429138764723389969684318979879678131896523
Short name T561
Test name
Test status
Simulation time 766920935 ps
CPU time 25.84 seconds
Started Nov 22 01:59:12 PM PST 23
Finished Nov 22 01:59:39 PM PST 23
Peak memory 203848 kb
Host smart-3ec11c37-2977-46fc-b604-03f828fe3eac
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25149229445114740125784546803075040429138764723389969684318979879678131896523 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.25149229445114740125784546803075040429138764723389969684318979879678131896523
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.29493632326655323930980438780420371099432100380790513624331673718136699585171
Short name T330
Test name
Test status
Simulation time 7116170935 ps
CPU time 34.63 seconds
Started Nov 22 01:59:17 PM PST 23
Finished Nov 22 01:59:52 PM PST 23
Peak memory 204376 kb
Host smart-d4e1bf1f-76fa-4962-a329-7c89a5c2247f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29493632326655323930980438780420371099432100380790513624331673718136699585171 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 44.xbar_same_source.29493632326655323930980438780420371099432100380790513624331673718136699585171
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.43121491066361304397593513066967538529786931595531313774511654140992485545309
Short name T110
Test name
Test status
Simulation time 669983435 ps
CPU time 4.1 seconds
Started Nov 22 01:58:57 PM PST 23
Finished Nov 22 01:59:04 PM PST 23
Peak memory 203040 kb
Host smart-13d9b522-333b-4474-81a1-f7e38108d118
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=43121491066361304397593513066967538529786931595531313774511654140992485545309 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 44.xbar_smoke.43121491066361304397593513066967538529786931595531313774511654140992485545309
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.102272214088991772473481662110646317441721754546990887746891094330788704261988
Short name T236
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.24 seconds
Started Nov 22 01:59:10 PM PST 23
Finished Nov 22 02:00:00 PM PST 23
Peak memory 203280 kb
Host smart-0c6c21e4-db0a-4caa-b7f6-a16538a1f54b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=102272214088991772473481662110646317441721754546990887746891094330788704261988 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.102272214088991772473481662110646317441721754546990887746891094330788704261988
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.96885804664765019962394591536840129153866429570581459715120912403293047862253
Short name T93
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.36 seconds
Started Nov 22 01:59:27 PM PST 23
Finished Nov 22 02:00:12 PM PST 23
Peak memory 203232 kb
Host smart-cf4bc748-0d29-4a1e-8a66-21f8e0de0766
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=96885804664765019962394591536840129153866429570581459715120912403293047862253 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.96885804664765019962394591536840129153866429570581459715120912403293047862253
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.4484489712494645370777134697745763350046282050567534244024436031983957280501
Short name T777
Test name
Test status
Simulation time 116233435 ps
CPU time 2.68 seconds
Started Nov 22 01:59:11 PM PST 23
Finished Nov 22 01:59:15 PM PST 23
Peak memory 203056 kb
Host smart-ac90e773-a29d-478b-9624-2a934615617b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4484489712494645370777134697745763350046282050567534244024436031983957280501 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.4484489712494645370777134697745763350046282050567534244024436031983957280501
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.38432323961762559874760549487672021588697592944769100282731482250594013392052
Short name T222
Test name
Test status
Simulation time 18894549184 ps
CPU time 130.57 seconds
Started Nov 22 01:59:14 PM PST 23
Finished Nov 22 02:01:26 PM PST 23
Peak memory 211420 kb
Host smart-4dd3f871-4ec8-43ca-aa79-d7eec3034656
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=38432323961762559874760549487672021588697592944769100282731482250594013392052 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 44.xbar_stress_all_with_error.38432323961762559874760549487672021588697592944769100282731482250594013392052
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.83644630036828641672172229539928078343189245847210876256193078312623321985430
Short name T861
Test name
Test status
Simulation time 5188549184 ps
CPU time 302.9 seconds
Started Nov 22 01:59:25 PM PST 23
Finished Nov 22 02:04:29 PM PST 23
Peak memory 208508 kb
Host smart-485c9b58-0f00-4b18-b1f3-548fb5a97ed5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83644630036828641672172229539928078343189245847210876256193078312623321985430 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.83644630036828641672172229539928078343189245847210876256193078312623321985430
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.57795305007841566871949203054898101845611816311177477450262794424133840749196
Short name T759
Test name
Test status
Simulation time 5188549184 ps
CPU time 227.78 seconds
Started Nov 22 01:59:29 PM PST 23
Finished Nov 22 02:03:18 PM PST 23
Peak memory 219572 kb
Host smart-1c46d53e-0b3f-44bb-a309-5a02cfe89b04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57795305007841566871949203054898101845611816311177477450262794424133840749196 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.57795305007841566871949203054898101845611816311177477450262794424133840749196
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.78633589497079924499894836392653610380937919577182262607812898776284736038787
Short name T85
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.88 seconds
Started Nov 22 01:59:11 PM PST 23
Finished Nov 22 01:59:42 PM PST 23
Peak memory 211396 kb
Host smart-774667d2-0411-48b9-b8c9-6d90297b1f6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78633589497079924499894836392653610380937919577182262607812898776284736038787 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 44.xbar_unmapped_addr.78633589497079924499894836392653610380937919577182262607812898776284736038787
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.46343984752019750320662579992446223499814603717388237870871827209877176349066
Short name T601
Test name
Test status
Simulation time 7399045935 ps
CPU time 64.67 seconds
Started Nov 22 01:59:12 PM PST 23
Finished Nov 22 02:00:18 PM PST 23
Peak memory 206144 kb
Host smart-5faa79c1-b984-44b4-8892-d79faf3a54ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46343984752019750320662579992446223499814603717388237870871827209877176349066 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.46343984752019750320662579992446223499814603717388237870871827209877176349066
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.82825288395444168786841807422182362745131584812280858703259131211915972485125
Short name T184
Test name
Test status
Simulation time 304288045935 ps
CPU time 771.88 seconds
Started Nov 22 01:59:13 PM PST 23
Finished Nov 22 02:12:06 PM PST 23
Peak memory 211244 kb
Host smart-0beb79c2-5ac8-434d-9f9f-cf3632bdf184
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=82825288395444168786841807422182362745131584812280858703259131211915972485125 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.82825288395444168786841807422182362745131584812280858703259131211915972485125
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.83960374166221800137875704425788212886198042258523382442711121931190791017929
Short name T101
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.95 seconds
Started Nov 22 01:59:11 PM PST 23
Finished Nov 22 01:59:39 PM PST 23
Peak memory 203312 kb
Host smart-fc6f0490-f3bc-43cc-8fc9-254bd88fb150
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83960374166221800137875704425788212886198042258523382442711121931190791017929 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.83960374166221800137875704425788212886198042258523382442711121931190791017929
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.55916700629332025195898833123924956428558310285337518674541675257017518275489
Short name T746
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.2 seconds
Started Nov 22 01:59:14 PM PST 23
Finished Nov 22 01:59:51 PM PST 23
Peak memory 203276 kb
Host smart-39009de3-a2b9-41b4-aab4-06584fd06772
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55916700629332025195898833123924956428558310285337518674541675257017518275489 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 45.xbar_error_random.55916700629332025195898833123924956428558310285337518674541675257017518275489
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.5988273312660642733439048110447372364741396952716157067729797696720410364790
Short name T247
Test name
Test status
Simulation time 4402420935 ps
CPU time 39.09 seconds
Started Nov 22 01:59:24 PM PST 23
Finished Nov 22 02:00:04 PM PST 23
Peak memory 211420 kb
Host smart-f6de4936-4dcc-42ac-859e-83d4ea304230
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5988273312660642733439048110447372364741396952716157067729797696720410364790 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 45.xbar_random.5988273312660642733439048110447372364741396952716157067729797696720410364790
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.65284889576323709794229213409696974755652660932560974034320123551571278569995
Short name T825
Test name
Test status
Simulation time 188793233435 ps
CPU time 329.85 seconds
Started Nov 22 01:59:25 PM PST 23
Finished Nov 22 02:04:56 PM PST 23
Peak memory 204800 kb
Host smart-25fe46ac-a6c6-4cd8-b2a4-9c8399563024
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=65284889576323709794229213409696974755652660932560974034320123551571278569995 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 45.xbar_random_large_delays.65284889576323709794229213409696974755652660932560974034320123551571278569995
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.22377669303199530458109714862459311269413466108931963938261495825706655455433
Short name T741
Test name
Test status
Simulation time 126189108435 ps
CPU time 323.95 seconds
Started Nov 22 01:59:11 PM PST 23
Finished Nov 22 02:04:36 PM PST 23
Peak memory 211452 kb
Host smart-0552747f-346d-4ef5-998c-04c7b9c049d7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=22377669303199530458109714862459311269413466108931963938261495825706655455433 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.22377669303199530458109714862459311269413466108931963938261495825706655455433
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.64721544018516720041298083676962388243752259731729914267170788965116612724706
Short name T267
Test name
Test status
Simulation time 766920935 ps
CPU time 28.04 seconds
Started Nov 22 01:59:11 PM PST 23
Finished Nov 22 01:59:41 PM PST 23
Peak memory 203852 kb
Host smart-25edfa65-ae95-4450-8f88-b2e59c5dd8f3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64721544018516720041298083676962388243752259731729914267170788965116612724706 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.64721544018516720041298083676962388243752259731729914267170788965116612724706
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.98402505306554549701847354496483223626655926130555989040811311400447788982605
Short name T74
Test name
Test status
Simulation time 7116170935 ps
CPU time 39.54 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 01:59:50 PM PST 23
Peak memory 204320 kb
Host smart-ff69df18-b1f8-435a-a3c9-6b9778c363ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=98402505306554549701847354496483223626655926130555989040811311400447788982605 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 45.xbar_same_source.98402505306554549701847354496483223626655926130555989040811311400447788982605
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.20321655488540448250385516547885920765744013666691262658366326086109184715844
Short name T115
Test name
Test status
Simulation time 669983435 ps
CPU time 4.12 seconds
Started Nov 22 01:59:24 PM PST 23
Finished Nov 22 01:59:29 PM PST 23
Peak memory 203176 kb
Host smart-87f788e5-bf22-4090-b89b-68bb59c68432
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20321655488540448250385516547885920765744013666691262658366326086109184715844 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 45.xbar_smoke.20321655488540448250385516547885920765744013666691262658366326086109184715844
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.16996749486935253972278689687105330673965032781014578047697052323138193393818
Short name T524
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.74 seconds
Started Nov 22 01:59:25 PM PST 23
Finished Nov 22 02:00:15 PM PST 23
Peak memory 203164 kb
Host smart-f2717ab7-a01b-4826-a039-777f15386dc1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=16996749486935253972278689687105330673965032781014578047697052323138193393818 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.16996749486935253972278689687105330673965032781014578047697052323138193393818
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.8322348117548744294044017512040403463904920338419872651811303813850944752559
Short name T100
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.89 seconds
Started Nov 22 01:59:28 PM PST 23
Finished Nov 22 02:00:14 PM PST 23
Peak memory 203276 kb
Host smart-d6cf116c-d3bf-4fac-8bd7-5c0dd88d1ae6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=8322348117548744294044017512040403463904920338419872651811303813850944752559 -assert nopostproc +UVM_TESTN
AME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.8322348117548744294044017512040403463904920338419872651811303813850944752559
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.70292353038719412302986727847924943648001542342249636427757426874005373267589
Short name T109
Test name
Test status
Simulation time 116233435 ps
CPU time 2.42 seconds
Started Nov 22 01:59:12 PM PST 23
Finished Nov 22 01:59:16 PM PST 23
Peak memory 203112 kb
Host smart-f70d4332-b55b-4e81-bb39-c551e3e3de49
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70292353038719412302986727847924943648001542342249636427757426874005373267589 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.70292353038719412302986727847924943648001542342249636427757426874005373267589
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.43284111459278069574383448020520493977045782937041876546286771518690499253343
Short name T697
Test name
Test status
Simulation time 18904859184 ps
CPU time 141.73 seconds
Started Nov 22 01:59:12 PM PST 23
Finished Nov 22 02:01:35 PM PST 23
Peak memory 205800 kb
Host smart-c5f60263-c8c3-4a4b-bf5d-af84ef729ae2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=43284111459278069574383448020520493977045782937041876546286771518690499253343 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 45.xbar_stress_all.43284111459278069574383448020520493977045782937041876546286771518690499253343
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.111595043917262870332978923381615182900038873086325471308457885862561473243915
Short name T623
Test name
Test status
Simulation time 18894549184 ps
CPU time 118.35 seconds
Started Nov 22 01:59:08 PM PST 23
Finished Nov 22 02:01:07 PM PST 23
Peak memory 211432 kb
Host smart-3d894ee9-7525-4052-9bb0-1eb5b5bf4ed8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111595043917262870332978923381615182900038873086325471308457885862561473243915 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.111595043917262870332978923381615182900038873086325471308457885862561473243915
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.87799849281780788981639538063665037641585231113994885481845671128709315398653
Short name T737
Test name
Test status
Simulation time 5188549184 ps
CPU time 296.38 seconds
Started Nov 22 01:59:11 PM PST 23
Finished Nov 22 02:04:09 PM PST 23
Peak memory 208444 kb
Host smart-b9f4e3c1-7957-4e0d-a5a9-280f68fef31b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87799849281780788981639538063665037641585231113994885481845671128709315398653 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.87799849281780788981639538063665037641585231113994885481845671128709315398653
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.105697952934206977580523581076536400617957224411687711599161662107255515158918
Short name T658
Test name
Test status
Simulation time 5188549184 ps
CPU time 223.29 seconds
Started Nov 22 01:59:10 PM PST 23
Finished Nov 22 02:02:54 PM PST 23
Peak memory 219616 kb
Host smart-92057d84-e2a5-4e89-88b1-714a2dc23270
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105697952934206977580523581076536400617957224411687711599161662107255515158918 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_
build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.105697952934206977580523581076536400617957224411687711599161662107255515158918
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.9677155116446948156617911572584071800204403826130066856084474678640862481465
Short name T228
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.91 seconds
Started Nov 22 01:59:11 PM PST 23
Finished Nov 22 01:59:41 PM PST 23
Peak memory 211396 kb
Host smart-b0e13349-3353-4e54-adaa-bbee25cddf7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=9677155116446948156617911572584071800204403826130066856084474678640862481465 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 45.xbar_unmapped_addr.9677155116446948156617911572584071800204403826130066856084474678640862481465
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.84395126601819730625170505597985831036106009215523319431523338471848876827318
Short name T374
Test name
Test status
Simulation time 7399045935 ps
CPU time 61.23 seconds
Started Nov 22 01:59:33 PM PST 23
Finished Nov 22 02:00:35 PM PST 23
Peak memory 206408 kb
Host smart-9a837dcf-8499-4f9d-acfa-6c64ef73e614
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=84395126601819730625170505597985831036106009215523319431523338471848876827318 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.84395126601819730625170505597985831036106009215523319431523338471848876827318
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.89770793823816094198056941982959525364915668612498000264219761113328409166192
Short name T708
Test name
Test status
Simulation time 304288045935 ps
CPU time 776.39 seconds
Started Nov 22 01:59:26 PM PST 23
Finished Nov 22 02:12:24 PM PST 23
Peak memory 211400 kb
Host smart-f64eec21-157e-4d86-8c1a-84cd7018e648
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=89770793823816094198056941982959525364915668612498000264219761113328409166192 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.89770793823816094198056941982959525364915668612498000264219761113328409166192
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.8540973565686040203824026042613996353776022723648841603075503088122005792134
Short name T403
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.21 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 01:59:59 PM PST 23
Peak memory 203348 kb
Host smart-4c69ae26-6af6-4c83-8fb8-4fa79797eb34
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8540973565686040203824026042613996353776022723648841603075503088122005792134 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.8540973565686040203824026042613996353776022723648841603075503088122005792134
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.70016948829019114473737480738359356604251503425263417136474810469687724286002
Short name T429
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.07 seconds
Started Nov 22 01:59:27 PM PST 23
Finished Nov 22 02:00:04 PM PST 23
Peak memory 203268 kb
Host smart-ee0d2d7d-8e4e-47fa-812f-f50ca8bb54b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70016948829019114473737480738359356604251503425263417136474810469687724286002 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 46.xbar_error_random.70016948829019114473737480738359356604251503425263417136474810469687724286002
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.95265102162302015042212760733075379663594787639945357293586017806637681677494
Short name T717
Test name
Test status
Simulation time 4402420935 ps
CPU time 40.51 seconds
Started Nov 22 01:59:26 PM PST 23
Finished Nov 22 02:00:07 PM PST 23
Peak memory 211456 kb
Host smart-193248e3-d8b8-4863-aa58-ccd6591bd3dd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=95265102162302015042212760733075379663594787639945357293586017806637681677494 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 46.xbar_random.95265102162302015042212760733075379663594787639945357293586017806637681677494
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.9583573318610268772212960779235085522639777824064808570312204809013429212835
Short name T400
Test name
Test status
Simulation time 188793233435 ps
CPU time 322.44 seconds
Started Nov 22 01:59:31 PM PST 23
Finished Nov 22 02:04:54 PM PST 23
Peak memory 204832 kb
Host smart-718b6bc5-566a-4cb3-ad4d-f7fa7734b9fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=9583573318610268772212960779235085522639777824064808570312204809013429212835 -assert nopostproc +UVM_T
ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 46.xbar_random_large_delays.9583573318610268772212960779235085522639777824064808570312204809013429212835
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.12109587629565220235471805193279771851813513824548971120226626799424316074663
Short name T671
Test name
Test status
Simulation time 126189108435 ps
CPU time 331 seconds
Started Nov 22 01:59:29 PM PST 23
Finished Nov 22 02:05:01 PM PST 23
Peak memory 211396 kb
Host smart-b7697986-d6e2-4009-8cee-ba3bf060e8d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=12109587629565220235471805193279771851813513824548971120226626799424316074663 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.12109587629565220235471805193279771851813513824548971120226626799424316074663
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.99008015253309273949817096315042157071031326046395395038866091934972486545624
Short name T405
Test name
Test status
Simulation time 766920935 ps
CPU time 26.02 seconds
Started Nov 22 01:59:27 PM PST 23
Finished Nov 22 01:59:54 PM PST 23
Peak memory 203808 kb
Host smart-d8ce6f0e-4674-4930-b11e-1815b3ac8ed8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99008015253309273949817096315042157071031326046395395038866091934972486545624 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.99008015253309273949817096315042157071031326046395395038866091934972486545624
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.12314572933242195680118306921065086084514988399697852874731460003880423325745
Short name T125
Test name
Test status
Simulation time 7116170935 ps
CPU time 36.04 seconds
Started Nov 22 01:59:29 PM PST 23
Finished Nov 22 02:00:06 PM PST 23
Peak memory 204296 kb
Host smart-1437d91a-4546-4582-aad6-8401a2a31f38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12314572933242195680118306921065086084514988399697852874731460003880423325745 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 46.xbar_same_source.12314572933242195680118306921065086084514988399697852874731460003880423325745
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.78568543275948345520040927859459494054257964331626311888260999732078189302206
Short name T219
Test name
Test status
Simulation time 669983435 ps
CPU time 4.33 seconds
Started Nov 22 01:59:09 PM PST 23
Finished Nov 22 01:59:14 PM PST 23
Peak memory 203192 kb
Host smart-66785655-aa6e-4573-afae-428efdf39b6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78568543275948345520040927859459494054257964331626311888260999732078189302206 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 46.xbar_smoke.78568543275948345520040927859459494054257964331626311888260999732078189302206
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.80838674473252137862680043017173151294082922101622932919788353172505235321212
Short name T818
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.61 seconds
Started Nov 22 01:59:14 PM PST 23
Finished Nov 22 02:00:02 PM PST 23
Peak memory 203276 kb
Host smart-9badc557-db5b-4b15-a198-3eb272f8b885
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=80838674473252137862680043017173151294082922101622932919788353172505235321212 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.80838674473252137862680043017173151294082922101622932919788353172505235321212
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.55693629913546147553304879052752782475199824551352420387511271276281124236432
Short name T464
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.09 seconds
Started Nov 22 01:59:26 PM PST 23
Finished Nov 22 02:00:11 PM PST 23
Peak memory 203092 kb
Host smart-adf980bb-85ba-4f55-b03c-bdd7bfdd9931
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=55693629913546147553304879052752782475199824551352420387511271276281124236432 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.55693629913546147553304879052752782475199824551352420387511271276281124236432
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.35729776374274383134955878234694428100575092089189383330194009639104148265766
Short name T169
Test name
Test status
Simulation time 116233435 ps
CPU time 2.47 seconds
Started Nov 22 01:59:25 PM PST 23
Finished Nov 22 01:59:29 PM PST 23
Peak memory 202976 kb
Host smart-f3774a2a-638d-46e2-9590-d9483ef8964f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35729776374274383134955878234694428100575092089189383330194009639104148265766 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.35729776374274383134955878234694428100575092089189383330194009639104148265766
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.99933848833976647564776536358742262174175984355417148268011221885647435845163
Short name T337
Test name
Test status
Simulation time 18904859184 ps
CPU time 124.61 seconds
Started Nov 22 01:59:24 PM PST 23
Finished Nov 22 02:01:30 PM PST 23
Peak memory 205796 kb
Host smart-57bdc1ae-8199-4186-811d-964a34a6962d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99933848833976647564776536358742262174175984355417148268011221885647435845163 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 46.xbar_stress_all.99933848833976647564776536358742262174175984355417148268011221885647435845163
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.115772116578973845507515945985499423531916184787199523892874103338242277297229
Short name T15
Test name
Test status
Simulation time 18894549184 ps
CPU time 124.33 seconds
Started Nov 22 01:59:25 PM PST 23
Finished Nov 22 02:01:30 PM PST 23
Peak memory 211424 kb
Host smart-dc7d91f6-ad30-44e5-9d96-470c596ff23f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115772116578973845507515945985499423531916184787199523892874103338242277297229 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.115772116578973845507515945985499423531916184787199523892874103338242277297229
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.87268709572054278480847109009805193856920618972592027072214083252857948142615
Short name T778
Test name
Test status
Simulation time 5188549184 ps
CPU time 293.38 seconds
Started Nov 22 01:59:26 PM PST 23
Finished Nov 22 02:04:20 PM PST 23
Peak memory 208508 kb
Host smart-699f0e78-e43e-416a-bc6f-a03bd480e139
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87268709572054278480847109009805193856920618972592027072214083252857948142615 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.87268709572054278480847109009805193856920618972592027072214083252857948142615
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.122291266504956157532251244205161620516118781752404915182612601637620079019
Short name T14
Test name
Test status
Simulation time 5188549184 ps
CPU time 229.11 seconds
Started Nov 22 01:59:29 PM PST 23
Finished Nov 22 02:03:19 PM PST 23
Peak memory 219588 kb
Host smart-c76664a3-2226-4457-8b98-9ca070ec8f2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=122291266504956157532251244205161620516118781752404915182612601637620079019 -assert nopostproc +UVM_TESTNAME=xba
r_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.122291266504956157532251244205161620516118781752404915182612601637620079019
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.41502406988816708394501259289420024349995105935267963677052409754603363982544
Short name T670
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.16 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 02:00:02 PM PST 23
Peak memory 211420 kb
Host smart-38c77cac-4447-4f2b-867a-f5afcd3c4f59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41502406988816708394501259289420024349995105935267963677052409754603363982544 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 46.xbar_unmapped_addr.41502406988816708394501259289420024349995105935267963677052409754603363982544
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.94774520961057306706626831880496585896480412152579224295332044291283197606324
Short name T868
Test name
Test status
Simulation time 7399045935 ps
CPU time 71.18 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 02:00:45 PM PST 23
Peak memory 206264 kb
Host smart-80a0e5dd-4c44-41cb-9a20-9b3c8e749ece
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=94774520961057306706626831880496585896480412152579224295332044291283197606324 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.94774520961057306706626831880496585896480412152579224295332044291283197606324
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.53474278304739196356309190161412380173157229974445196622836846025463018303437
Short name T63
Test name
Test status
Simulation time 304288045935 ps
CPU time 792.53 seconds
Started Nov 22 01:59:24 PM PST 23
Finished Nov 22 02:12:38 PM PST 23
Peak memory 211444 kb
Host smart-e0f28741-607c-4f9e-ae82-766cd943d1fb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=53474278304739196356309190161412380173157229974445196622836846025463018303437 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.53474278304739196356309190161412380173157229974445196622836846025463018303437
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.562048886162943952805559118712243480149376563123162882806948745923684382850
Short name T805
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.44 seconds
Started Nov 22 01:59:33 PM PST 23
Finished Nov 22 02:00:01 PM PST 23
Peak memory 203300 kb
Host smart-0b00e913-e71b-4d24-9fca-ce2025a69d3d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=562048886162943952805559118712243480149376563123162882806948745923684382850 -assert nopostproc +UVM_TESTNAME=xba
r_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.562048886162943952805559118712243480149376563123162882806948745923684382850
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.108950862981976048600911231139250833443287944877896339264499402395848702224717
Short name T519
Test name
Test status
Simulation time 4402420935 ps
CPU time 34.94 seconds
Started Nov 22 01:59:29 PM PST 23
Finished Nov 22 02:00:05 PM PST 23
Peak memory 203256 kb
Host smart-e4fd233f-02a9-4f7b-8bc6-b588c6de6539
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=108950862981976048600911231139250833443287944877896339264499402395848702224717 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_l
og /dev/null -cm_name 47.xbar_error_random.108950862981976048600911231139250833443287944877896339264499402395848702224717
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.8848440241416312037200340716956134314924981683769781136650703664336744161928
Short name T322
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.84 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 211364 kb
Host smart-59852e51-dde9-4a98-a176-d8c84179886b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8848440241416312037200340716956134314924981683769781136650703664336744161928 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 47.xbar_random.8848440241416312037200340716956134314924981683769781136650703664336744161928
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.48140254157867019154931975237050221402825843482045000841252658879059955032747
Short name T709
Test name
Test status
Simulation time 188793233435 ps
CPU time 316.79 seconds
Started Nov 22 01:59:30 PM PST 23
Finished Nov 22 02:04:47 PM PST 23
Peak memory 204716 kb
Host smart-06bf237d-6e7e-47be-bbec-67020ddb81c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=48140254157867019154931975237050221402825843482045000841252658879059955032747 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 47.xbar_random_large_delays.48140254157867019154931975237050221402825843482045000841252658879059955032747
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.100359643328429248215219829059428084962457933036191167914047600063143613686689
Short name T137
Test name
Test status
Simulation time 126189108435 ps
CPU time 326.16 seconds
Started Nov 22 01:59:30 PM PST 23
Finished Nov 22 02:04:57 PM PST 23
Peak memory 211476 kb
Host smart-a926d89c-27ed-420e-980e-b92484fa63ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=100359643328429248215219829059428084962457933036191167914047600063143613686689 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.100359643328429248215219829059428084962457933036191167914047600063143613686689
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.43258591474016032022425867297709266287302197300520267024107652077121407767150
Short name T522
Test name
Test status
Simulation time 766920935 ps
CPU time 24.4 seconds
Started Nov 22 01:59:31 PM PST 23
Finished Nov 22 01:59:56 PM PST 23
Peak memory 203788 kb
Host smart-2e7b4a52-9c39-4561-a5e5-7f841872e59e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43258591474016032022425867297709266287302197300520267024107652077121407767150 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.43258591474016032022425867297709266287302197300520267024107652077121407767150
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.109063471939902019818560083293469665286256493072183588397532116865927377055320
Short name T565
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.47 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 02:00:11 PM PST 23
Peak memory 204284 kb
Host smart-ec6cb5bd-d0c9-44bf-aff7-0e0861a3097c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=109063471939902019818560083293469665286256493072183588397532116865927377055320 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 47.xbar_same_source.109063471939902019818560083293469665286256493072183588397532116865927377055320
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.44468828397226572859577424185441854776558308105774181119084502875871101962038
Short name T346
Test name
Test status
Simulation time 669983435 ps
CPU time 4.35 seconds
Started Nov 22 01:59:27 PM PST 23
Finished Nov 22 01:59:32 PM PST 23
Peak memory 203192 kb
Host smart-00f9eb54-be2a-4c63-86ea-c338c94b8011
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44468828397226572859577424185441854776558308105774181119084502875871101962038 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 47.xbar_smoke.44468828397226572859577424185441854776558308105774181119084502875871101962038
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.62807695096048539614669949804940492293183957687823288822575224778762732221002
Short name T594
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.4 seconds
Started Nov 22 01:59:30 PM PST 23
Finished Nov 22 02:00:19 PM PST 23
Peak memory 203276 kb
Host smart-d1fccbd8-69aa-4ebe-89d1-3db3da5f3988
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=62807695096048539614669949804940492293183957687823288822575224778762732221002 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.62807695096048539614669949804940492293183957687823288822575224778762732221002
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.23201314904916571695162653979704603603297785443026158909153894256137569610501
Short name T559
Test name
Test status
Simulation time 17662295935 ps
CPU time 43.19 seconds
Started Nov 22 01:59:30 PM PST 23
Finished Nov 22 02:00:14 PM PST 23
Peak memory 203156 kb
Host smart-85cf06c5-6681-48b0-9966-d98322466359
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=23201314904916571695162653979704603603297785443026158909153894256137569610501 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.23201314904916571695162653979704603603297785443026158909153894256137569610501
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.41260529701953088779501569551677226084875642303555166865727134156058389072124
Short name T564
Test name
Test status
Simulation time 116233435 ps
CPU time 2.41 seconds
Started Nov 22 01:59:23 PM PST 23
Finished Nov 22 01:59:26 PM PST 23
Peak memory 203052 kb
Host smart-a1e2d695-cc07-4bad-b629-55d188a4f4c3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41260529701953088779501569551677226084875642303555166865727134156058389072124 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.41260529701953088779501569551677226084875642303555166865727134156058389072124
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.103738605176620230307502374829591685792681246949384422332984014551826712871654
Short name T731
Test name
Test status
Simulation time 18904859184 ps
CPU time 146.57 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 02:02:00 PM PST 23
Peak memory 205768 kb
Host smart-1d187291-1fa6-4c0f-8424-67d34d05d4d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103738605176620230307502374829591685792681246949384422332984014551826712871654 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 47.xbar_stress_all.103738605176620230307502374829591685792681246949384422332984014551826712871654
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.83168824691791314718142069036420287117158324550098556158224533547379349299304
Short name T840
Test name
Test status
Simulation time 18894549184 ps
CPU time 117.66 seconds
Started Nov 22 01:59:53 PM PST 23
Finished Nov 22 02:01:51 PM PST 23
Peak memory 211404 kb
Host smart-11d3942a-2899-4d37-ba69-d42db7487545
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=83168824691791314718142069036420287117158324550098556158224533547379349299304 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 47.xbar_stress_all_with_error.83168824691791314718142069036420287117158324550098556158224533547379349299304
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.76229916884390045322318757663927733529313276134199078830765489792626873509172
Short name T287
Test name
Test status
Simulation time 5188549184 ps
CPU time 294.71 seconds
Started Nov 22 01:59:33 PM PST 23
Finished Nov 22 02:04:29 PM PST 23
Peak memory 208568 kb
Host smart-c3a70b23-7b61-44a0-af59-c257770a7571
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76229916884390045322318757663927733529313276134199078830765489792626873509172 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.76229916884390045322318757663927733529313276134199078830765489792626873509172
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.97872229861069232598021615146499960603402945161389252504486512443181627913183
Short name T568
Test name
Test status
Simulation time 5188549184 ps
CPU time 224.01 seconds
Started Nov 22 01:59:31 PM PST 23
Finished Nov 22 02:03:16 PM PST 23
Peak memory 219532 kb
Host smart-69285915-6b5e-497f-abee-6f679bb3f992
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=97872229861069232598021615146499960603402945161389252504486512443181627913183 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.97872229861069232598021615146499960603402945161389252504486512443181627913183
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.28430787282477136237417925257545156984769292270165826025635262987995424781508
Short name T36
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.2 seconds
Started Nov 22 01:59:34 PM PST 23
Finished Nov 22 02:00:03 PM PST 23
Peak memory 211344 kb
Host smart-7b68aaab-047b-46c5-abf1-c0873986b8f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28430787282477136237417925257545156984769292270165826025635262987995424781508 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 47.xbar_unmapped_addr.28430787282477136237417925257545156984769292270165826025635262987995424781508
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.13246766173576808418192117885706017419230350494215945965662720639196821882953
Short name T47
Test name
Test status
Simulation time 7399045935 ps
CPU time 62 seconds
Started Nov 22 01:59:24 PM PST 23
Finished Nov 22 02:00:27 PM PST 23
Peak memory 206268 kb
Host smart-66c12cad-6524-47a0-877a-1ff73471b1e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13246766173576808418192117885706017419230350494215945965662720639196821882953 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.13246766173576808418192117885706017419230350494215945965662720639196821882953
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.105027950635706095506228838975915933796756511169617334071200806376834687693653
Short name T485
Test name
Test status
Simulation time 304288045935 ps
CPU time 773.96 seconds
Started Nov 22 01:59:41 PM PST 23
Finished Nov 22 02:12:36 PM PST 23
Peak memory 211480 kb
Host smart-c1183847-ab1c-4a80-a424-087342ba5d5c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=105027950635706095506228838975915933796756511169617334071200806376834687693653 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.105027950635706095506228838975915933796756511169617334071200806376834687693653
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.114241754173383741217646580302787865060365495626578133578031902324707696250856
Short name T209
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.65 seconds
Started Nov 22 01:59:40 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 203324 kb
Host smart-eb240908-db80-4d29-b774-a1c77ce62df9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=114241754173383741217646580302787865060365495626578133578031902324707696250856 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.114241754173383741217646580302787865060365495626578133578031902324707696250856
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.58295356256307496682863688222949506954074744842940374521139098688183846996230
Short name T255
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.85 seconds
Started Nov 22 01:59:33 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 203260 kb
Host smart-be660da9-b3c6-4b5c-9836-2dedbd8a42b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=58295356256307496682863688222949506954074744842940374521139098688183846996230 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 48.xbar_error_random.58295356256307496682863688222949506954074744842940374521139098688183846996230
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.74884753844040790324274442695159773943619774008614236810211191741388390294558
Short name T891
Test name
Test status
Simulation time 4402420935 ps
CPU time 35.61 seconds
Started Nov 22 01:59:27 PM PST 23
Finished Nov 22 02:00:04 PM PST 23
Peak memory 211464 kb
Host smart-4960f6e2-d5de-47b5-9ecf-daaee6e1553e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74884753844040790324274442695159773943619774008614236810211191741388390294558 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 48.xbar_random.74884753844040790324274442695159773943619774008614236810211191741388390294558
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.72153245589833401280713504427303897656838421577421544765754741687874526337196
Short name T414
Test name
Test status
Simulation time 188793233435 ps
CPU time 322.38 seconds
Started Nov 22 01:59:31 PM PST 23
Finished Nov 22 02:04:54 PM PST 23
Peak memory 204784 kb
Host smart-341e1b8f-0cc2-4b54-adf8-df647c8c86a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=72153245589833401280713504427303897656838421577421544765754741687874526337196 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 48.xbar_random_large_delays.72153245589833401280713504427303897656838421577421544765754741687874526337196
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.93312289607544323843658701217415944042952398808916944162972182447154102083789
Short name T792
Test name
Test status
Simulation time 126189108435 ps
CPU time 329.64 seconds
Started Nov 22 01:59:41 PM PST 23
Finished Nov 22 02:05:12 PM PST 23
Peak memory 211476 kb
Host smart-8f201225-aab9-4c55-8803-9d736e8bd491
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=93312289607544323843658701217415944042952398808916944162972182447154102083789 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.93312289607544323843658701217415944042952398808916944162972182447154102083789
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.73959896250919288314884116439821731724675767372538125740084359839687835978166
Short name T766
Test name
Test status
Simulation time 766920935 ps
CPU time 24.93 seconds
Started Nov 22 01:59:31 PM PST 23
Finished Nov 22 01:59:57 PM PST 23
Peak memory 203832 kb
Host smart-177248fa-762b-44e4-96a9-5d63386511f4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73959896250919288314884116439821731724675767372538125740084359839687835978166 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.73959896250919288314884116439821731724675767372538125740084359839687835978166
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.56075606949707255872327399908398369416163880477581866432010851176310693645069
Short name T206
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.24 seconds
Started Nov 22 01:59:31 PM PST 23
Finished Nov 22 02:00:10 PM PST 23
Peak memory 204204 kb
Host smart-87e43101-c1a5-43ac-89f9-880a877b933f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56075606949707255872327399908398369416163880477581866432010851176310693645069 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 48.xbar_same_source.56075606949707255872327399908398369416163880477581866432010851176310693645069
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.97760140680386711211291744916722354982620012986906746069311963400715655435931
Short name T527
Test name
Test status
Simulation time 669983435 ps
CPU time 4.04 seconds
Started Nov 22 01:59:33 PM PST 23
Finished Nov 22 01:59:38 PM PST 23
Peak memory 203204 kb
Host smart-7674fedc-10cb-46bf-a9d8-946a42107827
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=97760140680386711211291744916722354982620012986906746069311963400715655435931 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 48.xbar_smoke.97760140680386711211291744916722354982620012986906746069311963400715655435931
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.78648118164368474369879998974886199264177939928568662143435145428617268645801
Short name T440
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.78 seconds
Started Nov 22 01:59:42 PM PST 23
Finished Nov 22 02:00:31 PM PST 23
Peak memory 203164 kb
Host smart-de824f32-03e0-481b-8bf7-380740761acb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=78648118164368474369879998974886199264177939928568662143435145428617268645801 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.78648118164368474369879998974886199264177939928568662143435145428617268645801
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.92041071508703734300586995908596712704148218045500381248650758366667103763322
Short name T333
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.01 seconds
Started Nov 22 01:59:46 PM PST 23
Finished Nov 22 02:00:31 PM PST 23
Peak memory 203324 kb
Host smart-e37484a7-1316-4ad0-a14f-1c68d7e90e0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=92041071508703734300586995908596712704148218045500381248650758366667103763322 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.92041071508703734300586995908596712704148218045500381248650758366667103763322
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.45821705746177718456216293850339998923724930632739255665463143321507042935461
Short name T351
Test name
Test status
Simulation time 116233435 ps
CPU time 2.43 seconds
Started Nov 22 01:59:45 PM PST 23
Finished Nov 22 01:59:49 PM PST 23
Peak memory 203132 kb
Host smart-157efe64-bd8c-4938-92a2-ef69efd9a0d9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45821705746177718456216293850339998923724930632739255665463143321507042935461 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.45821705746177718456216293850339998923724930632739255665463143321507042935461
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.68368811755303580124363092124727308914119975105518466000492146569417271749955
Short name T441
Test name
Test status
Simulation time 18904859184 ps
CPU time 134.51 seconds
Started Nov 22 01:59:31 PM PST 23
Finished Nov 22 02:01:46 PM PST 23
Peak memory 205828 kb
Host smart-5adb6bdb-3dc2-44cb-b4aa-bf853ea83d0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68368811755303580124363092124727308914119975105518466000492146569417271749955 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 48.xbar_stress_all.68368811755303580124363092124727308914119975105518466000492146569417271749955
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.29108922158359978401843758156668942959633586813063217583660154065766986945193
Short name T808
Test name
Test status
Simulation time 18894549184 ps
CPU time 119.8 seconds
Started Nov 22 01:59:32 PM PST 23
Finished Nov 22 02:01:33 PM PST 23
Peak memory 211416 kb
Host smart-005e2a52-bbe5-4728-9f5f-2b94ad3e39d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=29108922158359978401843758156668942959633586813063217583660154065766986945193 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 48.xbar_stress_all_with_error.29108922158359978401843758156668942959633586813063217583660154065766986945193
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.10508084094868865708157989756097677178447845830505864829668443645803062144647
Short name T327
Test name
Test status
Simulation time 5188549184 ps
CPU time 303.24 seconds
Started Nov 22 01:59:34 PM PST 23
Finished Nov 22 02:04:39 PM PST 23
Peak memory 208432 kb
Host smart-b9f64b07-e767-4aac-a125-0d6c6d08c4c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=10508084094868865708157989756097677178447845830505864829668443645803062144647 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.10508084094868865708157989756097677178447845830505864829668443645803062144647
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.5954765221544935464081935528984587586663036869314194412123203551030523995029
Short name T760
Test name
Test status
Simulation time 5188549184 ps
CPU time 226.48 seconds
Started Nov 22 01:59:34 PM PST 23
Finished Nov 22 02:03:21 PM PST 23
Peak memory 219688 kb
Host smart-fc9b6a47-e610-4733-adc9-6d1edf0b2750
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5954765221544935464081935528984587586663036869314194412123203551030523995029 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.5954765221544935464081935528984587586663036869314194412123203551030523995029
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.76164355055999083391933254266458736561119029787227161926619777575808380690031
Short name T334
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.94 seconds
Started Nov 22 01:59:38 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 211360 kb
Host smart-a950293b-59b5-46d2-a835-de80b9c5b1d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76164355055999083391933254266458736561119029787227161926619777575808380690031 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 48.xbar_unmapped_addr.76164355055999083391933254266458736561119029787227161926619777575808380690031
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.52830715471147148009590767208615720651415798543164008648202378380518164691855
Short name T76
Test name
Test status
Simulation time 7399045935 ps
CPU time 62.86 seconds
Started Nov 22 01:59:34 PM PST 23
Finished Nov 22 02:00:38 PM PST 23
Peak memory 206292 kb
Host smart-a31fb7b6-5a5c-4b5d-b6ea-1d41aa07d5ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=52830715471147148009590767208615720651415798543164008648202378380518164691855 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.52830715471147148009590767208615720651415798543164008648202378380518164691855
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.15265468723567431243090748642722988385397815338225098046845772446823799285113
Short name T39
Test name
Test status
Simulation time 304288045935 ps
CPU time 783.51 seconds
Started Nov 22 01:59:27 PM PST 23
Finished Nov 22 02:12:31 PM PST 23
Peak memory 211432 kb
Host smart-1b72340c-d2cf-4479-9431-ac0a015cdb0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=15265468723567431243090748642722988385397815338225098046845772446823799285113 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.15265468723567431243090748642722988385397815338225098046845772446823799285113
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.56919592087124068293170986015696920477496422116078751667401939206212481556535
Short name T430
Test name
Test status
Simulation time 3310545935 ps
CPU time 26.29 seconds
Started Nov 22 01:59:42 PM PST 23
Finished Nov 22 02:00:09 PM PST 23
Peak memory 203356 kb
Host smart-16523940-d30a-47dc-aad3-30f11063acfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=56919592087124068293170986015696920477496422116078751667401939206212481556535 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.56919592087124068293170986015696920477496422116078751667401939206212481556535
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.64216131141565753863256167287075933848444838610270875964312166738142502473907
Short name T28
Test name
Test status
Simulation time 4402420935 ps
CPU time 34.01 seconds
Started Nov 22 01:59:29 PM PST 23
Finished Nov 22 02:00:04 PM PST 23
Peak memory 203268 kb
Host smart-81ba8122-77a2-4804-ae15-d75c2030a3ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64216131141565753863256167287075933848444838610270875964312166738142502473907 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 49.xbar_error_random.64216131141565753863256167287075933848444838610270875964312166738142502473907
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.87861933662970419509665310465315738377781922000802650885451297331831015520240
Short name T412
Test name
Test status
Simulation time 4402420935 ps
CPU time 40.22 seconds
Started Nov 22 01:59:40 PM PST 23
Finished Nov 22 02:00:21 PM PST 23
Peak memory 211420 kb
Host smart-38391d79-bfdf-4a8c-9f22-9e421f3624c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87861933662970419509665310465315738377781922000802650885451297331831015520240 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 49.xbar_random.87861933662970419509665310465315738377781922000802650885451297331831015520240
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.112018236398834295246287348120350445892576364110164683844013094221993293740756
Short name T477
Test name
Test status
Simulation time 188793233435 ps
CPU time 331.38 seconds
Started Nov 22 01:59:31 PM PST 23
Finished Nov 22 02:05:03 PM PST 23
Peak memory 204832 kb
Host smart-c470febe-9085-4327-b59c-d43ae560f4ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=112018236398834295246287348120350445892576364110164683844013094221993293740756 -assert nopostproc +UVM
_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.
vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.112018236398834295246287348120350445892576364110164683844013094221993293740756
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.50757837858836594636045838165299299739595024980360521186744625149559176155979
Short name T769
Test name
Test status
Simulation time 126189108435 ps
CPU time 323.54 seconds
Started Nov 22 01:59:28 PM PST 23
Finished Nov 22 02:04:53 PM PST 23
Peak memory 211476 kb
Host smart-c9d7d648-fd16-494c-9daa-960ad7977a59
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=50757837858836594636045838165299299739595024980360521186744625149559176155979 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.50757837858836594636045838165299299739595024980360521186744625149559176155979
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.11615541685106864586847069071209464493394275655460236501236737379945464801411
Short name T251
Test name
Test status
Simulation time 766920935 ps
CPU time 26.92 seconds
Started Nov 22 01:59:35 PM PST 23
Finished Nov 22 02:00:03 PM PST 23
Peak memory 203796 kb
Host smart-a501cfba-1df9-4f67-956a-dbfe4f3c01bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11615541685106864586847069071209464493394275655460236501236737379945464801411 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.11615541685106864586847069071209464493394275655460236501236737379945464801411
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.8899628720424381146592272580747073581188493714701377889009417728050200155510
Short name T865
Test name
Test status
Simulation time 7116170935 ps
CPU time 39.88 seconds
Started Nov 22 01:59:27 PM PST 23
Finished Nov 22 02:00:08 PM PST 23
Peak memory 204336 kb
Host smart-9c703b23-b2e6-46d8-8a81-23b548ae9b6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8899628720424381146592272580747073581188493714701377889009417728050200155510 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 49.xbar_same_source.8899628720424381146592272580747073581188493714701377889009417728050200155510
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.60076302714569243585377939711295894036831629294895263687868425249772562428972
Short name T431
Test name
Test status
Simulation time 669983435 ps
CPU time 4.1 seconds
Started Nov 22 01:59:40 PM PST 23
Finished Nov 22 01:59:45 PM PST 23
Peak memory 203080 kb
Host smart-26bf1f46-eb2f-42db-adfe-a233cf3003a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=60076302714569243585377939711295894036831629294895263687868425249772562428972 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 49.xbar_smoke.60076302714569243585377939711295894036831629294895263687868425249772562428972
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.27899760164480351651430220010332160475960535283712683081533906379808201780222
Short name T540
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.79 seconds
Started Nov 22 01:59:29 PM PST 23
Finished Nov 22 02:00:17 PM PST 23
Peak memory 203280 kb
Host smart-9bfc22f5-6005-4b88-9a26-cd903b8faa65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=27899760164480351651430220010332160475960535283712683081533906379808201780222 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.27899760164480351651430220010332160475960535283712683081533906379808201780222
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.100197315296253917407626184922247664247673946998528593731596164009216846294065
Short name T436
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.05 seconds
Started Nov 22 01:59:27 PM PST 23
Finished Nov 22 02:00:13 PM PST 23
Peak memory 203212 kb
Host smart-58f9d121-b8a6-477b-b01c-10a21b3392a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=100197315296253917407626184922247664247673946998528593731596164009216846294065 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.100197315296253917407626184922247664247673946998528593731596164009216846294065
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.47781018867161803178417882447840125939967174476928797291857078583778209821696
Short name T512
Test name
Test status
Simulation time 116233435 ps
CPU time 2.52 seconds
Started Nov 22 01:59:34 PM PST 23
Finished Nov 22 01:59:38 PM PST 23
Peak memory 203056 kb
Host smart-55c6906c-03d8-4a07-8115-3179f35a9ab7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47781018867161803178417882447840125939967174476928797291857078583778209821696 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.47781018867161803178417882447840125939967174476928797291857078583778209821696
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.108269090839502998467372311535571291956909052294547990158758104079085561594620
Short name T763
Test name
Test status
Simulation time 18904859184 ps
CPU time 136.84 seconds
Started Nov 22 01:59:29 PM PST 23
Finished Nov 22 02:01:47 PM PST 23
Peak memory 205640 kb
Host smart-6ee731c9-cf5f-47ac-a9ff-303284f376dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=108269090839502998467372311535571291956909052294547990158758104079085561594620 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 49.xbar_stress_all.108269090839502998467372311535571291956909052294547990158758104079085561594620
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.80581111102941271235605927757666289468160396815724017864003437369524868587128
Short name T554
Test name
Test status
Simulation time 18894549184 ps
CPU time 125.95 seconds
Started Nov 22 01:59:30 PM PST 23
Finished Nov 22 02:01:37 PM PST 23
Peak memory 211444 kb
Host smart-cbe03d70-00ac-4dae-a2cb-2cc3ec7d375d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=80581111102941271235605927757666289468160396815724017864003437369524868587128 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 49.xbar_stress_all_with_error.80581111102941271235605927757666289468160396815724017864003437369524868587128
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.42199624814749912120635726509045716821972795562555257090924045342706909055419
Short name T175
Test name
Test status
Simulation time 5188549184 ps
CPU time 291.21 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 02:04:35 PM PST 23
Peak memory 208508 kb
Host smart-30eb5437-1ee3-4105-b55f-a1458c0c013f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=42199624814749912120635726509045716821972795562555257090924045342706909055419 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.42199624814749912120635726509045716821972795562555257090924045342706909055419
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.57112404281087326735607283537541822462439143163466779523181455945297061050810
Short name T814
Test name
Test status
Simulation time 5188549184 ps
CPU time 222.5 seconds
Started Nov 22 01:59:42 PM PST 23
Finished Nov 22 02:03:25 PM PST 23
Peak memory 219624 kb
Host smart-4da02acb-b71a-48a3-b177-746f5b752a48
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=57112404281087326735607283537541822462439143163466779523181455945297061050810 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.57112404281087326735607283537541822462439143163466779523181455945297061050810
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.45201898692479164631270938575941876177900418769431853265413054482115157685620
Short name T651
Test name
Test status
Simulation time 3307045935 ps
CPU time 29.13 seconds
Started Nov 22 01:59:43 PM PST 23
Finished Nov 22 02:00:13 PM PST 23
Peak memory 211388 kb
Host smart-57f6dd3e-af66-4d67-8a82-7f8e928fbd8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45201898692479164631270938575941876177900418769431853265413054482115157685620 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 49.xbar_unmapped_addr.45201898692479164631270938575941876177900418769431853265413054482115157685620
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.66931818207995991192114891360870659347380370488881654714003831452989859586646
Short name T367
Test name
Test status
Simulation time 7399045935 ps
CPU time 58.85 seconds
Started Nov 22 01:56:43 PM PST 23
Finished Nov 22 01:57:44 PM PST 23
Peak memory 211536 kb
Host smart-57a26434-d22a-44c3-8881-cd19fa70ded8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66931818207995991192114891360870659347380370488881654714003831452989859586646 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.66931818207995991192114891360870659347380370488881654714003831452989859586646
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.97613835298354261913982626994206894341917634790735855123556049459417839479164
Short name T216
Test name
Test status
Simulation time 304288045935 ps
CPU time 787.15 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 02:09:30 PM PST 23
Peak memory 211444 kb
Host smart-a1240bec-7594-4871-9449-f3b7e07ab292
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=97613835298354261913982626994206894341917634790735855123556049459417839479164 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.97613835298354261913982626994206894341917634790735855123556049459417839479164
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.54246583528864505995791275005677274727795381907734497187367754717407280378352
Short name T297
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.72 seconds
Started Nov 22 01:56:19 PM PST 23
Finished Nov 22 01:56:46 PM PST 23
Peak memory 203312 kb
Host smart-a2f8bffe-0208-409e-a604-4f29f3a8c83b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54246583528864505995791275005677274727795381907734497187367754717407280378352 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.54246583528864505995791275005677274727795381907734497187367754717407280378352
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.78062546394595283004642194831948520242501104462206730914330273211972461168166
Short name T705
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.91 seconds
Started Nov 22 01:56:38 PM PST 23
Finished Nov 22 01:57:13 PM PST 23
Peak memory 203244 kb
Host smart-c08259ed-9c97-4b33-ae44-1fb6717045ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78062546394595283004642194831948520242501104462206730914330273211972461168166 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 5.xbar_error_random.78062546394595283004642194831948520242501104462206730914330273211972461168166
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.58355571446340004197197597077413201901623338042455582633387295064788239964899
Short name T880
Test name
Test status
Simulation time 4402420935 ps
CPU time 36.79 seconds
Started Nov 22 01:56:39 PM PST 23
Finished Nov 22 01:57:16 PM PST 23
Peak memory 211420 kb
Host smart-b0905aa9-0644-453a-896b-db0ea9a4872a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=58355571446340004197197597077413201901623338042455582633387295064788239964899 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 5.xbar_random.58355571446340004197197597077413201901623338042455582633387295064788239964899
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.30650469445080861661377686952095105832611820732602470106044280889546375759480
Short name T197
Test name
Test status
Simulation time 126189108435 ps
CPU time 327.29 seconds
Started Nov 22 01:56:38 PM PST 23
Finished Nov 22 02:02:06 PM PST 23
Peak memory 211496 kb
Host smart-2d7414e3-e279-444d-ad6e-dfbc633deed6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=30650469445080861661377686952095105832611820732602470106044280889546375759480 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.30650469445080861661377686952095105832611820732602470106044280889546375759480
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.77678808682604215958173841945701416261723902739937292080167739690617374504930
Short name T474
Test name
Test status
Simulation time 766920935 ps
CPU time 27.32 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:56:49 PM PST 23
Peak memory 211364 kb
Host smart-f9578db3-00a8-4e16-80c1-efa188fef168
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77678808682604215958173841945701416261723902739937292080167739690617374504930 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.77678808682604215958173841945701416261723902739937292080167739690617374504930
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.64376559714457528803612092927354828818521395320615612429246470654904773319824
Short name T762
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.22 seconds
Started Nov 22 01:56:41 PM PST 23
Finished Nov 22 01:57:20 PM PST 23
Peak memory 204204 kb
Host smart-542ed5cb-9427-4007-b679-cb05332e8ea4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64376559714457528803612092927354828818521395320615612429246470654904773319824 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 5.xbar_same_source.64376559714457528803612092927354828818521395320615612429246470654904773319824
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.22870381636554162089814287043803815466960749926993782189242840208607835479139
Short name T72
Test name
Test status
Simulation time 669983435 ps
CPU time 4.15 seconds
Started Nov 22 01:56:34 PM PST 23
Finished Nov 22 01:56:38 PM PST 23
Peak memory 203068 kb
Host smart-90ac4b4e-815e-4cd7-bcdc-510c36511c25
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22870381636554162089814287043803815466960749926993782189242840208607835479139 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 5.xbar_smoke.22870381636554162089814287043803815466960749926993782189242840208607835479139
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.17471908497687680571557667672093705855577087922302953645765408933429161196378
Short name T853
Test name
Test status
Simulation time 28419483435 ps
CPU time 48.14 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:57:10 PM PST 23
Peak memory 203092 kb
Host smart-dcb3ea25-19ca-41c3-8624-b908546e3c3b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=17471908497687680571557667672093705855577087922302953645765408933429161196378 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.17471908497687680571557667672093705855577087922302953645765408933429161196378
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.13191518172267470768052485982704943314595139700484579220494178787270541265575
Short name T452
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.22 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:57:06 PM PST 23
Peak memory 203260 kb
Host smart-79e66786-0bcb-4aec-ae41-a5bb8c92f717
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=13191518172267470768052485982704943314595139700484579220494178787270541265575 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.13191518172267470768052485982704943314595139700484579220494178787270541265575
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.9435703290282668804550186144414856543181276241778710417942916186631974043539
Short name T529
Test name
Test status
Simulation time 116233435 ps
CPU time 2.45 seconds
Started Nov 22 01:56:17 PM PST 23
Finished Nov 22 01:56:20 PM PST 23
Peak memory 203032 kb
Host smart-87df0562-0ba7-4d4b-8039-4d6d385094c6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9435703290282668804550186144414856543181276241778710417942916186631974043539 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mod
e.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.9435703290282668804550186144414856543181276241778710417942916186631974043539
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.54160907065305977678533069528459652702646453638876779683572745574631158109156
Short name T757
Test name
Test status
Simulation time 18904859184 ps
CPU time 133.46 seconds
Started Nov 22 01:56:23 PM PST 23
Finished Nov 22 01:58:37 PM PST 23
Peak memory 205796 kb
Host smart-a0d0ad61-3270-4d65-8685-1f243f8f5b83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54160907065305977678533069528459652702646453638876779683572745574631158109156 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 5.xbar_stress_all.54160907065305977678533069528459652702646453638876779683572745574631158109156
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.27286682945841062549054516486811694802809650827001920305427463209883591552843
Short name T502
Test name
Test status
Simulation time 18894549184 ps
CPU time 124.38 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:58:26 PM PST 23
Peak memory 211460 kb
Host smart-1c56a089-08ab-48bc-b715-5be069feb75e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=27286682945841062549054516486811694802809650827001920305427463209883591552843 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 5.xbar_stress_all_with_error.27286682945841062549054516486811694802809650827001920305427463209883591552843
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.105016040117700030240433494372396098040266786532054771849231974727629874302123
Short name T387
Test name
Test status
Simulation time 5188549184 ps
CPU time 290.5 seconds
Started Nov 22 01:56:41 PM PST 23
Finished Nov 22 02:01:32 PM PST 23
Peak memory 208420 kb
Host smart-385d6d7c-17bc-4194-938c-e4d7ec8672ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105016040117700030240433494372396098040266786532054771849231974727629874302123 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.105016040117700030240433494372396098040266786532054771849231974727629874302123
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.23063972975686843532812170833645621642652925169405671478879647944233020831925
Short name T521
Test name
Test status
Simulation time 5188549184 ps
CPU time 229.42 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 02:00:12 PM PST 23
Peak memory 219680 kb
Host smart-5b5daded-13e8-44be-b1f8-0fbef766fe0f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23063972975686843532812170833645621642652925169405671478879647944233020831925 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.23063972975686843532812170833645621642652925169405671478879647944233020831925
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.36969834053298424942594247512592395610317714062884505551525961554297510577961
Short name T275
Test name
Test status
Simulation time 3307045935 ps
CPU time 27.32 seconds
Started Nov 22 01:56:39 PM PST 23
Finished Nov 22 01:57:07 PM PST 23
Peak memory 211432 kb
Host smart-1a30c05e-aed4-4f99-957d-b5f1b089a926
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36969834053298424942594247512592395610317714062884505551525961554297510577961 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 5.xbar_unmapped_addr.36969834053298424942594247512592395610317714062884505551525961554297510577961
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.44401306851859457153597553485637088601201117673921065560301417145761338781372
Short name T355
Test name
Test status
Simulation time 7399045935 ps
CPU time 62.53 seconds
Started Nov 22 01:56:41 PM PST 23
Finished Nov 22 01:57:45 PM PST 23
Peak memory 211536 kb
Host smart-7f4f3f73-c8d1-4665-8e2b-069c717a51d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44401306851859457153597553485637088601201117673921065560301417145761338781372 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.44401306851859457153597553485637088601201117673921065560301417145761338781372
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.40428315480696354287958190981460822593889183980938192987506740521850207680296
Short name T543
Test name
Test status
Simulation time 304288045935 ps
CPU time 739 seconds
Started Nov 22 01:56:41 PM PST 23
Finished Nov 22 02:09:00 PM PST 23
Peak memory 211384 kb
Host smart-172cb5d9-2fa4-4127-aa42-eba63e21128d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=40428315480696354287958190981460822593889183980938192987506740521850207680296 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.40428315480696354287958190981460822593889183980938192987506740521850207680296
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.48507376374136876563065030980347676409684353879326905984564974960012033703826
Short name T571
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.75 seconds
Started Nov 22 01:56:40 PM PST 23
Finished Nov 22 01:57:07 PM PST 23
Peak memory 203268 kb
Host smart-7eb21693-9da7-431c-a418-94ec7261d785
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=48507376374136876563065030980347676409684353879326905984564974960012033703826 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.48507376374136876563065030980347676409684353879326905984564974960012033703826
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.88739298659495333017248009049669694447230649131293656759284402285384812772038
Short name T217
Test name
Test status
Simulation time 4402420935 ps
CPU time 32.72 seconds
Started Nov 22 01:56:25 PM PST 23
Finished Nov 22 01:56:59 PM PST 23
Peak memory 203264 kb
Host smart-382e4046-bfcf-4ef3-8ee6-c6bc9b2302cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=88739298659495333017248009049669694447230649131293656759284402285384812772038 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 6.xbar_error_random.88739298659495333017248009049669694447230649131293656759284402285384812772038
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.92352237696161008099608059796506887517304469177057087035282176701492822541528
Short name T395
Test name
Test status
Simulation time 4402420935 ps
CPU time 38.48 seconds
Started Nov 22 01:56:39 PM PST 23
Finished Nov 22 01:57:18 PM PST 23
Peak memory 211456 kb
Host smart-543bad33-e918-44f9-8922-7eb538bd2ad7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92352237696161008099608059796506887517304469177057087035282176701492822541528 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 6.xbar_random.92352237696161008099608059796506887517304469177057087035282176701492822541528
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.69525774503140551382797243659901499986643969870798734121840216307357693767949
Short name T301
Test name
Test status
Simulation time 188793233435 ps
CPU time 322.72 seconds
Started Nov 22 01:56:42 PM PST 23
Finished Nov 22 02:02:07 PM PST 23
Peak memory 204808 kb
Host smart-b2264a69-e2e1-44d4-b59b-621a6a89d816
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=69525774503140551382797243659901499986643969870798734121840216307357693767949 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 6.xbar_random_large_delays.69525774503140551382797243659901499986643969870798734121840216307357693767949
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.30026160737761848629356307535773302196141947737167464581189024074189088907302
Short name T212
Test name
Test status
Simulation time 126189108435 ps
CPU time 321.51 seconds
Started Nov 22 01:56:43 PM PST 23
Finished Nov 22 02:02:07 PM PST 23
Peak memory 211436 kb
Host smart-415579e1-0472-4b0b-b1ad-5a565dec55ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=30026160737761848629356307535773302196141947737167464581189024074189088907302 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.30026160737761848629356307535773302196141947737167464581189024074189088907302
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.41312530935865104627356084420930889321595574103812425315971925438499893623678
Short name T627
Test name
Test status
Simulation time 766920935 ps
CPU time 24.93 seconds
Started Nov 22 01:56:39 PM PST 23
Finished Nov 22 01:57:04 PM PST 23
Peak memory 211248 kb
Host smart-c884ae17-d8c8-429f-8b0a-3889e4821478
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41312530935865104627356084420930889321595574103812425315971925438499893623678 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.41312530935865104627356084420930889321595574103812425315971925438499893623678
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.97758342339130703692331186509715370204519648313773097206421801198787695020949
Short name T150
Test name
Test status
Simulation time 7116170935 ps
CPU time 35.72 seconds
Started Nov 22 01:56:25 PM PST 23
Finished Nov 22 01:57:02 PM PST 23
Peak memory 204184 kb
Host smart-17231e24-7c4b-40da-8663-dfb15830389a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=97758342339130703692331186509715370204519648313773097206421801198787695020949 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 6.xbar_same_source.97758342339130703692331186509715370204519648313773097206421801198787695020949
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.108804954822406577550006727735271584849159252796263100390256548822668896785139
Short name T288
Test name
Test status
Simulation time 669983435 ps
CPU time 4.12 seconds
Started Nov 22 01:56:38 PM PST 23
Finished Nov 22 01:56:42 PM PST 23
Peak memory 203144 kb
Host smart-c2581f55-7c78-46eb-ae4b-b65e42693d55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=108804954822406577550006727735271584849159252796263100390256548822668896785139 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 6.xbar_smoke.108804954822406577550006727735271584849159252796263100390256548822668896785139
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.97899968730589369060406678186195401965622051862005957927274285202039382839289
Short name T259
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.87 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:57:09 PM PST 23
Peak memory 203268 kb
Host smart-f5b64d7c-9cf0-465d-a775-6c9cb36e651f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=97899968730589369060406678186195401965622051862005957927274285202039382839289 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.97899968730589369060406678186195401965622051862005957927274285202039382839289
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.92396614670049546236007058928831061432808977200006819829112174032381262624099
Short name T514
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.19 seconds
Started Nov 22 01:56:26 PM PST 23
Finished Nov 22 01:57:11 PM PST 23
Peak memory 203272 kb
Host smart-ed7778e1-275b-46c5-9171-a066eed93791
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=92396614670049546236007058928831061432808977200006819829112174032381262624099 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.92396614670049546236007058928831061432808977200006819829112174032381262624099
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.62276736723529133592555152413366152826809391964122236788658338087884327291678
Short name T604
Test name
Test status
Simulation time 116233435 ps
CPU time 2.49 seconds
Started Nov 22 01:56:37 PM PST 23
Finished Nov 22 01:56:40 PM PST 23
Peak memory 203020 kb
Host smart-ce21b645-913c-41b6-9271-ef995c51a580
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62276736723529133592555152413366152826809391964122236788658338087884327291678 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.62276736723529133592555152413366152826809391964122236788658338087884327291678
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.16665942913996613112117563516528306649963024412906155095166480694391328671293
Short name T22
Test name
Test status
Simulation time 18904859184 ps
CPU time 130.94 seconds
Started Nov 22 01:56:40 PM PST 23
Finished Nov 22 01:58:52 PM PST 23
Peak memory 205804 kb
Host smart-b1481c57-105b-4749-930f-7b33daa1849e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16665942913996613112117563516528306649963024412906155095166480694391328671293 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 6.xbar_stress_all.16665942913996613112117563516528306649963024412906155095166480694391328671293
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.49153391372200311243425622848389088409780062418920029429796239885396128603844
Short name T349
Test name
Test status
Simulation time 18894549184 ps
CPU time 124.95 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 01:58:28 PM PST 23
Peak memory 211492 kb
Host smart-0ded3e18-3040-4d86-9682-6600bf4af7a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49153391372200311243425622848389088409780062418920029429796239885396128603844 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 6.xbar_stress_all_with_error.49153391372200311243425622848389088409780062418920029429796239885396128603844
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.93959675798420163578255484515935540708671837667377375670669540280759458243575
Short name T510
Test name
Test status
Simulation time 5188549184 ps
CPU time 295.06 seconds
Started Nov 22 01:56:41 PM PST 23
Finished Nov 22 02:01:37 PM PST 23
Peak memory 208348 kb
Host smart-fd8908ee-7442-4da4-871d-222e69610767
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93959675798420163578255484515935540708671837667377375670669540280759458243575 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.93959675798420163578255484515935540708671837667377375670669540280759458243575
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.87257170279860528078138912725759505568952118860727113254319624345257526184661
Short name T526
Test name
Test status
Simulation time 5188549184 ps
CPU time 226.35 seconds
Started Nov 22 01:56:25 PM PST 23
Finished Nov 22 02:00:13 PM PST 23
Peak memory 219496 kb
Host smart-2731aa5a-d9aa-415e-a4da-900a42332377
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=87257170279860528078138912725759505568952118860727113254319624345257526184661 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.87257170279860528078138912725759505568952118860727113254319624345257526184661
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.91884903548407620134303048959539696802688135570920737853054051082233123553587
Short name T25
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.44 seconds
Started Nov 22 01:56:26 PM PST 23
Finished Nov 22 01:56:56 PM PST 23
Peak memory 211384 kb
Host smart-ce38cc53-fb1a-43b7-8890-e984eb753a43
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91884903548407620134303048959539696802688135570920737853054051082233123553587 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 6.xbar_unmapped_addr.91884903548407620134303048959539696802688135570920737853054051082233123553587
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.55865046580786153359434316391192737381628666413900078621213892184901302828921
Short name T722
Test name
Test status
Simulation time 7399045935 ps
CPU time 69.1 seconds
Started Nov 22 01:56:26 PM PST 23
Finished Nov 22 01:57:36 PM PST 23
Peak memory 211424 kb
Host smart-5b9f5019-4ab5-47fa-90fb-40e5746b2ddc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55865046580786153359434316391192737381628666413900078621213892184901302828921 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.55865046580786153359434316391192737381628666413900078621213892184901302828921
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.108259988687269675968505639314938844829245220481285287392913487002815769715053
Short name T874
Test name
Test status
Simulation time 304288045935 ps
CPU time 772.15 seconds
Started Nov 22 01:56:24 PM PST 23
Finished Nov 22 02:09:17 PM PST 23
Peak memory 211412 kb
Host smart-e4570c4b-e110-4c1f-9ac6-86548b8acb65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=108259988687269675968505639314938844829245220481285287392913487002815769715053 -assert nopostproc +UVM_TES
TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bui
ld_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.108259988687269675968505639314938844829245220481285287392913487002815769715053
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.16990518244452758899291666391287904079074279803648194437412842843313658275196
Short name T116
Test name
Test status
Simulation time 3310545935 ps
CPU time 25.43 seconds
Started Nov 22 01:56:42 PM PST 23
Finished Nov 22 01:57:09 PM PST 23
Peak memory 203324 kb
Host smart-1cc110f8-7470-42b8-95d9-26832e722e8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16990518244452758899291666391287904079074279803648194437412842843313658275196 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.16990518244452758899291666391287904079074279803648194437412842843313658275196
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.99896241324684580186403792552610093203243371412667288929344127462815018167497
Short name T877
Test name
Test status
Simulation time 4402420935 ps
CPU time 35 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 01:56:58 PM PST 23
Peak memory 203224 kb
Host smart-11694801-56d6-4eff-96b4-1f3c871d99f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99896241324684580186403792552610093203243371412667288929344127462815018167497 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 7.xbar_error_random.99896241324684580186403792552610093203243371412667288929344127462815018167497
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.85056859913727389294234536743247834385820444636373799143220574829915724966834
Short name T91
Test name
Test status
Simulation time 4402420935 ps
CPU time 42.46 seconds
Started Nov 22 01:56:25 PM PST 23
Finished Nov 22 01:57:09 PM PST 23
Peak memory 211432 kb
Host smart-0a485694-18f0-4efa-9f25-e28f8ba9b8aa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=85056859913727389294234536743247834385820444636373799143220574829915724966834 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 7.xbar_random.85056859913727389294234536743247834385820444636373799143220574829915724966834
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.56874872947171303721690069207169800870414930822955405676179224100407328276222
Short name T33
Test name
Test status
Simulation time 188793233435 ps
CPU time 328.39 seconds
Started Nov 22 01:56:37 PM PST 23
Finished Nov 22 02:02:06 PM PST 23
Peak memory 204828 kb
Host smart-9123ed93-197c-4832-8b72-6e20a45a4103
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=56874872947171303721690069207169800870414930822955405676179224100407328276222 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 7.xbar_random_large_delays.56874872947171303721690069207169800870414930822955405676179224100407328276222
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.15936299935124164813517062078905529056694713954785305282904099347449111003625
Short name T208
Test name
Test status
Simulation time 126189108435 ps
CPU time 327.84 seconds
Started Nov 22 01:56:25 PM PST 23
Finished Nov 22 02:01:54 PM PST 23
Peak memory 211436 kb
Host smart-acddb314-15ba-4eda-8014-baa6469d3a71
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=15936299935124164813517062078905529056694713954785305282904099347449111003625 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.15936299935124164813517062078905529056694713954785305282904099347449111003625
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.51971260111126061420521854876165361588122936872390610603104849856717733225764
Short name T632
Test name
Test status
Simulation time 766920935 ps
CPU time 25.5 seconds
Started Nov 22 01:56:24 PM PST 23
Finished Nov 22 01:56:51 PM PST 23
Peak memory 211304 kb
Host smart-ae6ca619-d53a-4634-aeff-4a889bbe029f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51971260111126061420521854876165361588122936872390610603104849856717733225764 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.51971260111126061420521854876165361588122936872390610603104849856717733225764
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.26063269957424246291641535572846874194865053120372247108853566837826273448582
Short name T177
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.22 seconds
Started Nov 22 01:56:41 PM PST 23
Finished Nov 22 01:57:20 PM PST 23
Peak memory 204268 kb
Host smart-b2026d08-ae15-480c-9fc8-02f543bd46fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=26063269957424246291641535572846874194865053120372247108853566837826273448582 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 7.xbar_same_source.26063269957424246291641535572846874194865053120372247108853566837826273448582
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.69433826804863296442068265705516864584604801440468229462045883783864624495213
Short name T893
Test name
Test status
Simulation time 669983435 ps
CPU time 4.16 seconds
Started Nov 22 01:56:39 PM PST 23
Finished Nov 22 01:56:44 PM PST 23
Peak memory 203056 kb
Host smart-eea661d3-eb5b-4e5e-b203-0152f93e1993
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=69433826804863296442068265705516864584604801440468229462045883783864624495213 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 7.xbar_smoke.69433826804863296442068265705516864584604801440468229462045883783864624495213
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.74825811663602021642397044239436915849859059043282794767875669864083310357712
Short name T7
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.72 seconds
Started Nov 22 01:56:22 PM PST 23
Finished Nov 22 01:57:11 PM PST 23
Peak memory 203324 kb
Host smart-2cd8e7b4-139c-4cc0-bafc-49dbf80cf84c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=74825811663602021642397044239436915849859059043282794767875669864083310357712 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.74825811663602021642397044239436915849859059043282794767875669864083310357712
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.88527152154730913201069640251775244292037360368381204327387788595582462972339
Short name T156
Test name
Test status
Simulation time 17662295935 ps
CPU time 44.22 seconds
Started Nov 22 01:56:20 PM PST 23
Finished Nov 22 01:57:06 PM PST 23
Peak memory 203276 kb
Host smart-d6ec9fe0-503a-4cb8-9456-9b4a0afe2257
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=88527152154730913201069640251775244292037360368381204327387788595582462972339 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.88527152154730913201069640251775244292037360368381204327387788595582462972339
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.594812922959669099248416522094515203877421772205962041488169017831569160759
Short name T842
Test name
Test status
Simulation time 116233435 ps
CPU time 2.61 seconds
Started Nov 22 01:56:40 PM PST 23
Finished Nov 22 01:56:44 PM PST 23
Peak memory 203116 kb
Host smart-7de4e5cb-6d5a-4ac3-a4ac-9d0d33a75b4b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594812922959669099248416522094515203877421772205962041488169017831569160759 -assert nopostproc +U
VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.594812922959669099248416522094515203877421772205962041488169017831569160759
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.62259677637245474281982901799518052766991926934557945035183380485805044071214
Short name T791
Test name
Test status
Simulation time 18904859184 ps
CPU time 142.01 seconds
Started Nov 22 01:56:21 PM PST 23
Finished Nov 22 01:58:44 PM PST 23
Peak memory 205852 kb
Host smart-a8b74c3d-c367-41d6-8b7c-0730478bd00f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62259677637245474281982901799518052766991926934557945035183380485805044071214 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm
_log /dev/null -cm_name 7.xbar_stress_all.62259677637245474281982901799518052766991926934557945035183380485805044071214
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.110166392039847247567874580360221997895356564002754957430567474459927054142600
Short name T260
Test name
Test status
Simulation time 18894549184 ps
CPU time 124.47 seconds
Started Nov 22 01:56:41 PM PST 23
Finished Nov 22 01:58:47 PM PST 23
Peak memory 211436 kb
Host smart-ffde11ea-9434-42a3-b73c-da9c50f16e75
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110166392039847247567874580360221997895356564002754957430567474459927054142600 -assert nopostproc +UVM_TESTNAME=
xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.110166392039847247567874580360221997895356564002754957430567474459927054142600
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.23721986079475719904549937338259850771284133211122023439136837032338503708797
Short name T798
Test name
Test status
Simulation time 5188549184 ps
CPU time 294.28 seconds
Started Nov 22 01:56:42 PM PST 23
Finished Nov 22 02:01:37 PM PST 23
Peak memory 208480 kb
Host smart-6e63b34b-b4ba-4144-840d-f46e2c5fd667
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=23721986079475719904549937338259850771284133211122023439136837032338503708797 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.23721986079475719904549937338259850771284133211122023439136837032338503708797
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3091878746848500050335900339970152180395532678237217520920640617270484342280
Short name T701
Test name
Test status
Simulation time 5188549184 ps
CPU time 219.79 seconds
Started Nov 22 01:56:50 PM PST 23
Finished Nov 22 02:00:31 PM PST 23
Peak memory 219604 kb
Host smart-81d926e7-a373-4b1d-99b1-6f91dbeebf80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3091878746848500050335900339970152180395532678237217520920640617270484342280 -assert nopostproc +UVM_TESTNAME=xb
ar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3091878746848500050335900339970152180395532678237217520920640617270484342280
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.41064383069347067164324019890757068813876891147350161930641350854811912756302
Short name T362
Test name
Test status
Simulation time 3307045935 ps
CPU time 27.55 seconds
Started Nov 22 01:56:44 PM PST 23
Finished Nov 22 01:57:13 PM PST 23
Peak memory 211360 kb
Host smart-10ce4ab7-374f-43de-8530-2a137ad12385
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=41064383069347067164324019890757068813876891147350161930641350854811912756302 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 7.xbar_unmapped_addr.41064383069347067164324019890757068813876891147350161930641350854811912756302
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.614918709091410183428333397839332534977442954606681823025878414991572106159
Short name T714
Test name
Test status
Simulation time 7399045935 ps
CPU time 63.16 seconds
Started Nov 22 01:56:49 PM PST 23
Finished Nov 22 01:57:53 PM PST 23
Peak memory 211428 kb
Host smart-94e2dea2-a87d-4a1e-be74-9c6d4aac7e83
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=614918709091410183428333397839332534977442954606681823025878414991572106159 -assert nopostproc +UVM_TESTNAME=xba
r_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 8.xbar_access_same_device.614918709091410183428333397839332534977442954606681823025878414991572106159
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.15246446150326802966376467177298682495253728851824023038861647954512848718858
Short name T480
Test name
Test status
Simulation time 304288045935 ps
CPU time 792.45 seconds
Started Nov 22 01:56:45 PM PST 23
Finished Nov 22 02:09:59 PM PST 23
Peak memory 211428 kb
Host smart-0568669c-ce4d-419e-bdc0-1fa4e7ab2c4c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=15246446150326802966376467177298682495253728851824023038861647954512848718858 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.15246446150326802966376467177298682495253728851824023038861647954512848718858
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.99965925791035440103235406196824046301005687786197865724732490029035184108144
Short name T356
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.67 seconds
Started Nov 22 01:56:42 PM PST 23
Finished Nov 22 01:57:11 PM PST 23
Peak memory 203384 kb
Host smart-49a51199-f45f-47dd-8a48-6c0b6ecef406
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=99965925791035440103235406196824046301005687786197865724732490029035184108144 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.99965925791035440103235406196824046301005687786197865724732490029035184108144
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.89954700052640579151317527083757119789293323864779058587140086949038664229476
Short name T214
Test name
Test status
Simulation time 4402420935 ps
CPU time 33.34 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:28 PM PST 23
Peak memory 203228 kb
Host smart-486961f2-9c8f-4c95-88d4-444e5583820e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=89954700052640579151317527083757119789293323864779058587140086949038664229476 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_lo
g /dev/null -cm_name 8.xbar_error_random.89954700052640579151317527083757119789293323864779058587140086949038664229476
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.73730091651516586587972952512603571804975674817580872349308025807728170638434
Short name T800
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.89 seconds
Started Nov 22 01:56:50 PM PST 23
Finished Nov 22 01:57:29 PM PST 23
Peak memory 211496 kb
Host smart-6f287763-c27f-4f25-9a45-6319b5654775
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73730091651516586587972952512603571804975674817580872349308025807728170638434 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 8.xbar_random.73730091651516586587972952512603571804975674817580872349308025807728170638434
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.48108869674024276426132936623856531490342202448728466150718227884614846233573
Short name T44
Test name
Test status
Simulation time 188793233435 ps
CPU time 326.64 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 02:02:24 PM PST 23
Peak memory 204824 kb
Host smart-891f97ff-db8e-4cde-b11f-5d452520280f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=48108869674024276426132936623856531490342202448728466150718227884614846233573 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 8.xbar_random_large_delays.48108869674024276426132936623856531490342202448728466150718227884614846233573
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.34873221433101493431130050135453493357266792326056142893597797404893965164290
Short name T41
Test name
Test status
Simulation time 126189108435 ps
CPU time 329.76 seconds
Started Nov 22 01:56:45 PM PST 23
Finished Nov 22 02:02:16 PM PST 23
Peak memory 211412 kb
Host smart-cda9fc35-a343-415b-97c8-7b47f075a375
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=34873221433101493431130050135453493357266792326056142893597797404893965164290 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.34873221433101493431130050135453493357266792326056142893597797404893965164290
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.38417533205741918085401044437595929913365316872028922627929878136431680849338
Short name T776
Test name
Test status
Simulation time 766920935 ps
CPU time 24.7 seconds
Started Nov 22 01:56:42 PM PST 23
Finished Nov 22 01:57:08 PM PST 23
Peak memory 211340 kb
Host smart-a8fc084f-6039-4c00-8dd8-5b9f4130927d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38417533205741918085401044437595929913365316872028922627929878136431680849338 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.38417533205741918085401044437595929913365316872028922627929878136431680849338
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.91437705756404649819623588621258407702474111227160795519536830838970501980432
Short name T256
Test name
Test status
Simulation time 7116170935 ps
CPU time 38.64 seconds
Started Nov 22 01:56:45 PM PST 23
Finished Nov 22 01:57:24 PM PST 23
Peak memory 204256 kb
Host smart-bbd495d1-a0f6-446d-8176-e2692a58ea21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=91437705756404649819623588621258407702474111227160795519536830838970501980432 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 8.xbar_same_source.91437705756404649819623588621258407702474111227160795519536830838970501980432
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.78273732325532961171718146698568231759885555513307522678009731710490662986284
Short name T95
Test name
Test status
Simulation time 669983435 ps
CPU time 4.29 seconds
Started Nov 22 01:56:45 PM PST 23
Finished Nov 22 01:56:50 PM PST 23
Peak memory 203140 kb
Host smart-5559781e-87c8-4480-88d9-feb5f9e1dc99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78273732325532961171718146698568231759885555513307522678009731710490662986284 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 8.xbar_smoke.78273732325532961171718146698568231759885555513307522678009731710490662986284
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.44016875679582213511268544643310967157681297492054222109122874381771990392001
Short name T799
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.74 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:41 PM PST 23
Peak memory 203224 kb
Host smart-7504a875-2bec-4ae7-9f54-5fea37c21954
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=44016875679582213511268544643310967157681297492054222109122874381771990392001 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.44016875679582213511268544643310967157681297492054222109122874381771990392001
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.29152483705713135721410197660438508417619125980837549402643119348296698348817
Short name T270
Test name
Test status
Simulation time 17662295935 ps
CPU time 43.8 seconds
Started Nov 22 01:56:42 PM PST 23
Finished Nov 22 01:57:27 PM PST 23
Peak memory 203276 kb
Host smart-8fee697e-9780-41c7-8ab3-ad9853a5f510
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=29152483705713135721410197660438508417619125980837549402643119348296698348817 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.29152483705713135721410197660438508417619125980837549402643119348296698348817
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.84725226614170070383719749015862329065257170350209322909772054547020943239302
Short name T585
Test name
Test status
Simulation time 116233435 ps
CPU time 2.62 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:56:57 PM PST 23
Peak memory 203136 kb
Host smart-45e71dc5-58df-4a8f-8d60-cad87fe4eddd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84725226614170070383719749015862329065257170350209322909772054547020943239302 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.84725226614170070383719749015862329065257170350209322909772054547020943239302
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.113606487635598489446804434930976224265481500450288198611977782475906718865501
Short name T54
Test name
Test status
Simulation time 18904859184 ps
CPU time 134.58 seconds
Started Nov 22 01:56:50 PM PST 23
Finished Nov 22 01:59:05 PM PST 23
Peak memory 205796 kb
Host smart-d4e10b2b-6b89-4318-8f7b-7846b11660f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=113606487635598489446804434930976224265481500450288198611977782475906718865501 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 8.xbar_stress_all.113606487635598489446804434930976224265481500450288198611977782475906718865501
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.16108308671332238811291110614194103785427318495559792139910642163987288317750
Short name T161
Test name
Test status
Simulation time 18894549184 ps
CPU time 123.46 seconds
Started Nov 22 01:56:49 PM PST 23
Finished Nov 22 01:58:54 PM PST 23
Peak memory 211348 kb
Host smart-a0f6a4f5-84b8-4c25-b3bb-1d6168aa3603
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=16108308671332238811291110614194103785427318495559792139910642163987288317750 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 8.xbar_stress_all_with_error.16108308671332238811291110614194103785427318495559792139910642163987288317750
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.67474804017817204853811335096053858624627559480373816277680908308829633655566
Short name T603
Test name
Test status
Simulation time 5188549184 ps
CPU time 294.54 seconds
Started Nov 22 01:56:45 PM PST 23
Finished Nov 22 02:01:40 PM PST 23
Peak memory 208508 kb
Host smart-71ff4c89-005c-49e0-98d3-d0ed2f9f9d29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=67474804017817204853811335096053858624627559480373816277680908308829633655566 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.67474804017817204853811335096053858624627559480373816277680908308829633655566
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.40311953569843005673767947690432525823392121887827297327774513810308752628204
Short name T434
Test name
Test status
Simulation time 3307045935 ps
CPU time 27.67 seconds
Started Nov 22 01:56:48 PM PST 23
Finished Nov 22 01:57:17 PM PST 23
Peak memory 211348 kb
Host smart-a713b559-cc32-4f52-9a99-20ae64579289
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=40311953569843005673767947690432525823392121887827297327774513810308752628204 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 8.xbar_unmapped_addr.40311953569843005673767947690432525823392121887827297327774513810308752628204
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.71576588708673971858148740895899322343558796760509904935800041143879452433025
Short name T639
Test name
Test status
Simulation time 7399045935 ps
CPU time 63.35 seconds
Started Nov 22 01:56:53 PM PST 23
Finished Nov 22 01:57:58 PM PST 23
Peak memory 211456 kb
Host smart-9d793b53-bdce-4e19-98c8-8e0a04646ec5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71576588708673971858148740895899322343558796760509904935800041143879452433025 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode
.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.71576588708673971858148740895899322343558796760509904935800041143879452433025
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.83858242747227639361337815041551033962725685243075463580462593259813630714551
Short name T810
Test name
Test status
Simulation time 304288045935 ps
CPU time 778.44 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 02:09:55 PM PST 23
Peak memory 211332 kb
Host smart-a2b429bc-bfd0-4196-b260-1ded7f4e8554
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=83858242747227639361337815041551033962725685243075463580462593259813630714551 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_buil
d_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.83858242747227639361337815041551033962725685243075463580462593259813630714551
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.46168818934696676562057653945424819043973822902545568305765418251367678056140
Short name T870
Test name
Test status
Simulation time 3310545935 ps
CPU time 27.38 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 01:57:25 PM PST 23
Peak memory 203272 kb
Host smart-6493b6a7-cd78-4e29-8d1f-65737d6fa209
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=46168818934696676562057653945424819043973822902545568305765418251367678056140 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.46168818934696676562057653945424819043973822902545568305765418251367678056140
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.928832523884422042080223160189187066176878128322784620617208644142372844257
Short name T200
Test name
Test status
Simulation time 4402420935 ps
CPU time 32.88 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:57:32 PM PST 23
Peak memory 203276 kb
Host smart-40fe1cf4-ddf1-4985-9f6d-f5914bf68c98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=928832523884422042080223160189187066176878128322784620617208644142372844257 -assert nopostproc +UVM_TESTNAME=xba
r_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 9.xbar_error_random.928832523884422042080223160189187066176878128322784620617208644142372844257
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.1353165708982310649559736366496654169098455677061283223700937436610314141143
Short name T289
Test name
Test status
Simulation time 4402420935 ps
CPU time 37.18 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:30 PM PST 23
Peak memory 211444 kb
Host smart-c9581cd0-813d-4399-bdaa-413ffbaf8909
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1353165708982310649559736366496654169098455677061283223700937436610314141143 -assert nopostproc +UVM_TESTNAME=xb
ar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 9.xbar_random.1353165708982310649559736366496654169098455677061283223700937436610314141143
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.53591546817449572647141351941138357908803103520598158887609910810789065986844
Short name T339
Test name
Test status
Simulation time 188793233435 ps
CPU time 324.1 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 02:02:23 PM PST 23
Peak memory 204824 kb
Host smart-0f99174f-a626-4ffd-9612-22bc1859b3cf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=53591546817449572647141351941138357908803103520598158887609910810789065986844 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.v
db -cm_log /dev/null -cm_name 9.xbar_random_large_delays.53591546817449572647141351941138357908803103520598158887609910810789065986844
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.29986941869734533092890101442338969617275727186605800841406341219526949551934
Short name T771
Test name
Test status
Simulation time 126189108435 ps
CPU time 322.83 seconds
Started Nov 22 01:56:58 PM PST 23
Finished Nov 22 02:02:23 PM PST 23
Peak memory 211448 kb
Host smart-c6642230-bac0-4c7e-a64a-1555902e4f70
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=29986941869734533092890101442338969617275727186605800841406341219526949551934 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -
cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.29986941869734533092890101442338969617275727186605800841406341219526949551934
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.6370823308345896701708803081997339204647381937401402950239843347805917033904
Short name T834
Test name
Test status
Simulation time 766920935 ps
CPU time 26.17 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:57:19 PM PST 23
Peak memory 211272 kb
Host smart-4a1ad07b-bb51-40e9-bd6c-5e706edc5876
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6370823308345896701708803081997339204647381937401402950239843347805917033904 -assert nopostproc +
UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mo
de.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.6370823308345896701708803081997339204647381937401402950239843347805917033904
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.33658324108113517285454544993379039875437128990392694746806923523548534664680
Short name T596
Test name
Test status
Simulation time 7116170935 ps
CPU time 37.5 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:33 PM PST 23
Peak memory 204332 kb
Host smart-2442e110-c95b-48ab-88ac-c35ae016654e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=33658324108113517285454544993379039875437128990392694746806923523548534664680 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 9.xbar_same_source.33658324108113517285454544993379039875437128990392694746806923523548534664680
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.110652087091872761578278453367124973599127425428623874694294197134593127203747
Short name T461
Test name
Test status
Simulation time 669983435 ps
CPU time 4.05 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 01:57:03 PM PST 23
Peak memory 203120 kb
Host smart-93e0db55-b647-4d82-bbb9-266936d5c50d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110652087091872761578278453367124973599127425428623874694294197134593127203747 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log
/dev/null -cm_name 9.xbar_smoke.110652087091872761578278453367124973599127425428623874694294197134593127203747
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.77916692711577721039721535855559095911401253698046839791502972167273651689631
Short name T149
Test name
Test status
Simulation time 28419483435 ps
CPU time 47.77 seconds
Started Nov 22 01:56:47 PM PST 23
Finished Nov 22 01:57:37 PM PST 23
Peak memory 203204 kb
Host smart-de045e2b-75cf-417c-ac91-e3442d7d7118
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=77916692711577721039721535855559095911401253698046839791502972167273651689631 -assert nopostproc +UVM_
TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vd
b -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.77916692711577721039721535855559095911401253698046839791502972167273651689631
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.43928048894936147896352298127451768629872399580121521481127560071444731048616
Short name T542
Test name
Test status
Simulation time 17662295935 ps
CPU time 45.69 seconds
Started Nov 22 01:56:55 PM PST 23
Finished Nov 22 01:57:43 PM PST 23
Peak memory 203276 kb
Host smart-16968525-11cc-432c-9b23-eb6e3fbe3800
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=43928048894936147896352298127451768629872399580121521481127560071444731048616 -assert nopostproc +UVM_TEST
NAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.43928048894936147896352298127451768629872399580121521481127560071444731048616
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.100040184052480525100435700655673908936844404623928655747336512792555023749701
Short name T102
Test name
Test status
Simulation time 116233435 ps
CPU time 2.56 seconds
Started Nov 22 01:56:52 PM PST 23
Finished Nov 22 01:56:55 PM PST 23
Peak memory 203152 kb
Host smart-6c4c9af9-f1eb-4b7d-84f2-d1c3bfd7dd12
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100040184052480525100435700655673908936844404623928655747336512792555023749701 -assert nopostproc
+UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_m
ode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.100040184052480525100435700655673908936844404623928655747336512792555023749701
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.115553642322259547401694464867060135803873966288579745096864195026797484332337
Short name T579
Test name
Test status
Simulation time 18904859184 ps
CPU time 137.9 seconds
Started Nov 22 01:56:57 PM PST 23
Finished Nov 22 01:59:17 PM PST 23
Peak memory 205848 kb
Host smart-78d729d5-0749-4774-9872-0ffd1a140121
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=115553642322259547401694464867060135803873966288579745096864195026797484332337 -assert nopostproc +UVM_TESTNAME=
xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 9.xbar_stress_all.115553642322259547401694464867060135803873966288579745096864195026797484332337
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.20305573546218396538481157746140466784198726805017262473471362529096938777921
Short name T284
Test name
Test status
Simulation time 18894549184 ps
CPU time 125.54 seconds
Started Nov 22 01:56:56 PM PST 23
Finished Nov 22 01:59:04 PM PST 23
Peak memory 211404 kb
Host smart-d832254d-a03d-41c6-ab0a-927b625aee2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20305573546218396538481157746140466784198726805017262473471362529096938777921 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -c
m_log /dev/null -cm_name 9.xbar_stress_all_with_error.20305573546218396538481157746140466784198726805017262473471362529096938777921
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.61784516150035825269372193281200618488431602495479923809134434268056985306986
Short name T819
Test name
Test status
Simulation time 5188549184 ps
CPU time 297.36 seconds
Started Nov 22 01:56:58 PM PST 23
Finished Nov 22 02:01:57 PM PST 23
Peak memory 208508 kb
Host smart-d201270c-d794-41d7-8122-e52805431f7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=61784516150035825269372193281200618488431602495479923809134434268056985306986 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_bu
ild_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.61784516150035825269372193281200618488431602495479923809134434268056985306986
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.24250824564108948700326499374457346309851023163925773644368944161051102019022
Short name T626
Test name
Test status
Simulation time 5188549184 ps
CPU time 222.91 seconds
Started Nov 22 01:57:05 PM PST 23
Finished Nov 22 02:00:49 PM PST 23
Peak memory 219524 kb
Host smart-4526eb05-6f52-41b0-92f8-95199121269d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=24250824564108948700326499374457346309851023163925773644368944161051102019022 -assert nopostproc +UVM_TESTNAME=x
bar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_b
uild_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.24250824564108948700326499374457346309851023163925773644368944161051102019022
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.74631801756044922695433451413627818841551249152780808602294213157893843130053
Short name T450
Test name
Test status
Simulation time 3307045935 ps
CPU time 28.39 seconds
Started Nov 22 01:56:54 PM PST 23
Finished Nov 22 01:57:24 PM PST 23
Peak memory 211388 kb
Host smart-c470cdb5-155c-4517-9574-0333ab7e072d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=74631801756044922695433451413627818841551249152780808602294213157893843130053 -assert nopostproc +UVM_TESTNAME=x
bar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb
-cm_log /dev/null -cm_name 9.xbar_unmapped_addr.74631801756044922695433451413627818841551249152780808602294213157893843130053
Directory /workspace/9.xbar_unmapped_addr/latest
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