Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1783	1			T1	6		T6	16		T20	2
all_values[1]	1727	1			T1	4		T6	16		T20	1
all_values[2]	1679	1			T1	1		T6	19		T20	1
all_values[3]	1767	1			T1	4		T6	12		T20	3
all_values[4]	1738	1			T1	4		T6	16		T20	4
all_values[5]	1744	1			T1	3		T6	12		T20	4
all_values[6]	1763	1			T1	3		T6	12		T20	2
all_values[7]	1767	1			T1	3		T6	13		T20	3
all_values[8]	1744	1			T1	6		T6	19		T20	2
all_values[9]	1697	1			T1	1		T6	23		T20	2
all_values[10]	1798	1			T1	4		T6	12		T12	4
all_values[11]	1683	1			T1	4		T6	17		T20	2
all_values[12]	1762	1			T6	20		T20	2		T12	3
all_values[13]	1657	1			T1	5		T6	21		T20	4
all_values[14]	1780	1			T1	6		T6	14		T20	1
all_values[15]	1676	1			T1	3		T6	12		T20	2
all_values[16]	1754	1			T1	1		T6	22		T20	1
all_values[17]	1697	1			T1	2		T6	12		T20	3
all_values[18]	1698	1			T1	2		T6	16		T20	2
all_values[19]	1718	1			T6	14		T20	1		T12	3
all_values[20]	1677	1			T6	13		T12	6		T13	4
all_values[21]	1684	1			T1	3		T6	19		T20	1
all_values[22]	1713	1			T1	3		T6	13		T20	4
all_values[23]	1756	1			T1	1		T6	13		T20	3
all_values[24]	1754	1			T1	5		T6	15		T20	3
all_values[25]	1771	1			T1	1		T6	13		T12	5
all_values[26]	1728	1			T1	3		T6	15		T20	1
all_values[27]	1834	1			T1	1		T6	25		T20	4
all_values[28]	1694	1			T1	4		T6	18		T12	5
all_values[29]	1674	1			T1	5		T6	18		T20	1
all_values[30]	1752	1			T1	1		T6	20		T20	3
all_values[31]	1661	1			T1	2		T6	23		T20	1
all_values[32]	1733	1			T1	4		T6	14		T20	1
all_values[33]	1740	1			T1	3		T6	21		T20	3
all_values[34]	1710	1			T1	4		T6	14		T12	5
all_values[35]	1736	1			T1	5		T6	15		T20	1
all_values[36]	1756	1			T1	3		T6	14		T20	2
all_values[37]	1643	1			T1	4		T6	14		T20	1
all_values[38]	1711	1			T1	6		T6	18		T20	1
all_values[39]	1725	1			T6	14		T20	3		T12	6
all_values[40]	1702	1			T1	4		T6	20		T20	1
all_values[41]	1834	1			T1	4		T6	15		T20	1
all_values[42]	1699	1			T1	1		T6	16		T20	2
all_values[43]	1681	1			T1	3		T6	17		T20	1
all_values[44]	1783	1			T1	2		T6	15		T20	1
all_values[45]	1720	1			T1	4		T6	16		T20	2
all_values[46]	1723	1			T1	5		T6	22		T20	2
all_values[47]	1728	1			T1	4		T6	14		T12	4
all_values[48]	1719	1			T1	4		T6	20		T12	3
all_values[49]	1678	1			T1	3		T6	14		T12	7
all_values[50]	1720	1			T1	2		T6	16		T12	3
all_values[51]	1729	1			T1	2		T6	14		T20	1
all_values[52]	1692	1			T1	3		T6	15		T20	5
all_values[53]	1675	1			T1	3		T6	19		T20	1
all_values[54]	1697	1			T1	2		T6	19		T20	2
all_values[55]	1748	1			T1	7		T6	14		T20	2
all_values[56]	1725	1			T1	3		T6	10		T20	3
all_values[57]	1714	1			T1	1		T6	13		T20	1
all_values[58]	1721	1			T1	3		T6	25		T20	3
all_values[59]	1635	1			T1	2		T6	24		T20	2
all_values[60]	1751	1			T1	2		T6	14		T20	1
all_values[61]	1781	1			T1	3		T6	15		T20	2
all_values[62]	1693	1			T1	4		T6	23		T20	1
all_values[63]	1710	1			T1	2		T6	10		T20	2