Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2004	1			T1	2		T3	1		T6	26
all_values[1]	1922	1			T1	4		T3	2		T6	31
all_values[2]	1822	1			T1	2		T6	32		T9	1
all_values[3]	1831	1			T1	3		T3	3		T6	28
all_values[4]	1859	1			T1	2		T3	1		T6	26
all_values[5]	1867	1			T1	2		T3	2		T6	27
all_values[6]	1852	1			T1	3		T3	2		T6	27
all_values[7]	1836	1			T1	2		T3	2		T6	29
all_values[8]	1878	1			T1	1		T3	2		T6	27
all_values[9]	1830	1			T3	1		T6	24		T9	3
all_values[10]	1842	1			T1	3		T3	3		T6	31
all_values[11]	1835	1			T1	1		T3	4		T6	26
all_values[12]	1866	1			T1	1		T6	24		T7	1
all_values[13]	1879	1			T1	3		T3	1		T6	25
all_values[14]	1876	1			T1	1		T3	3		T6	31
all_values[15]	1847	1			T3	2		T6	22		T9	4
all_values[16]	1866	1			T1	4		T3	1		T6	19
all_values[17]	1936	1			T3	3		T6	25		T9	4
all_values[18]	1769	1			T3	2		T6	36		T9	3
all_values[19]	1872	1			T6	31		T10	5		T13	1
all_values[20]	1895	1			T6	23		T7	2		T9	2
all_values[21]	1842	1			T1	3		T3	2		T6	20
all_values[22]	1810	1			T1	2		T6	22		T9	3
all_values[23]	1923	1			T1	4		T6	29		T9	2
all_values[24]	1861	1			T1	4		T3	2		T6	29
all_values[25]	1840	1			T1	1		T3	1		T6	32
all_values[26]	1800	1			T1	5		T3	1		T6	26
all_values[27]	1807	1			T1	2		T6	33		T9	1
all_values[28]	1897	1			T1	1		T3	2		T6	31
all_values[29]	1855	1			T1	3		T3	3		T6	20
all_values[30]	1901	1			T1	1		T6	15		T7	1
all_values[31]	1902	1			T1	2		T3	1		T6	25
all_values[32]	1914	1			T1	3		T6	34		T9	2
all_values[33]	1801	1			T1	1		T3	1		T6	30
all_values[34]	1863	1			T1	1		T3	1		T6	30
all_values[35]	1792	1			T1	3		T3	2		T6	18
all_values[36]	1836	1			T1	1		T3	1		T6	18
all_values[37]	1869	1			T1	5		T3	5		T6	32
all_values[38]	1928	1			T1	1		T3	3		T6	26
all_values[39]	1870	1			T1	1		T3	1		T6	27
all_values[40]	1940	1			T1	2		T6	27		T10	8
all_values[41]	1784	1			T3	2		T6	21		T10	3
all_values[42]	1805	1			T1	1		T3	3		T6	26
all_values[43]	1787	1			T1	3		T3	2		T6	19
all_values[44]	1809	1			T1	2		T3	4		T6	22
all_values[45]	1869	1			T3	1		T6	30		T7	1
all_values[46]	1817	1			T1	2		T3	1		T6	21
all_values[47]	1832	1			T1	5		T3	1		T6	29
all_values[48]	1877	1			T3	2		T6	30		T9	2
all_values[49]	1900	1			T1	2		T3	1		T6	25
all_values[50]	1911	1			T1	2		T3	1		T6	24
all_values[51]	1865	1			T1	1		T3	1		T6	32
all_values[52]	1844	1			T1	1		T6	32		T7	1
all_values[53]	1850	1			T1	2		T6	27		T9	4
all_values[54]	1765	1			T1	1		T6	20		T9	2
all_values[55]	1835	1			T1	1		T3	1		T6	22
all_values[56]	1895	1			T1	2		T3	3		T6	33
all_values[57]	1904	1			T1	2		T3	2		T6	28
all_values[58]	1835	1			T1	5		T3	2		T6	29
all_values[59]	1857	1			T1	1		T6	22		T9	1
all_values[60]	1946	1			T1	1		T6	34		T9	3
all_values[61]	1910	1			T1	2		T3	1		T6	31
all_values[62]	1931	1			T1	2		T3	1		T6	26
all_values[63]	1873	1			T1	2		T3	3		T6	23