Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1621	1			T4	9		T6	1		T8	3
all_values[1]	1564	1			T4	9		T5	2		T6	2
all_values[2]	1616	1			T4	17		T5	1		T6	3
all_values[3]	1690	1			T4	6		T5	3		T6	1
all_values[4]	1614	1			T4	12		T5	3		T6	1
all_values[5]	1545	1			T4	7		T6	1		T8	1
all_values[6]	1683	1			T4	9		T5	1		T8	1
all_values[7]	1629	1			T4	6		T5	1		T6	1
all_values[8]	1620	1			T4	11		T5	7		T8	2
all_values[9]	1591	1			T4	13		T5	3		T6	1
all_values[10]	1591	1			T4	8		T5	1		T6	1
all_values[11]	1713	1			T4	11		T5	5		T8	1
all_values[12]	1632	1			T4	17		T5	1		T28	6
all_values[13]	1614	1			T4	12		T5	2		T8	1
all_values[14]	1601	1			T4	7		T5	2		T6	1
all_values[15]	1659	1			T4	3		T5	2		T8	4
all_values[16]	1544	1			T4	11		T5	2		T28	9
all_values[17]	1683	1			T4	12		T5	1		T6	1
all_values[18]	1639	1			T4	8		T5	2		T28	10
all_values[19]	1699	1			T4	8		T5	4		T6	2
all_values[20]	1584	1			T4	13		T5	2		T28	5
all_values[21]	1600	1			T4	16		T5	1		T6	2
all_values[22]	1624	1			T4	9		T5	2		T8	2
all_values[23]	1639	1			T4	7		T5	4		T6	1
all_values[24]	1730	1			T4	11		T5	1		T28	5
all_values[25]	1643	1			T4	8		T5	3		T6	1
all_values[26]	1553	1			T4	8		T5	1		T28	9
all_values[27]	1646	1			T4	11		T5	4		T28	5
all_values[28]	1627	1			T4	5		T5	1		T28	6
all_values[29]	1605	1			T4	10		T5	1		T6	1
all_values[30]	1612	1			T4	6		T5	2		T6	1
all_values[31]	1666	1			T4	8		T5	7		T28	6
all_values[32]	1657	1			T4	14		T5	3		T6	1
all_values[33]	1638	1			T4	3		T5	4		T6	1
all_values[34]	1661	1			T4	11		T5	4		T6	1
all_values[35]	1641	1			T4	5		T5	1		T6	1
all_values[36]	1707	1			T4	8		T5	3		T6	1
all_values[37]	1595	1			T4	9		T28	7		T14	14
all_values[38]	1622	1			T4	10		T5	2		T6	1
all_values[39]	1618	1			T4	10		T5	2		T6	1
all_values[40]	1578	1			T4	9		T5	3		T6	1
all_values[41]	1596	1			T4	6		T5	2		T6	1
all_values[42]	1617	1			T4	11		T5	3		T8	2
all_values[43]	1660	1			T4	13		T5	3		T28	6
all_values[44]	1596	1			T4	6		T5	2		T6	1
all_values[45]	1606	1			T4	7		T5	1		T6	1
all_values[46]	1626	1			T4	8		T5	3		T6	1
all_values[47]	1666	1			T4	11		T5	1		T8	1
all_values[48]	1528	1			T4	7		T5	2		T8	1
all_values[49]	1571	1			T4	10		T5	4		T6	4
all_values[50]	1507	1			T4	5		T5	2		T8	2
all_values[51]	1630	1			T4	7		T5	2		T6	1
all_values[52]	1657	1			T4	15		T5	2		T6	1
all_values[53]	1577	1			T4	6		T5	3		T6	2
all_values[54]	1616	1			T4	11		T8	3		T28	7
all_values[55]	1616	1			T4	10		T5	1		T8	2
all_values[56]	1676	1			T4	13		T5	2		T6	1
all_values[57]	1631	1			T4	8		T5	1		T8	1
all_values[58]	1615	1			T4	13		T5	2		T8	1
all_values[59]	1701	1			T4	7		T5	2		T6	1
all_values[60]	1682	1			T4	9		T6	1		T28	8
all_values[61]	1656	1			T4	6		T5	2		T6	1
all_values[62]	1631	1			T4	6		T5	2		T6	1
all_values[63]	1657	1			T4	15		T5	2		T28	10