Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.73 98.53 90.07 98.80 93.72 99.26 100.00


Total test records in report: 875
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T763 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1198531955 Dec 27 12:28:25 PM PST 23 Dec 27 12:39:53 PM PST 23 16483357351 ps
T764 /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.413863709 Dec 27 12:28:57 PM PST 23 Dec 27 12:30:02 PM PST 23 270760097 ps
T765 /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.690731145 Dec 27 12:27:30 PM PST 23 Dec 27 12:32:53 PM PST 23 72752212380 ps
T766 /workspace/coverage/xbar_build_mode/20.xbar_smoke.3912526347 Dec 27 12:28:21 PM PST 23 Dec 27 12:29:10 PM PST 23 173157380 ps
T767 /workspace/coverage/xbar_build_mode/49.xbar_error_random.2259042160 Dec 27 12:32:00 PM PST 23 Dec 27 12:33:05 PM PST 23 703598198 ps
T768 /workspace/coverage/xbar_build_mode/13.xbar_random.940058263 Dec 27 12:27:52 PM PST 23 Dec 27 12:29:02 PM PST 23 1454362091 ps
T245 /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.4010415640 Dec 27 12:30:09 PM PST 23 Dec 27 12:34:18 PM PST 23 44780995552 ps
T769 /workspace/coverage/xbar_build_mode/19.xbar_smoke.2606293004 Dec 27 12:27:50 PM PST 23 Dec 27 12:28:24 PM PST 23 42210109 ps
T770 /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3638031982 Dec 27 12:27:21 PM PST 23 Dec 27 12:28:11 PM PST 23 4486477283 ps
T771 /workspace/coverage/xbar_build_mode/21.xbar_error_random.731170336 Dec 27 12:27:56 PM PST 23 Dec 27 12:28:46 PM PST 23 570986350 ps
T772 /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2137015581 Dec 27 12:28:12 PM PST 23 Dec 27 12:29:07 PM PST 23 139759285 ps
T773 /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3530867737 Dec 27 12:30:12 PM PST 23 Dec 27 12:32:48 PM PST 23 28081193215 ps
T774 /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3146606269 Dec 27 12:28:06 PM PST 23 Dec 27 12:29:11 PM PST 23 21672466542 ps
T775 /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3193453809 Dec 27 12:28:04 PM PST 23 Dec 27 12:29:26 PM PST 23 22240761005 ps
T776 /workspace/coverage/xbar_build_mode/11.xbar_smoke.2780414697 Dec 27 12:28:25 PM PST 23 Dec 27 12:29:15 PM PST 23 166306941 ps
T777 /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.197378451 Dec 27 12:29:27 PM PST 23 Dec 27 12:31:16 PM PST 23 2358427336 ps
T778 /workspace/coverage/xbar_build_mode/33.xbar_smoke.2952909034 Dec 27 12:28:24 PM PST 23 Dec 27 12:29:13 PM PST 23 38022485 ps
T779 /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.4292074588 Dec 27 12:28:54 PM PST 23 Dec 27 12:29:55 PM PST 23 736586707 ps
T780 /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1111656514 Dec 27 12:28:35 PM PST 23 Dec 27 12:30:33 PM PST 23 342577660 ps
T781 /workspace/coverage/xbar_build_mode/19.xbar_random.2643038257 Dec 27 12:27:45 PM PST 23 Dec 27 12:28:37 PM PST 23 763926400 ps
T782 /workspace/coverage/xbar_build_mode/2.xbar_random.3992871461 Dec 27 12:20:32 PM PST 23 Dec 27 12:20:44 PM PST 23 512401223 ps
T783 /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2996978707 Dec 27 12:28:50 PM PST 23 Dec 27 12:29:45 PM PST 23 54463473 ps
T784 /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3203618397 Dec 27 12:28:47 PM PST 23 Dec 27 12:33:18 PM PST 23 530867252 ps
T127 /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1340720611 Dec 27 12:27:22 PM PST 23 Dec 27 12:38:18 PM PST 23 145247252532 ps
T785 /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2629156279 Dec 27 12:28:31 PM PST 23 Dec 27 12:30:09 PM PST 23 7335396770 ps
T22 /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3090816786 Dec 27 12:28:04 PM PST 23 Dec 27 12:31:59 PM PST 23 16400894962 ps
T786 /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2227647412 Dec 27 12:29:34 PM PST 23 Dec 27 12:32:12 PM PST 23 2271888516 ps
T787 /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.539757359 Dec 27 12:28:12 PM PST 23 Dec 27 12:28:56 PM PST 23 191374089 ps
T788 /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2902121091 Dec 27 12:20:21 PM PST 23 Dec 27 12:22:45 PM PST 23 525634180 ps
T789 /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2694583272 Dec 27 12:29:52 PM PST 23 Dec 27 12:31:16 PM PST 23 9159798079 ps
T128 /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2919929959 Dec 27 12:27:51 PM PST 23 Dec 27 12:31:36 PM PST 23 21708812144 ps
T790 /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.546273689 Dec 27 12:26:58 PM PST 23 Dec 27 12:28:01 PM PST 23 446377836 ps
T791 /workspace/coverage/xbar_build_mode/16.xbar_stress_all.982215056 Dec 27 12:27:47 PM PST 23 Dec 27 12:30:18 PM PST 23 8542071275 ps
T33 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1370205035 Dec 27 12:28:11 PM PST 23 Dec 27 12:32:33 PM PST 23 7263174471 ps
T792 /workspace/coverage/xbar_build_mode/21.xbar_random.3129271743 Dec 27 12:28:05 PM PST 23 Dec 27 12:29:04 PM PST 23 271290493 ps
T793 /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1692377279 Dec 27 12:27:53 PM PST 23 Dec 27 12:29:18 PM PST 23 2526910854 ps
T794 /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.691481588 Dec 27 12:29:11 PM PST 23 Dec 27 12:30:49 PM PST 23 1508179500 ps
T795 /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3212429278 Dec 27 12:31:38 PM PST 23 Dec 27 12:35:34 PM PST 23 147948265116 ps
T796 /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3788417618 Dec 27 12:29:42 PM PST 23 Dec 27 12:32:41 PM PST 23 31866366324 ps
T797 /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1175757707 Dec 27 12:26:08 PM PST 23 Dec 27 12:27:39 PM PST 23 26352174041 ps
T798 /workspace/coverage/xbar_build_mode/18.xbar_stress_all.814276103 Dec 27 12:28:05 PM PST 23 Dec 27 12:29:49 PM PST 23 814790640 ps
T799 /workspace/coverage/xbar_build_mode/37.xbar_smoke.2582521514 Dec 27 12:28:42 PM PST 23 Dec 27 12:29:38 PM PST 23 111193313 ps
T800 /workspace/coverage/xbar_build_mode/30.xbar_error_random.3603994549 Dec 27 12:28:22 PM PST 23 Dec 27 12:29:15 PM PST 23 196225233 ps
T801 /workspace/coverage/xbar_build_mode/20.xbar_same_source.2874998282 Dec 27 12:28:19 PM PST 23 Dec 27 12:29:19 PM PST 23 2691914639 ps
T802 /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2970624871 Dec 27 12:29:42 PM PST 23 Dec 27 12:30:52 PM PST 23 386844690 ps
T803 /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.733456295 Dec 27 12:28:04 PM PST 23 Dec 27 12:29:24 PM PST 23 401096128 ps
T804 /workspace/coverage/xbar_build_mode/20.xbar_stress_all.890519648 Dec 27 12:28:02 PM PST 23 Dec 27 12:31:05 PM PST 23 14177636742 ps
T805 /workspace/coverage/xbar_build_mode/21.xbar_same_source.20927992 Dec 27 12:27:50 PM PST 23 Dec 27 12:28:39 PM PST 23 709309754 ps
T806 /workspace/coverage/xbar_build_mode/9.xbar_smoke.2756073217 Dec 27 12:27:24 PM PST 23 Dec 27 12:27:55 PM PST 23 127816632 ps
T807 /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1935029721 Dec 27 12:30:09 PM PST 23 Dec 27 12:31:25 PM PST 23 936690260 ps
T808 /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.266731206 Dec 27 12:26:16 PM PST 23 Dec 27 12:26:47 PM PST 23 752203807 ps
T809 /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3250855975 Dec 27 12:28:41 PM PST 23 Dec 27 12:30:03 PM PST 23 4904118644 ps
T810 /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.764599035 Dec 27 12:28:45 PM PST 23 Dec 27 12:35:14 PM PST 23 49836242066 ps
T811 /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1880841673 Dec 27 12:20:17 PM PST 23 Dec 27 12:20:54 PM PST 23 9466320206 ps
T201 /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.639901022 Dec 27 12:28:53 PM PST 23 Dec 27 12:30:15 PM PST 23 233608521 ps
T812 /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3785022497 Dec 27 12:24:48 PM PST 23 Dec 27 12:25:14 PM PST 23 2297989770 ps
T813 /workspace/coverage/xbar_build_mode/37.xbar_random.1268497907 Dec 27 12:28:31 PM PST 23 Dec 27 12:29:43 PM PST 23 813267662 ps
T814 /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2194136259 Dec 27 12:28:25 PM PST 23 Dec 27 12:29:43 PM PST 23 14407038467 ps
T187 /workspace/coverage/xbar_build_mode/18.xbar_same_source.1289890739 Dec 27 12:27:51 PM PST 23 Dec 27 12:28:46 PM PST 23 2983584657 ps
T815 /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2709003309 Dec 27 12:28:59 PM PST 23 Dec 27 12:36:54 PM PST 23 3020260521 ps
T816 /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3495916719 Dec 27 12:28:04 PM PST 23 Dec 27 12:28:53 PM PST 23 800872925 ps
T817 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3404030467 Dec 27 12:27:45 PM PST 23 Dec 27 12:30:32 PM PST 23 24755318050 ps
T818 /workspace/coverage/xbar_build_mode/43.xbar_same_source.1560826724 Dec 27 12:29:04 PM PST 23 Dec 27 12:30:10 PM PST 23 1424508810 ps
T819 /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1967639953 Dec 27 12:29:41 PM PST 23 Dec 27 12:31:02 PM PST 23 303344136 ps
T820 /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.791235268 Dec 27 12:29:36 PM PST 23 Dec 27 12:40:19 PM PST 23 92375589263 ps
T821 /workspace/coverage/xbar_build_mode/14.xbar_same_source.3980759684 Dec 27 12:27:30 PM PST 23 Dec 27 12:28:12 PM PST 23 627326528 ps
T822 /workspace/coverage/xbar_build_mode/28.xbar_same_source.3405589726 Dec 27 12:30:26 PM PST 23 Dec 27 12:31:24 PM PST 23 106680302 ps
T823 /workspace/coverage/xbar_build_mode/42.xbar_error_random.2559976811 Dec 27 12:28:43 PM PST 23 Dec 27 12:29:44 PM PST 23 73639321 ps
T824 /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1649187460 Dec 27 12:26:32 PM PST 23 Dec 27 12:27:10 PM PST 23 3634398974 ps
T825 /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2328539199 Dec 27 12:31:57 PM PST 23 Dec 27 12:33:08 PM PST 23 7919311662 ps
T826 /workspace/coverage/xbar_build_mode/46.xbar_same_source.3227266454 Dec 27 12:29:49 PM PST 23 Dec 27 12:31:03 PM PST 23 1372049310 ps
T827 /workspace/coverage/xbar_build_mode/33.xbar_error_random.1198898377 Dec 27 12:28:48 PM PST 23 Dec 27 12:30:16 PM PST 23 3070858760 ps
T828 /workspace/coverage/xbar_build_mode/23.xbar_smoke.3149486675 Dec 27 12:28:05 PM PST 23 Dec 27 12:28:41 PM PST 23 30063709 ps
T829 /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2084380190 Dec 27 12:28:00 PM PST 23 Dec 27 12:30:26 PM PST 23 365997420 ps
T830 /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.113226963 Dec 27 12:28:55 PM PST 23 Dec 27 12:38:50 PM PST 23 65716530995 ps
T831 /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3517778092 Dec 27 12:28:06 PM PST 23 Dec 27 12:28:44 PM PST 23 30322911 ps
T832 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3105840059 Dec 27 12:22:19 PM PST 23 Dec 27 12:26:30 PM PST 23 24381670395 ps
T833 /workspace/coverage/xbar_build_mode/48.xbar_same_source.3056482358 Dec 27 12:29:11 PM PST 23 Dec 27 12:30:15 PM PST 23 514500086 ps
T202 /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1694594631 Dec 27 12:28:56 PM PST 23 Dec 27 12:30:26 PM PST 23 357650957 ps
T834 /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1019252662 Dec 27 12:23:23 PM PST 23 Dec 27 12:24:46 PM PST 23 272880983 ps
T140 /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3826675560 Dec 27 12:26:13 PM PST 23 Dec 27 12:26:40 PM PST 23 2371216928 ps
T835 /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.705394278 Dec 27 12:29:49 PM PST 23 Dec 27 12:33:17 PM PST 23 9392275157 ps
T836 /workspace/coverage/xbar_build_mode/32.xbar_same_source.3184045129 Dec 27 12:28:25 PM PST 23 Dec 27 12:29:38 PM PST 23 5146475729 ps
T837 /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2819325082 Dec 27 12:29:24 PM PST 23 Dec 27 12:30:48 PM PST 23 6246734009 ps
T838 /workspace/coverage/xbar_build_mode/15.xbar_stress_all.2490585327 Dec 27 12:27:37 PM PST 23 Dec 27 12:30:35 PM PST 23 13702888265 ps
T839 /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.893119353 Dec 27 12:24:37 PM PST 23 Dec 27 12:25:13 PM PST 23 44689218 ps
T840 /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3002846498 Dec 27 12:27:21 PM PST 23 Dec 27 12:28:14 PM PST 23 1053320890 ps
T841 /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1151321183 Dec 27 12:27:57 PM PST 23 Dec 27 12:30:25 PM PST 23 14529815223 ps
T842 /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3166986201 Dec 27 12:30:06 PM PST 23 Dec 27 12:32:57 PM PST 23 18490799773 ps
T843 /workspace/coverage/xbar_build_mode/23.xbar_error_random.3805618778 Dec 27 12:28:03 PM PST 23 Dec 27 12:28:47 PM PST 23 280953707 ps
T844 /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3671835264 Dec 27 12:27:57 PM PST 23 Dec 27 12:28:33 PM PST 23 30049517 ps
T845 /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1197025924 Dec 27 12:29:35 PM PST 23 Dec 27 12:31:32 PM PST 23 528133420 ps
T846 /workspace/coverage/xbar_build_mode/35.xbar_error_random.2084195187 Dec 27 12:28:29 PM PST 23 Dec 27 12:29:28 PM PST 23 537851549 ps
T847 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.390021696 Dec 27 12:29:10 PM PST 23 Dec 27 12:30:42 PM PST 23 522570206 ps
T848 /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3171429387 Dec 27 12:29:07 PM PST 23 Dec 27 12:33:17 PM PST 23 28926694068 ps
T849 /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2381888157 Dec 27 12:28:25 PM PST 23 Dec 27 12:29:41 PM PST 23 5291867506 ps
T850 /workspace/coverage/xbar_build_mode/2.xbar_same_source.3631220758 Dec 27 12:25:44 PM PST 23 Dec 27 12:25:58 PM PST 23 475372556 ps
T851 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.866771260 Dec 27 12:28:07 PM PST 23 Dec 27 12:29:10 PM PST 23 443515196 ps
T852 /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1315923301 Dec 27 12:27:53 PM PST 23 Dec 27 12:33:09 PM PST 23 59153176889 ps
T853 /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1927715768 Dec 27 12:26:52 PM PST 23 Dec 27 12:27:15 PM PST 23 25321766 ps
T854 /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2349194582 Dec 27 12:28:50 PM PST 23 Dec 27 12:30:09 PM PST 23 4720277268 ps
T855 /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1320508528 Dec 27 12:29:23 PM PST 23 Dec 27 12:30:20 PM PST 23 57635091 ps
T856 /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1637476703 Dec 27 12:27:53 PM PST 23 Dec 27 12:28:56 PM PST 23 6616990248 ps
T857 /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1757713388 Dec 27 12:28:53 PM PST 23 Dec 27 12:30:18 PM PST 23 6184761082 ps
T141 /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3184612305 Dec 27 12:29:28 PM PST 23 Dec 27 12:41:37 PM PST 23 149391771105 ps
T858 /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3109432007 Dec 27 12:27:59 PM PST 23 Dec 27 12:37:40 PM PST 23 93367223914 ps
T66 /workspace/coverage/xbar_build_mode/40.xbar_random.625245855 Dec 27 12:28:44 PM PST 23 Dec 27 12:29:48 PM PST 23 380516881 ps
T859 /workspace/coverage/xbar_build_mode/13.xbar_stress_all.775362297 Dec 27 12:29:10 PM PST 23 Dec 27 12:31:35 PM PST 23 705365727 ps
T860 /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.288394617 Dec 27 12:27:31 PM PST 23 Dec 27 12:30:35 PM PST 23 18478174815 ps
T861 /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3476909548 Dec 27 12:28:53 PM PST 23 Dec 27 12:29:49 PM PST 23 81773305 ps
T862 /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1906804719 Dec 27 12:29:09 PM PST 23 Dec 27 12:33:31 PM PST 23 11005640386 ps
T863 /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4104345037 Dec 27 12:21:02 PM PST 23 Dec 27 12:21:24 PM PST 23 844795203 ps
T864 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3515404912 Dec 27 12:28:11 PM PST 23 Dec 27 12:30:26 PM PST 23 1696888873 ps
T865 /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2205770043 Dec 27 12:28:37 PM PST 23 Dec 27 12:29:56 PM PST 23 9535993386 ps
T866 /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.599576297 Dec 27 12:32:11 PM PST 23 Dec 27 12:33:15 PM PST 23 205954247 ps
T867 /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.597561174 Dec 27 12:28:36 PM PST 23 Dec 27 12:39:36 PM PST 23 172856289552 ps
T142 /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3091152698 Dec 27 12:28:15 PM PST 23 Dec 27 12:30:01 PM PST 23 2667333353 ps
T868 /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.8457972 Dec 27 12:29:46 PM PST 23 Dec 27 12:31:09 PM PST 23 7348255546 ps
T869 /workspace/coverage/xbar_build_mode/0.xbar_random.3827230112 Dec 27 12:24:59 PM PST 23 Dec 27 12:25:23 PM PST 23 1891591762 ps
T870 /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4223989740 Dec 27 12:28:53 PM PST 23 Dec 27 12:29:49 PM PST 23 52258102 ps
T871 /workspace/coverage/xbar_build_mode/29.xbar_smoke.1591276722 Dec 27 12:28:11 PM PST 23 Dec 27 12:28:52 PM PST 23 39010682 ps
T872 /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1915592425 Dec 27 12:28:04 PM PST 23 Dec 27 12:28:48 PM PST 23 401133065 ps
T873 /workspace/coverage/xbar_build_mode/49.xbar_stress_all.2322979353 Dec 27 12:29:04 PM PST 23 Dec 27 12:34:36 PM PST 23 33321361010 ps
T874 /workspace/coverage/xbar_build_mode/46.xbar_error_random.51225966 Dec 27 12:28:57 PM PST 23 Dec 27 12:29:55 PM PST 23 14941653 ps
T875 /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1344221713 Dec 27 12:26:33 PM PST 23 Dec 27 12:27:04 PM PST 23 670234267 ps

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1037993973
Short name T4
Test name
Test status
Simulation time 4937705712 ps
CPU time 131.41 seconds
Started Dec 27 12:29:50 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 208028 kb
Host smart-89a4f876-a655-4d6a-9aa9-b18453e33026
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1037993973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re
set_error.1037993973
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3310193502
Short name T78
Test name
Test status
Simulation time 157376541543 ps
CPU time 641.54 seconds
Started Dec 27 12:31:59 PM PST 23
Finished Dec 27 12:43:25 PM PST 23
Peak memory 210804 kb
Host smart-16ce8e45-b7fe-456d-afc8-9bbbdfafbf31
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3310193502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl
ow_rsp.3310193502
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.246380495
Short name T31
Test name
Test status
Simulation time 11821472465 ps
CPU time 466.35 seconds
Started Dec 27 12:28:57 PM PST 23
Finished Dec 27 12:37:39 PM PST 23
Peak memory 221824 kb
Host smart-8fe26a36-2158-4430-9a3f-329c4e71f9d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=246380495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand
_reset.246380495
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2385216639
Short name T251
Test name
Test status
Simulation time 78912167510 ps
CPU time 363.15 seconds
Started Dec 27 12:28:43 PM PST 23
Finished Dec 27 12:35:39 PM PST 23
Peak memory 210884 kb
Host smart-a69e0285-c07c-4ec2-97f5-493af2a13c9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2385216639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.2385216639
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4134640937
Short name T96
Test name
Test status
Simulation time 25341247158 ps
CPU time 220.12 seconds
Started Dec 27 12:28:10 PM PST 23
Finished Dec 27 12:32:29 PM PST 23
Peak memory 204632 kb
Host smart-39b3187f-00c2-47ee-a564-b7338788cc70
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4134640937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.4134640937
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2393793825
Short name T9
Test name
Test status
Simulation time 35971144338 ps
CPU time 177.72 seconds
Started Dec 27 12:28:02 PM PST 23
Finished Dec 27 12:31:33 PM PST 23
Peak memory 211084 kb
Host smart-0d8842a6-93f9-40cf-a616-c7371e5c5f4c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393793825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2393793825
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.62125950
Short name T15
Test name
Test status
Simulation time 234837945 ps
CPU time 24.74 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 203992 kb
Host smart-667e29a6-e0e9-4df0-b5ee-8e6a89889e4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62125950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.62125950
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2264754624
Short name T112
Test name
Test status
Simulation time 363060006002 ps
CPU time 510.43 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:38:17 PM PST 23
Peak memory 211216 kb
Host smart-b8f2f785-0abc-40b5-84b4-ec4cdae6ce39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2264754624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl
ow_rsp.2264754624
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1079469994
Short name T86
Test name
Test status
Simulation time 8391941165 ps
CPU time 286.12 seconds
Started Dec 27 12:27:21 PM PST 23
Finished Dec 27 12:32:36 PM PST 23
Peak memory 209524 kb
Host smart-68bb9f4b-4fc8-4d85-924f-eb5b2e1226f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1079469994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1079469994
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.38275900
Short name T38
Test name
Test status
Simulation time 22041524004 ps
CPU time 167.38 seconds
Started Dec 27 12:26:30 PM PST 23
Finished Dec 27 12:29:33 PM PST 23
Peak memory 204380 kb
Host smart-016c9bea-f1cc-4a0e-92f6-cac17d7bdb4a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=38275900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.38275900
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.4257833032
Short name T115
Test name
Test status
Simulation time 7036582657 ps
CPU time 191.24 seconds
Started Dec 27 12:28:35 PM PST 23
Finished Dec 27 12:32:37 PM PST 23
Peak memory 209064 kb
Host smart-d50bca00-100c-442e-bd0d-d2aad3065e28
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4257833032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.4257833032
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.19750569
Short name T20
Test name
Test status
Simulation time 3669020040 ps
CPU time 338.71 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:34:18 PM PST 23
Peak memory 210104 kb
Host smart-5433cc61-7965-4cec-8f4f-008baa38f938
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=19750569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_
reset.19750569
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3352460438
Short name T155
Test name
Test status
Simulation time 2165794117 ps
CPU time 333.4 seconds
Started Dec 27 12:26:35 PM PST 23
Finished Dec 27 12:32:25 PM PST 23
Peak memory 208924 kb
Host smart-0440b59a-a084-41c9-8cbd-6bce227a7aee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3352460438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand
_reset.3352460438
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3090816786
Short name T22
Test name
Test status
Simulation time 16400894962 ps
CPU time 200.23 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 211236 kb
Host smart-8159466a-fcae-49f4-9ddb-8e14126daf6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3090816786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.3090816786
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.861007135
Short name T284
Test name
Test status
Simulation time 813657553 ps
CPU time 191.58 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:33:01 PM PST 23
Peak memory 210920 kb
Host smart-68f41811-8bb7-438e-9cdd-2759990dc071
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=861007135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_res
et_error.861007135
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.4168172648
Short name T26
Test name
Test status
Simulation time 975792130 ps
CPU time 38.9 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:29:25 PM PST 23
Peak memory 211212 kb
Host smart-dd69ebad-96ce-4c26-b19d-e9cefdb55255
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4168172648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.4168172648
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2919929959
Short name T128
Test name
Test status
Simulation time 21708812144 ps
CPU time 194.12 seconds
Started Dec 27 12:27:51 PM PST 23
Finished Dec 27 12:31:36 PM PST 23
Peak memory 205548 kb
Host smart-6fc68f02-d092-4bd2-a028-13fba8332343
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2919929959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl
ow_rsp.2919929959
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.2863487902
Short name T167
Test name
Test status
Simulation time 780854836 ps
CPU time 23.36 seconds
Started Dec 27 12:27:42 PM PST 23
Finished Dec 27 12:28:36 PM PST 23
Peak memory 210304 kb
Host smart-0c7a296f-a1e6-455b-94b5-587be897e594
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2863487902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2863487902
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3549139
Short name T744
Test name
Test status
Simulation time 954388578 ps
CPU time 23.69 seconds
Started Dec 27 12:26:35 PM PST 23
Finished Dec 27 12:27:15 PM PST 23
Peak memory 204248 kb
Host smart-c3ae8bbf-e476-4c05-8755-8ba93a711623
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3549139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3549139
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2683705790
Short name T574
Test name
Test status
Simulation time 40231634948 ps
CPU time 144.38 seconds
Started Dec 27 12:27:40 PM PST 23
Finished Dec 27 12:30:35 PM PST 23
Peak memory 204900 kb
Host smart-27f215c8-50b1-45a5-b245-50d00f88d824
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2683705790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.2683705790
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1885044892
Short name T311
Test name
Test status
Simulation time 150927528 ps
CPU time 18.41 seconds
Started Dec 27 12:26:35 PM PST 23
Finished Dec 27 12:27:09 PM PST 23
Peak memory 202656 kb
Host smart-cf77995d-e9b7-43e2-a1ce-bef7711d827f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1885044892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1885044892
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.3086851558
Short name T252
Test name
Test status
Simulation time 479095008 ps
CPU time 16.75 seconds
Started Dec 27 12:24:57 PM PST 23
Finished Dec 27 12:25:14 PM PST 23
Peak memory 202916 kb
Host smart-09f892c7-3a67-4151-9285-b089a9655b3a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3086851558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3086851558
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.3827230112
Short name T869
Test name
Test status
Simulation time 1891591762 ps
CPU time 20.41 seconds
Started Dec 27 12:24:59 PM PST 23
Finished Dec 27 12:25:23 PM PST 23
Peak memory 209936 kb
Host smart-169bcef2-492a-4799-9450-3fb3fea85aeb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3827230112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3827230112
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3277837186
Short name T506
Test name
Test status
Simulation time 94760819078 ps
CPU time 128.14 seconds
Started Dec 27 12:25:05 PM PST 23
Finished Dec 27 12:27:16 PM PST 23
Peak memory 211132 kb
Host smart-a8cb55c8-fdc6-4c34-9359-973b5c115d9d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277837186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3277837186
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2620019365
Short name T436
Test name
Test status
Simulation time 37260243687 ps
CPU time 152.71 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:38:22 PM PST 23
Peak memory 211092 kb
Host smart-a258a83e-a147-46f2-af2a-22b8747c8c82
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2620019365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2620019365
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3094604320
Short name T577
Test name
Test status
Simulation time 145225637 ps
CPU time 12.63 seconds
Started Dec 27 12:27:50 PM PST 23
Finished Dec 27 12:28:34 PM PST 23
Peak memory 210820 kb
Host smart-177f6f57-4b1a-4865-ad82-fa8b001d1d76
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094604320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3094604320
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.1683362896
Short name T562
Test name
Test status
Simulation time 867032707 ps
CPU time 18.95 seconds
Started Dec 27 12:26:35 PM PST 23
Finished Dec 27 12:27:11 PM PST 23
Peak memory 203084 kb
Host smart-90ccc980-a959-476d-8241-a5916e7ef13b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1683362896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1683362896
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.1832968548
Short name T212
Test name
Test status
Simulation time 117161046 ps
CPU time 3.09 seconds
Started Dec 27 12:24:48 PM PST 23
Finished Dec 27 12:24:53 PM PST 23
Peak memory 202680 kb
Host smart-9caa897c-39a6-4218-acc3-4eb35dca0bae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1832968548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1832968548
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.685162979
Short name T143
Test name
Test status
Simulation time 9241368349 ps
CPU time 32.89 seconds
Started Dec 27 12:35:19 PM PST 23
Finished Dec 27 12:36:09 PM PST 23
Peak memory 202772 kb
Host smart-0e58f004-ee72-41db-a25a-a50916bf54c8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=685162979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.685162979
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3785022497
Short name T812
Test name
Test status
Simulation time 2297989770 ps
CPU time 23.54 seconds
Started Dec 27 12:24:48 PM PST 23
Finished Dec 27 12:25:14 PM PST 23
Peak memory 202748 kb
Host smart-8419d57a-84df-4c6d-a988-5a5c1b855aee
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3785022497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3785022497
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3539321420
Short name T253
Test name
Test status
Simulation time 24131124 ps
CPU time 2.46 seconds
Started Dec 27 12:25:00 PM PST 23
Finished Dec 27 12:25:05 PM PST 23
Peak memory 202832 kb
Host smart-6cd5e31f-4b38-4227-9af8-6f4175f32daa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539321420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3539321420
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3086216532
Short name T663
Test name
Test status
Simulation time 2771546436 ps
CPU time 102.2 seconds
Started Dec 27 12:28:18 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 206112 kb
Host smart-78dc23a3-b1ed-47f9-a048-67a1ec77ef62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3086216532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3086216532
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.538575569
Short name T333
Test name
Test status
Simulation time 5790888372 ps
CPU time 122.73 seconds
Started Dec 27 12:21:22 PM PST 23
Finished Dec 27 12:23:26 PM PST 23
Peak memory 205820 kb
Host smart-d05d1503-a9c7-4f5d-a35d-4e7541871743
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=538575569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.538575569
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.328661554
Short name T72
Test name
Test status
Simulation time 95602923 ps
CPU time 20.87 seconds
Started Dec 27 12:28:39 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 205080 kb
Host smart-b4156e0a-3fb5-458d-9412-1846c441bff5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=328661554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese
t_error.328661554
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.4195768356
Short name T448
Test name
Test status
Simulation time 1679165497 ps
CPU time 19.25 seconds
Started Dec 27 12:22:38 PM PST 23
Finished Dec 27 12:22:58 PM PST 23
Peak memory 211228 kb
Host smart-c0286370-af44-4ada-bb54-3030ec2103d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4195768356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.4195768356
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.551748719
Short name T126
Test name
Test status
Simulation time 947119869 ps
CPU time 19.81 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:28:57 PM PST 23
Peak memory 210768 kb
Host smart-dc671423-9d30-4a7c-91e3-52a03ae21d1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=551748719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.551748719
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.597561174
Short name T867
Test name
Test status
Simulation time 172856289552 ps
CPU time 609.56 seconds
Started Dec 27 12:28:36 PM PST 23
Finished Dec 27 12:39:36 PM PST 23
Peak memory 205052 kb
Host smart-3cd11886-ddc1-42dd-b5a9-956521c21951
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=597561174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow
_rsp.597561174
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1945024781
Short name T122
Test name
Test status
Simulation time 97860213 ps
CPU time 10.17 seconds
Started Dec 27 12:25:11 PM PST 23
Finished Dec 27 12:25:25 PM PST 23
Peak memory 201900 kb
Host smart-85bd981f-552f-4e5e-a1cd-e978e672fca6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1945024781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1945024781
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.2458255084
Short name T373
Test name
Test status
Simulation time 335794952 ps
CPU time 20.27 seconds
Started Dec 27 12:26:02 PM PST 23
Finished Dec 27 12:26:30 PM PST 23
Peak memory 202844 kb
Host smart-f7e5624c-6d76-4b0f-abc0-8388b8ef79f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2458255084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2458255084
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.2536878508
Short name T291
Test name
Test status
Simulation time 22219313 ps
CPU time 2.96 seconds
Started Dec 27 12:21:31 PM PST 23
Finished Dec 27 12:21:35 PM PST 23
Peak memory 202956 kb
Host smart-739b4ee2-b1de-496a-bfa6-aa65333bb68c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2536878508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2536878508
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2395302956
Short name T487
Test name
Test status
Simulation time 57696604381 ps
CPU time 266.05 seconds
Started Dec 27 12:28:36 PM PST 23
Finished Dec 27 12:33:57 PM PST 23
Peak memory 210888 kb
Host smart-10a70b05-1e39-4ca2-8f65-4fd4096b781e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2395302956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2395302956
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3277007903
Short name T209
Test name
Test status
Simulation time 38199001 ps
CPU time 4.04 seconds
Started Dec 27 12:28:10 PM PST 23
Finished Dec 27 12:28:53 PM PST 23
Peak memory 201612 kb
Host smart-0f79f694-0a2f-49c5-8777-65d58f3bc2c2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277007903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3277007903
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.2046175872
Short name T702
Test name
Test status
Simulation time 859836695 ps
CPU time 20.53 seconds
Started Dec 27 12:21:43 PM PST 23
Finished Dec 27 12:22:04 PM PST 23
Peak memory 203504 kb
Host smart-e897c924-7e38-41e2-ac80-fb395f317d67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2046175872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2046175872
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.3238367138
Short name T646
Test name
Test status
Simulation time 158988558 ps
CPU time 3 seconds
Started Dec 27 12:28:44 PM PST 23
Finished Dec 27 12:29:39 PM PST 23
Peak memory 202640 kb
Host smart-0204d5be-4c99-4b52-ba23-861fb8fb22fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3238367138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3238367138
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.907572156
Short name T447
Test name
Test status
Simulation time 4679479531 ps
CPU time 25.28 seconds
Started Dec 27 12:24:00 PM PST 23
Finished Dec 27 12:24:26 PM PST 23
Peak memory 203060 kb
Host smart-bc9a1a03-e706-4ccb-8c9c-2429e561c73b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=907572156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.907572156
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.167038622
Short name T587
Test name
Test status
Simulation time 5171521375 ps
CPU time 32.14 seconds
Started Dec 27 12:23:43 PM PST 23
Finished Dec 27 12:24:17 PM PST 23
Peak memory 203112 kb
Host smart-aa2cee1b-64fc-4d0d-8f49-814fe7e790cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=167038622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.167038622
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3896256835
Short name T401
Test name
Test status
Simulation time 61682324 ps
CPU time 2.42 seconds
Started Dec 27 12:25:36 PM PST 23
Finished Dec 27 12:25:46 PM PST 23
Peak memory 202764 kb
Host smart-9ac79122-30f1-4536-a7b5-71a7dde6b126
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896256835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3896256835
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.3643124243
Short name T701
Test name
Test status
Simulation time 2010775334 ps
CPU time 47.22 seconds
Started Dec 27 12:25:12 PM PST 23
Finished Dec 27 12:26:02 PM PST 23
Peak memory 209904 kb
Host smart-65674529-e8f3-4d75-bc94-2a84a8dd7a88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3643124243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3643124243
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2473780310
Short name T445
Test name
Test status
Simulation time 9110596104 ps
CPU time 189.36 seconds
Started Dec 27 12:28:23 PM PST 23
Finished Dec 27 12:32:19 PM PST 23
Peak memory 206996 kb
Host smart-bc65266f-d129-4047-ac1a-f15e9314b8d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2473780310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2473780310
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2477268795
Short name T497
Test name
Test status
Simulation time 432516068 ps
CPU time 142.41 seconds
Started Dec 27 12:26:13 PM PST 23
Finished Dec 27 12:28:47 PM PST 23
Peak memory 206604 kb
Host smart-a8e98d19-febd-46cc-aaa4-22608b2f54a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2477268795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.2477268795
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2902121091
Short name T788
Test name
Test status
Simulation time 525634180 ps
CPU time 139.91 seconds
Started Dec 27 12:20:21 PM PST 23
Finished Dec 27 12:22:45 PM PST 23
Peak memory 210160 kb
Host smart-6b7c78c5-199f-4e7d-9fe1-4505316b45d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2902121091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.2902121091
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.966659481
Short name T750
Test name
Test status
Simulation time 100052411 ps
CPU time 9.03 seconds
Started Dec 27 12:27:24 PM PST 23
Finished Dec 27 12:28:01 PM PST 23
Peak memory 211036 kb
Host smart-14ab73f2-942e-4b2e-90e1-1eeb166ebea1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=966659481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.966659481
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1517578264
Short name T98
Test name
Test status
Simulation time 17686378704 ps
CPU time 147.97 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:32:19 PM PST 23
Peak memory 211288 kb
Host smart-3f53751e-3845-4172-8fbe-59a195281f76
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1517578264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.1517578264
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2535588770
Short name T307
Test name
Test status
Simulation time 103415215 ps
CPU time 10.81 seconds
Started Dec 27 12:27:23 PM PST 23
Finished Dec 27 12:28:02 PM PST 23
Peak memory 203032 kb
Host smart-03511b7e-0d1b-4b57-8ef8-f6d7c037f7b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2535588770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2535588770
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.2821728642
Short name T516
Test name
Test status
Simulation time 543454317 ps
CPU time 9.64 seconds
Started Dec 27 12:27:34 PM PST 23
Finished Dec 27 12:28:12 PM PST 23
Peak memory 202820 kb
Host smart-57a9dfb3-3538-446f-8bbe-33bb5d045ab1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2821728642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2821728642
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.2557181751
Short name T84
Test name
Test status
Simulation time 3519805673 ps
CPU time 19.04 seconds
Started Dec 27 12:27:24 PM PST 23
Finished Dec 27 12:28:11 PM PST 23
Peak memory 211224 kb
Host smart-09573e58-b5a8-40ed-8e39-6ca2bbb1c43d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2557181751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2557181751
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3896726012
Short name T107
Test name
Test status
Simulation time 22744440402 ps
CPU time 129.7 seconds
Started Dec 27 12:27:25 PM PST 23
Finished Dec 27 12:30:03 PM PST 23
Peak memory 211212 kb
Host smart-78f82f61-3dfd-4f73-8d40-5fbbd6e951bf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896726012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3896726012
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.887492444
Short name T469
Test name
Test status
Simulation time 16240760478 ps
CPU time 125.81 seconds
Started Dec 27 12:27:28 PM PST 23
Finished Dec 27 12:30:02 PM PST 23
Peak memory 204424 kb
Host smart-12838d96-02f2-4bad-8036-c3d29540c23a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=887492444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.887492444
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2696997179
Short name T520
Test name
Test status
Simulation time 601536270 ps
CPU time 15.45 seconds
Started Dec 27 12:27:25 PM PST 23
Finished Dec 27 12:28:08 PM PST 23
Peak memory 211000 kb
Host smart-2cbc5335-cf63-4496-87ff-f6ac1e585f8b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696997179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2696997179
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.1609473775
Short name T584
Test name
Test status
Simulation time 67749486 ps
CPU time 4.22 seconds
Started Dec 27 12:27:24 PM PST 23
Finished Dec 27 12:27:56 PM PST 23
Peak memory 202832 kb
Host smart-55b50553-cf65-4dbf-9a43-192c4d346c6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1609473775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1609473775
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.1646717228
Short name T522
Test name
Test status
Simulation time 185848655 ps
CPU time 2.96 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:28:48 PM PST 23
Peak memory 202948 kb
Host smart-e7803a39-764d-4843-9aa4-bee7b5642666
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1646717228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1646717228
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2586807879
Short name T330
Test name
Test status
Simulation time 20966196236 ps
CPU time 39.41 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:29:24 PM PST 23
Peak memory 203032 kb
Host smart-f8eccd6c-0b54-4794-922e-35b2ee328a87
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586807879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2586807879
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3484418113
Short name T236
Test name
Test status
Simulation time 3519094439 ps
CPU time 29.84 seconds
Started Dec 27 12:27:30 PM PST 23
Finished Dec 27 12:28:29 PM PST 23
Peak memory 202932 kb
Host smart-9175c849-0b19-4c4c-b475-22028e65bfa1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3484418113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3484418113
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2996978707
Short name T783
Test name
Test status
Simulation time 54463473 ps
CPU time 2.18 seconds
Started Dec 27 12:28:50 PM PST 23
Finished Dec 27 12:29:45 PM PST 23
Peak memory 202884 kb
Host smart-d6627226-16c5-4bd6-b805-29b07d93ef96
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996978707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2996978707
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1037955829
Short name T150
Test name
Test status
Simulation time 16777964621 ps
CPU time 115.85 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:31:45 PM PST 23
Peak memory 211272 kb
Host smart-5023797d-afb5-4b67-a9de-f522380c5d1c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1037955829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1037955829
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1256032353
Short name T566
Test name
Test status
Simulation time 1674928762 ps
CPU time 276.76 seconds
Started Dec 27 12:27:23 PM PST 23
Finished Dec 27 12:32:28 PM PST 23
Peak memory 210428 kb
Host smart-b00149eb-70ef-4a97-929a-fd6985e08120
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1256032353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.1256032353
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2252179188
Short name T704
Test name
Test status
Simulation time 4743441067 ps
CPU time 56.23 seconds
Started Dec 27 12:29:59 PM PST 23
Finished Dec 27 12:31:48 PM PST 23
Peak memory 206392 kb
Host smart-9733eab7-f2a4-4d2b-8a05-67d97adf4517
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2252179188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.2252179188
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2946757050
Short name T649
Test name
Test status
Simulation time 389742059 ps
CPU time 16.12 seconds
Started Dec 27 12:27:33 PM PST 23
Finished Dec 27 12:28:18 PM PST 23
Peak memory 211036 kb
Host smart-822eeb87-c1ed-4b23-9a9d-8f66647bfd9a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2946757050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2946757050
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3703426517
Short name T594
Test name
Test status
Simulation time 411320386 ps
CPU time 25.1 seconds
Started Dec 27 12:27:23 PM PST 23
Finished Dec 27 12:28:16 PM PST 23
Peak memory 211076 kb
Host smart-3c3c4dca-a90b-4d28-83bf-3cd572013ad8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3703426517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3703426517
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.823890973
Short name T134
Test name
Test status
Simulation time 46151277617 ps
CPU time 285.59 seconds
Started Dec 27 12:27:26 PM PST 23
Finished Dec 27 12:32:39 PM PST 23
Peak memory 205260 kb
Host smart-3e6d9681-baaf-427c-b51f-2ace228b6cac
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=823890973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo
w_rsp.823890973
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2137015581
Short name T772
Test name
Test status
Simulation time 139759285 ps
CPU time 15.32 seconds
Started Dec 27 12:28:12 PM PST 23
Finished Dec 27 12:29:07 PM PST 23
Peak memory 202932 kb
Host smart-11c04e1f-3f93-47dd-9ab4-778de48c4c1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2137015581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2137015581
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.2791929204
Short name T341
Test name
Test status
Simulation time 637836006 ps
CPU time 16.7 seconds
Started Dec 27 12:27:36 PM PST 23
Finished Dec 27 12:28:22 PM PST 23
Peak memory 202896 kb
Host smart-5b2baa48-ad36-40c1-8642-14e66c98db00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2791929204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2791929204
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.491554415
Short name T709
Test name
Test status
Simulation time 1187922321 ps
CPU time 22.68 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:29:08 PM PST 23
Peak memory 211052 kb
Host smart-01d1b7d3-aa0d-45d5-b3bd-ce203acf6f90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=491554415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.491554415
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3814851957
Short name T473
Test name
Test status
Simulation time 4843235993 ps
CPU time 23 seconds
Started Dec 27 12:27:26 PM PST 23
Finished Dec 27 12:28:17 PM PST 23
Peak memory 203200 kb
Host smart-c21959e0-eda0-4fdb-aec8-236494fe40d2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814851957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3814851957
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.288394617
Short name T860
Test name
Test status
Simulation time 18478174815 ps
CPU time 155.56 seconds
Started Dec 27 12:27:31 PM PST 23
Finished Dec 27 12:30:35 PM PST 23
Peak memory 204468 kb
Host smart-7372fb63-3656-484a-9e16-a80e050aa543
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=288394617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.288394617
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.4019668893
Short name T358
Test name
Test status
Simulation time 185992381 ps
CPU time 24.72 seconds
Started Dec 27 12:27:25 PM PST 23
Finished Dec 27 12:28:18 PM PST 23
Peak memory 211236 kb
Host smart-7135a370-565d-40be-ba46-2d1bdc9c278e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019668893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.4019668893
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.924180236
Short name T204
Test name
Test status
Simulation time 3816998862 ps
CPU time 21.2 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:30:10 PM PST 23
Peak memory 202952 kb
Host smart-23b736fe-d9db-477a-8a9e-881e1954c472
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=924180236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.924180236
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.2780414697
Short name T776
Test name
Test status
Simulation time 166306941 ps
CPU time 2.39 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:29:15 PM PST 23
Peak memory 202828 kb
Host smart-6e60b350-cb0c-4c7b-8eb2-699577016f81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2780414697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2780414697
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.273453173
Short name T206
Test name
Test status
Simulation time 40808964177 ps
CPU time 51.07 seconds
Started Dec 27 12:27:48 PM PST 23
Finished Dec 27 12:29:10 PM PST 23
Peak memory 202908 kb
Host smart-3ae26f56-9aca-4f87-93ab-ff31b0a0f9b2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=273453173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.273453173
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.4195797904
Short name T567
Test name
Test status
Simulation time 19351323814 ps
CPU time 48.89 seconds
Started Dec 27 12:27:24 PM PST 23
Finished Dec 27 12:28:40 PM PST 23
Peak memory 203068 kb
Host smart-3ac7b5eb-a99d-43e9-b889-ea0c71e52879
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4195797904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.4195797904
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2604834762
Short name T694
Test name
Test status
Simulation time 64170582 ps
CPU time 2.42 seconds
Started Dec 27 12:28:20 PM PST 23
Finished Dec 27 12:29:07 PM PST 23
Peak memory 202984 kb
Host smart-c08141b4-de9b-4f39-a4ee-2509ccd4b1f5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604834762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2604834762
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.201529187
Short name T193
Test name
Test status
Simulation time 668417368 ps
CPU time 20.48 seconds
Started Dec 27 12:27:26 PM PST 23
Finished Dec 27 12:28:14 PM PST 23
Peak memory 204448 kb
Host smart-c05c5e03-b849-499a-b3f7-366d0fb452f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=201529187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.201529187
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.4165096238
Short name T591
Test name
Test status
Simulation time 2851552951 ps
CPU time 83.01 seconds
Started Dec 27 12:28:24 PM PST 23
Finished Dec 27 12:30:34 PM PST 23
Peak memory 204348 kb
Host smart-8055bb22-2076-4474-b759-657dd78f8404
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4165096238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.4165096238
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3869176317
Short name T756
Test name
Test status
Simulation time 486576149 ps
CPU time 137.08 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 206200 kb
Host smart-07f55f3d-4fe3-4459-aff9-e8d73fdd3a05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3869176317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.3869176317
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1032044865
Short name T749
Test name
Test status
Simulation time 521064512 ps
CPU time 21.25 seconds
Started Dec 27 12:27:44 PM PST 23
Finished Dec 27 12:28:37 PM PST 23
Peak memory 211112 kb
Host smart-85e95dca-2d0b-40fa-b928-1cce2c5236f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1032044865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1032044865
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1938181021
Short name T221
Test name
Test status
Simulation time 245051203 ps
CPU time 14.37 seconds
Started Dec 27 12:27:22 PM PST 23
Finished Dec 27 12:28:05 PM PST 23
Peak memory 211148 kb
Host smart-1600bed1-ad44-423b-8119-7264d6ec07c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1938181021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1938181021
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3418252834
Short name T746
Test name
Test status
Simulation time 12248829859 ps
CPU time 113.6 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:32:34 PM PST 23
Peak memory 210836 kb
Host smart-dce7fa06-44a6-4045-93e1-dfd9d16b9593
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3418252834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.3418252834
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3413342095
Short name T2
Test name
Test status
Simulation time 20945131 ps
CPU time 2.28 seconds
Started Dec 27 12:28:11 PM PST 23
Finished Dec 27 12:28:52 PM PST 23
Peak memory 202800 kb
Host smart-b53178e9-6e9a-4375-9338-407ba97c8921
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3413342095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3413342095
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.208908529
Short name T386
Test name
Test status
Simulation time 428603658 ps
CPU time 19.19 seconds
Started Dec 27 12:28:22 PM PST 23
Finished Dec 27 12:29:27 PM PST 23
Peak memory 202940 kb
Host smart-d933e6ed-8534-4075-939f-8fe8281d326a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=208908529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.208908529
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.4238830422
Short name T45
Test name
Test status
Simulation time 1908473489 ps
CPU time 27.08 seconds
Started Dec 27 12:27:29 PM PST 23
Finished Dec 27 12:28:25 PM PST 23
Peak memory 204008 kb
Host smart-bf1c165c-a339-49f3-8db1-707f7e0f1746
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4238830422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.4238830422
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2869572733
Short name T544
Test name
Test status
Simulation time 62915451410 ps
CPU time 229.98 seconds
Started Dec 27 12:27:24 PM PST 23
Finished Dec 27 12:31:43 PM PST 23
Peak memory 204204 kb
Host smart-608bc0bb-b9b3-4b77-8b36-ae273cfa9f0b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869572733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2869572733
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.321026436
Short name T53
Test name
Test status
Simulation time 91880045258 ps
CPU time 170.67 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:31:29 PM PST 23
Peak memory 204520 kb
Host smart-cefa6242-ac87-4769-979d-db3cabe57571
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=321026436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.321026436
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.1086053170
Short name T655
Test name
Test status
Simulation time 461497303 ps
CPU time 20.11 seconds
Started Dec 27 12:27:54 PM PST 23
Finished Dec 27 12:28:47 PM PST 23
Peak memory 203956 kb
Host smart-95817961-4075-4b28-93ce-b82f6418a8e2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086053170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1086053170
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.1394460843
Short name T350
Test name
Test status
Simulation time 691945229 ps
CPU time 14.9 seconds
Started Dec 27 12:27:35 PM PST 23
Finished Dec 27 12:28:19 PM PST 23
Peak memory 202928 kb
Host smart-a07a6dc5-2935-4827-bde2-b5f12ac1fa9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1394460843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1394460843
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.2271500202
Short name T599
Test name
Test status
Simulation time 28653362 ps
CPU time 2.28 seconds
Started Dec 27 12:27:25 PM PST 23
Finished Dec 27 12:27:55 PM PST 23
Peak memory 203004 kb
Host smart-df3c4f51-9de9-4b09-aed4-cdf249889927
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2271500202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2271500202
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3725579011
Short name T602
Test name
Test status
Simulation time 5971915186 ps
CPU time 35.6 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:31:16 PM PST 23
Peak memory 202448 kb
Host smart-a6ec117b-a10d-4e52-a16d-6a968848868d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725579011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3725579011
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2336646471
Short name T215
Test name
Test status
Simulation time 17688781405 ps
CPU time 42.35 seconds
Started Dec 27 12:27:25 PM PST 23
Finished Dec 27 12:28:36 PM PST 23
Peak memory 203008 kb
Host smart-9538ad0b-8188-4edf-9415-990a5630dc6d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2336646471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2336646471
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2369825541
Short name T535
Test name
Test status
Simulation time 40617959 ps
CPU time 2.25 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:28:48 PM PST 23
Peak memory 202968 kb
Host smart-40bfa06e-e15e-4c0f-9fdc-df9c4bea4720
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369825541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2369825541
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.363357593
Short name T57
Test name
Test status
Simulation time 5976143187 ps
CPU time 157.58 seconds
Started Dec 27 12:27:31 PM PST 23
Finished Dec 27 12:30:38 PM PST 23
Peak memory 209132 kb
Host smart-c375fbe8-7e72-4316-9dcf-ccfb0c9b56fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=363357593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.363357593
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2227647412
Short name T786
Test name
Test status
Simulation time 2271888516 ps
CPU time 103.34 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:32:12 PM PST 23
Peak memory 206632 kb
Host smart-bb4775dc-eb4d-4a9d-b22f-7a299a26757f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2227647412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2227647412
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3109861328
Short name T285
Test name
Test status
Simulation time 3133782691 ps
CPU time 425.89 seconds
Started Dec 27 12:28:23 PM PST 23
Finished Dec 27 12:36:15 PM PST 23
Peak memory 212812 kb
Host smart-5a60644c-c569-4761-a1af-0a9c62d882d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3109861328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.3109861328
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3461578659
Short name T214
Test name
Test status
Simulation time 10348619 ps
CPU time 21.83 seconds
Started Dec 27 12:29:25 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 204644 kb
Host smart-a40f5e92-10b1-47f4-87ea-2724d842e89a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3461578659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.3461578659
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.76728141
Short name T402
Test name
Test status
Simulation time 134670585 ps
CPU time 19.7 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:30:36 PM PST 23
Peak memory 211012 kb
Host smart-8e5446d5-ed62-4845-bb83-63c94cac8457
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=76728141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.76728141
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2781883991
Short name T64
Test name
Test status
Simulation time 905062332 ps
CPU time 23.05 seconds
Started Dec 27 12:28:33 PM PST 23
Finished Dec 27 12:29:45 PM PST 23
Peak memory 210996 kb
Host smart-3c6674a0-1821-4a24-b521-1e3f37df8c78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2781883991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2781883991
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1340720611
Short name T127
Test name
Test status
Simulation time 145247252532 ps
CPU time 627.56 seconds
Started Dec 27 12:27:22 PM PST 23
Finished Dec 27 12:38:18 PM PST 23
Peak memory 211312 kb
Host smart-8f8f40c3-8385-46d1-bf0e-ed651e43a10a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1340720611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl
ow_rsp.1340720611
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1489472728
Short name T408
Test name
Test status
Simulation time 124101814 ps
CPU time 15.68 seconds
Started Dec 27 12:27:25 PM PST 23
Finished Dec 27 12:28:09 PM PST 23
Peak memory 202860 kb
Host smart-5e56ccb3-b8d8-4b5c-966b-fdd971b2b5e6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1489472728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1489472728
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.1503053762
Short name T630
Test name
Test status
Simulation time 845973381 ps
CPU time 30.31 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:30:19 PM PST 23
Peak memory 202708 kb
Host smart-cd7e5642-a351-422d-9e15-4edb5e7fcd81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1503053762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1503053762
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.940058263
Short name T768
Test name
Test status
Simulation time 1454362091 ps
CPU time 37.11 seconds
Started Dec 27 12:27:52 PM PST 23
Finished Dec 27 12:29:02 PM PST 23
Peak memory 211228 kb
Host smart-b8a725ff-ce27-43ec-8f9b-e4d3b8afd9c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=940058263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.940058263
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.1248783842
Short name T484
Test name
Test status
Simulation time 18082208911 ps
CPU time 112.89 seconds
Started Dec 27 12:28:00 PM PST 23
Finished Dec 27 12:30:26 PM PST 23
Peak memory 211128 kb
Host smart-18629aa8-982c-40d1-ae5e-75eb6738622d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248783842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1248783842
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.690731145
Short name T765
Test name
Test status
Simulation time 72752212380 ps
CPU time 294.3 seconds
Started Dec 27 12:27:30 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 204636 kb
Host smart-edd3ff71-df09-46ef-9833-c792cad1118d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=690731145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.690731145
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1635052425
Short name T762
Test name
Test status
Simulation time 211437574 ps
CPU time 14.94 seconds
Started Dec 27 12:28:17 PM PST 23
Finished Dec 27 12:29:14 PM PST 23
Peak memory 203960 kb
Host smart-d2c9d802-24bb-4a8b-b275-58c3ac67c9d5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635052425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1635052425
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.1370912639
Short name T624
Test name
Test status
Simulation time 647734023 ps
CPU time 14.47 seconds
Started Dec 27 12:28:45 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 202476 kb
Host smart-458484d2-0ae8-41a6-bfcc-bedcf1a10f35
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1370912639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1370912639
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.1951717850
Short name T183
Test name
Test status
Simulation time 262431861 ps
CPU time 3.91 seconds
Started Dec 27 12:28:01 PM PST 23
Finished Dec 27 12:28:38 PM PST 23
Peak memory 202856 kb
Host smart-12e4f9e0-16fa-41a5-bbe3-0d4ba4cc7962
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1951717850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1951717850
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.840033366
Short name T228
Test name
Test status
Simulation time 6460069232 ps
CPU time 27.54 seconds
Started Dec 27 12:27:21 PM PST 23
Finished Dec 27 12:28:17 PM PST 23
Peak memory 202984 kb
Host smart-4b0eff60-9928-49be-8715-405721f37a25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=840033366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.840033366
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1063921351
Short name T664
Test name
Test status
Simulation time 6195592806 ps
CPU time 40.11 seconds
Started Dec 27 12:29:50 PM PST 23
Finished Dec 27 12:31:21 PM PST 23
Peak memory 202656 kb
Host smart-c88ab7ca-e7d3-4812-bf5e-ba8afc4eb302
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1063921351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1063921351
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.288938602
Short name T297
Test name
Test status
Simulation time 48280944 ps
CPU time 2.15 seconds
Started Dec 27 12:27:34 PM PST 23
Finished Dec 27 12:28:05 PM PST 23
Peak memory 203016 kb
Host smart-d8e76d3c-aa31-47c4-ac36-3c6565160baa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288938602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.288938602
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.775362297
Short name T859
Test name
Test status
Simulation time 705365727 ps
CPU time 90.81 seconds
Started Dec 27 12:29:10 PM PST 23
Finished Dec 27 12:31:35 PM PST 23
Peak memory 207660 kb
Host smart-db634718-32c2-4c89-b834-709131c682c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=775362297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.775362297
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1963671197
Short name T430
Test name
Test status
Simulation time 1617655836 ps
CPU time 53.6 seconds
Started Dec 27 12:27:33 PM PST 23
Finished Dec 27 12:29:00 PM PST 23
Peak memory 205100 kb
Host smart-ec325b2b-c952-4e1e-bca7-dd4051d693b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1963671197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1963671197
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3544770747
Short name T364
Test name
Test status
Simulation time 6212380348 ps
CPU time 174.84 seconds
Started Dec 27 12:27:31 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 208880 kb
Host smart-776cee14-c1f8-44e0-a2b1-1f9844b6bf8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3544770747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran
d_reset.3544770747
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2084380190
Short name T829
Test name
Test status
Simulation time 365997420 ps
CPU time 112.12 seconds
Started Dec 27 12:28:00 PM PST 23
Finished Dec 27 12:30:26 PM PST 23
Peak memory 208696 kb
Host smart-46e0005e-e1d4-4793-8452-5bf6740a3afd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2084380190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.2084380190
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3665754901
Short name T230
Test name
Test status
Simulation time 127805851 ps
CPU time 15.02 seconds
Started Dec 27 12:27:35 PM PST 23
Finished Dec 27 12:28:19 PM PST 23
Peak memory 211060 kb
Host smart-59c692b9-38ce-47ae-b467-3b6e63b7c9b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3665754901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3665754901
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1497658924
Short name T549
Test name
Test status
Simulation time 4649839217 ps
CPU time 34.69 seconds
Started Dec 27 12:27:32 PM PST 23
Finished Dec 27 12:28:36 PM PST 23
Peak memory 211072 kb
Host smart-255af707-218d-47a7-82be-7bdd6c1010ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1497658924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1497658924
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.820242128
Short name T517
Test name
Test status
Simulation time 114256606249 ps
CPU time 741.83 seconds
Started Dec 27 12:29:16 PM PST 23
Finished Dec 27 12:42:33 PM PST 23
Peak memory 211116 kb
Host smart-5048af69-06fe-45c1-b4d4-4ce560b05f8c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=820242128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slo
w_rsp.820242128
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2634262372
Short name T313
Test name
Test status
Simulation time 257581784 ps
CPU time 5.51 seconds
Started Dec 27 12:28:00 PM PST 23
Finished Dec 27 12:28:39 PM PST 23
Peak memory 202304 kb
Host smart-1db7e681-cd0b-45e0-817c-19a03cf9133b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2634262372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2634262372
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.281287186
Short name T503
Test name
Test status
Simulation time 220327682 ps
CPU time 14.17 seconds
Started Dec 27 12:29:26 PM PST 23
Finished Dec 27 12:30:34 PM PST 23
Peak memory 202856 kb
Host smart-2910eb93-8801-4e41-8c50-7444fb1857a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=281287186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.281287186
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.2462305335
Short name T406
Test name
Test status
Simulation time 373594585 ps
CPU time 26.04 seconds
Started Dec 27 12:27:50 PM PST 23
Finished Dec 27 12:28:48 PM PST 23
Peak memory 211032 kb
Host smart-88408da7-3731-4c99-b888-dbc7d356d759
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2462305335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2462305335
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2583096945
Short name T388
Test name
Test status
Simulation time 52432020065 ps
CPU time 172.93 seconds
Started Dec 27 12:27:29 PM PST 23
Finished Dec 27 12:30:50 PM PST 23
Peak memory 211236 kb
Host smart-bf6d46f5-8b14-4ef3-bd05-82270d75a3ef
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583096945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2583096945
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1467476507
Short name T203
Test name
Test status
Simulation time 1440093579 ps
CPU time 10.57 seconds
Started Dec 27 12:27:35 PM PST 23
Finished Dec 27 12:28:14 PM PST 23
Peak memory 202832 kb
Host smart-80d0c0a2-0a5e-4f74-8b3a-771fa7397145
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1467476507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1467476507
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.421526187
Short name T404
Test name
Test status
Simulation time 596204355 ps
CPU time 18.81 seconds
Started Dec 27 12:27:36 PM PST 23
Finished Dec 27 12:28:24 PM PST 23
Peak memory 203968 kb
Host smart-e6f44ce9-3c0a-4e7b-9601-f1925c141c89
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421526187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.421526187
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.3980759684
Short name T821
Test name
Test status
Simulation time 627326528 ps
CPU time 13.21 seconds
Started Dec 27 12:27:30 PM PST 23
Finished Dec 27 12:28:12 PM PST 23
Peak memory 202996 kb
Host smart-eee18b05-8c35-41bb-9db0-2b3a3727f8b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3980759684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3980759684
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3997815441
Short name T257
Test name
Test status
Simulation time 14426608268 ps
CPU time 38.63 seconds
Started Dec 27 12:28:58 PM PST 23
Finished Dec 27 12:30:32 PM PST 23
Peak memory 202992 kb
Host smart-8637e398-60cd-4a65-ba40-8ff94bcb6dd1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997815441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3997815441
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2489123240
Short name T551
Test name
Test status
Simulation time 5336679818 ps
CPU time 30.67 seconds
Started Dec 27 12:27:38 PM PST 23
Finished Dec 27 12:28:39 PM PST 23
Peak memory 202952 kb
Host smart-240e8fe7-2e15-432f-9c48-c4a6229407a4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2489123240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2489123240
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.724341371
Short name T461
Test name
Test status
Simulation time 69494223 ps
CPU time 2.07 seconds
Started Dec 27 12:27:28 PM PST 23
Finished Dec 27 12:27:58 PM PST 23
Peak memory 202944 kb
Host smart-e2e27fe0-3b59-4abf-803c-c6f556a493e2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724341371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.724341371
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.2920731915
Short name T705
Test name
Test status
Simulation time 465145364 ps
CPU time 58.25 seconds
Started Dec 27 12:27:53 PM PST 23
Finished Dec 27 12:29:24 PM PST 23
Peak memory 206624 kb
Host smart-869cf0c5-db22-4660-a4a9-8590d6249b10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2920731915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2920731915
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.742354412
Short name T316
Test name
Test status
Simulation time 4617278849 ps
CPU time 114.36 seconds
Started Dec 27 12:29:42 PM PST 23
Finished Dec 27 12:32:30 PM PST 23
Peak memory 211184 kb
Host smart-c7cbc100-b7ee-4d5d-84a9-b99eba713b9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=742354412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.742354412
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3494136227
Short name T414
Test name
Test status
Simulation time 457324130 ps
CPU time 137.54 seconds
Started Dec 27 12:27:27 PM PST 23
Finished Dec 27 12:30:13 PM PST 23
Peak memory 211136 kb
Host smart-c0a235e6-f8bc-4a23-ac69-714df55c6cec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3494136227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.3494136227
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3291992075
Short name T366
Test name
Test status
Simulation time 956238965 ps
CPU time 222.9 seconds
Started Dec 27 12:29:15 PM PST 23
Finished Dec 27 12:33:52 PM PST 23
Peak memory 219244 kb
Host smart-9b4dae7b-2cde-42fc-bb68-06c14e735d44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3291992075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.3291992075
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2545881254
Short name T707
Test name
Test status
Simulation time 291484253 ps
CPU time 8.82 seconds
Started Dec 27 12:27:33 PM PST 23
Finished Dec 27 12:28:11 PM PST 23
Peak memory 211112 kb
Host smart-84f1b2b0-4193-41a8-b6e6-81733c9720ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2545881254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2545881254
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2044549977
Short name T83
Test name
Test status
Simulation time 8645731106 ps
CPU time 61.55 seconds
Started Dec 27 12:29:45 PM PST 23
Finished Dec 27 12:31:39 PM PST 23
Peak memory 211100 kb
Host smart-75818be5-264e-46fe-b6c3-a3d560585e90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2044549977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2044549977
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.3181655229
Short name T488
Test name
Test status
Simulation time 6725744682 ps
CPU time 40.37 seconds
Started Dec 27 12:27:29 PM PST 23
Finished Dec 27 12:28:38 PM PST 23
Peak memory 211260 kb
Host smart-ffbab97b-16f1-4997-bba5-3305dfbc2eed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3181655229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.3181655229
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.1444137453
Short name T628
Test name
Test status
Simulation time 770759080 ps
CPU time 19.01 seconds
Started Dec 27 12:27:32 PM PST 23
Finished Dec 27 12:28:20 PM PST 23
Peak memory 202888 kb
Host smart-36112dac-8fb9-434f-bc3b-d8bcfd9d1639
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1444137453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1444137453
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.3449928042
Short name T88
Test name
Test status
Simulation time 2024845207 ps
CPU time 34.95 seconds
Started Dec 27 12:27:27 PM PST 23
Finished Dec 27 12:28:31 PM PST 23
Peak memory 204036 kb
Host smart-e23f1749-b6fa-4782-8309-c84940eaba39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3449928042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3449928042
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1228771397
Short name T580
Test name
Test status
Simulation time 3867618761 ps
CPU time 24.78 seconds
Started Dec 27 12:27:34 PM PST 23
Finished Dec 27 12:28:28 PM PST 23
Peak memory 203032 kb
Host smart-eee36d53-9b28-4e14-90dd-599410309442
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228771397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1228771397
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.2096412300
Short name T121
Test name
Test status
Simulation time 20029381742 ps
CPU time 178.64 seconds
Started Dec 27 12:27:26 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 211284 kb
Host smart-65899f97-0623-4033-92cb-c6540e8878a4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2096412300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2096412300
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.504478486
Short name T157
Test name
Test status
Simulation time 31310539 ps
CPU time 3.12 seconds
Started Dec 27 12:27:31 PM PST 23
Finished Dec 27 12:28:03 PM PST 23
Peak memory 202900 kb
Host smart-01555920-cbf6-4b45-8985-004e1a9cb1bb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504478486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.504478486
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.1703761659
Short name T266
Test name
Test status
Simulation time 1068744696 ps
CPU time 21.41 seconds
Started Dec 27 12:27:29 PM PST 23
Finished Dec 27 12:28:19 PM PST 23
Peak memory 203000 kb
Host smart-e0163b56-0d40-4448-b766-a7ab9a95e37c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1703761659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1703761659
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.2836060655
Short name T626
Test name
Test status
Simulation time 235113449 ps
CPU time 3.59 seconds
Started Dec 27 12:27:36 PM PST 23
Finished Dec 27 12:28:09 PM PST 23
Peak memory 202944 kb
Host smart-11fdf846-8e5a-4f87-b01f-81bc051f08d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2836060655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2836060655
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.4282806964
Short name T681
Test name
Test status
Simulation time 12797787344 ps
CPU time 28.08 seconds
Started Dec 27 12:27:31 PM PST 23
Finished Dec 27 12:28:28 PM PST 23
Peak memory 202900 kb
Host smart-1255db97-4790-4c83-8474-e7b266f54a9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4282806964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4282806964
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.5623435
Short name T389
Test name
Test status
Simulation time 34735305 ps
CPU time 2.12 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:30:18 PM PST 23
Peak memory 202828 kb
Host smart-d0d11157-8661-4dca-bd84-35ecc2a2a73f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5623435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.5623435
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.2490585327
Short name T838
Test name
Test status
Simulation time 13702888265 ps
CPU time 148.69 seconds
Started Dec 27 12:27:37 PM PST 23
Finished Dec 27 12:30:35 PM PST 23
Peak memory 206900 kb
Host smart-6be8a772-fbce-498e-8652-e651521c1a8c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2490585327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2490585327
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.234464656
Short name T339
Test name
Test status
Simulation time 1349982044 ps
CPU time 28.29 seconds
Started Dec 27 12:27:56 PM PST 23
Finished Dec 27 12:28:57 PM PST 23
Peak memory 203872 kb
Host smart-74d9d36e-bd99-41d0-9732-ff46fcd94944
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=234464656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.234464656
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2049862724
Short name T116
Test name
Test status
Simulation time 6080726182 ps
CPU time 345.75 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:34:32 PM PST 23
Peak memory 208960 kb
Host smart-bef6ad15-5e13-406f-8354-f300182ee225
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2049862724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.2049862724
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1523391467
Short name T36
Test name
Test status
Simulation time 154257866 ps
CPU time 65.81 seconds
Started Dec 27 12:27:43 PM PST 23
Finished Dec 27 12:29:19 PM PST 23
Peak memory 206684 kb
Host smart-65fe0611-d585-4022-be3e-f00c3a9f32e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1523391467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.1523391467
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.507426029
Short name T132
Test name
Test status
Simulation time 845005381 ps
CPU time 5.27 seconds
Started Dec 27 12:27:43 PM PST 23
Finished Dec 27 12:28:19 PM PST 23
Peak memory 204152 kb
Host smart-72e077f5-4243-4168-b86e-2d0c510e9e9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=507426029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.507426029
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.539757359
Short name T787
Test name
Test status
Simulation time 191374089 ps
CPU time 4.59 seconds
Started Dec 27 12:28:12 PM PST 23
Finished Dec 27 12:28:56 PM PST 23
Peak memory 203116 kb
Host smart-749316c5-573b-46d9-b7af-705a0d69a47f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=539757359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.539757359
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.1230129831
Short name T737
Test name
Test status
Simulation time 2177311245 ps
CPU time 15.88 seconds
Started Dec 27 12:27:35 PM PST 23
Finished Dec 27 12:28:20 PM PST 23
Peak memory 211140 kb
Host smart-e473cb48-7dec-4066-89c8-b53489615489
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1230129831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1230129831
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3760616399
Short name T639
Test name
Test status
Simulation time 52889664395 ps
CPU time 217.67 seconds
Started Dec 27 12:27:34 PM PST 23
Finished Dec 27 12:31:41 PM PST 23
Peak memory 203992 kb
Host smart-9501c67f-45c2-4276-9cd2-ae14597ccedc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760616399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3760616399
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2876973761
Short name T51
Test name
Test status
Simulation time 28792645485 ps
CPU time 207.42 seconds
Started Dec 27 12:27:39 PM PST 23
Finished Dec 27 12:31:37 PM PST 23
Peak memory 204228 kb
Host smart-190c4f84-059c-4ef3-be65-fc1863c2d087
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2876973761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2876973761
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2719527609
Short name T640
Test name
Test status
Simulation time 111267298 ps
CPU time 14.87 seconds
Started Dec 27 12:27:38 PM PST 23
Finished Dec 27 12:28:23 PM PST 23
Peak memory 204008 kb
Host smart-c7351e21-7899-4f28-978a-2d4d0f345069
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719527609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2719527609
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.765408631
Short name T714
Test name
Test status
Simulation time 1859498978 ps
CPU time 26.1 seconds
Started Dec 27 12:27:49 PM PST 23
Finished Dec 27 12:28:47 PM PST 23
Peak memory 202852 kb
Host smart-49744798-2167-44ae-aa50-f455cf1f21df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=765408631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.765408631
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.749196398
Short name T679
Test name
Test status
Simulation time 23351277 ps
CPU time 1.89 seconds
Started Dec 27 12:28:14 PM PST 23
Finished Dec 27 12:28:58 PM PST 23
Peak memory 202836 kb
Host smart-ea0d1bf4-7392-440c-b088-aa8ee62148bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=749196398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.749196398
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2898472836
Short name T244
Test name
Test status
Simulation time 12429223655 ps
CPU time 39.35 seconds
Started Dec 27 12:28:36 PM PST 23
Finished Dec 27 12:30:06 PM PST 23
Peak memory 202764 kb
Host smart-3f14dfd4-bbb5-4df8-a287-8c7ab46a0b62
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898472836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2898472836
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1509249821
Short name T104
Test name
Test status
Simulation time 8275726910 ps
CPU time 29.53 seconds
Started Dec 27 12:28:13 PM PST 23
Finished Dec 27 12:29:22 PM PST 23
Peak memory 202900 kb
Host smart-d9c0428f-f71a-4c05-933e-19e65b11098e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1509249821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1509249821
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2494523646
Short name T606
Test name
Test status
Simulation time 35370422 ps
CPU time 1.94 seconds
Started Dec 27 12:27:47 PM PST 23
Finished Dec 27 12:28:20 PM PST 23
Peak memory 202876 kb
Host smart-085548dd-c98b-4ac1-9d32-24ca250bc146
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494523646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2494523646
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.982215056
Short name T791
Test name
Test status
Simulation time 8542071275 ps
CPU time 120.27 seconds
Started Dec 27 12:27:47 PM PST 23
Finished Dec 27 12:30:18 PM PST 23
Peak memory 206344 kb
Host smart-fbebbb35-7c60-4106-9091-4bdf414c7aab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=982215056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.982215056
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3404030467
Short name T817
Test name
Test status
Simulation time 24755318050 ps
CPU time 136 seconds
Started Dec 27 12:27:45 PM PST 23
Finished Dec 27 12:30:32 PM PST 23
Peak memory 207860 kb
Host smart-13169435-dc72-4f78-91e9-0b5011721ecd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3404030467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3404030467
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.814799195
Short name T19
Test name
Test status
Simulation time 14550509288 ps
CPU time 341.84 seconds
Started Dec 27 12:28:03 PM PST 23
Finished Dec 27 12:34:19 PM PST 23
Peak memory 210488 kb
Host smart-6feb14c4-91f6-4b19-af38-89821305369f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=814799195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand
_reset.814799195
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2229145542
Short name T730
Test name
Test status
Simulation time 1169553148 ps
CPU time 239.76 seconds
Started Dec 27 12:27:59 PM PST 23
Finished Dec 27 12:32:33 PM PST 23
Peak memory 210684 kb
Host smart-a9fa7614-d3d5-47c7-ae9e-43df8f2d094a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2229145542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re
set_error.2229145542
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.4292610548
Short name T686
Test name
Test status
Simulation time 955123630 ps
CPU time 26.29 seconds
Started Dec 27 12:27:40 PM PST 23
Finished Dec 27 12:28:36 PM PST 23
Peak memory 211012 kb
Host smart-1fa6dfa8-dd05-4349-8155-cf13d13d105a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4292610548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.4292610548
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2799617397
Short name T713
Test name
Test status
Simulation time 812747166 ps
CPU time 24.64 seconds
Started Dec 27 12:27:37 PM PST 23
Finished Dec 27 12:28:31 PM PST 23
Peak memory 205108 kb
Host smart-c99ffb57-4dd5-46a6-b32a-9903adc369f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2799617397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2799617397
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3833617097
Short name T273
Test name
Test status
Simulation time 19241561334 ps
CPU time 117.11 seconds
Started Dec 27 12:27:49 PM PST 23
Finished Dec 27 12:30:18 PM PST 23
Peak memory 205524 kb
Host smart-418805a1-95fd-416b-9b83-22878aed4689
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3833617097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.3833617097
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.1783842890
Short name T726
Test name
Test status
Simulation time 159618189 ps
CPU time 4.14 seconds
Started Dec 27 12:27:44 PM PST 23
Finished Dec 27 12:28:20 PM PST 23
Peak memory 202884 kb
Host smart-6250b399-ab36-42c7-b084-9d990df5501a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1783842890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.1783842890
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.1529742422
Short name T452
Test name
Test status
Simulation time 215008381 ps
CPU time 23.67 seconds
Started Dec 27 12:27:48 PM PST 23
Finished Dec 27 12:28:43 PM PST 23
Peak memory 202932 kb
Host smart-817713d9-d004-408e-99f8-bc50fda7a4a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1529742422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1529742422
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.1256140699
Short name T46
Test name
Test status
Simulation time 174216789 ps
CPU time 18.81 seconds
Started Dec 27 12:27:38 PM PST 23
Finished Dec 27 12:28:27 PM PST 23
Peak memory 211120 kb
Host smart-b1a4c0c1-ab53-47b6-9bfc-6b7756d93b6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1256140699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1256140699
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3433925848
Short name T533
Test name
Test status
Simulation time 8298275676 ps
CPU time 45.12 seconds
Started Dec 27 12:27:48 PM PST 23
Finished Dec 27 12:29:05 PM PST 23
Peak memory 211072 kb
Host smart-100b7e79-5103-4193-90a8-f6a2c5863cfd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433925848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3433925848
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2648227339
Short name T703
Test name
Test status
Simulation time 30564322625 ps
CPU time 67.71 seconds
Started Dec 27 12:27:37 PM PST 23
Finished Dec 27 12:29:14 PM PST 23
Peak memory 204368 kb
Host smart-632c431e-2c75-40b0-8af7-a9f659456ad8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2648227339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2648227339
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.1455572844
Short name T50
Test name
Test status
Simulation time 135574012 ps
CPU time 15.28 seconds
Started Dec 27 12:27:39 PM PST 23
Finished Dec 27 12:28:24 PM PST 23
Peak memory 211220 kb
Host smart-17186671-8b8f-4075-9b38-dc4fd9d28e65
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455572844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1455572844
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.2119210405
Short name T343
Test name
Test status
Simulation time 141064670 ps
CPU time 6.8 seconds
Started Dec 27 12:27:35 PM PST 23
Finished Dec 27 12:28:11 PM PST 23
Peak memory 202936 kb
Host smart-cf1c9756-72bb-49ec-8c49-2477f9e816b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2119210405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2119210405
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.526002562
Short name T570
Test name
Test status
Simulation time 29701525 ps
CPU time 2.21 seconds
Started Dec 27 12:28:10 PM PST 23
Finished Dec 27 12:28:50 PM PST 23
Peak memory 202860 kb
Host smart-a8ded911-09aa-4fb8-a1a6-1d359eb8f5ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=526002562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.526002562
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.629593451
Short name T310
Test name
Test status
Simulation time 3336542750 ps
CPU time 18.65 seconds
Started Dec 27 12:27:43 PM PST 23
Finished Dec 27 12:28:34 PM PST 23
Peak memory 203072 kb
Host smart-01c9ae7d-67d7-4296-b727-a786a398a421
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=629593451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.629593451
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1334970502
Short name T695
Test name
Test status
Simulation time 5418100747 ps
CPU time 31.91 seconds
Started Dec 27 12:27:53 PM PST 23
Finished Dec 27 12:28:58 PM PST 23
Peak memory 202904 kb
Host smart-1fd3ac17-0b55-4d08-8424-7599567fa631
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1334970502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1334970502
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3485219815
Short name T224
Test name
Test status
Simulation time 80559356 ps
CPU time 2.34 seconds
Started Dec 27 12:27:43 PM PST 23
Finished Dec 27 12:28:16 PM PST 23
Peak memory 202988 kb
Host smart-4dde2c16-3e55-4e02-b4ef-179788773e6c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485219815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3485219815
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3254067091
Short name T125
Test name
Test status
Simulation time 15296910084 ps
CPU time 171.67 seconds
Started Dec 27 12:28:34 PM PST 23
Finished Dec 27 12:32:15 PM PST 23
Peak memory 211172 kb
Host smart-510246be-6e28-41a6-99d4-e7326fe096a5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3254067091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3254067091
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.836699157
Short name T254
Test name
Test status
Simulation time 6271737445 ps
CPU time 183.86 seconds
Started Dec 27 12:27:46 PM PST 23
Finished Dec 27 12:31:21 PM PST 23
Peak memory 209468 kb
Host smart-f9acb7b3-9ce4-4112-941b-0c6c72d28d18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=836699157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.836699157
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2956247472
Short name T509
Test name
Test status
Simulation time 5361329721 ps
CPU time 293.89 seconds
Started Dec 27 12:27:49 PM PST 23
Finished Dec 27 12:33:15 PM PST 23
Peak memory 224588 kb
Host smart-28213e1f-dea3-4763-bf2c-780a92fd17fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2956247472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re
set_error.2956247472
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2236776649
Short name T760
Test name
Test status
Simulation time 796181083 ps
CPU time 15.88 seconds
Started Dec 27 12:27:43 PM PST 23
Finished Dec 27 12:28:30 PM PST 23
Peak memory 211076 kb
Host smart-9955ca80-b823-4da2-b5a5-e87d140246ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2236776649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2236776649
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1579692373
Short name T162
Test name
Test status
Simulation time 2610486245 ps
CPU time 47.47 seconds
Started Dec 27 12:29:13 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 203820 kb
Host smart-043a2f6d-001d-4966-b6a3-ff9492edf079
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1579692373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1579692373
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3873025987
Short name T677
Test name
Test status
Simulation time 19614188834 ps
CPU time 103.87 seconds
Started Dec 27 12:28:03 PM PST 23
Finished Dec 27 12:30:21 PM PST 23
Peak memory 205436 kb
Host smart-9bdf6e88-f93c-4817-9eaa-522ff582b23b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3873025987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl
ow_rsp.3873025987
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.571890643
Short name T676
Test name
Test status
Simulation time 526273320 ps
CPU time 15.74 seconds
Started Dec 27 12:27:57 PM PST 23
Finished Dec 27 12:28:47 PM PST 23
Peak memory 203084 kb
Host smart-f2223586-0bed-406e-bcf6-a37a894ce143
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=571890643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.571890643
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.4002843886
Short name T457
Test name
Test status
Simulation time 1086331305 ps
CPU time 24.01 seconds
Started Dec 27 12:27:39 PM PST 23
Finished Dec 27 12:28:34 PM PST 23
Peak memory 202916 kb
Host smart-e1d47e4d-be2a-40ee-859a-d0169f193596
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4002843886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.4002843886
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.328517276
Short name T627
Test name
Test status
Simulation time 57562776 ps
CPU time 5.21 seconds
Started Dec 27 12:27:59 PM PST 23
Finished Dec 27 12:28:37 PM PST 23
Peak memory 203516 kb
Host smart-7770f319-46bc-476e-bedb-8ef13f3663e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=328517276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.328517276
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.488980292
Short name T392
Test name
Test status
Simulation time 35505679381 ps
CPU time 179.58 seconds
Started Dec 27 12:27:51 PM PST 23
Finished Dec 27 12:31:23 PM PST 23
Peak memory 204164 kb
Host smart-1e26a5a7-9681-4db0-86f9-441e7cb5dbe0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=488980292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.488980292
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3788417618
Short name T796
Test name
Test status
Simulation time 31866366324 ps
CPU time 125.85 seconds
Started Dec 27 12:29:42 PM PST 23
Finished Dec 27 12:32:41 PM PST 23
Peak memory 211100 kb
Host smart-9139d127-c8c5-4697-869c-8e5deed31064
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3788417618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3788417618
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2716565625
Short name T563
Test name
Test status
Simulation time 361299442 ps
CPU time 13.94 seconds
Started Dec 27 12:27:53 PM PST 23
Finished Dec 27 12:28:40 PM PST 23
Peak memory 211072 kb
Host smart-5794a4e6-b2ce-43fb-ac5b-c67e31971d11
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716565625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2716565625
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.1289890739
Short name T187
Test name
Test status
Simulation time 2983584657 ps
CPU time 22.45 seconds
Started Dec 27 12:27:51 PM PST 23
Finished Dec 27 12:28:46 PM PST 23
Peak memory 203276 kb
Host smart-89e14895-902e-4e36-8c3c-e8f6f0f6622c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1289890739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1289890739
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.1963476593
Short name T751
Test name
Test status
Simulation time 126718129 ps
CPU time 3.29 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:28:45 PM PST 23
Peak memory 202880 kb
Host smart-85926487-3056-40b7-a05c-be44af23a744
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1963476593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1963476593
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1637476703
Short name T856
Test name
Test status
Simulation time 6616990248 ps
CPU time 29.07 seconds
Started Dec 27 12:27:53 PM PST 23
Finished Dec 27 12:28:56 PM PST 23
Peak memory 203076 kb
Host smart-d3c4af67-2618-4cc8-a888-8f0d31927666
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637476703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1637476703
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2291138100
Short name T58
Test name
Test status
Simulation time 3115056088 ps
CPU time 25.72 seconds
Started Dec 27 12:27:42 PM PST 23
Finished Dec 27 12:28:39 PM PST 23
Peak memory 203068 kb
Host smart-f6261a7a-f94c-4e10-90f5-d4b81253e692
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2291138100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2291138100
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1164141866
Short name T367
Test name
Test status
Simulation time 33334941 ps
CPU time 2.02 seconds
Started Dec 27 12:28:20 PM PST 23
Finished Dec 27 12:29:11 PM PST 23
Peak memory 203000 kb
Host smart-e59fd63a-df29-4264-b0e8-6664b1ce2285
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164141866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1164141866
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.814276103
Short name T798
Test name
Test status
Simulation time 814790640 ps
CPU time 68.21 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:29:49 PM PST 23
Peak memory 210992 kb
Host smart-50e3f31e-ce0c-4d7b-a1bb-2d627aaa788d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=814276103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.814276103
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1692377279
Short name T793
Test name
Test status
Simulation time 2526910854 ps
CPU time 52.27 seconds
Started Dec 27 12:27:53 PM PST 23
Finished Dec 27 12:29:18 PM PST 23
Peak memory 205744 kb
Host smart-ef755644-1f95-4fa0-9be7-661ffc21ae36
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1692377279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1692377279
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.754379321
Short name T21
Test name
Test status
Simulation time 5010126184 ps
CPU time 311.47 seconds
Started Dec 27 12:27:59 PM PST 23
Finished Dec 27 12:33:43 PM PST 23
Peak memory 219452 kb
Host smart-7f77c889-92c7-4c54-81b9-910b030d6bba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=754379321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_res
et_error.754379321
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.2649985293
Short name T382
Test name
Test status
Simulation time 17603208 ps
CPU time 2.79 seconds
Started Dec 27 12:27:52 PM PST 23
Finished Dec 27 12:28:27 PM PST 23
Peak memory 202884 kb
Host smart-ca126e22-2087-448c-ac58-a727d5bf4850
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2649985293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2649985293
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.1027939140
Short name T634
Test name
Test status
Simulation time 132031199 ps
CPU time 6.53 seconds
Started Dec 27 12:27:46 PM PST 23
Finished Dec 27 12:28:24 PM PST 23
Peak memory 203620 kb
Host smart-7ef4e595-94dd-4f52-bf5e-e3116eaaf151
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1027939140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1027939140
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.252970169
Short name T586
Test name
Test status
Simulation time 72062182963 ps
CPU time 567.2 seconds
Started Dec 27 12:28:06 PM PST 23
Finished Dec 27 12:38:09 PM PST 23
Peak memory 211292 kb
Host smart-7296ca3a-c9a8-4399-95d8-958e29418b75
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=252970169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo
w_rsp.252970169
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.680441390
Short name T604
Test name
Test status
Simulation time 4611669830 ps
CPU time 25.4 seconds
Started Dec 27 12:27:47 PM PST 23
Finished Dec 27 12:28:44 PM PST 23
Peak memory 202980 kb
Host smart-d0beecaa-805a-4cc9-ad9a-3e22a7b4396c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=680441390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.680441390
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.598663981
Short name T519
Test name
Test status
Simulation time 563215094 ps
CPU time 16.34 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:28:56 PM PST 23
Peak memory 202988 kb
Host smart-b619f2f1-4398-46c1-826f-7fa742904c27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=598663981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.598663981
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.2643038257
Short name T781
Test name
Test status
Simulation time 763926400 ps
CPU time 21.34 seconds
Started Dec 27 12:27:45 PM PST 23
Finished Dec 27 12:28:37 PM PST 23
Peak memory 211156 kb
Host smart-0f781a8e-5d39-4971-9a64-4b24c8cd09f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2643038257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2643038257
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.913815547
Short name T588
Test name
Test status
Simulation time 94819620610 ps
CPU time 200.21 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 204156 kb
Host smart-b23a572c-f898-418a-a5b4-2372539e646a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=913815547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.913815547
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2153933717
Short name T633
Test name
Test status
Simulation time 14099309979 ps
CPU time 80.38 seconds
Started Dec 27 12:27:46 PM PST 23
Finished Dec 27 12:29:38 PM PST 23
Peak memory 211192 kb
Host smart-232586a3-dcaf-4422-9267-3578a73c27f1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2153933717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2153933717
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.1937204587
Short name T601
Test name
Test status
Simulation time 2418390214 ps
CPU time 15.17 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:28:54 PM PST 23
Peak memory 203324 kb
Host smart-0a352bde-7b8b-412c-9470-a30e4ebf4619
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1937204587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1937204587
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2606293004
Short name T769
Test name
Test status
Simulation time 42210109 ps
CPU time 2.29 seconds
Started Dec 27 12:27:50 PM PST 23
Finished Dec 27 12:28:24 PM PST 23
Peak memory 202848 kb
Host smart-1725a6f0-9968-4505-85dd-4c80acd58268
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2606293004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2606293004
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.3146606269
Short name T774
Test name
Test status
Simulation time 21672466542 ps
CPU time 29.28 seconds
Started Dec 27 12:28:06 PM PST 23
Finished Dec 27 12:29:11 PM PST 23
Peak memory 202928 kb
Host smart-7e9cb334-5a24-466c-b05e-84b4d4ec2903
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146606269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3146606269
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1366339888
Short name T332
Test name
Test status
Simulation time 5063422347 ps
CPU time 21.88 seconds
Started Dec 27 12:27:43 PM PST 23
Finished Dec 27 12:28:36 PM PST 23
Peak memory 202960 kb
Host smart-22e0e875-c121-41de-a36c-c1532f7e4658
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1366339888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1366339888
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1470522621
Short name T418
Test name
Test status
Simulation time 74797434 ps
CPU time 2.17 seconds
Started Dec 27 12:27:49 PM PST 23
Finished Dec 27 12:28:23 PM PST 23
Peak memory 202900 kb
Host smart-e8d6e115-9214-430b-9363-73c0bef9eb64
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470522621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1470522621
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.664102179
Short name T510
Test name
Test status
Simulation time 3279938691 ps
CPU time 99.96 seconds
Started Dec 27 12:28:16 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 206196 kb
Host smart-521cece6-adbe-4ab8-828f-6fedb3dcc22d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=664102179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.664102179
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3144517073
Short name T546
Test name
Test status
Simulation time 4315614837 ps
CPU time 45.77 seconds
Started Dec 27 12:27:54 PM PST 23
Finished Dec 27 12:29:14 PM PST 23
Peak memory 211028 kb
Host smart-86e9feb5-fda8-440f-b246-e4690d3d3075
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3144517073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3144517073
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1485241028
Short name T745
Test name
Test status
Simulation time 1025131936 ps
CPU time 185.67 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 210872 kb
Host smart-c936873b-b890-4770-9cb9-9f8f5ec9df42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1485241028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.1485241028
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.848139227
Short name T25
Test name
Test status
Simulation time 7797181 ps
CPU time 2.5 seconds
Started Dec 27 12:27:53 PM PST 23
Finished Dec 27 12:28:29 PM PST 23
Peak memory 202860 kb
Host smart-583d8c07-ae50-4421-b219-6b54bb644c56
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=848139227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res
et_error.848139227
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.1357591354
Short name T249
Test name
Test status
Simulation time 741683988 ps
CPU time 26.4 seconds
Started Dec 27 12:28:17 PM PST 23
Finished Dec 27 12:29:25 PM PST 23
Peak memory 210888 kb
Host smart-b05961e7-d6be-4713-99ff-db785a366ee0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1357591354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1357591354
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2979879183
Short name T529
Test name
Test status
Simulation time 1734484615 ps
CPU time 31.85 seconds
Started Dec 27 12:25:36 PM PST 23
Finished Dec 27 12:26:16 PM PST 23
Peak memory 202692 kb
Host smart-ddcbcb0e-05ca-4fa3-a20a-3a5f0eda0c88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2979879183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2979879183
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1175757707
Short name T797
Test name
Test status
Simulation time 26352174041 ps
CPU time 82.2 seconds
Started Dec 27 12:26:08 PM PST 23
Finished Dec 27 12:27:39 PM PST 23
Peak memory 211044 kb
Host smart-f8101244-6904-47b5-a3bd-9baaca36fcc0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1175757707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.1175757707
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.243372246
Short name T225
Test name
Test status
Simulation time 1508422508 ps
CPU time 13.94 seconds
Started Dec 27 12:28:59 PM PST 23
Finished Dec 27 12:30:08 PM PST 23
Peak memory 202664 kb
Host smart-f78c62b8-22cf-4fc4-ba4d-510376a1d7ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=243372246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.243372246
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.1170184855
Short name T290
Test name
Test status
Simulation time 196600709 ps
CPU time 21.2 seconds
Started Dec 27 12:26:08 PM PST 23
Finished Dec 27 12:26:38 PM PST 23
Peak memory 202784 kb
Host smart-4c46e31d-5270-4885-a4f5-29925856696c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1170184855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1170184855
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.3992871461
Short name T782
Test name
Test status
Simulation time 512401223 ps
CPU time 9.84 seconds
Started Dec 27 12:20:32 PM PST 23
Finished Dec 27 12:20:44 PM PST 23
Peak memory 203384 kb
Host smart-eb41e8fb-fc43-4fae-8515-e200d537cf52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3992871461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3992871461
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.96704372
Short name T416
Test name
Test status
Simulation time 72974106088 ps
CPU time 192.55 seconds
Started Dec 27 12:28:02 PM PST 23
Finished Dec 27 12:31:49 PM PST 23
Peak memory 210860 kb
Host smart-041b341c-9e17-49a8-bb55-75a684d15021
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=96704372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.96704372
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3136078436
Short name T113
Test name
Test status
Simulation time 32336962147 ps
CPU time 211.31 seconds
Started Dec 27 12:25:34 PM PST 23
Finished Dec 27 12:29:13 PM PST 23
Peak memory 204672 kb
Host smart-b9f63695-4e9c-4e62-9010-231ed392ef94
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3136078436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3136078436
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1630451662
Short name T178
Test name
Test status
Simulation time 741912768 ps
CPU time 21.91 seconds
Started Dec 27 12:25:45 PM PST 23
Finished Dec 27 12:26:13 PM PST 23
Peak memory 210600 kb
Host smart-b9cceedd-f3fd-4103-a1af-ca1ce8aac2a6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630451662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1630451662
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.3631220758
Short name T850
Test name
Test status
Simulation time 475372556 ps
CPU time 7.77 seconds
Started Dec 27 12:25:44 PM PST 23
Finished Dec 27 12:25:58 PM PST 23
Peak memory 201956 kb
Host smart-f2d52338-2f39-4e6b-8e1c-d83c40538fda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3631220758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3631220758
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.2440883720
Short name T616
Test name
Test status
Simulation time 52599887 ps
CPU time 2.45 seconds
Started Dec 27 12:25:12 PM PST 23
Finished Dec 27 12:25:17 PM PST 23
Peak memory 202468 kb
Host smart-d6207de8-e2db-409d-962b-77873c07c6a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2440883720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2440883720
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.4060780751
Short name T70
Test name
Test status
Simulation time 4423730481 ps
CPU time 27.36 seconds
Started Dec 27 12:25:07 PM PST 23
Finished Dec 27 12:25:38 PM PST 23
Peak memory 202920 kb
Host smart-1c23d10a-fb4c-422a-b14d-8a5322f47a13
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060780751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4060780751
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2675894380
Short name T362
Test name
Test status
Simulation time 12958298280 ps
CPU time 34.71 seconds
Started Dec 27 12:25:03 PM PST 23
Finished Dec 27 12:25:41 PM PST 23
Peak memory 202984 kb
Host smart-28be73b1-3ac7-40f1-8d36-f549461fdfc4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2675894380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2675894380
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3333537577
Short name T658
Test name
Test status
Simulation time 30136687 ps
CPU time 2.34 seconds
Started Dec 27 12:25:07 PM PST 23
Finished Dec 27 12:25:13 PM PST 23
Peak memory 202840 kb
Host smart-0b5557c6-9bf7-4765-9f8a-1ec57b0e0262
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333537577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3333537577
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.230552178
Short name T732
Test name
Test status
Simulation time 1083865702 ps
CPU time 62.21 seconds
Started Dec 27 12:26:04 PM PST 23
Finished Dec 27 12:27:15 PM PST 23
Peak memory 205304 kb
Host smart-8ed4b2d0-f376-42e8-8b10-5bd9e20e7510
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=230552178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.230552178
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3709631952
Short name T396
Test name
Test status
Simulation time 4611758989 ps
CPU time 78.6 seconds
Started Dec 27 12:19:58 PM PST 23
Finished Dec 27 12:21:18 PM PST 23
Peak memory 211292 kb
Host smart-5a7cc002-44bf-40d1-8af5-bd363fe46818
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3709631952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3709631952
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2501441217
Short name T293
Test name
Test status
Simulation time 61845700 ps
CPU time 7.5 seconds
Started Dec 27 12:26:03 PM PST 23
Finished Dec 27 12:26:19 PM PST 23
Peak memory 205076 kb
Host smart-6fdc0354-f1a9-4861-ba69-38f99a527522
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2501441217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand
_reset.2501441217
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.546273689
Short name T790
Test name
Test status
Simulation time 446377836 ps
CPU time 41.89 seconds
Started Dec 27 12:26:58 PM PST 23
Finished Dec 27 12:28:01 PM PST 23
Peak memory 206420 kb
Host smart-7ffa2e9b-ef91-401f-a313-6f28ea279d94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=546273689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese
t_error.546273689
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2284969505
Short name T314
Test name
Test status
Simulation time 103521475 ps
CPU time 15.71 seconds
Started Dec 27 12:28:26 PM PST 23
Finished Dec 27 12:29:29 PM PST 23
Peak memory 203668 kb
Host smart-1912c1a2-ae17-467a-b1eb-de8c98cfc96b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2284969505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2284969505
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1934988198
Short name T434
Test name
Test status
Simulation time 121710017 ps
CPU time 4.23 seconds
Started Dec 27 12:27:55 PM PST 23
Finished Dec 27 12:28:32 PM PST 23
Peak memory 203064 kb
Host smart-5d24ad07-bebf-44f0-bbfe-ce09bb9a2668
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1934988198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1934988198
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1315923301
Short name T852
Test name
Test status
Simulation time 59153176889 ps
CPU time 283.56 seconds
Started Dec 27 12:27:53 PM PST 23
Finished Dec 27 12:33:09 PM PST 23
Peak memory 205884 kb
Host smart-7ece9965-a46a-463d-8b20-efc3989b7d38
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1315923301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.1315923301
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2365693361
Short name T101
Test name
Test status
Simulation time 238488542 ps
CPU time 7.25 seconds
Started Dec 27 12:28:58 PM PST 23
Finished Dec 27 12:30:01 PM PST 23
Peak memory 202896 kb
Host smart-6444f6d5-da7e-4c0d-a2d9-7eb1a653c344
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2365693361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2365693361
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.2890532354
Short name T384
Test name
Test status
Simulation time 213504962 ps
CPU time 16.72 seconds
Started Dec 27 12:28:00 PM PST 23
Finished Dec 27 12:28:50 PM PST 23
Peak memory 202996 kb
Host smart-2dc10bf8-928b-49dd-99b1-7251f11c27ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2890532354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2890532354
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.2773347948
Short name T613
Test name
Test status
Simulation time 236815727 ps
CPU time 25.05 seconds
Started Dec 27 12:27:53 PM PST 23
Finished Dec 27 12:28:51 PM PST 23
Peak memory 210968 kb
Host smart-70fd4bd5-f72c-4ec5-a279-2ea6b03e130a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2773347948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2773347948
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.21297382
Short name T748
Test name
Test status
Simulation time 33405337939 ps
CPU time 140.47 seconds
Started Dec 27 12:27:56 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 211136 kb
Host smart-858cdbcc-b021-4c09-ab34-aa4010ba0a20
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=21297382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.21297382
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3887732699
Short name T548
Test name
Test status
Simulation time 17706239188 ps
CPU time 180.71 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:31:39 PM PST 23
Peak memory 204732 kb
Host smart-8f1ae7ea-2a00-4bff-a86b-0340676c7e28
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3887732699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3887732699
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2804009441
Short name T725
Test name
Test status
Simulation time 278263638 ps
CPU time 17.83 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:28:56 PM PST 23
Peak memory 211080 kb
Host smart-9225b735-d82e-409f-b39c-4c574f26e92a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804009441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2804009441
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.2874998282
Short name T801
Test name
Test status
Simulation time 2691914639 ps
CPU time 14.87 seconds
Started Dec 27 12:28:19 PM PST 23
Finished Dec 27 12:29:19 PM PST 23
Peak memory 202880 kb
Host smart-88ef6650-6e60-4e92-a472-2dc56246d97a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2874998282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2874998282
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.3912526347
Short name T766
Test name
Test status
Simulation time 173157380 ps
CPU time 3.5 seconds
Started Dec 27 12:28:21 PM PST 23
Finished Dec 27 12:29:10 PM PST 23
Peak memory 203008 kb
Host smart-7ba336ee-41a1-4b75-bd90-7f0be33a2791
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3912526347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3912526347
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.4081657997
Short name T561
Test name
Test status
Simulation time 24309855279 ps
CPU time 35.66 seconds
Started Dec 27 12:27:49 PM PST 23
Finished Dec 27 12:28:57 PM PST 23
Peak memory 202928 kb
Host smart-05bce2e7-51fd-4e33-98c0-78f662399a50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081657997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.4081657997
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.156160860
Short name T603
Test name
Test status
Simulation time 4083140526 ps
CPU time 31.08 seconds
Started Dec 27 12:28:03 PM PST 23
Finished Dec 27 12:29:07 PM PST 23
Peak memory 203060 kb
Host smart-74019231-018a-4784-abd7-ef6e9b99a0e3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=156160860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.156160860
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1684066946
Short name T675
Test name
Test status
Simulation time 31715659 ps
CPU time 2.02 seconds
Started Dec 27 12:29:13 PM PST 23
Finished Dec 27 12:30:10 PM PST 23
Peak memory 202596 kb
Host smart-a316110d-f299-4e8e-be77-4b6352b8b6fb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684066946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1684066946
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.890519648
Short name T804
Test name
Test status
Simulation time 14177636742 ps
CPU time 149.31 seconds
Started Dec 27 12:28:02 PM PST 23
Finished Dec 27 12:31:05 PM PST 23
Peak memory 211132 kb
Host smart-daf83786-6622-4ee3-a9e7-52dd3bb7c5ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=890519648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.890519648
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.691481588
Short name T794
Test name
Test status
Simulation time 1508179500 ps
CPU time 43.43 seconds
Started Dec 27 12:29:11 PM PST 23
Finished Dec 27 12:30:49 PM PST 23
Peak memory 211100 kb
Host smart-0d9a1e2b-6a44-413f-8b43-661906fc52b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=691481588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.691481588
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2099417405
Short name T32
Test name
Test status
Simulation time 498019593 ps
CPU time 214.67 seconds
Started Dec 27 12:27:51 PM PST 23
Finished Dec 27 12:31:58 PM PST 23
Peak memory 207420 kb
Host smart-d3386e56-315c-465c-ad75-14476b3c36ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2099417405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.2099417405
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1262954816
Short name T610
Test name
Test status
Simulation time 1202210042 ps
CPU time 36.91 seconds
Started Dec 27 12:28:00 PM PST 23
Finished Dec 27 12:29:11 PM PST 23
Peak memory 206524 kb
Host smart-a00c3df0-4ddb-4ef3-be19-8ae04f7c6531
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1262954816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.1262954816
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.2903277248
Short name T712
Test name
Test status
Simulation time 229835219 ps
CPU time 5.95 seconds
Started Dec 27 12:28:20 PM PST 23
Finished Dec 27 12:29:14 PM PST 23
Peak memory 210996 kb
Host smart-c6bc6160-84d3-44fc-a49a-8313d2a65c6c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2903277248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2903277248
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3671835264
Short name T844
Test name
Test status
Simulation time 30049517 ps
CPU time 2.3 seconds
Started Dec 27 12:27:57 PM PST 23
Finished Dec 27 12:28:33 PM PST 23
Peak memory 203004 kb
Host smart-3268050b-c932-4982-bc8a-5315eababbdc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3671835264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3671835264
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.32170795
Short name T87
Test name
Test status
Simulation time 67329935833 ps
CPU time 491.28 seconds
Started Dec 27 12:29:03 PM PST 23
Finished Dec 27 12:38:09 PM PST 23
Peak memory 206280 kb
Host smart-7001b4f4-c51d-442f-b71b-2730771ea252
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=32170795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow
_rsp.32170795
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.913569817
Short name T635
Test name
Test status
Simulation time 138085516 ps
CPU time 16.85 seconds
Started Dec 27 12:28:27 PM PST 23
Finished Dec 27 12:29:31 PM PST 23
Peak memory 202876 kb
Host smart-edacf26e-4935-49d1-b05e-bd9020552dea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=913569817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.913569817
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.731170336
Short name T771
Test name
Test status
Simulation time 570986350 ps
CPU time 16.19 seconds
Started Dec 27 12:27:56 PM PST 23
Finished Dec 27 12:28:46 PM PST 23
Peak memory 202856 kb
Host smart-8363e0af-eccd-43d1-aedd-cbdbc487e241
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=731170336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.731170336
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.3129271743
Short name T792
Test name
Test status
Simulation time 271290493 ps
CPU time 23.73 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:29:04 PM PST 23
Peak memory 203816 kb
Host smart-d005f8f7-0c53-40ad-ac83-aff7ec523c92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3129271743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3129271743
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3063625691
Short name T565
Test name
Test status
Simulation time 1812778768 ps
CPU time 10.13 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:28:56 PM PST 23
Peak memory 202984 kb
Host smart-bc4d1a73-1d9d-4eb6-8ab6-df1a3a95cd3b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063625691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3063625691
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2586256113
Short name T629
Test name
Test status
Simulation time 24542123032 ps
CPU time 207.02 seconds
Started Dec 27 12:27:59 PM PST 23
Finished Dec 27 12:31:59 PM PST 23
Peak memory 211232 kb
Host smart-8c8ccb3d-3385-4c01-ac9b-721ccca15c81
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2586256113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2586256113
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.4079331260
Short name T147
Test name
Test status
Simulation time 42593532 ps
CPU time 4.03 seconds
Started Dec 27 12:28:00 PM PST 23
Finished Dec 27 12:28:38 PM PST 23
Peak memory 203564 kb
Host smart-81cf1440-1616-46b4-9275-45659fe529f4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079331260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.4079331260
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.20927992
Short name T805
Test name
Test status
Simulation time 709309754 ps
CPU time 17.04 seconds
Started Dec 27 12:27:50 PM PST 23
Finished Dec 27 12:28:39 PM PST 23
Peak memory 202792 kb
Host smart-986930c4-677d-4324-bcec-40ec815d9666
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20927992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.20927992
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.3970097259
Short name T377
Test name
Test status
Simulation time 39613855 ps
CPU time 2.44 seconds
Started Dec 27 12:28:41 PM PST 23
Finished Dec 27 12:29:35 PM PST 23
Peak memory 203024 kb
Host smart-2472c967-46c9-4e97-b965-435703688397
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3970097259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3970097259
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3302581565
Short name T186
Test name
Test status
Simulation time 12672822443 ps
CPU time 36.83 seconds
Started Dec 27 12:28:03 PM PST 23
Finished Dec 27 12:29:14 PM PST 23
Peak memory 203036 kb
Host smart-aa10f1f9-7e0e-4225-b0c4-f7808cbf6876
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302581565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3302581565
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.671152355
Short name T611
Test name
Test status
Simulation time 29031148 ps
CPU time 2.29 seconds
Started Dec 27 12:28:16 PM PST 23
Finished Dec 27 12:29:01 PM PST 23
Peak memory 202912 kb
Host smart-475f3f4c-a1e7-473a-b1a6-0a73100d1d2c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671152355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.671152355
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.3343425548
Short name T114
Test name
Test status
Simulation time 55019128763 ps
CPU time 305.69 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:33:46 PM PST 23
Peak memory 206372 kb
Host smart-888e929b-959f-4454-b4dc-298cb8804bc1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3343425548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3343425548
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.881991380
Short name T724
Test name
Test status
Simulation time 2884869651 ps
CPU time 50.79 seconds
Started Dec 27 12:28:01 PM PST 23
Finished Dec 27 12:29:26 PM PST 23
Peak memory 204304 kb
Host smart-d72a9a89-7fa7-4403-969c-082a03dcabbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=881991380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.881991380
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.68538546
Short name T282
Test name
Test status
Simulation time 342208226 ps
CPU time 135.41 seconds
Started Dec 27 12:27:52 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 207612 kb
Host smart-f331930c-27ea-4e1d-bf32-c5d0ce97b338
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=68538546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_
reset.68538546
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.405207950
Short name T449
Test name
Test status
Simulation time 1590495183 ps
CPU time 266.51 seconds
Started Dec 27 12:29:35 PM PST 23
Finished Dec 27 12:34:56 PM PST 23
Peak memory 219396 kb
Host smart-d9bd6eb5-7fc2-4e45-a9dd-281efb502ba9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=405207950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_res
et_error.405207950
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3974019741
Short name T486
Test name
Test status
Simulation time 27972177 ps
CPU time 1.82 seconds
Started Dec 27 12:27:58 PM PST 23
Finished Dec 27 12:28:34 PM PST 23
Peak memory 202916 kb
Host smart-9baad9c8-b235-411f-8586-04d2777af6ab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3974019741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3974019741
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.2082526920
Short name T513
Test name
Test status
Simulation time 949718564 ps
CPU time 29.25 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:29:12 PM PST 23
Peak memory 203016 kb
Host smart-73d2ce12-7f2b-45e8-a331-8136c3bdab65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2082526920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2082526920
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1151321183
Short name T841
Test name
Test status
Simulation time 14529815223 ps
CPU time 114.78 seconds
Started Dec 27 12:27:57 PM PST 23
Finished Dec 27 12:30:25 PM PST 23
Peak memory 211016 kb
Host smart-223fc25d-1fb7-459f-a310-6297bef41ebb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1151321183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.1151321183
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2661229973
Short name T7
Test name
Test status
Simulation time 123863631 ps
CPU time 17.28 seconds
Started Dec 27 12:29:30 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 203028 kb
Host smart-42f5feae-420c-4c50-8111-5eeb95ec46bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2661229973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2661229973
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.1739600637
Short name T148
Test name
Test status
Simulation time 184450369 ps
CPU time 15.31 seconds
Started Dec 27 12:27:58 PM PST 23
Finished Dec 27 12:28:47 PM PST 23
Peak memory 202904 kb
Host smart-c5e47d88-c7b4-40d9-8e01-ba90e81e416d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1739600637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1739600637
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.2121562644
Short name T144
Test name
Test status
Simulation time 154145017 ps
CPU time 14.4 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:29:01 PM PST 23
Peak memory 210984 kb
Host smart-995e0b04-8520-4e34-8f8f-bba953d1f622
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2121562644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2121562644
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1262658402
Short name T315
Test name
Test status
Simulation time 15959045067 ps
CPU time 47.13 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:29:31 PM PST 23
Peak memory 211212 kb
Host smart-d63e0262-c028-4f99-bd5b-c59831a2eea7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262658402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1262658402
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3172550911
Short name T456
Test name
Test status
Simulation time 25162912524 ps
CPU time 178.98 seconds
Started Dec 27 12:28:11 PM PST 23
Finished Dec 27 12:31:48 PM PST 23
Peak memory 204532 kb
Host smart-f94fd386-2586-4175-baa6-068c21bae2ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3172550911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3172550911
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.152871951
Short name T735
Test name
Test status
Simulation time 80797102 ps
CPU time 7.16 seconds
Started Dec 27 12:28:02 PM PST 23
Finished Dec 27 12:28:43 PM PST 23
Peak memory 203980 kb
Host smart-83196641-7794-48dc-aa6d-80f99573c708
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152871951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.152871951
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.2397551705
Short name T262
Test name
Test status
Simulation time 198389406 ps
CPU time 6.01 seconds
Started Dec 27 12:29:10 PM PST 23
Finished Dec 27 12:30:11 PM PST 23
Peak memory 203232 kb
Host smart-f0fefb19-a732-44dd-8e9d-b6a86c1cd809
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2397551705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2397551705
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.2790952537
Short name T455
Test name
Test status
Simulation time 30529638 ps
CPU time 2.09 seconds
Started Dec 27 12:27:55 PM PST 23
Finished Dec 27 12:28:30 PM PST 23
Peak memory 202904 kb
Host smart-01e51a1d-990f-48ec-9742-71aea52502bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2790952537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2790952537
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2259116885
Short name T331
Test name
Test status
Simulation time 17395712014 ps
CPU time 42.88 seconds
Started Dec 27 12:28:11 PM PST 23
Finished Dec 27 12:29:32 PM PST 23
Peak memory 203044 kb
Host smart-52c5286f-7f80-499b-b826-b3ae9aef47b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259116885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2259116885
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1381428171
Short name T205
Test name
Test status
Simulation time 7539616612 ps
CPU time 30.71 seconds
Started Dec 27 12:27:52 PM PST 23
Finished Dec 27 12:28:55 PM PST 23
Peak memory 203096 kb
Host smart-d15a3e6e-7d23-4508-981f-8a8e4b496e6d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1381428171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1381428171
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2506093156
Short name T378
Test name
Test status
Simulation time 44741131 ps
CPU time 2.54 seconds
Started Dec 27 12:28:06 PM PST 23
Finished Dec 27 12:28:44 PM PST 23
Peak memory 202796 kb
Host smart-910b89cc-2cf2-4314-9c61-c2d1169d5f83
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506093156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2506093156
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3348342029
Short name T422
Test name
Test status
Simulation time 1167969739 ps
CPU time 124.91 seconds
Started Dec 27 12:31:57 PM PST 23
Finished Dec 27 12:34:47 PM PST 23
Peak memory 206728 kb
Host smart-a401440d-0f0e-4f50-b8bf-3907a2c62eb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3348342029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3348342029
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3996977345
Short name T605
Test name
Test status
Simulation time 6886402721 ps
CPU time 170 seconds
Started Dec 27 12:27:58 PM PST 23
Finished Dec 27 12:31:21 PM PST 23
Peak memory 208416 kb
Host smart-6457e635-1089-48cb-bb93-9acc0bb26bfd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3996977345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3996977345
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.2060502250
Short name T550
Test name
Test status
Simulation time 134606930 ps
CPU time 83.73 seconds
Started Dec 27 12:28:02 PM PST 23
Finished Dec 27 12:30:00 PM PST 23
Peak memory 206628 kb
Host smart-406655e2-df30-4486-980f-562ff29b7c65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2060502250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.2060502250
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3785771560
Short name T530
Test name
Test status
Simulation time 4809335325 ps
CPU time 604.1 seconds
Started Dec 27 12:27:56 PM PST 23
Finished Dec 27 12:38:33 PM PST 23
Peak memory 227620 kb
Host smart-d8b7afe7-e60e-4d80-86b4-d0c141659729
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3785771560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.3785771560
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1990698853
Short name T76
Test name
Test status
Simulation time 736076083 ps
CPU time 28.66 seconds
Started Dec 27 12:28:01 PM PST 23
Finished Dec 27 12:29:03 PM PST 23
Peak memory 211084 kb
Host smart-cd2fc8ee-9e87-4fbf-89bf-7a4105d7a9cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1990698853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1990698853
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.866771260
Short name T851
Test name
Test status
Simulation time 443515196 ps
CPU time 27.49 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:29:10 PM PST 23
Peak memory 211080 kb
Host smart-e2542033-cf6f-429c-8a23-f8f114bebe33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=866771260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.866771260
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.721170833
Short name T135
Test name
Test status
Simulation time 49454415964 ps
CPU time 391.86 seconds
Started Dec 27 12:28:06 PM PST 23
Finished Dec 27 12:35:13 PM PST 23
Peak memory 211132 kb
Host smart-f7276249-f428-41e2-b1b6-776b9907455b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=721170833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slo
w_rsp.721170833
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.523906178
Short name T103
Test name
Test status
Simulation time 119627581 ps
CPU time 4.95 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:28:48 PM PST 23
Peak memory 202848 kb
Host smart-69201773-d4e2-4404-99b3-a0cab12e9bce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=523906178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.523906178
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.3805618778
Short name T843
Test name
Test status
Simulation time 280953707 ps
CPU time 10.39 seconds
Started Dec 27 12:28:03 PM PST 23
Finished Dec 27 12:28:47 PM PST 23
Peak memory 202884 kb
Host smart-042550db-caef-4efa-9552-a1d7608435f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3805618778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3805618778
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.481035954
Short name T692
Test name
Test status
Simulation time 883499844 ps
CPU time 5.93 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:29:55 PM PST 23
Peak memory 203040 kb
Host smart-7930d0b3-45cf-47ba-a1b0-26d6d9cded9f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=481035954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.481035954
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.162790204
Short name T55
Test name
Test status
Simulation time 23721339968 ps
CPU time 215.47 seconds
Started Dec 27 12:28:30 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 211200 kb
Host smart-5b7a6a64-48c7-456e-a44e-12f1fbf26e8c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=162790204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.162790204
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.3462786735
Short name T275
Test name
Test status
Simulation time 214609926 ps
CPU time 22.81 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:29:09 PM PST 23
Peak memory 204084 kb
Host smart-6831a870-afb9-4e21-b824-08d5376839c5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462786735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3462786735
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.4180419915
Short name T37
Test name
Test status
Simulation time 398989627 ps
CPU time 15.59 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:29:32 PM PST 23
Peak memory 203140 kb
Host smart-85e246fa-a39f-4087-80f2-35186f9ef5dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4180419915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.4180419915
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.3149486675
Short name T828
Test name
Test status
Simulation time 30063709 ps
CPU time 2.18 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:28:41 PM PST 23
Peak memory 202992 kb
Host smart-623cba31-63ed-4ba6-b5e8-6ec422709d4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3149486675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3149486675
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2830347800
Short name T320
Test name
Test status
Simulation time 6299443485 ps
CPU time 32.48 seconds
Started Dec 27 12:29:05 PM PST 23
Finished Dec 27 12:30:31 PM PST 23
Peak memory 202996 kb
Host smart-85ce2419-9dba-4a48-8b92-8e2f88961b43
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830347800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2830347800
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1749071639
Short name T185
Test name
Test status
Simulation time 10105438541 ps
CPU time 33.79 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:29:17 PM PST 23
Peak memory 203068 kb
Host smart-292da446-c0b6-4083-b5cf-cc1a4a84b62f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1749071639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1749071639
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3517778092
Short name T831
Test name
Test status
Simulation time 30322911 ps
CPU time 2.24 seconds
Started Dec 27 12:28:06 PM PST 23
Finished Dec 27 12:28:44 PM PST 23
Peak memory 202924 kb
Host smart-2ead5b24-e1bd-4ae3-be73-38d1981742b1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517778092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3517778092
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.1068147515
Short name T689
Test name
Test status
Simulation time 3757175819 ps
CPU time 69.78 seconds
Started Dec 27 12:28:11 PM PST 23
Finished Dec 27 12:29:59 PM PST 23
Peak memory 211204 kb
Host smart-4c98a9f5-eab7-4fc3-8c1f-1ceff9a8f72c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1068147515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1068147515
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.733456295
Short name T803
Test name
Test status
Simulation time 401096128 ps
CPU time 44.77 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:29:24 PM PST 23
Peak memory 204464 kb
Host smart-50172d50-fbe3-43c0-83b9-5ed44f7bd912
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=733456295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.733456295
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3276539953
Short name T595
Test name
Test status
Simulation time 2322836375 ps
CPU time 230.86 seconds
Started Dec 27 12:28:21 PM PST 23
Finished Dec 27 12:32:58 PM PST 23
Peak memory 219568 kb
Host smart-d65ff4b4-a921-4684-9a63-bec0081590b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3276539953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.3276539953
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.4231436925
Short name T424
Test name
Test status
Simulation time 56255332 ps
CPU time 3.02 seconds
Started Dec 27 12:28:02 PM PST 23
Finished Dec 27 12:28:39 PM PST 23
Peak memory 211076 kb
Host smart-bbc3a09e-9b04-45a7-bc0f-719090bc8e2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4231436925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.4231436925
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.3733238442
Short name T29
Test name
Test status
Simulation time 1016612265 ps
CPU time 24.1 seconds
Started Dec 27 12:28:19 PM PST 23
Finished Dec 27 12:29:28 PM PST 23
Peak memory 203980 kb
Host smart-2f1ba442-7e12-4259-a7ce-c6bc85388907
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3733238442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3733238442
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3109432007
Short name T858
Test name
Test status
Simulation time 93367223914 ps
CPU time 547.87 seconds
Started Dec 27 12:27:59 PM PST 23
Finished Dec 27 12:37:40 PM PST 23
Peak memory 205348 kb
Host smart-c0431045-ceec-4967-a6e4-0bc7f2302ea0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3109432007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl
ow_rsp.3109432007
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1389526037
Short name T90
Test name
Test status
Simulation time 1832368639 ps
CPU time 24.38 seconds
Started Dec 27 12:28:20 PM PST 23
Finished Dec 27 12:29:31 PM PST 23
Peak memory 203240 kb
Host smart-d136eaa3-e169-4c11-8b09-3e5f66c62a9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1389526037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1389526037
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.1624065494
Short name T490
Test name
Test status
Simulation time 412443402 ps
CPU time 7.3 seconds
Started Dec 27 12:28:52 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 202820 kb
Host smart-d7f93eea-7ddf-4aa0-a01f-596b2e780848
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1624065494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1624065494
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.4178327813
Short name T641
Test name
Test status
Simulation time 768616927 ps
CPU time 28.22 seconds
Started Dec 27 12:28:06 PM PST 23
Finished Dec 27 12:29:09 PM PST 23
Peak memory 210896 kb
Host smart-8f33accd-1fc6-42c4-88b7-a7d5accf5a18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4178327813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.4178327813
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3048801256
Short name T472
Test name
Test status
Simulation time 45624735464 ps
CPU time 89.16 seconds
Started Dec 27 12:28:10 PM PST 23
Finished Dec 27 12:30:18 PM PST 23
Peak memory 203564 kb
Host smart-4b30ad63-f9a6-4e20-acfe-8cbe25d8c42e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048801256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3048801256
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3611905703
Short name T349
Test name
Test status
Simulation time 75975768424 ps
CPU time 280.34 seconds
Started Dec 27 12:28:10 PM PST 23
Finished Dec 27 12:33:28 PM PST 23
Peak memory 204176 kb
Host smart-e2d4e604-9f71-4b46-8234-44878e0778a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3611905703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3611905703
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.308217527
Short name T547
Test name
Test status
Simulation time 450229863 ps
CPU time 27.26 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:29:07 PM PST 23
Peak memory 211064 kb
Host smart-f94f5853-ebb3-4bba-a80b-248d618d87b4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308217527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.308217527
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.2633510771
Short name T351
Test name
Test status
Simulation time 539728176 ps
CPU time 7.57 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:28:51 PM PST 23
Peak memory 203044 kb
Host smart-59a59eef-6c14-4658-93b1-5b636735fe53
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2633510771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2633510771
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.1958837463
Short name T409
Test name
Test status
Simulation time 33713792 ps
CPU time 1.94 seconds
Started Dec 27 12:28:19 PM PST 23
Finished Dec 27 12:29:06 PM PST 23
Peak memory 202888 kb
Host smart-ba6a8e19-0c2e-4468-903c-25f2a3560fb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1958837463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1958837463
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2381888157
Short name T849
Test name
Test status
Simulation time 5291867506 ps
CPU time 29.76 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:29:41 PM PST 23
Peak memory 202956 kb
Host smart-6e37ed82-283a-4f62-aa63-743afc509e25
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381888157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2381888157
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1624945645
Short name T160
Test name
Test status
Simulation time 7767901603 ps
CPU time 33.44 seconds
Started Dec 27 12:28:17 PM PST 23
Finished Dec 27 12:29:33 PM PST 23
Peak memory 202936 kb
Host smart-553cd7df-0e62-4a57-8d13-8828a2db9bd7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1624945645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1624945645
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.268028075
Short name T498
Test name
Test status
Simulation time 88331454 ps
CPU time 2.23 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:28:42 PM PST 23
Peak memory 202856 kb
Host smart-340033d8-ee6d-4782-b44e-adf412e77d6c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268028075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.268028075
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2840389626
Short name T412
Test name
Test status
Simulation time 1422511726 ps
CPU time 53.85 seconds
Started Dec 27 12:28:02 PM PST 23
Finished Dec 27 12:29:30 PM PST 23
Peak memory 206572 kb
Host smart-561586a9-9cc6-4c99-a4fd-91e2b24a3906
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2840389626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2840389626
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3681858103
Short name T354
Test name
Test status
Simulation time 13654865639 ps
CPU time 184.76 seconds
Started Dec 27 12:28:43 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 205140 kb
Host smart-226515d0-2104-4ad9-afad-f38d49e34131
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3681858103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3681858103
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.703795022
Short name T435
Test name
Test status
Simulation time 478632260 ps
CPU time 127.01 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:31:04 PM PST 23
Peak memory 207188 kb
Host smart-6cf0054e-b110-4f17-b80b-9ce1c908be2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=703795022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand
_reset.703795022
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2515584156
Short name T417
Test name
Test status
Simulation time 45189956 ps
CPU time 4.97 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:28:42 PM PST 23
Peak memory 211084 kb
Host smart-94d2639f-00ff-4781-933c-e586e36f0c86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2515584156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2515584156
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3495916719
Short name T816
Test name
Test status
Simulation time 800872925 ps
CPU time 15.73 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:28:53 PM PST 23
Peak memory 203044 kb
Host smart-4d70a27a-cd71-4bca-b17f-632270c574fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3495916719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3495916719
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.288410577
Short name T267
Test name
Test status
Simulation time 56850812236 ps
CPU time 451.45 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:36:15 PM PST 23
Peak memory 211200 kb
Host smart-897dae6f-a5ba-4649-bbb0-de255f91f9c5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=288410577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo
w_rsp.288410577
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2460199562
Short name T231
Test name
Test status
Simulation time 161057951 ps
CPU time 16.45 seconds
Started Dec 27 12:27:56 PM PST 23
Finished Dec 27 12:28:46 PM PST 23
Peak memory 203020 kb
Host smart-1705d6e3-e619-4c29-82d2-476524caa4c5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2460199562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2460199562
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.652116495
Short name T17
Test name
Test status
Simulation time 253294123 ps
CPU time 12.64 seconds
Started Dec 27 12:28:36 PM PST 23
Finished Dec 27 12:29:39 PM PST 23
Peak memory 202932 kb
Host smart-eba86157-fd2f-45de-9433-5e7ca79fc670
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=652116495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.652116495
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.4237516292
Short name T79
Test name
Test status
Simulation time 1944312266 ps
CPU time 27.72 seconds
Started Dec 27 12:28:36 PM PST 23
Finished Dec 27 12:29:54 PM PST 23
Peak memory 204060 kb
Host smart-5fba3467-848a-4f6a-ba8f-7677ca1dc46e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4237516292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.4237516292
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1175015393
Short name T260
Test name
Test status
Simulation time 116716752402 ps
CPU time 272.09 seconds
Started Dec 27 12:29:00 PM PST 23
Finished Dec 27 12:34:28 PM PST 23
Peak memory 211224 kb
Host smart-6eaedcda-13f1-4750-b0d0-838a55690e7e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175015393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1175015393
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2464250208
Short name T71
Test name
Test status
Simulation time 21336545216 ps
CPU time 156.22 seconds
Started Dec 27 12:27:59 PM PST 23
Finished Dec 27 12:31:08 PM PST 23
Peak memory 211228 kb
Host smart-3d2e7b3d-107b-4447-90eb-cf8b2adea81b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2464250208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2464250208
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.159223650
Short name T523
Test name
Test status
Simulation time 23239748 ps
CPU time 3.31 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:28:45 PM PST 23
Peak memory 203000 kb
Host smart-5e2985b5-cbe2-42d6-bdc5-fa76be4167bd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159223650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.159223650
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.218939885
Short name T6
Test name
Test status
Simulation time 427884649 ps
CPU time 8.57 seconds
Started Dec 27 12:29:05 PM PST 23
Finished Dec 27 12:30:08 PM PST 23
Peak memory 202816 kb
Host smart-2e614bcd-e310-4668-b493-3bd489f275f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=218939885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.218939885
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.459352232
Short name T708
Test name
Test status
Simulation time 170870981 ps
CPU time 3.03 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:28:49 PM PST 23
Peak memory 202984 kb
Host smart-7c297dc9-50ed-4ba6-92ca-a5634d5b7327
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=459352232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.459352232
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.4167927762
Short name T327
Test name
Test status
Simulation time 17196744397 ps
CPU time 31.27 seconds
Started Dec 27 12:27:59 PM PST 23
Finished Dec 27 12:29:09 PM PST 23
Peak memory 202960 kb
Host smart-86e73fe0-b7fd-4e69-ba57-55c3d1896ff1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167927762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.4167927762
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3293971349
Short name T153
Test name
Test status
Simulation time 3713858187 ps
CPU time 21.02 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:29:03 PM PST 23
Peak memory 202976 kb
Host smart-0d6d86b6-da22-457e-a2a0-57e5e0285cdc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3293971349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3293971349
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2391301109
Short name T234
Test name
Test status
Simulation time 66597129 ps
CPU time 1.97 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:28:39 PM PST 23
Peak memory 202900 kb
Host smart-5a5fa1b8-cf63-4855-bc95-f8fcb10c2979
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391301109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2391301109
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.2168000552
Short name T312
Test name
Test status
Simulation time 215151317 ps
CPU time 3.52 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 203028 kb
Host smart-3847de85-0671-4351-a1a0-2766d2cadab1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2168000552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2168000552
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.2451680243
Short name T427
Test name
Test status
Simulation time 1045911177 ps
CPU time 72.67 seconds
Started Dec 27 12:28:01 PM PST 23
Finished Dec 27 12:29:48 PM PST 23
Peak memory 206092 kb
Host smart-a799c1a0-637e-4966-aa88-65b2c8866abc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2451680243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2451680243
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.294691182
Short name T438
Test name
Test status
Simulation time 12309757515 ps
CPU time 231.9 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:32:38 PM PST 23
Peak memory 209124 kb
Host smart-a3663a93-b166-4f53-910a-98fd974f39f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=294691182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand
_reset.294691182
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.44028579
Short name T723
Test name
Test status
Simulation time 6530423950 ps
CPU time 246.81 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:32:54 PM PST 23
Peak memory 219348 kb
Host smart-b6911d4f-1290-4a63-bba7-9a21c044cc94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=44028579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rese
t_error.44028579
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3269849807
Short name T117
Test name
Test status
Simulation time 176753669 ps
CPU time 8.21 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:29:41 PM PST 23
Peak memory 204148 kb
Host smart-6b947dd4-8487-41b7-94a7-5ba191a6e55f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3269849807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3269849807
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3277805918
Short name T110
Test name
Test status
Simulation time 2888811898 ps
CPU time 30.7 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:29:16 PM PST 23
Peak memory 211200 kb
Host smart-57297560-1306-4873-bc42-74d9ee4bffa1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3277805918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3277805918
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3906838261
Short name T41
Test name
Test status
Simulation time 36233244264 ps
CPU time 92.58 seconds
Started Dec 27 12:28:31 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 204096 kb
Host smart-4045ce7e-34df-4cc4-b8a0-a4ec50f5819c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3906838261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.3906838261
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1930740334
Short name T467
Test name
Test status
Simulation time 78875982 ps
CPU time 10.15 seconds
Started Dec 27 12:28:41 PM PST 23
Finished Dec 27 12:29:43 PM PST 23
Peak memory 203044 kb
Host smart-62157784-9c7a-4d3a-ac8a-da92022a703f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1930740334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1930740334
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.2050214273
Short name T560
Test name
Test status
Simulation time 1386160673 ps
CPU time 19.41 seconds
Started Dec 27 12:28:06 PM PST 23
Finished Dec 27 12:29:01 PM PST 23
Peak memory 203036 kb
Host smart-17d92e54-1228-49ed-b51d-394d094b470a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2050214273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2050214273
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.3045558213
Short name T298
Test name
Test status
Simulation time 238920130 ps
CPU time 4.91 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:30:20 PM PST 23
Peak memory 202932 kb
Host smart-02429f07-f43b-4ad1-80ec-724a5d6acf7d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3045558213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3045558213
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.183009654
Short name T431
Test name
Test status
Simulation time 7970956179 ps
CPU time 48.65 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:29:29 PM PST 23
Peak memory 211144 kb
Host smart-3b112937-97a6-4507-b9f0-34b6f0dd8636
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=183009654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.183009654
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3849026528
Short name T318
Test name
Test status
Simulation time 33832702 ps
CPU time 4.57 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:28:48 PM PST 23
Peak memory 202964 kb
Host smart-ec68780e-5aef-4dd5-ab06-8f8e4f8a1dfb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849026528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3849026528
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.471365172
Short name T30
Test name
Test status
Simulation time 769099394 ps
CPU time 6.49 seconds
Started Dec 27 12:29:20 PM PST 23
Finished Dec 27 12:30:21 PM PST 23
Peak memory 202860 kb
Host smart-40c9ee32-08da-464d-a82a-79b77620d204
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=471365172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.471365172
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.799940333
Short name T376
Test name
Test status
Simulation time 201615613 ps
CPU time 2.73 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:30:31 PM PST 23
Peak memory 202804 kb
Host smart-40cf09d2-a914-4f06-9ba4-ae034e167a58
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=799940333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.799940333
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2575362848
Short name T515
Test name
Test status
Simulation time 5624652209 ps
CPU time 25.84 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:44 PM PST 23
Peak memory 202960 kb
Host smart-06b989aa-259a-44ce-a3a5-01b9710905c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575362848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2575362848
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3193453809
Short name T775
Test name
Test status
Simulation time 22240761005 ps
CPU time 47.95 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:29:26 PM PST 23
Peak memory 202964 kb
Host smart-55264fd0-2361-4541-bdf8-0496c3beec09
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3193453809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3193453809
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2740365333
Short name T306
Test name
Test status
Simulation time 35498761 ps
CPU time 2.28 seconds
Started Dec 27 12:28:06 PM PST 23
Finished Dec 27 12:28:43 PM PST 23
Peak memory 202880 kb
Host smart-3cd2e707-e5c1-4520-989d-f83fb2ce3202
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740365333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2740365333
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.666000753
Short name T92
Test name
Test status
Simulation time 1854621920 ps
CPU time 32.48 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:29:17 PM PST 23
Peak memory 211080 kb
Host smart-11da89dc-6f05-4988-80c2-1a4513a3683f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=666000753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.666000753
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1254664706
Short name T683
Test name
Test status
Simulation time 2848493944 ps
CPU time 147.84 seconds
Started Dec 27 12:29:20 PM PST 23
Finished Dec 27 12:32:43 PM PST 23
Peak memory 208636 kb
Host smart-81af4405-7f30-4a67-a0f3-54f33e5ec2e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1254664706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1254664706
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1425130056
Short name T319
Test name
Test status
Simulation time 154573877 ps
CPU time 70.93 seconds
Started Dec 27 12:29:40 PM PST 23
Finished Dec 27 12:31:45 PM PST 23
Peak memory 206368 kb
Host smart-cdcff880-3db2-4976-8c89-e9cbd2032dee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1425130056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.1425130056
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1277557650
Short name T195
Test name
Test status
Simulation time 579290697 ps
CPU time 22.41 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:29:05 PM PST 23
Peak memory 204284 kb
Host smart-bdcbe97b-9b96-4075-a1cd-c207038408e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1277557650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1277557650
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.102328236
Short name T700
Test name
Test status
Simulation time 365920747 ps
CPU time 4.25 seconds
Started Dec 27 12:28:06 PM PST 23
Finished Dec 27 12:28:45 PM PST 23
Peak memory 203040 kb
Host smart-77639d14-76df-4fac-88c8-ac82aaaa8e24
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102328236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.102328236
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.170478774
Short name T278
Test name
Test status
Simulation time 350239358234 ps
CPU time 852.15 seconds
Started Dec 27 12:29:59 PM PST 23
Finished Dec 27 12:45:03 PM PST 23
Peak memory 206920 kb
Host smart-30ad77dc-79ef-43ef-9faa-943ee4e3331a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=170478774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo
w_rsp.170478774
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2982146431
Short name T721
Test name
Test status
Simulation time 84590670 ps
CPU time 10.12 seconds
Started Dec 27 12:30:05 PM PST 23
Finished Dec 27 12:31:06 PM PST 23
Peak memory 202856 kb
Host smart-ff4a0af7-439c-4f4e-9fae-56426bc2befa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2982146431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2982146431
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.2572802858
Short name T120
Test name
Test status
Simulation time 165520912 ps
CPU time 17.02 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:29:04 PM PST 23
Peak memory 202996 kb
Host smart-00e9fc28-1c88-47e0-a284-9838545c290f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2572802858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2572802858
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.3668907959
Short name T77
Test name
Test status
Simulation time 248819885 ps
CPU time 9.37 seconds
Started Dec 27 12:28:16 PM PST 23
Finished Dec 27 12:29:07 PM PST 23
Peak memory 203764 kb
Host smart-5da069a1-4d38-4170-b82d-e8aad65a82c1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3668907959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3668907959
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3058007622
Short name T111
Test name
Test status
Simulation time 50208707953 ps
CPU time 221.01 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:36:32 PM PST 23
Peak memory 210964 kb
Host smart-52d52358-0453-4302-a8be-492ab0958b3d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058007622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3058007622
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1765957901
Short name T462
Test name
Test status
Simulation time 98073490479 ps
CPU time 222.07 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:32:24 PM PST 23
Peak memory 211208 kb
Host smart-21821df4-5002-4d80-85f1-a0a4775b929f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1765957901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1765957901
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2445210058
Short name T196
Test name
Test status
Simulation time 94713165 ps
CPU time 7.54 seconds
Started Dec 27 12:28:16 PM PST 23
Finished Dec 27 12:29:04 PM PST 23
Peak memory 211020 kb
Host smart-c55341d5-819e-400d-8896-7c8776e40f64
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445210058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2445210058
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.3977510537
Short name T379
Test name
Test status
Simulation time 230665180 ps
CPU time 15.35 seconds
Started Dec 27 12:28:17 PM PST 23
Finished Dec 27 12:29:15 PM PST 23
Peak memory 203304 kb
Host smart-0b19ecb8-a89a-4d3a-8193-bc0695a3e0be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3977510537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3977510537
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.928759075
Short name T56
Test name
Test status
Simulation time 29999440 ps
CPU time 1.87 seconds
Started Dec 27 12:29:58 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 202980 kb
Host smart-7bd66c6a-27fb-4108-93d5-20af262cbf2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=928759075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.928759075
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2819325082
Short name T837
Test name
Test status
Simulation time 6246734009 ps
CPU time 29.63 seconds
Started Dec 27 12:29:24 PM PST 23
Finished Dec 27 12:30:48 PM PST 23
Peak memory 202936 kb
Host smart-715f4e9d-1649-45df-a7e1-bb6bb60dae1a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819325082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2819325082
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3681046068
Short name T647
Test name
Test status
Simulation time 5369261252 ps
CPU time 28.34 seconds
Started Dec 27 12:28:23 PM PST 23
Finished Dec 27 12:29:38 PM PST 23
Peak memory 203116 kb
Host smart-47bc68a0-3291-4370-9bb1-95dba0b1c6a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3681046068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3681046068
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1320508528
Short name T855
Test name
Test status
Simulation time 57635091 ps
CPU time 2.06 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:20 PM PST 23
Peak memory 202916 kb
Host smart-98532a10-7742-447c-a9cc-e6ccb720d2a7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320508528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1320508528
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.761347240
Short name T597
Test name
Test status
Simulation time 22729635456 ps
CPU time 253.87 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:33:03 PM PST 23
Peak memory 209420 kb
Host smart-c3c84ab7-04e1-4488-9217-ec2f3ff9fcf8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=761347240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.761347240
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.97709775
Short name T3
Test name
Test status
Simulation time 3059916611 ps
CPU time 100.28 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:30:25 PM PST 23
Peak memory 204260 kb
Host smart-1153e804-7671-4eea-9ff3-5f635b9840f4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=97709775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.97709775
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.125920859
Short name T423
Test name
Test status
Simulation time 4498348618 ps
CPU time 176.37 seconds
Started Dec 27 12:28:11 PM PST 23
Finished Dec 27 12:31:46 PM PST 23
Peak memory 207628 kb
Host smart-bd849570-1d45-4b93-a19b-3da93fe423fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=125920859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand
_reset.125920859
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1318112916
Short name T283
Test name
Test status
Simulation time 2403194890 ps
CPU time 269.09 seconds
Started Dec 27 12:28:03 PM PST 23
Finished Dec 27 12:33:06 PM PST 23
Peak memory 220968 kb
Host smart-a49848fb-2035-4b62-bec3-fba23275f9c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1318112916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.1318112916
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1915592425
Short name T872
Test name
Test status
Simulation time 401133065 ps
CPU time 9.43 seconds
Started Dec 27 12:28:04 PM PST 23
Finished Dec 27 12:28:48 PM PST 23
Peak memory 211232 kb
Host smart-db8cdd8c-4414-4543-8f7a-5ad92cffd1fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1915592425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1915592425
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3007889296
Short name T433
Test name
Test status
Simulation time 478454824 ps
CPU time 25.77 seconds
Started Dec 27 12:29:22 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 203668 kb
Host smart-a0381f04-5e85-4c22-9120-e6c40c8bf221
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3007889296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3007889296
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.3835534153
Short name T292
Test name
Test status
Simulation time 824414117 ps
CPU time 19.1 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:29:04 PM PST 23
Peak memory 203028 kb
Host smart-7bde4334-7e67-43fe-a907-bf274bfb2575
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3835534153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.3835534153
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.1999128115
Short name T607
Test name
Test status
Simulation time 1166325413 ps
CPU time 21.83 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:29:08 PM PST 23
Peak memory 202936 kb
Host smart-001d24b3-7135-4473-89c3-4caf50c95cee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1999128115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1999128115
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.3623739200
Short name T304
Test name
Test status
Simulation time 163671491 ps
CPU time 17.69 seconds
Started Dec 27 12:28:18 PM PST 23
Finished Dec 27 12:29:19 PM PST 23
Peak memory 203580 kb
Host smart-c6260e66-7673-48ae-80c3-c0779003582e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3623739200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3623739200
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2710977474
Short name T407
Test name
Test status
Simulation time 54901792839 ps
CPU time 227.42 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:34:04 PM PST 23
Peak memory 211128 kb
Host smart-eabf46bf-53a6-4d70-8f43-64c900e57851
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710977474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2710977474
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.4041349188
Short name T482
Test name
Test status
Simulation time 16535634454 ps
CPU time 125.21 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 211204 kb
Host smart-ab3c8382-c2f5-4291-ba47-9d13d7608267
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4041349188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4041349188
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.599576297
Short name T866
Test name
Test status
Simulation time 205954247 ps
CPU time 20.25 seconds
Started Dec 27 12:32:11 PM PST 23
Finished Dec 27 12:33:15 PM PST 23
Peak memory 210876 kb
Host smart-c3c188f3-b083-44b2-9f30-27f5e66a7819
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599576297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.599576297
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.3405589726
Short name T822
Test name
Test status
Simulation time 106680302 ps
CPU time 2.83 seconds
Started Dec 27 12:30:26 PM PST 23
Finished Dec 27 12:31:24 PM PST 23
Peak memory 202924 kb
Host smart-3dd5ac3e-a934-40ff-8832-4ed094391a37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3405589726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3405589726
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.4040795984
Short name T492
Test name
Test status
Simulation time 164921969 ps
CPU time 2.62 seconds
Started Dec 27 12:29:30 PM PST 23
Finished Dec 27 12:30:26 PM PST 23
Peak memory 202940 kb
Host smart-aaa1aee2-a10e-487d-a60f-89e24a06e81e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4040795984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.4040795984
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3321581818
Short name T131
Test name
Test status
Simulation time 34383990171 ps
CPU time 60.71 seconds
Started Dec 27 12:28:14 PM PST 23
Finished Dec 27 12:29:55 PM PST 23
Peak memory 202932 kb
Host smart-b5a96a00-e0a4-454a-8751-9fe6f34f4bf0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321581818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3321581818
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3483551404
Short name T754
Test name
Test status
Simulation time 19484767077 ps
CPU time 38.26 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:29:24 PM PST 23
Peak memory 203000 kb
Host smart-0ee07d21-67bc-4cd2-8c57-4e35d923f84d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3483551404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3483551404
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2608886741
Short name T394
Test name
Test status
Simulation time 62517699 ps
CPU time 2.24 seconds
Started Dec 27 12:30:59 PM PST 23
Finished Dec 27 12:31:53 PM PST 23
Peak memory 202928 kb
Host smart-1b328097-db0c-4b4b-968e-ecd7d36aae52
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608886741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2608886741
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.662744935
Short name T177
Test name
Test status
Simulation time 621825400 ps
CPU time 58.98 seconds
Started Dec 27 12:29:00 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 206724 kb
Host smart-c2706bd0-7ec1-48c4-a86b-3b768147f01e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=662744935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.662744935
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3515404912
Short name T864
Test name
Test status
Simulation time 1696888873 ps
CPU time 96.07 seconds
Started Dec 27 12:28:11 PM PST 23
Finished Dec 27 12:30:26 PM PST 23
Peak memory 207424 kb
Host smart-8f638721-0077-45ad-a669-ed711ee18943
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3515404912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3515404912
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.228611959
Short name T47
Test name
Test status
Simulation time 5205385292 ps
CPU time 43.94 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:33:33 PM PST 23
Peak memory 205680 kb
Host smart-8018767f-f4c2-491e-aa55-fe9f3f76b70f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=228611959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand
_reset.228611959
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1370205035
Short name T33
Test name
Test status
Simulation time 7263174471 ps
CPU time 223.63 seconds
Started Dec 27 12:28:11 PM PST 23
Finished Dec 27 12:32:33 PM PST 23
Peak memory 209764 kb
Host smart-d9b9835d-5277-45bd-9816-c1784213e537
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1370205035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.1370205035
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3824534500
Short name T666
Test name
Test status
Simulation time 48033140 ps
CPU time 2 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:28:47 PM PST 23
Peak memory 202860 kb
Host smart-db756b0c-e6c6-41d4-bf36-33826ef96a89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3824534500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3824534500
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.2039863980
Short name T642
Test name
Test status
Simulation time 1361946500 ps
CPU time 15.34 seconds
Started Dec 27 12:28:45 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 204676 kb
Host smart-8656ed70-ea58-4d3e-800e-5a1ed96e1f18
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2039863980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2039863980
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1565745815
Short name T109
Test name
Test status
Simulation time 16706661011 ps
CPU time 90.35 seconds
Started Dec 27 12:29:12 PM PST 23
Finished Dec 27 12:31:36 PM PST 23
Peak memory 205260 kb
Host smart-79f83029-3bc3-4461-81c1-4a952bba1274
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1565745815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.1565745815
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.978496213
Short name T752
Test name
Test status
Simulation time 152303201 ps
CPU time 16.18 seconds
Started Dec 27 12:28:39 PM PST 23
Finished Dec 27 12:29:47 PM PST 23
Peak memory 203064 kb
Host smart-c30943b4-68b4-45f2-9d56-2ec7f8143551
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=978496213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.978496213
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.1987466453
Short name T711
Test name
Test status
Simulation time 1613311180 ps
CPU time 19.38 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:29:07 PM PST 23
Peak memory 202932 kb
Host smart-49f41465-8679-442b-9ef5-09dee07f2f2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1987466453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1987466453
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.2084784462
Short name T268
Test name
Test status
Simulation time 127118127 ps
CPU time 3.56 seconds
Started Dec 27 12:28:12 PM PST 23
Finished Dec 27 12:28:54 PM PST 23
Peak memory 202620 kb
Host smart-6db16890-8ce7-40c3-a61c-97d2a1f69999
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2084784462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2084784462
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.242251906
Short name T168
Test name
Test status
Simulation time 45307766421 ps
CPU time 185.58 seconds
Started Dec 27 12:29:14 PM PST 23
Finished Dec 27 12:33:14 PM PST 23
Peak memory 204276 kb
Host smart-c371baa4-3c9b-47c9-b1fc-2c6815523c30
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=242251906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.242251906
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.648666460
Short name T152
Test name
Test status
Simulation time 28352606012 ps
CPU time 144.23 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:33:05 PM PST 23
Peak memory 210660 kb
Host smart-15838895-695f-4e88-b9dd-cca6ea201e07
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=648666460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.648666460
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3933047783
Short name T174
Test name
Test status
Simulation time 78150931 ps
CPU time 6.29 seconds
Started Dec 27 12:28:12 PM PST 23
Finished Dec 27 12:28:58 PM PST 23
Peak memory 203768 kb
Host smart-a380c385-b268-46a8-a22e-bec17f5f1ebe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933047783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3933047783
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.1984285309
Short name T662
Test name
Test status
Simulation time 146930217 ps
CPU time 10.54 seconds
Started Dec 27 12:28:12 PM PST 23
Finished Dec 27 12:29:02 PM PST 23
Peak memory 203140 kb
Host smart-7b25d6b1-923e-4354-8010-a9b01dbc7a8a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1984285309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1984285309
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.1591276722
Short name T871
Test name
Test status
Simulation time 39010682 ps
CPU time 2.15 seconds
Started Dec 27 12:28:11 PM PST 23
Finished Dec 27 12:28:52 PM PST 23
Peak memory 203012 kb
Host smart-24b357e1-d0e9-4112-abf9-e6a285b803b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1591276722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1591276722
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.10548776
Short name T583
Test name
Test status
Simulation time 12188488668 ps
CPU time 28.8 seconds
Started Dec 27 12:28:24 PM PST 23
Finished Dec 27 12:29:40 PM PST 23
Peak memory 202900 kb
Host smart-48cb40a5-9fe1-4d4d-8695-f32fd6a44d98
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=10548776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.10548776
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.241872056
Short name T40
Test name
Test status
Simulation time 4663552139 ps
CPU time 34.3 seconds
Started Dec 27 12:28:23 PM PST 23
Finished Dec 27 12:29:44 PM PST 23
Peak memory 202892 kb
Host smart-6caf7919-2e1d-458b-94db-84b58ca0fa55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=241872056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.241872056
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.734304796
Short name T233
Test name
Test status
Simulation time 51688625 ps
CPU time 2.07 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:30:30 PM PST 23
Peak memory 202864 kb
Host smart-bce027a2-137a-43d4-9472-e37477383bad
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734304796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.734304796
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.1337975678
Short name T618
Test name
Test status
Simulation time 496349119 ps
CPU time 52.07 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:31:20 PM PST 23
Peak memory 211120 kb
Host smart-6a423938-9060-4653-8222-7dca1a5bacde
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1337975678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1337975678
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1027513300
Short name T23
Test name
Test status
Simulation time 5137816089 ps
CPU time 145.83 seconds
Started Dec 27 12:28:12 PM PST 23
Finished Dec 27 12:31:16 PM PST 23
Peak memory 205076 kb
Host smart-816f2fc0-75ab-4e1d-97cc-b1eaec8a6258
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1027513300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1027513300
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3517964522
Short name T415
Test name
Test status
Simulation time 152373109 ps
CPU time 46.25 seconds
Started Dec 27 12:29:25 PM PST 23
Finished Dec 27 12:31:06 PM PST 23
Peak memory 205868 kb
Host smart-3b529fa4-29ba-458f-ac8b-2ec6d8f1c824
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3517964522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.3517964522
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.1547546065
Short name T27
Test name
Test status
Simulation time 2118396240 ps
CPU time 225.09 seconds
Started Dec 27 12:28:17 PM PST 23
Finished Dec 27 12:32:44 PM PST 23
Peak memory 211020 kb
Host smart-204b8028-d249-4a95-beed-690cafb7dce0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1547546065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.1547546065
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2778220931
Short name T181
Test name
Test status
Simulation time 1102596450 ps
CPU time 14.25 seconds
Started Dec 27 12:28:33 PM PST 23
Finished Dec 27 12:29:37 PM PST 23
Peak memory 203952 kb
Host smart-f2fee3bc-fff0-48e3-96fa-1f5ae7190baf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2778220931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2778220931
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.468341299
Short name T538
Test name
Test status
Simulation time 131449559 ps
CPU time 10.02 seconds
Started Dec 27 12:25:36 PM PST 23
Finished Dec 27 12:25:54 PM PST 23
Peak memory 203260 kb
Host smart-379ecf60-5f72-4b39-9bcd-82f49ce2d186
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=468341299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.468341299
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3467197758
Short name T250
Test name
Test status
Simulation time 103107037940 ps
CPU time 765.06 seconds
Started Dec 27 12:26:04 PM PST 23
Finished Dec 27 12:38:58 PM PST 23
Peak memory 210932 kb
Host smart-e9faeabe-fc1c-46f4-9d7e-203c92e8db03
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3467197758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo
w_rsp.3467197758
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.4136868192
Short name T476
Test name
Test status
Simulation time 363367498 ps
CPU time 10.75 seconds
Started Dec 27 12:31:47 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 202696 kb
Host smart-4773713b-cd97-4142-a7a3-32714e242b2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4136868192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.4136868192
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.397586372
Short name T336
Test name
Test status
Simulation time 172842866 ps
CPU time 12.55 seconds
Started Dec 27 12:21:36 PM PST 23
Finished Dec 27 12:21:49 PM PST 23
Peak memory 202812 kb
Host smart-436b4ca6-fa0b-4de8-90e6-d791e0b40d69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=397586372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.397586372
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.4265722351
Short name T734
Test name
Test status
Simulation time 177095228 ps
CPU time 4.92 seconds
Started Dec 27 12:25:44 PM PST 23
Finished Dec 27 12:25:56 PM PST 23
Peak memory 202016 kb
Host smart-6f3ebc40-6bc5-47eb-ba67-4386425d08de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4265722351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.4265722351
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3283286076
Short name T161
Test name
Test status
Simulation time 53843234530 ps
CPU time 159.77 seconds
Started Dec 27 12:26:08 PM PST 23
Finished Dec 27 12:28:57 PM PST 23
Peak memory 211032 kb
Host smart-672d2240-8e28-4c58-8447-13ddeeae7e09
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283286076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3283286076
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.33910305
Short name T400
Test name
Test status
Simulation time 79056883817 ps
CPU time 218.34 seconds
Started Dec 27 12:26:03 PM PST 23
Finished Dec 27 12:29:50 PM PST 23
Peak memory 204312 kb
Host smart-1bf68887-c318-4a5b-bf8f-3aba7154d190
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=33910305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.33910305
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2209755069
Short name T743
Test name
Test status
Simulation time 570346046 ps
CPU time 26.56 seconds
Started Dec 27 12:21:20 PM PST 23
Finished Dec 27 12:21:47 PM PST 23
Peak memory 211128 kb
Host smart-a23272ef-3195-4f67-96a5-b5c0d2bf5e70
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209755069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2209755069
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.3045921244
Short name T289
Test name
Test status
Simulation time 50680892 ps
CPU time 3.74 seconds
Started Dec 27 12:26:52 PM PST 23
Finished Dec 27 12:27:16 PM PST 23
Peak memory 202572 kb
Host smart-8385bc99-ec84-4b50-b665-a64af62c5e00
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3045921244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3045921244
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.1535909959
Short name T299
Test name
Test status
Simulation time 231571402 ps
CPU time 2.88 seconds
Started Dec 27 12:25:44 PM PST 23
Finished Dec 27 12:25:54 PM PST 23
Peak memory 201744 kb
Host smart-ba54cd80-3860-4486-bd12-b3351d9eeaa9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1535909959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1535909959
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1389396569
Short name T248
Test name
Test status
Simulation time 4710128801 ps
CPU time 26.27 seconds
Started Dec 27 12:31:47 PM PST 23
Finished Dec 27 12:33:00 PM PST 23
Peak memory 202752 kb
Host smart-addf8836-5386-485f-b2ef-10686ca0efba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389396569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1389396569
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1648070429
Short name T11
Test name
Test status
Simulation time 11549681896 ps
CPU time 29.25 seconds
Started Dec 27 12:25:44 PM PST 23
Finished Dec 27 12:26:20 PM PST 23
Peak memory 201792 kb
Host smart-d6cf1139-2065-475a-bd6a-246a2db7b440
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1648070429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1648070429
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1927715768
Short name T853
Test name
Test status
Simulation time 25321766 ps
CPU time 2.1 seconds
Started Dec 27 12:26:52 PM PST 23
Finished Dec 27 12:27:15 PM PST 23
Peak memory 202564 kb
Host smart-19f08d91-dedf-476c-8f3e-b7c5854aa5cd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927715768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1927715768
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.1856362363
Short name T690
Test name
Test status
Simulation time 6183045606 ps
CPU time 88.02 seconds
Started Dec 27 12:24:17 PM PST 23
Finished Dec 27 12:25:45 PM PST 23
Peak memory 207580 kb
Host smart-288812b0-75fb-44d5-8df4-91f974cb8e3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1856362363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1856362363
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3641943964
Short name T739
Test name
Test status
Simulation time 3432223029 ps
CPU time 83.83 seconds
Started Dec 27 12:27:29 PM PST 23
Finished Dec 27 12:29:21 PM PST 23
Peak memory 204224 kb
Host smart-26e1d514-4175-4730-8e4b-485e1c0e86d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3641943964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3641943964
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3091810586
Short name T192
Test name
Test status
Simulation time 3020360324 ps
CPU time 463.87 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:36:26 PM PST 23
Peak memory 220684 kb
Host smart-f1ce5df8-b165-4fd2-93cd-57699d9cd900
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3091810586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand
_reset.3091810586
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3030513095
Short name T442
Test name
Test status
Simulation time 2330968248 ps
CPU time 209.32 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:35:35 PM PST 23
Peak memory 210560 kb
Host smart-d21aaa66-237c-4613-bf0c-beea93174893
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3030513095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.3030513095
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.2819124533
Short name T380
Test name
Test status
Simulation time 424768553 ps
CPU time 14.93 seconds
Started Dec 27 12:26:03 PM PST 23
Finished Dec 27 12:26:26 PM PST 23
Peak memory 210916 kb
Host smart-e831b970-c0b3-4869-9196-ded4483a4491
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2819124533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2819124533
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.750444133
Short name T296
Test name
Test status
Simulation time 209741153 ps
CPU time 13.79 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:29:29 PM PST 23
Peak memory 202940 kb
Host smart-365d8e9b-c52c-4f2c-8203-d10e29a937d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=750444133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.750444133
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.3603994549
Short name T800
Test name
Test status
Simulation time 196225233 ps
CPU time 6.59 seconds
Started Dec 27 12:28:22 PM PST 23
Finished Dec 27 12:29:15 PM PST 23
Peak memory 203000 kb
Host smart-e9e2fe15-093e-4068-bd41-13d74257885b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3603994549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3603994549
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.376778067
Short name T136
Test name
Test status
Simulation time 803478971 ps
CPU time 4.89 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:28:52 PM PST 23
Peak memory 203008 kb
Host smart-a76e8cfe-78e0-4b2f-9e43-a060e2ba1628
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=376778067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.376778067
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2763121119
Short name T443
Test name
Test status
Simulation time 34668796234 ps
CPU time 206.7 seconds
Started Dec 27 12:28:26 PM PST 23
Finished Dec 27 12:32:39 PM PST 23
Peak memory 204252 kb
Host smart-d13d0e78-85ad-419c-8a60-86ae9898fce8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763121119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2763121119
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3307113314
Short name T269
Test name
Test status
Simulation time 9386515991 ps
CPU time 55.17 seconds
Started Dec 27 12:28:26 PM PST 23
Finished Dec 27 12:30:13 PM PST 23
Peak memory 211092 kb
Host smart-3b923d57-70eb-48e3-bddb-cef716cfaa23
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3307113314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3307113314
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.978139879
Short name T576
Test name
Test status
Simulation time 91940814 ps
CPU time 10.29 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:29:23 PM PST 23
Peak memory 203884 kb
Host smart-3a98ce03-3648-4ac6-8bc3-cc9029fbcb30
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978139879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.978139879
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.2383382478
Short name T308
Test name
Test status
Simulation time 2423608261 ps
CPU time 12.39 seconds
Started Dec 27 12:28:38 PM PST 23
Finished Dec 27 12:29:42 PM PST 23
Peak memory 203156 kb
Host smart-cc63f645-1e42-41ce-8816-beb8cb9817e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2383382478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2383382478
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.159087305
Short name T149
Test name
Test status
Simulation time 34410625 ps
CPU time 2.11 seconds
Started Dec 27 12:28:13 PM PST 23
Finished Dec 27 12:28:54 PM PST 23
Peak memory 202996 kb
Host smart-08d336f3-d6e8-44a4-8b07-57dd0db80821
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=159087305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.159087305
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.112437764
Short name T69
Test name
Test status
Simulation time 7186213139 ps
CPU time 36.16 seconds
Started Dec 27 12:28:21 PM PST 23
Finished Dec 27 12:29:43 PM PST 23
Peak memory 202908 kb
Host smart-03f6ac2c-2d53-4678-983a-c46e79dfbdc6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=112437764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.112437764
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3385805353
Short name T159
Test name
Test status
Simulation time 4025964469 ps
CPU time 32.78 seconds
Started Dec 27 12:28:32 PM PST 23
Finished Dec 27 12:29:54 PM PST 23
Peak memory 202808 kb
Host smart-51b221b8-f8bf-476e-9d44-27eb809e2594
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3385805353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3385805353
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.552285251
Short name T478
Test name
Test status
Simulation time 80156687 ps
CPU time 2.25 seconds
Started Dec 27 12:28:19 PM PST 23
Finished Dec 27 12:29:06 PM PST 23
Peak memory 202876 kb
Host smart-b99d6f91-cf87-449b-8948-535abf1b5797
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552285251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.552285251
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1532761429
Short name T213
Test name
Test status
Simulation time 3065157940 ps
CPU time 201.98 seconds
Started Dec 27 12:28:33 PM PST 23
Finished Dec 27 12:32:44 PM PST 23
Peak memory 211232 kb
Host smart-fafe89dd-3b16-44cb-b06c-04e81de17f5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1532761429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1532761429
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1373446911
Short name T622
Test name
Test status
Simulation time 252105562 ps
CPU time 59.56 seconds
Started Dec 27 12:28:34 PM PST 23
Finished Dec 27 12:30:23 PM PST 23
Peak memory 207848 kb
Host smart-23930911-7602-467a-aa94-eff03e56fca3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1373446911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.1373446911
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.3637278284
Short name T590
Test name
Test status
Simulation time 1382396602 ps
CPU time 17.97 seconds
Started Dec 27 12:28:13 PM PST 23
Finished Dec 27 12:29:11 PM PST 23
Peak memory 211024 kb
Host smart-e8f336ba-910b-4e3a-9fee-09f2a95451db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3637278284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3637278284
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.1293848474
Short name T280
Test name
Test status
Simulation time 605484949 ps
CPU time 9.9 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:30:27 PM PST 23
Peak memory 211164 kb
Host smart-f5d9793e-1483-4c47-9af7-be05e18bd282
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1293848474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1293848474
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.791235268
Short name T820
Test name
Test status
Simulation time 92375589263 ps
CPU time 589.22 seconds
Started Dec 27 12:29:36 PM PST 23
Finished Dec 27 12:40:19 PM PST 23
Peak memory 206736 kb
Host smart-07647936-553d-40c9-bb65-714b19e19b78
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=791235268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo
w_rsp.791235268
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.639837043
Short name T334
Test name
Test status
Simulation time 16403019 ps
CPU time 1.73 seconds
Started Dec 27 12:28:18 PM PST 23
Finished Dec 27 12:29:04 PM PST 23
Peak memory 202956 kb
Host smart-b851b279-703f-46d3-a8b6-6acc151d233e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=639837043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.639837043
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.2227890926
Short name T512
Test name
Test status
Simulation time 490816436 ps
CPU time 3.81 seconds
Started Dec 27 12:28:13 PM PST 23
Finished Dec 27 12:28:56 PM PST 23
Peak memory 202812 kb
Host smart-9ef7e313-612f-4b18-8863-b4d79b7af04f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2227890926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2227890926
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.2580665345
Short name T65
Test name
Test status
Simulation time 1224117956 ps
CPU time 31.38 seconds
Started Dec 27 12:28:46 PM PST 23
Finished Dec 27 12:30:10 PM PST 23
Peak memory 202968 kb
Host smart-4d81835b-df99-49f6-b4c3-9801193c9ec6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2580665345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2580665345
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.4035578115
Short name T637
Test name
Test status
Simulation time 32576258154 ps
CPU time 161.22 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:32:26 PM PST 23
Peak memory 211208 kb
Host smart-9276dc6b-d288-481f-8db2-a783880f3ad8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035578115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.4035578115
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1792051761
Short name T429
Test name
Test status
Simulation time 43516585325 ps
CPU time 202.34 seconds
Started Dec 27 12:28:13 PM PST 23
Finished Dec 27 12:32:16 PM PST 23
Peak memory 211132 kb
Host smart-2c8934d4-f109-4947-b3ea-17b2380a9423
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1792051761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1792051761
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.225789041
Short name T208
Test name
Test status
Simulation time 96199682 ps
CPU time 7.69 seconds
Started Dec 27 12:28:24 PM PST 23
Finished Dec 27 12:29:19 PM PST 23
Peak memory 211024 kb
Host smart-f2b6987a-9b50-4af6-a2e7-978bfc8b0bd3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225789041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.225789041
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.1222643392
Short name T309
Test name
Test status
Simulation time 377111161 ps
CPU time 7.66 seconds
Started Dec 27 12:28:16 PM PST 23
Finished Dec 27 12:29:06 PM PST 23
Peak memory 203152 kb
Host smart-9516ae6a-2d33-4df3-9c17-0dbd990f0a8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1222643392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1222643392
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.1931729262
Short name T621
Test name
Test status
Simulation time 696039917 ps
CPU time 3.75 seconds
Started Dec 27 12:28:18 PM PST 23
Finished Dec 27 12:29:04 PM PST 23
Peak memory 202772 kb
Host smart-182092b3-caad-424a-b47c-70a2ebffa770
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1931729262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1931729262
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.1682690233
Short name T652
Test name
Test status
Simulation time 9291265992 ps
CPU time 28.72 seconds
Started Dec 27 12:28:35 PM PST 23
Finished Dec 27 12:29:54 PM PST 23
Peak memory 203024 kb
Host smart-2b0f2720-5fb5-48c3-afbf-98b9d9cc0670
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682690233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1682690233
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3278086769
Short name T458
Test name
Test status
Simulation time 3263711422 ps
CPU time 27.74 seconds
Started Dec 27 12:28:16 PM PST 23
Finished Dec 27 12:29:25 PM PST 23
Peak memory 203004 kb
Host smart-21f3bc32-8c5e-4b49-a721-9d2f0281eea7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3278086769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3278086769
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2398908750
Short name T375
Test name
Test status
Simulation time 113753278 ps
CPU time 2.14 seconds
Started Dec 27 12:28:38 PM PST 23
Finished Dec 27 12:29:31 PM PST 23
Peak memory 202900 kb
Host smart-6be962ef-a1ad-455d-8b5a-5792d00248fb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398908750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2398908750
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.405374206
Short name T156
Test name
Test status
Simulation time 2473172522 ps
CPU time 94.13 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:30:31 PM PST 23
Peak memory 207008 kb
Host smart-8f450658-51b9-46f2-8346-5dc034439c51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=405374206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.405374206
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3500760359
Short name T403
Test name
Test status
Simulation time 636705465 ps
CPU time 42.2 seconds
Started Dec 27 12:29:31 PM PST 23
Finished Dec 27 12:31:06 PM PST 23
Peak memory 205144 kb
Host smart-97bd677f-a8c5-4608-871a-9f38ef3ba955
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3500760359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3500760359
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1347160742
Short name T499
Test name
Test status
Simulation time 3320950289 ps
CPU time 471.04 seconds
Started Dec 27 12:28:33 PM PST 23
Finished Dec 27 12:37:17 PM PST 23
Peak memory 223504 kb
Host smart-a73cfb06-b3dc-404c-8bce-e9ac4ccbb8db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1347160742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.1347160742
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1198531955
Short name T763
Test name
Test status
Simulation time 16483357351 ps
CPU time 641.51 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:39:53 PM PST 23
Peak memory 222496 kb
Host smart-b18bf50c-f311-474d-ae45-f160a1770c7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1198531955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.1198531955
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3980558690
Short name T727
Test name
Test status
Simulation time 65956056 ps
CPU time 7.79 seconds
Started Dec 27 12:28:21 PM PST 23
Finished Dec 27 12:29:15 PM PST 23
Peak memory 211112 kb
Host smart-87bf74de-4d48-4ff9-94a4-59fabbc68974
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3980558690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3980558690
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.1845531563
Short name T623
Test name
Test status
Simulation time 116085399 ps
CPU time 15.3 seconds
Started Dec 27 12:29:37 PM PST 23
Finished Dec 27 12:30:46 PM PST 23
Peak memory 204992 kb
Host smart-b869cd55-0566-4d16-8241-c41060a51b1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1845531563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1845531563
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.4128357337
Short name T500
Test name
Test status
Simulation time 34803511721 ps
CPU time 132.08 seconds
Started Dec 27 12:28:12 PM PST 23
Finished Dec 27 12:31:04 PM PST 23
Peak memory 211308 kb
Host smart-1484be60-80b7-4039-9d27-8b39d2f94aae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4128357337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.4128357337
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3840301799
Short name T410
Test name
Test status
Simulation time 479839115 ps
CPU time 10.72 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:30:00 PM PST 23
Peak memory 203240 kb
Host smart-3dbd7b8f-0f04-45b3-a448-242c3c958ad0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3840301799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3840301799
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.3477184200
Short name T184
Test name
Test status
Simulation time 750946319 ps
CPU time 17.63 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:29:24 PM PST 23
Peak memory 203060 kb
Host smart-58ed15d4-adde-4c01-ac59-8e03d8ac01cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3477184200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3477184200
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.864468620
Short name T361
Test name
Test status
Simulation time 375856921 ps
CPU time 12.23 seconds
Started Dec 27 12:28:32 PM PST 23
Finished Dec 27 12:29:33 PM PST 23
Peak memory 211108 kb
Host smart-76b5211b-ab9e-4b96-93d7-bd370880fd1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=864468620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.864468620
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2922327819
Short name T505
Test name
Test status
Simulation time 61125291323 ps
CPU time 217.28 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 211128 kb
Host smart-dd4b6c12-320c-41a8-9803-8ac523d64f2b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922327819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2922327819
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.4010415640
Short name T245
Test name
Test status
Simulation time 44780995552 ps
CPU time 197.38 seconds
Started Dec 27 12:30:09 PM PST 23
Finished Dec 27 12:34:18 PM PST 23
Peak memory 211060 kb
Host smart-801ebe90-18d1-4e73-8783-76b989e0282e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4010415640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.4010415640
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1967639953
Short name T819
Test name
Test status
Simulation time 303344136 ps
CPU time 27.49 seconds
Started Dec 27 12:29:41 PM PST 23
Finished Dec 27 12:31:02 PM PST 23
Peak memory 204348 kb
Host smart-a9bf3a36-0e65-42ae-95b5-91bedd7d80c5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967639953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1967639953
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.3184045129
Short name T836
Test name
Test status
Simulation time 5146475729 ps
CPU time 25.56 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:29:38 PM PST 23
Peak memory 203952 kb
Host smart-3002b82f-57e7-46a7-88e3-517ee6800cd0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3184045129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3184045129
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.2617021569
Short name T600
Test name
Test status
Simulation time 678304946 ps
CPU time 3.85 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:29:00 PM PST 23
Peak memory 202468 kb
Host smart-2d57a24d-0846-4bed-bab9-5cb943bfab62
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2617021569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2617021569
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2421329285
Short name T62
Test name
Test status
Simulation time 22681838013 ps
CPU time 40.74 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 202916 kb
Host smart-d8d8a5ff-3174-46d6-ba11-9edb9b3b9198
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421329285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2421329285
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1417168992
Short name T759
Test name
Test status
Simulation time 3426012200 ps
CPU time 27.05 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:29:13 PM PST 23
Peak memory 203016 kb
Host smart-33955f39-4966-46dc-8f5a-35ba7d2746fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1417168992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1417168992
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2016710609
Short name T363
Test name
Test status
Simulation time 36143748 ps
CPU time 2.2 seconds
Started Dec 27 12:29:31 PM PST 23
Finished Dec 27 12:30:26 PM PST 23
Peak memory 202768 kb
Host smart-2cd10b0c-fe8a-445a-b3e1-b0cb02ffd826
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016710609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2016710609
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2407425721
Short name T439
Test name
Test status
Simulation time 6897585502 ps
CPU time 92.58 seconds
Started Dec 27 12:28:46 PM PST 23
Finished Dec 27 12:31:11 PM PST 23
Peak memory 206780 kb
Host smart-bcf9c2dd-6d89-4062-be2d-22cf9acca2a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2407425721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2407425721
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2310167734
Short name T470
Test name
Test status
Simulation time 262503077 ps
CPU time 15.35 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:29:27 PM PST 23
Peak memory 202896 kb
Host smart-8157e0f4-d4d1-4e79-98dd-52d4c03aab5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2310167734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2310167734
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3126950200
Short name T276
Test name
Test status
Simulation time 4418035434 ps
CPU time 215.32 seconds
Started Dec 27 12:28:22 PM PST 23
Finished Dec 27 12:32:44 PM PST 23
Peak memory 209672 kb
Host smart-791aa3e0-0346-4858-a677-56e1d6914255
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3126950200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re
set_error.3126950200
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1935029721
Short name T807
Test name
Test status
Simulation time 936690260 ps
CPU time 24.42 seconds
Started Dec 27 12:30:09 PM PST 23
Finished Dec 27 12:31:25 PM PST 23
Peak memory 204172 kb
Host smart-a4b1472d-c942-42ec-b297-b38fb651cedb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1935029721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1935029721
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.3091152698
Short name T142
Test name
Test status
Simulation time 2667333353 ps
CPU time 64.79 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:30:01 PM PST 23
Peak memory 205076 kb
Host smart-e53f1f5d-cd97-4469-bb55-20d64d9fd181
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3091152698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3091152698
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.290682394
Short name T511
Test name
Test status
Simulation time 38143359444 ps
CPU time 339.86 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:34:56 PM PST 23
Peak memory 206032 kb
Host smart-2cf7ab03-238a-4a68-ac88-c01e7ddb414f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=290682394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slo
w_rsp.290682394
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2225405936
Short name T722
Test name
Test status
Simulation time 107163791 ps
CPU time 15.18 seconds
Started Dec 27 12:29:22 PM PST 23
Finished Dec 27 12:30:32 PM PST 23
Peak memory 203228 kb
Host smart-2a85d46d-5deb-4921-bf5d-c83b83b4461e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2225405936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2225405936
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.1198898377
Short name T827
Test name
Test status
Simulation time 3070858760 ps
CPU time 35.44 seconds
Started Dec 27 12:28:48 PM PST 23
Finished Dec 27 12:30:16 PM PST 23
Peak memory 203116 kb
Host smart-5e4e83f2-2200-4243-984c-a620442dd15d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1198898377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1198898377
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.4262843794
Short name T674
Test name
Test status
Simulation time 2037179230 ps
CPU time 17.06 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:29:37 PM PST 23
Peak memory 203672 kb
Host smart-0ab6c6dd-9062-4c3e-b8b5-fa2b3124bf90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4262843794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.4262843794
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.388639493
Short name T569
Test name
Test status
Simulation time 60825802041 ps
CPU time 221.13 seconds
Started Dec 27 12:28:13 PM PST 23
Finished Dec 27 12:32:34 PM PST 23
Peak memory 211148 kb
Host smart-02604cab-486b-47de-ad65-2ed624de1493
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=388639493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.388639493
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.4010926611
Short name T419
Test name
Test status
Simulation time 20702413292 ps
CPU time 123.99 seconds
Started Dec 27 12:28:35 PM PST 23
Finished Dec 27 12:31:30 PM PST 23
Peak memory 204252 kb
Host smart-66177a29-076c-44bd-9729-a431f22ee290
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4010926611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.4010926611
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.434871134
Short name T572
Test name
Test status
Simulation time 433595060 ps
CPU time 27.54 seconds
Started Dec 27 12:28:23 PM PST 23
Finished Dec 27 12:29:37 PM PST 23
Peak memory 211064 kb
Host smart-a919bed6-2055-478d-8369-9ff2ef24bb9c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434871134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.434871134
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.1908104210
Short name T615
Test name
Test status
Simulation time 619770716 ps
CPU time 14.11 seconds
Started Dec 27 12:28:38 PM PST 23
Finished Dec 27 12:29:43 PM PST 23
Peak memory 203284 kb
Host smart-562db514-1694-465c-984b-70ff82235a51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1908104210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1908104210
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.2952909034
Short name T778
Test name
Test status
Simulation time 38022485 ps
CPU time 2.15 seconds
Started Dec 27 12:28:24 PM PST 23
Finished Dec 27 12:29:13 PM PST 23
Peak memory 202980 kb
Host smart-095694ea-f668-4fb4-b505-bfda90dddda8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2952909034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2952909034
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3087024845
Short name T369
Test name
Test status
Simulation time 4670170772 ps
CPU time 23.39 seconds
Started Dec 27 12:28:37 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 202932 kb
Host smart-34d6fefc-10d3-42b2-b31e-d7a7e20511d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087024845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3087024845
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1629450661
Short name T398
Test name
Test status
Simulation time 10763566126 ps
CPU time 35.44 seconds
Started Dec 27 12:28:17 PM PST 23
Finished Dec 27 12:29:34 PM PST 23
Peak memory 202848 kb
Host smart-033f89f4-9f77-4a25-862c-70aaf3051c26
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1629450661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1629450661
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3144564383
Short name T426
Test name
Test status
Simulation time 41152004 ps
CPU time 2.23 seconds
Started Dec 27 12:28:24 PM PST 23
Finished Dec 27 12:29:14 PM PST 23
Peak memory 202832 kb
Host smart-ff8b93fe-1306-4f6d-9c00-9e9dcb17951f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144564383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3144564383
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.832080328
Short name T489
Test name
Test status
Simulation time 2382721624 ps
CPU time 23.9 seconds
Started Dec 27 12:29:19 PM PST 23
Finished Dec 27 12:30:38 PM PST 23
Peak memory 204692 kb
Host smart-8cfa4c0b-78ec-4ba8-baf3-936939f8acba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=832080328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.832080328
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1361451423
Short name T645
Test name
Test status
Simulation time 5110008838 ps
CPU time 156.58 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:32:21 PM PST 23
Peak memory 208436 kb
Host smart-aadab839-21f0-4bf2-8856-35b75a690afb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1361451423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1361451423
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1366528017
Short name T146
Test name
Test status
Simulation time 302273620 ps
CPU time 134.53 seconds
Started Dec 27 12:28:33 PM PST 23
Finished Dec 27 12:31:38 PM PST 23
Peak memory 207308 kb
Host smart-fdf1fdd5-0873-4181-aa25-c339597273fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1366528017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.1366528017
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4061413058
Short name T281
Test name
Test status
Simulation time 3330802554 ps
CPU time 262.96 seconds
Started Dec 27 12:29:53 PM PST 23
Finished Dec 27 12:35:08 PM PST 23
Peak memory 222840 kb
Host smart-08a25639-ae83-48c0-9863-39a95f85a63c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4061413058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.4061413058
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3322746123
Short name T716
Test name
Test status
Simulation time 1272945761 ps
CPU time 26.39 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:29:23 PM PST 23
Peak memory 204196 kb
Host smart-44c3f569-cfbb-414a-abbf-466bcffe54df
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3322746123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3322746123
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1694594631
Short name T202
Test name
Test status
Simulation time 357650957 ps
CPU time 34.72 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:30:26 PM PST 23
Peak memory 211116 kb
Host smart-08ab8768-9d3e-4861-8485-c5a9f02295ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1694594631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1694594631
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2878182680
Short name T235
Test name
Test status
Simulation time 57019709211 ps
CPU time 312 seconds
Started Dec 27 12:28:24 PM PST 23
Finished Dec 27 12:34:23 PM PST 23
Peak memory 205772 kb
Host smart-c17549ac-fd20-4ec0-bc3f-d437ebc41eae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2878182680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.2878182680
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1423915117
Short name T685
Test name
Test status
Simulation time 145358195 ps
CPU time 11.96 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:29:28 PM PST 23
Peak memory 202888 kb
Host smart-d313b37f-e018-4dae-a5f1-2166ce834fed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1423915117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1423915117
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.2748981300
Short name T678
Test name
Test status
Simulation time 550370526 ps
CPU time 15.61 seconds
Started Dec 27 12:29:11 PM PST 23
Finished Dec 27 12:30:21 PM PST 23
Peak memory 202908 kb
Host smart-76207daa-4fdd-4a32-a087-1ec25c625d10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2748981300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2748981300
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.621726361
Short name T464
Test name
Test status
Simulation time 107189836 ps
CPU time 2.79 seconds
Started Dec 27 12:29:27 PM PST 23
Finished Dec 27 12:30:23 PM PST 23
Peak memory 202840 kb
Host smart-9d18bd0c-89d5-4c9b-810a-ceb657ea871d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=621726361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.621726361
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.4154463626
Short name T188
Test name
Test status
Simulation time 60304020605 ps
CPU time 245.38 seconds
Started Dec 27 12:28:58 PM PST 23
Finished Dec 27 12:33:58 PM PST 23
Peak memory 204628 kb
Host smart-fe6a3d60-908f-4c6b-9d26-2c269fa40116
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154463626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4154463626
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2779280468
Short name T747
Test name
Test status
Simulation time 27261174448 ps
CPU time 198.5 seconds
Started Dec 27 12:29:12 PM PST 23
Finished Dec 27 12:33:25 PM PST 23
Peak memory 211140 kb
Host smart-10731b68-91ee-4495-ab0d-b5bd74e1935e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2779280468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2779280468
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3579903898
Short name T346
Test name
Test status
Simulation time 53999696 ps
CPU time 3.41 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:29:54 PM PST 23
Peak memory 202864 kb
Host smart-699adf90-48b2-458e-9ee2-25e0a81e1414
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579903898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3579903898
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.158328932
Short name T238
Test name
Test status
Simulation time 381257625 ps
CPU time 8.23 seconds
Started Dec 27 12:28:31 PM PST 23
Finished Dec 27 12:29:28 PM PST 23
Peak memory 202868 kb
Host smart-14c8f3e5-8171-4120-9c17-306e14a74f1f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=158328932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.158328932
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.1279258574
Short name T411
Test name
Test status
Simulation time 26917863 ps
CPU time 2.15 seconds
Started Dec 27 12:28:23 PM PST 23
Finished Dec 27 12:29:12 PM PST 23
Peak memory 202976 kb
Host smart-61dd3aad-8ec7-4541-9bb4-5317729d52d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1279258574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1279258574
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2194136259
Short name T814
Test name
Test status
Simulation time 14407038467 ps
CPU time 31.71 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:29:43 PM PST 23
Peak memory 203004 kb
Host smart-c9581828-fa23-41b4-b055-c48942d40d18
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194136259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2194136259
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.4165915592
Short name T481
Test name
Test status
Simulation time 4269921157 ps
CPU time 32.89 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:30:21 PM PST 23
Peak memory 202916 kb
Host smart-8c93ac06-4980-46a2-9f88-1e2ee77e8557
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4165915592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.4165915592
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2162581576
Short name T477
Test name
Test status
Simulation time 25288381 ps
CPU time 2.03 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:29:18 PM PST 23
Peak memory 202948 kb
Host smart-71238f98-2f02-4f66-aca4-f53b85c1e079
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162581576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2162581576
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.3201435289
Short name T16
Test name
Test status
Simulation time 694288567 ps
CPU time 64.14 seconds
Started Dec 27 12:30:18 PM PST 23
Finished Dec 27 12:32:17 PM PST 23
Peak memory 206292 kb
Host smart-13f7ef9b-d82a-484c-990c-1e9b97a6604e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3201435289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3201435289
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3732038273
Short name T68
Test name
Test status
Simulation time 1537536679 ps
CPU time 60.34 seconds
Started Dec 27 12:28:32 PM PST 23
Finished Dec 27 12:30:22 PM PST 23
Peak memory 204284 kb
Host smart-ce109f14-f692-4646-87e0-5b8d01416fdf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3732038273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3732038273
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1493901031
Short name T216
Test name
Test status
Simulation time 2791341430 ps
CPU time 416.89 seconds
Started Dec 27 12:28:42 PM PST 23
Finished Dec 27 12:36:31 PM PST 23
Peak memory 219380 kb
Host smart-35ecfb2d-98d7-4b24-a230-b0e3356e31a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1493901031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.1493901031
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2244740853
Short name T459
Test name
Test status
Simulation time 1063940452 ps
CPU time 227.66 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:32:59 PM PST 23
Peak memory 219324 kb
Host smart-78059ff2-19fa-4963-8399-41013aef1292
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2244740853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.2244740853
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2214115753
Short name T217
Test name
Test status
Simulation time 187622762 ps
CPU time 16.21 seconds
Started Dec 27 12:28:32 PM PST 23
Finished Dec 27 12:29:38 PM PST 23
Peak memory 204172 kb
Host smart-04f50ea4-d250-4755-9704-ca18a148cd6b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2214115753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2214115753
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.639901022
Short name T201
Test name
Test status
Simulation time 233608521 ps
CPU time 27.54 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:30:15 PM PST 23
Peak memory 203532 kb
Host smart-b59a4062-f3a9-4aa4-8a7c-ac5a826ae216
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=639901022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.639901022
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1757345472
Short name T545
Test name
Test status
Simulation time 72146302762 ps
CPU time 563.38 seconds
Started Dec 27 12:28:43 PM PST 23
Finished Dec 27 12:38:59 PM PST 23
Peak memory 211196 kb
Host smart-9f534abe-6119-481f-9af4-afb806ee0a5b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1757345472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.1757345472
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.3830076439
Short name T617
Test name
Test status
Simulation time 403632288 ps
CPU time 5.85 seconds
Started Dec 27 12:29:02 PM PST 23
Finished Dec 27 12:30:03 PM PST 23
Peak memory 202860 kb
Host smart-91010555-ba43-42bf-b366-4b3dde0ccf5a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3830076439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3830076439
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.2084195187
Short name T846
Test name
Test status
Simulation time 537851549 ps
CPU time 10.26 seconds
Started Dec 27 12:28:29 PM PST 23
Finished Dec 27 12:29:28 PM PST 23
Peak memory 202864 kb
Host smart-3ec62941-5549-4fd1-b613-f28381ab4d49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2084195187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2084195187
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.3150189356
Short name T385
Test name
Test status
Simulation time 221161001 ps
CPU time 22.26 seconds
Started Dec 27 12:28:29 PM PST 23
Finished Dec 27 12:29:41 PM PST 23
Peak memory 211044 kb
Host smart-30efd3e2-89f0-4a47-be68-b7f4694178b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3150189356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3150189356
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1976435354
Short name T731
Test name
Test status
Simulation time 27010710352 ps
CPU time 180.23 seconds
Started Dec 27 12:28:37 PM PST 23
Finished Dec 27 12:32:28 PM PST 23
Peak memory 211212 kb
Host smart-6642c2bf-dfae-4c65-8fc3-81a0da6e839e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976435354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1976435354
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3691592592
Short name T61
Test name
Test status
Simulation time 5131144144 ps
CPU time 29.87 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:30:02 PM PST 23
Peak memory 203656 kb
Host smart-52f9d1f8-04ad-46d4-9f72-0fe26d9d4b8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3691592592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3691592592
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1552513016
Short name T536
Test name
Test status
Simulation time 248110629 ps
CPU time 20.05 seconds
Started Dec 27 12:29:19 PM PST 23
Finished Dec 27 12:30:34 PM PST 23
Peak memory 204140 kb
Host smart-af431665-7534-44d6-8c5d-9266354ee219
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552513016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1552513016
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.596033488
Short name T539
Test name
Test status
Simulation time 273697131 ps
CPU time 5.92 seconds
Started Dec 27 12:28:47 PM PST 23
Finished Dec 27 12:29:45 PM PST 23
Peak memory 202932 kb
Host smart-6090fe7a-563d-4df7-bd44-c59ca1e74f19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=596033488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.596033488
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.3994386693
Short name T682
Test name
Test status
Simulation time 48797114 ps
CPU time 2.16 seconds
Started Dec 27 12:28:38 PM PST 23
Finished Dec 27 12:29:32 PM PST 23
Peak memory 202936 kb
Host smart-153b83b0-4a34-4d92-b2fa-1a47862c5e4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3994386693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3994386693
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3927074337
Short name T342
Test name
Test status
Simulation time 6219647199 ps
CPU time 32 seconds
Started Dec 27 12:30:34 PM PST 23
Finished Dec 27 12:32:03 PM PST 23
Peak memory 202920 kb
Host smart-644b59da-0b05-49f8-9ad3-9ff0d361c86c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927074337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3927074337
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3660410832
Short name T274
Test name
Test status
Simulation time 4312886460 ps
CPU time 27.94 seconds
Started Dec 27 12:28:23 PM PST 23
Finished Dec 27 12:29:37 PM PST 23
Peak memory 203020 kb
Host smart-825e5ffa-f3b5-4c4c-8a52-dbc5161a3169
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3660410832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3660410832
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4223989740
Short name T870
Test name
Test status
Simulation time 52258102 ps
CPU time 2.16 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:29:49 PM PST 23
Peak memory 202888 kb
Host smart-99d08972-4edb-4103-80f4-be16ae9bd6ac
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223989740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.4223989740
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3562931404
Short name T753
Test name
Test status
Simulation time 2824651524 ps
CPU time 105.4 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:31:02 PM PST 23
Peak memory 206100 kb
Host smart-ef553a28-eb0a-464c-beaf-be5d73d3735c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3562931404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3562931404
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3589368434
Short name T450
Test name
Test status
Simulation time 1423410716 ps
CPU time 27.85 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:30:18 PM PST 23
Peak memory 203120 kb
Host smart-560def94-fcf8-4a8f-b9ad-eeb785cd13a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3589368434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3589368434
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1827227236
Short name T198
Test name
Test status
Simulation time 5850781690 ps
CPU time 462.18 seconds
Started Dec 27 12:28:34 PM PST 23
Finished Dec 27 12:37:05 PM PST 23
Peak memory 219408 kb
Host smart-42c970e3-9efc-4212-995b-aa1e574733e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1827227236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.1827227236
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1468720108
Short name T14
Test name
Test status
Simulation time 673263966 ps
CPU time 142.93 seconds
Started Dec 27 12:28:24 PM PST 23
Finished Dec 27 12:31:34 PM PST 23
Peak memory 209528 kb
Host smart-a935efc7-789d-4ec5-8e94-382668e61fbe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1468720108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.1468720108
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.329985681
Short name T75
Test name
Test status
Simulation time 4664567877 ps
CPU time 34.1 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 204924 kb
Host smart-fa77f50c-f61d-4469-b099-02a1d5ff1933
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=329985681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.329985681
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.197378451
Short name T777
Test name
Test status
Simulation time 2358427336 ps
CPU time 55.52 seconds
Started Dec 27 12:29:27 PM PST 23
Finished Dec 27 12:31:16 PM PST 23
Peak memory 205496 kb
Host smart-7c527f61-cb0b-483a-943f-fc5e1689fce0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=197378451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.197378451
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3184612305
Short name T141
Test name
Test status
Simulation time 149391771105 ps
CPU time 675.29 seconds
Started Dec 27 12:29:28 PM PST 23
Finished Dec 27 12:41:37 PM PST 23
Peak memory 211004 kb
Host smart-b9155b60-3d47-4819-9c52-7c6dca7ae62c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3184612305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.3184612305
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3387969696
Short name T504
Test name
Test status
Simulation time 933457938 ps
CPU time 22.74 seconds
Started Dec 27 12:29:20 PM PST 23
Finished Dec 27 12:30:38 PM PST 23
Peak memory 203268 kb
Host smart-c0a28af1-4274-4fc5-aa63-eb3695b8a762
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3387969696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3387969696
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.272723688
Short name T340
Test name
Test status
Simulation time 618200212 ps
CPU time 20.53 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 202836 kb
Host smart-48a21ce7-aa75-425b-b6e9-f6e6c4f6582b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=272723688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.272723688
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.2990980139
Short name T691
Test name
Test status
Simulation time 80557133 ps
CPU time 9.12 seconds
Started Dec 27 12:28:44 PM PST 23
Finished Dec 27 12:29:45 PM PST 23
Peak memory 211116 kb
Host smart-ff0ca3e4-af8b-49aa-8699-dcda8fce050d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2990980139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2990980139
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3838548590
Short name T688
Test name
Test status
Simulation time 41906525501 ps
CPU time 97.67 seconds
Started Dec 27 12:29:08 PM PST 23
Finished Dec 27 12:31:39 PM PST 23
Peak memory 204248 kb
Host smart-63de4481-7699-406a-b751-6d63a7461bcc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838548590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3838548590
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1023120815
Short name T352
Test name
Test status
Simulation time 4132677503 ps
CPU time 27.88 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:30:56 PM PST 23
Peak memory 203260 kb
Host smart-e5703969-c6a8-4a69-a4e4-7af9e6bbbab4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1023120815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1023120815
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2403986053
Short name T578
Test name
Test status
Simulation time 63812986 ps
CPU time 7.81 seconds
Started Dec 27 12:28:22 PM PST 23
Finished Dec 27 12:29:20 PM PST 23
Peak memory 211116 kb
Host smart-680646ed-d956-4fc3-968d-df961716e8db
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403986053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2403986053
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.2332507255
Short name T271
Test name
Test status
Simulation time 160352829 ps
CPU time 9.49 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:29:58 PM PST 23
Peak memory 203464 kb
Host smart-ea1f61c4-6071-49c9-a17c-cd3fd3096563
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2332507255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2332507255
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.693895538
Short name T573
Test name
Test status
Simulation time 186606779 ps
CPU time 3.61 seconds
Started Dec 27 12:29:41 PM PST 23
Finished Dec 27 12:30:38 PM PST 23
Peak memory 202824 kb
Host smart-cad6eafb-2770-44de-9784-5a2d6cb114f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=693895538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.693895538
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2343071834
Short name T368
Test name
Test status
Simulation time 17346661550 ps
CPU time 31.89 seconds
Started Dec 27 12:28:34 PM PST 23
Finished Dec 27 12:30:03 PM PST 23
Peak memory 202972 kb
Host smart-ad468723-3f3f-4641-874e-9c4b7381d756
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343071834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2343071834
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2350659409
Short name T542
Test name
Test status
Simulation time 3756135313 ps
CPU time 25.15 seconds
Started Dec 27 12:28:26 PM PST 23
Finished Dec 27 12:29:37 PM PST 23
Peak memory 203000 kb
Host smart-0eabc54c-cc20-47fd-b498-814c90388a5b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2350659409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2350659409
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.4009812817
Short name T138
Test name
Test status
Simulation time 92052148 ps
CPU time 2.31 seconds
Started Dec 27 12:28:49 PM PST 23
Finished Dec 27 12:29:44 PM PST 23
Peak memory 202880 kb
Host smart-a1070bd1-8bf1-4503-83de-916174d5442e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009812817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.4009812817
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.4223753803
Short name T356
Test name
Test status
Simulation time 1304826953 ps
CPU time 91.35 seconds
Started Dec 27 12:28:33 PM PST 23
Finished Dec 27 12:30:54 PM PST 23
Peak memory 206680 kb
Host smart-260a0b0c-63a0-434e-97fd-c5bdd6b1e86e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4223753803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.4223753803
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3946887639
Short name T684
Test name
Test status
Simulation time 2809574864 ps
CPU time 98.62 seconds
Started Dec 27 12:28:50 PM PST 23
Finished Dec 27 12:31:22 PM PST 23
Peak memory 207640 kb
Host smart-f0169793-ec1c-4833-9079-f7a70f5f2c87
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3946887639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3946887639
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2513447194
Short name T18
Test name
Test status
Simulation time 14460246 ps
CPU time 12.56 seconds
Started Dec 27 12:28:45 PM PST 23
Finished Dec 27 12:29:50 PM PST 23
Peak memory 203044 kb
Host smart-9f84a614-a96b-4088-98d9-15373d8b9bef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2513447194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.2513447194
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3393621726
Short name T326
Test name
Test status
Simulation time 4354522132 ps
CPU time 195.58 seconds
Started Dec 27 12:28:23 PM PST 23
Finished Dec 27 12:32:24 PM PST 23
Peak memory 211160 kb
Host smart-ab944ca5-5f43-4cc3-ae84-d2ab10af0233
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3393621726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.3393621726
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.4174178526
Short name T696
Test name
Test status
Simulation time 286249696 ps
CPU time 11.05 seconds
Started Dec 27 12:29:09 PM PST 23
Finished Dec 27 12:30:14 PM PST 23
Peak memory 204008 kb
Host smart-fadd4510-e1f6-4735-a75f-35dbb76e0c9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4174178526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.4174178526
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3043275707
Short name T54
Test name
Test status
Simulation time 1012588957 ps
CPU time 21.03 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 211112 kb
Host smart-13e66b16-d396-4f35-a0ce-9c24ba741765
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3043275707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3043275707
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.4174751665
Short name T654
Test name
Test status
Simulation time 165999371871 ps
CPU time 697.55 seconds
Started Dec 27 12:29:45 PM PST 23
Finished Dec 27 12:42:15 PM PST 23
Peak memory 206776 kb
Host smart-d89c4fd1-61e7-4b8f-a4e1-c2f6077f069b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4174751665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.4174751665
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2252998875
Short name T302
Test name
Test status
Simulation time 734528836 ps
CPU time 24.5 seconds
Started Dec 27 12:29:22 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 203344 kb
Host smart-033cc24c-b1e5-42a7-852e-eca1c4b4fd1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2252998875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2252998875
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.1393746491
Short name T13
Test name
Test status
Simulation time 826788652 ps
CPU time 15.15 seconds
Started Dec 27 12:29:19 PM PST 23
Finished Dec 27 12:30:29 PM PST 23
Peak memory 202924 kb
Host smart-8fdb709e-009d-441e-a792-54c26aed024f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1393746491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1393746491
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.1268497907
Short name T813
Test name
Test status
Simulation time 813267662 ps
CPU time 22.64 seconds
Started Dec 27 12:28:31 PM PST 23
Finished Dec 27 12:29:43 PM PST 23
Peak memory 204036 kb
Host smart-a127404c-0d66-4a74-b0e3-ef5c412550ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1268497907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1268497907
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2205770043
Short name T865
Test name
Test status
Simulation time 9535993386 ps
CPU time 28.22 seconds
Started Dec 27 12:28:37 PM PST 23
Finished Dec 27 12:29:56 PM PST 23
Peak memory 203636 kb
Host smart-0f6637f1-da8c-4773-a62d-37d914551b23
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205770043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2205770043
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2629156279
Short name T785
Test name
Test status
Simulation time 7335396770 ps
CPU time 48.57 seconds
Started Dec 27 12:28:31 PM PST 23
Finished Dec 27 12:30:09 PM PST 23
Peak memory 211196 kb
Host smart-9f65d1bf-7bb6-4bc4-a1cd-56f06fb4467e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2629156279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2629156279
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3974191808
Short name T301
Test name
Test status
Simulation time 223171546 ps
CPU time 25.27 seconds
Started Dec 27 12:28:49 PM PST 23
Finished Dec 27 12:30:07 PM PST 23
Peak memory 211136 kb
Host smart-3080c4d5-ad53-4594-a133-086fc10ea61e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974191808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3974191808
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.1827725996
Short name T163
Test name
Test status
Simulation time 594514943 ps
CPU time 12.24 seconds
Started Dec 27 12:30:29 PM PST 23
Finished Dec 27 12:31:38 PM PST 23
Peak memory 203364 kb
Host smart-587a3eea-0a55-4d73-8711-d22a92889e4c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1827725996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1827725996
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.2582521514
Short name T799
Test name
Test status
Simulation time 111193313 ps
CPU time 3.75 seconds
Started Dec 27 12:28:42 PM PST 23
Finished Dec 27 12:29:38 PM PST 23
Peak memory 202776 kb
Host smart-edeff065-e42e-438c-b8f4-e7dd0fcca72d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2582521514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2582521514
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1565107153
Short name T265
Test name
Test status
Simulation time 5188427897 ps
CPU time 32.09 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:30:49 PM PST 23
Peak memory 202676 kb
Host smart-a9df4d41-7371-4e59-be70-89ab0a118929
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565107153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1565107153
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2328539199
Short name T825
Test name
Test status
Simulation time 7919311662 ps
CPU time 26.17 seconds
Started Dec 27 12:31:57 PM PST 23
Finished Dec 27 12:33:08 PM PST 23
Peak memory 202600 kb
Host smart-1c9ec98d-00ae-43c4-adce-762b39d195dd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2328539199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2328539199
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1543150811
Short name T667
Test name
Test status
Simulation time 35483579 ps
CPU time 2.15 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:20 PM PST 23
Peak memory 202800 kb
Host smart-f8e093c3-2d9b-4755-98b2-d963e51934ef
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543150811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1543150811
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1638966758
Short name T166
Test name
Test status
Simulation time 9191650902 ps
CPU time 158.77 seconds
Started Dec 27 12:28:42 PM PST 23
Finished Dec 27 12:32:12 PM PST 23
Peak memory 210952 kb
Host smart-a32fc5e8-441e-4b3e-899a-1f3f60a40bff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1638966758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1638966758
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.741326373
Short name T496
Test name
Test status
Simulation time 9396739210 ps
CPU time 202.65 seconds
Started Dec 27 12:28:50 PM PST 23
Finished Dec 27 12:33:07 PM PST 23
Peak memory 208036 kb
Host smart-a98d5e19-e7f8-48d6-b068-00066a54ed3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=741326373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.741326373
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2953197113
Short name T661
Test name
Test status
Simulation time 5547135447 ps
CPU time 156.61 seconds
Started Dec 27 12:29:15 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 207824 kb
Host smart-56ff83d7-7450-4b6b-8ea2-259d1730b5f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2953197113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.2953197113
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2990518217
Short name T564
Test name
Test status
Simulation time 9054046963 ps
CPU time 332.42 seconds
Started Dec 27 12:29:18 PM PST 23
Finished Dec 27 12:35:46 PM PST 23
Peak memory 219304 kb
Host smart-b8571a16-6dc3-4a18-aa58-ffb86c34a4b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2990518217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.2990518217
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.4253531102
Short name T164
Test name
Test status
Simulation time 81754880 ps
CPU time 9.75 seconds
Started Dec 27 12:30:28 PM PST 23
Finished Dec 27 12:31:35 PM PST 23
Peak memory 211124 kb
Host smart-eafbd903-040f-432d-a9c0-88958af27692
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4253531102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.4253531102
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.1498151236
Short name T179
Test name
Test status
Simulation time 626065336 ps
CPU time 40.3 seconds
Started Dec 27 12:29:59 PM PST 23
Finished Dec 27 12:31:31 PM PST 23
Peak memory 205648 kb
Host smart-f6baa6e8-5790-4c99-b314-9a4e97d342ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1498151236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.1498151236
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3547177013
Short name T728
Test name
Test status
Simulation time 552541469 ps
CPU time 21.03 seconds
Started Dec 27 12:29:26 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 202936 kb
Host smart-39b79f9c-fe01-498b-9b58-c4a9b8174786
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3547177013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3547177013
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.3510013105
Short name T451
Test name
Test status
Simulation time 18064916 ps
CPU time 2.08 seconds
Started Dec 27 12:28:38 PM PST 23
Finished Dec 27 12:29:31 PM PST 23
Peak memory 202948 kb
Host smart-e5b65ec8-755a-4e26-956e-8b93bef4517f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3510013105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3510013105
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.3762126995
Short name T169
Test name
Test status
Simulation time 110174707 ps
CPU time 4.41 seconds
Started Dec 27 12:28:29 PM PST 23
Finished Dec 27 12:29:22 PM PST 23
Peak memory 202952 kb
Host smart-93b821bb-4193-4ec2-b26e-35874c344d9c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3762126995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3762126995
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3276681225
Short name T133
Test name
Test status
Simulation time 53870109782 ps
CPU time 208.24 seconds
Started Dec 27 12:30:24 PM PST 23
Finished Dec 27 12:34:49 PM PST 23
Peak memory 204492 kb
Host smart-7c212f6a-79b3-4246-b735-291b3828c299
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276681225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3276681225
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3797518241
Short name T733
Test name
Test status
Simulation time 1617761888 ps
CPU time 16.41 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:30:06 PM PST 23
Peak memory 202908 kb
Host smart-306c67c8-69ea-4d3f-bbea-67c2dcb9aa35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3797518241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3797518241
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2582858369
Short name T288
Test name
Test status
Simulation time 142101929 ps
CPU time 12.58 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:29:45 PM PST 23
Peak memory 211084 kb
Host smart-da7b7963-9e33-454e-92f8-0402295d5425
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582858369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2582858369
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.3331893663
Short name T355
Test name
Test status
Simulation time 559632424 ps
CPU time 18.11 seconds
Started Dec 27 12:28:57 PM PST 23
Finished Dec 27 12:30:09 PM PST 23
Peak memory 202864 kb
Host smart-8155addb-df7d-43c3-a48a-072d9d6a316f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3331893663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3331893663
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.215311136
Short name T243
Test name
Test status
Simulation time 337135866 ps
CPU time 2.63 seconds
Started Dec 27 12:29:59 PM PST 23
Finished Dec 27 12:30:54 PM PST 23
Peak memory 202944 kb
Host smart-62d82c22-a4b0-4722-91f5-0eb100662dbb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=215311136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.215311136
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.118656888
Short name T393
Test name
Test status
Simulation time 9882408977 ps
CPU time 27.46 seconds
Started Dec 27 12:29:38 PM PST 23
Finished Dec 27 12:30:59 PM PST 23
Peak memory 203088 kb
Host smart-15914130-668c-4458-803f-596096503faa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=118656888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.118656888
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1585221970
Short name T502
Test name
Test status
Simulation time 5012497667 ps
CPU time 22.46 seconds
Started Dec 27 12:29:24 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 202804 kb
Host smart-99ab3b75-8bec-4038-ad84-e2a317bee934
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1585221970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1585221970
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2247627846
Short name T742
Test name
Test status
Simulation time 98724386 ps
CPU time 2.14 seconds
Started Dec 27 12:30:00 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 202984 kb
Host smart-813d3025-1975-414e-b2c4-ef87c42e74c0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247627846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2247627846
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.670174075
Short name T123
Test name
Test status
Simulation time 5915904921 ps
CPU time 132.05 seconds
Started Dec 27 12:28:49 PM PST 23
Finished Dec 27 12:31:53 PM PST 23
Peak memory 207840 kb
Host smart-9474bbf4-ef51-40d5-87b5-1c35f04c04c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=670174075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.670174075
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1728151492
Short name T74
Test name
Test status
Simulation time 1435255012 ps
CPU time 10.95 seconds
Started Dec 27 12:28:46 PM PST 23
Finished Dec 27 12:29:49 PM PST 23
Peak memory 203224 kb
Host smart-578cf720-0275-4800-b51a-c927514bf019
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1728151492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1728151492
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2709003309
Short name T815
Test name
Test status
Simulation time 3020260521 ps
CPU time 419.94 seconds
Started Dec 27 12:28:59 PM PST 23
Finished Dec 27 12:36:54 PM PST 23
Peak memory 220664 kb
Host smart-6cebc9c8-ce64-4dc5-aae7-0de84bda1844
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2709003309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.2709003309
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1790728514
Short name T757
Test name
Test status
Simulation time 608246999 ps
CPU time 5.19 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:29:53 PM PST 23
Peak memory 211184 kb
Host smart-774013f8-21ab-4ede-a111-a0a6c9669d9d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1790728514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1790728514
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3510036229
Short name T48
Test name
Test status
Simulation time 640921574 ps
CPU time 20.62 seconds
Started Dec 27 12:28:41 PM PST 23
Finished Dec 27 12:29:53 PM PST 23
Peak memory 211064 kb
Host smart-b41ec6be-4616-4149-b64f-0d0ea3deb64c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3510036229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3510036229
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2840353559
Short name T420
Test name
Test status
Simulation time 183929655606 ps
CPU time 655.39 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:40:28 PM PST 23
Peak memory 206616 kb
Host smart-786f6fb6-536e-4717-80b4-d895aee28e8a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2840353559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.2840353559
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2530562426
Short name T328
Test name
Test status
Simulation time 703998618 ps
CPU time 20.4 seconds
Started Dec 27 12:28:45 PM PST 23
Finished Dec 27 12:29:57 PM PST 23
Peak memory 202892 kb
Host smart-1105682b-9442-456b-b4cf-86b7f3b140d2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2530562426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2530562426
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.54068618
Short name T286
Test name
Test status
Simulation time 55958923 ps
CPU time 2.11 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:29:53 PM PST 23
Peak memory 202844 kb
Host smart-d5704fde-d025-4a05-8a35-6089944cb15f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=54068618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.54068618
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.192724687
Short name T370
Test name
Test status
Simulation time 1283341355 ps
CPU time 30.66 seconds
Started Dec 27 12:28:50 PM PST 23
Finished Dec 27 12:30:15 PM PST 23
Peak memory 204144 kb
Host smart-022a6e93-18f8-4907-a984-2583115a5af0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=192724687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.192724687
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.541055025
Short name T524
Test name
Test status
Simulation time 156631538609 ps
CPU time 194.29 seconds
Started Dec 27 12:28:41 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 204368 kb
Host smart-d267c569-9402-4ee9-9b55-88fd9d996f55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=541055025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.541055025
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.190608763
Short name T521
Test name
Test status
Simulation time 42906161143 ps
CPU time 197.94 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 204560 kb
Host smart-2f3cab85-f865-4cad-95a7-84a4e0aa6690
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=190608763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.190608763
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1949068407
Short name T60
Test name
Test status
Simulation time 250934054 ps
CPU time 21.33 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:30:09 PM PST 23
Peak memory 211060 kb
Host smart-4dd620fb-7c0e-45c1-bec5-9bb264e4db3d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949068407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1949068407
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.901440359
Short name T255
Test name
Test status
Simulation time 427872089 ps
CPU time 17.09 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:35 PM PST 23
Peak memory 203172 kb
Host smart-14a7357e-1f4e-4fba-9aeb-942718a1b112
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=901440359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.901440359
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.1020546704
Short name T589
Test name
Test status
Simulation time 44563032 ps
CPU time 2.38 seconds
Started Dec 27 12:28:38 PM PST 23
Finished Dec 27 12:29:31 PM PST 23
Peak memory 202892 kb
Host smart-68021a75-c26f-48c1-9bbf-3bd79b4919b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1020546704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1020546704
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.433403843
Short name T42
Test name
Test status
Simulation time 22338766497 ps
CPU time 37.37 seconds
Started Dec 27 12:28:50 PM PST 23
Finished Dec 27 12:30:20 PM PST 23
Peak memory 202968 kb
Host smart-b1cff2f4-a5e3-49d6-a899-3fd37575a5d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=433403843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.433403843
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3086708683
Short name T93
Test name
Test status
Simulation time 8512424884 ps
CPU time 36.13 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:30:20 PM PST 23
Peak memory 202996 kb
Host smart-f4eaad5c-5687-41d5-9948-bb30e4d6355f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3086708683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3086708683
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.760316230
Short name T612
Test name
Test status
Simulation time 24159645 ps
CPU time 2.27 seconds
Started Dec 27 12:28:44 PM PST 23
Finished Dec 27 12:29:38 PM PST 23
Peak memory 202856 kb
Host smart-2313d7fa-1d83-4519-b3bc-226097245176
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760316230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.760316230
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.180577256
Short name T67
Test name
Test status
Simulation time 2723563004 ps
CPU time 42.03 seconds
Started Dec 27 12:29:25 PM PST 23
Finished Dec 27 12:31:01 PM PST 23
Peak memory 204368 kb
Host smart-13400b29-4ad0-47df-95b4-ffa3c25cb7a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=180577256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.180577256
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.291149183
Short name T698
Test name
Test status
Simulation time 6709292816 ps
CPU time 66.07 seconds
Started Dec 27 12:29:10 PM PST 23
Finished Dec 27 12:31:10 PM PST 23
Peak memory 205236 kb
Host smart-89dde723-de0c-486d-8df7-12ca312e4d4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=291149183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.291149183
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3203618397
Short name T784
Test name
Test status
Simulation time 530867252 ps
CPU time 218.62 seconds
Started Dec 27 12:28:47 PM PST 23
Finished Dec 27 12:33:18 PM PST 23
Peak memory 208400 kb
Host smart-d7f30788-8e9c-4163-b812-845ebd35fa7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3203618397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.3203618397
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2183051449
Short name T582
Test name
Test status
Simulation time 6340485102 ps
CPU time 159.23 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:32:28 PM PST 23
Peak memory 210032 kb
Host smart-354af49e-5f0f-4d91-b696-5fbeb75f1528
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2183051449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re
set_error.2183051449
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.4139984719
Short name T670
Test name
Test status
Simulation time 60356530 ps
CPU time 8.58 seconds
Started Dec 27 12:25:07 PM PST 23
Finished Dec 27 12:25:18 PM PST 23
Peak memory 203160 kb
Host smart-03bfed90-535f-47ae-b39c-dc6f62f1d1ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4139984719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.4139984719
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3103257608
Short name T474
Test name
Test status
Simulation time 7790002357 ps
CPU time 43.74 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 203868 kb
Host smart-7aacf15a-409a-4c26-bad6-a952ca54634c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3103257608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.3103257608
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2282416374
Short name T325
Test name
Test status
Simulation time 1063955398 ps
CPU time 25.76 seconds
Started Dec 27 12:26:18 PM PST 23
Finished Dec 27 12:26:57 PM PST 23
Peak memory 202704 kb
Host smart-53d5ea9d-ee4e-4a5d-aaf6-b0c464a6d9ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2282416374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2282416374
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.3473490431
Short name T653
Test name
Test status
Simulation time 234383016 ps
CPU time 5.11 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:28:51 PM PST 23
Peak memory 202776 kb
Host smart-54734cc5-e6f9-4fcb-9bf4-5a3103b53434
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3473490431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3473490431
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.566922186
Short name T657
Test name
Test status
Simulation time 204243461 ps
CPU time 15.38 seconds
Started Dec 27 12:21:39 PM PST 23
Finished Dec 27 12:21:55 PM PST 23
Peak memory 211228 kb
Host smart-d4f7eb69-0ebc-4454-be0d-9d0363a9b577
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=566922186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.566922186
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1723848687
Short name T261
Test name
Test status
Simulation time 41530309408 ps
CPU time 178.94 seconds
Started Dec 27 12:25:07 PM PST 23
Finished Dec 27 12:28:09 PM PST 23
Peak memory 211104 kb
Host smart-b0f6ab2a-e31c-469c-8e9a-f5d45fb5d9d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723848687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1723848687
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3288633838
Short name T329
Test name
Test status
Simulation time 62580104506 ps
CPU time 224.32 seconds
Started Dec 27 12:25:12 PM PST 23
Finished Dec 27 12:28:59 PM PST 23
Peak memory 210016 kb
Host smart-2084f81e-9c0b-4989-8bef-5335b8d3a6dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3288633838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3288633838
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2829294048
Short name T729
Test name
Test status
Simulation time 160988648 ps
CPU time 22.85 seconds
Started Dec 27 12:20:26 PM PST 23
Finished Dec 27 12:20:51 PM PST 23
Peak memory 203912 kb
Host smart-1629fd2f-81bf-4b6d-8d93-cfd67bc7f1bd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829294048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2829294048
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.2210779513
Short name T592
Test name
Test status
Simulation time 5610425813 ps
CPU time 24.77 seconds
Started Dec 27 12:21:55 PM PST 23
Finished Dec 27 12:22:20 PM PST 23
Peak memory 211168 kb
Host smart-3cf4191c-b992-4b51-94a9-fa3ca487feca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2210779513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2210779513
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.319499839
Short name T347
Test name
Test status
Simulation time 1085876085 ps
CPU time 3.85 seconds
Started Dec 27 12:28:23 PM PST 23
Finished Dec 27 12:29:13 PM PST 23
Peak memory 202528 kb
Host smart-ab11c29f-b900-42ff-968c-b82f83e69054
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=319499839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.319499839
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.4211876970
Short name T220
Test name
Test status
Simulation time 5642198195 ps
CPU time 37.01 seconds
Started Dec 27 12:26:03 PM PST 23
Finished Dec 27 12:26:48 PM PST 23
Peak memory 202676 kb
Host smart-a7d2d372-4001-4f3d-aa94-557e4a6b5c51
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211876970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.4211876970
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1028157667
Short name T717
Test name
Test status
Simulation time 9356819327 ps
CPU time 34.25 seconds
Started Dec 27 12:26:13 PM PST 23
Finished Dec 27 12:26:59 PM PST 23
Peak memory 202104 kb
Host smart-904e6976-3206-4b5f-9e62-fd0534becf80
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1028157667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1028157667
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1228069002
Short name T39
Test name
Test status
Simulation time 52512085 ps
CPU time 2.3 seconds
Started Dec 27 12:25:03 PM PST 23
Finished Dec 27 12:25:07 PM PST 23
Peak memory 202896 kb
Host smart-ff851287-6edc-4fe3-b375-09566276d121
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228069002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1228069002
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2487274778
Short name T97
Test name
Test status
Simulation time 4030783834 ps
CPU time 129.64 seconds
Started Dec 27 12:27:55 PM PST 23
Finished Dec 27 12:30:38 PM PST 23
Peak memory 206512 kb
Host smart-152928ca-b3ae-4ec0-b96a-7d7e7ae9d6f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2487274778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2487274778
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3105840059
Short name T832
Test name
Test status
Simulation time 24381670395 ps
CPU time 250.11 seconds
Started Dec 27 12:22:19 PM PST 23
Finished Dec 27 12:26:30 PM PST 23
Peak memory 211184 kb
Host smart-a8cdcfa6-7016-4678-9b3f-2b8f59a81a8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3105840059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3105840059
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.841529411
Short name T479
Test name
Test status
Simulation time 212936409 ps
CPU time 72.05 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:27:42 PM PST 23
Peak memory 206048 kb
Host smart-99ddb4f9-8425-4ada-92fa-4f7bc8dbdce5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=841529411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_
reset.841529411
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3328505842
Short name T463
Test name
Test status
Simulation time 7795566233 ps
CPU time 388.44 seconds
Started Dec 27 12:27:52 PM PST 23
Finished Dec 27 12:34:53 PM PST 23
Peak memory 225076 kb
Host smart-4b2fb476-3588-425b-ac71-d0b0baaf4ab3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3328505842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.3328505842
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.198904936
Short name T532
Test name
Test status
Simulation time 297016321 ps
CPU time 9.66 seconds
Started Dec 27 12:25:06 PM PST 23
Finished Dec 27 12:25:18 PM PST 23
Peak memory 204024 kb
Host smart-e3dfa41f-5569-4377-8ed9-4deeaefe7a5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=198904936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.198904936
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.725366243
Short name T172
Test name
Test status
Simulation time 1686585597 ps
CPU time 39.2 seconds
Started Dec 27 12:29:30 PM PST 23
Finished Dec 27 12:31:02 PM PST 23
Peak memory 204380 kb
Host smart-09acc8bf-c978-478a-b435-e8836de43462
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=725366243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.725366243
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.239098746
Short name T671
Test name
Test status
Simulation time 332641734683 ps
CPU time 604.07 seconds
Started Dec 27 12:28:49 PM PST 23
Finished Dec 27 12:39:46 PM PST 23
Peak memory 211232 kb
Host smart-f8564932-f659-4be9-8c19-b2862f8ffb3d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=239098746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo
w_rsp.239098746
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.703043921
Short name T710
Test name
Test status
Simulation time 33572004 ps
CPU time 4.33 seconds
Started Dec 27 12:29:40 PM PST 23
Finished Dec 27 12:30:38 PM PST 23
Peak memory 203048 kb
Host smart-6841b169-43d0-4a1b-91ac-6cb7381421d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=703043921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.703043921
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.2347565886
Short name T471
Test name
Test status
Simulation time 1724196436 ps
CPU time 17.89 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:30:02 PM PST 23
Peak memory 202808 kb
Host smart-b165fc04-1a81-4fc2-bd8d-588477853714
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2347565886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2347565886
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.625245855
Short name T66
Test name
Test status
Simulation time 380516881 ps
CPU time 11.53 seconds
Started Dec 27 12:28:44 PM PST 23
Finished Dec 27 12:29:48 PM PST 23
Peak memory 211196 kb
Host smart-de247ac8-da56-4362-a2ba-e386494625e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=625245855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.625245855
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3640746408
Short name T528
Test name
Test status
Simulation time 29685861626 ps
CPU time 200.28 seconds
Started Dec 27 12:28:50 PM PST 23
Finished Dec 27 12:33:03 PM PST 23
Peak memory 204332 kb
Host smart-1d3fa95e-c704-451a-98ef-7330c56057f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3640746408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3640746408
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1929608807
Short name T381
Test name
Test status
Simulation time 225410603 ps
CPU time 13.58 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:30:02 PM PST 23
Peak memory 211072 kb
Host smart-1a696fe0-053f-434c-ad36-9cbf8edeed7a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929608807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1929608807
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.984355261
Short name T372
Test name
Test status
Simulation time 193871861 ps
CPU time 4.68 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:29:53 PM PST 23
Peak memory 202832 kb
Host smart-6d5d6901-7c8d-448b-93e5-f6664ae7eda4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=984355261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.984355261
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.2852008525
Short name T322
Test name
Test status
Simulation time 45024724 ps
CPU time 1.96 seconds
Started Dec 27 12:28:43 PM PST 23
Finished Dec 27 12:29:37 PM PST 23
Peak memory 203048 kb
Host smart-d6eb5e27-0553-44cc-b4e8-af36ff09e2f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2852008525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2852008525
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3250855975
Short name T809
Test name
Test status
Simulation time 4904118644 ps
CPU time 29.63 seconds
Started Dec 27 12:28:41 PM PST 23
Finished Dec 27 12:30:03 PM PST 23
Peak memory 202900 kb
Host smart-39c4603a-0469-4f54-8f9c-02aa0c705dd2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250855975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3250855975
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3597835141
Short name T446
Test name
Test status
Simulation time 9458072499 ps
CPU time 25.34 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:30:10 PM PST 23
Peak memory 203096 kb
Host smart-2461f3ad-daa0-4618-894d-08c1beec04dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3597835141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3597835141
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1718494849
Short name T247
Test name
Test status
Simulation time 62015765 ps
CPU time 1.96 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:29:48 PM PST 23
Peak memory 202964 kb
Host smart-b4151161-cd88-412e-a10c-5400471a1422
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718494849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1718494849
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3622685899
Short name T644
Test name
Test status
Simulation time 1017125652 ps
CPU time 29.24 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:30:58 PM PST 23
Peak memory 204560 kb
Host smart-679811d7-f10e-4cce-84a1-f19a25367371
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3622685899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3622685899
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3877167005
Short name T279
Test name
Test status
Simulation time 3942205887 ps
CPU time 97.01 seconds
Started Dec 27 12:28:47 PM PST 23
Finished Dec 27 12:31:16 PM PST 23
Peak memory 211220 kb
Host smart-91e92843-e226-4d5a-9601-300dce7cef69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3877167005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3877167005
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1111656514
Short name T780
Test name
Test status
Simulation time 342577660 ps
CPU time 67.41 seconds
Started Dec 27 12:28:35 PM PST 23
Finished Dec 27 12:30:33 PM PST 23
Peak memory 206260 kb
Host smart-272b5b5b-6d60-46a1-87e8-228369a522e1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1111656514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.1111656514
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3037507754
Short name T353
Test name
Test status
Simulation time 192158531 ps
CPU time 73.03 seconds
Started Dec 27 12:29:22 PM PST 23
Finished Dec 27 12:31:30 PM PST 23
Peak memory 207712 kb
Host smart-3c80166f-41a9-4cd7-9c96-3d77c3b85e59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3037507754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re
set_error.3037507754
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.4294023098
Short name T755
Test name
Test status
Simulation time 42433704 ps
CPU time 7.06 seconds
Started Dec 27 12:29:17 PM PST 23
Finished Dec 27 12:30:19 PM PST 23
Peak memory 204216 kb
Host smart-ede858be-95cd-46ad-9137-f22eaf584a40
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4294023098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.4294023098
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2901255288
Short name T636
Test name
Test status
Simulation time 295837864 ps
CPU time 5.56 seconds
Started Dec 27 12:32:25 PM PST 23
Finished Dec 27 12:33:11 PM PST 23
Peak memory 202708 kb
Host smart-7a852cc1-52f1-43db-abc0-22f0291de001
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2901255288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2901255288
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3330906132
Short name T421
Test name
Test status
Simulation time 124206495943 ps
CPU time 385.65 seconds
Started Dec 27 12:28:52 PM PST 23
Finished Dec 27 12:36:11 PM PST 23
Peak memory 206364 kb
Host smart-ce669c80-27b7-46d7-acdf-361178afb2c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3330906132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl
ow_rsp.3330906132
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3934404065
Short name T399
Test name
Test status
Simulation time 911164075 ps
CPU time 29.37 seconds
Started Dec 27 12:29:03 PM PST 23
Finished Dec 27 12:30:28 PM PST 23
Peak memory 203020 kb
Host smart-52afd26a-8332-4fc8-a602-074ff18fac73
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3934404065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3934404065
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.3558906231
Short name T405
Test name
Test status
Simulation time 1378412671 ps
CPU time 11.96 seconds
Started Dec 27 12:29:04 PM PST 23
Finished Dec 27 12:30:10 PM PST 23
Peak memory 202888 kb
Host smart-34c30308-9b44-4dfe-b7a2-f71eeee9afd9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3558906231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3558906231
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.1396084921
Short name T218
Test name
Test status
Simulation time 228969183 ps
CPU time 16.87 seconds
Started Dec 27 12:31:53 PM PST 23
Finished Dec 27 12:32:56 PM PST 23
Peak memory 203660 kb
Host smart-19849b5f-65b1-4903-a5d5-76e325a81d86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1396084921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1396084921
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.1625851937
Short name T359
Test name
Test status
Simulation time 17688060503 ps
CPU time 51.08 seconds
Started Dec 27 12:28:52 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 211152 kb
Host smart-cd3d1f80-291d-46ea-abf2-bbafcfd35867
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625851937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1625851937
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.635959218
Short name T365
Test name
Test status
Simulation time 25584485303 ps
CPU time 177.54 seconds
Started Dec 27 12:31:36 PM PST 23
Finished Dec 27 12:35:25 PM PST 23
Peak memory 203612 kb
Host smart-e5e43b10-6008-4349-9177-17594ded4570
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=635959218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.635959218
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.2135521363
Short name T672
Test name
Test status
Simulation time 75865643 ps
CPU time 10.31 seconds
Started Dec 27 12:28:58 PM PST 23
Finished Dec 27 12:30:04 PM PST 23
Peak memory 203648 kb
Host smart-64719a57-5e1d-41c0-9cb3-6caba7c682b5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135521363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2135521363
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.1478812736
Short name T300
Test name
Test status
Simulation time 423226967 ps
CPU time 8.51 seconds
Started Dec 27 12:28:50 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 203188 kb
Host smart-4284e105-227b-4805-bbed-44b8472746fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1478812736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1478812736
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.1137566540
Short name T263
Test name
Test status
Simulation time 151194398 ps
CPU time 3.18 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:29:53 PM PST 23
Peak memory 202956 kb
Host smart-f782e14d-0cf6-4cbd-882c-c5733aa3f8be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1137566540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1137566540
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.811029699
Short name T440
Test name
Test status
Simulation time 13492546361 ps
CPU time 40.92 seconds
Started Dec 27 12:28:46 PM PST 23
Finished Dec 27 12:30:18 PM PST 23
Peak memory 202952 kb
Host smart-c746ed76-21b4-493c-b479-b0e1c943d29a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=811029699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.811029699
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1800347922
Short name T493
Test name
Test status
Simulation time 29808939 ps
CPU time 2.2 seconds
Started Dec 27 12:28:52 PM PST 23
Finished Dec 27 12:29:48 PM PST 23
Peak memory 202852 kb
Host smart-90d76921-e9c5-4cfe-b23c-7cbdd20d1ccc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800347922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1800347922
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.469904158
Short name T199
Test name
Test status
Simulation time 4487053175 ps
CPU time 89.05 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:31:17 PM PST 23
Peak memory 207660 kb
Host smart-1f94b4bc-ba11-4fab-a98a-5e1aeeaef87e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=469904158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.469904158
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2554043034
Short name T5
Test name
Test status
Simulation time 5041363786 ps
CPU time 39.7 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:30:30 PM PST 23
Peak memory 204332 kb
Host smart-044dc50e-f459-4f0f-a65a-fd6b62f98d33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2554043034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2554043034
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3200058744
Short name T130
Test name
Test status
Simulation time 7025012568 ps
CPU time 357.97 seconds
Started Dec 27 12:29:00 PM PST 23
Finished Dec 27 12:35:53 PM PST 23
Peak memory 207996 kb
Host smart-76f01cc7-5353-467e-b762-26ea72c2b2f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3200058744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.3200058744
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.891075973
Short name T475
Test name
Test status
Simulation time 4799065784 ps
CPU time 62.9 seconds
Started Dec 27 12:29:38 PM PST 23
Finished Dec 27 12:31:35 PM PST 23
Peak memory 207752 kb
Host smart-dd781bdc-4f45-40dd-8c1b-8c391db1bbc9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=891075973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res
et_error.891075973
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2894191739
Short name T508
Test name
Test status
Simulation time 567076924 ps
CPU time 11.67 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:29:58 PM PST 23
Peak memory 204160 kb
Host smart-dedddf7b-98d3-464b-810c-622150daeadc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2894191739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2894191739
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2885586130
Short name T741
Test name
Test status
Simulation time 1482675151 ps
CPU time 34.38 seconds
Started Dec 27 12:29:00 PM PST 23
Finished Dec 27 12:30:30 PM PST 23
Peak memory 211204 kb
Host smart-0aa004bc-7d03-43f6-bb5c-65e128449e80
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2885586130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2885586130
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.113226963
Short name T830
Test name
Test status
Simulation time 65716530995 ps
CPU time 540.11 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:38:50 PM PST 23
Peak memory 211292 kb
Host smart-ae91e9a7-a471-438f-9fd3-291b95dae138
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=113226963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slo
w_rsp.113226963
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.432645175
Short name T453
Test name
Test status
Simulation time 178792373 ps
CPU time 3.32 seconds
Started Dec 27 12:28:58 PM PST 23
Finished Dec 27 12:29:57 PM PST 23
Peak memory 203004 kb
Host smart-aa9fa272-8a52-464f-b5bb-76cea69688de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=432645175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.432645175
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.2559976811
Short name T823
Test name
Test status
Simulation time 73639321 ps
CPU time 8.41 seconds
Started Dec 27 12:28:43 PM PST 23
Finished Dec 27 12:29:44 PM PST 23
Peak memory 202904 kb
Host smart-1311ff91-a8b6-490e-ba6a-8228a71fb9ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2559976811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2559976811
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.2992270075
Short name T432
Test name
Test status
Simulation time 2860663363 ps
CPU time 39.96 seconds
Started Dec 27 12:29:02 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 203992 kb
Host smart-cc97c70b-3a6a-4032-91fc-2c29ed9ee535
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2992270075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2992270075
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1793557191
Short name T395
Test name
Test status
Simulation time 21147965347 ps
CPU time 56 seconds
Started Dec 27 12:32:50 PM PST 23
Finished Dec 27 12:34:22 PM PST 23
Peak memory 210924 kb
Host smart-6c1d2960-42fc-4600-84ec-f5fc9e556786
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793557191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1793557191
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1375838089
Short name T91
Test name
Test status
Simulation time 17546078591 ps
CPU time 97.43 seconds
Started Dec 27 12:29:01 PM PST 23
Finished Dec 27 12:31:34 PM PST 23
Peak memory 211276 kb
Host smart-d94b9f7e-0466-4e1b-b2aa-d184cd5c235f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1375838089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1375838089
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3276503622
Short name T324
Test name
Test status
Simulation time 24771040 ps
CPU time 2.18 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:29:47 PM PST 23
Peak memory 203028 kb
Host smart-987447ce-3de8-4328-85ba-ab12079b5b9b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276503622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3276503622
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.3161191706
Short name T659
Test name
Test status
Simulation time 739091776 ps
CPU time 16.87 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:30:05 PM PST 23
Peak memory 202888 kb
Host smart-c3db153e-810b-489e-b071-4845576a6781
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3161191706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3161191706
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.448194819
Short name T575
Test name
Test status
Simulation time 27614864 ps
CPU time 2.18 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:29:53 PM PST 23
Peak memory 202856 kb
Host smart-cbf1b9c7-03c1-4141-8d9c-9aa2d15fdd49
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=448194819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.448194819
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.1014433826
Short name T344
Test name
Test status
Simulation time 5986388082 ps
CPU time 26.18 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:30:11 PM PST 23
Peak memory 202964 kb
Host smart-27ac3985-3a29-493c-83bd-2ed894228d04
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1014433826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1014433826
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3476909548
Short name T861
Test name
Test status
Simulation time 81773305 ps
CPU time 2.18 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:29:49 PM PST 23
Peak memory 202852 kb
Host smart-3829a512-02b4-4765-8b32-87c63e887343
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476909548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3476909548
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1354762451
Short name T651
Test name
Test status
Simulation time 1624127412 ps
CPU time 161.26 seconds
Started Dec 27 12:29:38 PM PST 23
Finished Dec 27 12:33:13 PM PST 23
Peak memory 205348 kb
Host smart-84a04bef-047b-4f7b-9200-7e412791e362
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1354762451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1354762451
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1077158579
Short name T158
Test name
Test status
Simulation time 10564420659 ps
CPU time 79.3 seconds
Started Dec 27 12:28:45 PM PST 23
Finished Dec 27 12:30:56 PM PST 23
Peak memory 205352 kb
Host smart-db3b76de-0a6c-4537-8ab8-0ab0e5d3b8d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1077158579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1077158579
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1931360852
Short name T106
Test name
Test status
Simulation time 11392865634 ps
CPU time 364.31 seconds
Started Dec 27 12:29:03 PM PST 23
Finished Dec 27 12:36:02 PM PST 23
Peak memory 211080 kb
Host smart-aa6b13a9-148f-49dc-bbf3-9be48425e10d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1931360852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.1931360852
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.45076383
Short name T24
Test name
Test status
Simulation time 2429628209 ps
CPU time 221.56 seconds
Started Dec 27 12:30:08 PM PST 23
Finished Dec 27 12:34:42 PM PST 23
Peak memory 219384 kb
Host smart-aef24ea7-4701-4dad-b21a-018e557bbbb9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45076383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rese
t_error.45076383
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3786587367
Short name T552
Test name
Test status
Simulation time 278180430 ps
CPU time 15.22 seconds
Started Dec 27 12:28:48 PM PST 23
Finished Dec 27 12:29:56 PM PST 23
Peak memory 211104 kb
Host smart-1091a572-68bf-45b6-b1e6-c45c2614b1c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3786587367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3786587367
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2688923637
Short name T638
Test name
Test status
Simulation time 3578712385 ps
CPU time 59.22 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:30:49 PM PST 23
Peak memory 204548 kb
Host smart-b1d1bed1-eb9f-4fc7-adf6-b348d0c4445b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2688923637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2688923637
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1040637240
Short name T387
Test name
Test status
Simulation time 1396392635 ps
CPU time 11.9 seconds
Started Dec 27 12:28:52 PM PST 23
Finished Dec 27 12:29:57 PM PST 23
Peak memory 203084 kb
Host smart-6ed7f85d-cd2a-48b3-bdd9-58df7e8665e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1040637240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1040637240
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.1443926266
Short name T738
Test name
Test status
Simulation time 54638496 ps
CPU time 4.47 seconds
Started Dec 27 12:28:52 PM PST 23
Finished Dec 27 12:29:50 PM PST 23
Peak memory 202900 kb
Host smart-22dde804-67e1-4b76-ac85-55c423e516fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1443926266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1443926266
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.3154833866
Short name T211
Test name
Test status
Simulation time 68046996105 ps
CPU time 242.24 seconds
Started Dec 27 12:29:09 PM PST 23
Finished Dec 27 12:34:05 PM PST 23
Peak memory 211212 kb
Host smart-3094b70b-ec32-4307-aa64-fa074fa7b328
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154833866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3154833866
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2481314264
Short name T129
Test name
Test status
Simulation time 16141762496 ps
CPU time 111.37 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:31:39 PM PST 23
Peak memory 211036 kb
Host smart-6a9e7b6a-ab52-4a1b-9820-f7accd89c044
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2481314264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2481314264
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1305252185
Short name T514
Test name
Test status
Simulation time 56818809 ps
CPU time 5.77 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:29:53 PM PST 23
Peak memory 211084 kb
Host smart-623e91ff-a90a-488d-8c28-030780c4d9f1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305252185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1305252185
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.1560826724
Short name T818
Test name
Test status
Simulation time 1424508810 ps
CPU time 11.37 seconds
Started Dec 27 12:29:04 PM PST 23
Finished Dec 27 12:30:10 PM PST 23
Peak memory 202840 kb
Host smart-2712d597-e2b2-4e1b-b754-f40f7c230c0b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1560826724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1560826724
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.863648901
Short name T537
Test name
Test status
Simulation time 139680799 ps
CPU time 3.18 seconds
Started Dec 27 12:32:25 PM PST 23
Finished Dec 27 12:33:08 PM PST 23
Peak memory 202700 kb
Host smart-54b392eb-4cd6-4cc0-985a-28ddbd1f3ca2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=863648901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.863648901
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2460138826
Short name T321
Test name
Test status
Simulation time 10810084347 ps
CPU time 30.16 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:30:21 PM PST 23
Peak memory 203096 kb
Host smart-71913967-6a1a-4847-9b56-89e9526bc2dc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460138826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2460138826
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3627119408
Short name T239
Test name
Test status
Simulation time 80659172 ps
CPU time 2.26 seconds
Started Dec 27 12:28:42 PM PST 23
Finished Dec 27 12:29:37 PM PST 23
Peak memory 202892 kb
Host smart-f508c98b-a5c6-4c82-b56c-47be62bf54fe
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627119408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3627119408
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1197025924
Short name T845
Test name
Test status
Simulation time 528133420 ps
CPU time 62.17 seconds
Started Dec 27 12:29:35 PM PST 23
Finished Dec 27 12:31:32 PM PST 23
Peak memory 205192 kb
Host smart-aebee5b0-8fa5-47a4-8ebc-f97c6a8f2a37
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1197025924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1197025924
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.510359975
Short name T226
Test name
Test status
Simulation time 5858605705 ps
CPU time 180.46 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 209612 kb
Host smart-c96e5796-04b5-4472-81ad-8ff753b2f18e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=510359975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.510359975
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2123754793
Short name T693
Test name
Test status
Simulation time 418918012 ps
CPU time 128.29 seconds
Started Dec 27 12:29:18 PM PST 23
Finished Dec 27 12:32:21 PM PST 23
Peak memory 207428 kb
Host smart-a2ebbec6-62e5-443e-a8db-c1186212975d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2123754793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.2123754793
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3234255687
Short name T619
Test name
Test status
Simulation time 767148668 ps
CPU time 167.42 seconds
Started Dec 27 12:28:59 PM PST 23
Finished Dec 27 12:32:41 PM PST 23
Peak memory 211180 kb
Host smart-42cb651b-4b3c-400e-bf68-71cabe16dd3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3234255687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.3234255687
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3563947038
Short name T357
Test name
Test status
Simulation time 601363018 ps
CPU time 19.91 seconds
Started Dec 27 12:29:09 PM PST 23
Finished Dec 27 12:30:23 PM PST 23
Peak memory 211028 kb
Host smart-d89fb6d3-d05e-4750-af10-cba4ef2387ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3563947038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3563947038
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1357130699
Short name T100
Test name
Test status
Simulation time 25429493 ps
CPU time 2.55 seconds
Started Dec 27 12:29:01 PM PST 23
Finished Dec 27 12:29:59 PM PST 23
Peak memory 202992 kb
Host smart-6108f636-06c6-4531-9ac9-c68f53186149
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1357130699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1357130699
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.764599035
Short name T810
Test name
Test status
Simulation time 49836242066 ps
CPU time 336.43 seconds
Started Dec 27 12:28:45 PM PST 23
Finished Dec 27 12:35:14 PM PST 23
Peak memory 211176 kb
Host smart-7b886e03-6b57-4c1f-a591-63e6458ddffc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=764599035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo
w_rsp.764599035
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.32732559
Short name T665
Test name
Test status
Simulation time 175545875 ps
CPU time 2.97 seconds
Started Dec 27 12:29:01 PM PST 23
Finished Dec 27 12:30:00 PM PST 23
Peak memory 202852 kb
Host smart-71be9138-dc1e-4f41-aafa-64491de72c02
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=32732559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.32732559
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.2780601246
Short name T631
Test name
Test status
Simulation time 340772213 ps
CPU time 9.47 seconds
Started Dec 27 12:29:11 PM PST 23
Finished Dec 27 12:30:15 PM PST 23
Peak memory 202804 kb
Host smart-ad5270ab-4ff5-4a4f-8e45-00a51071d487
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2780601246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2780601246
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.984890159
Short name T241
Test name
Test status
Simulation time 941432001 ps
CPU time 33.18 seconds
Started Dec 27 12:28:52 PM PST 23
Finished Dec 27 12:30:19 PM PST 23
Peak memory 211116 kb
Host smart-a6003c3d-2b91-48fc-934f-b0ca8f6fc1a3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=984890159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.984890159
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.3933479489
Short name T495
Test name
Test status
Simulation time 32239183304 ps
CPU time 82.4 seconds
Started Dec 27 12:29:22 PM PST 23
Finished Dec 27 12:31:39 PM PST 23
Peak memory 211264 kb
Host smart-b624491a-43a8-4aff-bcd7-06cd4cf3eeff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933479489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3933479489
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.945844576
Short name T108
Test name
Test status
Simulation time 29410273495 ps
CPU time 250.23 seconds
Started Dec 27 12:28:50 PM PST 23
Finished Dec 27 12:33:54 PM PST 23
Peak memory 211300 kb
Host smart-66580670-9ccb-4e68-ae3d-1c48204490f2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=945844576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.945844576
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.737501108
Short name T223
Test name
Test status
Simulation time 312250006 ps
CPU time 16.08 seconds
Started Dec 27 12:29:33 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 203920 kb
Host smart-e6372db2-f91b-4f91-bf0e-acc077eaab20
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737501108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.737501108
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.1081297871
Short name T237
Test name
Test status
Simulation time 1273560919 ps
CPU time 25.54 seconds
Started Dec 27 12:29:19 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 202916 kb
Host smart-9f0a76ed-1801-4f91-9096-b956a8c9c9a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1081297871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1081297871
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2741560014
Short name T49
Test name
Test status
Simulation time 5596858801 ps
CPU time 22.13 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:41 PM PST 23
Peak memory 202952 kb
Host smart-01c782a3-bc3a-4892-b305-9a8708415096
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741560014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2741560014
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2686745947
Short name T668
Test name
Test status
Simulation time 2860870150 ps
CPU time 25.4 seconds
Started Dec 27 12:29:11 PM PST 23
Finished Dec 27 12:30:31 PM PST 23
Peak memory 202912 kb
Host smart-8c940fef-d70e-4609-ae41-a495d6617e13
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2686745947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2686745947
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2037992423
Short name T182
Test name
Test status
Simulation time 135166178 ps
CPU time 2.48 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:21 PM PST 23
Peak memory 203016 kb
Host smart-e8781ec9-83d5-4c65-b0ed-07cc0b9a45d2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037992423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2037992423
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.666475739
Short name T494
Test name
Test status
Simulation time 7845591177 ps
CPU time 125.04 seconds
Started Dec 27 12:29:24 PM PST 23
Finished Dec 27 12:32:23 PM PST 23
Peak memory 208500 kb
Host smart-a93206ee-f05f-48dd-972f-872c1dfe01a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=666475739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.666475739
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.926835729
Short name T468
Test name
Test status
Simulation time 16745216167 ps
CPU time 208.83 seconds
Started Dec 27 12:29:25 PM PST 23
Finished Dec 27 12:33:49 PM PST 23
Peak memory 204960 kb
Host smart-90895cf7-e5e9-40b7-b85c-dd7177e30210
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=926835729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.926835729
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4114328781
Short name T171
Test name
Test status
Simulation time 1259519448 ps
CPU time 39.77 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:31:16 PM PST 23
Peak memory 205156 kb
Host smart-0742daea-fd0b-4e27-81a9-73ed9afeeabf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4114328781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.4114328781
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2835488551
Short name T540
Test name
Test status
Simulation time 670514650 ps
CPU time 197.75 seconds
Started Dec 27 12:28:49 PM PST 23
Finished Dec 27 12:33:00 PM PST 23
Peak memory 210776 kb
Host smart-2da0045c-e761-461a-adc9-20be6c248038
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2835488551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.2835488551
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.781726418
Short name T348
Test name
Test status
Simulation time 102586165 ps
CPU time 17.83 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:30:08 PM PST 23
Peak memory 211112 kb
Host smart-0a53250a-6dae-4cfe-b03c-a9e44aadc676
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=781726418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.781726418
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.102390793
Short name T173
Test name
Test status
Simulation time 920939349 ps
CPU time 24.24 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 204540 kb
Host smart-42b9aa15-72f6-407d-9efe-b42f9125bec7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=102390793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.102390793
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1447877599
Short name T736
Test name
Test status
Simulation time 54625393582 ps
CPU time 258.04 seconds
Started Dec 27 12:29:06 PM PST 23
Finished Dec 27 12:34:17 PM PST 23
Peak memory 211100 kb
Host smart-39ac23ba-7bae-4531-90b9-bb55236de7bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1447877599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.1447877599
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2877200595
Short name T256
Test name
Test status
Simulation time 140854401 ps
CPU time 8.77 seconds
Started Dec 27 12:28:58 PM PST 23
Finished Dec 27 12:30:02 PM PST 23
Peak memory 202896 kb
Host smart-aa8b17a0-169b-4d15-a474-a053311ba139
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2877200595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2877200595
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.2097781625
Short name T294
Test name
Test status
Simulation time 58454218 ps
CPU time 6.27 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:30:47 PM PST 23
Peak memory 202868 kb
Host smart-af5a44b7-5744-425e-89c3-639459da2685
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2097781625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2097781625
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.748186380
Short name T525
Test name
Test status
Simulation time 186145101 ps
CPU time 7.06 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:47 PM PST 23
Peak memory 203584 kb
Host smart-ad641818-cbf4-48cf-b7c6-b617c2e53889
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=748186380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.748186380
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.934320687
Short name T391
Test name
Test status
Simulation time 9492450499 ps
CPU time 32.11 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:30:22 PM PST 23
Peak memory 203100 kb
Host smart-fdc6c687-d797-42ea-97ad-efcf22bf5075
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=934320687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.934320687
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3171429387
Short name T848
Test name
Test status
Simulation time 28926694068 ps
CPU time 197.5 seconds
Started Dec 27 12:29:07 PM PST 23
Finished Dec 27 12:33:17 PM PST 23
Peak memory 211188 kb
Host smart-bfe610d3-28fe-44e9-9ab0-deacd9866f65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3171429387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3171429387
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.1202061433
Short name T413
Test name
Test status
Simulation time 16892716 ps
CPU time 2.25 seconds
Started Dec 27 12:29:29 PM PST 23
Finished Dec 27 12:30:24 PM PST 23
Peak memory 203056 kb
Host smart-7ab6166b-3f13-4299-92a4-ff3a7033c721
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202061433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1202061433
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.3481523879
Short name T80
Test name
Test status
Simulation time 1420065322 ps
CPU time 20.73 seconds
Started Dec 27 12:31:11 PM PST 23
Finished Dec 27 12:32:20 PM PST 23
Peak memory 201888 kb
Host smart-77523992-7833-4082-879e-d93a3c72876c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3481523879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3481523879
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.4035908059
Short name T194
Test name
Test status
Simulation time 27166921 ps
CPU time 2.14 seconds
Started Dec 27 12:28:59 PM PST 23
Finished Dec 27 12:29:56 PM PST 23
Peak memory 203004 kb
Host smart-1973d902-6d20-4d7e-868a-ea3b4295b978
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4035908059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4035908059
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.4030093341
Short name T585
Test name
Test status
Simulation time 29969177479 ps
CPU time 39.38 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:30:29 PM PST 23
Peak memory 202920 kb
Host smart-e7bed417-688a-428c-885b-4644b08989b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030093341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.4030093341
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1757713388
Short name T857
Test name
Test status
Simulation time 6184761082 ps
CPU time 31.57 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:30:18 PM PST 23
Peak memory 203056 kb
Host smart-7505f931-45a4-4e16-ba6c-9a735c6da544
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1757713388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1757713388
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1571494047
Short name T374
Test name
Test status
Simulation time 31224808 ps
CPU time 1.87 seconds
Started Dec 27 12:28:57 PM PST 23
Finished Dec 27 12:29:53 PM PST 23
Peak memory 203032 kb
Host smart-3b2b14c3-dad3-4a4e-b707-71b4b40a5fe8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571494047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1571494047
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.705394278
Short name T835
Test name
Test status
Simulation time 9392275157 ps
CPU time 156.38 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:33:17 PM PST 23
Peak memory 206244 kb
Host smart-1dadf313-de6e-4c5d-9c5a-1f321a860816
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=705394278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.705394278
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1598796255
Short name T139
Test name
Test status
Simulation time 8818756848 ps
CPU time 349.06 seconds
Started Dec 27 12:29:03 PM PST 23
Finished Dec 27 12:35:47 PM PST 23
Peak memory 221044 kb
Host smart-1a5d2a23-5e8e-47df-8e6f-5e1c07920e59
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1598796255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.1598796255
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.105461035
Short name T52
Test name
Test status
Simulation time 549071342 ps
CPU time 13.47 seconds
Started Dec 27 12:30:15 PM PST 23
Finished Dec 27 12:31:22 PM PST 23
Peak memory 211012 kb
Host smart-ef9adf20-527b-4c0c-806e-40f970e63e86
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=105461035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.105461035
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.390021696
Short name T847
Test name
Test status
Simulation time 522570206 ps
CPU time 37.99 seconds
Started Dec 27 12:29:10 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 203624 kb
Host smart-8cd185bf-803f-4d6c-9833-4001da0c98d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=390021696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.390021696
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.380200925
Short name T94
Test name
Test status
Simulation time 45646671809 ps
CPU time 283.13 seconds
Started Dec 27 12:30:21 PM PST 23
Finished Dec 27 12:36:01 PM PST 23
Peak memory 205188 kb
Host smart-72f8e414-5904-451e-92b3-2a614bc7415b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=380200925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slo
w_rsp.380200925
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1971721933
Short name T596
Test name
Test status
Simulation time 214563525 ps
CPU time 7.96 seconds
Started Dec 27 12:29:51 PM PST 23
Finished Dec 27 12:30:50 PM PST 23
Peak memory 202812 kb
Host smart-bf6ee0f2-8780-45c3-ae66-06bf5b7439af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1971721933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1971721933
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.51225966
Short name T874
Test name
Test status
Simulation time 14941653 ps
CPU time 1.93 seconds
Started Dec 27 12:28:57 PM PST 23
Finished Dec 27 12:29:55 PM PST 23
Peak memory 202788 kb
Host smart-441052ea-297b-47fe-be1f-93c092d99686
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=51225966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.51225966
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.1541915859
Short name T191
Test name
Test status
Simulation time 129012952 ps
CPU time 4.5 seconds
Started Dec 27 12:28:57 PM PST 23
Finished Dec 27 12:30:02 PM PST 23
Peak memory 202872 kb
Host smart-08d7b104-3463-4970-8b53-7486bb2128b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1541915859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1541915859
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1302286334
Short name T718
Test name
Test status
Simulation time 30257172963 ps
CPU time 177.6 seconds
Started Dec 27 12:29:32 PM PST 23
Finished Dec 27 12:33:24 PM PST 23
Peak memory 204612 kb
Host smart-e711f27a-4d73-470a-9098-579968fce92a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302286334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1302286334
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.372921854
Short name T124
Test name
Test status
Simulation time 68649568819 ps
CPU time 117.08 seconds
Started Dec 27 12:29:31 PM PST 23
Finished Dec 27 12:32:23 PM PST 23
Peak memory 211068 kb
Host smart-b71b2d24-0014-4b04-b0ea-495940fdafb3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=372921854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.372921854
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.4184437305
Short name T200
Test name
Test status
Simulation time 357229648 ps
CPU time 13.34 seconds
Started Dec 27 12:29:18 PM PST 23
Finished Dec 27 12:30:27 PM PST 23
Peak memory 203912 kb
Host smart-b031c746-dfea-4e1a-a4ff-9272531c2e7a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184437305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.4184437305
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.3227266454
Short name T826
Test name
Test status
Simulation time 1372049310 ps
CPU time 22.42 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:31:03 PM PST 23
Peak memory 202872 kb
Host smart-ba0023e0-d112-4a59-9a27-8ee1a8d2d24d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3227266454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3227266454
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.1774257645
Short name T625
Test name
Test status
Simulation time 139636864 ps
CPU time 2.17 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:29:49 PM PST 23
Peak memory 202868 kb
Host smart-a8032098-4c3e-4271-a9bc-0724cefbe063
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1774257645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1774257645
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.8457972
Short name T868
Test name
Test status
Simulation time 7348255546 ps
CPU time 30.28 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:31:09 PM PST 23
Peak memory 202940 kb
Host smart-3808b7ca-ee4c-4914-89a9-074dcc0d55d6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=8457972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.8457972
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2349194582
Short name T854
Test name
Test status
Simulation time 4720277268 ps
CPU time 25.32 seconds
Started Dec 27 12:28:50 PM PST 23
Finished Dec 27 12:30:09 PM PST 23
Peak memory 203072 kb
Host smart-fc75c36f-2f1b-4a75-be70-bda30273ab36
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2349194582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2349194582
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3790715084
Short name T541
Test name
Test status
Simulation time 60263073 ps
CPU time 2.13 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 203008 kb
Host smart-607e1184-76d5-4919-91c0-3327e01a9629
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790715084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3790715084
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.4285454819
Short name T190
Test name
Test status
Simulation time 1120213126 ps
CPU time 71.59 seconds
Started Dec 27 12:28:57 PM PST 23
Finished Dec 27 12:31:04 PM PST 23
Peak memory 204804 kb
Host smart-110896b0-983e-4ab1-ab4e-54959e2d14f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4285454819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.4285454819
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2840789545
Short name T272
Test name
Test status
Simulation time 1244818610 ps
CPU time 130.13 seconds
Started Dec 27 12:30:12 PM PST 23
Finished Dec 27 12:33:16 PM PST 23
Peak memory 209248 kb
Host smart-959970a6-2efb-4fc0-8652-b8fe03425ea0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2840789545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2840789545
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.865568486
Short name T643
Test name
Test status
Simulation time 4903238832 ps
CPU time 159.56 seconds
Started Dec 27 12:28:57 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 210372 kb
Host smart-b390c5ec-469b-44a8-8d46-478331b9c1c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=865568486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res
et_error.865568486
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.4292074588
Short name T779
Test name
Test status
Simulation time 736586707 ps
CPU time 6.62 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:29:55 PM PST 23
Peak memory 204092 kb
Host smart-009496ad-fc81-46a7-9418-4efe23fbd1d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4292074588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4292074588
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1078079585
Short name T99
Test name
Test status
Simulation time 1964698545 ps
CPU time 57.42 seconds
Started Dec 27 12:29:01 PM PST 23
Finished Dec 27 12:30:54 PM PST 23
Peak memory 211052 kb
Host smart-97d59d05-5214-4a74-8e62-974c2a56434b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1078079585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1078079585
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3905525735
Short name T277
Test name
Test status
Simulation time 40821548641 ps
CPU time 305.68 seconds
Started Dec 27 12:29:42 PM PST 23
Finished Dec 27 12:35:41 PM PST 23
Peak memory 205912 kb
Host smart-d3180e10-4bf4-4de4-9dfb-5ce1a0b349d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3905525735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.3905525735
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3894372716
Short name T118
Test name
Test status
Simulation time 123193234 ps
CPU time 4.36 seconds
Started Dec 27 12:29:05 PM PST 23
Finished Dec 27 12:30:03 PM PST 23
Peak memory 203016 kb
Host smart-d2db4365-57cf-4de9-8c2b-048b50255af6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3894372716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3894372716
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.2812172158
Short name T526
Test name
Test status
Simulation time 149622597 ps
CPU time 13.23 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 202928 kb
Host smart-fd14cc5b-bea8-48db-b1d2-1b4191f3e591
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2812172158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2812172158
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.1342632626
Short name T246
Test name
Test status
Simulation time 1039837827 ps
CPU time 23.46 seconds
Started Dec 27 12:30:06 PM PST 23
Finished Dec 27 12:31:22 PM PST 23
Peak memory 203116 kb
Host smart-7d0d4ace-d04b-4b6f-80a6-7ad60ebd8842
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1342632626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.1342632626
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3530867737
Short name T773
Test name
Test status
Simulation time 28081193215 ps
CPU time 102.55 seconds
Started Dec 27 12:30:12 PM PST 23
Finished Dec 27 12:32:48 PM PST 23
Peak memory 204052 kb
Host smart-0afe4ea9-5647-404b-9d44-6af0a8d3cbf2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530867737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3530867737
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1216292956
Short name T568
Test name
Test status
Simulation time 21747419446 ps
CPU time 138.45 seconds
Started Dec 27 12:29:19 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 204300 kb
Host smart-895522fc-6d2e-4b5f-8d87-e91326e419df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1216292956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1216292956
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1644675117
Short name T557
Test name
Test status
Simulation time 404143251 ps
CPU time 15.9 seconds
Started Dec 27 12:29:24 PM PST 23
Finished Dec 27 12:30:34 PM PST 23
Peak memory 211072 kb
Host smart-10610b23-71b4-4c3f-91a1-816f974d48ff
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644675117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1644675117
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.924485123
Short name T491
Test name
Test status
Simulation time 1001800124 ps
CPU time 20.48 seconds
Started Dec 27 12:29:33 PM PST 23
Finished Dec 27 12:30:48 PM PST 23
Peak memory 203444 kb
Host smart-d1053ae4-20ec-4a41-848d-a6a9edfcabfd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=924485123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.924485123
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.4018442879
Short name T397
Test name
Test status
Simulation time 210698850 ps
CPU time 3.77 seconds
Started Dec 27 12:30:32 PM PST 23
Finished Dec 27 12:31:33 PM PST 23
Peak memory 202964 kb
Host smart-a30bcc92-58ce-45bc-9a90-eea54831dd6a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4018442879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4018442879
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2694583272
Short name T789
Test name
Test status
Simulation time 9159798079 ps
CPU time 32.25 seconds
Started Dec 27 12:29:52 PM PST 23
Finished Dec 27 12:31:16 PM PST 23
Peak memory 202988 kb
Host smart-a07e70f5-f29b-4912-90ee-ea41b0ce2535
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694583272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2694583272
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3619561741
Short name T466
Test name
Test status
Simulation time 30492798 ps
CPU time 2.13 seconds
Started Dec 27 12:28:59 PM PST 23
Finished Dec 27 12:29:56 PM PST 23
Peak memory 202884 kb
Host smart-5fbb865a-47e9-445b-aa7a-506677060cc6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619561741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3619561741
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.1395665859
Short name T82
Test name
Test status
Simulation time 949767669 ps
CPU time 25.2 seconds
Started Dec 27 12:29:42 PM PST 23
Finished Dec 27 12:31:01 PM PST 23
Peak memory 204760 kb
Host smart-aff8056e-4575-47d7-a20d-b2efa00bbe5b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1395665859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1395665859
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.681081205
Short name T501
Test name
Test status
Simulation time 1525584728 ps
CPU time 104.23 seconds
Started Dec 27 12:30:39 PM PST 23
Finished Dec 27 12:33:20 PM PST 23
Peak memory 205676 kb
Host smart-14526cad-e1ae-4b9a-8bf5-39f8917970cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=681081205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.681081205
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2634961556
Short name T390
Test name
Test status
Simulation time 388603177 ps
CPU time 92.14 seconds
Started Dec 27 12:29:16 PM PST 23
Finished Dec 27 12:31:43 PM PST 23
Peak memory 207556 kb
Host smart-5e0eafd8-38eb-4c34-9564-d14f5533fd41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2634961556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.2634961556
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1694216231
Short name T527
Test name
Test status
Simulation time 29912012 ps
CPU time 6.85 seconds
Started Dec 27 12:29:02 PM PST 23
Finished Dec 27 12:30:03 PM PST 23
Peak memory 202948 kb
Host smart-2f7c3a35-b59a-4594-9832-950a4a9acd30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1694216231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.1694216231
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.413863709
Short name T764
Test name
Test status
Simulation time 270760097 ps
CPU time 10.09 seconds
Started Dec 27 12:28:57 PM PST 23
Finished Dec 27 12:30:02 PM PST 23
Peak memory 204088 kb
Host smart-b490a545-4534-4434-9648-ef572419d096
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=413863709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.413863709
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.3235270411
Short name T81
Test name
Test status
Simulation time 2641082734 ps
CPU time 63.72 seconds
Started Dec 27 12:29:52 PM PST 23
Finished Dec 27 12:31:47 PM PST 23
Peak memory 206252 kb
Host smart-9932201f-0ac2-4fff-8c71-71121ca04510
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3235270411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3235270411
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1974250123
Short name T553
Test name
Test status
Simulation time 118267470465 ps
CPU time 398.77 seconds
Started Dec 27 12:29:12 PM PST 23
Finished Dec 27 12:36:46 PM PST 23
Peak memory 206044 kb
Host smart-c9601714-488d-4f86-bb3b-264dc16b163e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1974250123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.1974250123
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3867512959
Short name T650
Test name
Test status
Simulation time 134332754 ps
CPU time 16.04 seconds
Started Dec 27 12:29:06 PM PST 23
Finished Dec 27 12:30:15 PM PST 23
Peak memory 203036 kb
Host smart-88b5bf69-9e81-41b8-97bb-15de5c4e6952
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3867512959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3867512959
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.1547358652
Short name T145
Test name
Test status
Simulation time 2589869979 ps
CPU time 24.57 seconds
Started Dec 27 12:29:18 PM PST 23
Finished Dec 27 12:30:38 PM PST 23
Peak memory 202868 kb
Host smart-16a19b9b-c028-45af-9083-70eee5a38186
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1547358652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1547358652
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.526146139
Short name T660
Test name
Test status
Simulation time 3884988746 ps
CPU time 24.74 seconds
Started Dec 27 12:29:56 PM PST 23
Finished Dec 27 12:31:13 PM PST 23
Peak memory 211128 kb
Host smart-19c26fc0-edeb-4725-b2a4-e6e92b7e9e27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=526146139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.526146139
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3212429278
Short name T795
Test name
Test status
Simulation time 147948265116 ps
CPU time 184.53 seconds
Started Dec 27 12:31:38 PM PST 23
Finished Dec 27 12:35:34 PM PST 23
Peak memory 210908 kb
Host smart-f2b9cb02-585b-4cb2-8591-bf5384b421b8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212429278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3212429278
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3166986201
Short name T842
Test name
Test status
Simulation time 18490799773 ps
CPU time 119.82 seconds
Started Dec 27 12:30:06 PM PST 23
Finished Dec 27 12:32:57 PM PST 23
Peak memory 211132 kb
Host smart-dafa3122-091e-442d-ad86-14f81279b11c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3166986201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3166986201
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2589430098
Short name T758
Test name
Test status
Simulation time 131575616 ps
CPU time 10.32 seconds
Started Dec 27 12:29:57 PM PST 23
Finished Dec 27 12:31:00 PM PST 23
Peak memory 210992 kb
Host smart-bbdefa57-5e2a-40ca-bf6b-ea590ef6080a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589430098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2589430098
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.3056482358
Short name T833
Test name
Test status
Simulation time 514500086 ps
CPU time 10.46 seconds
Started Dec 27 12:29:11 PM PST 23
Finished Dec 27 12:30:15 PM PST 23
Peak memory 202844 kb
Host smart-9cfeab93-d22c-4f6d-a181-0b9368e8b799
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3056482358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3056482358
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.3122138848
Short name T608
Test name
Test status
Simulation time 91768773 ps
CPU time 2.74 seconds
Started Dec 27 12:30:24 PM PST 23
Finished Dec 27 12:31:24 PM PST 23
Peak memory 202900 kb
Host smart-d95b4338-4cb5-497e-8496-40ab41d7771f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3122138848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3122138848
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.477368163
Short name T581
Test name
Test status
Simulation time 6647121922 ps
CPU time 32.94 seconds
Started Dec 27 12:29:25 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 203076 kb
Host smart-7d8771ab-63c4-4a9a-b31c-f136862012a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=477368163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.477368163
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1711530973
Short name T507
Test name
Test status
Simulation time 8006239802 ps
CPU time 28.84 seconds
Started Dec 27 12:29:11 PM PST 23
Finished Dec 27 12:30:34 PM PST 23
Peak memory 202920 kb
Host smart-021fe88b-9ff3-4ec8-9fc3-9bcf2c487d67
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1711530973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1711530973
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1567209000
Short name T554
Test name
Test status
Simulation time 33156363 ps
CPU time 1.99 seconds
Started Dec 27 12:29:53 PM PST 23
Finished Dec 27 12:30:46 PM PST 23
Peak memory 203020 kb
Host smart-6912d544-a28d-43d9-a708-b4298d5e904c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567209000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1567209000
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1906804719
Short name T862
Test name
Test status
Simulation time 11005640386 ps
CPU time 207.2 seconds
Started Dec 27 12:29:09 PM PST 23
Finished Dec 27 12:33:31 PM PST 23
Peak memory 206892 kb
Host smart-d6415dfd-7ec6-4957-b366-63f189c6debf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1906804719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1906804719
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.4183904523
Short name T295
Test name
Test status
Simulation time 1932646098 ps
CPU time 32.66 seconds
Started Dec 27 12:29:12 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 203156 kb
Host smart-605ab768-53ad-4ff5-ac6c-3b2196344df2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4183904523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.4183904523
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.1706255596
Short name T425
Test name
Test status
Simulation time 331891481 ps
CPU time 89.96 seconds
Started Dec 27 12:28:59 PM PST 23
Finished Dec 27 12:31:24 PM PST 23
Peak memory 207328 kb
Host smart-31b80392-9c9c-42ce-a934-da7afb54b886
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1706255596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.1706255596
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3686007010
Short name T598
Test name
Test status
Simulation time 835604542 ps
CPU time 273.05 seconds
Started Dec 27 12:31:58 PM PST 23
Finished Dec 27 12:37:16 PM PST 23
Peak memory 219100 kb
Host smart-bc390d9d-8af3-4b4b-a113-3e748c7de2ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3686007010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.3686007010
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2970624871
Short name T802
Test name
Test status
Simulation time 386844690 ps
CPU time 16.97 seconds
Started Dec 27 12:29:42 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 204356 kb
Host smart-b94f33b1-7983-4bd9-85d9-c59557d85464
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2970624871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2970624871
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2252543323
Short name T165
Test name
Test status
Simulation time 5335274447 ps
CPU time 57.8 seconds
Started Dec 27 12:29:04 PM PST 23
Finished Dec 27 12:30:57 PM PST 23
Peak memory 211224 kb
Host smart-b18c0ffe-4797-4783-ae1c-bf72c5c49a42
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2252543323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2252543323
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3075114945
Short name T137
Test name
Test status
Simulation time 5073211011 ps
CPU time 25.38 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:33:11 PM PST 23
Peak memory 202776 kb
Host smart-4bd67bdd-3ef4-4e5c-8f0b-e23f570706bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3075114945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.3075114945
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1114133915
Short name T222
Test name
Test status
Simulation time 435084673 ps
CPU time 13.73 seconds
Started Dec 27 12:31:55 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 202788 kb
Host smart-61218e11-dadb-40f7-a9b8-fbf5cefb4917
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1114133915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1114133915
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.2259042160
Short name T767
Test name
Test status
Simulation time 703598198 ps
CPU time 19.45 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:33:05 PM PST 23
Peak memory 202664 kb
Host smart-06b51dc3-fc90-4568-bbcb-a474c43174da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2259042160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2259042160
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.3099952991
Short name T609
Test name
Test status
Simulation time 89063879 ps
CPU time 2.22 seconds
Started Dec 27 12:31:58 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 202700 kb
Host smart-e910596c-c691-4574-b75e-0b2bbdd90009
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3099952991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3099952991
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2976741430
Short name T556
Test name
Test status
Simulation time 11388207677 ps
CPU time 41.2 seconds
Started Dec 27 12:30:07 PM PST 23
Finished Dec 27 12:31:41 PM PST 23
Peak memory 204224 kb
Host smart-d437bbda-7639-4a76-9136-3137b0727484
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976741430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2976741430
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3361221550
Short name T534
Test name
Test status
Simulation time 3051428559 ps
CPU time 15.34 seconds
Started Dec 27 12:30:07 PM PST 23
Finished Dec 27 12:31:14 PM PST 23
Peak memory 202932 kb
Host smart-98e6069b-8364-4360-9ac9-33f356da2067
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3361221550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3361221550
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.4173011569
Short name T240
Test name
Test status
Simulation time 116468075 ps
CPU time 8.15 seconds
Started Dec 27 12:32:04 PM PST 23
Finished Dec 27 12:33:01 PM PST 23
Peak memory 210904 kb
Host smart-0c5ee595-e42e-495b-a5da-22dc7c9b3ea7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173011569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.4173011569
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.2378792398
Short name T8
Test name
Test status
Simulation time 149378935 ps
CPU time 6.4 seconds
Started Dec 27 12:29:11 PM PST 23
Finished Dec 27 12:30:12 PM PST 23
Peak memory 203232 kb
Host smart-a9e12065-2bf4-4993-9441-6795c6aef5c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2378792398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2378792398
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.176146939
Short name T531
Test name
Test status
Simulation time 185612062 ps
CPU time 3.27 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:21 PM PST 23
Peak memory 203020 kb
Host smart-054d14b6-62df-4d11-bed0-a64cbf660fdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=176146939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.176146939
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4074558445
Short name T323
Test name
Test status
Simulation time 6453965755 ps
CPU time 30.24 seconds
Started Dec 27 12:31:28 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 202200 kb
Host smart-314cb4b1-f442-43e3-8cd2-7059b6677d0d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074558445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.4074558445
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3684931356
Short name T558
Test name
Test status
Simulation time 5491688726 ps
CPU time 35.33 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:30:24 PM PST 23
Peak memory 203108 kb
Host smart-bdeedb49-5313-409d-ba80-9b202cb02ad6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3684931356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3684931356
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3923128162
Short name T338
Test name
Test status
Simulation time 84589722 ps
CPU time 2.62 seconds
Started Dec 27 12:29:59 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 203008 kb
Host smart-58520913-df79-4628-84ce-27d22bd8d895
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923128162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3923128162
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.2322979353
Short name T873
Test name
Test status
Simulation time 33321361010 ps
CPU time 277.1 seconds
Started Dec 27 12:29:04 PM PST 23
Finished Dec 27 12:34:36 PM PST 23
Peak memory 211056 kb
Host smart-5df31dba-3351-47a1-a3ae-7a8806016f98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2322979353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2322979353
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1593694510
Short name T227
Test name
Test status
Simulation time 6874466708 ps
CPU time 114.72 seconds
Started Dec 27 12:29:27 PM PST 23
Finished Dec 27 12:32:15 PM PST 23
Peak memory 206220 kb
Host smart-9bbf34d6-aec7-4231-b0cb-3a722ec85e70
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1593694510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1593694510
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1810214587
Short name T175
Test name
Test status
Simulation time 773024893 ps
CPU time 148.59 seconds
Started Dec 27 12:29:18 PM PST 23
Finished Dec 27 12:32:42 PM PST 23
Peak memory 211176 kb
Host smart-b3b0a618-d86f-4098-8362-87221caee5d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1810214587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.1810214587
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1764213082
Short name T35
Test name
Test status
Simulation time 764070313 ps
CPU time 92.95 seconds
Started Dec 27 12:30:14 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 208436 kb
Host smart-e088f99f-efc2-4ef3-938a-d09d360987ad
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1764213082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.1764213082
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3783264849
Short name T154
Test name
Test status
Simulation time 605713758 ps
CPU time 12.44 seconds
Started Dec 27 12:29:08 PM PST 23
Finished Dec 27 12:30:15 PM PST 23
Peak memory 204176 kb
Host smart-dfb252f8-7fe4-4c46-a8f0-f94c01080f8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3783264849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3783264849
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1499503406
Short name T207
Test name
Test status
Simulation time 397636911 ps
CPU time 35.18 seconds
Started Dec 27 12:23:42 PM PST 23
Finished Dec 27 12:24:19 PM PST 23
Peak memory 204972 kb
Host smart-743155ed-3910-4142-a331-1726de506e09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1499503406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1499503406
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2895107270
Short name T761
Test name
Test status
Simulation time 29674376972 ps
CPU time 95.14 seconds
Started Dec 27 12:22:21 PM PST 23
Finished Dec 27 12:23:58 PM PST 23
Peak memory 203116 kb
Host smart-95ce824d-78d0-4028-b87d-10bb37b13660
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2895107270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.2895107270
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.266731206
Short name T808
Test name
Test status
Simulation time 752203807 ps
CPU time 18.46 seconds
Started Dec 27 12:26:16 PM PST 23
Finished Dec 27 12:26:47 PM PST 23
Peak memory 202488 kb
Host smart-d06c6f13-524d-413a-8c31-e889bb1c7530
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=266731206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.266731206
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.3145007984
Short name T593
Test name
Test status
Simulation time 1156438375 ps
CPU time 25.01 seconds
Started Dec 27 12:25:09 PM PST 23
Finished Dec 27 12:25:38 PM PST 23
Peak memory 202752 kb
Host smart-900a6e29-638b-4517-85bc-1fed4fb6b602
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3145007984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3145007984
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.2134504462
Short name T73
Test name
Test status
Simulation time 301812661 ps
CPU time 19.73 seconds
Started Dec 27 12:25:58 PM PST 23
Finished Dec 27 12:26:24 PM PST 23
Peak memory 210880 kb
Host smart-ae6766da-63b0-47eb-9187-59524a5ba0ca
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2134504462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2134504462
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2337721400
Short name T95
Test name
Test status
Simulation time 150209168098 ps
CPU time 300.62 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:34:50 PM PST 23
Peak memory 210908 kb
Host smart-2ab9264e-4815-4be1-94d8-74ded0ef6c5e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337721400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2337721400
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1344221713
Short name T875
Test name
Test status
Simulation time 670234267 ps
CPU time 15 seconds
Started Dec 27 12:26:33 PM PST 23
Finished Dec 27 12:27:04 PM PST 23
Peak memory 203784 kb
Host smart-55fa7933-4b59-4bce-a0a8-60ab0d01eec1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344221713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1344221713
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.2918635092
Short name T44
Test name
Test status
Simulation time 2089133608 ps
CPU time 19.84 seconds
Started Dec 27 12:26:33 PM PST 23
Finished Dec 27 12:27:09 PM PST 23
Peak memory 202768 kb
Host smart-f4f7ada3-e173-488d-9741-15c1b37a2f88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2918635092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2918635092
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.1299660708
Short name T229
Test name
Test status
Simulation time 191249355 ps
CPU time 2.62 seconds
Started Dec 27 12:23:19 PM PST 23
Finished Dec 27 12:23:23 PM PST 23
Peak memory 202908 kb
Host smart-5b6ffae0-fc9d-43f0-a248-2890143d0b3e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1299660708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1299660708
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1880841673
Short name T811
Test name
Test status
Simulation time 9466320206 ps
CPU time 36.51 seconds
Started Dec 27 12:20:17 PM PST 23
Finished Dec 27 12:20:54 PM PST 23
Peak memory 202628 kb
Host smart-27887a2f-7e06-4a1f-9a1a-6e181713068d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880841673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1880841673
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.142235343
Short name T460
Test name
Test status
Simulation time 6877353615 ps
CPU time 38.13 seconds
Started Dec 27 12:26:32 PM PST 23
Finished Dec 27 12:27:25 PM PST 23
Peak memory 203016 kb
Host smart-ebe28200-499e-4be6-80a8-347b8cb29f55
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=142235343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.142235343
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2934501150
Short name T437
Test name
Test status
Simulation time 39096402 ps
CPU time 2.08 seconds
Started Dec 27 12:25:07 PM PST 23
Finished Dec 27 12:25:12 PM PST 23
Peak memory 202676 kb
Host smart-bb8ef7c1-76db-40d4-b6ff-117a0a9a98b9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934501150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2934501150
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3037312976
Short name T259
Test name
Test status
Simulation time 10199343236 ps
CPU time 44.41 seconds
Started Dec 27 12:26:16 PM PST 23
Finished Dec 27 12:27:13 PM PST 23
Peak memory 205044 kb
Host smart-0b1c8c5b-bf63-41e3-8658-1c9772f494ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3037312976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3037312976
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.4104345037
Short name T863
Test name
Test status
Simulation time 844795203 ps
CPU time 20.73 seconds
Started Dec 27 12:21:02 PM PST 23
Finished Dec 27 12:21:24 PM PST 23
Peak memory 203008 kb
Host smart-08f5df6a-920a-4d62-b969-7b9351c4acb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4104345037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4104345037
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3928218836
Short name T571
Test name
Test status
Simulation time 1254107306 ps
CPU time 187.85 seconds
Started Dec 27 12:24:59 PM PST 23
Finished Dec 27 12:28:10 PM PST 23
Peak memory 205928 kb
Host smart-ca123480-62a7-40d2-aeeb-c2a12cd2811b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3928218836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand
_reset.3928218836
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1517541666
Short name T197
Test name
Test status
Simulation time 520329367 ps
CPU time 116.22 seconds
Started Dec 27 12:24:41 PM PST 23
Finished Dec 27 12:26:38 PM PST 23
Peak memory 207504 kb
Host smart-e8e47b68-30c5-41a9-bd4b-7ffe99ad692a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1517541666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res
et_error.1517541666
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.917525872
Short name T699
Test name
Test status
Simulation time 77610910 ps
CPU time 9.5 seconds
Started Dec 27 12:25:58 PM PST 23
Finished Dec 27 12:26:14 PM PST 23
Peak memory 203828 kb
Host smart-c3a348c6-27bf-4136-a8c1-8f95b72d8cc4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=917525872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.917525872
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2888388451
Short name T189
Test name
Test status
Simulation time 493078685 ps
CPU time 46.43 seconds
Started Dec 27 12:26:35 PM PST 23
Finished Dec 27 12:27:37 PM PST 23
Peak memory 210828 kb
Host smart-a9e2c31d-419c-427f-8f18-271fe0d46f31
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2888388451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2888388451
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3041876110
Short name T620
Test name
Test status
Simulation time 267875310413 ps
CPU time 584.73 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:40:03 PM PST 23
Peak memory 210868 kb
Host smart-cbce5c5c-eed3-4f35-ab71-afd5c232ba32
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3041876110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.3041876110
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.2182585513
Short name T270
Test name
Test status
Simulation time 14201941 ps
CPU time 1.71 seconds
Started Dec 27 12:26:40 PM PST 23
Finished Dec 27 12:27:02 PM PST 23
Peak memory 202668 kb
Host smart-af8e77e4-f358-4e21-b763-d29ca28563b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2182585513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.2182585513
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.1204093705
Short name T264
Test name
Test status
Simulation time 2602335847 ps
CPU time 25.12 seconds
Started Dec 27 12:29:19 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 202708 kb
Host smart-0a2d1573-70fd-48a7-8902-42c4117d8374
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1204093705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1204093705
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.1340351093
Short name T43
Test name
Test status
Simulation time 738208489 ps
CPU time 22.97 seconds
Started Dec 27 12:26:48 PM PST 23
Finished Dec 27 12:27:32 PM PST 23
Peak memory 203956 kb
Host smart-d015089d-6a45-4f42-b8d4-db5f508036af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1340351093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1340351093
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.3153543032
Short name T555
Test name
Test status
Simulation time 16385599422 ps
CPU time 41.66 seconds
Started Dec 27 12:26:46 PM PST 23
Finished Dec 27 12:27:49 PM PST 23
Peak memory 202816 kb
Host smart-40cc0963-8e04-4a2d-9d0f-63f5f3063ead
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153543032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3153543032
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.275279380
Short name T89
Test name
Test status
Simulation time 29570122152 ps
CPU time 215.95 seconds
Started Dec 27 12:19:58 PM PST 23
Finished Dec 27 12:23:35 PM PST 23
Peak memory 204412 kb
Host smart-b1d129a9-2b1e-4d7c-b4a1-478e0f4b3536
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=275279380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.275279380
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.4119762544
Short name T559
Test name
Test status
Simulation time 72082662 ps
CPU time 5.86 seconds
Started Dec 27 12:26:19 PM PST 23
Finished Dec 27 12:26:39 PM PST 23
Peak memory 210288 kb
Host smart-a30d515f-486b-4360-883d-3b9568572699
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119762544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.4119762544
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.1876942553
Short name T480
Test name
Test status
Simulation time 275653697 ps
CPU time 6.52 seconds
Started Dec 27 12:26:26 PM PST 23
Finished Dec 27 12:26:46 PM PST 23
Peak memory 201752 kb
Host smart-b1c0f44a-00c9-4202-91a7-204bec4f9cb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1876942553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1876942553
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.966594271
Short name T105
Test name
Test status
Simulation time 180869579 ps
CPU time 3.41 seconds
Started Dec 27 12:25:00 PM PST 23
Finished Dec 27 12:25:06 PM PST 23
Peak memory 202864 kb
Host smart-ecef9201-f5c2-49a9-b3d6-64781afabf90
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=966594271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.966594271
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.200644087
Short name T454
Test name
Test status
Simulation time 11535595567 ps
CPU time 31.83 seconds
Started Dec 27 12:27:41 PM PST 23
Finished Dec 27 12:28:44 PM PST 23
Peak memory 202664 kb
Host smart-5096892b-0dd6-4504-ae1f-31cd459aabc4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=200644087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.200644087
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3172407561
Short name T287
Test name
Test status
Simulation time 4089218861 ps
CPU time 29 seconds
Started Dec 27 12:20:26 PM PST 23
Finished Dec 27 12:20:57 PM PST 23
Peak memory 202836 kb
Host smart-f2c96d79-cda5-4eff-acab-861ab046fc0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3172407561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3172407561
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1701046369
Short name T648
Test name
Test status
Simulation time 29055839 ps
CPU time 2.52 seconds
Started Dec 27 12:24:41 PM PST 23
Finished Dec 27 12:24:44 PM PST 23
Peak memory 201800 kb
Host smart-af0d5cd8-90f7-4670-a615-9319e117378a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701046369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1701046369
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.3313116167
Short name T719
Test name
Test status
Simulation time 1818225950 ps
CPU time 42.84 seconds
Started Dec 27 12:28:39 PM PST 23
Finished Dec 27 12:30:13 PM PST 23
Peak memory 205004 kb
Host smart-2b681a43-4b47-4b1f-b3db-e18dc28936c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3313116167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3313116167
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1868999342
Short name T706
Test name
Test status
Simulation time 19175632335 ps
CPU time 111.77 seconds
Started Dec 27 12:25:25 PM PST 23
Finished Dec 27 12:27:26 PM PST 23
Peak memory 206552 kb
Host smart-38a74930-b116-47d1-8fcd-8d9b8dda245e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1868999342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1868999342
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.403977833
Short name T740
Test name
Test status
Simulation time 194916304 ps
CPU time 80.93 seconds
Started Dec 27 12:24:38 PM PST 23
Finished Dec 27 12:26:00 PM PST 23
Peak memory 207112 kb
Host smart-a317ad9a-5523-4377-aba2-26aaf93c875b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=403977833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_
reset.403977833
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.893119353
Short name T839
Test name
Test status
Simulation time 44689218 ps
CPU time 34.4 seconds
Started Dec 27 12:24:37 PM PST 23
Finished Dec 27 12:25:13 PM PST 23
Peak memory 204764 kb
Host smart-606ddbcb-52c6-47e6-8925-38ba4d8f61c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=893119353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rese
t_error.893119353
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.3842610604
Short name T465
Test name
Test status
Simulation time 318002108 ps
CPU time 13.5 seconds
Started Dec 27 12:26:27 PM PST 23
Finished Dec 27 12:26:54 PM PST 23
Peak memory 210736 kb
Host smart-281c3ef0-0ab1-4bbb-b553-d6083261b8b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3842610604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3842610604
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3826675560
Short name T140
Test name
Test status
Simulation time 2371216928 ps
CPU time 14.52 seconds
Started Dec 27 12:26:13 PM PST 23
Finished Dec 27 12:26:40 PM PST 23
Peak memory 203324 kb
Host smart-3e376aa4-fa7e-42b1-a64a-806027f7c0c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3826675560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3826675560
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3872271606
Short name T232
Test name
Test status
Simulation time 609925619 ps
CPU time 16.45 seconds
Started Dec 27 12:24:58 PM PST 23
Finished Dec 27 12:25:16 PM PST 23
Peak memory 202772 kb
Host smart-3f19fab2-3650-4ee6-af7c-713bc86fd929
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3872271606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3872271606
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.719199829
Short name T614
Test name
Test status
Simulation time 1087351029 ps
CPU time 20.07 seconds
Started Dec 27 12:24:58 PM PST 23
Finished Dec 27 12:25:20 PM PST 23
Peak memory 202788 kb
Host smart-9a74abbf-f9a3-4444-844d-0dafdfc96392
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=719199829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.719199829
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.3963942521
Short name T242
Test name
Test status
Simulation time 100881881 ps
CPU time 11.32 seconds
Started Dec 27 12:20:26 PM PST 23
Finished Dec 27 12:20:40 PM PST 23
Peak memory 204036 kb
Host smart-f4c0edf6-db1e-43a7-b766-c6bf5c462199
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3963942521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3963942521
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1199441936
Short name T59
Test name
Test status
Simulation time 14621083764 ps
CPU time 66.53 seconds
Started Dec 27 12:24:38 PM PST 23
Finished Dec 27 12:25:45 PM PST 23
Peak memory 203800 kb
Host smart-75282bbb-0ba1-45c0-97eb-7d97b032f463
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199441936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1199441936
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.1509793996
Short name T176
Test name
Test status
Simulation time 7327946729 ps
CPU time 55.74 seconds
Started Dec 27 12:26:14 PM PST 23
Finished Dec 27 12:27:22 PM PST 23
Peak memory 204204 kb
Host smart-86b36bd6-cd16-4d26-ae46-38c6c240b2f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1509793996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1509793996
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3720082863
Short name T337
Test name
Test status
Simulation time 472123993 ps
CPU time 21.21 seconds
Started Dec 27 12:24:37 PM PST 23
Finished Dec 27 12:25:00 PM PST 23
Peak memory 209752 kb
Host smart-e75bf1bc-89fb-4834-9666-e84a8e3dc81a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720082863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3720082863
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.3816537268
Short name T151
Test name
Test status
Simulation time 674832151 ps
CPU time 6.46 seconds
Started Dec 27 12:24:38 PM PST 23
Finished Dec 27 12:24:46 PM PST 23
Peak memory 202684 kb
Host smart-28d70ff3-43a1-47ca-9328-19975f9787b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3816537268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3816537268
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.2697995727
Short name T10
Test name
Test status
Simulation time 322340488 ps
CPU time 3.57 seconds
Started Dec 27 12:29:10 PM PST 23
Finished Dec 27 12:30:07 PM PST 23
Peak memory 202688 kb
Host smart-9f11cf9d-3147-419e-9a06-0fafbf6b7ef1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2697995727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2697995727
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3746743209
Short name T669
Test name
Test status
Simulation time 12465777115 ps
CPU time 36.3 seconds
Started Dec 27 12:28:22 PM PST 23
Finished Dec 27 12:29:45 PM PST 23
Peak memory 202200 kb
Host smart-c244dbc7-ca4e-4f68-b4a4-d1316a4c1382
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746743209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3746743209
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1649187460
Short name T824
Test name
Test status
Simulation time 3634398974 ps
CPU time 22.74 seconds
Started Dec 27 12:26:32 PM PST 23
Finished Dec 27 12:27:10 PM PST 23
Peak memory 202848 kb
Host smart-c1d3d4a3-7c8b-4c7f-baf9-81e6088fadc0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1649187460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1649187460
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.211310014
Short name T303
Test name
Test status
Simulation time 24305366 ps
CPU time 1.84 seconds
Started Dec 27 12:29:00 PM PST 23
Finished Dec 27 12:29:57 PM PST 23
Peak memory 202632 kb
Host smart-f4f90713-63b2-4bb9-85b0-6adb75411ac0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211310014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.211310014
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2774518004
Short name T697
Test name
Test status
Simulation time 2906959740 ps
CPU time 92.14 seconds
Started Dec 27 12:25:58 PM PST 23
Finished Dec 27 12:27:35 PM PST 23
Peak memory 206232 kb
Host smart-8286ace8-2d98-4d7d-aaf8-1d563173aa7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2774518004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2774518004
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3098727486
Short name T119
Test name
Test status
Simulation time 2454289358 ps
CPU time 55.52 seconds
Started Dec 27 12:29:10 PM PST 23
Finished Dec 27 12:30:59 PM PST 23
Peak memory 205800 kb
Host smart-9c233891-f02b-476d-a91a-849f2370116c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3098727486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3098727486
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2779535318
Short name T34
Test name
Test status
Simulation time 336546023 ps
CPU time 122.69 seconds
Started Dec 27 12:24:58 PM PST 23
Finished Dec 27 12:27:02 PM PST 23
Peak memory 206548 kb
Host smart-2795f107-75d2-4def-9f39-d3d5c3d2db88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2779535318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.2779535318
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1019252662
Short name T834
Test name
Test status
Simulation time 272880983 ps
CPU time 81.06 seconds
Started Dec 27 12:23:23 PM PST 23
Finished Dec 27 12:24:46 PM PST 23
Peak memory 208460 kb
Host smart-e764b674-b203-4365-9115-04b97120a67b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1019252662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.1019252662
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.3302259523
Short name T12
Test name
Test status
Simulation time 84593721 ps
CPU time 10.04 seconds
Started Dec 27 12:24:58 PM PST 23
Finished Dec 27 12:25:10 PM PST 23
Peak memory 210960 kb
Host smart-b0d468dd-8c5d-42e2-84eb-0aeb53c60709
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3302259523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3302259523
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1328454733
Short name T483
Test name
Test status
Simulation time 803203510 ps
CPU time 35.2 seconds
Started Dec 27 12:27:29 PM PST 23
Finished Dec 27 12:28:33 PM PST 23
Peak memory 205816 kb
Host smart-16ea8871-cf31-4ff7-b71a-80e675395bab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1328454733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1328454733
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.400303796
Short name T579
Test name
Test status
Simulation time 54359292666 ps
CPU time 360.03 seconds
Started Dec 27 12:27:28 PM PST 23
Finished Dec 27 12:33:56 PM PST 23
Peak memory 206044 kb
Host smart-2faef959-392e-4b63-9706-1c906fc13374
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=400303796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow
_rsp.400303796
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.161689570
Short name T518
Test name
Test status
Simulation time 524167006 ps
CPU time 6.96 seconds
Started Dec 27 12:27:19 PM PST 23
Finished Dec 27 12:27:53 PM PST 23
Peak memory 202948 kb
Host smart-5fce99d2-67fa-4158-bdc7-b99f93b81662
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=161689570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.161689570
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.3903630710
Short name T687
Test name
Test status
Simulation time 888131394 ps
CPU time 15.16 seconds
Started Dec 27 12:27:31 PM PST 23
Finished Dec 27 12:28:15 PM PST 23
Peak memory 202956 kb
Host smart-cd174870-1b0e-4ca5-a413-7e9c4ccdb8dc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3903630710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3903630710
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.518157205
Short name T360
Test name
Test status
Simulation time 600051778 ps
CPU time 22.27 seconds
Started Dec 27 12:27:24 PM PST 23
Finished Dec 27 12:28:14 PM PST 23
Peak memory 211012 kb
Host smart-10c4cb5d-e82b-4d79-8412-ed1eb603993f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=518157205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.518157205
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2838607026
Short name T485
Test name
Test status
Simulation time 164946924797 ps
CPU time 247.23 seconds
Started Dec 27 12:29:21 PM PST 23
Finished Dec 27 12:34:23 PM PST 23
Peak memory 211292 kb
Host smart-0e84f885-87e8-4eda-ac1a-6d255751d36f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838607026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2838607026
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2982445887
Short name T170
Test name
Test status
Simulation time 21972079336 ps
CPU time 171.24 seconds
Started Dec 27 12:27:20 PM PST 23
Finished Dec 27 12:30:39 PM PST 23
Peak memory 211240 kb
Host smart-e56d5d70-6fe3-4a7f-a836-6b71409dbcc1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2982445887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2982445887
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.446375520
Short name T715
Test name
Test status
Simulation time 439453326 ps
CPU time 12.15 seconds
Started Dec 27 12:27:22 PM PST 23
Finished Dec 27 12:28:03 PM PST 23
Peak memory 211200 kb
Host smart-2b9ab5c5-5d72-4633-b78e-b452a947372d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446375520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.446375520
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.2843922461
Short name T317
Test name
Test status
Simulation time 287796363 ps
CPU time 5.89 seconds
Started Dec 27 12:28:16 PM PST 23
Finished Dec 27 12:29:04 PM PST 23
Peak memory 203184 kb
Host smart-05d80964-82f3-49a7-b40d-c12aa2f98612
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2843922461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2843922461
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.800971619
Short name T720
Test name
Test status
Simulation time 197218019 ps
CPU time 3.31 seconds
Started Dec 27 12:24:45 PM PST 23
Finished Dec 27 12:24:49 PM PST 23
Peak memory 202996 kb
Host smart-3e346335-55bc-4318-b78b-5e9332a41d16
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=800971619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.800971619
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2444707100
Short name T63
Test name
Test status
Simulation time 5829486188 ps
CPU time 25.04 seconds
Started Dec 27 12:24:58 PM PST 23
Finished Dec 27 12:25:25 PM PST 23
Peak memory 202848 kb
Host smart-05a34e4c-7049-4922-90ef-517ea17fc01c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444707100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2444707100
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3638031982
Short name T770
Test name
Test status
Simulation time 4486477283 ps
CPU time 22.31 seconds
Started Dec 27 12:27:21 PM PST 23
Finished Dec 27 12:28:11 PM PST 23
Peak memory 203044 kb
Host smart-06e88d59-f692-4b69-bcc9-d5a5222adf36
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3638031982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3638031982
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.526170081
Short name T258
Test name
Test status
Simulation time 63503066 ps
CPU time 2.04 seconds
Started Dec 27 12:24:37 PM PST 23
Finished Dec 27 12:24:41 PM PST 23
Peak memory 202492 kb
Host smart-2bc9c592-9a59-4230-b402-403c2b4de705
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526170081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.526170081
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1505050403
Short name T656
Test name
Test status
Simulation time 665380480 ps
CPU time 55.85 seconds
Started Dec 27 12:28:26 PM PST 23
Finished Dec 27 12:30:08 PM PST 23
Peak memory 205380 kb
Host smart-3e4afc3a-7fac-4fae-a450-ce476b8d279a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1505050403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1505050403
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2769311351
Short name T673
Test name
Test status
Simulation time 3094701687 ps
CPU time 117.68 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:31:46 PM PST 23
Peak memory 211100 kb
Host smart-ea60519f-4e57-44f7-a2c1-6d21ed1eb4b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2769311351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2769311351
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2500374124
Short name T335
Test name
Test status
Simulation time 6176721918 ps
CPU time 258.7 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:34:08 PM PST 23
Peak memory 219280 kb
Host smart-13d92bb4-604a-4efa-98ab-c83553012cdc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2500374124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand
_reset.2500374124
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.528982187
Short name T441
Test name
Test status
Simulation time 8458888060 ps
CPU time 90.83 seconds
Started Dec 27 12:28:49 PM PST 23
Finished Dec 27 12:31:13 PM PST 23
Peak memory 206964 kb
Host smart-9a60d631-c66f-46c4-990f-821ef073ff69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=528982187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rese
t_error.528982187
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.2001956142
Short name T210
Test name
Test status
Simulation time 335926981 ps
CPU time 5.23 seconds
Started Dec 27 12:27:21 PM PST 23
Finished Dec 27 12:27:54 PM PST 23
Peak memory 210968 kb
Host smart-82be5540-02a3-42fb-b629-28ba17e04fc5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2001956142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2001956142
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3002846498
Short name T840
Test name
Test status
Simulation time 1053320890 ps
CPU time 25.27 seconds
Started Dec 27 12:27:21 PM PST 23
Finished Dec 27 12:28:14 PM PST 23
Peak memory 211184 kb
Host smart-65b051b8-1acc-4486-82e6-0e79c1614c4e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3002846498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3002846498
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.4085226258
Short name T444
Test name
Test status
Simulation time 28890949188 ps
CPU time 236 seconds
Started Dec 27 12:27:23 PM PST 23
Finished Dec 27 12:31:47 PM PST 23
Peak memory 205820 kb
Host smart-b1814ffc-e29e-4936-b3b4-cb6483924aa4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4085226258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo
w_rsp.4085226258
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.540615300
Short name T371
Test name
Test status
Simulation time 26894130 ps
CPU time 3.76 seconds
Started Dec 27 12:27:26 PM PST 23
Finished Dec 27 12:27:59 PM PST 23
Peak memory 203036 kb
Host smart-d4c7fa53-93a6-4fa1-9e3d-ef238ce6e8cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=540615300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.540615300
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.1067295466
Short name T543
Test name
Test status
Simulation time 538956481 ps
CPU time 10.48 seconds
Started Dec 27 12:28:46 PM PST 23
Finished Dec 27 12:29:49 PM PST 23
Peak memory 202904 kb
Host smart-1cbda220-6c94-4d89-aa14-f0c07118d7da
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1067295466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1067295466
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.2713007752
Short name T632
Test name
Test status
Simulation time 674151743 ps
CPU time 14.74 seconds
Started Dec 27 12:27:18 PM PST 23
Finished Dec 27 12:28:01 PM PST 23
Peak memory 203864 kb
Host smart-68dd998a-87ea-412e-95cf-43f48ab6ed45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2713007752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2713007752
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1091718144
Short name T383
Test name
Test status
Simulation time 40151619693 ps
CPU time 205.41 seconds
Started Dec 27 12:28:37 PM PST 23
Finished Dec 27 12:32:59 PM PST 23
Peak memory 204632 kb
Host smart-39a9fd29-1397-4cc9-a3dc-aaddd7fda5bf
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091718144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1091718144
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.65853655
Short name T1
Test name
Test status
Simulation time 120790854 ps
CPU time 13.15 seconds
Started Dec 27 12:27:26 PM PST 23
Finished Dec 27 12:28:07 PM PST 23
Peak memory 210992 kb
Host smart-e03b38c5-ac8f-416a-b098-910d795e7594
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65853655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.65853655
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.3667978823
Short name T180
Test name
Test status
Simulation time 498087363 ps
CPU time 10.29 seconds
Started Dec 27 12:27:31 PM PST 23
Finished Dec 27 12:28:10 PM PST 23
Peak memory 203028 kb
Host smart-25f35150-e675-4041-bb65-488a0e91dc2d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3667978823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3667978823
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.2756073217
Short name T806
Test name
Test status
Simulation time 127816632 ps
CPU time 2.66 seconds
Started Dec 27 12:27:24 PM PST 23
Finished Dec 27 12:27:55 PM PST 23
Peak memory 202836 kb
Host smart-f81a1b72-5487-4021-955f-d92c1115f3de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2756073217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2756073217
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.929994187
Short name T305
Test name
Test status
Simulation time 3860859518 ps
CPU time 23.84 seconds
Started Dec 27 12:27:42 PM PST 23
Finished Dec 27 12:28:36 PM PST 23
Peak memory 202904 kb
Host smart-e0eed2ef-8161-4802-a457-5e8491b611a1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=929994187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.929994187
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1233002496
Short name T345
Test name
Test status
Simulation time 4011386907 ps
CPU time 20.2 seconds
Started Dec 27 12:27:17 PM PST 23
Finished Dec 27 12:28:05 PM PST 23
Peak memory 202908 kb
Host smart-b08b6c7d-c825-4d13-ae8a-662b6d877d32
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1233002496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1233002496
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2264971603
Short name T680
Test name
Test status
Simulation time 29909921 ps
CPU time 2.07 seconds
Started Dec 27 12:28:42 PM PST 23
Finished Dec 27 12:29:36 PM PST 23
Peak memory 202996 kb
Host smart-b4cdb78a-3ea2-4f4b-9a4e-d8e7854f6380
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264971603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2264971603
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2803275901
Short name T85
Test name
Test status
Simulation time 6423631529 ps
CPU time 131.49 seconds
Started Dec 27 12:27:17 PM PST 23
Finished Dec 27 12:29:56 PM PST 23
Peak memory 211276 kb
Host smart-ccb27b18-ad0e-480c-85eb-39717097c47d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2803275901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2803275901
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.589935550
Short name T428
Test name
Test status
Simulation time 1636147626 ps
CPU time 89.49 seconds
Started Dec 27 12:27:19 PM PST 23
Finished Dec 27 12:29:15 PM PST 23
Peak memory 204444 kb
Host smart-0c61d1bc-e9b0-4e27-ae36-74877a5f3be9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=589935550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.589935550
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3453252178
Short name T28
Test name
Test status
Simulation time 161321452 ps
CPU time 45.08 seconds
Started Dec 27 12:27:22 PM PST 23
Finished Dec 27 12:28:36 PM PST 23
Peak memory 206344 kb
Host smart-758c2522-e7e6-4e4c-abc5-466ff7e5b10e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3453252178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.3453252178
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.150387567
Short name T102
Test name
Test status
Simulation time 8765440671 ps
CPU time 316.95 seconds
Started Dec 27 12:27:50 PM PST 23
Finished Dec 27 12:33:38 PM PST 23
Peak memory 219472 kb
Host smart-cc533b6a-c6dd-4177-b553-9e01a009574c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=150387567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese
t_error.150387567
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.4023929492
Short name T219
Test name
Test status
Simulation time 251310896 ps
CPU time 16.74 seconds
Started Dec 27 12:27:20 PM PST 23
Finished Dec 27 12:28:05 PM PST 23
Peak memory 211072 kb
Host smart-3728378f-a10f-40e1-a965-7e7997da2d6e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4023929492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4023929492
Directory /workspace/9.xbar_unmapped_addr/latest
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