Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1830	1			T16	30		T19	4		T39	8
all_values[1]	1865	1			T1	2		T16	42		T19	5
all_values[2]	1844	1			T1	1		T16	34		T19	2
all_values[3]	1835	1			T16	47		T39	5		T26	7
all_values[4]	1746	1			T1	2		T16	36		T19	5
all_values[5]	1875	1			T16	41		T19	3		T39	11
all_values[6]	1827	1			T1	1		T16	21		T19	6
all_values[7]	1887	1			T16	20		T19	9		T39	4
all_values[8]	1774	1			T16	25		T19	4		T39	6
all_values[9]	1846	1			T1	1		T16	31		T19	7
all_values[10]	1799	1			T1	1		T16	39		T19	3
all_values[11]	1889	1			T16	30		T19	6		T39	8
all_values[12]	1872	1			T16	25		T19	8		T39	6
all_values[13]	1901	1			T1	2		T16	36		T19	10
all_values[14]	1914	1			T1	2		T16	29		T19	6
all_values[15]	1815	1			T16	30		T19	7		T39	5
all_values[16]	1845	1			T16	34		T19	7		T39	7
all_values[17]	1792	1			T16	33		T19	3		T39	10
all_values[18]	1860	1			T16	29		T19	4		T39	4
all_values[19]	1853	1			T1	1		T16	47		T19	6
all_values[20]	1861	1			T16	32		T19	11		T39	6
all_values[21]	1859	1			T16	34		T19	2		T39	5
all_values[22]	1841	1			T16	38		T19	2		T39	8
all_values[23]	1817	1			T16	31		T19	4		T39	10
all_values[24]	1794	1			T16	37		T39	4		T26	7
all_values[25]	1756	1			T16	24		T19	2		T39	10
all_values[26]	1851	1			T16	35		T19	6		T39	4
all_values[27]	1886	1			T16	31		T19	2		T39	11
all_values[28]	1834	1			T16	30		T19	9		T39	5
all_values[29]	1907	1			T16	46		T19	1		T39	7
all_values[30]	1851	1			T1	1		T16	27		T19	6
all_values[31]	1819	1			T16	31		T19	6		T39	6
all_values[32]	1885	1			T1	1		T16	29		T19	3
all_values[33]	1866	1			T16	30		T19	1		T39	7
all_values[34]	1955	1			T1	2		T16	43		T19	5
all_values[35]	1849	1			T16	34		T19	8		T39	2
all_values[36]	1854	1			T16	36		T19	12		T39	4
all_values[37]	1870	1			T16	31		T19	7		T39	4
all_values[38]	1785	1			T1	1		T16	28		T19	4
all_values[39]	1823	1			T1	1		T16	22		T19	7
all_values[40]	1866	1			T16	25		T19	2		T39	5
all_values[41]	1871	1			T16	23		T19	6		T39	6
all_values[42]	1825	1			T1	2		T16	31		T19	6
all_values[43]	1855	1			T16	41		T19	6		T39	7
all_values[44]	1847	1			T16	26		T19	6		T39	7
all_values[45]	1778	1			T16	29		T19	8		T39	3
all_values[46]	1810	1			T16	24		T19	5		T39	11
all_values[47]	1808	1			T16	25		T19	9		T39	9
all_values[48]	1956	1			T16	36		T19	8		T39	7
all_values[49]	1885	1			T16	29		T19	3		T39	3
all_values[50]	1998	1			T1	1		T16	42		T19	7
all_values[51]	1870	1			T1	2		T16	31		T19	5
all_values[52]	1912	1			T16	34		T19	7		T39	11
all_values[53]	1884	1			T16	38		T19	3		T39	4
all_values[54]	1871	1			T16	42		T19	4		T39	7
all_values[55]	1916	1			T1	1		T16	38		T19	7
all_values[56]	1876	1			T16	35		T19	7		T39	5
all_values[57]	1842	1			T1	1		T16	30		T19	3
all_values[58]	1870	1			T16	31		T19	5		T39	7
all_values[59]	1810	1			T16	30		T19	2		T39	9
all_values[60]	1812	1			T16	27		T19	7		T39	7
all_values[61]	1880	1			T16	25		T19	8		T39	9
all_values[62]	1887	1			T1	1		T16	37		T19	8
all_values[63]	1877	1			T1	1		T16	24		T19	4