Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1793	1			T6	8		T8	2		T9	9
all_values[1]	1721	1			T6	9		T8	2		T9	11
all_values[2]	1834	1			T6	8		T8	1		T9	6
all_values[3]	1767	1			T6	9		T8	5		T9	8
all_values[4]	1743	1			T6	8		T8	2		T9	9
all_values[5]	1773	1			T6	5		T9	11		T63	10
all_values[6]	1793	1			T6	9		T9	12		T63	21
all_values[7]	1804	1			T6	6		T8	3		T9	7
all_values[8]	1750	1			T6	7		T8	1		T9	6
all_values[9]	1778	1			T6	8		T8	3		T9	12
all_values[10]	1721	1			T6	7		T8	3		T9	13
all_values[11]	1741	1			T6	8		T8	3		T9	4
all_values[12]	1756	1			T6	9		T8	1		T9	8
all_values[13]	1805	1			T6	12		T8	2		T9	1
all_values[14]	1772	1			T6	6		T8	2		T9	8
all_values[15]	1783	1			T6	3		T8	3		T9	6
all_values[16]	1747	1			T6	12		T8	1		T9	10
all_values[17]	1768	1			T6	8		T8	3		T9	14
all_values[18]	1712	1			T6	12		T8	1		T9	8
all_values[19]	1783	1			T6	3		T8	1		T9	6
all_values[20]	1712	1			T6	8		T8	1		T9	6
all_values[21]	1777	1			T6	9		T8	1		T9	7
all_values[22]	1775	1			T6	10		T8	3		T9	10
all_values[23]	1774	1			T6	2		T8	1		T9	3
all_values[24]	1728	1			T6	7		T8	1		T9	7
all_values[25]	1770	1			T6	6		T8	3		T9	6
all_values[26]	1757	1			T6	8		T8	2		T9	5
all_values[27]	1785	1			T6	12		T8	3		T9	7
all_values[28]	1792	1			T6	8		T8	6		T9	9
all_values[29]	1847	1			T6	6		T9	5		T63	22
all_values[30]	1788	1			T6	7		T8	1		T9	6
all_values[31]	1693	1			T6	7		T8	2		T9	9
all_values[32]	1759	1			T6	5		T8	1		T9	5
all_values[33]	1734	1			T6	7		T8	1		T9	5
all_values[34]	1758	1			T6	6		T8	2		T9	7
all_values[35]	1755	1			T6	5		T8	1		T9	4
all_values[36]	1808	1			T6	7		T8	2		T9	4
all_values[37]	1805	1			T6	8		T8	4		T9	5
all_values[38]	1795	1			T6	13		T8	2		T9	7
all_values[39]	1763	1			T6	6		T9	7		T63	16
all_values[40]	1726	1			T6	3		T8	3		T9	4
all_values[41]	1789	1			T6	10		T8	1		T9	10
all_values[42]	1732	1			T6	13		T8	1		T9	8
all_values[43]	1747	1			T6	10		T8	3		T9	4
all_values[44]	1762	1			T6	10		T9	4		T63	19
all_values[45]	1774	1			T6	6		T8	2		T9	11
all_values[46]	1773	1			T6	7		T9	5		T63	17
all_values[47]	1781	1			T6	4		T8	1		T9	5
all_values[48]	1726	1			T6	9		T9	7		T63	21
all_values[49]	1842	1			T6	3		T8	1		T9	12
all_values[50]	1725	1			T6	2		T8	2		T9	5
all_values[51]	1807	1			T6	5		T8	1		T9	10
all_values[52]	1861	1			T6	5		T8	1		T9	8
all_values[53]	1738	1			T6	9		T8	1		T9	11
all_values[54]	1773	1			T6	9		T8	3		T9	10
all_values[55]	1746	1			T6	4		T8	1		T9	4
all_values[56]	1837	1			T6	5		T8	4		T9	8
all_values[57]	1708	1			T6	4		T8	4		T9	5
all_values[58]	1761	1			T6	8		T8	2		T9	10
all_values[59]	1825	1			T6	3		T8	3		T9	4
all_values[60]	1758	1			T6	9		T8	1		T9	7
all_values[61]	1781	1			T6	9		T9	7		T63	25
all_values[62]	1737	1			T6	8		T8	3		T9	5
all_values[63]	1802	1			T6	8		T8	1		T9	11