Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 463 1 T9 3 T12 4 T13 5
all_values[1] 487 1 T9 4 T12 3 T13 5
all_values[2] 434 1 T9 2 T12 1 T13 7
all_values[3] 469 1 T9 5 T12 4 T13 11
all_values[4] 469 1 T9 5 T12 4 T13 4
all_values[5] 483 1 T9 2 T12 3 T13 5
all_values[6] 506 1 T9 3 T12 6 T13 4
all_values[7] 451 1 T9 1 T12 5 T13 1
all_values[8] 468 1 T9 2 T12 7 T13 5
all_values[9] 465 1 T2 1 T9 5 T12 1
all_values[10] 433 1 T9 3 T12 2 T13 8
all_values[11] 458 1 T9 3 T12 3 T13 7
all_values[12] 435 1 T9 3 T12 2 T13 8
all_values[13] 451 1 T12 2 T13 8 T14 2
all_values[14] 448 1 T9 4 T12 5 T13 2
all_values[15] 486 1 T9 2 T12 2 T13 6
all_values[16] 433 1 T9 4 T12 1 T13 6
all_values[17] 445 1 T9 1 T12 3 T13 9
all_values[18] 450 1 T9 2 T12 3 T13 1
all_values[19] 437 1 T9 1 T12 4 T13 9
all_values[20] 440 1 T2 1 T12 4 T13 8
all_values[21] 477 1 T9 2 T12 9 T13 12
all_values[22] 462 1 T9 2 T12 2 T13 12
all_values[23] 466 1 T9 2 T12 4 T13 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%