Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1677	1			T9	9		T12	7		T13	11
all_values[1]	1760	1			T9	4		T12	11		T13	11
all_values[2]	1696	1			T9	7		T12	6		T13	12
all_values[3]	1733	1			T9	9		T12	8		T13	13
all_values[4]	1667	1			T9	10		T12	10		T13	15
all_values[5]	1658	1			T9	8		T12	3		T13	9
all_values[6]	1722	1			T9	3		T12	10		T13	11
all_values[7]	1623	1			T9	9		T12	9		T13	9
all_values[8]	1752	1			T9	11		T12	16		T13	13
all_values[9]	1657	1			T9	4		T12	4		T13	10
all_values[10]	1616	1			T9	3		T12	9		T13	8
all_values[11]	1694	1			T9	4		T12	5		T13	12
all_values[12]	1705	1			T9	7		T12	11		T13	15
all_values[13]	1676	1			T9	7		T12	6		T13	8
all_values[14]	1655	1			T9	7		T12	7		T13	13
all_values[15]	1708	1			T9	8		T12	6		T13	8
all_values[16]	1715	1			T9	7		T12	8		T13	8
all_values[17]	1734	1			T9	11		T12	9		T13	8
all_values[18]	1666	1			T9	5		T12	10		T13	17
all_values[19]	1715	1			T9	10		T12	7		T13	12
all_values[20]	1683	1			T9	8		T12	10		T13	17
all_values[21]	1708	1			T9	4		T12	8		T13	9
all_values[22]	1603	1			T9	6		T12	9		T13	7
all_values[23]	1619	1			T9	11		T12	4		T13	16
all_values[24]	1718	1			T9	3		T12	5		T13	9
all_values[25]	1648	1			T9	20		T12	12		T13	19
all_values[26]	1667	1			T9	5		T12	6		T13	10
all_values[27]	1632	1			T9	8		T12	8		T13	11
all_values[28]	1664	1			T9	8		T12	7		T13	11
all_values[29]	1709	1			T9	10		T12	8		T13	8
all_values[30]	1680	1			T9	11		T12	2		T13	12
all_values[31]	1636	1			T9	12		T12	8		T13	9
all_values[32]	1687	1			T9	7		T12	14		T13	15
all_values[33]	1599	1			T9	7		T12	8		T13	14
all_values[34]	1656	1			T9	8		T12	7		T13	10
all_values[35]	1708	1			T9	5		T12	5		T13	14
all_values[36]	1745	1			T9	4		T12	11		T13	12
all_values[37]	1675	1			T9	8		T12	9		T13	6
all_values[38]	1694	1			T9	9		T12	12		T13	12
all_values[39]	1704	1			T9	6		T12	4		T13	6
all_values[40]	1722	1			T9	11		T12	5		T13	13
all_values[41]	1773	1			T9	10		T12	3		T13	11
all_values[42]	1685	1			T9	9		T12	6		T13	13
all_values[43]	1695	1			T9	11		T12	8		T13	15
all_values[44]	1684	1			T9	11		T12	6		T13	13
all_values[45]	1575	1			T9	3		T12	6		T13	10
all_values[46]	1748	1			T9	3		T12	6		T13	12
all_values[47]	1744	1			T9	9		T12	4		T13	10
all_values[48]	1653	1			T9	12		T12	6		T13	9
all_values[49]	1660	1			T9	11		T12	4		T13	21
all_values[50]	1647	1			T9	12		T12	7		T13	13
all_values[51]	1663	1			T9	11		T12	10		T13	11
all_values[52]	1591	1			T9	3		T12	5		T13	10
all_values[53]	1664	1			T9	9		T12	4		T13	8
all_values[54]	1640	1			T9	11		T12	10		T13	16
all_values[55]	1671	1			T9	9		T12	10		T13	9
all_values[56]	1695	1			T9	7		T12	9		T13	10
all_values[57]	1690	1			T9	14		T12	7		T13	15
all_values[58]	1674	1			T9	8		T12	6		T13	17
all_values[59]	1680	1			T9	6		T12	3		T13	6
all_values[60]	1703	1			T9	12		T12	5		T13	17
all_values[61]	1678	1			T9	3		T12	6		T13	11
all_values[62]	1687	1			T9	5		T12	8		T13	11
all_values[63]	1669	1			T9	9		T12	3		T13	12