Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1909	1			T3	2		T5	17		T6	5
all_values[1]	1849	1			T3	3		T5	19		T6	6
all_values[2]	1887	1			T3	4		T5	20		T6	3
all_values[3]	1763	1			T3	7		T5	28		T6	3
all_values[4]	1822	1			T3	1		T5	33		T6	2
all_values[5]	1810	1			T3	1		T5	25		T6	5
all_values[6]	1841	1			T3	4		T5	25		T6	1
all_values[7]	1842	1			T3	2		T5	32		T6	3
all_values[8]	1790	1			T3	5		T5	24		T6	2
all_values[9]	1714	1			T3	1		T5	22		T6	3
all_values[10]	1782	1			T3	6		T5	18		T6	3
all_values[11]	1774	1			T3	1		T5	22		T6	3
all_values[12]	1802	1			T3	3		T5	19		T6	4
all_values[13]	1694	1			T3	3		T5	17		T6	2
all_values[14]	1908	1			T3	2		T5	27		T6	6
all_values[15]	1902	1			T3	4		T5	21		T6	1
all_values[16]	1753	1			T3	3		T5	17		T6	2
all_values[17]	1718	1			T3	7		T5	17		T6	2
all_values[18]	1767	1			T3	5		T5	21		T6	1
all_values[19]	1837	1			T3	5		T5	18		T6	1
all_values[20]	1816	1			T3	2		T5	19		T6	1
all_values[21]	1785	1			T3	1		T5	30		T6	1
all_values[22]	1775	1			T3	4		T5	16		T11	28
all_values[23]	1777	1			T3	3		T5	19		T6	2
all_values[24]	1804	1			T3	2		T5	23		T6	3
all_values[25]	1849	1			T3	2		T5	23		T6	4
all_values[26]	1817	1			T3	4		T5	9		T6	2
all_values[27]	1815	1			T3	3		T5	24		T6	3
all_values[28]	1856	1			T3	1		T5	20		T6	5
all_values[29]	1798	1			T3	4		T5	22		T6	2
all_values[30]	1876	1			T3	2		T5	23		T6	1
all_values[31]	1867	1			T5	25		T6	5		T9	2
all_values[32]	1840	1			T3	1		T5	17		T6	2
all_values[33]	1743	1			T3	2		T5	18		T6	4
all_values[34]	1870	1			T3	3		T5	24		T6	5
all_values[35]	1784	1			T3	4		T5	26		T6	3
all_values[36]	1812	1			T3	3		T5	21		T9	3
all_values[37]	1845	1			T3	5		T5	21		T6	1
all_values[38]	1823	1			T3	2		T5	20		T6	2
all_values[39]	1838	1			T3	3		T5	24		T6	3
all_values[40]	1832	1			T5	15		T6	4		T9	4
all_values[41]	1829	1			T3	4		T5	26		T6	6
all_values[42]	1741	1			T5	20		T6	1		T9	4
all_values[43]	1844	1			T3	4		T5	26		T6	2
all_values[44]	1726	1			T3	5		T5	25		T6	1
all_values[45]	1774	1			T3	3		T5	26		T6	2
all_values[46]	1804	1			T3	4		T5	27		T6	7
all_values[47]	1799	1			T3	1		T5	19		T6	2
all_values[48]	1864	1			T3	3		T5	26		T6	4
all_values[49]	1815	1			T3	4		T5	30		T6	3
all_values[50]	1824	1			T3	2		T5	24		T6	5
all_values[51]	1846	1			T3	2		T5	32		T6	8
all_values[52]	1943	1			T3	4		T5	29		T6	3
all_values[53]	1835	1			T3	4		T5	26		T6	3
all_values[54]	1881	1			T3	2		T5	18		T6	4
all_values[55]	1854	1			T3	4		T5	23		T6	5
all_values[56]	1872	1			T3	1		T5	19		T6	3
all_values[57]	1799	1			T3	4		T5	25		T6	4
all_values[58]	1757	1			T3	1		T5	23		T6	1
all_values[59]	1784	1			T3	3		T5	21		T6	7
all_values[60]	1751	1			T3	4		T5	20		T6	3
all_values[61]	1884	1			T3	2		T5	26		T6	3
all_values[62]	1835	1			T3	6		T5	21		T6	4
all_values[63]	1800	1			T3	2		T5	35		T6	2