| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.20 | 99.26 | 90.07 | 98.80 | 95.82 | 99.26 | 100.00 |
| T767 | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2696659266 | Jan 14 12:33:50 PM PST 24 | Jan 14 12:35:58 PM PST 24 | 35975360502 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.443300465 | Jan 14 12:33:38 PM PST 24 | Jan 14 12:34:14 PM PST 24 | 23983696808 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3836749825 | Jan 14 12:32:57 PM PST 24 | Jan 14 12:33:27 PM PST 24 | 3517152141 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1987883402 | Jan 14 12:33:29 PM PST 24 | Jan 14 12:38:12 PM PST 24 | 1957627681 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.265553219 | Jan 14 12:33:09 PM PST 24 | Jan 14 12:33:39 PM PST 24 | 7938291058 ps | ||
| T122 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.400991295 | Jan 14 12:34:50 PM PST 24 | Jan 14 12:39:39 PM PST 24 | 2052934308 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2516692455 | Jan 14 12:32:49 PM PST 24 | Jan 14 12:34:17 PM PST 24 | 2395484134 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2676883026 | Jan 14 12:33:16 PM PST 24 | Jan 14 12:34:54 PM PST 24 | 1441079857 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/42.xbar_error_random.942016795 | Jan 14 12:34:27 PM PST 24 | Jan 14 12:34:39 PM PST 24 | 153516112 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1494340655 | Jan 14 12:34:06 PM PST 24 | Jan 14 12:34:41 PM PST 24 | 4229346900 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2695518658 | Jan 14 12:34:45 PM PST 24 | Jan 14 12:36:06 PM PST 24 | 1394906252 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/7.xbar_random.278246497 | Jan 14 12:32:45 PM PST 24 | Jan 14 12:32:52 PM PST 24 | 63707476 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/16.xbar_random.2623578842 | Jan 14 12:33:08 PM PST 24 | Jan 14 12:33:21 PM PST 24 | 1200633917 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/48.xbar_smoke.18864039 | Jan 14 12:34:44 PM PST 24 | Jan 14 12:34:50 PM PST 24 | 154718223 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/7.xbar_smoke.1617410928 | Jan 14 12:32:48 PM PST 24 | Jan 14 12:32:55 PM PST 24 | 467398751 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/46.xbar_smoke.3200562305 | Jan 14 12:34:43 PM PST 24 | Jan 14 12:34:51 PM PST 24 | 451696323 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1132770615 | Jan 14 12:34:22 PM PST 24 | Jan 14 12:45:47 PM PST 24 | 5284666124 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3918773458 | Jan 14 12:32:28 PM PST 24 | Jan 14 12:32:31 PM PST 24 | 29348441 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2765368414 | Jan 14 12:32:59 PM PST 24 | Jan 14 12:33:31 PM PST 24 | 10802394928 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/35.xbar_error_random.957410310 | Jan 14 12:34:13 PM PST 24 | Jan 14 12:34:41 PM PST 24 | 833424790 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2330826898 | Jan 14 12:34:47 PM PST 24 | Jan 14 12:35:02 PM PST 24 | 521475118 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2234631775 | Jan 14 12:34:16 PM PST 24 | Jan 14 12:47:04 PM PST 24 | 208618267231 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.372783207 | Jan 14 12:33:13 PM PST 24 | Jan 14 12:35:11 PM PST 24 | 27696453010 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2108243849 | Jan 14 12:32:32 PM PST 24 | Jan 14 12:33:28 PM PST 24 | 15479900680 ps | ||
| T221 | /workspace/coverage/xbar_build_mode/27.xbar_random.3620652086 | Jan 14 12:33:33 PM PST 24 | Jan 14 12:34:11 PM PST 24 | 1042704490 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3607380347 | Jan 14 12:33:08 PM PST 24 | Jan 14 12:34:23 PM PST 24 | 1211273604 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/18.xbar_error_random.3622277095 | Jan 14 12:33:13 PM PST 24 | Jan 14 12:33:21 PM PST 24 | 59461828 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.327500044 | Jan 14 12:34:43 PM PST 24 | Jan 14 12:40:10 PM PST 24 | 89981769829 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1154690175 | Jan 14 12:32:38 PM PST 24 | Jan 14 12:36:00 PM PST 24 | 21810288768 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/43.xbar_same_source.1089482955 | Jan 14 12:34:27 PM PST 24 | Jan 14 12:34:55 PM PST 24 | 1491847346 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1569486616 | Jan 14 12:33:16 PM PST 24 | Jan 14 12:38:59 PM PST 24 | 15005594175 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2665236373 | Jan 14 12:33:11 PM PST 24 | Jan 14 12:33:24 PM PST 24 | 102794931 ps | ||
| T123 | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1529088005 | Jan 14 12:33:05 PM PST 24 | Jan 14 12:38:31 PM PST 24 | 12565314381 ps | ||
| T39 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.357061134 | Jan 14 12:34:45 PM PST 24 | Jan 14 12:36:00 PM PST 24 | 366866461 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3801386409 | Jan 14 12:32:31 PM PST 24 | Jan 14 12:33:35 PM PST 24 | 14234900680 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1444565652 | Jan 14 12:33:03 PM PST 24 | Jan 14 12:33:06 PM PST 24 | 152472259 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2611159780 | Jan 14 12:32:33 PM PST 24 | Jan 14 12:32:46 PM PST 24 | 131000688 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2899321997 | Jan 14 12:33:03 PM PST 24 | Jan 14 12:33:12 PM PST 24 | 562844101 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2892481910 | Jan 14 12:33:06 PM PST 24 | Jan 14 12:33:13 PM PST 24 | 252020454 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.3809906754 | Jan 14 12:32:48 PM PST 24 | Jan 14 12:35:52 PM PST 24 | 39096488418 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1598512876 | Jan 14 12:34:07 PM PST 24 | Jan 14 12:34:19 PM PST 24 | 111977277 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/6.xbar_same_source.670936892 | Jan 14 12:32:52 PM PST 24 | Jan 14 12:33:27 PM PST 24 | 2516366184 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/42.xbar_same_source.2462367225 | Jan 14 12:34:23 PM PST 24 | Jan 14 12:34:43 PM PST 24 | 1206608742 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/1.xbar_smoke.1766376416 | Jan 14 12:32:23 PM PST 24 | Jan 14 12:32:28 PM PST 24 | 288237800 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.4253180447 | Jan 14 12:34:38 PM PST 24 | Jan 14 12:37:42 PM PST 24 | 32028481859 ps | ||
| T202 | /workspace/coverage/xbar_build_mode/2.xbar_random.3353658540 | Jan 14 12:32:22 PM PST 24 | Jan 14 12:32:34 PM PST 24 | 258801857 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.531711253 | Jan 14 12:33:05 PM PST 24 | Jan 14 12:33:37 PM PST 24 | 3700752558 ps | ||
| T229 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1937269188 | Jan 14 12:34:23 PM PST 24 | Jan 14 12:38:28 PM PST 24 | 19342096841 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3412000821 | Jan 14 12:33:18 PM PST 24 | Jan 14 12:33:30 PM PST 24 | 119263649 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/9.xbar_smoke.158605358 | Jan 14 12:32:55 PM PST 24 | Jan 14 12:32:58 PM PST 24 | 45432384 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.182714181 | Jan 14 12:33:11 PM PST 24 | Jan 14 12:33:42 PM PST 24 | 22718476 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3187007569 | Jan 14 12:34:34 PM PST 24 | Jan 14 12:35:09 PM PST 24 | 5457043749 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3417797316 | Jan 14 12:33:08 PM PST 24 | Jan 14 12:41:15 PM PST 24 | 122959072951 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2465105352 | Jan 14 12:32:19 PM PST 24 | Jan 14 12:32:46 PM PST 24 | 2748155375 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1453623211 | Jan 14 12:34:09 PM PST 24 | Jan 14 12:34:38 PM PST 24 | 8714321304 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2957070192 | Jan 14 12:32:44 PM PST 24 | Jan 14 12:33:17 PM PST 24 | 3789219623 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/34.xbar_smoke.915058524 | Jan 14 12:34:00 PM PST 24 | Jan 14 12:34:04 PM PST 24 | 196565376 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.393198941 | Jan 14 12:34:33 PM PST 24 | Jan 14 12:36:12 PM PST 24 | 19250334987 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3331825177 | Jan 14 12:34:11 PM PST 24 | Jan 14 12:34:50 PM PST 24 | 2722007417 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3576175798 | Jan 14 12:33:51 PM PST 24 | Jan 14 12:36:02 PM PST 24 | 295055385 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3731965091 | Jan 14 12:33:27 PM PST 24 | Jan 14 12:34:19 PM PST 24 | 14282213735 ps | ||
| T131 | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1547092921 | Jan 14 12:33:11 PM PST 24 | Jan 14 12:44:13 PM PST 24 | 368091247509 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/5.xbar_smoke.676795510 | Jan 14 12:32:34 PM PST 24 | Jan 14 12:32:37 PM PST 24 | 66079593 ps | ||
| T32 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.325976578 | Jan 14 12:32:47 PM PST 24 | Jan 14 12:39:25 PM PST 24 | 5530766234 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3822474264 | Jan 14 12:32:28 PM PST 24 | Jan 14 12:36:28 PM PST 24 | 52927761378 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.4093430136 | Jan 14 12:33:46 PM PST 24 | Jan 14 12:35:45 PM PST 24 | 6382211443 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2520363637 | Jan 14 12:34:48 PM PST 24 | Jan 14 12:34:52 PM PST 24 | 47869846 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/44.xbar_random.4016976445 | Jan 14 12:34:33 PM PST 24 | Jan 14 12:35:19 PM PST 24 | 1383066448 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3515245157 | Jan 14 12:32:26 PM PST 24 | Jan 14 12:32:41 PM PST 24 | 1986970779 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.325645438 | Jan 14 12:33:08 PM PST 24 | Jan 14 12:34:31 PM PST 24 | 4928367219 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.177598153 | Jan 14 12:33:03 PM PST 24 | Jan 14 12:33:39 PM PST 24 | 4808517476 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2441045686 | Jan 14 12:34:27 PM PST 24 | Jan 14 12:34:50 PM PST 24 | 196764478 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.4271684851 | Jan 14 12:33:52 PM PST 24 | Jan 14 12:38:48 PM PST 24 | 3611162808 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/10.xbar_same_source.1946290082 | Jan 14 12:32:56 PM PST 24 | Jan 14 12:33:32 PM PST 24 | 3922439101 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/29.xbar_smoke.3221340979 | Jan 14 12:33:46 PM PST 24 | Jan 14 12:33:49 PM PST 24 | 60292861 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/48.xbar_random.4230437155 | Jan 14 12:34:46 PM PST 24 | Jan 14 12:35:25 PM PST 24 | 1238107767 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.2764243055 | Jan 14 12:33:38 PM PST 24 | Jan 14 12:36:24 PM PST 24 | 5688967184 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1739888971 | Jan 14 12:32:58 PM PST 24 | Jan 14 12:33:37 PM PST 24 | 6364269571 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2913992370 | Jan 14 12:34:43 PM PST 24 | Jan 14 12:35:05 PM PST 24 | 65413250 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3782493521 | Jan 14 12:32:58 PM PST 24 | Jan 14 12:34:02 PM PST 24 | 714433003 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2102416685 | Jan 14 12:33:28 PM PST 24 | Jan 14 12:33:31 PM PST 24 | 41581611 ps | ||
| T196 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.416924372 | Jan 14 12:32:18 PM PST 24 | Jan 14 12:32:56 PM PST 24 | 4930171248 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1757518766 | Jan 14 12:33:39 PM PST 24 | Jan 14 12:33:46 PM PST 24 | 313248815 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.89135151 | Jan 14 12:33:06 PM PST 24 | Jan 14 12:33:30 PM PST 24 | 831603789 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1893964342 | Jan 14 12:33:37 PM PST 24 | Jan 14 12:33:51 PM PST 24 | 126376992 ps | ||
| T172 | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2170269870 | Jan 14 12:33:03 PM PST 24 | Jan 14 12:36:41 PM PST 24 | 26889181363 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/9.xbar_error_random.2667880893 | Jan 14 12:32:53 PM PST 24 | Jan 14 12:33:03 PM PST 24 | 371580478 ps | ||
| T129 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.1347777349 | Jan 14 12:32:23 PM PST 24 | Jan 14 12:36:21 PM PST 24 | 9451502870 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3593572896 | Jan 14 12:32:45 PM PST 24 | Jan 14 12:34:00 PM PST 24 | 2215152406 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1822044703 | Jan 14 12:34:28 PM PST 24 | Jan 14 12:34:37 PM PST 24 | 153663412 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1781828234 | Jan 14 12:34:00 PM PST 24 | Jan 14 12:34:03 PM PST 24 | 67197487 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2673153571 | Jan 14 12:32:20 PM PST 24 | Jan 14 12:34:51 PM PST 24 | 2789341309 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.506224498 | Jan 14 12:32:53 PM PST 24 | Jan 14 12:33:14 PM PST 24 | 879864298 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.603147070 | Jan 14 12:32:22 PM PST 24 | Jan 14 12:33:18 PM PST 24 | 6973465204 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2899346880 | Jan 14 12:32:40 PM PST 24 | Jan 14 12:32:48 PM PST 24 | 70271932 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3039716473 | Jan 14 12:34:14 PM PST 24 | Jan 14 12:34:32 PM PST 24 | 231021561 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.2742271543 | Jan 14 12:32:58 PM PST 24 | Jan 14 12:33:17 PM PST 24 | 197110690 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3850031712 | Jan 14 12:32:54 PM PST 24 | Jan 14 12:33:21 PM PST 24 | 5739612084 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1322558235 | Jan 14 12:33:06 PM PST 24 | Jan 14 12:33:36 PM PST 24 | 908965879 ps | ||
| T218 | /workspace/coverage/xbar_build_mode/45.xbar_random.3674163739 | Jan 14 12:34:36 PM PST 24 | Jan 14 12:35:00 PM PST 24 | 666362357 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3834371147 | Jan 14 12:34:29 PM PST 24 | Jan 14 12:34:41 PM PST 24 | 330690082 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1633968590 | Jan 14 12:34:24 PM PST 24 | Jan 14 12:34:51 PM PST 24 | 197300747 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1706101094 | Jan 14 12:33:16 PM PST 24 | Jan 14 12:33:23 PM PST 24 | 837942498 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3238802025 | Jan 14 12:32:52 PM PST 24 | Jan 14 12:33:18 PM PST 24 | 7839175031 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/43.xbar_smoke.1178655765 | Jan 14 12:34:26 PM PST 24 | Jan 14 12:34:29 PM PST 24 | 23184091 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2627501052 | Jan 14 12:33:11 PM PST 24 | Jan 14 12:33:51 PM PST 24 | 475720774 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1926478033 | Jan 14 12:34:18 PM PST 24 | Jan 14 12:37:22 PM PST 24 | 24917385476 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.399033364 | Jan 14 12:34:36 PM PST 24 | Jan 14 12:38:14 PM PST 24 | 73209697884 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1237826937 | Jan 14 12:33:25 PM PST 24 | Jan 14 12:33:37 PM PST 24 | 30044105 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.4179548105 | Jan 14 12:33:18 PM PST 24 | Jan 14 12:33:44 PM PST 24 | 196267850 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1617667755 | Jan 14 12:32:31 PM PST 24 | Jan 14 12:33:31 PM PST 24 | 1548995772 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/31.xbar_error_random.3955694252 | Jan 14 12:33:51 PM PST 24 | Jan 14 12:34:07 PM PST 24 | 248835758 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1673611637 | Jan 14 12:34:19 PM PST 24 | Jan 14 12:34:58 PM PST 24 | 13969210662 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2688593756 | Jan 14 12:34:08 PM PST 24 | Jan 14 12:35:09 PM PST 24 | 1676969960 ps | ||
| T132 | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.6864565 | Jan 14 12:34:24 PM PST 24 | Jan 14 12:36:52 PM PST 24 | 19847306651 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/48.xbar_error_random.3529982134 | Jan 14 12:34:48 PM PST 24 | Jan 14 12:35:15 PM PST 24 | 726513983 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2782742176 | Jan 14 12:32:54 PM PST 24 | Jan 14 12:33:07 PM PST 24 | 131578313 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1707884647 | Jan 14 12:34:45 PM PST 24 | Jan 14 12:35:00 PM PST 24 | 618037962 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2313700146 | Jan 14 12:32:21 PM PST 24 | Jan 14 12:32:27 PM PST 24 | 27075287 ps | ||
| T124 | /workspace/coverage/xbar_build_mode/43.xbar_random.3236001460 | Jan 14 12:34:27 PM PST 24 | Jan 14 12:35:08 PM PST 24 | 1203434665 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2782172401 | Jan 14 12:33:30 PM PST 24 | Jan 14 12:34:24 PM PST 24 | 23345234659 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2688806354 | Jan 14 12:34:08 PM PST 24 | Jan 14 12:34:37 PM PST 24 | 361230057 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3113373780 | Jan 14 12:32:59 PM PST 24 | Jan 14 12:33:27 PM PST 24 | 6108119246 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.623242839 | Jan 14 12:34:52 PM PST 24 | Jan 14 12:38:15 PM PST 24 | 124497628279 ps | ||
| T125 | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.874669958 | Jan 14 12:32:15 PM PST 24 | Jan 14 12:34:44 PM PST 24 | 5083877364 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.710974854 | Jan 14 12:33:08 PM PST 24 | Jan 14 12:34:22 PM PST 24 | 674263413 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.4234767433 | Jan 14 12:32:53 PM PST 24 | Jan 14 12:33:05 PM PST 24 | 249537954 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2288151815 | Jan 14 12:34:14 PM PST 24 | Jan 14 12:34:37 PM PST 24 | 75192598 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/21.xbar_same_source.3020181742 | Jan 14 12:33:12 PM PST 24 | Jan 14 12:33:18 PM PST 24 | 689380020 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/16.xbar_smoke.3597096829 | Jan 14 12:33:03 PM PST 24 | Jan 14 12:33:08 PM PST 24 | 262989433 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2874717532 | Jan 14 12:33:06 PM PST 24 | Jan 14 12:33:41 PM PST 24 | 13472023799 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.827965710 | Jan 14 12:33:58 PM PST 24 | Jan 14 12:35:38 PM PST 24 | 4283393061 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/25.xbar_random.3559542985 | Jan 14 12:33:28 PM PST 24 | Jan 14 12:34:03 PM PST 24 | 3341556119 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2534053991 | Jan 14 12:34:10 PM PST 24 | Jan 14 12:34:13 PM PST 24 | 24933351 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/23.xbar_smoke.468459583 | Jan 14 12:33:18 PM PST 24 | Jan 14 12:33:22 PM PST 24 | 154720171 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/35.xbar_smoke.3241658633 | Jan 14 12:34:13 PM PST 24 | Jan 14 12:34:17 PM PST 24 | 379640432 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.25902171 | Jan 14 12:33:28 PM PST 24 | Jan 14 12:37:15 PM PST 24 | 51875972530 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3739770567 | Jan 14 12:34:20 PM PST 24 | Jan 14 12:39:56 PM PST 24 | 2865364737 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1227217548 | Jan 14 12:34:14 PM PST 24 | Jan 14 12:35:22 PM PST 24 | 4853771621 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.333981969 | Jan 14 12:34:39 PM PST 24 | Jan 14 12:35:46 PM PST 24 | 544075393 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3260092709 | Jan 14 12:32:57 PM PST 24 | Jan 14 12:33:32 PM PST 24 | 158834709 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2195587543 | Jan 14 12:33:45 PM PST 24 | Jan 14 12:46:54 PM PST 24 | 314854704706 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2741480356 | Jan 14 12:32:15 PM PST 24 | Jan 14 12:32:24 PM PST 24 | 471135918 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1789103320 | Jan 14 12:34:02 PM PST 24 | Jan 14 12:36:37 PM PST 24 | 8744855594 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.651456369 | Jan 14 12:32:46 PM PST 24 | Jan 14 12:36:56 PM PST 24 | 28248049925 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/17.xbar_random.409286694 | Jan 14 12:33:14 PM PST 24 | Jan 14 12:33:23 PM PST 24 | 652928807 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1895638941 | Jan 14 12:34:35 PM PST 24 | Jan 14 12:37:42 PM PST 24 | 1139311209 ps | ||
| T133 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.176912050 | Jan 14 12:32:19 PM PST 24 | Jan 14 12:32:48 PM PST 24 | 5694244322 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.4155378216 | Jan 14 12:34:19 PM PST 24 | Jan 14 12:34:58 PM PST 24 | 9159009083 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2301358331 | Jan 14 12:34:43 PM PST 24 | Jan 14 12:38:58 PM PST 24 | 1585951230 ps |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.4040649767 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 487410225 ps |
| CPU time | 58.94 seconds |
| Started | Jan 14 12:34:34 PM PST 24 |
| Finished | Jan 14 12:35:39 PM PST 24 |
| Peak memory | 211880 kb |
| Host | smart-186bdbdd-6a85-4acf-88bc-c06ca38ae07e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4040649767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.4040649767 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2500879561 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 193120088270 ps |
| CPU time | 573.7 seconds |
| Started | Jan 14 12:33:53 PM PST 24 |
| Finished | Jan 14 12:43:27 PM PST 24 |
| Peak memory | 212008 kb |
| Host | smart-ad8e86d9-62ec-47cb-8b03-79fd3e30e788 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2500879561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.2500879561 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3465637778 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 80378727775 ps |
| CPU time | 629.07 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:43:35 PM PST 24 |
| Peak memory | 206228 kb |
| Host | smart-e387b9b3-e17e-4277-aab6-5107b07c6b15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3465637778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.3465637778 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3184338334 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8041981840 ps |
| CPU time | 334.33 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:39:26 PM PST 24 |
| Peak memory | 220088 kb |
| Host | smart-c3e97f21-c17c-43a2-a1d8-64b654a370b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3184338334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.3184338334 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.701427567 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 66429047237 ps |
| CPU time | 587.97 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:43:02 PM PST 24 |
| Peak memory | 207136 kb |
| Host | smart-74366c8b-c0e9-41ea-b251-b9526db0024f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=701427567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.701427567 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.700108067 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 31833164911 ps |
| CPU time | 78.94 seconds |
| Started | Jan 14 12:33:04 PM PST 24 |
| Finished | Jan 14 12:34:24 PM PST 24 |
| Peak memory | 204880 kb |
| Host | smart-2205b022-c43c-4fd4-9659-8a3727d620cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=700108067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.700108067 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2031889679 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 248121259672 ps |
| CPU time | 710.74 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:45:05 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-1664e9ae-4a3d-42d7-957c-859e2b466edf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2031889679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.2031889679 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1240347510 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6404187201 ps |
| CPU time | 399.48 seconds |
| Started | Jan 14 12:34:12 PM PST 24 |
| Finished | Jan 14 12:40:52 PM PST 24 |
| Peak memory | 209724 kb |
| Host | smart-dbf9d59c-1807-4ee2-9d45-0afa61204fb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1240347510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.1240347510 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2930070279 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 740239085 ps |
| CPU time | 159.22 seconds |
| Started | Jan 14 12:33:41 PM PST 24 |
| Finished | Jan 14 12:36:21 PM PST 24 |
| Peak memory | 208544 kb |
| Host | smart-f89a7ada-8769-4a9d-a4f1-801bf50d8f1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2930070279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.2930070279 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1129180984 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4873026689 ps |
| CPU time | 130.43 seconds |
| Started | Jan 14 12:34:26 PM PST 24 |
| Finished | Jan 14 12:36:37 PM PST 24 |
| Peak memory | 208468 kb |
| Host | smart-001ec628-b915-4b67-9c12-a4ccf6fc893a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1129180984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1129180984 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2496658945 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1167026280 ps |
| CPU time | 42.94 seconds |
| Started | Jan 14 12:33:40 PM PST 24 |
| Finished | Jan 14 12:34:24 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-a3c9f289-6147-44c3-91c6-ba90a46676fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2496658945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2496658945 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1153584184 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4693505696 ps |
| CPU time | 181.97 seconds |
| Started | Jan 14 12:33:32 PM PST 24 |
| Finished | Jan 14 12:36:34 PM PST 24 |
| Peak memory | 207328 kb |
| Host | smart-f01e3780-f7a8-4402-afcb-58ee25ac9a94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1153584184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1153584184 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2521985917 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4179353770 ps |
| CPU time | 181.01 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:36:12 PM PST 24 |
| Peak memory | 209996 kb |
| Host | smart-4b6a5f87-fb55-4d3f-b360-57b3a303177f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2521985917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.2521985917 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.529854929 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 125090946 ps |
| CPU time | 17.52 seconds |
| Started | Jan 14 12:32:34 PM PST 24 |
| Finished | Jan 14 12:32:52 PM PST 24 |
| Peak memory | 206928 kb |
| Host | smart-49418326-8eb9-4ca3-8ce9-083d821d7cae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=529854929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese t_error.529854929 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.325976578 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5530766234 ps |
| CPU time | 394.74 seconds |
| Started | Jan 14 12:32:47 PM PST 24 |
| Finished | Jan 14 12:39:25 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-6678f63b-b9f1-43e9-86ee-ab22c6d616e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=325976578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_ reset.325976578 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.1751482924 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6837891722 ps |
| CPU time | 189.32 seconds |
| Started | Jan 14 12:34:20 PM PST 24 |
| Finished | Jan 14 12:37:30 PM PST 24 |
| Peak memory | 208476 kb |
| Host | smart-6bfa63e2-2c97-46a6-8719-e6b9cf1a7e46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1751482924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1751482924 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.3555778886 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 646095368 ps |
| CPU time | 19.98 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:26 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-de8f6e80-dd01-4f66-9dc5-3a0bbcf05c66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3555778886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3555778886 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2151337520 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1042274984 ps |
| CPU time | 93.11 seconds |
| Started | Jan 14 12:34:09 PM PST 24 |
| Finished | Jan 14 12:35:42 PM PST 24 |
| Peak memory | 207376 kb |
| Host | smart-ccb6944f-5628-48b0-a307-0258baa20b20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2151337520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.2151337520 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.357061134 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 366866461 ps |
| CPU time | 72.96 seconds |
| Started | Jan 14 12:34:45 PM PST 24 |
| Finished | Jan 14 12:36:00 PM PST 24 |
| Peak memory | 208260 kb |
| Host | smart-b921e53c-ab29-47bf-832e-7414f118a82b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=357061134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_res et_error.357061134 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1108176094 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3959612468 ps |
| CPU time | 317.02 seconds |
| Started | Jan 14 12:32:24 PM PST 24 |
| Finished | Jan 14 12:37:43 PM PST 24 |
| Peak memory | 208988 kb |
| Host | smart-61a1ac3c-72da-47b1-8eb5-d4cf7cd9759b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1108176094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.1108176094 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.413825392 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1215250328 ps |
| CPU time | 39.16 seconds |
| Started | Jan 14 12:34:17 PM PST 24 |
| Finished | Jan 14 12:34:57 PM PST 24 |
| Peak memory | 211804 kb |
| Host | smart-e94af70b-d29d-4f13-88fc-70dcbb592c66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=413825392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.413825392 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.1804065349 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 137869718 ps |
| CPU time | 22.27 seconds |
| Started | Jan 14 12:32:19 PM PST 24 |
| Finished | Jan 14 12:32:47 PM PST 24 |
| Peak memory | 205720 kb |
| Host | smart-b898d2a7-6829-4b45-be65-3000ec79d777 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1804065349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1804065349 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3957891135 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 108903903739 ps |
| CPU time | 274.81 seconds |
| Started | Jan 14 12:32:18 PM PST 24 |
| Finished | Jan 14 12:36:59 PM PST 24 |
| Peak memory | 211864 kb |
| Host | smart-09740d42-9c22-4809-af7a-7bc1d42c2cbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3957891135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.3957891135 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3925937275 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 752125059 ps |
| CPU time | 28.07 seconds |
| Started | Jan 14 12:32:18 PM PST 24 |
| Finished | Jan 14 12:32:52 PM PST 24 |
| Peak memory | 204236 kb |
| Host | smart-5a2a649a-b751-49b0-b174-571ab4f07944 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3925937275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3925937275 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.322487528 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1384133185 ps |
| CPU time | 34.17 seconds |
| Started | Jan 14 12:32:15 PM PST 24 |
| Finished | Jan 14 12:32:52 PM PST 24 |
| Peak memory | 203600 kb |
| Host | smart-75ec267c-a89a-4782-80be-9adadbd313e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=322487528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.322487528 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.4242373174 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 732450370 ps |
| CPU time | 14.18 seconds |
| Started | Jan 14 12:32:07 PM PST 24 |
| Finished | Jan 14 12:32:23 PM PST 24 |
| Peak memory | 211816 kb |
| Host | smart-11cfaa8e-1bcf-4bcb-9bca-2fcf64bb7174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4242373174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.4242373174 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3641536040 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 105025932411 ps |
| CPU time | 142.89 seconds |
| Started | Jan 14 12:32:18 PM PST 24 |
| Finished | Jan 14 12:34:47 PM PST 24 |
| Peak memory | 212048 kb |
| Host | smart-3f6cb185-2ecc-4753-82b6-366ef48b12eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641536040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3641536040 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.808203728 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 41790945583 ps |
| CPU time | 272.72 seconds |
| Started | Jan 14 12:32:11 PM PST 24 |
| Finished | Jan 14 12:36:50 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-6291561e-63fc-4158-b8d6-1028302fa11f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=808203728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.808203728 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.4277085382 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 200780001 ps |
| CPU time | 21.91 seconds |
| Started | Jan 14 12:32:17 PM PST 24 |
| Finished | Jan 14 12:32:45 PM PST 24 |
| Peak memory | 204668 kb |
| Host | smart-6f361afd-3661-453a-bc86-aeccca6024c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277085382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.4277085382 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2741480356 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 471135918 ps |
| CPU time | 6.81 seconds |
| Started | Jan 14 12:32:15 PM PST 24 |
| Finished | Jan 14 12:32:24 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-188cf808-ec95-47d8-908a-605b63065319 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2741480356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2741480356 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.2202999419 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 27666381 ps |
| CPU time | 2.48 seconds |
| Started | Jan 14 12:32:19 PM PST 24 |
| Finished | Jan 14 12:32:27 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-79ce50b3-1b48-4e9a-bdb8-fffd8b3383ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2202999419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2202999419 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2524603210 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 14097866823 ps |
| CPU time | 33.38 seconds |
| Started | Jan 14 12:32:10 PM PST 24 |
| Finished | Jan 14 12:32:50 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-5aa409f7-3d62-4fdb-91eb-0f212704150d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524603210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2524603210 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2465105352 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 2748155375 ps |
| CPU time | 21.63 seconds |
| Started | Jan 14 12:32:19 PM PST 24 |
| Finished | Jan 14 12:32:46 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-16776b89-5a4a-4eab-97c5-7ba56c2d6afb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2465105352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2465105352 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.4228087303 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 81576640 ps |
| CPU time | 2.16 seconds |
| Started | Jan 14 12:32:17 PM PST 24 |
| Finished | Jan 14 12:32:25 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-2a46ea96-84fa-47c0-90b4-548f8841d654 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228087303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.4228087303 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.874669958 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 5083877364 ps |
| CPU time | 146.1 seconds |
| Started | Jan 14 12:32:15 PM PST 24 |
| Finished | Jan 14 12:34:44 PM PST 24 |
| Peak memory | 207256 kb |
| Host | smart-311b9c75-8b6e-40d5-9739-350718b77ef9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=874669958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.874669958 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2673153571 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2789341309 ps |
| CPU time | 146.79 seconds |
| Started | Jan 14 12:32:20 PM PST 24 |
| Finished | Jan 14 12:34:51 PM PST 24 |
| Peak memory | 205696 kb |
| Host | smart-5d56892e-1845-4871-8a0a-03c82a52d71d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2673153571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2673153571 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3159553085 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 11799832995 ps |
| CPU time | 560.14 seconds |
| Started | Jan 14 12:32:18 PM PST 24 |
| Finished | Jan 14 12:41:44 PM PST 24 |
| Peak memory | 208676 kb |
| Host | smart-30d9e675-cc43-438f-a791-5e4a7636abf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3159553085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.3159553085 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.722821862 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1888008823 ps |
| CPU time | 231.41 seconds |
| Started | Jan 14 12:32:21 PM PST 24 |
| Finished | Jan 14 12:36:16 PM PST 24 |
| Peak memory | 220020 kb |
| Host | smart-1fb84fa1-4fdd-4284-b661-1884e49a27ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=722821862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rese t_error.722821862 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.1008184662 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 564648606 ps |
| CPU time | 14.99 seconds |
| Started | Jan 14 12:32:12 PM PST 24 |
| Finished | Jan 14 12:32:32 PM PST 24 |
| Peak memory | 211828 kb |
| Host | smart-79a8a677-ba2a-42cf-a6d0-cb2a14df5e0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1008184662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1008184662 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.1103976357 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1603830206 ps |
| CPU time | 25.46 seconds |
| Started | Jan 14 12:32:22 PM PST 24 |
| Finished | Jan 14 12:32:50 PM PST 24 |
| Peak memory | 211896 kb |
| Host | smart-0f693bac-817c-4471-8234-c687f53e1a95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1103976357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1103976357 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.352631578 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6664623523 ps |
| CPU time | 37.94 seconds |
| Started | Jan 14 12:32:26 PM PST 24 |
| Finished | Jan 14 12:33:06 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-62e46617-89b6-4e6b-a3b4-61cc9b6b9b2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=352631578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow _rsp.352631578 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2313700146 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 27075287 ps |
| CPU time | 2.54 seconds |
| Started | Jan 14 12:32:21 PM PST 24 |
| Finished | Jan 14 12:32:27 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-b515bc2a-30c3-45c3-8bfd-e01fa160a7f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2313700146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2313700146 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.314309568 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2786558198 ps |
| CPU time | 21.04 seconds |
| Started | Jan 14 12:32:14 PM PST 24 |
| Finished | Jan 14 12:32:38 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-71a341e6-e874-46f8-877a-8f21cb1a7b92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=314309568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.314309568 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.2646431588 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2272392100 ps |
| CPU time | 17.07 seconds |
| Started | Jan 14 12:32:21 PM PST 24 |
| Finished | Jan 14 12:32:42 PM PST 24 |
| Peak memory | 211848 kb |
| Host | smart-fe195f35-55f7-4d3a-b4d0-481e52c371ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2646431588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2646431588 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3822474264 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 52927761378 ps |
| CPU time | 239.55 seconds |
| Started | Jan 14 12:32:28 PM PST 24 |
| Finished | Jan 14 12:36:28 PM PST 24 |
| Peak memory | 211852 kb |
| Host | smart-79123d05-911f-4b48-a5bc-ac94e1d90485 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822474264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3822474264 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1194427751 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 5012273113 ps |
| CPU time | 30.36 seconds |
| Started | Jan 14 12:32:29 PM PST 24 |
| Finished | Jan 14 12:32:59 PM PST 24 |
| Peak memory | 211912 kb |
| Host | smart-68cc1911-9fd2-4a68-94c1-d51ae108e8c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1194427751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1194427751 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.1941750954 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 198099264 ps |
| CPU time | 26.71 seconds |
| Started | Jan 14 12:32:20 PM PST 24 |
| Finished | Jan 14 12:32:51 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-765c3bfa-c164-4f6f-a1a9-df10a074e65c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941750954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1941750954 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.1642800368 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 993069734 ps |
| CPU time | 19.15 seconds |
| Started | Jan 14 12:32:30 PM PST 24 |
| Finished | Jan 14 12:32:50 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-29c81f38-3003-4095-bc11-fb7d86f047aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1642800368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1642800368 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.1766376416 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 288237800 ps |
| CPU time | 3.05 seconds |
| Started | Jan 14 12:32:23 PM PST 24 |
| Finished | Jan 14 12:32:28 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-9e778901-8f09-42a9-aae5-d000e68d6867 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1766376416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1766376416 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.176912050 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5694244322 ps |
| CPU time | 23.32 seconds |
| Started | Jan 14 12:32:19 PM PST 24 |
| Finished | Jan 14 12:32:48 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-005d6324-d9f8-4ebc-8208-b291e60c3b3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=176912050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.176912050 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.309613738 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 4953097577 ps |
| CPU time | 30.39 seconds |
| Started | Jan 14 12:32:27 PM PST 24 |
| Finished | Jan 14 12:32:58 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-f7d6f3a3-8021-4337-93d6-727e1f92e4bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=309613738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.309613738 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.4174602314 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 42235627 ps |
| CPU time | 2.29 seconds |
| Started | Jan 14 12:32:19 PM PST 24 |
| Finished | Jan 14 12:32:27 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-87539c30-3516-4da3-8a0a-b103272e26cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174602314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.4174602314 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.950611675 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 25892158977 ps |
| CPU time | 265.04 seconds |
| Started | Jan 14 12:32:26 PM PST 24 |
| Finished | Jan 14 12:36:53 PM PST 24 |
| Peak memory | 210832 kb |
| Host | smart-99ed5460-6f44-4445-ad28-426e205746d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=950611675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.950611675 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.4190790639 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1361861609 ps |
| CPU time | 124.52 seconds |
| Started | Jan 14 12:32:23 PM PST 24 |
| Finished | Jan 14 12:34:30 PM PST 24 |
| Peak memory | 208584 kb |
| Host | smart-a7871fb0-8742-4e86-af12-afb4aecf4479 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4190790639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.4190790639 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.987648139 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1405746359 ps |
| CPU time | 45.73 seconds |
| Started | Jan 14 12:32:25 PM PST 24 |
| Finished | Jan 14 12:33:13 PM PST 24 |
| Peak memory | 211776 kb |
| Host | smart-b9e5281b-f0b9-4ebd-bc2b-361fe77360f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=987648139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rese t_error.987648139 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3018175495 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 637224999 ps |
| CPU time | 13.68 seconds |
| Started | Jan 14 12:32:20 PM PST 24 |
| Finished | Jan 14 12:32:38 PM PST 24 |
| Peak memory | 211924 kb |
| Host | smart-bac25e47-f380-43d4-9cdd-1cbc0c3a9aa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3018175495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3018175495 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2782742176 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 131578313 ps |
| CPU time | 12.84 seconds |
| Started | Jan 14 12:32:54 PM PST 24 |
| Finished | Jan 14 12:33:07 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-fea91d09-851e-437b-9595-98a52bf5f9da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2782742176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2782742176 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.745459093 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 87110562212 ps |
| CPU time | 786.06 seconds |
| Started | Jan 14 12:32:54 PM PST 24 |
| Finished | Jan 14 12:46:01 PM PST 24 |
| Peak memory | 211932 kb |
| Host | smart-d7c3edf2-bb48-48ad-bbae-1e2a9fcfa364 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=745459093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slo w_rsp.745459093 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2657740069 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 264630840 ps |
| CPU time | 20.94 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:33:31 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-5ac4dace-1188-4ff8-bcf7-5494c9e1db57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2657740069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2657740069 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.1423795356 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 809195487 ps |
| CPU time | 24.2 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:33:24 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-da9a18da-baf0-4ca8-9ef9-768a1c80f3da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1423795356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1423795356 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.3543627177 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 155544266 ps |
| CPU time | 16.4 seconds |
| Started | Jan 14 12:32:55 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 204792 kb |
| Host | smart-f82569a7-c819-4739-a863-bf8194dd5ec1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3543627177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3543627177 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3251962116 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 45555476384 ps |
| CPU time | 195.78 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:36:20 PM PST 24 |
| Peak memory | 211988 kb |
| Host | smart-79ee6a0d-832e-4ffd-98c3-2028cc4c64dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251962116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3251962116 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1011374016 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 31025259573 ps |
| CPU time | 170.24 seconds |
| Started | Jan 14 12:32:55 PM PST 24 |
| Finished | Jan 14 12:35:46 PM PST 24 |
| Peak memory | 211976 kb |
| Host | smart-25d9935a-4fd4-4574-b3a1-98cbf0965fa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1011374016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1011374016 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.4223026528 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 119570642 ps |
| CPU time | 5.98 seconds |
| Started | Jan 14 12:32:56 PM PST 24 |
| Finished | Jan 14 12:33:02 PM PST 24 |
| Peak memory | 211740 kb |
| Host | smart-e9de3c53-226a-48ee-82cb-c05988c9b707 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223026528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.4223026528 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.1946290082 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3922439101 ps |
| CPU time | 35.37 seconds |
| Started | Jan 14 12:32:56 PM PST 24 |
| Finished | Jan 14 12:33:32 PM PST 24 |
| Peak memory | 203928 kb |
| Host | smart-42ea1e9e-5585-4283-84c8-b75ca742972a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1946290082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1946290082 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.2828214031 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 161926367 ps |
| CPU time | 3.2 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:10 PM PST 24 |
| Peak memory | 203600 kb |
| Host | smart-5e5a91cd-66f5-4223-8c08-04eaf57e5eec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2828214031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2828214031 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3113373780 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 6108119246 ps |
| CPU time | 27.12 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:33:27 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-0b71cbdc-02eb-466d-b8ff-ce3509aac977 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113373780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3113373780 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3850031712 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 5739612084 ps |
| CPU time | 26.37 seconds |
| Started | Jan 14 12:32:54 PM PST 24 |
| Finished | Jan 14 12:33:21 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-a318dc50-7d19-4f73-9c54-0b9b6a0860dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3850031712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3850031712 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1227785682 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 26786470 ps |
| CPU time | 2.18 seconds |
| Started | Jan 14 12:32:54 PM PST 24 |
| Finished | Jan 14 12:32:57 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-62ec651e-786b-4c1e-bc58-3260959bf943 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227785682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1227785682 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.3423832473 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 9675478719 ps |
| CPU time | 167.69 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:35:55 PM PST 24 |
| Peak memory | 208140 kb |
| Host | smart-b69eceb6-dc2a-4b76-933f-b9d874245ed6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3423832473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3423832473 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.325645438 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 4928367219 ps |
| CPU time | 81.11 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:34:31 PM PST 24 |
| Peak memory | 205480 kb |
| Host | smart-e6196c5c-d4c3-4a3c-8a02-d473efeb4be5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=325645438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.325645438 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.454335361 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1797453467 ps |
| CPU time | 192.76 seconds |
| Started | Jan 14 12:33:02 PM PST 24 |
| Finished | Jan 14 12:36:16 PM PST 24 |
| Peak memory | 208424 kb |
| Host | smart-7b6d9dac-86af-4b6f-914f-e1c0b8d913df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=454335361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand _reset.454335361 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2254596463 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 3888809065 ps |
| CPU time | 141.29 seconds |
| Started | Jan 14 12:33:04 PM PST 24 |
| Finished | Jan 14 12:35:26 PM PST 24 |
| Peak memory | 209768 kb |
| Host | smart-366f4603-d53c-489d-8c00-9ff513256954 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2254596463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.2254596463 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.2899321997 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 562844101 ps |
| CPU time | 8.29 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 205060 kb |
| Host | smart-25152117-1b6c-4cf3-b6a4-7b724ecdea1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2899321997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2899321997 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.150146139 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2150659648 ps |
| CPU time | 35.7 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:33:35 PM PST 24 |
| Peak memory | 211916 kb |
| Host | smart-21d49166-9466-4212-b869-eabf36abfd6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=150146139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.150146139 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1488181927 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 32687316117 ps |
| CPU time | 211.8 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:36:32 PM PST 24 |
| Peak memory | 210980 kb |
| Host | smart-f7f1dee2-e898-407c-a642-081329ddc174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1488181927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.1488181927 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.4222240566 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 318529298 ps |
| CPU time | 11.6 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-f02e940c-b9ce-4ceb-a76b-1feee1a8ffda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4222240566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.4222240566 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.3144851138 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1054132693 ps |
| CPU time | 34.39 seconds |
| Started | Jan 14 12:33:04 PM PST 24 |
| Finished | Jan 14 12:33:40 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-4f9bc537-8b98-4fc1-b392-60365f297ebd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3144851138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3144851138 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.472139269 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 264120250 ps |
| CPU time | 8.21 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 204152 kb |
| Host | smart-1f0fdc2b-45ba-4a25-89b3-90bb2af494d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=472139269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.472139269 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1739888971 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 6364269571 ps |
| CPU time | 38.95 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:33:37 PM PST 24 |
| Peak memory | 211808 kb |
| Host | smart-6b74469f-90c3-4572-a799-6718ed8c0a19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739888971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1739888971 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.320353975 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 28952432853 ps |
| CPU time | 260.03 seconds |
| Started | Jan 14 12:32:55 PM PST 24 |
| Finished | Jan 14 12:37:16 PM PST 24 |
| Peak memory | 211832 kb |
| Host | smart-480987d7-6380-4bb5-862b-3877a66528c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=320353975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.320353975 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.54924564 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 213053128 ps |
| CPU time | 17.26 seconds |
| Started | Jan 14 12:32:57 PM PST 24 |
| Finished | Jan 14 12:33:15 PM PST 24 |
| Peak memory | 211848 kb |
| Host | smart-8820defd-56d8-45d9-a587-fd67c4b4b5a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54924564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.54924564 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.3049663850 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 293034280 ps |
| CPU time | 14.03 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-95fbe158-00d8-44c4-bbca-38a13785c108 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3049663850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3049663850 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.1117246125 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 188161172 ps |
| CPU time | 3.75 seconds |
| Started | Jan 14 12:32:55 PM PST 24 |
| Finished | Jan 14 12:33:00 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-7c02e3d5-18fa-4093-aa54-751b1f9b0595 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1117246125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1117246125 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1206624489 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 12204741873 ps |
| CPU time | 32.19 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-dba6717a-a46e-4e46-8bc9-3e39380b1cad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206624489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1206624489 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3836749825 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3517152141 ps |
| CPU time | 28.86 seconds |
| Started | Jan 14 12:32:57 PM PST 24 |
| Finished | Jan 14 12:33:27 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-0fc71a71-9e52-4f6a-b2ca-21407415e8cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3836749825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3836749825 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.13942589 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 33904266 ps |
| CPU time | 2.21 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:09 PM PST 24 |
| Peak memory | 203616 kb |
| Host | smart-a85a31b2-1f50-4165-a224-d842807e4725 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13942589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.13942589 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.3476668395 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 5082252375 ps |
| CPU time | 87.66 seconds |
| Started | Jan 14 12:32:57 PM PST 24 |
| Finished | Jan 14 12:34:26 PM PST 24 |
| Peak memory | 205440 kb |
| Host | smart-646da7c9-8e8b-433d-a274-47c43e1cdee2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3476668395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3476668395 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2429201328 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1343871297 ps |
| CPU time | 73.35 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:34:12 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-49acd57a-a10f-4d9c-91fe-8e2f83d814eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2429201328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2429201328 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.45301267 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 434378656 ps |
| CPU time | 149.59 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:35:29 PM PST 24 |
| Peak memory | 208964 kb |
| Host | smart-6f20344b-142a-42d2-917e-ec007fb14bd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=45301267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_ reset.45301267 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1348363547 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 20581375012 ps |
| CPU time | 934.44 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:48:41 PM PST 24 |
| Peak memory | 228272 kb |
| Host | smart-5d2b609f-59c2-4125-a555-ed7befc0a7d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1348363547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1348363547 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2520172274 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 794750417 ps |
| CPU time | 20.94 seconds |
| Started | Jan 14 12:33:04 PM PST 24 |
| Finished | Jan 14 12:33:26 PM PST 24 |
| Peak memory | 204796 kb |
| Host | smart-7698bb12-cd97-4deb-8e43-3eaece24bcc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2520172274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2520172274 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1322558235 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 908965879 ps |
| CPU time | 28.38 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:33:36 PM PST 24 |
| Peak memory | 206044 kb |
| Host | smart-f6fb13be-eeae-4a5b-978c-ecd70a56f11e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1322558235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1322558235 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2520301962 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 39188025658 ps |
| CPU time | 270.15 seconds |
| Started | Jan 14 12:33:00 PM PST 24 |
| Finished | Jan 14 12:37:31 PM PST 24 |
| Peak memory | 206368 kb |
| Host | smart-5c63a25e-ea5e-4a00-b7b1-1fc2ef8baead |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2520301962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.2520301962 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.180944212 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 78050008 ps |
| CPU time | 6.49 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:33:05 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-b6319936-15f1-410e-ab07-b4ac14afea2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=180944212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.180944212 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.760332089 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 45060922 ps |
| CPU time | 2.06 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:33:00 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-998b03bc-6ee5-4452-af4a-70e6a7d52ddb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=760332089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.760332089 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.3517978773 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 72304701 ps |
| CPU time | 6.52 seconds |
| Started | Jan 14 12:33:07 PM PST 24 |
| Finished | Jan 14 12:33:14 PM PST 24 |
| Peak memory | 211788 kb |
| Host | smart-06b0edf6-8644-463c-898c-44895413b37b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3517978773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3517978773 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.266942984 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 73883168476 ps |
| CPU time | 255.52 seconds |
| Started | Jan 14 12:33:01 PM PST 24 |
| Finished | Jan 14 12:37:18 PM PST 24 |
| Peak memory | 205216 kb |
| Host | smart-b0815acd-bdfd-42f8-987d-aa4fa9b70b0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=266942984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.266942984 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.584952301 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1639753282 ps |
| CPU time | 16.1 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:33:25 PM PST 24 |
| Peak memory | 203320 kb |
| Host | smart-b86b8681-41f0-4717-b89a-ff7198004e5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=584952301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.584952301 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.842943848 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 762856345 ps |
| CPU time | 26.17 seconds |
| Started | Jan 14 12:32:56 PM PST 24 |
| Finished | Jan 14 12:33:23 PM PST 24 |
| Peak memory | 211840 kb |
| Host | smart-827310a8-d7bc-4696-bda9-fe62a980e3d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842943848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.842943848 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.1466329612 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 7253155432 ps |
| CPU time | 25.72 seconds |
| Started | Jan 14 12:32:56 PM PST 24 |
| Finished | Jan 14 12:33:22 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-3d38eb13-803d-4a26-87aa-bf841adcfd11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1466329612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1466329612 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.2738292673 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 183996160 ps |
| CPU time | 3.42 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:33:08 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-1f450e92-082c-41ee-943c-28f1dccd8fd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2738292673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2738292673 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2666921887 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4076984646 ps |
| CPU time | 19.95 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:26 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-e90a3844-2e9c-4db9-ab17-3820defa27db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666921887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2666921887 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2528478016 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 13601380316 ps |
| CPU time | 39.36 seconds |
| Started | Jan 14 12:33:00 PM PST 24 |
| Finished | Jan 14 12:33:40 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-00553af5-3d71-4313-b9e6-c5d2b9ee8859 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2528478016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2528478016 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3421556762 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 59909001 ps |
| CPU time | 2.17 seconds |
| Started | Jan 14 12:33:02 PM PST 24 |
| Finished | Jan 14 12:33:06 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-1784724c-349d-4bf1-9705-4fcfe5985b94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421556762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3421556762 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.321553399 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1476536441 ps |
| CPU time | 189.33 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:36:15 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-6d2ab9f7-2916-41a8-96c0-6e33dce0e6ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=321553399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.321553399 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3607380347 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 1211273604 ps |
| CPU time | 73.76 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:34:23 PM PST 24 |
| Peak memory | 205108 kb |
| Host | smart-83005fdb-fd8f-47ec-b7f1-568c0572910e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3607380347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3607380347 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3005082686 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 163284446 ps |
| CPU time | 31.63 seconds |
| Started | Jan 14 12:32:54 PM PST 24 |
| Finished | Jan 14 12:33:27 PM PST 24 |
| Peak memory | 206908 kb |
| Host | smart-f26a8a16-8707-40a7-9aaf-f0c751a38eaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3005082686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.3005082686 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2896355390 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6322300800 ps |
| CPU time | 243.33 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:37:07 PM PST 24 |
| Peak memory | 220156 kb |
| Host | smart-0d7217c3-ba0a-4bd5-91b6-d8595088090b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2896355390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.2896355390 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.2742271543 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 197110690 ps |
| CPU time | 18.12 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:33:17 PM PST 24 |
| Peak memory | 205012 kb |
| Host | smart-e5cae558-bf94-4824-ad0f-93dad1a78b18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2742271543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2742271543 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.171161612 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 665350896 ps |
| CPU time | 37.59 seconds |
| Started | Jan 14 12:33:02 PM PST 24 |
| Finished | Jan 14 12:33:41 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-c2a29825-5034-4266-89d8-e0a1e60692a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=171161612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.171161612 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1688031772 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 439503333 ps |
| CPU time | 16.71 seconds |
| Started | Jan 14 12:33:02 PM PST 24 |
| Finished | Jan 14 12:33:20 PM PST 24 |
| Peak memory | 204016 kb |
| Host | smart-682e368d-0c7c-49fb-9453-bfb02a11420f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1688031772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1688031772 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.719654036 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 617507165 ps |
| CPU time | 21.44 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:28 PM PST 24 |
| Peak memory | 203328 kb |
| Host | smart-d113ce63-e389-4d56-b24d-301a6d8acfe3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=719654036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.719654036 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.3282687307 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 648560383 ps |
| CPU time | 17.26 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:24 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-3fc92e8d-9fbc-446e-bf24-b829cfa67f15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3282687307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3282687307 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.63743796 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 60470301634 ps |
| CPU time | 171.67 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:35:56 PM PST 24 |
| Peak memory | 204912 kb |
| Host | smart-c8d78d30-db76-48f9-99b4-dcfac4606386 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=63743796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.63743796 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1399782442 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 27905722003 ps |
| CPU time | 182.69 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:36:07 PM PST 24 |
| Peak memory | 204788 kb |
| Host | smart-382ea12c-a472-4e31-8b5b-b84f81fe0361 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1399782442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1399782442 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3312337788 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 358148804 ps |
| CPU time | 24.27 seconds |
| Started | Jan 14 12:32:55 PM PST 24 |
| Finished | Jan 14 12:33:20 PM PST 24 |
| Peak memory | 204752 kb |
| Host | smart-18002fc9-72fd-48f0-833f-4d6c01420ef5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312337788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3312337788 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.1518926008 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1233107885 ps |
| CPU time | 17.77 seconds |
| Started | Jan 14 12:33:02 PM PST 24 |
| Finished | Jan 14 12:33:21 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-f66164f4-a666-440f-af5e-4e289170f98d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1518926008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1518926008 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1860919368 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 25402465 ps |
| CPU time | 2.27 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-af614b66-9118-4b36-a3b7-e7b2098ad9b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1860919368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1860919368 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1562129160 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 8442308856 ps |
| CPU time | 31.96 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:38 PM PST 24 |
| Peak memory | 203180 kb |
| Host | smart-90483fb6-c0ba-49d5-9ce7-7e4d56aa1909 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562129160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1562129160 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.109592660 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3619215815 ps |
| CPU time | 28.37 seconds |
| Started | Jan 14 12:32:55 PM PST 24 |
| Finished | Jan 14 12:33:24 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-a449429c-c0df-4c4d-8baa-12d638249654 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=109592660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.109592660 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1444565652 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 152472259 ps |
| CPU time | 2.35 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:33:06 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-c5af91b2-b49b-45fd-93cb-69d233202c92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444565652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1444565652 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.1358050987 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1889961220 ps |
| CPU time | 134.37 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:35:21 PM PST 24 |
| Peak memory | 205880 kb |
| Host | smart-53899fc9-acc9-4012-a2fd-b9cfd46793f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1358050987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1358050987 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3782493521 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 714433003 ps |
| CPU time | 63.85 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:34:02 PM PST 24 |
| Peak memory | 205100 kb |
| Host | smart-a061bd99-2593-47f8-bcc2-1b9e481166dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3782493521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3782493521 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.4203599339 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12158692324 ps |
| CPU time | 549.5 seconds |
| Started | Jan 14 12:33:07 PM PST 24 |
| Finished | Jan 14 12:42:17 PM PST 24 |
| Peak memory | 221824 kb |
| Host | smart-630acc1d-3960-47b1-b508-9d418357a483 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4203599339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.4203599339 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3037681944 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4931883648 ps |
| CPU time | 237.4 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:37:04 PM PST 24 |
| Peak memory | 220068 kb |
| Host | smart-859fde96-9464-48bd-bc5a-78b8e761adae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3037681944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.3037681944 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3148695760 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 78258211 ps |
| CPU time | 2.24 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:09 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-830bbe73-2bf1-40d0-97e6-f2169f0ee79f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3148695760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3148695760 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.1050268883 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 138935005 ps |
| CPU time | 5.03 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:33:05 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-0575bda4-dcc9-4598-8040-d11c1873aa4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1050268883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1050268883 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1949169985 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 23133406072 ps |
| CPU time | 237.18 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:36:57 PM PST 24 |
| Peak memory | 206492 kb |
| Host | smart-12970534-005c-4e4f-ac3e-c6a2ec2b0923 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1949169985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1949169985 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1075587742 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3153414486 ps |
| CPU time | 28.25 seconds |
| Started | Jan 14 12:33:02 PM PST 24 |
| Finished | Jan 14 12:33:30 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-5ca5b8bc-103d-4792-b1d6-14ac6b6aa4da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1075587742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1075587742 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.2112188158 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 584953227 ps |
| CPU time | 24.24 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:33:33 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-5ebc4f4d-2b8c-4a8b-a89b-d563f53c64d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2112188158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2112188158 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.713014172 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 2175825129 ps |
| CPU time | 37.44 seconds |
| Started | Jan 14 12:32:56 PM PST 24 |
| Finished | Jan 14 12:33:35 PM PST 24 |
| Peak memory | 212028 kb |
| Host | smart-8fa1cd70-7ad8-4745-a662-3a66bc4faa13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=713014172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.713014172 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.2801996727 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 11821907970 ps |
| CPU time | 33.08 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 204308 kb |
| Host | smart-865681e1-7eb8-44b4-a4cd-90db1bdbe5db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801996727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2801996727 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1711935139 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 40822724428 ps |
| CPU time | 225.72 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:36:50 PM PST 24 |
| Peak memory | 205292 kb |
| Host | smart-d86e8b72-f0a0-4aa2-887e-83268ace0d5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1711935139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1711935139 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.1691760041 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 107731786 ps |
| CPU time | 6.6 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:13 PM PST 24 |
| Peak memory | 211804 kb |
| Host | smart-7fced824-0958-4ef8-9cf7-b20f0486f383 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691760041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1691760041 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.3443168777 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 358420805 ps |
| CPU time | 7.44 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:14 PM PST 24 |
| Peak memory | 203336 kb |
| Host | smart-6a862b22-f7c8-4858-a13a-46e61b76ac19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3443168777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3443168777 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.853707511 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 169339698 ps |
| CPU time | 3.28 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:10 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-5535a6ce-0858-4578-8f35-46b5aa16d660 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=853707511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.853707511 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2765368414 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 10802394928 ps |
| CPU time | 30.82 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:33:31 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-9810630c-e865-497b-869f-9a6980f8ca29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765368414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2765368414 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.531711253 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3700752558 ps |
| CPU time | 30.73 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:37 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-68338956-84a4-49f0-8284-51d9e305ed6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=531711253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.531711253 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1827770358 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 31381124 ps |
| CPU time | 2.46 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:08 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-9c37d205-2701-4861-9651-249f29afd5dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827770358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1827770358 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.710974854 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 674263413 ps |
| CPU time | 73.3 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:34:22 PM PST 24 |
| Peak memory | 205812 kb |
| Host | smart-0ea20c27-ee8d-47d7-80a5-98ed4f3248e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=710974854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.710974854 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2261804157 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 6220104873 ps |
| CPU time | 84.28 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:34:24 PM PST 24 |
| Peak memory | 206692 kb |
| Host | smart-c21e5e02-7853-44e4-9e79-9dc2e40d2842 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2261804157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2261804157 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1800484039 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 11233297727 ps |
| CPU time | 219.71 seconds |
| Started | Jan 14 12:33:04 PM PST 24 |
| Finished | Jan 14 12:36:45 PM PST 24 |
| Peak memory | 210056 kb |
| Host | smart-d031b19f-9365-4004-a11f-9bf669d6b5f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1800484039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.1800484039 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1871347508 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1149322395 ps |
| CPU time | 188.16 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:36:12 PM PST 24 |
| Peak memory | 220028 kb |
| Host | smart-b2513088-1196-47da-a5e6-9d423aa8aa8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1871347508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.1871347508 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1229055840 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 280221148 ps |
| CPU time | 10.42 seconds |
| Started | Jan 14 12:33:04 PM PST 24 |
| Finished | Jan 14 12:33:16 PM PST 24 |
| Peak memory | 211856 kb |
| Host | smart-177a5250-56b3-45dc-8090-729330ccdd82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1229055840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1229055840 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2049441631 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 342719667 ps |
| CPU time | 39.81 seconds |
| Started | Jan 14 12:33:01 PM PST 24 |
| Finished | Jan 14 12:33:42 PM PST 24 |
| Peak memory | 206460 kb |
| Host | smart-55cd1126-8a88-4417-b8fb-68001bbd2776 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2049441631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2049441631 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1734562305 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 92980332544 ps |
| CPU time | 705.76 seconds |
| Started | Jan 14 12:32:57 PM PST 24 |
| Finished | Jan 14 12:44:43 PM PST 24 |
| Peak memory | 207712 kb |
| Host | smart-ed5f8a18-acca-4b71-b834-45dd970462dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1734562305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.1734562305 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1570186181 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 149938134 ps |
| CPU time | 5.85 seconds |
| Started | Jan 14 12:33:00 PM PST 24 |
| Finished | Jan 14 12:33:06 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-839d077c-5723-479e-ae0e-876f12073dd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1570186181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1570186181 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2892481910 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 252020454 ps |
| CPU time | 6.51 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:33:13 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-ca99b29b-6c44-4e91-9c13-ab8fe2bb93dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2892481910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2892481910 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.1539495207 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1276752536 ps |
| CPU time | 22.34 seconds |
| Started | Jan 14 12:33:01 PM PST 24 |
| Finished | Jan 14 12:33:24 PM PST 24 |
| Peak memory | 204744 kb |
| Host | smart-3ee89480-5403-49bb-b6a3-8eb47c22b676 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1539495207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1539495207 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2040300547 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 3024160800 ps |
| CPU time | 14.41 seconds |
| Started | Jan 14 12:33:02 PM PST 24 |
| Finished | Jan 14 12:33:18 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-c9d828ba-4197-46d9-94f9-7fd8a2cdbbe2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040300547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2040300547 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.4109505477 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 13991005556 ps |
| CPU time | 73.37 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:34:12 PM PST 24 |
| Peak memory | 204764 kb |
| Host | smart-a9727d27-ce65-41df-8ff2-edfd7ec7a74d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4109505477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4109505477 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3692204024 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 132674147 ps |
| CPU time | 17.02 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:33:26 PM PST 24 |
| Peak memory | 211824 kb |
| Host | smart-379fe43f-9b49-463c-979a-5d61e4ae8728 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692204024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3692204024 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.3322470321 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 26051034 ps |
| CPU time | 2.11 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:33:02 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-6c12f6fc-7a27-4808-b846-79db8119fd1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3322470321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3322470321 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1291248899 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 8003237584 ps |
| CPU time | 39.51 seconds |
| Started | Jan 14 12:33:01 PM PST 24 |
| Finished | Jan 14 12:33:41 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-c8ad07fb-5880-4b79-b052-1522fedf39b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291248899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1291248899 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.177598153 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 4808517476 ps |
| CPU time | 35.39 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-8e31a2ac-42ea-4480-a047-b21413b732f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=177598153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.177598153 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2137275941 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 28708188 ps |
| CPU time | 2.4 seconds |
| Started | Jan 14 12:33:01 PM PST 24 |
| Finished | Jan 14 12:33:04 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-878f83eb-00ba-43b1-9ac7-41bf33cdbb66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137275941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2137275941 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.2702508683 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 1778379119 ps |
| CPU time | 46.26 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:52 PM PST 24 |
| Peak memory | 206352 kb |
| Host | smart-786a400c-012c-4891-b2e2-f762ed922e77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2702508683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2702508683 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1620697020 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 813065639 ps |
| CPU time | 20.44 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:27 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-8799bf65-739c-4371-8eda-6b9c4420779e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1620697020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1620697020 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2650178202 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 18084947 ps |
| CPU time | 26.77 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:33:26 PM PST 24 |
| Peak memory | 211812 kb |
| Host | smart-981f4482-7c44-4c48-a9e5-ae9dd4446385 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2650178202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.2650178202 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.905086597 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 4202620512 ps |
| CPU time | 224.22 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:36:52 PM PST 24 |
| Peak memory | 211972 kb |
| Host | smart-7bbebdcd-9674-4758-85d7-dd592ffa009f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=905086597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_res et_error.905086597 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1918174752 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 477972474 ps |
| CPU time | 13.07 seconds |
| Started | Jan 14 12:33:01 PM PST 24 |
| Finished | Jan 14 12:33:15 PM PST 24 |
| Peak memory | 211764 kb |
| Host | smart-0c26a44c-54e1-454e-9770-4837f7ba6d11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1918174752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1918174752 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2665236373 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 102794931 ps |
| CPU time | 12.09 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:33:24 PM PST 24 |
| Peak memory | 204724 kb |
| Host | smart-15b6bab8-aad6-49af-847e-2e01ce92b135 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2665236373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2665236373 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.950730114 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 52274683042 ps |
| CPU time | 151.25 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:35:42 PM PST 24 |
| Peak memory | 206144 kb |
| Host | smart-18df6473-b78c-4509-a2bd-a060689c3fb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=950730114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo w_rsp.950730114 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.89135151 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 831603789 ps |
| CPU time | 22.17 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:33:30 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-b08ae8f8-4875-4047-8f0c-70b25c7c7750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=89135151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.89135151 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.2865112429 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 202690755 ps |
| CPU time | 24.54 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:33:35 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-58e47b01-4ea8-4d09-9e1a-c01e56f6db95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2865112429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2865112429 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.2623578842 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1200633917 ps |
| CPU time | 11.62 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:33:21 PM PST 24 |
| Peak memory | 211796 kb |
| Host | smart-ae290c52-618b-4881-8905-6ca7551bea0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2623578842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2623578842 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.2170269870 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 26889181363 ps |
| CPU time | 216.61 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:36:41 PM PST 24 |
| Peak memory | 211924 kb |
| Host | smart-a4e41c2f-0075-4b95-b7c5-0867f8450b33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2170269870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2170269870 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2656816274 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 55584813 ps |
| CPU time | 6.56 seconds |
| Started | Jan 14 12:33:02 PM PST 24 |
| Finished | Jan 14 12:33:10 PM PST 24 |
| Peak memory | 204752 kb |
| Host | smart-a437bfa1-e81d-4d3a-ac72-610397630209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656816274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2656816274 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.4069211544 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 165987025 ps |
| CPU time | 11.42 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:33:11 PM PST 24 |
| Peak memory | 204028 kb |
| Host | smart-284b051f-7f8b-4db2-a8ea-4a0730bbd491 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4069211544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4069211544 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.3597096829 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 262989433 ps |
| CPU time | 3.95 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:33:08 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-55f02a86-467d-4b50-9389-46796775f004 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3597096829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3597096829 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2874717532 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 13472023799 ps |
| CPU time | 34.22 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:33:41 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-79754b30-e172-4384-8657-365a678de57d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874717532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2874717532 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.160910346 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 6030591087 ps |
| CPU time | 37.06 seconds |
| Started | Jan 14 12:33:00 PM PST 24 |
| Finished | Jan 14 12:33:38 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-28651543-3823-41c6-82e6-8451f67d2803 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=160910346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.160910346 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3065582981 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 65387824 ps |
| CPU time | 2.3 seconds |
| Started | Jan 14 12:33:07 PM PST 24 |
| Finished | Jan 14 12:33:10 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-0a9d745e-2ecf-4ebc-84d6-1982a2f2042b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065582981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3065582981 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.640450825 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3809845531 ps |
| CPU time | 109.51 seconds |
| Started | Jan 14 12:33:12 PM PST 24 |
| Finished | Jan 14 12:35:02 PM PST 24 |
| Peak memory | 208368 kb |
| Host | smart-45af908f-1f4a-4a86-aa86-f908a25e282f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=640450825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.640450825 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1769925486 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 146836106 ps |
| CPU time | 8.6 seconds |
| Started | Jan 14 12:33:04 PM PST 24 |
| Finished | Jan 14 12:33:14 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-bce9b788-fe44-40d8-bc42-68b8de228273 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1769925486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1769925486 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1529088005 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 12565314381 ps |
| CPU time | 324.78 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:38:31 PM PST 24 |
| Peak memory | 211888 kb |
| Host | smart-92f9046f-8e77-44ca-b9c3-4a17f7245c2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1529088005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.1529088005 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3091991571 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 400124717 ps |
| CPU time | 155.21 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:35:41 PM PST 24 |
| Peak memory | 211240 kb |
| Host | smart-bc457ef2-d00e-40e2-8946-cd97ed0c6a95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3091991571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.3091991571 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.3030997346 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1182178291 ps |
| CPU time | 30.64 seconds |
| Started | Jan 14 12:33:07 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-8efe4132-ea60-4f7f-a97d-9066d7182e44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3030997346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3030997346 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.1400596004 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 6677964989 ps |
| CPU time | 62.43 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:34:14 PM PST 24 |
| Peak memory | 205672 kb |
| Host | smart-ef1e7658-8a64-48e2-973a-d17052e0c7df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1400596004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1400596004 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1056559755 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 50993816086 ps |
| CPU time | 490.35 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:41:25 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-2d8aa7a9-e8df-40f6-9808-4c5944c2482f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1056559755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.1056559755 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2558281098 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 494337624 ps |
| CPU time | 10.47 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:17 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-9b762337-f693-471c-8b23-7861de02745c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2558281098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2558281098 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.191303466 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 57418645 ps |
| CPU time | 3.16 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:33:17 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-fb400be8-7a52-4684-a261-ed133973513b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=191303466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.191303466 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.409286694 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 652928807 ps |
| CPU time | 8.63 seconds |
| Started | Jan 14 12:33:14 PM PST 24 |
| Finished | Jan 14 12:33:23 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-11ec59d0-4d36-4d70-a4ab-4c38e30f8eb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=409286694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.409286694 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3973178914 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5979836832 ps |
| CPU time | 24.58 seconds |
| Started | Jan 14 12:33:14 PM PST 24 |
| Finished | Jan 14 12:33:40 PM PST 24 |
| Peak memory | 204316 kb |
| Host | smart-041182e1-fbc7-4137-8420-d6bd50ffaa40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973178914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3973178914 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3615467615 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 19402227962 ps |
| CPU time | 82.17 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:34:34 PM PST 24 |
| Peak memory | 211876 kb |
| Host | smart-6b2de00c-1895-4683-8c23-fab3301f0277 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3615467615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3615467615 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3304766611 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 482246868 ps |
| CPU time | 10.8 seconds |
| Started | Jan 14 12:33:14 PM PST 24 |
| Finished | Jan 14 12:33:26 PM PST 24 |
| Peak memory | 204300 kb |
| Host | smart-1696be53-1a15-4e6e-b1f2-944bc497c7ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304766611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3304766611 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.3991889497 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 200755285 ps |
| CPU time | 7.5 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:33:22 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-d5c75d65-7d56-4431-97fc-366669fda475 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3991889497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3991889497 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.77574918 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 33813172 ps |
| CPU time | 2.31 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 203628 kb |
| Host | smart-920b6e73-be70-4a2c-9678-1a42bf642ba2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=77574918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.77574918 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3712388670 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 5279524309 ps |
| CPU time | 22.48 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:33:34 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-ac8cf94d-4c57-4f5f-bcdd-0fb42795f92b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712388670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3712388670 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2830562073 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 7931321096 ps |
| CPU time | 36.68 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:33:48 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-dd1d53b0-1fc0-4add-b749-2748c07ed1b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2830562073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2830562073 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1983399314 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 118385486 ps |
| CPU time | 2.22 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:33:13 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-eb8e99be-73c0-4605-85b3-2e8f73a4639d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983399314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1983399314 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2864921682 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 704502698 ps |
| CPU time | 52.11 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:34:02 PM PST 24 |
| Peak memory | 206296 kb |
| Host | smart-99b4a8d0-9611-4681-8704-07c92c893975 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2864921682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2864921682 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1516983435 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 8954785510 ps |
| CPU time | 269.82 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:37:41 PM PST 24 |
| Peak memory | 207080 kb |
| Host | smart-529bf9a7-fbcd-429f-89ca-0641e2c899a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1516983435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1516983435 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3613193039 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 705286608 ps |
| CPU time | 210.34 seconds |
| Started | Jan 14 12:33:16 PM PST 24 |
| Finished | Jan 14 12:36:47 PM PST 24 |
| Peak memory | 208572 kb |
| Host | smart-ad67dee7-0e9b-41af-a100-b737b071ee33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3613193039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.3613193039 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.4087065614 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1122599361 ps |
| CPU time | 159.06 seconds |
| Started | Jan 14 12:33:16 PM PST 24 |
| Finished | Jan 14 12:35:56 PM PST 24 |
| Peak memory | 208116 kb |
| Host | smart-e1aef510-0953-4160-8f44-7bc9ec90f149 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4087065614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.4087065614 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.1797002341 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1041238203 ps |
| CPU time | 25.34 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 211796 kb |
| Host | smart-07bbfe2b-03cd-4720-8246-9478f736a332 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1797002341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1797002341 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2878349517 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 209315745 ps |
| CPU time | 7.09 seconds |
| Started | Jan 14 12:33:12 PM PST 24 |
| Finished | Jan 14 12:33:20 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-b3a9014b-673b-4b04-88d1-95e013ebaba8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2878349517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2878349517 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1157289832 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 20996793109 ps |
| CPU time | 192.11 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:36:22 PM PST 24 |
| Peak memory | 206328 kb |
| Host | smart-b48c814b-20b6-44ff-b508-356509315c8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1157289832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.1157289832 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.157897199 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 668225906 ps |
| CPU time | 15.81 seconds |
| Started | Jan 14 12:33:27 PM PST 24 |
| Finished | Jan 14 12:33:43 PM PST 24 |
| Peak memory | 204064 kb |
| Host | smart-0342472a-459d-4423-b41b-81d5084b4f8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=157897199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.157897199 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.3622277095 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 59461828 ps |
| CPU time | 7.25 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:33:21 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-b0c1b1b2-9584-4691-96e3-956016a832b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3622277095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3622277095 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.2693744666 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 113747508 ps |
| CPU time | 13.01 seconds |
| Started | Jan 14 12:33:17 PM PST 24 |
| Finished | Jan 14 12:33:31 PM PST 24 |
| Peak memory | 211900 kb |
| Host | smart-a5438ca8-d60f-4ee1-b2d4-7402a9d4b6dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2693744666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2693744666 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.3122317471 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 17818871484 ps |
| CPU time | 49.88 seconds |
| Started | Jan 14 12:33:17 PM PST 24 |
| Finished | Jan 14 12:34:07 PM PST 24 |
| Peak memory | 211884 kb |
| Host | smart-dc7408bb-28fb-4312-be8a-2930cac8aaf4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122317471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3122317471 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.372783207 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 27696453010 ps |
| CPU time | 116.22 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:35:11 PM PST 24 |
| Peak memory | 204824 kb |
| Host | smart-1728eb8c-5da5-424d-8fb9-bcb1a02c1260 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=372783207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.372783207 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1963533030 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1018933360 ps |
| CPU time | 23.34 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:33:32 PM PST 24 |
| Peak memory | 211884 kb |
| Host | smart-bb10bc9d-2754-4f76-ac91-c2bb3b827d5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963533030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1963533030 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1706101094 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 837942498 ps |
| CPU time | 6.41 seconds |
| Started | Jan 14 12:33:16 PM PST 24 |
| Finished | Jan 14 12:33:23 PM PST 24 |
| Peak memory | 203888 kb |
| Host | smart-266c90a3-c8d2-4ca2-a4d5-5636cb046cb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1706101094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1706101094 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.1271495570 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 115956144 ps |
| CPU time | 3.17 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:33:08 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-5c723943-37d7-4cac-91b5-247181a09f12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1271495570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1271495570 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.4139632578 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 5991672081 ps |
| CPU time | 33.06 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-412ac77f-dd97-425f-ba54-557f4d1613d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139632578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.4139632578 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1022457233 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 18687331184 ps |
| CPU time | 44.32 seconds |
| Started | Jan 14 12:33:03 PM PST 24 |
| Finished | Jan 14 12:33:49 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-e7b4fd8f-71db-481d-bff6-fb9fdb61e43a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1022457233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1022457233 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.4012786283 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 46649869 ps |
| CPU time | 2.05 seconds |
| Started | Jan 14 12:33:04 PM PST 24 |
| Finished | Jan 14 12:33:07 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-3f2d051c-d03d-442f-aebe-4206f5761eb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012786283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.4012786283 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.2686951452 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 420406116 ps |
| CPU time | 58.89 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:34:05 PM PST 24 |
| Peak memory | 206944 kb |
| Host | smart-7fba94a2-332c-489f-90f6-bebc8d02495c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2686951452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2686951452 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1532081378 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 3092726155 ps |
| CPU time | 190.8 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:36:24 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-f01c7f95-4660-4ab0-9634-40fe6d141318 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1532081378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1532081378 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3804763182 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2757278822 ps |
| CPU time | 112.64 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:35:04 PM PST 24 |
| Peak memory | 207192 kb |
| Host | smart-7f36ed30-6484-4f2f-8d13-75adc5fc57da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3804763182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.3804763182 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3261761797 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2012002515 ps |
| CPU time | 32.85 seconds |
| Started | Jan 14 12:33:27 PM PST 24 |
| Finished | Jan 14 12:34:00 PM PST 24 |
| Peak memory | 211916 kb |
| Host | smart-ca17ccd7-2cc1-4948-994d-90a9251d4f58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3261761797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3261761797 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.4182031531 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2769810334 ps |
| CPU time | 47.2 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:34:00 PM PST 24 |
| Peak memory | 206192 kb |
| Host | smart-ecd03311-ad56-433d-991b-4e0b0303d9ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4182031531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.4182031531 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1547092921 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 368091247509 ps |
| CPU time | 660.07 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:44:13 PM PST 24 |
| Peak memory | 207252 kb |
| Host | smart-f60b3698-01df-419a-b2cf-882b88f4819d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1547092921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.1547092921 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.4012008815 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 756128668 ps |
| CPU time | 21.84 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:33:29 PM PST 24 |
| Peak memory | 203992 kb |
| Host | smart-c7c5d3ae-461a-4621-a349-14a08689e0ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4012008815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.4012008815 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.672487850 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1030987363 ps |
| CPU time | 20.15 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:33:31 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-c50d8540-d366-4bee-9e6b-9952d4f1bf98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=672487850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.672487850 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.979386813 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 138364791 ps |
| CPU time | 18.41 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:33:19 PM PST 24 |
| Peak memory | 204264 kb |
| Host | smart-37ee1227-13ab-4d0f-b6f3-65e05ab9d754 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=979386813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.979386813 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.3407384178 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 29388647348 ps |
| CPU time | 63.73 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:34:10 PM PST 24 |
| Peak memory | 204916 kb |
| Host | smart-60298282-834f-444e-9908-4ff7d528ba19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407384178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3407384178 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2149471478 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 76006177454 ps |
| CPU time | 260.72 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:37:31 PM PST 24 |
| Peak memory | 211840 kb |
| Host | smart-87dd7397-ad8a-4017-b5ac-0d459a37efea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2149471478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2149471478 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.735351177 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 129573161 ps |
| CPU time | 16.73 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:33:29 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-bc1fd48e-5f45-4aa0-96c9-f4733b2dd032 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735351177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.735351177 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.29886214 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 607386325 ps |
| CPU time | 10.47 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:16 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-4d06e5b3-6e8c-4a2c-844e-33883a578249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=29886214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.29886214 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.2990634890 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 119052714 ps |
| CPU time | 3.02 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:33:17 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-29f753c8-e751-4477-9e50-74de03539dd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2990634890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2990634890 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.265553219 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 7938291058 ps |
| CPU time | 29.07 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-c918e07c-d85a-46dc-ba20-f2194a19317b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=265553219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.265553219 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2520789426 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 10908553463 ps |
| CPU time | 38.67 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:33:53 PM PST 24 |
| Peak memory | 204048 kb |
| Host | smart-aeb31c3b-6a19-4ae8-a11a-ce3dba880bd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2520789426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2520789426 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1968837515 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 34265487 ps |
| CPU time | 2.13 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:33:10 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-6f879534-0d85-48ba-8ee8-52a88cdd7f4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968837515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1968837515 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1123516489 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2030931678 ps |
| CPU time | 164.36 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:35:56 PM PST 24 |
| Peak memory | 211812 kb |
| Host | smart-03ee987d-bfa5-449e-ada9-21156b3eebdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1123516489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1123516489 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1904903284 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 9700892076 ps |
| CPU time | 217.33 seconds |
| Started | Jan 14 12:33:14 PM PST 24 |
| Finished | Jan 14 12:36:52 PM PST 24 |
| Peak memory | 210288 kb |
| Host | smart-7c9dbd15-9a91-4867-bd35-fa80e7c4938d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1904903284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1904903284 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.182714181 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 22718476 ps |
| CPU time | 30.1 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:33:42 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-ddab80f8-4e9d-462d-acb1-f4dd11541b3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=182714181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand _reset.182714181 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.229269454 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 22580129 ps |
| CPU time | 30.24 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:36 PM PST 24 |
| Peak memory | 206308 kb |
| Host | smart-188708fb-c890-4fc5-ade8-af84e2a3a869 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=229269454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res et_error.229269454 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2137646424 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 956621573 ps |
| CPU time | 32.33 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:33:43 PM PST 24 |
| Peak memory | 211812 kb |
| Host | smart-d81b32e3-227c-4a34-9c32-5b64f7b18501 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2137646424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2137646424 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.579398052 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1690451732 ps |
| CPU time | 48.43 seconds |
| Started | Jan 14 12:32:24 PM PST 24 |
| Finished | Jan 14 12:33:14 PM PST 24 |
| Peak memory | 211904 kb |
| Host | smart-675d5aa7-6445-449d-95ed-7ffebae17212 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=579398052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.579398052 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1906133697 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 36292808986 ps |
| CPU time | 164.84 seconds |
| Started | Jan 14 12:32:31 PM PST 24 |
| Finished | Jan 14 12:35:17 PM PST 24 |
| Peak memory | 206320 kb |
| Host | smart-a534dc26-ffe2-4bf7-8547-5c8eb1f8874a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1906133697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.1906133697 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.4073980963 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 254964255 ps |
| CPU time | 4.46 seconds |
| Started | Jan 14 12:32:32 PM PST 24 |
| Finished | Jan 14 12:32:37 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-f624c27c-a22d-4cfb-b2c7-7a07971a8763 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4073980963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.4073980963 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.2228882367 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 192450314 ps |
| CPU time | 15.69 seconds |
| Started | Jan 14 12:32:39 PM PST 24 |
| Finished | Jan 14 12:33:00 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-bc7473e0-f327-4804-88c0-33352583e8df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2228882367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2228882367 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.3353658540 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 258801857 ps |
| CPU time | 9.05 seconds |
| Started | Jan 14 12:32:22 PM PST 24 |
| Finished | Jan 14 12:32:34 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-1cf48460-3e9a-490e-aa9b-cb28fa0091a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3353658540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3353658540 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3801386409 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 14234900680 ps |
| CPU time | 63.29 seconds |
| Started | Jan 14 12:32:31 PM PST 24 |
| Finished | Jan 14 12:33:35 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-10675121-3d41-4f28-a111-e24eb891d944 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801386409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3801386409 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.603147070 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 6973465204 ps |
| CPU time | 53.73 seconds |
| Started | Jan 14 12:32:22 PM PST 24 |
| Finished | Jan 14 12:33:18 PM PST 24 |
| Peak memory | 211948 kb |
| Host | smart-a51259a2-0374-48b2-8b00-5c99e1f11234 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=603147070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.603147070 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.1647075120 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 387670693 ps |
| CPU time | 21.7 seconds |
| Started | Jan 14 12:32:16 PM PST 24 |
| Finished | Jan 14 12:32:39 PM PST 24 |
| Peak memory | 204908 kb |
| Host | smart-cfd8d587-a76b-4ec4-9d75-6e03e83477d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647075120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1647075120 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.1844520733 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 129223858 ps |
| CPU time | 8.76 seconds |
| Started | Jan 14 12:32:24 PM PST 24 |
| Finished | Jan 14 12:32:34 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-1a1be742-9221-43a4-861b-ddc07ef8d6c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1844520733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1844520733 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.2817912327 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 405403262 ps |
| CPU time | 3.49 seconds |
| Started | Jan 14 12:32:20 PM PST 24 |
| Finished | Jan 14 12:32:28 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-3c78c65f-8053-4ee5-9d9d-213cf50acf56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2817912327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2817912327 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3792022255 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3967995599 ps |
| CPU time | 24.64 seconds |
| Started | Jan 14 12:32:31 PM PST 24 |
| Finished | Jan 14 12:32:57 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-8e126689-7298-4c26-9a32-5bc1f8841ca5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792022255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3792022255 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.416924372 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4930171248 ps |
| CPU time | 32.04 seconds |
| Started | Jan 14 12:32:18 PM PST 24 |
| Finished | Jan 14 12:32:56 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-0f8d8cee-c573-4730-8eb0-abd6d271a913 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=416924372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.416924372 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3918773458 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 29348441 ps |
| CPU time | 2.52 seconds |
| Started | Jan 14 12:32:28 PM PST 24 |
| Finished | Jan 14 12:32:31 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-37533109-f4f1-495c-8efa-08e3a216297e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918773458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3918773458 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.1347777349 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 9451502870 ps |
| CPU time | 236.04 seconds |
| Started | Jan 14 12:32:23 PM PST 24 |
| Finished | Jan 14 12:36:21 PM PST 24 |
| Peak memory | 208940 kb |
| Host | smart-4fafe29e-e540-4635-8f6c-ca2848249ec4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1347777349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1347777349 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3888833217 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 786524557 ps |
| CPU time | 57.93 seconds |
| Started | Jan 14 12:32:22 PM PST 24 |
| Finished | Jan 14 12:33:22 PM PST 24 |
| Peak memory | 206256 kb |
| Host | smart-dcfadea6-def0-468f-96f6-22c005bd68cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3888833217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3888833217 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2823639879 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 553154442 ps |
| CPU time | 220.42 seconds |
| Started | Jan 14 12:32:33 PM PST 24 |
| Finished | Jan 14 12:36:14 PM PST 24 |
| Peak memory | 209084 kb |
| Host | smart-20a3ab0d-537d-4bd9-bf5d-dbb79c1f3560 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2823639879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.2823639879 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3989976458 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1208619891 ps |
| CPU time | 271.8 seconds |
| Started | Jan 14 12:32:29 PM PST 24 |
| Finished | Jan 14 12:37:02 PM PST 24 |
| Peak memory | 220036 kb |
| Host | smart-fea9464f-b146-417f-8dbc-2c55dd8883f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3989976458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3989976458 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.3462353095 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 90892406 ps |
| CPU time | 11.11 seconds |
| Started | Jan 14 12:32:29 PM PST 24 |
| Finished | Jan 14 12:32:41 PM PST 24 |
| Peak memory | 204816 kb |
| Host | smart-a8cfe5c6-c51d-46bd-9886-526c56bc3b04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3462353095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3462353095 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.3018639674 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 731685890 ps |
| CPU time | 17.38 seconds |
| Started | Jan 14 12:33:17 PM PST 24 |
| Finished | Jan 14 12:33:35 PM PST 24 |
| Peak memory | 204164 kb |
| Host | smart-29606802-0ee6-4249-9275-bd6cd7394e90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3018639674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.3018639674 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1868077791 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 916080001 ps |
| CPU time | 13.31 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:33:25 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-00958521-935d-4f9f-add1-5de86f402d19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1868077791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1868077791 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.780708553 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2125519401 ps |
| CPU time | 36.63 seconds |
| Started | Jan 14 12:33:16 PM PST 24 |
| Finished | Jan 14 12:33:53 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-dda885a1-6d99-453a-8dc8-4673b0375743 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=780708553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.780708553 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.3217600746 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1134544018 ps |
| CPU time | 30.95 seconds |
| Started | Jan 14 12:33:14 PM PST 24 |
| Finished | Jan 14 12:33:46 PM PST 24 |
| Peak memory | 211848 kb |
| Host | smart-4093f140-6742-430e-ab49-c779d43d2cb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3217600746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3217600746 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.3084340414 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 17106821623 ps |
| CPU time | 75.28 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:34:29 PM PST 24 |
| Peak memory | 211832 kb |
| Host | smart-6ff8a091-bea6-4ccd-a682-73111ffeff6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084340414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3084340414 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3411490746 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 36525441554 ps |
| CPU time | 280.13 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:37:52 PM PST 24 |
| Peak memory | 205176 kb |
| Host | smart-70df3b37-b752-4993-b15e-b699de4373f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3411490746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3411490746 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.1841905631 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 102475493 ps |
| CPU time | 12.11 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:33:26 PM PST 24 |
| Peak memory | 211768 kb |
| Host | smart-db7588a6-abc9-4bf5-bb99-4d2e4470f3c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841905631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1841905631 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.3886749368 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 696880820 ps |
| CPU time | 10.04 seconds |
| Started | Jan 14 12:33:16 PM PST 24 |
| Finished | Jan 14 12:33:27 PM PST 24 |
| Peak memory | 204092 kb |
| Host | smart-e703c486-ae71-4ecf-816a-1fd0019f7168 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3886749368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3886749368 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2055213767 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 208228120 ps |
| CPU time | 3.72 seconds |
| Started | Jan 14 12:33:14 PM PST 24 |
| Finished | Jan 14 12:33:19 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-1d1d3c52-c399-4b37-bbd3-28d336b85d0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2055213767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2055213767 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.305321807 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 26184372570 ps |
| CPU time | 41.68 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:33:50 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-1fd47b65-e042-4d2c-bddc-ecbaed075ad1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=305321807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.305321807 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3885629528 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 4114872086 ps |
| CPU time | 29.86 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:33:42 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-7d4e3557-ffad-4f77-a4e0-155099d5d40b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3885629528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3885629528 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2520710503 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 38070319 ps |
| CPU time | 2.23 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-72e1960a-7a36-4ce3-bced-059a1a892cec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520710503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2520710503 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1569486616 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 15005594175 ps |
| CPU time | 342.12 seconds |
| Started | Jan 14 12:33:16 PM PST 24 |
| Finished | Jan 14 12:38:59 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-dde22c9d-cf65-459e-84cf-4eb8bf6545b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1569486616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1569486616 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2253142634 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 23914702544 ps |
| CPU time | 328.6 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:38:39 PM PST 24 |
| Peak memory | 207532 kb |
| Host | smart-d68c85e7-fbe9-4800-919d-bc8a49a624a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2253142634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2253142634 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2210785862 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 449954423 ps |
| CPU time | 110.84 seconds |
| Started | Jan 14 12:33:17 PM PST 24 |
| Finished | Jan 14 12:35:08 PM PST 24 |
| Peak memory | 206848 kb |
| Host | smart-47a22526-235e-4ac8-b61a-7d81a53268f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2210785862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.2210785862 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.715799794 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 739868957 ps |
| CPU time | 162.21 seconds |
| Started | Jan 14 12:33:17 PM PST 24 |
| Finished | Jan 14 12:36:00 PM PST 24 |
| Peak memory | 211080 kb |
| Host | smart-33716b45-88d8-4315-a709-408c8bb4c095 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=715799794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res et_error.715799794 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1390290510 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 13322156 ps |
| CPU time | 1.78 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:33:13 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-0d03efed-c864-461d-af9b-587c21974720 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1390290510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1390290510 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3709054396 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 193499688 ps |
| CPU time | 4.01 seconds |
| Started | Jan 14 12:33:06 PM PST 24 |
| Finished | Jan 14 12:33:11 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-cd1bf663-bc77-4cd1-9e24-0d85e228a07a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3709054396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3709054396 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3417797316 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 122959072951 ps |
| CPU time | 485.01 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:41:15 PM PST 24 |
| Peak memory | 211884 kb |
| Host | smart-25dcc814-ab6a-48fc-8b92-06719233ed48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3417797316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.3417797316 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2056291049 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1057864281 ps |
| CPU time | 23.2 seconds |
| Started | Jan 14 12:33:12 PM PST 24 |
| Finished | Jan 14 12:33:36 PM PST 24 |
| Peak memory | 204000 kb |
| Host | smart-d153619a-bcc3-49be-a9c5-7b147da4f044 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2056291049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2056291049 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.2962183602 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 964354691 ps |
| CPU time | 26.58 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:33:38 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-f38029a1-a697-4300-a4b6-2756eba7f09c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2962183602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2962183602 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.1333904457 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1178197098 ps |
| CPU time | 39.58 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:33:54 PM PST 24 |
| Peak memory | 211824 kb |
| Host | smart-8bc261ce-6fc5-4b76-a28f-e36d32a41d1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1333904457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1333904457 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3838166723 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 86002877879 ps |
| CPU time | 153.19 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:35:46 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-42b47e1a-2338-40b3-b0a5-83f8d7d86d32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838166723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3838166723 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1452948125 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 92696553364 ps |
| CPU time | 162.56 seconds |
| Started | Jan 14 12:33:27 PM PST 24 |
| Finished | Jan 14 12:36:11 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-68827d24-d5f3-4bb2-acb9-e6dcc56b9602 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1452948125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1452948125 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3944857682 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 307544703 ps |
| CPU time | 26.32 seconds |
| Started | Jan 14 12:33:27 PM PST 24 |
| Finished | Jan 14 12:33:54 PM PST 24 |
| Peak memory | 204080 kb |
| Host | smart-c4f3d65a-655e-4874-a5cd-b5d09dc5542d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944857682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3944857682 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.3020181742 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 689380020 ps |
| CPU time | 4.86 seconds |
| Started | Jan 14 12:33:12 PM PST 24 |
| Finished | Jan 14 12:33:18 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-5d1fae6d-c921-49fd-9de8-ebd8ecbdf3a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3020181742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3020181742 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.1464343540 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 276143271 ps |
| CPU time | 3.6 seconds |
| Started | Jan 14 12:33:05 PM PST 24 |
| Finished | Jan 14 12:33:10 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-b08dd1d4-1b9d-449f-9464-57a5923fedee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1464343540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1464343540 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.393471031 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 15420278934 ps |
| CPU time | 36.78 seconds |
| Started | Jan 14 12:33:27 PM PST 24 |
| Finished | Jan 14 12:34:05 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-a1c42278-ddb1-426f-be30-0c706e0c0c71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=393471031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.393471031 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1982814591 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4168367419 ps |
| CPU time | 29.88 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:33:40 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-faff7a1f-af8d-4789-b843-c4c4be662768 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1982814591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1982814591 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2243403173 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 33018511 ps |
| CPU time | 2.25 seconds |
| Started | Jan 14 12:33:09 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-d6e87c0e-5daa-4f51-8f18-fd739d8fa6d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243403173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2243403173 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.724263052 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 468033498 ps |
| CPU time | 41.21 seconds |
| Started | Jan 14 12:33:16 PM PST 24 |
| Finished | Jan 14 12:33:58 PM PST 24 |
| Peak memory | 205348 kb |
| Host | smart-9b5c6963-39ef-43c6-ae64-514a4f274e4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=724263052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.724263052 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2627501052 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 475720774 ps |
| CPU time | 39.27 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:33:51 PM PST 24 |
| Peak memory | 204380 kb |
| Host | smart-b7d2c583-5692-4a8d-827b-586ca7ca184d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2627501052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2627501052 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2662629219 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5018080475 ps |
| CPU time | 285.66 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:37:57 PM PST 24 |
| Peak memory | 210132 kb |
| Host | smart-84aa67bb-0ef2-4704-90cf-4a370bd623c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662629219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.2662629219 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1362048161 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 6676046976 ps |
| CPU time | 297.02 seconds |
| Started | Jan 14 12:33:11 PM PST 24 |
| Finished | Jan 14 12:38:10 PM PST 24 |
| Peak memory | 220164 kb |
| Host | smart-a837dc6b-1831-4e7d-ac5e-42cc172dad01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1362048161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.1362048161 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1767057853 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1509451496 ps |
| CPU time | 31.19 seconds |
| Started | Jan 14 12:33:12 PM PST 24 |
| Finished | Jan 14 12:33:44 PM PST 24 |
| Peak memory | 205372 kb |
| Host | smart-a256b1a2-1603-4842-bdac-45486d4d5fd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1767057853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1767057853 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.3270979372 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 287763520 ps |
| CPU time | 24.86 seconds |
| Started | Jan 14 12:33:25 PM PST 24 |
| Finished | Jan 14 12:33:51 PM PST 24 |
| Peak memory | 204412 kb |
| Host | smart-c527e126-bbe2-4dc4-b1ed-21b6d041ab30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3270979372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3270979372 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2515825643 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 218196273 ps |
| CPU time | 14.03 seconds |
| Started | Jan 14 12:33:20 PM PST 24 |
| Finished | Jan 14 12:33:35 PM PST 24 |
| Peak memory | 204012 kb |
| Host | smart-13c458ff-e4d4-497c-8b5b-19d487bcf990 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2515825643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2515825643 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.3185143200 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 85120701 ps |
| CPU time | 10.22 seconds |
| Started | Jan 14 12:33:25 PM PST 24 |
| Finished | Jan 14 12:33:36 PM PST 24 |
| Peak memory | 203576 kb |
| Host | smart-efd9063d-6b21-461e-a634-5a7e9e051959 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3185143200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3185143200 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.1767626104 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 669012046 ps |
| CPU time | 25.58 seconds |
| Started | Jan 14 12:33:12 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 204376 kb |
| Host | smart-c0d972bd-4feb-4ed5-a983-f666d82aa061 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1767626104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1767626104 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3682880698 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 26848927219 ps |
| CPU time | 60.19 seconds |
| Started | Jan 14 12:33:14 PM PST 24 |
| Finished | Jan 14 12:34:15 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-b64382f5-6e7b-46ec-920c-49e029efff0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682880698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3682880698 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3197837671 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 51151036681 ps |
| CPU time | 204 seconds |
| Started | Jan 14 12:33:18 PM PST 24 |
| Finished | Jan 14 12:36:43 PM PST 24 |
| Peak memory | 211848 kb |
| Host | smart-8e2b6520-5858-4503-9979-d34942619317 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3197837671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3197837671 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.2516706792 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 162759941 ps |
| CPU time | 5.88 seconds |
| Started | Jan 14 12:33:13 PM PST 24 |
| Finished | Jan 14 12:33:20 PM PST 24 |
| Peak memory | 204240 kb |
| Host | smart-9357f0c5-f659-420c-bf2a-d75038a29e6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516706792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2516706792 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.2495702661 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 941761624 ps |
| CPU time | 21.77 seconds |
| Started | Jan 14 12:33:16 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 203876 kb |
| Host | smart-dfd57945-bda6-48b5-aace-84f999dbc719 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2495702661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2495702661 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.2795872579 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 130325159 ps |
| CPU time | 3.25 seconds |
| Started | Jan 14 12:33:08 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-5460a8cc-e532-4393-aec0-916b973b2402 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2795872579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2795872579 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.234981112 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 22387602024 ps |
| CPU time | 41.26 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:33:53 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-444eeca3-2b5d-48b9-8d5c-9de2b8cc5b7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=234981112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.234981112 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2209032 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 4542811667 ps |
| CPU time | 34.5 seconds |
| Started | Jan 14 12:33:10 PM PST 24 |
| Finished | Jan 14 12:33:46 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-d261be80-427d-4848-80d1-0c7e2a40bc99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2209032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2209032 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2204780741 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 31181528 ps |
| CPU time | 1.9 seconds |
| Started | Jan 14 12:33:12 PM PST 24 |
| Finished | Jan 14 12:33:15 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-63a60907-485d-4235-8b79-d2b80363dea6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204780741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2204780741 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.1527462662 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 444012196 ps |
| CPU time | 45.95 seconds |
| Started | Jan 14 12:33:17 PM PST 24 |
| Finished | Jan 14 12:34:04 PM PST 24 |
| Peak memory | 206252 kb |
| Host | smart-b989af4a-d7b8-4924-b41c-2862986caa51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1527462662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1527462662 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2676883026 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1441079857 ps |
| CPU time | 97.85 seconds |
| Started | Jan 14 12:33:16 PM PST 24 |
| Finished | Jan 14 12:34:54 PM PST 24 |
| Peak memory | 206760 kb |
| Host | smart-6a038056-f400-4ba5-8b7e-e0c60a93a34c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2676883026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2676883026 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1558550974 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 303515360 ps |
| CPU time | 57.48 seconds |
| Started | Jan 14 12:33:14 PM PST 24 |
| Finished | Jan 14 12:34:13 PM PST 24 |
| Peak memory | 206896 kb |
| Host | smart-cbbd09be-8382-4da0-ad17-87edf1d2f332 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1558550974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.1558550974 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1063831046 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2397892167 ps |
| CPU time | 119.4 seconds |
| Started | Jan 14 12:33:28 PM PST 24 |
| Finished | Jan 14 12:35:28 PM PST 24 |
| Peak memory | 209244 kb |
| Host | smart-dcd3f332-3ff7-4628-a40a-ede9c76e9911 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1063831046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.1063831046 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.2727323777 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 731024735 ps |
| CPU time | 19.27 seconds |
| Started | Jan 14 12:33:17 PM PST 24 |
| Finished | Jan 14 12:33:37 PM PST 24 |
| Peak memory | 211820 kb |
| Host | smart-4f93b31a-44c4-483d-b87a-90352063adfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2727323777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2727323777 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1662222704 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 63633045 ps |
| CPU time | 4.57 seconds |
| Started | Jan 14 12:33:18 PM PST 24 |
| Finished | Jan 14 12:33:23 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-cc380216-be51-4b97-8474-d797887d3916 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1662222704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1662222704 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3578617017 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 39177683720 ps |
| CPU time | 250.53 seconds |
| Started | Jan 14 12:33:19 PM PST 24 |
| Finished | Jan 14 12:37:31 PM PST 24 |
| Peak memory | 206548 kb |
| Host | smart-c47a4035-2020-46a2-afff-1045e1483c86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3578617017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.3578617017 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3331100946 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 632128593 ps |
| CPU time | 17.11 seconds |
| Started | Jan 14 12:33:19 PM PST 24 |
| Finished | Jan 14 12:33:36 PM PST 24 |
| Peak memory | 203968 kb |
| Host | smart-d7ec1e3b-a260-465b-bfd8-6f10b94ebf61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3331100946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3331100946 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.2267120586 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3353542497 ps |
| CPU time | 30.85 seconds |
| Started | Jan 14 12:33:17 PM PST 24 |
| Finished | Jan 14 12:33:49 PM PST 24 |
| Peak memory | 203884 kb |
| Host | smart-b6e678f2-df1a-4861-bb7d-ffec8febbe49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2267120586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2267120586 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.309454517 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 578262798 ps |
| CPU time | 12.41 seconds |
| Started | Jan 14 12:33:17 PM PST 24 |
| Finished | Jan 14 12:33:31 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-e4e75501-9d58-4b65-ae52-7fd65a706606 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=309454517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.309454517 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3214715136 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 25362322727 ps |
| CPU time | 57.24 seconds |
| Started | Jan 14 12:33:29 PM PST 24 |
| Finished | Jan 14 12:34:27 PM PST 24 |
| Peak memory | 211832 kb |
| Host | smart-bc85be53-afbe-4232-b343-ee311b3cc36e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214715136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3214715136 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.901869170 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 7068158305 ps |
| CPU time | 48.89 seconds |
| Started | Jan 14 12:33:15 PM PST 24 |
| Finished | Jan 14 12:34:05 PM PST 24 |
| Peak memory | 211900 kb |
| Host | smart-6e8bd81f-c14b-4b73-a996-81880c464b3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=901869170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.901869170 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.4179548105 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 196267850 ps |
| CPU time | 24.9 seconds |
| Started | Jan 14 12:33:18 PM PST 24 |
| Finished | Jan 14 12:33:44 PM PST 24 |
| Peak memory | 211772 kb |
| Host | smart-604f377c-aa52-48aa-bfcf-7062e1f19eb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179548105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.4179548105 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.3128013772 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 249447568 ps |
| CPU time | 3.19 seconds |
| Started | Jan 14 12:33:14 PM PST 24 |
| Finished | Jan 14 12:33:18 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-2e5b17ca-dbf1-4a9f-941f-1f5da924c200 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3128013772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3128013772 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.468459583 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 154720171 ps |
| CPU time | 3.46 seconds |
| Started | Jan 14 12:33:18 PM PST 24 |
| Finished | Jan 14 12:33:22 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-ba600cfa-6777-4a85-8cac-317f12a66649 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=468459583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.468459583 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2258835300 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 19138837593 ps |
| CPU time | 44.92 seconds |
| Started | Jan 14 12:33:18 PM PST 24 |
| Finished | Jan 14 12:34:04 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-bbcb2547-331f-43cc-b6c0-2b82d38ce243 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258835300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2258835300 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1018379201 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 9148358537 ps |
| CPU time | 43.62 seconds |
| Started | Jan 14 12:33:26 PM PST 24 |
| Finished | Jan 14 12:34:10 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-1c87c49b-0ed0-45d4-b287-0a42f0c4db84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1018379201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1018379201 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.4042923348 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 22519543 ps |
| CPU time | 1.95 seconds |
| Started | Jan 14 12:33:24 PM PST 24 |
| Finished | Jan 14 12:33:26 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-2e321a51-7907-424d-a54a-82261305ed67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042923348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.4042923348 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.1170173964 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1309755682 ps |
| CPU time | 131.42 seconds |
| Started | Jan 14 12:33:20 PM PST 24 |
| Finished | Jan 14 12:35:32 PM PST 24 |
| Peak memory | 208792 kb |
| Host | smart-235bca59-a367-4545-9771-bad07683411c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1170173964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1170173964 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.158468152 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 7576606351 ps |
| CPU time | 186.4 seconds |
| Started | Jan 14 12:33:20 PM PST 24 |
| Finished | Jan 14 12:36:27 PM PST 24 |
| Peak memory | 212000 kb |
| Host | smart-4dfcf322-12e3-47c6-a4f1-4e7ae6251230 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=158468152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.158468152 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1944469658 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1084523201 ps |
| CPU time | 213.34 seconds |
| Started | Jan 14 12:33:29 PM PST 24 |
| Finished | Jan 14 12:37:03 PM PST 24 |
| Peak memory | 208496 kb |
| Host | smart-bc678bc9-8442-4f05-96c6-aeedaa729c50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1944469658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.1944469658 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1731304756 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 306001391 ps |
| CPU time | 41.89 seconds |
| Started | Jan 14 12:33:25 PM PST 24 |
| Finished | Jan 14 12:34:08 PM PST 24 |
| Peak memory | 206460 kb |
| Host | smart-19bbd80f-60c5-4c66-bae0-af6bd3ce74b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1731304756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.1731304756 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2102416685 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 41581611 ps |
| CPU time | 2.8 seconds |
| Started | Jan 14 12:33:28 PM PST 24 |
| Finished | Jan 14 12:33:31 PM PST 24 |
| Peak memory | 204272 kb |
| Host | smart-5fa999b5-bfab-4710-9802-9b879d4434cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2102416685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2102416685 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.184290922 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1486180727 ps |
| CPU time | 51.96 seconds |
| Started | Jan 14 12:33:29 PM PST 24 |
| Finished | Jan 14 12:34:22 PM PST 24 |
| Peak memory | 211792 kb |
| Host | smart-cd0fd9aa-4421-4551-8eb8-1b1aa6cd7edd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=184290922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.184290922 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.25902171 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 51875972530 ps |
| CPU time | 226.21 seconds |
| Started | Jan 14 12:33:28 PM PST 24 |
| Finished | Jan 14 12:37:15 PM PST 24 |
| Peak memory | 206460 kb |
| Host | smart-4be3e770-30a8-4e0a-b8a8-786542246aa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=25902171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow _rsp.25902171 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3412000821 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 119263649 ps |
| CPU time | 10.41 seconds |
| Started | Jan 14 12:33:18 PM PST 24 |
| Finished | Jan 14 12:33:30 PM PST 24 |
| Peak memory | 203920 kb |
| Host | smart-53b54d95-17e6-4c3d-96ca-3cd47f7c2967 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3412000821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3412000821 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2250892819 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 482169493 ps |
| CPU time | 16.47 seconds |
| Started | Jan 14 12:33:15 PM PST 24 |
| Finished | Jan 14 12:33:32 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-b445150a-0565-4245-a8f5-feb7cf7ae3cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2250892819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2250892819 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.2655491119 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 590543122 ps |
| CPU time | 10.99 seconds |
| Started | Jan 14 12:33:27 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 211552 kb |
| Host | smart-c3c48494-e802-4b45-83a1-d87191ac53b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2655491119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2655491119 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.1607458314 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 86733327423 ps |
| CPU time | 258.63 seconds |
| Started | Jan 14 12:33:25 PM PST 24 |
| Finished | Jan 14 12:37:45 PM PST 24 |
| Peak memory | 211872 kb |
| Host | smart-fdad948d-eb0c-453f-937e-d37232eb2f2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607458314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1607458314 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.704428448 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 27142442227 ps |
| CPU time | 56.65 seconds |
| Started | Jan 14 12:33:21 PM PST 24 |
| Finished | Jan 14 12:34:18 PM PST 24 |
| Peak memory | 204840 kb |
| Host | smart-ffa85838-2f9f-4cf3-aa66-00db919cc76e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=704428448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.704428448 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3248969346 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 53778290 ps |
| CPU time | 5.7 seconds |
| Started | Jan 14 12:33:26 PM PST 24 |
| Finished | Jan 14 12:33:32 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-0cb2bea7-68e8-4cf9-bdab-7c14ce00b97a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248969346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3248969346 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.68120861 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2539927993 ps |
| CPU time | 18.76 seconds |
| Started | Jan 14 12:33:24 PM PST 24 |
| Finished | Jan 14 12:33:43 PM PST 24 |
| Peak memory | 204156 kb |
| Host | smart-4f6bd0c1-6011-4390-aa07-1d8e2ec24f9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=68120861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.68120861 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.3879448383 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 199619045 ps |
| CPU time | 3.36 seconds |
| Started | Jan 14 12:33:20 PM PST 24 |
| Finished | Jan 14 12:33:24 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-194bde89-9846-4eb1-8026-dc6a39d53cc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3879448383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3879448383 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3876671929 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4251920043 ps |
| CPU time | 26.17 seconds |
| Started | Jan 14 12:33:31 PM PST 24 |
| Finished | Jan 14 12:33:57 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-62396944-6b03-4cbb-b61b-f00869e91e0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876671929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3876671929 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3408431843 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 8732943373 ps |
| CPU time | 37.47 seconds |
| Started | Jan 14 12:33:29 PM PST 24 |
| Finished | Jan 14 12:34:07 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-e9ffd8c7-25e2-40c8-abe2-9c18c1575c6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3408431843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3408431843 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.546976656 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 40920962 ps |
| CPU time | 2.34 seconds |
| Started | Jan 14 12:33:27 PM PST 24 |
| Finished | Jan 14 12:33:30 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-50b30c7d-2a07-456b-804c-eb9682ad4968 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546976656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.546976656 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.2455576767 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2192507784 ps |
| CPU time | 64.04 seconds |
| Started | Jan 14 12:33:27 PM PST 24 |
| Finished | Jan 14 12:34:32 PM PST 24 |
| Peak memory | 211872 kb |
| Host | smart-a4ce440c-a7c0-4cca-b823-8151ecaa43d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2455576767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2455576767 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3901747177 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 11102629428 ps |
| CPU time | 207.87 seconds |
| Started | Jan 14 12:33:18 PM PST 24 |
| Finished | Jan 14 12:36:46 PM PST 24 |
| Peak memory | 209812 kb |
| Host | smart-c703e389-27ec-4db4-991e-62cb4c3f3ef4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3901747177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3901747177 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.124842924 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 12858356190 ps |
| CPU time | 305.97 seconds |
| Started | Jan 14 12:33:28 PM PST 24 |
| Finished | Jan 14 12:38:35 PM PST 24 |
| Peak memory | 208724 kb |
| Host | smart-9dd78e05-a8fc-4ec9-bee9-b40baca8efde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=124842924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand _reset.124842924 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3422023208 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 7320065248 ps |
| CPU time | 368.49 seconds |
| Started | Jan 14 12:33:31 PM PST 24 |
| Finished | Jan 14 12:39:41 PM PST 24 |
| Peak memory | 212080 kb |
| Host | smart-cf9462e5-33e4-46e6-90db-17a2576424a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3422023208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.3422023208 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.328026024 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 91580929 ps |
| CPU time | 3.75 seconds |
| Started | Jan 14 12:33:25 PM PST 24 |
| Finished | Jan 14 12:33:29 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-e05ab442-e5ec-47d9-8832-2e9ecf63cbdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=328026024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.328026024 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3737653521 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 802405310 ps |
| CPU time | 43.73 seconds |
| Started | Jan 14 12:33:20 PM PST 24 |
| Finished | Jan 14 12:34:04 PM PST 24 |
| Peak memory | 211884 kb |
| Host | smart-5db1e83b-7349-4933-8d5f-81402a1f9a80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3737653521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3737653521 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2624302761 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 33845620450 ps |
| CPU time | 260.85 seconds |
| Started | Jan 14 12:33:22 PM PST 24 |
| Finished | Jan 14 12:37:44 PM PST 24 |
| Peak memory | 206460 kb |
| Host | smart-1d6f5462-dbff-43f5-9e8d-7fe8db06fb39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2624302761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.2624302761 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.371459026 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 273498624 ps |
| CPU time | 9.41 seconds |
| Started | Jan 14 12:33:22 PM PST 24 |
| Finished | Jan 14 12:33:32 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-1c48075f-5294-44c5-b099-70bc779c4ed7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=371459026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.371459026 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.2334676094 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 82220003 ps |
| CPU time | 2.65 seconds |
| Started | Jan 14 12:33:31 PM PST 24 |
| Finished | Jan 14 12:33:34 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-c8639993-def1-4535-84aa-596529b97258 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2334676094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2334676094 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.3559542985 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 3341556119 ps |
| CPU time | 34.92 seconds |
| Started | Jan 14 12:33:28 PM PST 24 |
| Finished | Jan 14 12:34:03 PM PST 24 |
| Peak memory | 204360 kb |
| Host | smart-8433f7da-27ea-4f47-b3b7-e804b0570461 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3559542985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3559542985 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3731965091 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 14282213735 ps |
| CPU time | 51.01 seconds |
| Started | Jan 14 12:33:27 PM PST 24 |
| Finished | Jan 14 12:34:19 PM PST 24 |
| Peak memory | 211928 kb |
| Host | smart-507a01c1-c30a-4969-8911-4a2c2f911a0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731965091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3731965091 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2782172401 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 23345234659 ps |
| CPU time | 53.41 seconds |
| Started | Jan 14 12:33:30 PM PST 24 |
| Finished | Jan 14 12:34:24 PM PST 24 |
| Peak memory | 204912 kb |
| Host | smart-5f30b946-9854-457e-9010-a04dca5cfa21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2782172401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2782172401 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3721164404 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 113428875 ps |
| CPU time | 13.85 seconds |
| Started | Jan 14 12:33:20 PM PST 24 |
| Finished | Jan 14 12:33:34 PM PST 24 |
| Peak memory | 211868 kb |
| Host | smart-a5a153aa-7dde-4653-a365-4999d6196e8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721164404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3721164404 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.3527822377 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 265318456 ps |
| CPU time | 12.98 seconds |
| Started | Jan 14 12:33:34 PM PST 24 |
| Finished | Jan 14 12:33:47 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-c258c14b-a590-42e5-960b-c1fe38fb7728 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3527822377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3527822377 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.1534702076 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 125425648 ps |
| CPU time | 3.34 seconds |
| Started | Jan 14 12:33:28 PM PST 24 |
| Finished | Jan 14 12:33:32 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-bc13a6e0-666a-46fa-995c-939cc99d2fc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1534702076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1534702076 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2421142197 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 27463861949 ps |
| CPU time | 35.59 seconds |
| Started | Jan 14 12:33:17 PM PST 24 |
| Finished | Jan 14 12:33:53 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-5f30bf63-265e-49cc-94fa-28a37ce8ccd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421142197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2421142197 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2075482252 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 9004341207 ps |
| CPU time | 32.63 seconds |
| Started | Jan 14 12:33:20 PM PST 24 |
| Finished | Jan 14 12:33:53 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-2b61b387-b89a-439a-bd94-df17a334893c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2075482252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2075482252 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2387583100 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 27564672 ps |
| CPU time | 2.11 seconds |
| Started | Jan 14 12:33:18 PM PST 24 |
| Finished | Jan 14 12:33:21 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-0b37d35a-f6f0-44fd-a929-4ac05d1227f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387583100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2387583100 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.822756136 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 6662997337 ps |
| CPU time | 196.04 seconds |
| Started | Jan 14 12:33:33 PM PST 24 |
| Finished | Jan 14 12:36:50 PM PST 24 |
| Peak memory | 206904 kb |
| Host | smart-f9682c60-6e82-46b1-bec9-640a3fcd35cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=822756136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.822756136 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.571849323 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3526241109 ps |
| CPU time | 533.37 seconds |
| Started | Jan 14 12:33:29 PM PST 24 |
| Finished | Jan 14 12:42:23 PM PST 24 |
| Peak memory | 220144 kb |
| Host | smart-349f635e-e0ad-4a7e-8b68-20afb137f8c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=571849323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand _reset.571849323 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.772337032 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 269859181 ps |
| CPU time | 67.95 seconds |
| Started | Jan 14 12:33:33 PM PST 24 |
| Finished | Jan 14 12:34:42 PM PST 24 |
| Peak memory | 208380 kb |
| Host | smart-2f5df452-eb08-49d6-bfef-efe3b85e4fc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=772337032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res et_error.772337032 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.4141792780 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 607489348 ps |
| CPU time | 12.21 seconds |
| Started | Jan 14 12:33:23 PM PST 24 |
| Finished | Jan 14 12:33:36 PM PST 24 |
| Peak memory | 204936 kb |
| Host | smart-6c242725-e6ae-4641-9569-ccc0fa67f7e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4141792780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.4141792780 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.434774961 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 863748476 ps |
| CPU time | 22.89 seconds |
| Started | Jan 14 12:33:35 PM PST 24 |
| Finished | Jan 14 12:33:59 PM PST 24 |
| Peak memory | 211844 kb |
| Host | smart-79e0bdfe-a01c-4a02-a0a9-94a576ceae04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=434774961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.434774961 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.498248724 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 30728344900 ps |
| CPU time | 164.55 seconds |
| Started | Jan 14 12:33:33 PM PST 24 |
| Finished | Jan 14 12:36:18 PM PST 24 |
| Peak memory | 206432 kb |
| Host | smart-5a8adb42-dedf-410c-b5e3-8db048ebd9ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=498248724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo w_rsp.498248724 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3394651997 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 479089757 ps |
| CPU time | 10.96 seconds |
| Started | Jan 14 12:33:33 PM PST 24 |
| Finished | Jan 14 12:33:44 PM PST 24 |
| Peak memory | 203840 kb |
| Host | smart-eada0f60-d36b-4e99-a8ad-bfbb8b1aaf6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3394651997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3394651997 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.3877134733 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 549300744 ps |
| CPU time | 12.03 seconds |
| Started | Jan 14 12:33:40 PM PST 24 |
| Finished | Jan 14 12:33:53 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-902fb3af-f6c4-4753-a345-a074f718b2e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3877134733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3877134733 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.1957027187 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 180152873 ps |
| CPU time | 13.97 seconds |
| Started | Jan 14 12:33:32 PM PST 24 |
| Finished | Jan 14 12:33:46 PM PST 24 |
| Peak memory | 211804 kb |
| Host | smart-45f25777-2728-4cdb-904a-25e282935f84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1957027187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.1957027187 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.857976324 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 70740989344 ps |
| CPU time | 193.39 seconds |
| Started | Jan 14 12:33:37 PM PST 24 |
| Finished | Jan 14 12:36:50 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-8ddce89f-da9c-4b96-a594-29a178741da2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=857976324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.857976324 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.2586619652 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 34142784577 ps |
| CPU time | 244.11 seconds |
| Started | Jan 14 12:33:38 PM PST 24 |
| Finished | Jan 14 12:37:43 PM PST 24 |
| Peak memory | 205416 kb |
| Host | smart-9573b3cc-a7dc-45e1-8c73-2c19bfbd1030 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2586619652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2586619652 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1893964342 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 126376992 ps |
| CPU time | 13.13 seconds |
| Started | Jan 14 12:33:37 PM PST 24 |
| Finished | Jan 14 12:33:51 PM PST 24 |
| Peak memory | 211840 kb |
| Host | smart-0057b002-0555-47aa-b44c-e8f514f4329a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893964342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1893964342 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.423198311 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2320241632 ps |
| CPU time | 35.93 seconds |
| Started | Jan 14 12:33:33 PM PST 24 |
| Finished | Jan 14 12:34:10 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-b543ff05-802a-43a5-ba5e-780cd1408b60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=423198311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.423198311 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.3286992602 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 460445649 ps |
| CPU time | 4.28 seconds |
| Started | Jan 14 12:33:35 PM PST 24 |
| Finished | Jan 14 12:33:40 PM PST 24 |
| Peak memory | 203600 kb |
| Host | smart-2472d76c-715b-4cdc-a95a-190a17aac932 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3286992602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3286992602 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1338369130 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 25532637943 ps |
| CPU time | 48.29 seconds |
| Started | Jan 14 12:33:34 PM PST 24 |
| Finished | Jan 14 12:34:23 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-0564851d-daa4-42bb-b3eb-e435a8e570c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338369130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1338369130 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3190325223 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 4083715640 ps |
| CPU time | 33.71 seconds |
| Started | Jan 14 12:33:34 PM PST 24 |
| Finished | Jan 14 12:34:08 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-14273674-c028-4897-a669-c8999bca2afd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3190325223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3190325223 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1475319551 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 33032451 ps |
| CPU time | 2.27 seconds |
| Started | Jan 14 12:33:34 PM PST 24 |
| Finished | Jan 14 12:33:37 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-770f8781-1df6-4d70-afcb-65a064f7fef5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475319551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1475319551 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.843913422 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5731041 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:33:40 PM PST 24 |
| Finished | Jan 14 12:33:42 PM PST 24 |
| Peak memory | 195104 kb |
| Host | smart-c762f1d3-a962-4513-bc9e-1f8bc21c47da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=843913422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.843913422 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.4294327268 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2519245965 ps |
| CPU time | 54.33 seconds |
| Started | Jan 14 12:33:40 PM PST 24 |
| Finished | Jan 14 12:34:35 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-be8a2bbc-babe-46bc-8bcf-b0d833aab04b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4294327268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.4294327268 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1237826937 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 30044105 ps |
| CPU time | 10.97 seconds |
| Started | Jan 14 12:33:25 PM PST 24 |
| Finished | Jan 14 12:33:37 PM PST 24 |
| Peak memory | 205884 kb |
| Host | smart-3345a8cc-34ca-4d48-8ff1-f974a40ca60c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1237826937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.1237826937 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3343685880 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1942898958 ps |
| CPU time | 248.52 seconds |
| Started | Jan 14 12:33:33 PM PST 24 |
| Finished | Jan 14 12:37:42 PM PST 24 |
| Peak memory | 220064 kb |
| Host | smart-fe458ea4-c2c9-4e3e-a402-05e990d1a7f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3343685880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.3343685880 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2647180463 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 169252933 ps |
| CPU time | 15.61 seconds |
| Started | Jan 14 12:33:30 PM PST 24 |
| Finished | Jan 14 12:33:46 PM PST 24 |
| Peak memory | 205012 kb |
| Host | smart-73eb4f52-85a4-4493-8c52-83557391fef4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2647180463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2647180463 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2176330983 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 75732279114 ps |
| CPU time | 707.17 seconds |
| Started | Jan 14 12:33:26 PM PST 24 |
| Finished | Jan 14 12:45:14 PM PST 24 |
| Peak memory | 206000 kb |
| Host | smart-75c3233a-9311-4faa-9d2d-181cc9712048 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2176330983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2176330983 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1360042458 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 893061181 ps |
| CPU time | 25.31 seconds |
| Started | Jan 14 12:33:28 PM PST 24 |
| Finished | Jan 14 12:33:54 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-3b0c8960-fa1e-463d-ad9c-126938fa37a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1360042458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1360042458 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.4142942475 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2354021256 ps |
| CPU time | 31.55 seconds |
| Started | Jan 14 12:33:33 PM PST 24 |
| Finished | Jan 14 12:34:05 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-7c247a23-ad16-4acf-8195-297d9ab4ea93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4142942475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.4142942475 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.3620652086 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1042704490 ps |
| CPU time | 37.51 seconds |
| Started | Jan 14 12:33:33 PM PST 24 |
| Finished | Jan 14 12:34:11 PM PST 24 |
| Peak memory | 211788 kb |
| Host | smart-b90de86d-dbc5-4751-b1c7-64f199a58849 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3620652086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3620652086 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.657899675 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 164880675218 ps |
| CPU time | 252.31 seconds |
| Started | Jan 14 12:33:26 PM PST 24 |
| Finished | Jan 14 12:37:38 PM PST 24 |
| Peak memory | 204872 kb |
| Host | smart-e951549b-d9a1-4177-ba95-a427216d4a23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=657899675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.657899675 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2106931181 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 19398971254 ps |
| CPU time | 69.71 seconds |
| Started | Jan 14 12:33:40 PM PST 24 |
| Finished | Jan 14 12:34:51 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-f5c94ffd-c37c-403e-9548-e9d526c3737e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2106931181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2106931181 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.15299024 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 77633615 ps |
| CPU time | 6.06 seconds |
| Started | Jan 14 12:33:40 PM PST 24 |
| Finished | Jan 14 12:33:47 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-3bfdc853-d31b-4444-b566-826f92d4261c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15299024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.15299024 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.3897090054 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2180638757 ps |
| CPU time | 23.16 seconds |
| Started | Jan 14 12:33:28 PM PST 24 |
| Finished | Jan 14 12:33:52 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-93258124-320f-44bf-9773-cb967e8d51c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3897090054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3897090054 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.3012417295 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 181910969 ps |
| CPU time | 2.98 seconds |
| Started | Jan 14 12:33:33 PM PST 24 |
| Finished | Jan 14 12:33:37 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-f6b504ea-8fb6-4206-abc6-691cea2b82d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3012417295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3012417295 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.4080486859 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4129202659 ps |
| CPU time | 26.54 seconds |
| Started | Jan 14 12:33:36 PM PST 24 |
| Finished | Jan 14 12:34:04 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-aa5e3802-768b-4ba8-bafe-da0c9b85a6fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080486859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4080486859 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3114564650 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 4096879074 ps |
| CPU time | 34.84 seconds |
| Started | Jan 14 12:33:35 PM PST 24 |
| Finished | Jan 14 12:34:10 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-113222b4-609d-4a9e-92ea-511712348320 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3114564650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3114564650 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2976469942 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 29327810 ps |
| CPU time | 2.63 seconds |
| Started | Jan 14 12:33:40 PM PST 24 |
| Finished | Jan 14 12:33:44 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-323ef996-292a-4ae9-ae88-0082bc2ddf65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976469942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2976469942 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.647215943 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1052498663 ps |
| CPU time | 76.89 seconds |
| Started | Jan 14 12:33:41 PM PST 24 |
| Finished | Jan 14 12:34:58 PM PST 24 |
| Peak memory | 206928 kb |
| Host | smart-382096a0-5961-4f62-998a-56ebb0488db0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647215943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.647215943 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.235690710 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2149507284 ps |
| CPU time | 47.74 seconds |
| Started | Jan 14 12:33:26 PM PST 24 |
| Finished | Jan 14 12:34:14 PM PST 24 |
| Peak memory | 206004 kb |
| Host | smart-af3d597f-1612-4592-b26c-ab9763cfeee1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=235690710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.235690710 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1803563872 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 506562447 ps |
| CPU time | 229.12 seconds |
| Started | Jan 14 12:33:27 PM PST 24 |
| Finished | Jan 14 12:37:17 PM PST 24 |
| Peak memory | 209268 kb |
| Host | smart-bafbf7fe-9bdb-4b7f-b07e-240c11fe1d43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1803563872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.1803563872 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1987883402 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1957627681 ps |
| CPU time | 282.35 seconds |
| Started | Jan 14 12:33:29 PM PST 24 |
| Finished | Jan 14 12:38:12 PM PST 24 |
| Peak memory | 220000 kb |
| Host | smart-4549fb66-b71b-41ad-83ea-30419047589e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1987883402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.1987883402 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.243123684 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1348885612 ps |
| CPU time | 15.38 seconds |
| Started | Jan 14 12:33:40 PM PST 24 |
| Finished | Jan 14 12:33:56 PM PST 24 |
| Peak memory | 204828 kb |
| Host | smart-b2bc6657-7430-43d6-8276-5ef4b8840381 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=243123684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.243123684 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3689548219 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1112008547 ps |
| CPU time | 19.16 seconds |
| Started | Jan 14 12:33:37 PM PST 24 |
| Finished | Jan 14 12:33:56 PM PST 24 |
| Peak memory | 211772 kb |
| Host | smart-1a2f5f1e-0eed-400f-96e1-5cfd8bd91248 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3689548219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3689548219 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3032003243 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 350035824484 ps |
| CPU time | 701.26 seconds |
| Started | Jan 14 12:33:37 PM PST 24 |
| Finished | Jan 14 12:45:19 PM PST 24 |
| Peak memory | 207208 kb |
| Host | smart-5e48c104-139d-470c-bcab-b09504210466 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3032003243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.3032003243 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1757518766 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 313248815 ps |
| CPU time | 5.91 seconds |
| Started | Jan 14 12:33:39 PM PST 24 |
| Finished | Jan 14 12:33:46 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-1ee8ce58-f1ab-486d-a39e-7b72e8435605 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1757518766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1757518766 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.90943756 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 16102807 ps |
| CPU time | 1.73 seconds |
| Started | Jan 14 12:33:38 PM PST 24 |
| Finished | Jan 14 12:33:41 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-314aca9c-7d18-4e0c-8881-1286f7152661 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=90943756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.90943756 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.3244942236 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 733270171 ps |
| CPU time | 24.68 seconds |
| Started | Jan 14 12:33:31 PM PST 24 |
| Finished | Jan 14 12:33:56 PM PST 24 |
| Peak memory | 211828 kb |
| Host | smart-38704986-5c34-4aef-b3bc-63a48105855c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3244942236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3244942236 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1554121725 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 205158480311 ps |
| CPU time | 302.23 seconds |
| Started | Jan 14 12:33:35 PM PST 24 |
| Finished | Jan 14 12:38:38 PM PST 24 |
| Peak memory | 211928 kb |
| Host | smart-846cd2fb-e832-4411-a229-a2a8f813e748 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554121725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1554121725 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1757002447 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 27976111399 ps |
| CPU time | 167.06 seconds |
| Started | Jan 14 12:33:35 PM PST 24 |
| Finished | Jan 14 12:36:23 PM PST 24 |
| Peak memory | 211896 kb |
| Host | smart-63695cad-addb-4887-99d4-85f1eaf6a0f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1757002447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1757002447 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3800081118 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 309695549 ps |
| CPU time | 25.64 seconds |
| Started | Jan 14 12:33:39 PM PST 24 |
| Finished | Jan 14 12:34:05 PM PST 24 |
| Peak memory | 211988 kb |
| Host | smart-aeefe4a5-2609-4558-a075-b573bcc1783a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800081118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3800081118 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.1560642872 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 9126154216 ps |
| CPU time | 34.89 seconds |
| Started | Jan 14 12:33:36 PM PST 24 |
| Finished | Jan 14 12:34:11 PM PST 24 |
| Peak memory | 204376 kb |
| Host | smart-d3e36de7-f24a-479b-a30e-5d3392e6f119 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1560642872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1560642872 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.3354739505 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 151099531 ps |
| CPU time | 3.95 seconds |
| Started | Jan 14 12:33:28 PM PST 24 |
| Finished | Jan 14 12:33:32 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-42f26afc-0c53-41c5-8bbc-de2f463c6a04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3354739505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3354739505 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2187925948 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 8722205993 ps |
| CPU time | 31.99 seconds |
| Started | Jan 14 12:33:35 PM PST 24 |
| Finished | Jan 14 12:34:07 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-e46a262a-2439-4d88-aa18-ed62c7181ab6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187925948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2187925948 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.907189338 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4823060475 ps |
| CPU time | 29.08 seconds |
| Started | Jan 14 12:33:35 PM PST 24 |
| Finished | Jan 14 12:34:04 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-7d6ca99b-000a-4938-b4b4-d77df2f078b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=907189338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.907189338 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3921396299 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 71406015 ps |
| CPU time | 2.32 seconds |
| Started | Jan 14 12:33:37 PM PST 24 |
| Finished | Jan 14 12:33:40 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-260618a2-c487-4c6b-8b25-4701cbdab973 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921396299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3921396299 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.2764243055 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 5688967184 ps |
| CPU time | 166 seconds |
| Started | Jan 14 12:33:38 PM PST 24 |
| Finished | Jan 14 12:36:24 PM PST 24 |
| Peak memory | 209416 kb |
| Host | smart-ae1e53c5-f4c5-4614-ac92-0e1e02fdfe8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2764243055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2764243055 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2951635671 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 5329888129 ps |
| CPU time | 133.93 seconds |
| Started | Jan 14 12:33:49 PM PST 24 |
| Finished | Jan 14 12:36:03 PM PST 24 |
| Peak memory | 211960 kb |
| Host | smart-39fdcd3a-565d-485c-b8c1-f22da75fec75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2951635671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2951635671 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1750907840 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 160682811 ps |
| CPU time | 22.21 seconds |
| Started | Jan 14 12:33:36 PM PST 24 |
| Finished | Jan 14 12:33:59 PM PST 24 |
| Peak memory | 205812 kb |
| Host | smart-eb329ec1-071d-4382-b102-2a7082712dda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1750907840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.1750907840 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3635148226 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 51698727 ps |
| CPU time | 2.18 seconds |
| Started | Jan 14 12:33:36 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-f5caf961-b211-4f9e-9b8f-62c9be6f5e74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3635148226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3635148226 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.3713397792 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3263186760 ps |
| CPU time | 68.39 seconds |
| Started | Jan 14 12:33:38 PM PST 24 |
| Finished | Jan 14 12:34:46 PM PST 24 |
| Peak memory | 211916 kb |
| Host | smart-a57b33ec-4fb3-4e51-ab1e-e8c31af05669 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3713397792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3713397792 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1368040065 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 198668775268 ps |
| CPU time | 707.09 seconds |
| Started | Jan 14 12:33:38 PM PST 24 |
| Finished | Jan 14 12:45:25 PM PST 24 |
| Peak memory | 212012 kb |
| Host | smart-da047592-2e9b-45f5-9737-ad6e88adf915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1368040065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.1368040065 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.544803255 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 104613309 ps |
| CPU time | 15.37 seconds |
| Started | Jan 14 12:33:41 PM PST 24 |
| Finished | Jan 14 12:33:57 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-10f0452e-36fc-4317-8916-b49078eb5937 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=544803255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.544803255 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.2012510321 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 720744682 ps |
| CPU time | 11.56 seconds |
| Started | Jan 14 12:33:44 PM PST 24 |
| Finished | Jan 14 12:33:56 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-f9f199b4-8e5c-412c-8974-3ab0525ba42d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2012510321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2012510321 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.2927524123 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 806680306 ps |
| CPU time | 13.9 seconds |
| Started | Jan 14 12:33:45 PM PST 24 |
| Finished | Jan 14 12:34:00 PM PST 24 |
| Peak memory | 204428 kb |
| Host | smart-fe0040a4-2e77-43da-96f0-b1b9d5fd1d72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2927524123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2927524123 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.779243862 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 11038579484 ps |
| CPU time | 53.15 seconds |
| Started | Jan 14 12:33:36 PM PST 24 |
| Finished | Jan 14 12:34:29 PM PST 24 |
| Peak memory | 211984 kb |
| Host | smart-c21361a2-7b2f-451c-98de-12b516969131 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=779243862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.779243862 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.509580850 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 9025802416 ps |
| CPU time | 76.52 seconds |
| Started | Jan 14 12:33:47 PM PST 24 |
| Finished | Jan 14 12:35:04 PM PST 24 |
| Peak memory | 205100 kb |
| Host | smart-098e2d68-45e5-4042-8ca7-201f3da44558 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=509580850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.509580850 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.176965189 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 158142862 ps |
| CPU time | 27.03 seconds |
| Started | Jan 14 12:33:34 PM PST 24 |
| Finished | Jan 14 12:34:01 PM PST 24 |
| Peak memory | 211788 kb |
| Host | smart-8b59acf5-b338-47c2-9f88-7331e7b5eeee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176965189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.176965189 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.3142654244 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 719908784 ps |
| CPU time | 16.06 seconds |
| Started | Jan 14 12:33:46 PM PST 24 |
| Finished | Jan 14 12:34:03 PM PST 24 |
| Peak memory | 204156 kb |
| Host | smart-4e1205a5-d1bd-49ad-863c-9188812218d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3142654244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3142654244 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.3221340979 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 60292861 ps |
| CPU time | 2.05 seconds |
| Started | Jan 14 12:33:46 PM PST 24 |
| Finished | Jan 14 12:33:49 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-67658793-e332-4884-823e-4a2b44dc92e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3221340979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3221340979 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.443300465 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 23983696808 ps |
| CPU time | 35.57 seconds |
| Started | Jan 14 12:33:38 PM PST 24 |
| Finished | Jan 14 12:34:14 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-1fb1b867-c504-4ace-8095-37f53110b106 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=443300465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.443300465 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1760117248 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 7406379782 ps |
| CPU time | 23.84 seconds |
| Started | Jan 14 12:33:35 PM PST 24 |
| Finished | Jan 14 12:34:00 PM PST 24 |
| Peak memory | 203796 kb |
| Host | smart-747e17fb-59dd-4149-8c92-580c81661b02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1760117248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1760117248 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1561028783 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 38380671 ps |
| CPU time | 2.09 seconds |
| Started | Jan 14 12:33:34 PM PST 24 |
| Finished | Jan 14 12:33:37 PM PST 24 |
| Peak memory | 203592 kb |
| Host | smart-f2b2c3ee-61bc-42c3-af04-199b17cbba98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561028783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1561028783 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.4235035632 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 869687153 ps |
| CPU time | 23.46 seconds |
| Started | Jan 14 12:33:45 PM PST 24 |
| Finished | Jan 14 12:34:09 PM PST 24 |
| Peak memory | 205556 kb |
| Host | smart-5aa7aa0e-f114-4809-b4af-a3eeed62cd44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4235035632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4235035632 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1381548162 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1608944043 ps |
| CPU time | 114.79 seconds |
| Started | Jan 14 12:33:47 PM PST 24 |
| Finished | Jan 14 12:35:42 PM PST 24 |
| Peak memory | 205632 kb |
| Host | smart-3e5b53d5-38f9-4eb3-80ec-906b4b640f79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1381548162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1381548162 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.514960584 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7121886379 ps |
| CPU time | 390.2 seconds |
| Started | Jan 14 12:33:52 PM PST 24 |
| Finished | Jan 14 12:40:23 PM PST 24 |
| Peak memory | 211228 kb |
| Host | smart-2b10abae-3efd-4d4b-bca3-6861ad1c7d04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=514960584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand _reset.514960584 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.419018606 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 176241666 ps |
| CPU time | 7.42 seconds |
| Started | Jan 14 12:33:42 PM PST 24 |
| Finished | Jan 14 12:33:50 PM PST 24 |
| Peak memory | 211908 kb |
| Host | smart-3f496ca4-8045-4aa0-a6bf-6e3e8612d7d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=419018606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.419018606 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1617667755 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 1548995772 ps |
| CPU time | 59.16 seconds |
| Started | Jan 14 12:32:31 PM PST 24 |
| Finished | Jan 14 12:33:31 PM PST 24 |
| Peak memory | 211776 kb |
| Host | smart-18513951-8b3e-40b1-be99-4f3bc08553db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1617667755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1617667755 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3301790634 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 13134686791 ps |
| CPU time | 104.13 seconds |
| Started | Jan 14 12:32:34 PM PST 24 |
| Finished | Jan 14 12:34:19 PM PST 24 |
| Peak memory | 206080 kb |
| Host | smart-9c4b6faf-44c6-4f13-98ee-429401a958d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3301790634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.3301790634 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1307356794 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 116998277 ps |
| CPU time | 15.73 seconds |
| Started | Jan 14 12:32:36 PM PST 24 |
| Finished | Jan 14 12:32:54 PM PST 24 |
| Peak memory | 204176 kb |
| Host | smart-b3650181-843f-4297-bf4a-adf8483dda34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1307356794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1307356794 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.1046173499 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 124323401 ps |
| CPU time | 16.1 seconds |
| Started | Jan 14 12:32:37 PM PST 24 |
| Finished | Jan 14 12:32:55 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-17590751-2eef-43e5-aaca-f5d3cd949b2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1046173499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1046173499 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.403942030 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 166976554 ps |
| CPU time | 6.92 seconds |
| Started | Jan 14 12:32:26 PM PST 24 |
| Finished | Jan 14 12:32:35 PM PST 24 |
| Peak memory | 203576 kb |
| Host | smart-70e14c36-a674-44c5-845a-eb522dfb4997 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=403942030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.403942030 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2865210975 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 46401276722 ps |
| CPU time | 257.49 seconds |
| Started | Jan 14 12:32:32 PM PST 24 |
| Finished | Jan 14 12:36:50 PM PST 24 |
| Peak memory | 211952 kb |
| Host | smart-a937ac80-4671-45e6-b062-985f5daab33a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865210975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2865210975 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3515245157 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1986970779 ps |
| CPU time | 13.09 seconds |
| Started | Jan 14 12:32:26 PM PST 24 |
| Finished | Jan 14 12:32:41 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-9524b1f3-e682-4506-a057-6436e7c646d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3515245157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3515245157 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2519240617 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 114131701 ps |
| CPU time | 22.51 seconds |
| Started | Jan 14 12:32:24 PM PST 24 |
| Finished | Jan 14 12:32:48 PM PST 24 |
| Peak memory | 211800 kb |
| Host | smart-05512f0a-b63b-44e7-aa98-84effb6cd56e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519240617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2519240617 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.572368153 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1550115270 ps |
| CPU time | 31.96 seconds |
| Started | Jan 14 12:32:31 PM PST 24 |
| Finished | Jan 14 12:33:04 PM PST 24 |
| Peak memory | 204224 kb |
| Host | smart-d73528e8-307d-4e3d-bd31-9114c1df1e4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=572368153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.572368153 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.2788863109 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 472065901 ps |
| CPU time | 3.44 seconds |
| Started | Jan 14 12:32:22 PM PST 24 |
| Finished | Jan 14 12:32:28 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-f2557ce4-23a7-4d70-8996-22ab78650ee9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2788863109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2788863109 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.353305504 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 11768978578 ps |
| CPU time | 30.16 seconds |
| Started | Jan 14 12:32:31 PM PST 24 |
| Finished | Jan 14 12:33:01 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-875d129f-7067-4bcc-acb9-5d005a461d36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=353305504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.353305504 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.794327706 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4069585777 ps |
| CPU time | 27.24 seconds |
| Started | Jan 14 12:32:27 PM PST 24 |
| Finished | Jan 14 12:32:55 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-8e5cd9d1-38cd-4574-95e3-da1d03e61555 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=794327706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.794327706 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3542823746 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 28415742 ps |
| CPU time | 2.24 seconds |
| Started | Jan 14 12:32:36 PM PST 24 |
| Finished | Jan 14 12:32:39 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-1d09ed22-4573-4b20-8fd7-3d7dbb09e404 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542823746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3542823746 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.1133852453 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2619905214 ps |
| CPU time | 78.51 seconds |
| Started | Jan 14 12:32:27 PM PST 24 |
| Finished | Jan 14 12:33:47 PM PST 24 |
| Peak memory | 205740 kb |
| Host | smart-1e26c63d-307f-42c6-a303-ab9f3d104f77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1133852453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1133852453 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3025248508 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1436357070 ps |
| CPU time | 90.53 seconds |
| Started | Jan 14 12:32:26 PM PST 24 |
| Finished | Jan 14 12:33:58 PM PST 24 |
| Peak memory | 206184 kb |
| Host | smart-1a6145cc-4398-4d27-8a29-3edf80970417 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3025248508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3025248508 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1648379153 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 71610301 ps |
| CPU time | 93.73 seconds |
| Started | Jan 14 12:32:34 PM PST 24 |
| Finished | Jan 14 12:34:09 PM PST 24 |
| Peak memory | 208160 kb |
| Host | smart-391f514f-dbf6-4f06-891e-88a073951669 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1648379153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.1648379153 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3516841906 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 226336336 ps |
| CPU time | 9.47 seconds |
| Started | Jan 14 12:32:27 PM PST 24 |
| Finished | Jan 14 12:32:38 PM PST 24 |
| Peak memory | 204936 kb |
| Host | smart-31271a4a-eaeb-4f26-afa7-f1a548eefe4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3516841906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3516841906 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1089308699 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 131124675 ps |
| CPU time | 20.97 seconds |
| Started | Jan 14 12:33:45 PM PST 24 |
| Finished | Jan 14 12:34:06 PM PST 24 |
| Peak memory | 211796 kb |
| Host | smart-7a719889-07bb-4128-aff3-aa36c6f6ba21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1089308699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1089308699 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.4078010243 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 57003779666 ps |
| CPU time | 341.65 seconds |
| Started | Jan 14 12:33:52 PM PST 24 |
| Finished | Jan 14 12:39:34 PM PST 24 |
| Peak memory | 206656 kb |
| Host | smart-31a62441-6be6-47c5-90ca-29ef86dc194c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4078010243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.4078010243 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3906209721 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 74910549 ps |
| CPU time | 8.58 seconds |
| Started | Jan 14 12:33:47 PM PST 24 |
| Finished | Jan 14 12:33:56 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-1c8a9126-4aa5-4d2a-aaaf-be9d99594846 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3906209721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3906209721 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.1799655410 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 183585605 ps |
| CPU time | 21.32 seconds |
| Started | Jan 14 12:33:39 PM PST 24 |
| Finished | Jan 14 12:34:01 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-a7b48bef-211d-4f9d-8125-69460634f2d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1799655410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1799655410 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.480770619 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 382508164 ps |
| CPU time | 11.12 seconds |
| Started | Jan 14 12:33:44 PM PST 24 |
| Finished | Jan 14 12:33:56 PM PST 24 |
| Peak memory | 211744 kb |
| Host | smart-9f4b1946-cd0b-46f1-95b6-e1007cd9339c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=480770619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.480770619 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2696659266 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 35975360502 ps |
| CPU time | 128.03 seconds |
| Started | Jan 14 12:33:50 PM PST 24 |
| Finished | Jan 14 12:35:58 PM PST 24 |
| Peak memory | 211868 kb |
| Host | smart-e24e0052-1e03-429f-a35f-e666cc750402 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696659266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2696659266 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.79611520 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 57985656884 ps |
| CPU time | 197.45 seconds |
| Started | Jan 14 12:33:43 PM PST 24 |
| Finished | Jan 14 12:37:01 PM PST 24 |
| Peak memory | 211972 kb |
| Host | smart-591ab50a-ad04-406e-9016-bd1bc40d9dd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=79611520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.79611520 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1930160336 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 273914323 ps |
| CPU time | 26.57 seconds |
| Started | Jan 14 12:33:48 PM PST 24 |
| Finished | Jan 14 12:34:15 PM PST 24 |
| Peak memory | 211788 kb |
| Host | smart-2823de5b-6aa2-488c-b2b6-844686ccb5db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930160336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1930160336 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.3903245654 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 168846206 ps |
| CPU time | 10.35 seconds |
| Started | Jan 14 12:33:47 PM PST 24 |
| Finished | Jan 14 12:33:58 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-60a530cf-b77c-4b8e-a35d-8e52965b4bcd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3903245654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3903245654 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.1209442927 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 338694194 ps |
| CPU time | 3.8 seconds |
| Started | Jan 14 12:33:46 PM PST 24 |
| Finished | Jan 14 12:33:51 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-68da832b-7e65-4bcc-a46b-6845f1ce46e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1209442927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1209442927 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.821111706 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 11104880402 ps |
| CPU time | 30.62 seconds |
| Started | Jan 14 12:33:43 PM PST 24 |
| Finished | Jan 14 12:34:14 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-8a717ace-e9ce-4110-ac46-e65d95aec378 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=821111706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.821111706 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1299436713 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 5918429648 ps |
| CPU time | 23.29 seconds |
| Started | Jan 14 12:33:46 PM PST 24 |
| Finished | Jan 14 12:34:10 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-7802c84e-1df4-4d24-83b5-79e82166e3bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1299436713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1299436713 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1931978531 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 28769661 ps |
| CPU time | 2.26 seconds |
| Started | Jan 14 12:33:39 PM PST 24 |
| Finished | Jan 14 12:33:42 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-429ede70-4fa7-42da-bca6-d2460a108b72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931978531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1931978531 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.3403871008 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 8884162137 ps |
| CPU time | 155.15 seconds |
| Started | Jan 14 12:33:39 PM PST 24 |
| Finished | Jan 14 12:36:15 PM PST 24 |
| Peak memory | 210024 kb |
| Host | smart-a3fbeb32-73d2-47a5-a542-e506393ec93e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3403871008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3403871008 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.4093430136 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 6382211443 ps |
| CPU time | 119.17 seconds |
| Started | Jan 14 12:33:46 PM PST 24 |
| Finished | Jan 14 12:35:45 PM PST 24 |
| Peak memory | 206772 kb |
| Host | smart-5a10e4a1-18b5-435e-9808-58c98a964b2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4093430136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.4093430136 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3576175798 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 295055385 ps |
| CPU time | 129.97 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:36:02 PM PST 24 |
| Peak memory | 208524 kb |
| Host | smart-53e12e62-9ee3-4eea-b9e7-aef7433bca7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3576175798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.3576175798 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2421309485 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 27499053 ps |
| CPU time | 34.25 seconds |
| Started | Jan 14 12:33:43 PM PST 24 |
| Finished | Jan 14 12:34:18 PM PST 24 |
| Peak memory | 206216 kb |
| Host | smart-d46a30ad-2adb-4bb0-a780-5eb97949057f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2421309485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.2421309485 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.502285608 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 20244827 ps |
| CPU time | 2.04 seconds |
| Started | Jan 14 12:33:47 PM PST 24 |
| Finished | Jan 14 12:33:49 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-5e8b6dce-7614-45ac-9bef-a076f1924ab0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=502285608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.502285608 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3803825698 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3696593137 ps |
| CPU time | 21.07 seconds |
| Started | Jan 14 12:33:43 PM PST 24 |
| Finished | Jan 14 12:34:05 PM PST 24 |
| Peak memory | 211920 kb |
| Host | smart-cec8623d-aac0-49fd-91e4-138bc489a82c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3803825698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3803825698 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2195587543 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 314854704706 ps |
| CPU time | 788.48 seconds |
| Started | Jan 14 12:33:45 PM PST 24 |
| Finished | Jan 14 12:46:54 PM PST 24 |
| Peak memory | 207236 kb |
| Host | smart-ab19d0b8-0adf-4ad7-bbcc-906aca0651ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2195587543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2195587543 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3674774540 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 80425374 ps |
| CPU time | 2.63 seconds |
| Started | Jan 14 12:33:52 PM PST 24 |
| Finished | Jan 14 12:33:55 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-9128a89a-ea79-4b38-97b9-30b5d6bdfbb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3674774540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3674774540 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.3955694252 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 248835758 ps |
| CPU time | 15.66 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:34:07 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-e227e0c9-5202-4970-ada6-827b894889a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3955694252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3955694252 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.2964122542 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 444787620 ps |
| CPU time | 13.66 seconds |
| Started | Jan 14 12:33:48 PM PST 24 |
| Finished | Jan 14 12:34:02 PM PST 24 |
| Peak memory | 204532 kb |
| Host | smart-b247198f-ac5f-4c24-a760-694a3ad8c17e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2964122542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.2964122542 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3183858708 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 172661427940 ps |
| CPU time | 236.27 seconds |
| Started | Jan 14 12:33:47 PM PST 24 |
| Finished | Jan 14 12:37:43 PM PST 24 |
| Peak memory | 205388 kb |
| Host | smart-0cbfc6cc-6a5c-46e4-aa6d-aa6f27a7e6a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183858708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3183858708 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1460898022 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 25731425846 ps |
| CPU time | 189.46 seconds |
| Started | Jan 14 12:33:52 PM PST 24 |
| Finished | Jan 14 12:37:02 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-adcf5bc3-4dbc-49fd-b604-83a2105fcecf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1460898022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1460898022 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.1137547128 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 89356243 ps |
| CPU time | 12.06 seconds |
| Started | Jan 14 12:33:45 PM PST 24 |
| Finished | Jan 14 12:33:58 PM PST 24 |
| Peak memory | 204720 kb |
| Host | smart-98498031-5ce6-4ce9-a3b9-0f0730afe6e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137547128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.1137547128 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.4126848638 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 92649023 ps |
| CPU time | 5.55 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:33:58 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-98098e1f-e4c1-40f7-b0a4-b700d6ece81a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4126848638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.4126848638 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.1933293121 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 409805587 ps |
| CPU time | 3.14 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:33:55 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-fe601a4a-3df3-4b12-b5c2-7e7702ba6300 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1933293121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1933293121 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.4185545702 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 21029915747 ps |
| CPU time | 33.31 seconds |
| Started | Jan 14 12:33:43 PM PST 24 |
| Finished | Jan 14 12:34:17 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-6c1be250-bb4b-4535-9783-d8fd023f564f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185545702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.4185545702 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1562107756 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 4380322807 ps |
| CPU time | 30.9 seconds |
| Started | Jan 14 12:33:41 PM PST 24 |
| Finished | Jan 14 12:34:13 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-753f67a5-1d4f-4991-9b1e-397acc05a092 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1562107756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1562107756 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.883900845 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 29498671 ps |
| CPU time | 2.33 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:33:54 PM PST 24 |
| Peak memory | 203628 kb |
| Host | smart-ef0225c4-45f4-447b-994b-e1b0dfd652a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883900845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.883900845 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3253349856 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2050318205 ps |
| CPU time | 46.34 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:34:38 PM PST 24 |
| Peak memory | 206856 kb |
| Host | smart-6850b6ad-e6bc-4645-8ead-e59c0c6ef611 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3253349856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3253349856 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.825700826 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 6161023804 ps |
| CPU time | 195.96 seconds |
| Started | Jan 14 12:33:52 PM PST 24 |
| Finished | Jan 14 12:37:08 PM PST 24 |
| Peak memory | 209544 kb |
| Host | smart-6f160ad2-f854-4e58-86f1-28b3e74f1aad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=825700826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.825700826 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1715897404 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 6260608031 ps |
| CPU time | 353.94 seconds |
| Started | Jan 14 12:33:56 PM PST 24 |
| Finished | Jan 14 12:39:51 PM PST 24 |
| Peak memory | 209852 kb |
| Host | smart-9798321d-93b5-4dcf-b572-68c2ae884f47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1715897404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1715897404 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3412526859 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 476229873 ps |
| CPU time | 156.5 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:36:28 PM PST 24 |
| Peak memory | 209836 kb |
| Host | smart-781325e4-314b-4f94-b35b-f19541321e6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3412526859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.3412526859 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.2634401531 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 57112553 ps |
| CPU time | 2.35 seconds |
| Started | Jan 14 12:33:46 PM PST 24 |
| Finished | Jan 14 12:33:49 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-79ebb0fe-3ec7-4c50-b773-5e5fd8279de8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2634401531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2634401531 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.2496088526 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 421861184 ps |
| CPU time | 7.47 seconds |
| Started | Jan 14 12:33:52 PM PST 24 |
| Finished | Jan 14 12:34:00 PM PST 24 |
| Peak memory | 211860 kb |
| Host | smart-afe1c1cd-74a5-470a-8376-6c3e21d2ac72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2496088526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2496088526 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1592044329 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1984901129 ps |
| CPU time | 23.01 seconds |
| Started | Jan 14 12:33:53 PM PST 24 |
| Finished | Jan 14 12:34:17 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-051b83de-628c-4e21-857a-8bd065a7b79c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1592044329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1592044329 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.2240176678 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 122705750 ps |
| CPU time | 15.11 seconds |
| Started | Jan 14 12:33:53 PM PST 24 |
| Finished | Jan 14 12:34:09 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-a73666bf-3988-46a3-8390-8c6f6905b889 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2240176678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2240176678 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.217182493 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1657743368 ps |
| CPU time | 28.85 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:34:21 PM PST 24 |
| Peak memory | 204772 kb |
| Host | smart-f7779445-3ffa-436b-93ca-431bdfd301a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=217182493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.217182493 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3615034746 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 67821685655 ps |
| CPU time | 145.6 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:36:17 PM PST 24 |
| Peak memory | 211988 kb |
| Host | smart-9318ab42-26fd-41e4-9eea-6c3ac756fffc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615034746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3615034746 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1732937086 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2324706437 ps |
| CPU time | 24.16 seconds |
| Started | Jan 14 12:33:59 PM PST 24 |
| Finished | Jan 14 12:34:24 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-c7f78ce9-56c6-4a2c-8c91-34f3cb0af485 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1732937086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1732937086 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.528515352 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 45417858 ps |
| CPU time | 5.69 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:33:58 PM PST 24 |
| Peak memory | 204436 kb |
| Host | smart-a12b005d-562e-444e-a16d-da75733883b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528515352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.528515352 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.738533813 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 656588090 ps |
| CPU time | 15.83 seconds |
| Started | Jan 14 12:33:56 PM PST 24 |
| Finished | Jan 14 12:34:12 PM PST 24 |
| Peak memory | 203992 kb |
| Host | smart-38513624-3e00-4825-944b-062ee8cd5df7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=738533813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.738533813 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.3488022349 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 269006049 ps |
| CPU time | 3.08 seconds |
| Started | Jan 14 12:33:50 PM PST 24 |
| Finished | Jan 14 12:33:54 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-a3eb7581-f79b-476d-acc0-b43f76759b85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3488022349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3488022349 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.969178040 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 18670432504 ps |
| CPU time | 36.1 seconds |
| Started | Jan 14 12:33:50 PM PST 24 |
| Finished | Jan 14 12:34:26 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-fdfb111c-3181-44ea-8da2-1b650884ad84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=969178040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.969178040 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.1582365658 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4820402734 ps |
| CPU time | 29.61 seconds |
| Started | Jan 14 12:34:02 PM PST 24 |
| Finished | Jan 14 12:34:33 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-fee8fb90-c780-4dcb-8674-3e25750395be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1582365658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1582365658 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.4177101377 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 110288402 ps |
| CPU time | 2.46 seconds |
| Started | Jan 14 12:33:50 PM PST 24 |
| Finished | Jan 14 12:33:53 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-2a837954-8bb0-4288-906f-16147710d7d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177101377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.4177101377 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.3128630652 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 376353950 ps |
| CPU time | 22.3 seconds |
| Started | Jan 14 12:33:53 PM PST 24 |
| Finished | Jan 14 12:34:16 PM PST 24 |
| Peak memory | 205184 kb |
| Host | smart-d067846f-27e4-4c10-8d65-5fc4f5c93e71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3128630652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3128630652 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3559079565 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5310677462 ps |
| CPU time | 104.93 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:35:36 PM PST 24 |
| Peak memory | 205488 kb |
| Host | smart-47e935b3-b05b-41ae-a009-ee7b834e5580 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3559079565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3559079565 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.4271684851 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 3611162808 ps |
| CPU time | 295.57 seconds |
| Started | Jan 14 12:33:52 PM PST 24 |
| Finished | Jan 14 12:38:48 PM PST 24 |
| Peak memory | 209272 kb |
| Host | smart-3bfedbb5-83de-4a01-81a0-5ea0125bf696 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4271684851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.4271684851 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3355269202 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 110354693 ps |
| CPU time | 13.28 seconds |
| Started | Jan 14 12:33:52 PM PST 24 |
| Finished | Jan 14 12:34:06 PM PST 24 |
| Peak memory | 205356 kb |
| Host | smart-eec9349c-f2c9-454e-94f8-6ef43f1eb160 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3355269202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.3355269202 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3285757573 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 363497198 ps |
| CPU time | 12.3 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:34:04 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-d2e38cd0-927f-4db0-a34e-4d860c0ae20a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3285757573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3285757573 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.4237461207 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 92374199 ps |
| CPU time | 15.22 seconds |
| Started | Jan 14 12:34:04 PM PST 24 |
| Finished | Jan 14 12:34:20 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-6ae2d059-9e31-4684-af97-58c87f11fb4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4237461207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.4237461207 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2339036417 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 88836081655 ps |
| CPU time | 475.92 seconds |
| Started | Jan 14 12:34:01 PM PST 24 |
| Finished | Jan 14 12:41:58 PM PST 24 |
| Peak memory | 206900 kb |
| Host | smart-a838a9f0-ec41-49c1-a82b-50d7b1c3cab9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2339036417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.2339036417 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2342937850 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 573323123 ps |
| CPU time | 19.22 seconds |
| Started | Jan 14 12:34:01 PM PST 24 |
| Finished | Jan 14 12:34:21 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-f905c077-1d3d-494e-983b-7a1e30b7f1bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2342937850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2342937850 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.2196878669 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 584591797 ps |
| CPU time | 17.31 seconds |
| Started | Jan 14 12:33:59 PM PST 24 |
| Finished | Jan 14 12:34:17 PM PST 24 |
| Peak memory | 203616 kb |
| Host | smart-0cd4ea65-a87e-4fbc-b058-40d4bb1d745e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2196878669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2196878669 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.3437400429 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 629209755 ps |
| CPU time | 21.09 seconds |
| Started | Jan 14 12:33:56 PM PST 24 |
| Finished | Jan 14 12:34:18 PM PST 24 |
| Peak memory | 204828 kb |
| Host | smart-d157a687-b5f9-47e4-9ef4-39bdbe1f69f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3437400429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3437400429 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.701458731 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 27654851457 ps |
| CPU time | 167.81 seconds |
| Started | Jan 14 12:33:53 PM PST 24 |
| Finished | Jan 14 12:36:41 PM PST 24 |
| Peak memory | 204812 kb |
| Host | smart-099803b6-7cc4-40ca-adf6-e66b696394a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=701458731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.701458731 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.190407885 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 21644002305 ps |
| CPU time | 51.04 seconds |
| Started | Jan 14 12:33:59 PM PST 24 |
| Finished | Jan 14 12:34:50 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-35af6c9f-c948-4f45-85d3-de7a09c71468 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=190407885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.190407885 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2628316801 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 783053715 ps |
| CPU time | 21.17 seconds |
| Started | Jan 14 12:33:51 PM PST 24 |
| Finished | Jan 14 12:34:13 PM PST 24 |
| Peak memory | 211856 kb |
| Host | smart-ac912e5f-5b68-46b2-9b14-7c86686e83bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628316801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2628316801 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.2006880077 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336896495 ps |
| CPU time | 6.48 seconds |
| Started | Jan 14 12:33:59 PM PST 24 |
| Finished | Jan 14 12:34:05 PM PST 24 |
| Peak memory | 203884 kb |
| Host | smart-798fd53a-b74c-420e-9f4a-c822b31271d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2006880077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2006880077 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.3406257867 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 522618141 ps |
| CPU time | 3.32 seconds |
| Started | Jan 14 12:33:56 PM PST 24 |
| Finished | Jan 14 12:34:00 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-035e54d8-40d8-47a7-91cf-2d15f76b7c5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3406257867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3406257867 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1095100725 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 24131297287 ps |
| CPU time | 41.65 seconds |
| Started | Jan 14 12:33:55 PM PST 24 |
| Finished | Jan 14 12:34:37 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-2204fed0-01f6-4f30-b968-23b42e22b289 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095100725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1095100725 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1978457480 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 8004410735 ps |
| CPU time | 23.89 seconds |
| Started | Jan 14 12:33:55 PM PST 24 |
| Finished | Jan 14 12:34:19 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-34fa6582-22a0-4de9-8dbd-4fe70daa0877 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1978457480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1978457480 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.271125532 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 99171793 ps |
| CPU time | 2.22 seconds |
| Started | Jan 14 12:33:54 PM PST 24 |
| Finished | Jan 14 12:33:57 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-ca688d68-0dcd-4d24-9237-97d6720fab4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271125532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.271125532 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.4170227949 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3176553211 ps |
| CPU time | 118.14 seconds |
| Started | Jan 14 12:34:02 PM PST 24 |
| Finished | Jan 14 12:36:01 PM PST 24 |
| Peak memory | 206100 kb |
| Host | smart-7c89530a-c5f3-4356-a43b-9734d9569850 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4170227949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.4170227949 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.827965710 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4283393061 ps |
| CPU time | 99.5 seconds |
| Started | Jan 14 12:33:58 PM PST 24 |
| Finished | Jan 14 12:35:38 PM PST 24 |
| Peak memory | 206048 kb |
| Host | smart-f3947456-3e4b-4b6c-924c-7a87276ccaf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=827965710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.827965710 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1263353523 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 331677056 ps |
| CPU time | 80.26 seconds |
| Started | Jan 14 12:33:58 PM PST 24 |
| Finished | Jan 14 12:35:18 PM PST 24 |
| Peak memory | 208632 kb |
| Host | smart-219e7dc6-0499-4921-84d7-8754b7ed43c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1263353523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.1263353523 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2517980651 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 31260122 ps |
| CPU time | 17.71 seconds |
| Started | Jan 14 12:34:01 PM PST 24 |
| Finished | Jan 14 12:34:20 PM PST 24 |
| Peak memory | 205412 kb |
| Host | smart-0906e53e-8c0e-4ed7-a453-b79bf0f85da7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2517980651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.2517980651 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3495939413 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 348182567 ps |
| CPU time | 7.01 seconds |
| Started | Jan 14 12:33:59 PM PST 24 |
| Finished | Jan 14 12:34:06 PM PST 24 |
| Peak memory | 211836 kb |
| Host | smart-f7bd510e-bd95-4e4e-901d-e6f8c1a0ab9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3495939413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3495939413 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1185956892 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 184404935 ps |
| CPU time | 12.94 seconds |
| Started | Jan 14 12:34:00 PM PST 24 |
| Finished | Jan 14 12:34:13 PM PST 24 |
| Peak memory | 211844 kb |
| Host | smart-5ba2189c-8e29-4c15-b1b0-d510a545d885 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1185956892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1185956892 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3993408513 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 72220344185 ps |
| CPU time | 122.65 seconds |
| Started | Jan 14 12:34:00 PM PST 24 |
| Finished | Jan 14 12:36:03 PM PST 24 |
| Peak memory | 205920 kb |
| Host | smart-68935d59-68bd-4d8b-9725-7c1bfa28bdf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3993408513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.3993408513 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1228963353 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 272161809 ps |
| CPU time | 11.68 seconds |
| Started | Jan 14 12:34:04 PM PST 24 |
| Finished | Jan 14 12:34:16 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-711d6717-3bd4-414c-9bd0-c9f1d3a8d198 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1228963353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1228963353 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.1499995829 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 42139184 ps |
| CPU time | 5.1 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:13 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-ca27181d-d6d1-441a-81ad-65d1c8d2ada0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1499995829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1499995829 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.933300394 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1374097364 ps |
| CPU time | 17.5 seconds |
| Started | Jan 14 12:34:01 PM PST 24 |
| Finished | Jan 14 12:34:19 PM PST 24 |
| Peak memory | 211888 kb |
| Host | smart-bef36a37-f72f-47a2-9fb1-688dfc8e14fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=933300394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.933300394 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.3018488132 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 170637965330 ps |
| CPU time | 223.19 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:37:51 PM PST 24 |
| Peak memory | 204888 kb |
| Host | smart-3fe8150b-a033-4227-af52-17c10afbf311 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018488132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3018488132 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3610895582 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 4913343585 ps |
| CPU time | 24.98 seconds |
| Started | Jan 14 12:34:00 PM PST 24 |
| Finished | Jan 14 12:34:26 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-1be9bec1-4a1b-4494-975b-454836612804 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3610895582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3610895582 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.515182836 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 87468026 ps |
| CPU time | 9.46 seconds |
| Started | Jan 14 12:34:03 PM PST 24 |
| Finished | Jan 14 12:34:13 PM PST 24 |
| Peak memory | 204400 kb |
| Host | smart-f3156920-2e69-4e14-84a8-d57edaf9c50d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515182836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.515182836 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.3319621212 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2058064830 ps |
| CPU time | 11.12 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:19 PM PST 24 |
| Peak memory | 203956 kb |
| Host | smart-733723bf-d535-4a13-9cb9-4f9fef9ce432 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3319621212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3319621212 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.915058524 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 196565376 ps |
| CPU time | 3.49 seconds |
| Started | Jan 14 12:34:00 PM PST 24 |
| Finished | Jan 14 12:34:04 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-088b7548-5f2f-4bcf-9a21-c9493c02141a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=915058524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.915058524 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3673373630 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 6564457580 ps |
| CPU time | 27.86 seconds |
| Started | Jan 14 12:34:02 PM PST 24 |
| Finished | Jan 14 12:34:30 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-7c82d971-01a4-47ef-9baf-9c8ea8d82bd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673373630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3673373630 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.378013402 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 9413540361 ps |
| CPU time | 32.69 seconds |
| Started | Jan 14 12:34:03 PM PST 24 |
| Finished | Jan 14 12:34:36 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-74e8b0ac-b02b-45f8-9aad-f86dc2f87a22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=378013402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.378013402 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1781828234 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 67197487 ps |
| CPU time | 2.11 seconds |
| Started | Jan 14 12:34:00 PM PST 24 |
| Finished | Jan 14 12:34:03 PM PST 24 |
| Peak memory | 203576 kb |
| Host | smart-408bd864-abaf-495c-a037-30c136eaa06c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781828234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1781828234 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1690663436 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 10483076470 ps |
| CPU time | 54.94 seconds |
| Started | Jan 14 12:34:08 PM PST 24 |
| Finished | Jan 14 12:35:03 PM PST 24 |
| Peak memory | 206236 kb |
| Host | smart-b56d3edb-d155-4676-bcba-f46323e893c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1690663436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1690663436 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1789103320 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 8744855594 ps |
| CPU time | 153.95 seconds |
| Started | Jan 14 12:34:02 PM PST 24 |
| Finished | Jan 14 12:36:37 PM PST 24 |
| Peak memory | 205684 kb |
| Host | smart-15d867eb-26d5-4e88-8786-f8872ec23204 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1789103320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1789103320 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.568239875 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2653196109 ps |
| CPU time | 239.75 seconds |
| Started | Jan 14 12:34:11 PM PST 24 |
| Finished | Jan 14 12:38:11 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-7cbb3493-b501-40f8-a546-2bcef2ab019a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=568239875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.568239875 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2650997811 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 156135470 ps |
| CPU time | 18.13 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:26 PM PST 24 |
| Peak memory | 211848 kb |
| Host | smart-9fc9da0e-93ac-4f13-8db8-cd25f8db6d58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2650997811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2650997811 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2688593756 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1676969960 ps |
| CPU time | 60.93 seconds |
| Started | Jan 14 12:34:08 PM PST 24 |
| Finished | Jan 14 12:35:09 PM PST 24 |
| Peak memory | 206516 kb |
| Host | smart-0032a152-5ff4-46c0-9e32-71d54e7d1f29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2688593756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2688593756 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.259644067 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 18519151366 ps |
| CPU time | 81.02 seconds |
| Started | Jan 14 12:34:13 PM PST 24 |
| Finished | Jan 14 12:35:35 PM PST 24 |
| Peak memory | 211920 kb |
| Host | smart-3da9047d-b59a-402c-ac8b-9b8de172bf6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=259644067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slo w_rsp.259644067 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2226320822 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 212472835 ps |
| CPU time | 12.65 seconds |
| Started | Jan 14 12:34:12 PM PST 24 |
| Finished | Jan 14 12:34:25 PM PST 24 |
| Peak memory | 203876 kb |
| Host | smart-e666b7f2-1008-40cc-af0f-2a89180753ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2226320822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2226320822 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.957410310 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 833424790 ps |
| CPU time | 27.65 seconds |
| Started | Jan 14 12:34:13 PM PST 24 |
| Finished | Jan 14 12:34:41 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-7a324e57-7fe6-44f2-b787-847c2bf29a88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=957410310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.957410310 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.356862588 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 532002051 ps |
| CPU time | 27.25 seconds |
| Started | Jan 14 12:34:05 PM PST 24 |
| Finished | Jan 14 12:34:33 PM PST 24 |
| Peak memory | 211860 kb |
| Host | smart-0be6ca07-e3c2-4873-bba3-5672f3930f58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=356862588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.356862588 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3377254270 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2208856058 ps |
| CPU time | 11.23 seconds |
| Started | Jan 14 12:34:15 PM PST 24 |
| Finished | Jan 14 12:34:27 PM PST 24 |
| Peak memory | 203876 kb |
| Host | smart-8b0af0cb-6b12-430a-8787-e1271af33997 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377254270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3377254270 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1117766122 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 23974413811 ps |
| CPU time | 166.29 seconds |
| Started | Jan 14 12:34:09 PM PST 24 |
| Finished | Jan 14 12:36:55 PM PST 24 |
| Peak memory | 205068 kb |
| Host | smart-2b99b7ef-a585-4b23-a407-9d4fa8e13438 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1117766122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1117766122 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2440669767 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 109836049 ps |
| CPU time | 16.99 seconds |
| Started | Jan 14 12:34:09 PM PST 24 |
| Finished | Jan 14 12:34:27 PM PST 24 |
| Peak memory | 205088 kb |
| Host | smart-b8ebec27-ed1d-41ce-831b-2b774182b53a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440669767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2440669767 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.863131327 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 925892801 ps |
| CPU time | 11.62 seconds |
| Started | Jan 14 12:34:12 PM PST 24 |
| Finished | Jan 14 12:34:25 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-06962869-2506-4e77-acbb-5896c5ee398b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=863131327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.863131327 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.3241658633 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 379640432 ps |
| CPU time | 3.46 seconds |
| Started | Jan 14 12:34:13 PM PST 24 |
| Finished | Jan 14 12:34:17 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-031fa1b5-b37a-44f1-b897-3ea86f8defee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3241658633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3241658633 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1453623211 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 8714321304 ps |
| CPU time | 29.02 seconds |
| Started | Jan 14 12:34:09 PM PST 24 |
| Finished | Jan 14 12:34:38 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-e325358f-5df3-42be-af55-8522f5a51ead |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453623211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1453623211 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1090111039 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2471011720 ps |
| CPU time | 20.55 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:28 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-cad668bf-2cd6-4fda-bce0-188baa416cd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1090111039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1090111039 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.595556677 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 50130248 ps |
| CPU time | 2.42 seconds |
| Started | Jan 14 12:34:10 PM PST 24 |
| Finished | Jan 14 12:34:13 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-cc173d60-8c7e-47f7-a424-8f11f46b3ea3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595556677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.595556677 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.4183042469 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 481198674 ps |
| CPU time | 6.3 seconds |
| Started | Jan 14 12:34:08 PM PST 24 |
| Finished | Jan 14 12:34:15 PM PST 24 |
| Peak memory | 204544 kb |
| Host | smart-1048052d-331d-424d-a6d8-4e85e0fb6a0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4183042469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4183042469 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3516945918 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 188257691 ps |
| CPU time | 7.01 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:15 PM PST 24 |
| Peak memory | 204088 kb |
| Host | smart-752f842f-0d04-4715-827b-0e9d9c36df64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3516945918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3516945918 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1875072001 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 171551210 ps |
| CPU time | 32.88 seconds |
| Started | Jan 14 12:34:12 PM PST 24 |
| Finished | Jan 14 12:34:45 PM PST 24 |
| Peak memory | 206180 kb |
| Host | smart-96c4d641-cdc7-4e4d-9a50-cadbc51fe446 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1875072001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.1875072001 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.2246107296 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 417036991 ps |
| CPU time | 6.49 seconds |
| Started | Jan 14 12:34:09 PM PST 24 |
| Finished | Jan 14 12:34:16 PM PST 24 |
| Peak memory | 211880 kb |
| Host | smart-9606b9f3-259f-4706-a07d-cbbf109520bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2246107296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2246107296 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2980336565 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 760402133 ps |
| CPU time | 50.39 seconds |
| Started | Jan 14 12:34:18 PM PST 24 |
| Finished | Jan 14 12:35:10 PM PST 24 |
| Peak memory | 211824 kb |
| Host | smart-45327c70-8b7a-40c6-889b-57229a72fe81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2980336565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2980336565 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2446354214 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 87126160530 ps |
| CPU time | 310.61 seconds |
| Started | Jan 14 12:34:05 PM PST 24 |
| Finished | Jan 14 12:39:16 PM PST 24 |
| Peak memory | 211860 kb |
| Host | smart-2b00ab4f-3ed6-4e31-b103-8e8084dd07c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2446354214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.2446354214 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1494340655 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4229346900 ps |
| CPU time | 34.1 seconds |
| Started | Jan 14 12:34:06 PM PST 24 |
| Finished | Jan 14 12:34:41 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-d1a15f8d-4e9b-4775-8fdc-894c8cad0cbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1494340655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1494340655 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.3350532030 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 247785650 ps |
| CPU time | 15.49 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:34:31 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-6366825a-4728-4745-9865-171a0814bf9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3350532030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3350532030 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.239062632 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 4063160876 ps |
| CPU time | 43.05 seconds |
| Started | Jan 14 12:34:18 PM PST 24 |
| Finished | Jan 14 12:35:02 PM PST 24 |
| Peak memory | 211828 kb |
| Host | smart-f89983a1-df9e-4420-8a11-038110432271 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=239062632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.239062632 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.837734324 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 56563192696 ps |
| CPU time | 111.93 seconds |
| Started | Jan 14 12:34:00 PM PST 24 |
| Finished | Jan 14 12:35:53 PM PST 24 |
| Peak memory | 211912 kb |
| Host | smart-88982c4c-5fee-4a75-9e82-296639984e92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=837734324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.837734324 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2820841759 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 32628247373 ps |
| CPU time | 210.28 seconds |
| Started | Jan 14 12:34:18 PM PST 24 |
| Finished | Jan 14 12:37:50 PM PST 24 |
| Peak memory | 205212 kb |
| Host | smart-3838d498-9bbd-419f-9c39-2625488f1f33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2820841759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2820841759 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.3561342441 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 202485187 ps |
| CPU time | 22.2 seconds |
| Started | Jan 14 12:33:58 PM PST 24 |
| Finished | Jan 14 12:34:21 PM PST 24 |
| Peak memory | 211820 kb |
| Host | smart-39c8cd19-6657-4e67-8ce0-bb920772dcfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561342441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3561342441 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.2221593416 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 803327717 ps |
| CPU time | 13.68 seconds |
| Started | Jan 14 12:34:11 PM PST 24 |
| Finished | Jan 14 12:34:25 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-af9ac3aa-862d-4747-99e5-758d12069ae3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2221593416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2221593416 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.1252533104 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 143271850 ps |
| CPU time | 3.38 seconds |
| Started | Jan 14 12:34:08 PM PST 24 |
| Finished | Jan 14 12:34:12 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-01220e58-4d36-4e55-9195-8146e0a5e0b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1252533104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1252533104 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.310437574 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 5701669141 ps |
| CPU time | 32.44 seconds |
| Started | Jan 14 12:34:08 PM PST 24 |
| Finished | Jan 14 12:34:41 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-0e58763c-11a3-4125-a2ec-e9e32c862d9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=310437574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.310437574 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3788728023 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 6597702814 ps |
| CPU time | 39.13 seconds |
| Started | Jan 14 12:34:10 PM PST 24 |
| Finished | Jan 14 12:34:49 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-45285af1-feed-47fa-b533-da71c44c36dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3788728023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3788728023 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2700944097 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 53753316 ps |
| CPU time | 2.47 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:10 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-f6eb9a55-164d-4457-9c8f-e4d914d60d55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700944097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2700944097 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3331825177 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2722007417 ps |
| CPU time | 38.58 seconds |
| Started | Jan 14 12:34:11 PM PST 24 |
| Finished | Jan 14 12:34:50 PM PST 24 |
| Peak memory | 205652 kb |
| Host | smart-2d4a18db-597d-4f99-bd6b-fb07ad15f304 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3331825177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3331825177 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3918866276 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 7517373557 ps |
| CPU time | 41.42 seconds |
| Started | Jan 14 12:34:11 PM PST 24 |
| Finished | Jan 14 12:34:53 PM PST 24 |
| Peak memory | 205416 kb |
| Host | smart-10b4096d-031e-4eaf-b474-ce5ace6be874 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3918866276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3918866276 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1562572052 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 5679283417 ps |
| CPU time | 332.53 seconds |
| Started | Jan 14 12:34:06 PM PST 24 |
| Finished | Jan 14 12:39:40 PM PST 24 |
| Peak memory | 210412 kb |
| Host | smart-f9c4d87b-a04b-4fb9-bf33-c3c76ad26b62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1562572052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.1562572052 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2288151815 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 75192598 ps |
| CPU time | 21.9 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:34:37 PM PST 24 |
| Peak memory | 205872 kb |
| Host | smart-9fbd5c29-1fac-4f03-9b5e-2d80d55829a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2288151815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.2288151815 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.3342861347 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 4321673798 ps |
| CPU time | 32.37 seconds |
| Started | Jan 14 12:34:08 PM PST 24 |
| Finished | Jan 14 12:34:40 PM PST 24 |
| Peak memory | 205560 kb |
| Host | smart-bd17ea6b-bb87-4164-b42d-93d81db0cff6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3342861347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3342861347 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1227217548 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 4853771621 ps |
| CPU time | 67.13 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:35:22 PM PST 24 |
| Peak memory | 211940 kb |
| Host | smart-08bfa855-10e0-46e0-80fc-16a24a34de40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1227217548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1227217548 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3097379290 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 153198120402 ps |
| CPU time | 649.09 seconds |
| Started | Jan 14 12:34:09 PM PST 24 |
| Finished | Jan 14 12:44:59 PM PST 24 |
| Peak memory | 211960 kb |
| Host | smart-372c1c40-6e40-441d-a02a-058911fd20ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3097379290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.3097379290 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.3708628631 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 702217641 ps |
| CPU time | 23.84 seconds |
| Started | Jan 14 12:34:12 PM PST 24 |
| Finished | Jan 14 12:34:37 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-5ebe29b9-5825-4fc4-96db-88322bd82a5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3708628631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.3708628631 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.2945535895 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 132176776 ps |
| CPU time | 16.24 seconds |
| Started | Jan 14 12:34:09 PM PST 24 |
| Finished | Jan 14 12:34:26 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-3a04274d-ef9b-4891-b930-62adc2b98bdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2945535895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2945535895 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.1194957302 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 888546436 ps |
| CPU time | 7.71 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:15 PM PST 24 |
| Peak memory | 204192 kb |
| Host | smart-1ff7429a-64e1-4dc2-a5bf-8b415b775f82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1194957302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1194957302 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.619400543 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 201452776249 ps |
| CPU time | 306.87 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:39:14 PM PST 24 |
| Peak memory | 204812 kb |
| Host | smart-56ecb59c-140a-4340-bdc3-1145acbf64c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=619400543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.619400543 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.503952272 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 44123139748 ps |
| CPU time | 238.96 seconds |
| Started | Jan 14 12:34:13 PM PST 24 |
| Finished | Jan 14 12:38:13 PM PST 24 |
| Peak memory | 204800 kb |
| Host | smart-79544ed1-3357-480c-a06c-a4df4b31121a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=503952272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.503952272 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1598512876 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 111977277 ps |
| CPU time | 11.5 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:19 PM PST 24 |
| Peak memory | 204636 kb |
| Host | smart-2bb4e14e-80cd-4667-9255-b60c7b592178 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598512876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1598512876 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.3582733829 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1460599459 ps |
| CPU time | 32.63 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:40 PM PST 24 |
| Peak memory | 203956 kb |
| Host | smart-edfcde3a-4164-4f1f-b3e2-75120490837f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3582733829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3582733829 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.2163865937 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 63424081 ps |
| CPU time | 2.43 seconds |
| Started | Jan 14 12:34:06 PM PST 24 |
| Finished | Jan 14 12:34:09 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-7ed45190-5e4d-42d0-9863-54a3ea942ec6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2163865937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2163865937 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2397138441 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5718803979 ps |
| CPU time | 34.7 seconds |
| Started | Jan 14 12:34:06 PM PST 24 |
| Finished | Jan 14 12:34:42 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-eccf1458-6900-4f13-b370-0d882ad555ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397138441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2397138441 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2330788678 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4053991803 ps |
| CPU time | 29.98 seconds |
| Started | Jan 14 12:34:04 PM PST 24 |
| Finished | Jan 14 12:34:35 PM PST 24 |
| Peak memory | 203848 kb |
| Host | smart-74ad7a45-135b-49e1-8de3-c75e3d400358 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2330788678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2330788678 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.4230460847 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 51361159 ps |
| CPU time | 2.48 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:10 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-66ab8563-6439-474c-a8ae-4b2019ea5f05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230460847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.4230460847 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.144767486 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1603686088 ps |
| CPU time | 259.51 seconds |
| Started | Jan 14 12:34:10 PM PST 24 |
| Finished | Jan 14 12:38:30 PM PST 24 |
| Peak memory | 211400 kb |
| Host | smart-a443a0c2-66df-421e-9acc-0b8b46c0a4f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=144767486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.144767486 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2520995447 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 4220698385 ps |
| CPU time | 16.65 seconds |
| Started | Jan 14 12:34:08 PM PST 24 |
| Finished | Jan 14 12:34:26 PM PST 24 |
| Peak memory | 203792 kb |
| Host | smart-c31c8b70-3423-4461-9171-902e8f82fdb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2520995447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2520995447 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.943618972 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 54329196 ps |
| CPU time | 15.36 seconds |
| Started | Jan 14 12:34:13 PM PST 24 |
| Finished | Jan 14 12:34:29 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-0f1aefe0-ab31-4004-bc2a-29d8bcd0b5eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=943618972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand _reset.943618972 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1822434401 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 10926642515 ps |
| CPU time | 327.03 seconds |
| Started | Jan 14 12:34:11 PM PST 24 |
| Finished | Jan 14 12:39:39 PM PST 24 |
| Peak memory | 220120 kb |
| Host | smart-ede4249f-6f91-41af-a3c1-81336d1c86cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1822434401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1822434401 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.4244116395 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 167772981 ps |
| CPU time | 5.11 seconds |
| Started | Jan 14 12:34:10 PM PST 24 |
| Finished | Jan 14 12:34:16 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-ff7dcfde-5c3d-4b83-b0be-2aeeee6b2a04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4244116395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.4244116395 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.3865776813 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1277984585 ps |
| CPU time | 29 seconds |
| Started | Jan 14 12:34:12 PM PST 24 |
| Finished | Jan 14 12:34:41 PM PST 24 |
| Peak memory | 205420 kb |
| Host | smart-06d8cc0f-bb90-4ed7-b5ad-b6e1b039e60d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3865776813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3865776813 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1926478033 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 24917385476 ps |
| CPU time | 182.56 seconds |
| Started | Jan 14 12:34:18 PM PST 24 |
| Finished | Jan 14 12:37:22 PM PST 24 |
| Peak memory | 211884 kb |
| Host | smart-97ab9b3f-b14d-4843-b6fd-54e96a14ef6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1926478033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.1926478033 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.621144574 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 338722936 ps |
| CPU time | 15.62 seconds |
| Started | Jan 14 12:34:18 PM PST 24 |
| Finished | Jan 14 12:34:34 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-ef7572cf-5cc6-4bf0-b763-5e427ee851f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=621144574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.621144574 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2534053991 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 24933351 ps |
| CPU time | 1.88 seconds |
| Started | Jan 14 12:34:10 PM PST 24 |
| Finished | Jan 14 12:34:13 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-8deab5d3-b41c-4adc-8128-59f4aaa8e19e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2534053991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2534053991 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.4224791830 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3498794801 ps |
| CPU time | 34.81 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:34:50 PM PST 24 |
| Peak memory | 203880 kb |
| Host | smart-8aee248b-d5fe-4d38-81ce-9be9c389a7ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4224791830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.4224791830 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1560587451 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 97153653102 ps |
| CPU time | 216.23 seconds |
| Started | Jan 14 12:34:08 PM PST 24 |
| Finished | Jan 14 12:37:45 PM PST 24 |
| Peak memory | 205036 kb |
| Host | smart-02529b6b-0e72-4209-82d9-a224d591f184 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560587451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1560587451 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.395282175 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 177210543539 ps |
| CPU time | 389.83 seconds |
| Started | Jan 14 12:34:17 PM PST 24 |
| Finished | Jan 14 12:40:47 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-178ede62-0588-4ab9-9dd5-a6517f254492 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=395282175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.395282175 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2688806354 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 361230057 ps |
| CPU time | 28.97 seconds |
| Started | Jan 14 12:34:08 PM PST 24 |
| Finished | Jan 14 12:34:37 PM PST 24 |
| Peak memory | 211796 kb |
| Host | smart-22b66ff6-b704-4024-b87e-5c212388c29a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688806354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2688806354 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.3080954845 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1450455683 ps |
| CPU time | 19.13 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:34:34 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-f72cdcff-b688-4215-8407-61cca75be17f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3080954845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3080954845 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.125385113 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 214563499 ps |
| CPU time | 3.42 seconds |
| Started | Jan 14 12:34:07 PM PST 24 |
| Finished | Jan 14 12:34:11 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-2503d98a-9af7-461d-9440-1321e8e2682f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=125385113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.125385113 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.835300477 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 5002265125 ps |
| CPU time | 29 seconds |
| Started | Jan 14 12:34:08 PM PST 24 |
| Finished | Jan 14 12:34:38 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-0d8963f1-f6e2-4727-b167-ed91ddd832b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=835300477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.835300477 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3634507375 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 5328311076 ps |
| CPU time | 28.02 seconds |
| Started | Jan 14 12:34:13 PM PST 24 |
| Finished | Jan 14 12:34:42 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-75477199-366b-48ae-bf05-694e473369cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3634507375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3634507375 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.150235189 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 30062122 ps |
| CPU time | 2.07 seconds |
| Started | Jan 14 12:34:11 PM PST 24 |
| Finished | Jan 14 12:34:14 PM PST 24 |
| Peak memory | 203592 kb |
| Host | smart-f5d245b3-69ae-479d-8bc6-5d504c90cd80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150235189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.150235189 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.3085743925 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 28236499941 ps |
| CPU time | 179.71 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:37:14 PM PST 24 |
| Peak memory | 208600 kb |
| Host | smart-3b12f7a8-6a68-44b6-8117-b63e908dc015 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085743925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3085743925 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3947883149 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1967849048 ps |
| CPU time | 61.96 seconds |
| Started | Jan 14 12:34:17 PM PST 24 |
| Finished | Jan 14 12:35:19 PM PST 24 |
| Peak memory | 204688 kb |
| Host | smart-51b88f58-52c9-4e71-83ad-0a3d2d283158 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3947883149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3947883149 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2637231580 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 15568208150 ps |
| CPU time | 492.48 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:42:27 PM PST 24 |
| Peak memory | 220152 kb |
| Host | smart-db04b8b3-ef6b-4f64-b6e9-61399835e825 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2637231580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.2637231580 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1132770615 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 5284666124 ps |
| CPU time | 684.1 seconds |
| Started | Jan 14 12:34:22 PM PST 24 |
| Finished | Jan 14 12:45:47 PM PST 24 |
| Peak memory | 220248 kb |
| Host | smart-66e48e57-46ed-478c-8f9b-912a2faf18d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1132770615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.1132770615 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3682988519 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 879134543 ps |
| CPU time | 14.26 seconds |
| Started | Jan 14 12:34:19 PM PST 24 |
| Finished | Jan 14 12:34:34 PM PST 24 |
| Peak memory | 204828 kb |
| Host | smart-f4050a7a-37ca-47c2-b0d8-2b44f4cb88fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3682988519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3682988519 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.2383340249 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2524034247 ps |
| CPU time | 62.19 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:35:18 PM PST 24 |
| Peak memory | 206652 kb |
| Host | smart-9ef77aaa-787c-4deb-b5a2-afc7b47b202f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2383340249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2383340249 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2234631775 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 208618267231 ps |
| CPU time | 766.35 seconds |
| Started | Jan 14 12:34:16 PM PST 24 |
| Finished | Jan 14 12:47:04 PM PST 24 |
| Peak memory | 207652 kb |
| Host | smart-bfea50ec-524e-4c0c-81b8-cecab5868246 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2234631775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.2234631775 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2872557812 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 385037276 ps |
| CPU time | 14.96 seconds |
| Started | Jan 14 12:34:20 PM PST 24 |
| Finished | Jan 14 12:34:35 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-5b6b5d31-c35f-4177-a135-961105cabd32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2872557812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2872557812 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.2878171816 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 790240423 ps |
| CPU time | 10 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:34:25 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-493a88b0-8d56-4c70-a64e-1fa5e8f72572 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2878171816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2878171816 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.1815505415 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2118503083 ps |
| CPU time | 28.85 seconds |
| Started | Jan 14 12:34:16 PM PST 24 |
| Finished | Jan 14 12:34:45 PM PST 24 |
| Peak memory | 211764 kb |
| Host | smart-4c5f3f02-3140-4405-abdf-7cccc7be00ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1815505415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1815505415 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1311797726 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 100657515775 ps |
| CPU time | 241.63 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:38:16 PM PST 24 |
| Peak memory | 205208 kb |
| Host | smart-8b95468f-a642-43a0-8aa0-b81aa37f9b67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311797726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1311797726 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3456086827 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 48240300865 ps |
| CPU time | 167.52 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:37:03 PM PST 24 |
| Peak memory | 204992 kb |
| Host | smart-0ffab34c-52e9-48bc-9cde-de2fa39b69b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3456086827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3456086827 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3039716473 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 231021561 ps |
| CPU time | 17.9 seconds |
| Started | Jan 14 12:34:14 PM PST 24 |
| Finished | Jan 14 12:34:32 PM PST 24 |
| Peak memory | 204816 kb |
| Host | smart-3f407b0c-46c7-49d8-9498-86d56c792e10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039716473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3039716473 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.188026635 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 852551102 ps |
| CPU time | 20.49 seconds |
| Started | Jan 14 12:34:17 PM PST 24 |
| Finished | Jan 14 12:34:38 PM PST 24 |
| Peak memory | 204028 kb |
| Host | smart-e4fbbe2e-6d71-438f-b922-7f03c249d1cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=188026635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.188026635 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.1157967561 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 25824497 ps |
| CPU time | 2.22 seconds |
| Started | Jan 14 12:34:16 PM PST 24 |
| Finished | Jan 14 12:34:19 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-45381ee1-16b6-4eaa-99a8-3440ce3d95fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1157967561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1157967561 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.120643117 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 11232886787 ps |
| CPU time | 27.46 seconds |
| Started | Jan 14 12:34:15 PM PST 24 |
| Finished | Jan 14 12:34:43 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-338d7261-9144-403b-ac7e-fd1c59415db8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=120643117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.120643117 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2372902932 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 4270841128 ps |
| CPU time | 27.85 seconds |
| Started | Jan 14 12:34:15 PM PST 24 |
| Finished | Jan 14 12:34:44 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-30a7a471-9e8e-49a3-9cf9-f9bea0afaff0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2372902932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2372902932 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1285430713 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30714434 ps |
| CPU time | 2.19 seconds |
| Started | Jan 14 12:34:17 PM PST 24 |
| Finished | Jan 14 12:34:20 PM PST 24 |
| Peak memory | 203616 kb |
| Host | smart-901af415-d7ba-4140-9306-f952c1b1546f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285430713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1285430713 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1237015839 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1215907877 ps |
| CPU time | 102.7 seconds |
| Started | Jan 14 12:34:15 PM PST 24 |
| Finished | Jan 14 12:35:59 PM PST 24 |
| Peak memory | 207236 kb |
| Host | smart-3dbe545f-684b-4808-8aa6-2367dfc9f00a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1237015839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1237015839 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.3677833166 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 351450738 ps |
| CPU time | 80.45 seconds |
| Started | Jan 14 12:34:20 PM PST 24 |
| Finished | Jan 14 12:35:42 PM PST 24 |
| Peak memory | 208132 kb |
| Host | smart-4d3a69c8-ab07-48b5-a56f-df244875af79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3677833166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.3677833166 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3844569026 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9809803872 ps |
| CPU time | 415.42 seconds |
| Started | Jan 14 12:34:17 PM PST 24 |
| Finished | Jan 14 12:41:13 PM PST 24 |
| Peak memory | 220068 kb |
| Host | smart-1c7347c1-59b0-441f-855b-1239c939981e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3844569026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.3844569026 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.118290830 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 63677555 ps |
| CPU time | 6.68 seconds |
| Started | Jan 14 12:34:13 PM PST 24 |
| Finished | Jan 14 12:34:21 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-c78e4eb9-4a4a-44ce-8ba3-8ebdff3661c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=118290830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.118290830 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.3585767304 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3868084630 ps |
| CPU time | 62.23 seconds |
| Started | Jan 14 12:32:38 PM PST 24 |
| Finished | Jan 14 12:33:41 PM PST 24 |
| Peak memory | 211908 kb |
| Host | smart-94fc47f2-e1b9-4985-8444-9a97b84997ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3585767304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.3585767304 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2004026855 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 67722342834 ps |
| CPU time | 498.9 seconds |
| Started | Jan 14 12:32:41 PM PST 24 |
| Finished | Jan 14 12:41:04 PM PST 24 |
| Peak memory | 206148 kb |
| Host | smart-757bc48e-fc02-488b-acc4-334b19f87d2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2004026855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.2004026855 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1001430896 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 31335183 ps |
| CPU time | 4.9 seconds |
| Started | Jan 14 12:32:39 PM PST 24 |
| Finished | Jan 14 12:32:49 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-15c68cbb-46c6-4e18-8ebc-60eb7a7bcb26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1001430896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1001430896 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.2371103709 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 170990384 ps |
| CPU time | 11.47 seconds |
| Started | Jan 14 12:32:39 PM PST 24 |
| Finished | Jan 14 12:32:55 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-958b956f-dc51-4591-8c8a-615e8c163b7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2371103709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2371103709 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.4087869232 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 303192530 ps |
| CPU time | 5.6 seconds |
| Started | Jan 14 12:32:31 PM PST 24 |
| Finished | Jan 14 12:32:38 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-aa233f68-cf56-4f2a-86d9-272227b187f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4087869232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.4087869232 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.2108243849 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 15479900680 ps |
| CPU time | 55.1 seconds |
| Started | Jan 14 12:32:32 PM PST 24 |
| Finished | Jan 14 12:33:28 PM PST 24 |
| Peak memory | 204932 kb |
| Host | smart-d0c38297-b190-4202-a782-37e94d4eae51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108243849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2108243849 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.1154690175 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 21810288768 ps |
| CPU time | 200.4 seconds |
| Started | Jan 14 12:32:38 PM PST 24 |
| Finished | Jan 14 12:36:00 PM PST 24 |
| Peak memory | 204800 kb |
| Host | smart-119375cb-c287-4cf5-96cb-cde253a78d4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1154690175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1154690175 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2611159780 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 131000688 ps |
| CPU time | 12.13 seconds |
| Started | Jan 14 12:32:33 PM PST 24 |
| Finished | Jan 14 12:32:46 PM PST 24 |
| Peak memory | 211800 kb |
| Host | smart-1eb27dce-01ac-4510-be2a-d31e2caa224c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611159780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2611159780 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.451567084 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 736524496 ps |
| CPU time | 18.63 seconds |
| Started | Jan 14 12:32:34 PM PST 24 |
| Finished | Jan 14 12:32:53 PM PST 24 |
| Peak memory | 204052 kb |
| Host | smart-e1961e5b-e6ad-416a-b698-a3d77fd05ad7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=451567084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.451567084 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2153276686 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 158816619 ps |
| CPU time | 3.27 seconds |
| Started | Jan 14 12:32:27 PM PST 24 |
| Finished | Jan 14 12:32:32 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-8a24fe07-b5b1-4e01-9dd7-f19bf846d9c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2153276686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2153276686 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1683126311 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 19844044428 ps |
| CPU time | 35.25 seconds |
| Started | Jan 14 12:32:34 PM PST 24 |
| Finished | Jan 14 12:33:10 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-b3bb1c61-acf6-4a1e-96dc-c8c3ba3d9b2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683126311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1683126311 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.995355299 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 10937907909 ps |
| CPU time | 29.43 seconds |
| Started | Jan 14 12:32:27 PM PST 24 |
| Finished | Jan 14 12:32:57 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-6b2d7682-c4ef-4485-8f8a-f874d1e6325e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=995355299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.995355299 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.501449769 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 35975222 ps |
| CPU time | 2.24 seconds |
| Started | Jan 14 12:32:27 PM PST 24 |
| Finished | Jan 14 12:32:30 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-c206892d-9e8a-4d4d-aec8-dc6f8f003694 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501449769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.501449769 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.3412419709 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 10528698386 ps |
| CPU time | 343.41 seconds |
| Started | Jan 14 12:32:34 PM PST 24 |
| Finished | Jan 14 12:38:19 PM PST 24 |
| Peak memory | 207572 kb |
| Host | smart-8cfbc6d8-af20-4bda-91d8-77cf3694dfce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3412419709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3412419709 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.533491511 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12025467116 ps |
| CPU time | 219.62 seconds |
| Started | Jan 14 12:32:39 PM PST 24 |
| Finished | Jan 14 12:36:24 PM PST 24 |
| Peak memory | 208488 kb |
| Host | smart-96725cca-37a4-48fd-b855-b1a720c7a205 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=533491511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.533491511 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.680296676 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 4318792533 ps |
| CPU time | 468.51 seconds |
| Started | Jan 14 12:32:34 PM PST 24 |
| Finished | Jan 14 12:40:24 PM PST 24 |
| Peak memory | 208552 kb |
| Host | smart-8e1acfc0-0377-41cd-9581-aceff9d6c03c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=680296676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_ reset.680296676 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1143806958 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 430843205 ps |
| CPU time | 89.48 seconds |
| Started | Jan 14 12:32:34 PM PST 24 |
| Finished | Jan 14 12:34:04 PM PST 24 |
| Peak memory | 209492 kb |
| Host | smart-78804179-84bd-49b7-845c-fec362dd9d75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1143806958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.1143806958 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.7380956 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 82278256 ps |
| CPU time | 9 seconds |
| Started | Jan 14 12:32:35 PM PST 24 |
| Finished | Jan 14 12:32:44 PM PST 24 |
| Peak memory | 211984 kb |
| Host | smart-45aad66d-3931-43fc-b360-7bec2c2a5c1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=7380956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.7380956 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.1233343181 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 308896584 ps |
| CPU time | 17.86 seconds |
| Started | Jan 14 12:34:17 PM PST 24 |
| Finished | Jan 14 12:34:35 PM PST 24 |
| Peak memory | 204668 kb |
| Host | smart-a01d80f6-6b10-4e59-8aa6-1f23b482be27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1233343181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1233343181 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.181718595 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 13591790914 ps |
| CPU time | 81.83 seconds |
| Started | Jan 14 12:34:16 PM PST 24 |
| Finished | Jan 14 12:35:39 PM PST 24 |
| Peak memory | 211860 kb |
| Host | smart-0c2e7a3d-27d1-4cb5-aac5-560586e34fcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=181718595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo w_rsp.181718595 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3023248522 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 50722158 ps |
| CPU time | 5.88 seconds |
| Started | Jan 14 12:34:19 PM PST 24 |
| Finished | Jan 14 12:34:25 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-c6bb6b11-bdb3-4a9f-a47a-04f70cd42e5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3023248522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3023248522 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.4048450435 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 295784863 ps |
| CPU time | 10.8 seconds |
| Started | Jan 14 12:34:23 PM PST 24 |
| Finished | Jan 14 12:34:35 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-a41a5376-fd6a-41ee-901a-2714a1a3886c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4048450435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.4048450435 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1673611637 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 13969210662 ps |
| CPU time | 38.36 seconds |
| Started | Jan 14 12:34:19 PM PST 24 |
| Finished | Jan 14 12:34:58 PM PST 24 |
| Peak memory | 204836 kb |
| Host | smart-69f8b500-5562-4341-9745-4a724dfbf6c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673611637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1673611637 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2422421012 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 27273761227 ps |
| CPU time | 220.55 seconds |
| Started | Jan 14 12:34:18 PM PST 24 |
| Finished | Jan 14 12:37:59 PM PST 24 |
| Peak memory | 205260 kb |
| Host | smart-e36623dc-d941-46f4-a3da-b95936deb2e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2422421012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2422421012 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3531533047 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 67969941 ps |
| CPU time | 9.1 seconds |
| Started | Jan 14 12:34:15 PM PST 24 |
| Finished | Jan 14 12:34:25 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-9b2f8424-0dc3-4783-8e48-5659b41db2ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531533047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3531533047 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.3601466911 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 9448966825 ps |
| CPU time | 33.97 seconds |
| Started | Jan 14 12:34:17 PM PST 24 |
| Finished | Jan 14 12:34:52 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-16d5d598-24d5-437c-9e37-b201ca4e403d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3601466911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3601466911 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.3633659133 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 437819758 ps |
| CPU time | 3.26 seconds |
| Started | Jan 14 12:34:17 PM PST 24 |
| Finished | Jan 14 12:34:21 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-fd67d50a-053c-4600-9d91-0d102d38f2ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3633659133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3633659133 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1480304430 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 5265586569 ps |
| CPU time | 25.96 seconds |
| Started | Jan 14 12:34:15 PM PST 24 |
| Finished | Jan 14 12:34:42 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-fe95b5f1-aa91-47a9-9bd5-54822b43e7e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480304430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1480304430 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.485022383 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 6697000123 ps |
| CPU time | 26.85 seconds |
| Started | Jan 14 12:34:15 PM PST 24 |
| Finished | Jan 14 12:34:43 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-f1cd1877-62a5-4d35-ae57-5f5ce80fac01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=485022383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.485022383 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3854006452 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 29642742 ps |
| CPU time | 2.36 seconds |
| Started | Jan 14 12:34:20 PM PST 24 |
| Finished | Jan 14 12:34:23 PM PST 24 |
| Peak memory | 203564 kb |
| Host | smart-52d0de36-f565-4d5b-9342-f2183ce2a6ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854006452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3854006452 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.2111710432 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 207393940 ps |
| CPU time | 22.13 seconds |
| Started | Jan 14 12:34:16 PM PST 24 |
| Finished | Jan 14 12:34:39 PM PST 24 |
| Peak memory | 211936 kb |
| Host | smart-28c1ae89-58a9-4290-af7d-a3bb9f01c389 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2111710432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2111710432 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3805046469 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2670465364 ps |
| CPU time | 225.82 seconds |
| Started | Jan 14 12:34:15 PM PST 24 |
| Finished | Jan 14 12:38:02 PM PST 24 |
| Peak memory | 207324 kb |
| Host | smart-beb11d81-196c-4e38-8207-358aa010d750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3805046469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3805046469 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1937269188 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 19342096841 ps |
| CPU time | 244.33 seconds |
| Started | Jan 14 12:34:23 PM PST 24 |
| Finished | Jan 14 12:38:28 PM PST 24 |
| Peak memory | 208632 kb |
| Host | smart-78d28798-8fb7-404d-8cd7-b882024b02a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1937269188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.1937269188 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3069184360 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 656028020 ps |
| CPU time | 181.03 seconds |
| Started | Jan 14 12:34:20 PM PST 24 |
| Finished | Jan 14 12:37:22 PM PST 24 |
| Peak memory | 210960 kb |
| Host | smart-c4607706-e978-45c8-b0a1-396985430231 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3069184360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.3069184360 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1273740260 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 687807627 ps |
| CPU time | 25.81 seconds |
| Started | Jan 14 12:34:19 PM PST 24 |
| Finished | Jan 14 12:34:46 PM PST 24 |
| Peak memory | 211868 kb |
| Host | smart-64eaffc4-5dfc-4a57-ac3f-c6c7bf83581d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1273740260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1273740260 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3248054343 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 374285888 ps |
| CPU time | 30.5 seconds |
| Started | Jan 14 12:34:19 PM PST 24 |
| Finished | Jan 14 12:34:50 PM PST 24 |
| Peak memory | 205332 kb |
| Host | smart-58af8918-1fba-4960-bdbf-f321284c44c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3248054343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3248054343 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3308559835 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 35003032822 ps |
| CPU time | 254.81 seconds |
| Started | Jan 14 12:34:19 PM PST 24 |
| Finished | Jan 14 12:38:34 PM PST 24 |
| Peak memory | 211888 kb |
| Host | smart-d0c5defe-0bd9-4136-b58e-80de6b5a7544 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3308559835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.3308559835 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1423026676 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 211190845 ps |
| CPU time | 9 seconds |
| Started | Jan 14 12:34:22 PM PST 24 |
| Finished | Jan 14 12:34:32 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-59f25e4c-0431-4dd0-86d0-8a6726c9d3ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1423026676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1423026676 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.3371564317 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2213151347 ps |
| CPU time | 28.43 seconds |
| Started | Jan 14 12:34:22 PM PST 24 |
| Finished | Jan 14 12:34:52 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-25cc2d34-c13d-4cf9-9dea-b0e80fed844f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3371564317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3371564317 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.560160568 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1253478554 ps |
| CPU time | 33.05 seconds |
| Started | Jan 14 12:34:22 PM PST 24 |
| Finished | Jan 14 12:34:56 PM PST 24 |
| Peak memory | 211872 kb |
| Host | smart-a4dad1db-b06c-49ec-9fc4-b7f1c5fa57ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=560160568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.560160568 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.4155378216 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 9159009083 ps |
| CPU time | 38.21 seconds |
| Started | Jan 14 12:34:19 PM PST 24 |
| Finished | Jan 14 12:34:58 PM PST 24 |
| Peak memory | 204912 kb |
| Host | smart-e760bde8-3036-4dc1-ac16-b298c35a179a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155378216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.4155378216 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.6864565 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 19847306651 ps |
| CPU time | 146.73 seconds |
| Started | Jan 14 12:34:24 PM PST 24 |
| Finished | Jan 14 12:36:52 PM PST 24 |
| Peak memory | 211856 kb |
| Host | smart-f2b92d54-2831-4331-97ca-ec621ffd1b21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=6864565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.6864565 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3554386602 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 125320930 ps |
| CPU time | 12.7 seconds |
| Started | Jan 14 12:34:18 PM PST 24 |
| Finished | Jan 14 12:34:31 PM PST 24 |
| Peak memory | 211776 kb |
| Host | smart-22bf3ebd-eae0-4ced-9c3f-fec77c393d29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554386602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3554386602 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.1342838333 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 43871604 ps |
| CPU time | 4.13 seconds |
| Started | Jan 14 12:34:23 PM PST 24 |
| Finished | Jan 14 12:34:28 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-afc2bb6d-2056-4eba-a041-56988083ddc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1342838333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1342838333 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.801686841 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 61465691 ps |
| CPU time | 2.13 seconds |
| Started | Jan 14 12:34:20 PM PST 24 |
| Finished | Jan 14 12:34:23 PM PST 24 |
| Peak memory | 203176 kb |
| Host | smart-1a8a1a21-b399-4d4e-8f08-e96322e44ee3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=801686841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.801686841 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2257525815 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 4877265890 ps |
| CPU time | 26.61 seconds |
| Started | Jan 14 12:34:18 PM PST 24 |
| Finished | Jan 14 12:34:46 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-6e4d1b24-18ce-4040-88c2-646ed304cd33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257525815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2257525815 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3124021104 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 11670583853 ps |
| CPU time | 38.98 seconds |
| Started | Jan 14 12:34:21 PM PST 24 |
| Finished | Jan 14 12:35:01 PM PST 24 |
| Peak memory | 203848 kb |
| Host | smart-1bacd450-dced-42e3-9e59-04da89dfe066 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3124021104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3124021104 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2917478855 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 27540309 ps |
| CPU time | 1.9 seconds |
| Started | Jan 14 12:34:21 PM PST 24 |
| Finished | Jan 14 12:34:23 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-314e4d40-a30c-4d63-b7b7-d4b25a88638d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917478855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2917478855 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2405865431 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 27066084284 ps |
| CPU time | 228.14 seconds |
| Started | Jan 14 12:34:24 PM PST 24 |
| Finished | Jan 14 12:38:13 PM PST 24 |
| Peak memory | 210240 kb |
| Host | smart-d4e832b3-8cd3-4319-add0-3aaf8c8318bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2405865431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2405865431 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3739770567 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2865364737 ps |
| CPU time | 335.43 seconds |
| Started | Jan 14 12:34:20 PM PST 24 |
| Finished | Jan 14 12:39:56 PM PST 24 |
| Peak memory | 211604 kb |
| Host | smart-a32593f9-3b80-45dc-b123-b3c739a20b84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3739770567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.3739770567 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.4210150883 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 970320553 ps |
| CPU time | 281.64 seconds |
| Started | Jan 14 12:34:21 PM PST 24 |
| Finished | Jan 14 12:39:03 PM PST 24 |
| Peak memory | 220008 kb |
| Host | smart-1ba50809-31fd-4d37-98d6-3def97c3aca3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4210150883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.4210150883 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.3350242365 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 80435078 ps |
| CPU time | 10.44 seconds |
| Started | Jan 14 12:34:22 PM PST 24 |
| Finished | Jan 14 12:34:33 PM PST 24 |
| Peak memory | 205228 kb |
| Host | smart-62a1b866-963e-47e2-b2c4-fdf67566e1a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3350242365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3350242365 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2441045686 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 196764478 ps |
| CPU time | 22.76 seconds |
| Started | Jan 14 12:34:27 PM PST 24 |
| Finished | Jan 14 12:34:50 PM PST 24 |
| Peak memory | 205472 kb |
| Host | smart-c639728f-278c-4bc0-bf39-b31aaad04f01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2441045686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2441045686 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.664628650 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 83460351108 ps |
| CPU time | 360.15 seconds |
| Started | Jan 14 12:34:28 PM PST 24 |
| Finished | Jan 14 12:40:29 PM PST 24 |
| Peak memory | 206360 kb |
| Host | smart-20971f34-d41b-40e3-9fb9-27d9e9f2b29b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=664628650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slo w_rsp.664628650 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.1536278392 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 573983540 ps |
| CPU time | 22.23 seconds |
| Started | Jan 14 12:34:22 PM PST 24 |
| Finished | Jan 14 12:34:44 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-eebeb222-5fb9-45e0-815d-0f937701e5df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1536278392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.1536278392 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.942016795 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 153516112 ps |
| CPU time | 11.95 seconds |
| Started | Jan 14 12:34:27 PM PST 24 |
| Finished | Jan 14 12:34:39 PM PST 24 |
| Peak memory | 203600 kb |
| Host | smart-9affa7ac-b1bf-47ce-b492-5922eced1cf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=942016795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.942016795 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.1721476064 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 139307628 ps |
| CPU time | 5.2 seconds |
| Started | Jan 14 12:34:27 PM PST 24 |
| Finished | Jan 14 12:34:32 PM PST 24 |
| Peak memory | 211828 kb |
| Host | smart-b808eedd-2aba-4469-9057-ac792267670a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1721476064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1721476064 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.492884754 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 74493827130 ps |
| CPU time | 192.7 seconds |
| Started | Jan 14 12:34:22 PM PST 24 |
| Finished | Jan 14 12:37:36 PM PST 24 |
| Peak memory | 211844 kb |
| Host | smart-1ce10b04-6650-45a3-8e2c-7ee5c10b8c26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=492884754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.492884754 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2225355702 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 91313633764 ps |
| CPU time | 226.38 seconds |
| Started | Jan 14 12:34:25 PM PST 24 |
| Finished | Jan 14 12:38:12 PM PST 24 |
| Peak memory | 205208 kb |
| Host | smart-1630e532-2b94-4df8-9c7c-0cb957e96baf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2225355702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2225355702 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.376230117 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 805143165 ps |
| CPU time | 17.98 seconds |
| Started | Jan 14 12:34:22 PM PST 24 |
| Finished | Jan 14 12:34:41 PM PST 24 |
| Peak memory | 204740 kb |
| Host | smart-b25d416a-cbbb-4686-927c-feb22619ad6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376230117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.376230117 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.2462367225 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 1206608742 ps |
| CPU time | 19.51 seconds |
| Started | Jan 14 12:34:23 PM PST 24 |
| Finished | Jan 14 12:34:43 PM PST 24 |
| Peak memory | 204140 kb |
| Host | smart-193b4576-dc47-4066-adeb-6d222968e31e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2462367225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2462367225 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.3792901113 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 169763590 ps |
| CPU time | 3.66 seconds |
| Started | Jan 14 12:34:19 PM PST 24 |
| Finished | Jan 14 12:34:24 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-90ffbf84-bc1e-4edd-b070-2066a33d8d93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3792901113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3792901113 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3637285289 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 39134111554 ps |
| CPU time | 46.65 seconds |
| Started | Jan 14 12:34:22 PM PST 24 |
| Finished | Jan 14 12:35:10 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-9e53b77e-2259-4363-adba-89f1d45ac80c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637285289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3637285289 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.931476988 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 7982763887 ps |
| CPU time | 30.59 seconds |
| Started | Jan 14 12:34:21 PM PST 24 |
| Finished | Jan 14 12:34:52 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-636ebb34-b8c1-4539-9ec2-99120a9fe686 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=931476988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.931476988 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.71584139 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 189748258 ps |
| CPU time | 2.54 seconds |
| Started | Jan 14 12:34:25 PM PST 24 |
| Finished | Jan 14 12:34:28 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-472f3a5d-2a99-4ad5-ba55-fd39a4f27fe2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71584139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.71584139 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1613129503 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1467236440 ps |
| CPU time | 81.56 seconds |
| Started | Jan 14 12:34:28 PM PST 24 |
| Finished | Jan 14 12:35:50 PM PST 24 |
| Peak memory | 206804 kb |
| Host | smart-80ace2e2-12a2-49a9-89ce-02f8eb9b4158 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1613129503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1613129503 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1633968590 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 197300747 ps |
| CPU time | 25.9 seconds |
| Started | Jan 14 12:34:24 PM PST 24 |
| Finished | Jan 14 12:34:51 PM PST 24 |
| Peak memory | 204764 kb |
| Host | smart-c97a7df1-d32a-40bc-a45f-f878637ad4bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1633968590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1633968590 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1569215727 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 876293084 ps |
| CPU time | 249.11 seconds |
| Started | Jan 14 12:34:22 PM PST 24 |
| Finished | Jan 14 12:38:32 PM PST 24 |
| Peak memory | 208896 kb |
| Host | smart-217f4bcf-128b-4269-86df-7d041df475f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1569215727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1569215727 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1674796690 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 666483948 ps |
| CPU time | 213.85 seconds |
| Started | Jan 14 12:34:21 PM PST 24 |
| Finished | Jan 14 12:37:56 PM PST 24 |
| Peak memory | 220084 kb |
| Host | smart-b87d5e7b-d1b1-45e9-a1a1-43aa216f2fb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1674796690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.1674796690 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.104288888 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 862866195 ps |
| CPU time | 27.47 seconds |
| Started | Jan 14 12:34:24 PM PST 24 |
| Finished | Jan 14 12:34:52 PM PST 24 |
| Peak memory | 205020 kb |
| Host | smart-aefeb50f-b818-4c98-886a-946ec33b6114 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=104288888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.104288888 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2881293325 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 262617276 ps |
| CPU time | 22.35 seconds |
| Started | Jan 14 12:34:26 PM PST 24 |
| Finished | Jan 14 12:34:48 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-9b358fc3-095e-41ea-bad8-57f3dde6f541 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2881293325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2881293325 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.4247830095 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 78155140255 ps |
| CPU time | 209.83 seconds |
| Started | Jan 14 12:34:24 PM PST 24 |
| Finished | Jan 14 12:37:54 PM PST 24 |
| Peak memory | 206184 kb |
| Host | smart-cda57efc-5e8c-4f60-b571-84bc95f74c47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4247830095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.4247830095 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3834371147 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 330690082 ps |
| CPU time | 10.25 seconds |
| Started | Jan 14 12:34:29 PM PST 24 |
| Finished | Jan 14 12:34:41 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-b021bb54-fcfa-43f9-82bd-e8d394006e79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3834371147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3834371147 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.1788403405 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2649661322 ps |
| CPU time | 31.81 seconds |
| Started | Jan 14 12:34:26 PM PST 24 |
| Finished | Jan 14 12:34:58 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-8340286c-9c0a-4e8f-ada6-b2812de290b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1788403405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1788403405 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.3236001460 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1203434665 ps |
| CPU time | 40.58 seconds |
| Started | Jan 14 12:34:27 PM PST 24 |
| Finished | Jan 14 12:35:08 PM PST 24 |
| Peak memory | 211860 kb |
| Host | smart-0d53395c-6f76-445d-9329-a1955bd68189 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3236001460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3236001460 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.408933063 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 281183444468 ps |
| CPU time | 348.45 seconds |
| Started | Jan 14 12:34:24 PM PST 24 |
| Finished | Jan 14 12:40:13 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-d969c580-bd05-435e-bd19-a4f3d73c114e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=408933063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.408933063 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.582636371 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 179057730258 ps |
| CPU time | 347.29 seconds |
| Started | Jan 14 12:34:29 PM PST 24 |
| Finished | Jan 14 12:40:18 PM PST 24 |
| Peak memory | 211956 kb |
| Host | smart-a6cbcfc6-0717-4d7c-9fb4-dae2c63f91ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=582636371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.582636371 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.32324132 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 77136432 ps |
| CPU time | 8.49 seconds |
| Started | Jan 14 12:34:26 PM PST 24 |
| Finished | Jan 14 12:34:35 PM PST 24 |
| Peak memory | 211764 kb |
| Host | smart-12e84e9a-da16-4bb9-9e79-a506d5184a4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32324132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.32324132 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.1089482955 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1491847346 ps |
| CPU time | 27.38 seconds |
| Started | Jan 14 12:34:27 PM PST 24 |
| Finished | Jan 14 12:34:55 PM PST 24 |
| Peak memory | 204048 kb |
| Host | smart-c19c6f08-6bda-444e-9fc0-f17afc819fb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1089482955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1089482955 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.1178655765 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 23184091 ps |
| CPU time | 2.33 seconds |
| Started | Jan 14 12:34:26 PM PST 24 |
| Finished | Jan 14 12:34:29 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-243b8432-12b5-4466-b6ae-15ed0c5a45bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1178655765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1178655765 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.3558248349 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 16351632719 ps |
| CPU time | 28.72 seconds |
| Started | Jan 14 12:34:24 PM PST 24 |
| Finished | Jan 14 12:34:54 PM PST 24 |
| Peak memory | 203852 kb |
| Host | smart-303dc124-df41-44e1-9a4e-a66f13816d79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558248349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3558248349 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3148278323 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4831678789 ps |
| CPU time | 23.44 seconds |
| Started | Jan 14 12:34:27 PM PST 24 |
| Finished | Jan 14 12:34:51 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-10198c0b-56a4-4871-895b-7c11af389f79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3148278323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3148278323 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.749217940 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 32047733 ps |
| CPU time | 2.55 seconds |
| Started | Jan 14 12:34:25 PM PST 24 |
| Finished | Jan 14 12:34:28 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-7d98c71f-e0ac-4192-91d6-05b1a327f414 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749217940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.749217940 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.1016044974 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 11132018145 ps |
| CPU time | 122.08 seconds |
| Started | Jan 14 12:34:31 PM PST 24 |
| Finished | Jan 14 12:36:37 PM PST 24 |
| Peak memory | 207404 kb |
| Host | smart-b9ae2626-2df7-4510-8ae9-609fd4017180 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1016044974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1016044974 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1582790826 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 374494252 ps |
| CPU time | 146.52 seconds |
| Started | Jan 14 12:34:33 PM PST 24 |
| Finished | Jan 14 12:37:07 PM PST 24 |
| Peak memory | 208324 kb |
| Host | smart-52322e94-d2e3-47a7-8f64-94ad78b90fa3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1582790826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.1582790826 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2035458669 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 10409014281 ps |
| CPU time | 518.72 seconds |
| Started | Jan 14 12:34:32 PM PST 24 |
| Finished | Jan 14 12:43:19 PM PST 24 |
| Peak memory | 220396 kb |
| Host | smart-a26b022c-ff3d-4127-b56c-0c57f8fbfe54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2035458669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.2035458669 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3376989634 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 72717429 ps |
| CPU time | 11.68 seconds |
| Started | Jan 14 12:34:28 PM PST 24 |
| Finished | Jan 14 12:34:40 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-7c48dd67-7715-4d08-8d38-b51b6252fe23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3376989634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3376989634 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1437286366 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 228594795 ps |
| CPU time | 18.6 seconds |
| Started | Jan 14 12:34:31 PM PST 24 |
| Finished | Jan 14 12:34:53 PM PST 24 |
| Peak memory | 205500 kb |
| Host | smart-65a35a46-a5f1-48dd-b240-3cd704050f0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1437286366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1437286366 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2002834905 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 22761596686 ps |
| CPU time | 202.04 seconds |
| Started | Jan 14 12:34:29 PM PST 24 |
| Finished | Jan 14 12:37:53 PM PST 24 |
| Peak memory | 206312 kb |
| Host | smart-35a9be82-1fae-4680-a16e-9fd035b6c471 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2002834905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.2002834905 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2998139072 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 628390292 ps |
| CPU time | 15.21 seconds |
| Started | Jan 14 12:34:35 PM PST 24 |
| Finished | Jan 14 12:34:57 PM PST 24 |
| Peak memory | 202832 kb |
| Host | smart-914a5568-4f39-4bf0-af5d-77db91ff0f16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2998139072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2998139072 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.2702350240 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 219820122 ps |
| CPU time | 23.16 seconds |
| Started | Jan 14 12:34:36 PM PST 24 |
| Finished | Jan 14 12:35:05 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-8d8dfa0b-0cf0-4125-90d4-9d96597dfdf4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2702350240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2702350240 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.4016976445 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 1383066448 ps |
| CPU time | 38.47 seconds |
| Started | Jan 14 12:34:33 PM PST 24 |
| Finished | Jan 14 12:35:19 PM PST 24 |
| Peak memory | 211852 kb |
| Host | smart-c57bdda3-f984-4483-a26a-163c9135179c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4016976445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.4016976445 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.393198941 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 19250334987 ps |
| CPU time | 91.09 seconds |
| Started | Jan 14 12:34:33 PM PST 24 |
| Finished | Jan 14 12:36:12 PM PST 24 |
| Peak memory | 211956 kb |
| Host | smart-e06aa48f-c83e-4e46-a02f-137bf075bfa3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=393198941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.393198941 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1009729431 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 39631915229 ps |
| CPU time | 146.55 seconds |
| Started | Jan 14 12:34:32 PM PST 24 |
| Finished | Jan 14 12:37:07 PM PST 24 |
| Peak memory | 211940 kb |
| Host | smart-a4d3fba1-e362-4374-94a8-20e9c0ee9e14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1009729431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1009729431 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.359270214 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 108047738 ps |
| CPU time | 11.7 seconds |
| Started | Jan 14 12:34:33 PM PST 24 |
| Finished | Jan 14 12:34:52 PM PST 24 |
| Peak memory | 211788 kb |
| Host | smart-7762bd7a-8354-41cd-aff9-37ae7b567cb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359270214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.359270214 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.3950558553 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 794338459 ps |
| CPU time | 11.85 seconds |
| Started | Jan 14 12:34:36 PM PST 24 |
| Finished | Jan 14 12:34:54 PM PST 24 |
| Peak memory | 204020 kb |
| Host | smart-334e9d37-2643-4a46-b7e8-b728956ae4e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3950558553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3950558553 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.1783951917 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 678590535 ps |
| CPU time | 4.12 seconds |
| Started | Jan 14 12:34:32 PM PST 24 |
| Finished | Jan 14 12:34:45 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-bd24e0bf-3a08-4941-861e-3d4ccd8113f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1783951917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1783951917 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2324596207 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 8748374657 ps |
| CPU time | 34.37 seconds |
| Started | Jan 14 12:34:30 PM PST 24 |
| Finished | Jan 14 12:35:06 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-adc3fa2f-e22d-4c4a-8d2c-597d04204f68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324596207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2324596207 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1624946304 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3894322948 ps |
| CPU time | 22.33 seconds |
| Started | Jan 14 12:34:34 PM PST 24 |
| Finished | Jan 14 12:35:03 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-28e44482-1042-4bda-8aa9-951b24151c11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1624946304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1624946304 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.374474543 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 51319423 ps |
| CPU time | 2.04 seconds |
| Started | Jan 14 12:34:34 PM PST 24 |
| Finished | Jan 14 12:34:43 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-c01782aa-3db1-4b8a-9524-2a94667da82f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374474543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.374474543 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3288992786 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1990961823 ps |
| CPU time | 188.92 seconds |
| Started | Jan 14 12:34:33 PM PST 24 |
| Finished | Jan 14 12:37:49 PM PST 24 |
| Peak memory | 208992 kb |
| Host | smart-ad678658-46e1-4c3d-8908-c2efbceb9506 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3288992786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3288992786 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2556076634 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 571418127 ps |
| CPU time | 35.42 seconds |
| Started | Jan 14 12:34:36 PM PST 24 |
| Finished | Jan 14 12:35:17 PM PST 24 |
| Peak memory | 211760 kb |
| Host | smart-3ac7b8b0-8879-48e0-b1d7-42a84863e874 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2556076634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2556076634 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3580122883 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 485484734 ps |
| CPU time | 156.43 seconds |
| Started | Jan 14 12:34:41 PM PST 24 |
| Finished | Jan 14 12:37:23 PM PST 24 |
| Peak memory | 208144 kb |
| Host | smart-7495678a-e0a1-48d2-9c59-ba33edfec238 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3580122883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3580122883 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2952361525 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 670072672 ps |
| CPU time | 144.64 seconds |
| Started | Jan 14 12:34:36 PM PST 24 |
| Finished | Jan 14 12:37:06 PM PST 24 |
| Peak memory | 210984 kb |
| Host | smart-03adb2c9-8492-4f0b-bc08-dc5cd2bd5c99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2952361525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.2952361525 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1822044703 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 153663412 ps |
| CPU time | 6.71 seconds |
| Started | Jan 14 12:34:28 PM PST 24 |
| Finished | Jan 14 12:34:37 PM PST 24 |
| Peak memory | 211924 kb |
| Host | smart-f1bcada5-21be-431b-9b59-0bfc424b6fb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1822044703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1822044703 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1658068520 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 928076654 ps |
| CPU time | 17.14 seconds |
| Started | Jan 14 12:34:34 PM PST 24 |
| Finished | Jan 14 12:34:58 PM PST 24 |
| Peak memory | 204292 kb |
| Host | smart-232f225a-2838-4321-9fdf-79246de7ef46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1658068520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1658068520 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2500352611 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 137454315897 ps |
| CPU time | 483.22 seconds |
| Started | Jan 14 12:34:33 PM PST 24 |
| Finished | Jan 14 12:42:44 PM PST 24 |
| Peak memory | 207012 kb |
| Host | smart-3e394a90-e16d-46ca-ae62-b5865a43752b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2500352611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.2500352611 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3676906694 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 151928583 ps |
| CPU time | 14.83 seconds |
| Started | Jan 14 12:34:35 PM PST 24 |
| Finished | Jan 14 12:34:56 PM PST 24 |
| Peak memory | 202596 kb |
| Host | smart-be01f0c6-221b-48fe-8547-b4e134cfe2e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3676906694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3676906694 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.3013220890 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 742080611 ps |
| CPU time | 23.78 seconds |
| Started | Jan 14 12:34:30 PM PST 24 |
| Finished | Jan 14 12:34:55 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-cdc64ce7-ccf9-4b40-8d2e-691eff344a3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3013220890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3013220890 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.3674163739 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 666362357 ps |
| CPU time | 17.9 seconds |
| Started | Jan 14 12:34:36 PM PST 24 |
| Finished | Jan 14 12:35:00 PM PST 24 |
| Peak memory | 204608 kb |
| Host | smart-ce44191d-0c04-4ffb-a3fb-c461ace7cd6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3674163739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3674163739 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.738724623 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 41229662615 ps |
| CPU time | 165.83 seconds |
| Started | Jan 14 12:34:37 PM PST 24 |
| Finished | Jan 14 12:37:28 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-552d7a99-5c79-4b34-817e-bce0184dd54a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=738724623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.738724623 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.399033364 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 73209697884 ps |
| CPU time | 212.38 seconds |
| Started | Jan 14 12:34:36 PM PST 24 |
| Finished | Jan 14 12:38:14 PM PST 24 |
| Peak memory | 211836 kb |
| Host | smart-774b778a-0593-4a00-8879-0496f287f370 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=399033364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.399033364 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.399360099 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 42894439 ps |
| CPU time | 2.17 seconds |
| Started | Jan 14 12:34:31 PM PST 24 |
| Finished | Jan 14 12:34:37 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-883845d5-7540-4c1d-960b-1b8943f03d96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399360099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.399360099 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.3554459496 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 485453906 ps |
| CPU time | 7.92 seconds |
| Started | Jan 14 12:34:34 PM PST 24 |
| Finished | Jan 14 12:34:48 PM PST 24 |
| Peak memory | 203984 kb |
| Host | smart-96540761-ea33-4f59-bc30-34476988fdee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3554459496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3554459496 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.2850713380 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 236670849 ps |
| CPU time | 3.56 seconds |
| Started | Jan 14 12:34:37 PM PST 24 |
| Finished | Jan 14 12:34:45 PM PST 24 |
| Peak memory | 203560 kb |
| Host | smart-6f35590f-d8b1-4729-9fd5-ff6ea5d64dd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2850713380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2850713380 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3889635480 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 8713458715 ps |
| CPU time | 30.96 seconds |
| Started | Jan 14 12:34:35 PM PST 24 |
| Finished | Jan 14 12:35:12 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-0a60b314-360d-47e1-a1d4-6d900c857466 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889635480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3889635480 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.657727373 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 29629085219 ps |
| CPU time | 44.83 seconds |
| Started | Jan 14 12:34:32 PM PST 24 |
| Finished | Jan 14 12:35:25 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-24d0c8d4-dd9d-4a0e-be21-f81f043c94e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=657727373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.657727373 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.263188600 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 40072890 ps |
| CPU time | 2.41 seconds |
| Started | Jan 14 12:34:31 PM PST 24 |
| Finished | Jan 14 12:34:37 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-b28ca546-9364-4b41-b2f9-76f04de5c37e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263188600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.263188600 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1363727518 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 589202698 ps |
| CPU time | 78.22 seconds |
| Started | Jan 14 12:34:35 PM PST 24 |
| Finished | Jan 14 12:36:00 PM PST 24 |
| Peak memory | 207752 kb |
| Host | smart-7a8550a0-9c30-4fb8-9bde-f3a02758941c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1363727518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1363727518 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2128602091 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4948723981 ps |
| CPU time | 107.37 seconds |
| Started | Jan 14 12:34:36 PM PST 24 |
| Finished | Jan 14 12:36:29 PM PST 24 |
| Peak memory | 206636 kb |
| Host | smart-372baf36-db30-4052-9de6-3dd7d777a2dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2128602091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2128602091 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2301358331 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1585951230 ps |
| CPU time | 250.88 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:38:58 PM PST 24 |
| Peak memory | 209520 kb |
| Host | smart-523911e2-6fb3-4eb5-ac28-8c35e38fb188 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2301358331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.2301358331 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1895638941 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 1139311209 ps |
| CPU time | 180.2 seconds |
| Started | Jan 14 12:34:35 PM PST 24 |
| Finished | Jan 14 12:37:42 PM PST 24 |
| Peak memory | 220076 kb |
| Host | smart-e067ffec-2c1f-4647-bb59-a5cfec6b1dfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1895638941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.1895638941 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.2553321400 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 20117128 ps |
| CPU time | 1.99 seconds |
| Started | Jan 14 12:34:33 PM PST 24 |
| Finished | Jan 14 12:34:42 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-095b8fa0-d4a3-40a2-a0c0-4c25d248b83a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2553321400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2553321400 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2943669970 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5089667905 ps |
| CPU time | 40.47 seconds |
| Started | Jan 14 12:34:36 PM PST 24 |
| Finished | Jan 14 12:35:22 PM PST 24 |
| Peak memory | 211884 kb |
| Host | smart-eebf8434-9093-4cd0-bf92-a1100c1ff79e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2943669970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2943669970 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.3477723973 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 387793801103 ps |
| CPU time | 747.41 seconds |
| Started | Jan 14 12:34:40 PM PST 24 |
| Finished | Jan 14 12:47:13 PM PST 24 |
| Peak memory | 211976 kb |
| Host | smart-9881052e-5e0f-4f34-921c-8db400495edd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3477723973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.3477723973 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.3654909522 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 423261719 ps |
| CPU time | 18.1 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:35:05 PM PST 24 |
| Peak memory | 203348 kb |
| Host | smart-38273a37-ce35-443e-8257-2da235d0c116 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3654909522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3654909522 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.3412901796 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 911528507 ps |
| CPU time | 14.37 seconds |
| Started | Jan 14 12:34:36 PM PST 24 |
| Finished | Jan 14 12:34:56 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-71bf7655-bd9d-46e6-9bc0-ed5d1675c9ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3412901796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3412901796 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.3091452388 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1500696096 ps |
| CPU time | 41.43 seconds |
| Started | Jan 14 12:34:38 PM PST 24 |
| Finished | Jan 14 12:35:24 PM PST 24 |
| Peak memory | 211868 kb |
| Host | smart-cccfb718-500d-4f9e-b4fc-784b4bf352dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3091452388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3091452388 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.3585857131 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 12436337386 ps |
| CPU time | 72.08 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:35:59 PM PST 24 |
| Peak memory | 211696 kb |
| Host | smart-4e0b2458-4b29-4897-8e9b-ba6fc9aa7529 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585857131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3585857131 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3408484206 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 37612995680 ps |
| CPU time | 247.95 seconds |
| Started | Jan 14 12:34:37 PM PST 24 |
| Finished | Jan 14 12:38:50 PM PST 24 |
| Peak memory | 212012 kb |
| Host | smart-afe0ba2a-3f57-41b4-b8c7-8ee50c0f6f62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3408484206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3408484206 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1991816500 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 285370712 ps |
| CPU time | 15.06 seconds |
| Started | Jan 14 12:34:39 PM PST 24 |
| Finished | Jan 14 12:34:57 PM PST 24 |
| Peak memory | 211844 kb |
| Host | smart-f69eca5f-81a1-401c-b2ac-b30e5fca1ccb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991816500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1991816500 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.3932803507 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 7148711884 ps |
| CPU time | 34.24 seconds |
| Started | Jan 14 12:34:39 PM PST 24 |
| Finished | Jan 14 12:35:17 PM PST 24 |
| Peak memory | 204404 kb |
| Host | smart-b6525dc3-6481-4527-9025-b84f8b9d4b2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3932803507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3932803507 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.3200562305 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 451696323 ps |
| CPU time | 3.67 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:34:51 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-501c66b6-6e15-4405-8fad-2704fab9b7b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3200562305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3200562305 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3187007569 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5457043749 ps |
| CPU time | 28.9 seconds |
| Started | Jan 14 12:34:34 PM PST 24 |
| Finished | Jan 14 12:35:09 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-0b466162-2f14-4709-a073-558f204f45a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187007569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3187007569 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.4091363135 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 15970668358 ps |
| CPU time | 46.2 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:35:33 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-1212af1a-f75b-4e63-8ad9-30ff6a51ec72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4091363135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.4091363135 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3195841939 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 35396395 ps |
| CPU time | 2.47 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:34:49 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-cdee6e93-8102-4792-980d-aecc534f1f29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195841939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3195841939 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.320513405 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 5462413680 ps |
| CPU time | 113 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:36:40 PM PST 24 |
| Peak memory | 206480 kb |
| Host | smart-d1ec4485-9216-44c1-9fdb-e831a59037b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=320513405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.320513405 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.333981969 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 544075393 ps |
| CPU time | 60.94 seconds |
| Started | Jan 14 12:34:39 PM PST 24 |
| Finished | Jan 14 12:35:46 PM PST 24 |
| Peak memory | 205312 kb |
| Host | smart-a515d022-1f77-4446-807f-fe951136c51c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=333981969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.333981969 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1901578792 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1197378094 ps |
| CPU time | 96.3 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:36:23 PM PST 24 |
| Peak memory | 207680 kb |
| Host | smart-2c35619d-9d6f-4562-adfd-58a77db13af2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1901578792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1901578792 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2913992370 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 65413250 ps |
| CPU time | 18.63 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:35:05 PM PST 24 |
| Peak memory | 205588 kb |
| Host | smart-1799613e-2fce-47d6-8101-1d04c0f59eb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2913992370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2913992370 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.660204431 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 441473552 ps |
| CPU time | 18.21 seconds |
| Started | Jan 14 12:34:38 PM PST 24 |
| Finished | Jan 14 12:35:00 PM PST 24 |
| Peak memory | 211792 kb |
| Host | smart-0f251c9c-6ce4-4257-9f6c-8493592c8c12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=660204431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.660204431 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.506521784 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 34224845 ps |
| CPU time | 4.96 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:34:52 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-13fc1d20-384e-4983-a70e-935f77b8fbb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=506521784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.506521784 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.327500044 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 89981769829 ps |
| CPU time | 323.14 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:40:10 PM PST 24 |
| Peak memory | 206648 kb |
| Host | smart-e1731c13-3a42-415c-aaa9-2bf1a217ecc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=327500044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slo w_rsp.327500044 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.4239059793 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 39429733 ps |
| CPU time | 4.47 seconds |
| Started | Jan 14 12:34:40 PM PST 24 |
| Finished | Jan 14 12:34:50 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-9fb6b1c6-1266-4823-9be8-7aa28a4deaa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4239059793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.4239059793 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.2860512655 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 617831648 ps |
| CPU time | 18.7 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:35:06 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-69e6e057-0e1b-49a3-a9e1-0e0b50d6efe4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2860512655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2860512655 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.2173923794 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1293988178 ps |
| CPU time | 32.95 seconds |
| Started | Jan 14 12:34:42 PM PST 24 |
| Finished | Jan 14 12:35:19 PM PST 24 |
| Peak memory | 211796 kb |
| Host | smart-18a34bf9-1ad7-493f-a7fb-9a6c4db8f7ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2173923794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2173923794 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.4253180447 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 32028481859 ps |
| CPU time | 179.77 seconds |
| Started | Jan 14 12:34:38 PM PST 24 |
| Finished | Jan 14 12:37:42 PM PST 24 |
| Peak memory | 211996 kb |
| Host | smart-c90edb55-f791-42bb-9be5-91c26f976705 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253180447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.4253180447 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1118318956 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1942449476 ps |
| CPU time | 12.99 seconds |
| Started | Jan 14 12:34:40 PM PST 24 |
| Finished | Jan 14 12:34:59 PM PST 24 |
| Peak memory | 203628 kb |
| Host | smart-bdca9b2a-acf8-4b6b-a16c-e43773b3298e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1118318956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1118318956 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.921940325 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 214134154 ps |
| CPU time | 22.79 seconds |
| Started | Jan 14 12:34:42 PM PST 24 |
| Finished | Jan 14 12:35:09 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-24fb89bb-484a-4edb-9870-5ad71a1ef8f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921940325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.921940325 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.3713244986 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 268297228 ps |
| CPU time | 15.88 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:35:03 PM PST 24 |
| Peak memory | 204104 kb |
| Host | smart-05b26931-d54a-4750-ba10-5d1ff09ecec6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3713244986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3713244986 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.4118407789 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 366203132 ps |
| CPU time | 3.6 seconds |
| Started | Jan 14 12:34:38 PM PST 24 |
| Finished | Jan 14 12:34:45 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-593fe5d7-4c1a-4d4f-a2c7-6cbb97a92767 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4118407789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4118407789 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2349516975 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 4425958835 ps |
| CPU time | 24.52 seconds |
| Started | Jan 14 12:34:39 PM PST 24 |
| Finished | Jan 14 12:35:07 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-aff506c9-e0a8-464f-b70f-9f854ad1cd89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349516975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2349516975 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.984979311 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4674099584 ps |
| CPU time | 22.68 seconds |
| Started | Jan 14 12:34:40 PM PST 24 |
| Finished | Jan 14 12:35:09 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-9bc60f0b-99ff-43cd-9766-75e8e83a64c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=984979311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.984979311 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1235730382 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 28631108 ps |
| CPU time | 2.16 seconds |
| Started | Jan 14 12:34:38 PM PST 24 |
| Finished | Jan 14 12:34:44 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-7e6c2c5d-8be0-46ef-af97-8c53287fe244 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235730382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1235730382 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2445512387 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 482561182 ps |
| CPU time | 38.74 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:35:26 PM PST 24 |
| Peak memory | 206104 kb |
| Host | smart-f0f3d17c-0b72-4774-b0d3-6b0c1f5961ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2445512387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2445512387 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2330826898 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 521475118 ps |
| CPU time | 13.83 seconds |
| Started | Jan 14 12:34:47 PM PST 24 |
| Finished | Jan 14 12:35:02 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-8916b238-1e2e-44ca-9a02-ae69f978dcf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2330826898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2330826898 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1034879069 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 86393801 ps |
| CPU time | 20.94 seconds |
| Started | Jan 14 12:34:49 PM PST 24 |
| Finished | Jan 14 12:35:11 PM PST 24 |
| Peak memory | 206292 kb |
| Host | smart-a6ca8181-84d1-44a5-a3d4-8de102a23428 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1034879069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.1034879069 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2185769891 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 115694439 ps |
| CPU time | 2.17 seconds |
| Started | Jan 14 12:34:42 PM PST 24 |
| Finished | Jan 14 12:34:49 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-770d2749-5e1c-45ed-b683-2990b09a3563 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2185769891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2185769891 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2520363637 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 47869846 ps |
| CPU time | 3.4 seconds |
| Started | Jan 14 12:34:48 PM PST 24 |
| Finished | Jan 14 12:34:52 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-c81b985a-f9ab-4214-8e5e-a81a4225d9cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2520363637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2520363637 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.95842919 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 51914013390 ps |
| CPU time | 424.97 seconds |
| Started | Jan 14 12:34:46 PM PST 24 |
| Finished | Jan 14 12:41:52 PM PST 24 |
| Peak memory | 211912 kb |
| Host | smart-c354d606-cb4c-42ea-9cce-3944763e78bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=95842919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow _rsp.95842919 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1420457389 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 123220086 ps |
| CPU time | 3.33 seconds |
| Started | Jan 14 12:34:47 PM PST 24 |
| Finished | Jan 14 12:34:52 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-3578a6f2-2b55-484d-bcaa-a7dcb8381596 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1420457389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1420457389 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.3529982134 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 726513983 ps |
| CPU time | 26.27 seconds |
| Started | Jan 14 12:34:48 PM PST 24 |
| Finished | Jan 14 12:35:15 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-4096fe50-f1f7-49ea-8fb4-d9502f34483f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3529982134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3529982134 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.4230437155 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1238107767 ps |
| CPU time | 37.29 seconds |
| Started | Jan 14 12:34:46 PM PST 24 |
| Finished | Jan 14 12:35:25 PM PST 24 |
| Peak memory | 211864 kb |
| Host | smart-93108884-e404-4570-bb99-a9718db38c4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4230437155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.4230437155 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2795592578 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 32619190424 ps |
| CPU time | 200.38 seconds |
| Started | Jan 14 12:34:48 PM PST 24 |
| Finished | Jan 14 12:38:09 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-f74f2abc-9fdc-4758-8cee-91017262693f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795592578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2795592578 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2909565833 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1218265110 ps |
| CPU time | 11.99 seconds |
| Started | Jan 14 12:34:47 PM PST 24 |
| Finished | Jan 14 12:35:00 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-5ed7438d-009b-44cb-b54f-5ed4bc3a3ea6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2909565833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2909565833 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3908737356 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 66138878 ps |
| CPU time | 6.52 seconds |
| Started | Jan 14 12:34:47 PM PST 24 |
| Finished | Jan 14 12:34:55 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-872bea23-52b3-412a-b08b-d72eb5b38c01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908737356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3908737356 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1707884647 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 618037962 ps |
| CPU time | 12.52 seconds |
| Started | Jan 14 12:34:45 PM PST 24 |
| Finished | Jan 14 12:35:00 PM PST 24 |
| Peak memory | 204028 kb |
| Host | smart-f994ab4a-08e8-44dc-9dc8-eddcdad0ee1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1707884647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1707884647 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.18864039 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 154718223 ps |
| CPU time | 3.24 seconds |
| Started | Jan 14 12:34:44 PM PST 24 |
| Finished | Jan 14 12:34:50 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-7b681001-14b6-43a7-90ec-bf41d129b612 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=18864039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.18864039 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2045969539 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 7056681208 ps |
| CPU time | 37.2 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:35:24 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-bafe328f-598a-47ec-971f-eaf6720f5dda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045969539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2045969539 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.507603846 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3319533715 ps |
| CPU time | 26.88 seconds |
| Started | Jan 14 12:34:44 PM PST 24 |
| Finished | Jan 14 12:35:14 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-0020f77b-ac74-412f-9fc8-ce49fc3f1057 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=507603846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.507603846 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3979575985 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 37218598 ps |
| CPU time | 2.28 seconds |
| Started | Jan 14 12:34:43 PM PST 24 |
| Finished | Jan 14 12:34:49 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-77084393-f68a-4e0c-91d1-b4af53908641 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979575985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3979575985 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.3054961208 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1471603173 ps |
| CPU time | 178.57 seconds |
| Started | Jan 14 12:34:48 PM PST 24 |
| Finished | Jan 14 12:37:48 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-50878b5b-e4ab-4731-a3ad-764266b1ea5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3054961208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3054961208 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2695518658 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1394906252 ps |
| CPU time | 78.55 seconds |
| Started | Jan 14 12:34:45 PM PST 24 |
| Finished | Jan 14 12:36:06 PM PST 24 |
| Peak memory | 206524 kb |
| Host | smart-133efeca-1a48-4a8e-8cc9-6302feec85b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2695518658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2695518658 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.915269570 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 728200242 ps |
| CPU time | 216.53 seconds |
| Started | Jan 14 12:34:47 PM PST 24 |
| Finished | Jan 14 12:38:25 PM PST 24 |
| Peak memory | 208228 kb |
| Host | smart-d0742caa-3466-48b4-b536-f259da34f87f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=915269570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand _reset.915269570 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1251966244 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1769429766 ps |
| CPU time | 55.68 seconds |
| Started | Jan 14 12:34:46 PM PST 24 |
| Finished | Jan 14 12:35:43 PM PST 24 |
| Peak memory | 207332 kb |
| Host | smart-9b340151-f965-4c0c-a9a3-e69792ed81c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1251966244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1251966244 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.1949151517 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 466018790 ps |
| CPU time | 21.26 seconds |
| Started | Jan 14 12:34:46 PM PST 24 |
| Finished | Jan 14 12:35:09 PM PST 24 |
| Peak memory | 211808 kb |
| Host | smart-334f77f7-988e-4b64-b869-a34da195badd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1949151517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1949151517 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.668862643 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1567719269 ps |
| CPU time | 41.21 seconds |
| Started | Jan 14 12:34:50 PM PST 24 |
| Finished | Jan 14 12:35:32 PM PST 24 |
| Peak memory | 211832 kb |
| Host | smart-de2e5ddc-fcd7-4c38-8ee8-ce568bf3ec1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=668862643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.668862643 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2756787271 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 130423942943 ps |
| CPU time | 592.78 seconds |
| Started | Jan 14 12:34:48 PM PST 24 |
| Finished | Jan 14 12:44:42 PM PST 24 |
| Peak memory | 207404 kb |
| Host | smart-afe03152-756a-44c0-b292-e02600a9a3af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2756787271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2756787271 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3220976917 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 201132497 ps |
| CPU time | 17.27 seconds |
| Started | Jan 14 12:34:53 PM PST 24 |
| Finished | Jan 14 12:35:11 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-ce7fb224-2625-44a9-9680-4836b2e2ae84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3220976917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3220976917 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.3220304602 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 5917809841 ps |
| CPU time | 30.82 seconds |
| Started | Jan 14 12:34:53 PM PST 24 |
| Finished | Jan 14 12:35:25 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-403954a3-2c3c-4ba1-a0f2-97856f07a4c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3220304602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3220304602 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.3265049441 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 107418825 ps |
| CPU time | 3.09 seconds |
| Started | Jan 14 12:34:48 PM PST 24 |
| Finished | Jan 14 12:34:52 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-806c4c37-0a15-4eb6-a6af-adcfeef4b2eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3265049441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3265049441 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.623242839 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 124497628279 ps |
| CPU time | 201.79 seconds |
| Started | Jan 14 12:34:52 PM PST 24 |
| Finished | Jan 14 12:38:15 PM PST 24 |
| Peak memory | 204892 kb |
| Host | smart-3dda627d-dc11-4007-b225-8c79bf3eb27a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=623242839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.623242839 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3603835524 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 79133702583 ps |
| CPU time | 171.44 seconds |
| Started | Jan 14 12:34:46 PM PST 24 |
| Finished | Jan 14 12:37:39 PM PST 24 |
| Peak memory | 205012 kb |
| Host | smart-0be367ae-fa44-466f-9327-918522859fc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3603835524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3603835524 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2359602478 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 281790145 ps |
| CPU time | 17.13 seconds |
| Started | Jan 14 12:34:48 PM PST 24 |
| Finished | Jan 14 12:35:06 PM PST 24 |
| Peak memory | 204720 kb |
| Host | smart-435bbd13-3544-4295-8854-3173a9482365 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359602478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2359602478 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.1941289358 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 334450297 ps |
| CPU time | 7.95 seconds |
| Started | Jan 14 12:34:48 PM PST 24 |
| Finished | Jan 14 12:34:57 PM PST 24 |
| Peak memory | 203960 kb |
| Host | smart-7312fdf3-f941-41a8-b51c-05bccec6440d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941289358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1941289358 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.1623908443 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 98779032 ps |
| CPU time | 2.46 seconds |
| Started | Jan 14 12:34:46 PM PST 24 |
| Finished | Jan 14 12:34:50 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-8e234cc3-fda4-47fe-8b08-c888a2dae546 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1623908443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1623908443 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2826692822 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 34584416943 ps |
| CPU time | 58.27 seconds |
| Started | Jan 14 12:34:46 PM PST 24 |
| Finished | Jan 14 12:35:46 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-86f87f44-873b-4df7-a2ab-37e71bbee47a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826692822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2826692822 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2811372532 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3240232156 ps |
| CPU time | 22.67 seconds |
| Started | Jan 14 12:34:52 PM PST 24 |
| Finished | Jan 14 12:35:15 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-4e9cecc4-4a41-42d1-b081-8ef5f2629d7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2811372532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2811372532 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3687353710 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 33373182 ps |
| CPU time | 2.04 seconds |
| Started | Jan 14 12:34:48 PM PST 24 |
| Finished | Jan 14 12:34:51 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-91347b0c-a803-407a-8075-bedcfb837ac7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687353710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3687353710 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.2182994465 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1310245611 ps |
| CPU time | 116.81 seconds |
| Started | Jan 14 12:35:00 PM PST 24 |
| Finished | Jan 14 12:37:03 PM PST 24 |
| Peak memory | 207080 kb |
| Host | smart-41d1c911-5549-46c6-a596-c848344d8a36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2182994465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2182994465 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2572679662 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 25913818434 ps |
| CPU time | 251.98 seconds |
| Started | Jan 14 12:34:52 PM PST 24 |
| Finished | Jan 14 12:39:05 PM PST 24 |
| Peak memory | 210160 kb |
| Host | smart-4e15cf2a-0d5d-4f4c-b5e4-0a5082a1ed62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2572679662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2572679662 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.400991295 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2052934308 ps |
| CPU time | 287.74 seconds |
| Started | Jan 14 12:34:50 PM PST 24 |
| Finished | Jan 14 12:39:39 PM PST 24 |
| Peak memory | 208596 kb |
| Host | smart-bc7b3dbe-cd40-4cef-b83b-96c351d379b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=400991295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand _reset.400991295 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.3408206850 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 439392484 ps |
| CPU time | 145.29 seconds |
| Started | Jan 14 12:34:53 PM PST 24 |
| Finished | Jan 14 12:37:19 PM PST 24 |
| Peak memory | 210524 kb |
| Host | smart-b343ae42-e3c7-479d-8aec-00eff2f34b5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3408206850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.3408206850 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3825296161 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 941721553 ps |
| CPU time | 16.22 seconds |
| Started | Jan 14 12:34:49 PM PST 24 |
| Finished | Jan 14 12:35:06 PM PST 24 |
| Peak memory | 205232 kb |
| Host | smart-f3ca5d99-bf3c-4220-8b0c-2d662b1c07e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3825296161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3825296161 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1556371516 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 156769488 ps |
| CPU time | 4.04 seconds |
| Started | Jan 14 12:32:36 PM PST 24 |
| Finished | Jan 14 12:32:42 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-0a4a4ff0-2ac7-4dde-9856-7d2c55759339 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1556371516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1556371516 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.252341058 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 140242608165 ps |
| CPU time | 535.14 seconds |
| Started | Jan 14 12:32:36 PM PST 24 |
| Finished | Jan 14 12:41:33 PM PST 24 |
| Peak memory | 207088 kb |
| Host | smart-dd71f3e3-051c-42fc-ad58-b3464530f01f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=252341058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow _rsp.252341058 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.2891212332 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 54450771 ps |
| CPU time | 2.82 seconds |
| Started | Jan 14 12:32:39 PM PST 24 |
| Finished | Jan 14 12:32:48 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-6ef05600-7452-452e-81c9-a8f385a1b1d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2891212332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2891212332 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.3284926230 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 373964543 ps |
| CPU time | 20.44 seconds |
| Started | Jan 14 12:32:38 PM PST 24 |
| Finished | Jan 14 12:33:00 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-f7434dfe-5693-4f98-be85-c29e34e4d595 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3284926230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3284926230 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.2922876654 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 63923777 ps |
| CPU time | 8.63 seconds |
| Started | Jan 14 12:32:37 PM PST 24 |
| Finished | Jan 14 12:32:47 PM PST 24 |
| Peak memory | 211836 kb |
| Host | smart-83998743-1698-4347-b152-a4b12515b7c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2922876654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2922876654 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1751622671 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 45679205666 ps |
| CPU time | 146.47 seconds |
| Started | Jan 14 12:32:34 PM PST 24 |
| Finished | Jan 14 12:35:01 PM PST 24 |
| Peak memory | 211948 kb |
| Host | smart-1b1ee65c-df79-49dd-a54d-128437ca5419 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751622671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1751622671 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1875706454 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 27755410667 ps |
| CPU time | 229.49 seconds |
| Started | Jan 14 12:32:40 PM PST 24 |
| Finished | Jan 14 12:36:35 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-7117cddb-543f-48a9-95dc-f60969bbb25a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1875706454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1875706454 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.2061269587 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 384638230 ps |
| CPU time | 16.11 seconds |
| Started | Jan 14 12:32:38 PM PST 24 |
| Finished | Jan 14 12:32:55 PM PST 24 |
| Peak memory | 204892 kb |
| Host | smart-f62ee8ef-3f2b-455e-9b4e-c66bc5bf7fd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061269587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2061269587 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.95641080 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1433647652 ps |
| CPU time | 6.39 seconds |
| Started | Jan 14 12:32:40 PM PST 24 |
| Finished | Jan 14 12:32:52 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-d5a69a0a-cccf-491c-8f32-b4bc2ee0ae61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=95641080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.95641080 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.676795510 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 66079593 ps |
| CPU time | 2.28 seconds |
| Started | Jan 14 12:32:34 PM PST 24 |
| Finished | Jan 14 12:32:37 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-01c76109-c56c-433c-b788-095da31e4ede |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=676795510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.676795510 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1383894422 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 5566513920 ps |
| CPU time | 33.54 seconds |
| Started | Jan 14 12:32:38 PM PST 24 |
| Finished | Jan 14 12:33:13 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-e03c2c32-3cd0-401f-9737-eaa0d43b4a05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383894422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1383894422 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3255338611 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 9453426428 ps |
| CPU time | 33.37 seconds |
| Started | Jan 14 12:32:37 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-0269b07b-810b-46f7-a334-767036f2cd48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3255338611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3255338611 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2899346880 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 70271932 ps |
| CPU time | 2.7 seconds |
| Started | Jan 14 12:32:40 PM PST 24 |
| Finished | Jan 14 12:32:48 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-938b5049-28c2-4396-839d-23f5f0f3d1ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899346880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2899346880 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2102252464 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1066703653 ps |
| CPU time | 111.91 seconds |
| Started | Jan 14 12:32:39 PM PST 24 |
| Finished | Jan 14 12:34:35 PM PST 24 |
| Peak memory | 207248 kb |
| Host | smart-ea9f3537-3093-4319-9eb5-0843ceba38f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2102252464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2102252464 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3593572896 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2215152406 ps |
| CPU time | 70.86 seconds |
| Started | Jan 14 12:32:45 PM PST 24 |
| Finished | Jan 14 12:34:00 PM PST 24 |
| Peak memory | 206560 kb |
| Host | smart-8e16ca9d-febd-4f5f-b249-74cc4a661a8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3593572896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3593572896 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1894596848 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 9187055787 ps |
| CPU time | 467.08 seconds |
| Started | Jan 14 12:32:43 PM PST 24 |
| Finished | Jan 14 12:40:33 PM PST 24 |
| Peak memory | 211380 kb |
| Host | smart-6b871c8a-0625-4a36-a502-1833b05941cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1894596848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.1894596848 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.189936293 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 242038818 ps |
| CPU time | 89.25 seconds |
| Started | Jan 14 12:32:46 PM PST 24 |
| Finished | Jan 14 12:34:19 PM PST 24 |
| Peak memory | 209136 kb |
| Host | smart-58f62c51-4ae0-4981-bb25-7aff70c2e4f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=189936293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese t_error.189936293 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1345176636 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 202827047 ps |
| CPU time | 8.75 seconds |
| Started | Jan 14 12:32:38 PM PST 24 |
| Finished | Jan 14 12:32:48 PM PST 24 |
| Peak memory | 211740 kb |
| Host | smart-bcda4540-4a62-40e7-83d4-cfdae38e5fa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1345176636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1345176636 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.3446422786 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1345340300 ps |
| CPU time | 37.26 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:33:31 PM PST 24 |
| Peak memory | 204840 kb |
| Host | smart-1fb8b8f8-9809-4100-9227-31b37cd1a1b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3446422786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3446422786 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1266758514 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 169435166555 ps |
| CPU time | 569.13 seconds |
| Started | Jan 14 12:32:44 PM PST 24 |
| Finished | Jan 14 12:42:15 PM PST 24 |
| Peak memory | 211896 kb |
| Host | smart-fae864a5-0e0a-42a8-996a-2f9d9b6362c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1266758514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.1266758514 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.809163210 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 289270357 ps |
| CPU time | 9.52 seconds |
| Started | Jan 14 12:32:44 PM PST 24 |
| Finished | Jan 14 12:32:55 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-a063c97e-1cbe-4585-9090-7994b120dfcd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=809163210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.809163210 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.3707403811 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1517603993 ps |
| CPU time | 33.12 seconds |
| Started | Jan 14 12:32:45 PM PST 24 |
| Finished | Jan 14 12:33:20 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-ec59bdb2-ae2c-4b78-95e9-1630087cafb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3707403811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3707403811 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.3738978569 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 126340022 ps |
| CPU time | 2.58 seconds |
| Started | Jan 14 12:32:45 PM PST 24 |
| Finished | Jan 14 12:32:52 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-2d3a1721-f75a-4203-b1a3-5c28b445e53b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3738978569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3738978569 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1465760285 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 22715909044 ps |
| CPU time | 143.99 seconds |
| Started | Jan 14 12:32:43 PM PST 24 |
| Finished | Jan 14 12:35:10 PM PST 24 |
| Peak memory | 211916 kb |
| Host | smart-30788f51-fb4c-4dbd-a87f-e54de910f3e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465760285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1465760285 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2942867260 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 7042415742 ps |
| CPU time | 56.63 seconds |
| Started | Jan 14 12:32:45 PM PST 24 |
| Finished | Jan 14 12:33:44 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-0cebf0ad-53bd-43b9-ad5c-59bad7d3c12a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2942867260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2942867260 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2892002992 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 191365716 ps |
| CPU time | 17.04 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:33:11 PM PST 24 |
| Peak memory | 211796 kb |
| Host | smart-27ec79eb-0d44-48aa-9f15-781a4bc46697 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892002992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2892002992 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.670936892 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2516366184 ps |
| CPU time | 33.98 seconds |
| Started | Jan 14 12:32:52 PM PST 24 |
| Finished | Jan 14 12:33:27 PM PST 24 |
| Peak memory | 204092 kb |
| Host | smart-67fc6243-3f81-4869-9bf1-76e2a6943919 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=670936892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.670936892 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.3769984561 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 33126085 ps |
| CPU time | 2.37 seconds |
| Started | Jan 14 12:32:41 PM PST 24 |
| Finished | Jan 14 12:32:48 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-ffccf4b3-f7dc-4c1b-a01d-8699c6d74b9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3769984561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3769984561 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1512104521 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 7163707869 ps |
| CPU time | 30.69 seconds |
| Started | Jan 14 12:32:45 PM PST 24 |
| Finished | Jan 14 12:33:20 PM PST 24 |
| Peak memory | 203796 kb |
| Host | smart-e4a5f7c0-c89f-42df-a4a6-58cc33191158 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512104521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1512104521 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3295475919 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 10592433587 ps |
| CPU time | 31.97 seconds |
| Started | Jan 14 12:32:43 PM PST 24 |
| Finished | Jan 14 12:33:18 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-46c645d4-1ab6-4a25-a626-04a50a54ae54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3295475919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3295475919 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.753318316 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 56139369 ps |
| CPU time | 2.15 seconds |
| Started | Jan 14 12:32:43 PM PST 24 |
| Finished | Jan 14 12:32:48 PM PST 24 |
| Peak memory | 203592 kb |
| Host | smart-cbf97906-2a0c-42e6-aa9f-083ae92d4942 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753318316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.753318316 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.390458369 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 992802692 ps |
| CPU time | 53.89 seconds |
| Started | Jan 14 12:32:42 PM PST 24 |
| Finished | Jan 14 12:33:39 PM PST 24 |
| Peak memory | 207324 kb |
| Host | smart-43ea7f33-2fa4-45a2-b5f5-bce37bda9a33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=390458369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.390458369 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.368952192 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 3725152262 ps |
| CPU time | 85.24 seconds |
| Started | Jan 14 12:32:52 PM PST 24 |
| Finished | Jan 14 12:34:18 PM PST 24 |
| Peak memory | 204820 kb |
| Host | smart-32f4c47e-78b7-4fe2-8eed-fe036982b7bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=368952192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.368952192 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.509790676 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 841191849 ps |
| CPU time | 334.44 seconds |
| Started | Jan 14 12:32:44 PM PST 24 |
| Finished | Jan 14 12:38:20 PM PST 24 |
| Peak memory | 210072 kb |
| Host | smart-180a1a70-edc6-4895-aa9b-92baef8f358a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=509790676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_ reset.509790676 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2771022196 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4895843098 ps |
| CPU time | 126.48 seconds |
| Started | Jan 14 12:32:48 PM PST 24 |
| Finished | Jan 14 12:34:57 PM PST 24 |
| Peak memory | 210100 kb |
| Host | smart-ad0565f1-7dda-4268-8be1-87a26937c3dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2771022196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.2771022196 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.4259664815 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 79306678 ps |
| CPU time | 10.39 seconds |
| Started | Jan 14 12:32:48 PM PST 24 |
| Finished | Jan 14 12:33:01 PM PST 24 |
| Peak memory | 204764 kb |
| Host | smart-d51c106d-2f2b-4f93-98aa-736018d64f6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4259664815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.4259664815 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.4278616211 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 486461592 ps |
| CPU time | 35.34 seconds |
| Started | Jan 14 12:32:49 PM PST 24 |
| Finished | Jan 14 12:33:26 PM PST 24 |
| Peak memory | 211864 kb |
| Host | smart-a407022e-9120-4df3-882c-47ad31fcf570 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4278616211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.4278616211 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3240169656 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 8862523365 ps |
| CPU time | 71.85 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:34:05 PM PST 24 |
| Peak memory | 205592 kb |
| Host | smart-118d2146-b1dc-45c9-b426-6cc579feb832 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3240169656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.3240169656 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1086699243 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1661647933 ps |
| CPU time | 25.27 seconds |
| Started | Jan 14 12:32:47 PM PST 24 |
| Finished | Jan 14 12:33:16 PM PST 24 |
| Peak memory | 204036 kb |
| Host | smart-ff7503b9-502f-41a8-9ddd-8509a22a74d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1086699243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1086699243 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.406907856 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 216537298 ps |
| CPU time | 21.07 seconds |
| Started | Jan 14 12:32:49 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-3558d3a7-53a3-4f7f-8e88-b7a470af38b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=406907856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.406907856 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.278246497 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 63707476 ps |
| CPU time | 2.25 seconds |
| Started | Jan 14 12:32:45 PM PST 24 |
| Finished | Jan 14 12:32:52 PM PST 24 |
| Peak memory | 203628 kb |
| Host | smart-449b648f-1725-4f18-8fd2-be2dcaee0dcd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=278246497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.278246497 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2030828931 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2692371754 ps |
| CPU time | 15.47 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:33:09 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-de1500b3-794e-40fd-a57c-2e86e8b383f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030828931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2030828931 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4217425621 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 12900719870 ps |
| CPU time | 98.61 seconds |
| Started | Jan 14 12:32:52 PM PST 24 |
| Finished | Jan 14 12:34:32 PM PST 24 |
| Peak memory | 204824 kb |
| Host | smart-ad003035-b1d0-4610-a80c-805f766be6ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4217425621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4217425621 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.856251345 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1161564060 ps |
| CPU time | 28.1 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:33:22 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-a9631fc9-c066-423a-a65d-c62a3a50b0c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856251345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.856251345 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.999772948 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 348482923 ps |
| CPU time | 15.9 seconds |
| Started | Jan 14 12:32:47 PM PST 24 |
| Finished | Jan 14 12:33:07 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-c94a4f6a-c9cb-4b99-8ed7-4a320f943b01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=999772948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.999772948 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.1617410928 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 467398751 ps |
| CPU time | 3.93 seconds |
| Started | Jan 14 12:32:48 PM PST 24 |
| Finished | Jan 14 12:32:55 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-37bc6a4e-bf77-4ece-843d-17f910abe6a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1617410928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1617410928 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.1911140178 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 7890042233 ps |
| CPU time | 30.18 seconds |
| Started | Jan 14 12:32:47 PM PST 24 |
| Finished | Jan 14 12:33:21 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-b1585dff-56a7-4e44-a0fe-61ea375ef2ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911140178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1911140178 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3267671741 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 10018507567 ps |
| CPU time | 38.18 seconds |
| Started | Jan 14 12:32:49 PM PST 24 |
| Finished | Jan 14 12:33:29 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-dacc593e-53bc-49aa-8a03-fa813219ce52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3267671741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3267671741 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2354132797 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 38342895 ps |
| CPU time | 2.26 seconds |
| Started | Jan 14 12:32:56 PM PST 24 |
| Finished | Jan 14 12:32:59 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-c704ac2c-bdf4-42bc-b8a6-b275c3f9fe91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354132797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2354132797 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2516692455 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2395484134 ps |
| CPU time | 85.77 seconds |
| Started | Jan 14 12:32:49 PM PST 24 |
| Finished | Jan 14 12:34:17 PM PST 24 |
| Peak memory | 206660 kb |
| Host | smart-882feb4c-b006-4498-8540-a016e079aa1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2516692455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2516692455 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.4060721787 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4152915132 ps |
| CPU time | 122.04 seconds |
| Started | Jan 14 12:32:49 PM PST 24 |
| Finished | Jan 14 12:34:53 PM PST 24 |
| Peak memory | 206416 kb |
| Host | smart-539a4531-c043-4a02-9471-65919f7b6e41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4060721787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.4060721787 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1842780815 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 3835193272 ps |
| CPU time | 250.15 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:37:04 PM PST 24 |
| Peak memory | 224172 kb |
| Host | smart-f040f0ca-c422-41c3-afbf-7e3aa890d97e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1842780815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.1842780815 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2547419478 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 256033412 ps |
| CPU time | 12.42 seconds |
| Started | Jan 14 12:32:48 PM PST 24 |
| Finished | Jan 14 12:33:03 PM PST 24 |
| Peak memory | 211768 kb |
| Host | smart-36ed9b4a-0302-4798-83bc-285953bc867a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2547419478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2547419478 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2535093236 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 122699765 ps |
| CPU time | 7.79 seconds |
| Started | Jan 14 12:32:56 PM PST 24 |
| Finished | Jan 14 12:33:05 PM PST 24 |
| Peak memory | 203580 kb |
| Host | smart-fa94031b-df60-4045-bda7-cf2df7ad5031 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2535093236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2535093236 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.24113277 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 142296541048 ps |
| CPU time | 252.82 seconds |
| Started | Jan 14 12:32:50 PM PST 24 |
| Finished | Jan 14 12:37:05 PM PST 24 |
| Peak memory | 211900 kb |
| Host | smart-08246227-dfa3-4d0b-a4f1-2e11a308bf7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=24113277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.24113277 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.506224498 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 879864298 ps |
| CPU time | 20.45 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:33:14 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-cd990a87-f3ca-4cfd-b22b-2675d63ef6a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=506224498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.506224498 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.2394139881 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 1015657432 ps |
| CPU time | 16.95 seconds |
| Started | Jan 14 12:32:55 PM PST 24 |
| Finished | Jan 14 12:33:13 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-158fb780-9103-43a0-b173-ff45b78e6888 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2394139881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2394139881 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.136736462 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 419881844 ps |
| CPU time | 12.4 seconds |
| Started | Jan 14 12:32:47 PM PST 24 |
| Finished | Jan 14 12:33:03 PM PST 24 |
| Peak memory | 211816 kb |
| Host | smart-85548bca-a0e4-4711-b003-74138df38abb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=136736462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.136736462 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.3809906754 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 39096488418 ps |
| CPU time | 181.02 seconds |
| Started | Jan 14 12:32:48 PM PST 24 |
| Finished | Jan 14 12:35:52 PM PST 24 |
| Peak memory | 212032 kb |
| Host | smart-b0fc035b-3850-45a8-8987-1584f11700c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809906754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3809906754 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.245911400 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2239434248 ps |
| CPU time | 15.58 seconds |
| Started | Jan 14 12:32:50 PM PST 24 |
| Finished | Jan 14 12:33:07 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-d4de8e78-a7ed-4815-ae23-11592c62891a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=245911400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.245911400 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.618653103 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 489621216 ps |
| CPU time | 17.85 seconds |
| Started | Jan 14 12:32:48 PM PST 24 |
| Finished | Jan 14 12:33:09 PM PST 24 |
| Peak memory | 204824 kb |
| Host | smart-ba782e52-cc38-4bd9-9a6d-a9dbf9631859 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618653103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.618653103 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.528958304 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 140518254 ps |
| CPU time | 9.12 seconds |
| Started | Jan 14 12:32:54 PM PST 24 |
| Finished | Jan 14 12:33:05 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-a178b87e-16c8-45de-bfa4-9f135f785ca4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=528958304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.528958304 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.3144671145 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 93780075 ps |
| CPU time | 2.88 seconds |
| Started | Jan 14 12:32:51 PM PST 24 |
| Finished | Jan 14 12:32:55 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-c9c0c959-7510-49b3-a8fd-5f39c577ff1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3144671145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3144671145 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.4091497098 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 8782235241 ps |
| CPU time | 32.05 seconds |
| Started | Jan 14 12:32:50 PM PST 24 |
| Finished | Jan 14 12:33:24 PM PST 24 |
| Peak memory | 203792 kb |
| Host | smart-7c6a6d94-e0f5-4a0e-af4c-a2e20e4304ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091497098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.4091497098 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3238802025 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 7839175031 ps |
| CPU time | 24.71 seconds |
| Started | Jan 14 12:32:52 PM PST 24 |
| Finished | Jan 14 12:33:18 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-fd60bc45-40ff-4f62-8f19-2f4f4f840fce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3238802025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3238802025 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.153833711 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 29787623 ps |
| CPU time | 2.48 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:32:56 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-68c11abb-131e-4366-abd0-33c7e18f36bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153833711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.153833711 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1796265367 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 26943392588 ps |
| CPU time | 300.76 seconds |
| Started | Jan 14 12:32:54 PM PST 24 |
| Finished | Jan 14 12:37:55 PM PST 24 |
| Peak memory | 207424 kb |
| Host | smart-51b3bdfb-5de6-4d85-a6fe-3c03de7505d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1796265367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1796265367 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.856199374 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 5781587780 ps |
| CPU time | 140.55 seconds |
| Started | Jan 14 12:32:52 PM PST 24 |
| Finished | Jan 14 12:35:14 PM PST 24 |
| Peak memory | 206512 kb |
| Host | smart-c39803dd-d7fe-40ac-a44e-5f2b766a94bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=856199374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.856199374 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3260092709 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 158834709 ps |
| CPU time | 34.04 seconds |
| Started | Jan 14 12:32:57 PM PST 24 |
| Finished | Jan 14 12:33:32 PM PST 24 |
| Peak memory | 206824 kb |
| Host | smart-94eba888-7e5f-46d7-8efa-29a2fe549a35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3260092709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.3260092709 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2388221879 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 16913248002 ps |
| CPU time | 493.66 seconds |
| Started | Jan 14 12:32:57 PM PST 24 |
| Finished | Jan 14 12:41:11 PM PST 24 |
| Peak memory | 220048 kb |
| Host | smart-b4d1bfbf-2fcf-4c90-830c-5e72cfccf0cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2388221879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2388221879 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.1026489859 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 146250172 ps |
| CPU time | 16.95 seconds |
| Started | Jan 14 12:32:56 PM PST 24 |
| Finished | Jan 14 12:33:14 PM PST 24 |
| Peak memory | 211768 kb |
| Host | smart-ae0f1556-4156-4312-85b4-fcb50c79e773 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1026489859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1026489859 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1222991227 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 382685773 ps |
| CPU time | 29.24 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:33:29 PM PST 24 |
| Peak memory | 211596 kb |
| Host | smart-282c7888-5840-4fd6-868a-0d48d6b846c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1222991227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1222991227 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2192364827 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 16159056624 ps |
| CPU time | 125.97 seconds |
| Started | Jan 14 12:32:59 PM PST 24 |
| Finished | Jan 14 12:35:06 PM PST 24 |
| Peak memory | 206192 kb |
| Host | smart-7eb8a020-cb7b-416d-a6d8-be79253e549d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2192364827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2192364827 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2873909256 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 569617054 ps |
| CPU time | 14.88 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:33:08 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-b01c0f52-7db2-469b-9c13-3ae08d08d668 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2873909256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2873909256 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.2667880893 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 371580478 ps |
| CPU time | 9.9 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:33:03 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-9757c95c-db19-4292-89ee-b47df8880845 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2667880893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2667880893 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.1675106932 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 77009107 ps |
| CPU time | 4.9 seconds |
| Started | Jan 14 12:32:51 PM PST 24 |
| Finished | Jan 14 12:32:57 PM PST 24 |
| Peak memory | 204524 kb |
| Host | smart-135a4ed2-6657-4f40-9d7b-41bd314aae5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1675106932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1675106932 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.2324059386 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5683310775 ps |
| CPU time | 17.49 seconds |
| Started | Jan 14 12:32:45 PM PST 24 |
| Finished | Jan 14 12:33:07 PM PST 24 |
| Peak memory | 211864 kb |
| Host | smart-c1f56ae0-f269-4202-9f08-117b588d8951 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324059386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2324059386 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.651456369 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 28248049925 ps |
| CPU time | 245.85 seconds |
| Started | Jan 14 12:32:46 PM PST 24 |
| Finished | Jan 14 12:36:56 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-9fae4f9f-ba38-4750-b104-7d0f86e1f90f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=651456369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.651456369 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1350138956 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 187910041 ps |
| CPU time | 20.81 seconds |
| Started | Jan 14 12:32:48 PM PST 24 |
| Finished | Jan 14 12:33:12 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-fa524b3d-affa-4dd7-bf66-c24ec168986e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350138956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1350138956 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.1446243902 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 513089441 ps |
| CPU time | 18.06 seconds |
| Started | Jan 14 12:32:58 PM PST 24 |
| Finished | Jan 14 12:33:17 PM PST 24 |
| Peak memory | 204108 kb |
| Host | smart-2b5c3ea7-d86a-4458-a975-3bb4c56c290c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1446243902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1446243902 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.158605358 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 45432384 ps |
| CPU time | 2.25 seconds |
| Started | Jan 14 12:32:55 PM PST 24 |
| Finished | Jan 14 12:32:58 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-bdb0a156-a2c6-4a29-b8b4-65393bc301ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=158605358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.158605358 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.683438057 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 5050761286 ps |
| CPU time | 29.44 seconds |
| Started | Jan 14 12:32:55 PM PST 24 |
| Finished | Jan 14 12:33:25 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-22bb89ad-08f1-4baa-bc60-80897e5c2230 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=683438057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.683438057 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2957070192 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 3789219623 ps |
| CPU time | 30.23 seconds |
| Started | Jan 14 12:32:44 PM PST 24 |
| Finished | Jan 14 12:33:17 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-0a14a9d7-67fb-47f4-b28d-cb9157ff4418 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2957070192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2957070192 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.4192607632 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 53082054 ps |
| CPU time | 2.52 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:32:56 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-8c76487d-d77d-4752-baa4-c205cf1fd778 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192607632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.4192607632 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.976156122 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1820717306 ps |
| CPU time | 56.14 seconds |
| Started | Jan 14 12:32:52 PM PST 24 |
| Finished | Jan 14 12:33:49 PM PST 24 |
| Peak memory | 207220 kb |
| Host | smart-c4c1442a-fa75-4f6a-a2e2-709c03e2a2e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=976156122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.976156122 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2206187718 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 7745798429 ps |
| CPU time | 164.81 seconds |
| Started | Jan 14 12:32:54 PM PST 24 |
| Finished | Jan 14 12:35:40 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-7153a4a6-2e20-4524-b027-b6875f475081 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2206187718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2206187718 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3525360659 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 168890938 ps |
| CPU time | 89.96 seconds |
| Started | Jan 14 12:32:51 PM PST 24 |
| Finished | Jan 14 12:34:22 PM PST 24 |
| Peak memory | 208352 kb |
| Host | smart-58846d85-56f5-4c7a-b057-fd858243c54b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3525360659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.3525360659 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2090635411 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 5292519946 ps |
| CPU time | 268.09 seconds |
| Started | Jan 14 12:32:56 PM PST 24 |
| Finished | Jan 14 12:37:25 PM PST 24 |
| Peak memory | 220064 kb |
| Host | smart-14fa8454-84c7-41e8-bfdd-ed9992953c34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2090635411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2090635411 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.4234767433 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 249537954 ps |
| CPU time | 11 seconds |
| Started | Jan 14 12:32:53 PM PST 24 |
| Finished | Jan 14 12:33:05 PM PST 24 |
| Peak memory | 211872 kb |
| Host | smart-aa88b81a-a9bd-4b0f-bf9c-7a4c704c8c1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4234767433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4234767433 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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