Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 499 1 T5 5 T6 1 T10 1
all_values[1] 550 1 T5 4 T6 1 T11 4
all_values[2] 509 1 T5 3 T23 1 T71 2
all_values[3] 517 1 T5 4 T6 1 T10 1
all_values[4] 541 1 T5 2 T6 1 T10 2
all_values[5] 516 1 T5 2 T11 1 T65 1
all_values[6] 575 1 T5 2 T10 1 T11 6
all_values[7] 526 1 T5 3 T11 2 T14 2
all_values[8] 495 1 T5 2 T6 1 T10 2
all_values[9] 533 1 T5 3 T10 1 T11 1
all_values[10] 529 1 T5 3 T10 3 T11 5
all_values[11] 519 1 T5 9 T10 1 T11 1
all_values[12] 557 1 T5 9 T6 1 T10 1
all_values[13] 500 1 T5 6 T6 1 T10 2
all_values[14] 559 1 T5 7 T10 2 T11 3
all_values[15] 515 1 T5 3 T10 1 T11 1
all_values[16] 564 1 T5 5 T10 1 T11 5
all_values[17] 528 1 T5 8 T6 1 T10 2
all_values[18] 532 1 T5 4 T6 1 T10 1
all_values[19] 533 1 T5 7 T6 1 T10 1
all_values[20] 570 1 T5 13 T16 1 T23 5
all_values[21] 480 1 T5 4 T11 1 T14 1
all_values[22] 522 1 T5 3 T6 1 T11 3
all_values[23] 538 1 T5 8 T6 2 T11 6

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