| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.20 | 99.26 | 90.07 | 98.80 | 95.82 | 99.26 | 100.00 |
| T770 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3151526608 | Jan 17 01:50:54 PM PST 24 | Jan 17 01:55:48 PM PST 24 | 4079051395 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1869427398 | Jan 17 01:52:39 PM PST 24 | Jan 17 01:53:20 PM PST 24 | 9533452597 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2839202237 | Jan 17 01:51:37 PM PST 24 | Jan 17 01:51:42 PM PST 24 | 34896704 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.4053823526 | Jan 17 01:50:54 PM PST 24 | Jan 17 01:52:22 PM PST 24 | 1451758334 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3348121194 | Jan 17 01:50:57 PM PST 24 | Jan 17 01:55:15 PM PST 24 | 75943746228 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1493743838 | Jan 17 01:52:44 PM PST 24 | Jan 17 01:52:52 PM PST 24 | 92116067 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3923946643 | Jan 17 01:54:10 PM PST 24 | Jan 17 01:54:59 PM PST 24 | 1162543377 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1437635657 | Jan 17 01:50:54 PM PST 24 | Jan 17 01:51:25 PM PST 24 | 11273917843 ps | ||
| T278 | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.321093369 | Jan 17 01:49:37 PM PST 24 | Jan 17 01:49:53 PM PST 24 | 326758560 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2394412377 | Jan 17 01:49:50 PM PST 24 | Jan 17 01:52:29 PM PST 24 | 9384621624 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1521958083 | Jan 17 01:49:41 PM PST 24 | Jan 17 01:49:47 PM PST 24 | 194337387 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/33.xbar_random.1060770916 | Jan 17 01:52:30 PM PST 24 | Jan 17 01:52:54 PM PST 24 | 141339711 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/22.xbar_error_random.3227372813 | Jan 17 01:51:08 PM PST 24 | Jan 17 01:51:22 PM PST 24 | 108146070 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2256498952 | Jan 17 01:53:18 PM PST 24 | Jan 17 01:56:08 PM PST 24 | 8955576109 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.817665844 | Jan 17 01:54:31 PM PST 24 | Jan 17 01:54:59 PM PST 24 | 1635023578 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1683232875 | Jan 17 01:53:19 PM PST 24 | Jan 17 01:53:48 PM PST 24 | 4921655634 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1519191628 | Jan 17 01:50:02 PM PST 24 | Jan 17 01:50:40 PM PST 24 | 4640483246 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.4018555984 | Jan 17 01:54:10 PM PST 24 | Jan 17 01:56:02 PM PST 24 | 1109630508 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1037121678 | Jan 17 01:53:34 PM PST 24 | Jan 17 01:53:53 PM PST 24 | 440032861 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3389223215 | Jan 17 01:52:20 PM PST 24 | Jan 17 01:57:17 PM PST 24 | 31866534190 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/25.xbar_same_source.494840579 | Jan 17 01:51:26 PM PST 24 | Jan 17 01:51:54 PM PST 24 | 3356786563 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/16.xbar_random.3987513314 | Jan 17 01:50:29 PM PST 24 | Jan 17 01:50:45 PM PST 24 | 411536496 ps | ||
| T142 | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.4277614130 | Jan 17 01:49:29 PM PST 24 | Jan 17 02:02:27 PM PST 24 | 242086434300 ps | ||
| T305 | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3379702922 | Jan 17 01:52:14 PM PST 24 | Jan 17 01:52:34 PM PST 24 | 109441206 ps | ||
| T263 | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.179842292 | Jan 17 01:50:58 PM PST 24 | Jan 17 01:54:49 PM PST 24 | 71582447789 ps | ||
| T306 | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2262005283 | Jan 17 01:53:36 PM PST 24 | Jan 17 01:54:10 PM PST 24 | 1429516335 ps | ||
| T155 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.882017903 | Jan 17 01:51:46 PM PST 24 | Jan 17 01:52:04 PM PST 24 | 461967310 ps | ||
| T307 | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2499843984 | Jan 17 01:51:24 PM PST 24 | Jan 17 01:51:46 PM PST 24 | 1167921161 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1167500087 | Jan 17 01:54:29 PM PST 24 | Jan 17 01:54:33 PM PST 24 | 6558015 ps | ||
| T36 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.4268563633 | Jan 17 01:53:36 PM PST 24 | Jan 17 01:58:26 PM PST 24 | 1362138360 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.4294863925 | Jan 17 01:54:12 PM PST 24 | Jan 17 01:54:34 PM PST 24 | 498764860 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1555056300 | Jan 17 01:50:13 PM PST 24 | Jan 17 01:50:25 PM PST 24 | 123125419 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2089713678 | Jan 17 01:51:46 PM PST 24 | Jan 17 01:52:27 PM PST 24 | 20487467217 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2366740424 | Jan 17 01:53:44 PM PST 24 | Jan 17 01:55:27 PM PST 24 | 19354138543 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1431918763 | Jan 17 01:53:03 PM PST 24 | Jan 17 01:53:48 PM PST 24 | 7521319271 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3588121009 | Jan 17 01:52:13 PM PST 24 | Jan 17 01:54:57 PM PST 24 | 15986205100 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3032296548 | Jan 17 01:49:49 PM PST 24 | Jan 17 01:49:54 PM PST 24 | 513475636 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3746883206 | Jan 17 01:52:39 PM PST 24 | Jan 17 01:53:11 PM PST 24 | 7412994343 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/49.xbar_same_source.1247961685 | Jan 17 01:54:32 PM PST 24 | Jan 17 01:54:46 PM PST 24 | 816749064 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2578885908 | Jan 17 01:53:06 PM PST 24 | Jan 17 01:54:23 PM PST 24 | 1262338375 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1585106509 | Jan 17 01:49:29 PM PST 24 | Jan 17 01:49:35 PM PST 24 | 509676814 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/40.xbar_error_random.555461465 | Jan 17 01:53:25 PM PST 24 | Jan 17 01:53:33 PM PST 24 | 72502097 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2716262033 | Jan 17 01:52:51 PM PST 24 | Jan 17 01:56:06 PM PST 24 | 6626987420 ps | ||
| T259 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3137699229 | Jan 17 01:52:18 PM PST 24 | Jan 17 01:53:53 PM PST 24 | 1694791717 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/7.xbar_smoke.4097455937 | Jan 17 01:49:37 PM PST 24 | Jan 17 01:49:41 PM PST 24 | 24413527 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.727379516 | Jan 17 01:52:29 PM PST 24 | Jan 17 01:56:18 PM PST 24 | 28450254984 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.4282439273 | Jan 17 01:50:40 PM PST 24 | Jan 17 01:51:22 PM PST 24 | 505962721 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1122276218 | Jan 17 01:53:28 PM PST 24 | Jan 17 01:54:13 PM PST 24 | 11327713018 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/19.xbar_random.3859765825 | Jan 17 01:50:57 PM PST 24 | Jan 17 01:51:07 PM PST 24 | 92146927 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2838551466 | Jan 17 01:49:13 PM PST 24 | Jan 17 01:49:44 PM PST 24 | 4493105490 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.42905464 | Jan 17 01:51:13 PM PST 24 | Jan 17 01:51:50 PM PST 24 | 8680632752 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2967852935 | Jan 17 01:51:25 PM PST 24 | Jan 17 01:51:42 PM PST 24 | 454445435 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.660154656 | Jan 17 01:54:21 PM PST 24 | Jan 17 01:54:31 PM PST 24 | 1570905811 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/11.xbar_random.1816661852 | Jan 17 01:50:08 PM PST 24 | Jan 17 01:50:19 PM PST 24 | 251308193 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1427995871 | Jan 17 01:49:49 PM PST 24 | Jan 17 01:49:59 PM PST 24 | 210924971 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2661520538 | Jan 17 01:50:13 PM PST 24 | Jan 17 01:50:17 PM PST 24 | 53768730 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/47.xbar_same_source.2256019105 | Jan 17 01:54:14 PM PST 24 | Jan 17 01:54:19 PM PST 24 | 71476467 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1708169015 | Jan 17 01:50:37 PM PST 24 | Jan 17 01:51:21 PM PST 24 | 18785524652 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/23.xbar_error_random.518342604 | Jan 17 01:51:20 PM PST 24 | Jan 17 01:51:34 PM PST 24 | 1067294663 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1775348539 | Jan 17 01:49:30 PM PST 24 | Jan 17 01:51:10 PM PST 24 | 324890766 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.831238409 | Jan 17 01:53:36 PM PST 24 | Jan 17 01:57:17 PM PST 24 | 3000161051 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.67000806 | Jan 17 01:54:33 PM PST 24 | Jan 17 01:56:07 PM PST 24 | 16779816184 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1021111740 | Jan 17 01:54:30 PM PST 24 | Jan 17 01:56:24 PM PST 24 | 27772346145 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.563116883 | Jan 17 01:52:33 PM PST 24 | Jan 17 01:53:15 PM PST 24 | 1496229237 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/47.xbar_error_random.866567017 | Jan 17 01:54:18 PM PST 24 | Jan 17 01:54:55 PM PST 24 | 1822047541 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.4266749990 | Jan 17 01:51:56 PM PST 24 | Jan 17 01:52:48 PM PST 24 | 775898218 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3060023721 | Jan 17 01:50:13 PM PST 24 | Jan 17 01:50:53 PM PST 24 | 8831621626 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/13.xbar_random.2468072538 | Jan 17 01:50:13 PM PST 24 | Jan 17 01:50:49 PM PST 24 | 1605261048 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3644017511 | Jan 17 01:53:33 PM PST 24 | Jan 17 01:54:06 PM PST 24 | 1001131501 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/1.xbar_smoke.3773888901 | Jan 17 01:49:14 PM PST 24 | Jan 17 01:49:18 PM PST 24 | 29278532 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/35.xbar_same_source.276066733 | Jan 17 01:52:38 PM PST 24 | Jan 17 01:52:57 PM PST 24 | 1047571960 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1608752859 | Jan 17 01:49:39 PM PST 24 | Jan 17 01:53:34 PM PST 24 | 11457891041 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.325077153 | Jan 17 01:52:34 PM PST 24 | Jan 17 01:52:46 PM PST 24 | 74678043 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3806225614 | Jan 17 01:53:08 PM PST 24 | Jan 17 01:53:11 PM PST 24 | 84575265 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.986421822 | Jan 17 01:52:05 PM PST 24 | Jan 17 01:56:45 PM PST 24 | 112923097917 ps | ||
| T148 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1577433837 | Jan 17 01:51:19 PM PST 24 | Jan 17 01:57:44 PM PST 24 | 6092109239 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1672358240 | Jan 17 01:54:32 PM PST 24 | Jan 17 01:55:19 PM PST 24 | 20470815993 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.32032965 | Jan 17 01:50:34 PM PST 24 | Jan 17 01:50:40 PM PST 24 | 30710665 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1258086590 | Jan 17 01:50:13 PM PST 24 | Jan 17 01:50:17 PM PST 24 | 203232887 ps | ||
| T264 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2790343935 | Jan 17 01:51:56 PM PST 24 | Jan 17 01:57:21 PM PST 24 | 1584915998 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/11.xbar_error_random.3590025955 | Jan 17 01:49:57 PM PST 24 | Jan 17 01:50:18 PM PST 24 | 821170277 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2465697320 | Jan 17 01:49:49 PM PST 24 | Jan 17 02:01:31 PM PST 24 | 99973917795 ps | ||
| T156 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.406187261 | Jan 17 01:51:42 PM PST 24 | Jan 17 01:59:18 PM PST 24 | 126774923446 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1546318043 | Jan 17 01:49:14 PM PST 24 | Jan 17 01:49:18 PM PST 24 | 27580190 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.37449644 | Jan 17 01:50:00 PM PST 24 | Jan 17 01:50:20 PM PST 24 | 116259210 ps | ||
| T38 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2603917005 | Jan 17 01:53:03 PM PST 24 | Jan 17 01:59:29 PM PST 24 | 746569741 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3482707830 | Jan 17 01:52:06 PM PST 24 | Jan 17 01:54:11 PM PST 24 | 712165705 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/35.xbar_smoke.1926127713 | Jan 17 01:52:38 PM PST 24 | Jan 17 01:52:42 PM PST 24 | 36438026 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2420113945 | Jan 17 01:52:07 PM PST 24 | Jan 17 01:54:57 PM PST 24 | 580051095 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/24.xbar_smoke.4016304668 | Jan 17 01:51:19 PM PST 24 | Jan 17 01:51:22 PM PST 24 | 46231338 ps | ||
| T149 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1028323674 | Jan 17 01:53:03 PM PST 24 | Jan 17 01:54:41 PM PST 24 | 4989382791 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3925609393 | Jan 17 01:53:22 PM PST 24 | Jan 17 01:53:46 PM PST 24 | 167869948 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1305062380 | Jan 17 01:53:35 PM PST 24 | Jan 17 01:54:13 PM PST 24 | 5887385131 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3088686544 | Jan 17 01:50:37 PM PST 24 | Jan 17 01:50:45 PM PST 24 | 25137653 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/30.xbar_error_random.4123746464 | Jan 17 01:52:12 PM PST 24 | Jan 17 01:52:22 PM PST 24 | 405132135 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.4178605051 | Jan 17 01:50:38 PM PST 24 | Jan 17 01:51:12 PM PST 24 | 3922220225 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.742116283 | Jan 17 01:52:44 PM PST 24 | Jan 17 01:56:54 PM PST 24 | 114276106842 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1241118594 | Jan 17 01:49:47 PM PST 24 | Jan 17 01:53:39 PM PST 24 | 36947812489 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.4102684046 | Jan 17 01:49:31 PM PST 24 | Jan 17 01:49:41 PM PST 24 | 292770174 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3120204895 | Jan 17 01:50:37 PM PST 24 | Jan 17 01:52:17 PM PST 24 | 656634421 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2821248269 | Jan 17 01:49:47 PM PST 24 | Jan 17 01:49:50 PM PST 24 | 34470070 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/20.xbar_same_source.4076495480 | Jan 17 01:51:07 PM PST 24 | Jan 17 01:51:42 PM PST 24 | 3232001314 ps | ||
| T150 | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3347421961 | Jan 17 01:49:35 PM PST 24 | Jan 17 01:50:18 PM PST 24 | 1776220533 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1454648073 | Jan 17 01:52:11 PM PST 24 | Jan 17 01:52:14 PM PST 24 | 31004240 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/5.xbar_smoke.341102783 | Jan 17 01:49:40 PM PST 24 | Jan 17 01:49:44 PM PST 24 | 132215050 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3809888118 | Jan 17 01:49:49 PM PST 24 | Jan 17 01:50:03 PM PST 24 | 1604511466 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/25.xbar_smoke.3298054768 | Jan 17 01:51:25 PM PST 24 | Jan 17 01:51:32 PM PST 24 | 263540657 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.580480984 | Jan 17 01:53:00 PM PST 24 | Jan 17 01:57:05 PM PST 24 | 48205976133 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3667359086 | Jan 17 01:52:44 PM PST 24 | Jan 17 01:55:29 PM PST 24 | 82361791520 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1554344071 | Jan 17 01:52:38 PM PST 24 | Jan 17 01:55:20 PM PST 24 | 4350625370 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/37.xbar_smoke.2994852953 | Jan 17 01:52:56 PM PST 24 | Jan 17 01:53:01 PM PST 24 | 343211679 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3926571912 | Jan 17 01:52:18 PM PST 24 | Jan 17 01:54:03 PM PST 24 | 27486295362 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/41.xbar_same_source.2366935888 | Jan 17 01:53:40 PM PST 24 | Jan 17 01:54:18 PM PST 24 | 3035503803 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3928613634 | Jan 17 01:50:00 PM PST 24 | Jan 17 01:50:36 PM PST 24 | 6246552064 ps | ||
| T151 | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1998773983 | Jan 17 01:50:06 PM PST 24 | Jan 17 02:02:04 PM PST 24 | 159247893035 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2150273067 | Jan 17 01:49:47 PM PST 24 | Jan 17 01:53:14 PM PST 24 | 58356447115 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/45.xbar_error_random.47788098 | Jan 17 01:54:10 PM PST 24 | Jan 17 01:54:25 PM PST 24 | 170743554 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/32.xbar_smoke.3065488525 | Jan 17 01:52:20 PM PST 24 | Jan 17 01:52:25 PM PST 24 | 29305918 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2225349759 | Jan 17 01:50:02 PM PST 24 | Jan 17 01:51:19 PM PST 24 | 719330587 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2082893426 | Jan 17 01:50:03 PM PST 24 | Jan 17 01:50:08 PM PST 24 | 43434702 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/13.xbar_error_random.698755021 | Jan 17 01:50:14 PM PST 24 | Jan 17 01:50:20 PM PST 24 | 197068978 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3150933978 | Jan 17 01:53:27 PM PST 24 | Jan 17 01:54:16 PM PST 24 | 7286489045 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.4117788752 | Jan 17 01:53:28 PM PST 24 | Jan 17 01:54:04 PM PST 24 | 676997152 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3626782208 | Jan 17 01:54:15 PM PST 24 | Jan 17 01:54:41 PM PST 24 | 208091334 ps | ||
| T30 | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2542314267 | Jan 17 01:53:43 PM PST 24 | Jan 17 02:05:02 PM PST 24 | 18981139960 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1284502663 | Jan 17 01:50:15 PM PST 24 | Jan 17 01:52:57 PM PST 24 | 6909347938 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1761094350 | Jan 17 01:52:35 PM PST 24 | Jan 17 01:54:04 PM PST 24 | 194312406 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/12.xbar_random.2417461666 | Jan 17 01:50:12 PM PST 24 | Jan 17 01:50:34 PM PST 24 | 2476072099 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.362409977 | Jan 17 01:53:45 PM PST 24 | Jan 17 01:54:19 PM PST 24 | 9722579851 ps | ||
| T265 | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2269876008 | Jan 17 01:51:55 PM PST 24 | Jan 17 01:59:31 PM PST 24 | 65981797574 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2608305731 | Jan 17 01:52:51 PM PST 24 | Jan 17 01:52:58 PM PST 24 | 45613862 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2688893022 | Jan 17 01:50:01 PM PST 24 | Jan 17 01:50:13 PM PST 24 | 63839224 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.4006819502 | Jan 17 01:50:18 PM PST 24 | Jan 17 01:50:21 PM PST 24 | 29631989 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2794715700 | Jan 17 01:50:50 PM PST 24 | Jan 17 01:51:29 PM PST 24 | 11126748411 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2120867879 | Jan 17 01:53:37 PM PST 24 | Jan 17 01:54:08 PM PST 24 | 2694656520 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/10.xbar_smoke.755749576 | Jan 17 01:50:00 PM PST 24 | Jan 17 01:50:10 PM PST 24 | 191467627 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.4053663270 | Jan 17 01:50:03 PM PST 24 | Jan 17 01:50:27 PM PST 24 | 159516555 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/22.xbar_random.2283809294 | Jan 17 01:51:08 PM PST 24 | Jan 17 01:51:22 PM PST 24 | 122484507 ps | ||
| T152 | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3080732642 | Jan 17 01:49:47 PM PST 24 | Jan 17 01:50:25 PM PST 24 | 2655934691 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2774739023 | Jan 17 01:49:15 PM PST 24 | Jan 17 01:49:34 PM PST 24 | 715768080 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1658692080 | Jan 17 01:50:27 PM PST 24 | Jan 17 01:51:05 PM PST 24 | 9744709896 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/15.xbar_error_random.689855785 | Jan 17 01:50:20 PM PST 24 | Jan 17 01:50:25 PM PST 24 | 42490937 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1593614137 | Jan 17 01:53:32 PM PST 24 | Jan 17 02:00:36 PM PST 24 | 270259459707 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1902420344 | Jan 17 01:53:35 PM PST 24 | Jan 17 01:53:57 PM PST 24 | 223557602 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/12.xbar_error_random.283584650 | Jan 17 01:50:15 PM PST 24 | Jan 17 01:50:40 PM PST 24 | 205631044 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1909524459 | Jan 17 01:53:34 PM PST 24 | Jan 17 01:54:54 PM PST 24 | 2170061963 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2962229886 | Jan 17 01:52:07 PM PST 24 | Jan 17 01:52:40 PM PST 24 | 10451520174 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.646048102 | Jan 17 01:52:02 PM PST 24 | Jan 17 01:58:34 PM PST 24 | 5971885577 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2152535546 | Jan 17 01:50:03 PM PST 24 | Jan 17 01:54:02 PM PST 24 | 775541656 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.809592176 | Jan 17 01:49:35 PM PST 24 | Jan 17 01:49:47 PM PST 24 | 98846877 ps |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2688372996 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 35390439246 ps |
| CPU time | 269.28 seconds |
| Started | Jan 17 01:51:29 PM PST 24 |
| Finished | Jan 17 01:56:01 PM PST 24 |
| Peak memory | 207132 kb |
| Host | smart-b7884bf8-8c4e-426f-8bbe-47a363628e68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2688372996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2688372996 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3610147316 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 77082730519 ps |
| CPU time | 668.44 seconds |
| Started | Jan 17 01:51:26 PM PST 24 |
| Finished | Jan 17 02:02:40 PM PST 24 |
| Peak memory | 207608 kb |
| Host | smart-5a44e9c2-ff1d-4345-befc-7e3032217816 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3610147316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.3610147316 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2010349714 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 262304237025 ps |
| CPU time | 544.87 seconds |
| Started | Jan 17 01:49:36 PM PST 24 |
| Finished | Jan 17 01:58:43 PM PST 24 |
| Peak memory | 211924 kb |
| Host | smart-5ef48f0b-f177-4cfb-ac45-b410980b35b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2010349714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.2010349714 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2368348483 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 135578335719 ps |
| CPU time | 575.39 seconds |
| Started | Jan 17 01:50:24 PM PST 24 |
| Finished | Jan 17 02:00:02 PM PST 24 |
| Peak memory | 207252 kb |
| Host | smart-f252a409-40d4-4a25-a342-e9ea2553697d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2368348483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.2368348483 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.4243505402 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 16143482 ps |
| CPU time | 2.18 seconds |
| Started | Jan 17 01:51:02 PM PST 24 |
| Finished | Jan 17 01:51:10 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-d489962f-9a98-4d4b-8830-cdfd5990f937 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243505402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.4243505402 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2749636702 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 112128019254 ps |
| CPU time | 272.06 seconds |
| Started | Jan 17 01:49:56 PM PST 24 |
| Finished | Jan 17 01:54:30 PM PST 24 |
| Peak memory | 205280 kb |
| Host | smart-43b2cfe2-612c-4a0c-bd0c-dff01e1d2096 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2749636702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2749636702 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3196772886 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 164102363854 ps |
| CPU time | 780.53 seconds |
| Started | Jan 17 01:52:37 PM PST 24 |
| Finished | Jan 17 02:05:40 PM PST 24 |
| Peak memory | 211988 kb |
| Host | smart-9c667853-5eb6-4b0c-8455-3eee46d3d88d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3196772886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.3196772886 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.452771738 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 31982357106 ps |
| CPU time | 148.59 seconds |
| Started | Jan 17 01:50:00 PM PST 24 |
| Finished | Jan 17 01:52:35 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-fc1eca01-1e27-4a7e-964b-171903361288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=452771738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.452771738 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2249562798 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 15200063212 ps |
| CPU time | 707.63 seconds |
| Started | Jan 17 01:49:51 PM PST 24 |
| Finished | Jan 17 02:01:40 PM PST 24 |
| Peak memory | 223776 kb |
| Host | smart-aaf99a89-38e0-4abd-a971-5b4613591f1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2249562798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.2249562798 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2554728912 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 7247418920 ps |
| CPU time | 408.31 seconds |
| Started | Jan 17 01:51:37 PM PST 24 |
| Finished | Jan 17 01:58:28 PM PST 24 |
| Peak memory | 210584 kb |
| Host | smart-a2897d83-4acb-4fa6-96eb-c4ab7d5a4dc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2554728912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.2554728912 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2641750212 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9392116723 ps |
| CPU time | 192.05 seconds |
| Started | Jan 17 01:54:12 PM PST 24 |
| Finished | Jan 17 01:57:25 PM PST 24 |
| Peak memory | 208960 kb |
| Host | smart-f13133d2-df3a-417b-958d-f8f0bf259990 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2641750212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2641750212 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.4277614130 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 242086434300 ps |
| CPU time | 777.39 seconds |
| Started | Jan 17 01:49:29 PM PST 24 |
| Finished | Jan 17 02:02:27 PM PST 24 |
| Peak memory | 211896 kb |
| Host | smart-f983ffe0-aeb7-463e-9687-71b06d2a3092 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4277614130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.4277614130 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.796075708 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 12754587148 ps |
| CPU time | 505.62 seconds |
| Started | Jan 17 01:52:05 PM PST 24 |
| Finished | Jan 17 02:00:32 PM PST 24 |
| Peak memory | 220268 kb |
| Host | smart-0048065b-eaab-4302-9ad8-3ef5778bd2a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=796075708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand _reset.796075708 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.2678118356 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 666893640 ps |
| CPU time | 234.21 seconds |
| Started | Jan 17 01:50:37 PM PST 24 |
| Finished | Jan 17 01:54:37 PM PST 24 |
| Peak memory | 211620 kb |
| Host | smart-d2a20d7c-3c8d-464f-871d-21b25691db4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2678118356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.2678118356 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2542314267 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 18981139960 ps |
| CPU time | 677.87 seconds |
| Started | Jan 17 01:53:43 PM PST 24 |
| Finished | Jan 17 02:05:02 PM PST 24 |
| Peak memory | 220192 kb |
| Host | smart-aa57d1a0-f32f-4abf-bfd7-b942d4c2bb24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2542314267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.2542314267 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3282095518 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 8055884258 ps |
| CPU time | 283.35 seconds |
| Started | Jan 17 01:51:08 PM PST 24 |
| Finished | Jan 17 01:55:52 PM PST 24 |
| Peak memory | 212016 kb |
| Host | smart-aee0a971-889d-4360-ad0f-4855f9bf2152 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3282095518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.3282095518 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1675908428 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 14988175012 ps |
| CPU time | 409.96 seconds |
| Started | Jan 17 01:51:10 PM PST 24 |
| Finished | Jan 17 01:58:01 PM PST 24 |
| Peak memory | 210128 kb |
| Host | smart-7e90e58e-4d70-4272-aa59-f089170ed547 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1675908428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.1675908428 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3105266360 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1936219777 ps |
| CPU time | 21.5 seconds |
| Started | Jan 17 01:54:03 PM PST 24 |
| Finished | Jan 17 01:54:28 PM PST 24 |
| Peak memory | 204840 kb |
| Host | smart-c4d93109-8496-4850-a1fa-feb53dfd9600 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3105266360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3105266360 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.775691640 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4097552375 ps |
| CPU time | 315.16 seconds |
| Started | Jan 17 01:49:35 PM PST 24 |
| Finished | Jan 17 01:54:53 PM PST 24 |
| Peak memory | 220276 kb |
| Host | smart-33d3bb1a-34f5-4106-97c7-52156f1bf0b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=775691640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese t_error.775691640 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2603917005 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 746569741 ps |
| CPU time | 381.72 seconds |
| Started | Jan 17 01:53:03 PM PST 24 |
| Finished | Jan 17 01:59:29 PM PST 24 |
| Peak memory | 209732 kb |
| Host | smart-d6cf1bca-1d1f-4520-854a-2edf6637e6a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2603917005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.2603917005 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2662408309 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 21721658937 ps |
| CPU time | 747.71 seconds |
| Started | Jan 17 01:50:01 PM PST 24 |
| Finished | Jan 17 02:02:34 PM PST 24 |
| Peak memory | 225108 kb |
| Host | smart-8986ab82-1523-473a-9f40-62720a1775a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662408309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.2662408309 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.1102799858 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 239754010 ps |
| CPU time | 24.06 seconds |
| Started | Jan 17 01:50:27 PM PST 24 |
| Finished | Jan 17 01:50:52 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-b4be217f-7dcb-4eb7-9a3e-0fd0ec5438a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1102799858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1102799858 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1274567069 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 194930054418 ps |
| CPU time | 690.74 seconds |
| Started | Jan 17 01:50:44 PM PST 24 |
| Finished | Jan 17 02:02:15 PM PST 24 |
| Peak memory | 207820 kb |
| Host | smart-d1ed32fb-fcb6-4313-9cb0-1eaf907bc639 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1274567069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.1274567069 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2139891589 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 503686417 ps |
| CPU time | 20.57 seconds |
| Started | Jan 17 01:49:11 PM PST 24 |
| Finished | Jan 17 01:49:33 PM PST 24 |
| Peak memory | 205684 kb |
| Host | smart-d14cc73e-c0a0-4811-bae3-8e6556ecfee0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2139891589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2139891589 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2380047394 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 97015300750 ps |
| CPU time | 617.14 seconds |
| Started | Jan 17 01:49:07 PM PST 24 |
| Finished | Jan 17 01:59:25 PM PST 24 |
| Peak memory | 207996 kb |
| Host | smart-4ac9981c-4701-40e8-b039-ed2b1d615deb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2380047394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.2380047394 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.269261358 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 104638533 ps |
| CPU time | 13.49 seconds |
| Started | Jan 17 01:49:17 PM PST 24 |
| Finished | Jan 17 01:49:37 PM PST 24 |
| Peak memory | 203836 kb |
| Host | smart-20fbd2d3-46b7-408a-abbc-7595e6f8c7d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=269261358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.269261358 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.574801408 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 762029559 ps |
| CPU time | 16.15 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:49:33 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-f3b897c5-c4c7-493f-b796-dca6ff79f31e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=574801408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.574801408 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.3582052874 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 107580602 ps |
| CPU time | 15.58 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:49:32 PM PST 24 |
| Peak memory | 211964 kb |
| Host | smart-d34f43e9-98b2-4d9c-8350-9ff516eb7b6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3582052874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3582052874 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2855801307 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 8143978692 ps |
| CPU time | 40.23 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:49:56 PM PST 24 |
| Peak memory | 212016 kb |
| Host | smart-525e8c01-a902-4355-bab5-a853e66d6536 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855801307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2855801307 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3601402213 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 51174272402 ps |
| CPU time | 190.64 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:52:27 PM PST 24 |
| Peak memory | 205340 kb |
| Host | smart-76dd40a3-e3ab-45de-bb14-eaa43481d15b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3601402213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3601402213 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3357057779 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 432104117 ps |
| CPU time | 24.36 seconds |
| Started | Jan 17 01:49:14 PM PST 24 |
| Finished | Jan 17 01:49:40 PM PST 24 |
| Peak memory | 211916 kb |
| Host | smart-c0c9dccf-8354-45b3-af0d-2d7f40b57950 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357057779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3357057779 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.4135886981 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 524522137 ps |
| CPU time | 19.53 seconds |
| Started | Jan 17 01:49:14 PM PST 24 |
| Finished | Jan 17 01:49:36 PM PST 24 |
| Peak memory | 204196 kb |
| Host | smart-3bff4a76-e072-4e1a-be63-120cfcf7dc9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4135886981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4135886981 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.958917259 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 455632731 ps |
| CPU time | 3.21 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:49:19 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-b3f7249b-4610-4032-9848-0a8f995a7ec6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=958917259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.958917259 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.237976619 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 10880291921 ps |
| CPU time | 34.25 seconds |
| Started | Jan 17 01:49:12 PM PST 24 |
| Finished | Jan 17 01:49:49 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-ab9842ce-f976-4667-b217-c16f2be5e111 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=237976619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.237976619 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2838551466 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4493105490 ps |
| CPU time | 27.71 seconds |
| Started | Jan 17 01:49:13 PM PST 24 |
| Finished | Jan 17 01:49:44 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-96b874fe-e185-455f-b480-5101d9398719 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2838551466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2838551466 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.1694919192 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 29079392 ps |
| CPU time | 2.42 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:49:19 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-f5618a7b-d5ce-4b64-aae5-7390cec4cd87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694919192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1694919192 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.56729665 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4459691592 ps |
| CPU time | 154.87 seconds |
| Started | Jan 17 01:49:27 PM PST 24 |
| Finished | Jan 17 01:52:03 PM PST 24 |
| Peak memory | 207448 kb |
| Host | smart-636454be-903a-4237-9414-ddbb3f04f94e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=56729665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.56729665 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.91001497 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 3445479741 ps |
| CPU time | 121.66 seconds |
| Started | Jan 17 01:49:13 PM PST 24 |
| Finished | Jan 17 01:51:17 PM PST 24 |
| Peak memory | 206112 kb |
| Host | smart-a05a03d2-30d2-48ba-8fed-20b38a66bc42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=91001497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.91001497 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1508919225 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 854587900 ps |
| CPU time | 317.99 seconds |
| Started | Jan 17 01:49:14 PM PST 24 |
| Finished | Jan 17 01:54:34 PM PST 24 |
| Peak memory | 210532 kb |
| Host | smart-cf0bab15-d107-471f-b79c-45855d6367a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1508919225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1508919225 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2917182626 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1454080027 ps |
| CPU time | 207.51 seconds |
| Started | Jan 17 01:49:13 PM PST 24 |
| Finished | Jan 17 01:52:43 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-0b09273a-9154-4c59-9161-c268ae9e894f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2917182626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.2917182626 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.289708555 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 874232914 ps |
| CPU time | 30.22 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:49:47 PM PST 24 |
| Peak memory | 204504 kb |
| Host | smart-802bc1c7-96bf-4c8b-be44-1c6c8057695d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=289708555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.289708555 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.3660289942 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 242290477 ps |
| CPU time | 17.93 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:49:34 PM PST 24 |
| Peak memory | 211904 kb |
| Host | smart-1ba25030-6231-4c17-8e9a-26c2b485b786 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3660289942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3660289942 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1025177604 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 15599510502 ps |
| CPU time | 147.47 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:51:44 PM PST 24 |
| Peak memory | 211960 kb |
| Host | smart-10634dce-2e9d-46f5-945e-645be4f66314 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1025177604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.1025177604 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3455189460 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 34132191 ps |
| CPU time | 4.61 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:49:21 PM PST 24 |
| Peak memory | 203872 kb |
| Host | smart-d02f0f37-ba78-4841-94ae-e566d24c4004 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3455189460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3455189460 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.3554185780 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2689771922 ps |
| CPU time | 35.56 seconds |
| Started | Jan 17 01:49:14 PM PST 24 |
| Finished | Jan 17 01:49:52 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-631dd1a5-9363-4104-96dc-ef8d14fad014 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3554185780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3554185780 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.957332822 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 4756339743 ps |
| CPU time | 26.46 seconds |
| Started | Jan 17 01:49:16 PM PST 24 |
| Finished | Jan 17 01:49:43 PM PST 24 |
| Peak memory | 212028 kb |
| Host | smart-067f4cfd-f166-4039-af83-89429fe9e64f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=957332822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.957332822 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.197208770 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 178998954264 ps |
| CPU time | 347.45 seconds |
| Started | Jan 17 01:49:16 PM PST 24 |
| Finished | Jan 17 01:55:04 PM PST 24 |
| Peak memory | 210560 kb |
| Host | smart-dd71fbf6-d495-42ab-a628-00241b1a4b02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=197208770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.197208770 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3214869776 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 30571082656 ps |
| CPU time | 202.84 seconds |
| Started | Jan 17 01:49:16 PM PST 24 |
| Finished | Jan 17 01:52:40 PM PST 24 |
| Peak memory | 212020 kb |
| Host | smart-0c15d25d-8949-4c20-a9ab-4343547df148 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3214869776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3214869776 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.4059952200 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 216443675 ps |
| CPU time | 26.3 seconds |
| Started | Jan 17 01:49:14 PM PST 24 |
| Finished | Jan 17 01:49:42 PM PST 24 |
| Peak memory | 205076 kb |
| Host | smart-51af4243-3aa7-4190-8273-fb30e92164e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059952200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.4059952200 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2774739023 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 715768080 ps |
| CPU time | 17.07 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:49:34 PM PST 24 |
| Peak memory | 204068 kb |
| Host | smart-d43549f6-8123-4ad3-a15d-b9c37678f4ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2774739023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2774739023 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.3773888901 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 29278532 ps |
| CPU time | 2.38 seconds |
| Started | Jan 17 01:49:14 PM PST 24 |
| Finished | Jan 17 01:49:18 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-cf3a60b5-5a53-4a61-9eca-6802939262ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3773888901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3773888901 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1207668682 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 5603966794 ps |
| CPU time | 28.42 seconds |
| Started | Jan 17 01:49:16 PM PST 24 |
| Finished | Jan 17 01:49:45 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-2970dbd9-75ac-4f32-bf8b-816be4e56aea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207668682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1207668682 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2961323196 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5060054153 ps |
| CPU time | 23.92 seconds |
| Started | Jan 17 01:49:13 PM PST 24 |
| Finished | Jan 17 01:49:40 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-7065d4a8-d355-4e95-9eba-3ecc753affeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2961323196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2961323196 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1546318043 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 27580190 ps |
| CPU time | 2.36 seconds |
| Started | Jan 17 01:49:14 PM PST 24 |
| Finished | Jan 17 01:49:18 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-f78a8964-c6a7-47ca-9bd1-9d15ec0f9c3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546318043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1546318043 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.303933573 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 3778068296 ps |
| CPU time | 152.24 seconds |
| Started | Jan 17 01:49:15 PM PST 24 |
| Finished | Jan 17 01:51:49 PM PST 24 |
| Peak memory | 208244 kb |
| Host | smart-3a991243-7dd2-4766-ba67-3c236c7e02c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=303933573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.303933573 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.52444042 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1754978147 ps |
| CPU time | 146.72 seconds |
| Started | Jan 17 01:49:16 PM PST 24 |
| Finished | Jan 17 01:51:44 PM PST 24 |
| Peak memory | 207688 kb |
| Host | smart-f73ad5b8-7459-497d-a5e2-f88d7ae054a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=52444042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.52444042 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2693410871 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 217518705 ps |
| CPU time | 34.17 seconds |
| Started | Jan 17 01:49:14 PM PST 24 |
| Finished | Jan 17 01:49:50 PM PST 24 |
| Peak memory | 206700 kb |
| Host | smart-bf431295-dd3a-4085-b41c-7b81fd2949c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2693410871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.2693410871 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.4011673381 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 79825910 ps |
| CPU time | 24.83 seconds |
| Started | Jan 17 01:49:14 PM PST 24 |
| Finished | Jan 17 01:49:41 PM PST 24 |
| Peak memory | 206120 kb |
| Host | smart-f24e30b8-f95d-4636-b0f3-57fc957bbf61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4011673381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.4011673381 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.591292987 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 838904075 ps |
| CPU time | 17.89 seconds |
| Started | Jan 17 01:49:16 PM PST 24 |
| Finished | Jan 17 01:49:35 PM PST 24 |
| Peak memory | 211992 kb |
| Host | smart-83698334-d6b2-464a-8933-2d05f2598cd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=591292987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.591292987 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.3874804560 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 479537489 ps |
| CPU time | 35.3 seconds |
| Started | Jan 17 01:50:04 PM PST 24 |
| Finished | Jan 17 01:50:42 PM PST 24 |
| Peak memory | 204464 kb |
| Host | smart-186f85e0-1e46-4085-a970-51c3db81fe73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3874804560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3874804560 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1519191628 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 4640483246 ps |
| CPU time | 34.09 seconds |
| Started | Jan 17 01:50:02 PM PST 24 |
| Finished | Jan 17 01:50:40 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-067713da-1bd6-4be4-b9fe-186e463b526b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1519191628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1519191628 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2688893022 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 63839224 ps |
| CPU time | 7.31 seconds |
| Started | Jan 17 01:50:01 PM PST 24 |
| Finished | Jan 17 01:50:13 PM PST 24 |
| Peak memory | 203888 kb |
| Host | smart-52cb669c-60ea-4fb3-89a7-d0ba371379f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2688893022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2688893022 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.607514234 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 966790371 ps |
| CPU time | 30.75 seconds |
| Started | Jan 17 01:50:01 PM PST 24 |
| Finished | Jan 17 01:50:37 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-d08f8610-e53e-4542-89b0-2a588c7f2580 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=607514234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.607514234 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.4228741451 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 186735616 ps |
| CPU time | 30.3 seconds |
| Started | Jan 17 01:50:03 PM PST 24 |
| Finished | Jan 17 01:50:36 PM PST 24 |
| Peak memory | 211992 kb |
| Host | smart-daa90e7b-65b0-46a8-8ad1-bf062a0513e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4228741451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.4228741451 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3780530818 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 232420970214 ps |
| CPU time | 382.88 seconds |
| Started | Jan 17 01:50:01 PM PST 24 |
| Finished | Jan 17 01:56:29 PM PST 24 |
| Peak memory | 205516 kb |
| Host | smart-ce903a08-536d-4a5b-936e-498214f45b93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780530818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3780530818 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2266104347 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 73645934 ps |
| CPU time | 9.33 seconds |
| Started | Jan 17 01:49:57 PM PST 24 |
| Finished | Jan 17 01:50:07 PM PST 24 |
| Peak memory | 204768 kb |
| Host | smart-a685b934-21d0-4a74-9533-07f0c89ee669 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266104347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2266104347 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.3715098684 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 160714022 ps |
| CPU time | 3.45 seconds |
| Started | Jan 17 01:49:57 PM PST 24 |
| Finished | Jan 17 01:50:07 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-1d58a576-c53f-4e92-9adc-e855bb5dfa08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3715098684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3715098684 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.755749576 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 191467627 ps |
| CPU time | 3.95 seconds |
| Started | Jan 17 01:50:00 PM PST 24 |
| Finished | Jan 17 01:50:10 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-d6d7c6d5-7c4c-468d-ac7e-67c7d24e5220 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=755749576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.755749576 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2049511130 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 32752946373 ps |
| CPU time | 46.82 seconds |
| Started | Jan 17 01:49:55 PM PST 24 |
| Finished | Jan 17 01:50:44 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-bcdf48fc-bf4d-4eb0-a29a-cdf525326c37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049511130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2049511130 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3331685758 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 6491894983 ps |
| CPU time | 32.25 seconds |
| Started | Jan 17 01:50:04 PM PST 24 |
| Finished | Jan 17 01:50:39 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-c448b064-c704-42c4-b8d9-18b27934ac20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3331685758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3331685758 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2752331182 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 29051930 ps |
| CPU time | 2.24 seconds |
| Started | Jan 17 01:50:01 PM PST 24 |
| Finished | Jan 17 01:50:08 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-09e544d9-d207-4828-8469-ceca9c5f9691 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752331182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2752331182 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.2396688919 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3482683556 ps |
| CPU time | 57.73 seconds |
| Started | Jan 17 01:49:57 PM PST 24 |
| Finished | Jan 17 01:50:55 PM PST 24 |
| Peak memory | 206480 kb |
| Host | smart-10e6e42a-eeb6-45b5-9cf7-4a61022d9f6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2396688919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2396688919 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3676238755 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 822468580 ps |
| CPU time | 18.73 seconds |
| Started | Jan 17 01:49:59 PM PST 24 |
| Finished | Jan 17 01:50:25 PM PST 24 |
| Peak memory | 204348 kb |
| Host | smart-9424007b-e967-4b03-886b-feb396b88560 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3676238755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3676238755 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2152535546 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 775541656 ps |
| CPU time | 235.91 seconds |
| Started | Jan 17 01:50:03 PM PST 24 |
| Finished | Jan 17 01:54:02 PM PST 24 |
| Peak memory | 220140 kb |
| Host | smart-93e04b03-9b1f-4979-922c-9bbd9f5bca14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2152535546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.2152535546 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1268485932 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 956369581 ps |
| CPU time | 27.73 seconds |
| Started | Jan 17 01:50:02 PM PST 24 |
| Finished | Jan 17 01:50:34 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-bed5994c-a493-411e-b788-25805d30e449 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1268485932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1268485932 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.1776518048 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 465264160 ps |
| CPU time | 19.92 seconds |
| Started | Jan 17 01:49:57 PM PST 24 |
| Finished | Jan 17 01:50:18 PM PST 24 |
| Peak memory | 211856 kb |
| Host | smart-893f7092-acf1-4ed0-b804-dd4a376961a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1776518048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1776518048 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.907679593 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 46042303122 ps |
| CPU time | 419.9 seconds |
| Started | Jan 17 01:49:59 PM PST 24 |
| Finished | Jan 17 01:57:06 PM PST 24 |
| Peak memory | 206372 kb |
| Host | smart-4cf2e4d2-a6cf-4a05-9966-15c8f42ffaea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=907679593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slo w_rsp.907679593 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1222386006 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 385273736 ps |
| CPU time | 10.33 seconds |
| Started | Jan 17 01:50:02 PM PST 24 |
| Finished | Jan 17 01:50:16 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-d918192c-7173-41ec-a073-abf9d1228796 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1222386006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1222386006 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.3590025955 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 821170277 ps |
| CPU time | 20.1 seconds |
| Started | Jan 17 01:49:57 PM PST 24 |
| Finished | Jan 17 01:50:18 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-cb1be7c2-1b20-4dbd-9662-30d967c86fe0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3590025955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3590025955 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.1816661852 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 251308193 ps |
| CPU time | 9.76 seconds |
| Started | Jan 17 01:50:08 PM PST 24 |
| Finished | Jan 17 01:50:19 PM PST 24 |
| Peak memory | 204404 kb |
| Host | smart-aedadce3-a779-4939-a447-71ee35de6220 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1816661852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1816661852 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.4153347880 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 43538451623 ps |
| CPU time | 139.72 seconds |
| Started | Jan 17 01:50:03 PM PST 24 |
| Finished | Jan 17 01:52:26 PM PST 24 |
| Peak memory | 205040 kb |
| Host | smart-97b92e54-e820-4747-ba74-159bdc120955 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153347880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.4153347880 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3862395174 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 35167934407 ps |
| CPU time | 100.26 seconds |
| Started | Jan 17 01:50:00 PM PST 24 |
| Finished | Jan 17 01:51:46 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-20ac1378-daa4-43b9-a592-bd9100a56c4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3862395174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3862395174 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.4053663270 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 159516555 ps |
| CPU time | 21.2 seconds |
| Started | Jan 17 01:50:03 PM PST 24 |
| Finished | Jan 17 01:50:27 PM PST 24 |
| Peak memory | 204492 kb |
| Host | smart-b8869cfc-396c-4123-88dd-6b06b425f163 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053663270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.4053663270 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.3495747443 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 388707549 ps |
| CPU time | 6.13 seconds |
| Started | Jan 17 01:50:03 PM PST 24 |
| Finished | Jan 17 01:50:12 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-51e93d84-3eff-45cc-9eda-072b513a0c60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3495747443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3495747443 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2104332908 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 38334342 ps |
| CPU time | 2.44 seconds |
| Started | Jan 17 01:50:06 PM PST 24 |
| Finished | Jan 17 01:50:10 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-4b74f4e7-f206-4611-ad7a-3a7b3dfeb4b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2104332908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2104332908 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3995759325 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 6627931784 ps |
| CPU time | 27.25 seconds |
| Started | Jan 17 01:50:03 PM PST 24 |
| Finished | Jan 17 01:50:33 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-03b892a2-a2c1-45b0-ac37-8a270de5116b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995759325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3995759325 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2279832215 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 11038652337 ps |
| CPU time | 26.81 seconds |
| Started | Jan 17 01:50:00 PM PST 24 |
| Finished | Jan 17 01:50:33 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-bf60003c-2f15-4747-89e9-250c199701fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2279832215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2279832215 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2082893426 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 43434702 ps |
| CPU time | 1.99 seconds |
| Started | Jan 17 01:50:03 PM PST 24 |
| Finished | Jan 17 01:50:08 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-5d1ef420-dc0e-4afb-9720-4f9dd13ab46c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082893426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2082893426 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2225349759 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 719330587 ps |
| CPU time | 73.01 seconds |
| Started | Jan 17 01:50:02 PM PST 24 |
| Finished | Jan 17 01:51:19 PM PST 24 |
| Peak memory | 207116 kb |
| Host | smart-114bac27-8276-43c4-88c2-40d8bb16681a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2225349759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2225349759 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2688626021 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 28698799011 ps |
| CPU time | 198.55 seconds |
| Started | Jan 17 01:50:15 PM PST 24 |
| Finished | Jan 17 01:53:35 PM PST 24 |
| Peak memory | 205844 kb |
| Host | smart-40510a48-dff7-41dc-a2c3-7d0fc110d109 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2688626021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2688626021 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2200465570 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3946167507 ps |
| CPU time | 519.55 seconds |
| Started | Jan 17 01:50:17 PM PST 24 |
| Finished | Jan 17 01:58:58 PM PST 24 |
| Peak memory | 220156 kb |
| Host | smart-eb4347cc-d6a5-442d-b303-d32a643c32f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2200465570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.2200465570 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.989990920 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 787034910 ps |
| CPU time | 158.18 seconds |
| Started | Jan 17 01:50:08 PM PST 24 |
| Finished | Jan 17 01:52:47 PM PST 24 |
| Peak memory | 211760 kb |
| Host | smart-c6f0c547-4d39-4b47-a3bf-27b2bf6ee01a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=989990920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_res et_error.989990920 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.3968260305 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 84848841 ps |
| CPU time | 11.82 seconds |
| Started | Jan 17 01:50:03 PM PST 24 |
| Finished | Jan 17 01:50:18 PM PST 24 |
| Peak memory | 205020 kb |
| Host | smart-5c114aaf-c580-42ed-a241-a6071828860b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3968260305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3968260305 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.670875727 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1070940330 ps |
| CPU time | 33.46 seconds |
| Started | Jan 17 01:50:15 PM PST 24 |
| Finished | Jan 17 01:50:49 PM PST 24 |
| Peak memory | 205880 kb |
| Host | smart-3df18d89-ccde-4466-945d-dd98aad0e61a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=670875727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.670875727 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.74209601 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 19277832084 ps |
| CPU time | 162.5 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:52:57 PM PST 24 |
| Peak memory | 206340 kb |
| Host | smart-9763302d-830a-42c7-ad7a-724b95d5cb1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=74209601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow _rsp.74209601 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.611522255 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 79877612 ps |
| CPU time | 11.31 seconds |
| Started | Jan 17 01:50:15 PM PST 24 |
| Finished | Jan 17 01:50:27 PM PST 24 |
| Peak memory | 203840 kb |
| Host | smart-9e2583ec-0e62-4c84-a2b8-5ef4b6b93532 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=611522255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.611522255 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.283584650 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 205631044 ps |
| CPU time | 24.99 seconds |
| Started | Jan 17 01:50:15 PM PST 24 |
| Finished | Jan 17 01:50:40 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-8a51b1d6-4220-40a4-b91c-da21d29f8665 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=283584650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.283584650 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.2417461666 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2476072099 ps |
| CPU time | 21.12 seconds |
| Started | Jan 17 01:50:12 PM PST 24 |
| Finished | Jan 17 01:50:34 PM PST 24 |
| Peak memory | 204600 kb |
| Host | smart-79ea6d33-1d46-4602-8682-3a7326f3c249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2417461666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2417461666 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3060023721 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 8831621626 ps |
| CPU time | 38.96 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:53 PM PST 24 |
| Peak memory | 204952 kb |
| Host | smart-eac938a2-8ae1-4982-af08-953ae3b3fd08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060023721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3060023721 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2051902461 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 16586441923 ps |
| CPU time | 82.01 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:51:36 PM PST 24 |
| Peak memory | 211996 kb |
| Host | smart-0eed0bc7-7b34-4f2a-b7ed-0778cbc6bbb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2051902461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2051902461 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.896248524 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 44783524 ps |
| CPU time | 3.56 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:18 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-95691633-439f-41f7-babe-7d40afa5d075 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896248524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.896248524 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.422109600 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 20545921 ps |
| CPU time | 1.96 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:50:22 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-bd0a1f6d-8f52-4073-8c66-fc8bb471756a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=422109600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.422109600 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.4292447458 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 572484450 ps |
| CPU time | 3.94 seconds |
| Started | Jan 17 01:50:06 PM PST 24 |
| Finished | Jan 17 01:50:12 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-6921590f-d349-4db9-beaf-434c75387afe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4292447458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.4292447458 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1306326235 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 19860712953 ps |
| CPU time | 36.16 seconds |
| Started | Jan 17 01:50:18 PM PST 24 |
| Finished | Jan 17 01:50:55 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-206107dd-c100-4b1b-bd4c-8eb3953b4a85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306326235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1306326235 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1078194022 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 6377073578 ps |
| CPU time | 29.04 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:43 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-58e0e796-ee11-49fe-9051-855aa0b7478d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1078194022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1078194022 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.846915065 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 37987540 ps |
| CPU time | 2.47 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:16 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-07ed35d6-6140-4d40-b8aa-7cdd3955637b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846915065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.846915065 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.1016428878 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 28769171850 ps |
| CPU time | 370.62 seconds |
| Started | Jan 17 01:50:14 PM PST 24 |
| Finished | Jan 17 01:56:25 PM PST 24 |
| Peak memory | 207580 kb |
| Host | smart-09292a67-e066-4157-b450-0c60e6a07ed3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1016428878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1016428878 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.541871192 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1475623660 ps |
| CPU time | 125.68 seconds |
| Started | Jan 17 01:50:08 PM PST 24 |
| Finished | Jan 17 01:52:14 PM PST 24 |
| Peak memory | 208436 kb |
| Host | smart-7e6a7930-ab24-487b-bcc1-7a23d4036007 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=541871192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.541871192 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1555056300 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 123125419 ps |
| CPU time | 11.26 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:25 PM PST 24 |
| Peak memory | 205700 kb |
| Host | smart-eacd9fdf-871a-4f85-b76c-fb041d8d89d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555056300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.1555056300 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.805185338 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 604848604 ps |
| CPU time | 150.12 seconds |
| Started | Jan 17 01:50:11 PM PST 24 |
| Finished | Jan 17 01:52:41 PM PST 24 |
| Peak memory | 210856 kb |
| Host | smart-7937f0e1-b241-4a07-a8d7-fa6d712aa8b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=805185338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res et_error.805185338 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3625421126 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 165664236 ps |
| CPU time | 11.39 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:25 PM PST 24 |
| Peak memory | 211908 kb |
| Host | smart-ca61ee66-d27a-44e5-8c0b-453448d660c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3625421126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3625421126 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2968899164 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1252535913 ps |
| CPU time | 50.68 seconds |
| Started | Jan 17 01:50:06 PM PST 24 |
| Finished | Jan 17 01:50:58 PM PST 24 |
| Peak memory | 211924 kb |
| Host | smart-247fbb1c-93ad-432c-98e9-90c4d06e5a01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2968899164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2968899164 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1998773983 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 159247893035 ps |
| CPU time | 716.6 seconds |
| Started | Jan 17 01:50:06 PM PST 24 |
| Finished | Jan 17 02:02:04 PM PST 24 |
| Peak memory | 211980 kb |
| Host | smart-cbc80696-550f-4d89-ad99-6050a6236060 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1998773983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.1998773983 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2679261161 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 454043798 ps |
| CPU time | 8.37 seconds |
| Started | Jan 17 01:50:14 PM PST 24 |
| Finished | Jan 17 01:50:23 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-5e2ffc58-f332-4b3f-9d5d-9169990b2974 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2679261161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2679261161 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.698755021 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 197068978 ps |
| CPU time | 4.88 seconds |
| Started | Jan 17 01:50:14 PM PST 24 |
| Finished | Jan 17 01:50:20 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-98bc6985-e46d-419e-af69-d2cbab13656b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=698755021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.698755021 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.2468072538 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1605261048 ps |
| CPU time | 34.82 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:49 PM PST 24 |
| Peak memory | 211940 kb |
| Host | smart-19350275-4a3e-41e4-9f0c-8ec9409ba5b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2468072538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.2468072538 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3272183596 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 82438691584 ps |
| CPU time | 241 seconds |
| Started | Jan 17 01:50:10 PM PST 24 |
| Finished | Jan 17 01:54:12 PM PST 24 |
| Peak memory | 212016 kb |
| Host | smart-b059c3f6-88ab-4572-9d06-a9c35138cd47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272183596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3272183596 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1589539044 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 8762448862 ps |
| CPU time | 81.32 seconds |
| Started | Jan 17 01:50:10 PM PST 24 |
| Finished | Jan 17 01:51:32 PM PST 24 |
| Peak memory | 204948 kb |
| Host | smart-d79e0d0c-0dc0-4206-bfa9-1a8151d2b2d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1589539044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1589539044 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3505343032 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 110420340 ps |
| CPU time | 13.27 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:27 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-c7c38efe-8c0f-419d-b487-3bf1eaf6fb05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505343032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3505343032 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.1360395656 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 242795486 ps |
| CPU time | 14.79 seconds |
| Started | Jan 17 01:50:10 PM PST 24 |
| Finished | Jan 17 01:50:26 PM PST 24 |
| Peak memory | 204144 kb |
| Host | smart-bd57f5d8-e6b7-4fc3-8993-0d6206cde59d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1360395656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1360395656 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1092802378 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 36117554 ps |
| CPU time | 2.39 seconds |
| Started | Jan 17 01:50:05 PM PST 24 |
| Finished | Jan 17 01:50:10 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-6258c740-cec6-4190-a3ba-a82399e1ac32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1092802378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1092802378 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.597477220 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 8041473448 ps |
| CPU time | 33.16 seconds |
| Started | Jan 17 01:50:20 PM PST 24 |
| Finished | Jan 17 01:50:55 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-9d3bf1c4-bdeb-4512-bd0f-37699e5f4328 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=597477220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.597477220 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2407331272 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3366639487 ps |
| CPU time | 25.68 seconds |
| Started | Jan 17 01:50:16 PM PST 24 |
| Finished | Jan 17 01:50:43 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-54fe87ce-5052-486b-a6ae-0d745e20aaf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2407331272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2407331272 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2661520538 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 53768730 ps |
| CPU time | 2.18 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:17 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-d414daf9-553d-4f02-b52c-bde40d28b410 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661520538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2661520538 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.60574366 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3418157592 ps |
| CPU time | 106.37 seconds |
| Started | Jan 17 01:50:15 PM PST 24 |
| Finished | Jan 17 01:52:02 PM PST 24 |
| Peak memory | 207848 kb |
| Host | smart-2cf3eedb-c7ba-4a27-8fb7-1779b4858718 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=60574366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.60574366 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.531562181 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 314156441 ps |
| CPU time | 13.57 seconds |
| Started | Jan 17 01:50:20 PM PST 24 |
| Finished | Jan 17 01:50:35 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-b7690c70-5928-4bc9-998e-e8cbf0dda60a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=531562181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.531562181 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3215462430 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 939707659 ps |
| CPU time | 364.97 seconds |
| Started | Jan 17 01:50:14 PM PST 24 |
| Finished | Jan 17 01:56:20 PM PST 24 |
| Peak memory | 211916 kb |
| Host | smart-675e6270-14b5-49bd-b504-50545dcdfc22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3215462430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.3215462430 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.773615064 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 4651558706 ps |
| CPU time | 351.71 seconds |
| Started | Jan 17 01:50:12 PM PST 24 |
| Finished | Jan 17 01:56:04 PM PST 24 |
| Peak memory | 220204 kb |
| Host | smart-7b3f6c03-eb48-4fe6-8727-07cd6f846b42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=773615064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res et_error.773615064 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1258086590 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 203232887 ps |
| CPU time | 3.92 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:17 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-6db8f7e3-1e38-460a-ac6a-ec1e0bf9b741 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1258086590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1258086590 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.3762384396 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 567458629 ps |
| CPU time | 35.18 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:50:56 PM PST 24 |
| Peak memory | 211908 kb |
| Host | smart-1085132d-0c1e-4987-93a1-f0ba30cf82d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3762384396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3762384396 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3279479409 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 13790294497 ps |
| CPU time | 125.12 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:52:25 PM PST 24 |
| Peak memory | 206280 kb |
| Host | smart-af735493-7ccc-421f-989c-1d06986356a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3279479409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.3279479409 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2449209000 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 763515654 ps |
| CPU time | 22.38 seconds |
| Started | Jan 17 01:50:18 PM PST 24 |
| Finished | Jan 17 01:50:41 PM PST 24 |
| Peak memory | 203968 kb |
| Host | smart-f7177335-a243-4d33-a1c4-faa910d7c1d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2449209000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2449209000 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.2558268629 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 359876124 ps |
| CPU time | 8.07 seconds |
| Started | Jan 17 01:50:15 PM PST 24 |
| Finished | Jan 17 01:50:24 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-22bf7a22-7895-4dce-8214-4c968970ca34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2558268629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2558268629 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.3736476776 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 791317500 ps |
| CPU time | 21.58 seconds |
| Started | Jan 17 01:50:09 PM PST 24 |
| Finished | Jan 17 01:50:32 PM PST 24 |
| Peak memory | 211932 kb |
| Host | smart-b2657244-93e7-4f37-8ee8-a9d99367860d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3736476776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3736476776 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.3210702129 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 51180899112 ps |
| CPU time | 221.02 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:54:02 PM PST 24 |
| Peak memory | 211968 kb |
| Host | smart-f645bd2c-707c-4789-9995-cf6f308a4aaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210702129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3210702129 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1027041935 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 21079946110 ps |
| CPU time | 167.17 seconds |
| Started | Jan 17 01:50:16 PM PST 24 |
| Finished | Jan 17 01:53:04 PM PST 24 |
| Peak memory | 205136 kb |
| Host | smart-3a1f2272-6551-4351-9198-5977131597cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1027041935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1027041935 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.3266200580 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 264180634 ps |
| CPU time | 5.98 seconds |
| Started | Jan 17 01:50:18 PM PST 24 |
| Finished | Jan 17 01:50:26 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-50411578-8bf3-46aa-b6ed-46220023a32a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266200580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3266200580 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.3372873173 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 891626239 ps |
| CPU time | 20.06 seconds |
| Started | Jan 17 01:50:18 PM PST 24 |
| Finished | Jan 17 01:50:39 PM PST 24 |
| Peak memory | 204108 kb |
| Host | smart-25add68b-e499-441d-9cdc-5466e0a499d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3372873173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3372873173 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.2667708322 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 28822937 ps |
| CPU time | 2.53 seconds |
| Started | Jan 17 01:50:20 PM PST 24 |
| Finished | Jan 17 01:50:24 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-a58d5cf3-d7ac-4ee9-8cb4-7398ff66c91d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2667708322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2667708322 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1694084838 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 8572393011 ps |
| CPU time | 32.17 seconds |
| Started | Jan 17 01:50:15 PM PST 24 |
| Finished | Jan 17 01:50:48 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-f2a4dc33-15d0-42a5-a22d-f20a12716900 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694084838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1694084838 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2697446444 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4689307339 ps |
| CPU time | 34.86 seconds |
| Started | Jan 17 01:50:10 PM PST 24 |
| Finished | Jan 17 01:50:45 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-dfad8b3a-d407-43b6-964d-49fdb0ab8249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2697446444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2697446444 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3079392410 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 47064482 ps |
| CPU time | 2.33 seconds |
| Started | Jan 17 01:50:17 PM PST 24 |
| Finished | Jan 17 01:50:21 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-e376bdad-c7ac-4e70-aa47-c9776ed7a682 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079392410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3079392410 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3259377966 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2419563114 ps |
| CPU time | 98.13 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:51:58 PM PST 24 |
| Peak memory | 207208 kb |
| Host | smart-e494dbd7-621c-4ecb-a15a-c37b6d9a1cbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3259377966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3259377966 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1284502663 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 6909347938 ps |
| CPU time | 161.44 seconds |
| Started | Jan 17 01:50:15 PM PST 24 |
| Finished | Jan 17 01:52:57 PM PST 24 |
| Peak memory | 209660 kb |
| Host | smart-d2355e92-981b-4852-8530-718259ebc6df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1284502663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1284502663 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.408448480 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 596982625 ps |
| CPU time | 213.29 seconds |
| Started | Jan 17 01:50:18 PM PST 24 |
| Finished | Jan 17 01:53:52 PM PST 24 |
| Peak memory | 208740 kb |
| Host | smart-a7131636-f87a-4062-ad03-7b5ae3141609 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=408448480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand _reset.408448480 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2185496649 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 363690939 ps |
| CPU time | 101.57 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:52:02 PM PST 24 |
| Peak memory | 209596 kb |
| Host | smart-5ad7c1a0-660c-4952-bf09-5d854f6f023e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2185496649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.2185496649 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2597858895 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 58045896 ps |
| CPU time | 9.92 seconds |
| Started | Jan 17 01:50:16 PM PST 24 |
| Finished | Jan 17 01:50:26 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-a5649494-88b9-460d-88a3-380c59e9878d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2597858895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2597858895 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.88780543 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 314257350 ps |
| CPU time | 37.42 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:50:59 PM PST 24 |
| Peak memory | 211936 kb |
| Host | smart-f386ea08-57a9-4f74-96f2-83c76244cdfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=88780543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.88780543 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.162503211 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 85007233 ps |
| CPU time | 2.24 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:50:23 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-ad3a831b-b180-492b-af7b-790349d44247 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=162503211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.162503211 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.689855785 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 42490937 ps |
| CPU time | 3.04 seconds |
| Started | Jan 17 01:50:20 PM PST 24 |
| Finished | Jan 17 01:50:25 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-9fea84f8-c49c-4ca0-b508-decb8cdd204e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=689855785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.689855785 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.1431265358 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 197908850 ps |
| CPU time | 20.22 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:35 PM PST 24 |
| Peak memory | 211952 kb |
| Host | smart-b7ad9ced-60fa-40fa-a290-ce94aba312f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1431265358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1431265358 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.3473340151 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 42756786286 ps |
| CPU time | 65.57 seconds |
| Started | Jan 17 01:50:18 PM PST 24 |
| Finished | Jan 17 01:51:25 PM PST 24 |
| Peak memory | 211988 kb |
| Host | smart-d8630d81-1baa-4ced-a25c-e5f952f95c4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473340151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3473340151 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3220708975 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 41676354028 ps |
| CPU time | 257.7 seconds |
| Started | Jan 17 01:50:17 PM PST 24 |
| Finished | Jan 17 01:54:36 PM PST 24 |
| Peak memory | 204936 kb |
| Host | smart-48db2cc3-5f89-45c8-94d4-f0e2ad84fc1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3220708975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3220708975 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3648997744 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 142147430 ps |
| CPU time | 17.14 seconds |
| Started | Jan 17 01:50:13 PM PST 24 |
| Finished | Jan 17 01:50:31 PM PST 24 |
| Peak memory | 204784 kb |
| Host | smart-94e50e0b-f30c-417f-aadf-7a54fa532e1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648997744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3648997744 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.1965384146 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 968732370 ps |
| CPU time | 9.14 seconds |
| Started | Jan 17 01:50:21 PM PST 24 |
| Finished | Jan 17 01:50:35 PM PST 24 |
| Peak memory | 203924 kb |
| Host | smart-1601fa0b-20d1-413c-91b7-9829b3c4bcdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1965384146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1965384146 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.3228330971 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 201033574 ps |
| CPU time | 2.92 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:50:23 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-581ba9f6-5cb0-4551-9aaa-068f0f542970 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3228330971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3228330971 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1267001972 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 5368411099 ps |
| CPU time | 31.83 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:50:52 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-124ac0e6-9705-4663-8521-ad38fae3a148 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267001972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1267001972 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3068662434 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 12083338828 ps |
| CPU time | 36.99 seconds |
| Started | Jan 17 01:50:18 PM PST 24 |
| Finished | Jan 17 01:50:57 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-fb6bafb0-4a3f-4cf9-8124-50d27c2b7a4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3068662434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3068662434 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.4006819502 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 29631989 ps |
| CPU time | 2.09 seconds |
| Started | Jan 17 01:50:18 PM PST 24 |
| Finished | Jan 17 01:50:21 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-c604e472-19b1-4a25-b9ce-aff1c4e9b3af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006819502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.4006819502 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.3618452675 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1642175541 ps |
| CPU time | 47.39 seconds |
| Started | Jan 17 01:50:21 PM PST 24 |
| Finished | Jan 17 01:51:12 PM PST 24 |
| Peak memory | 205696 kb |
| Host | smart-c3652129-1fa6-4f43-b034-3b44d13cce98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3618452675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3618452675 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1748701940 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 456135101 ps |
| CPU time | 46.61 seconds |
| Started | Jan 17 01:50:21 PM PST 24 |
| Finished | Jan 17 01:51:11 PM PST 24 |
| Peak memory | 204900 kb |
| Host | smart-cbaa39ec-3c36-414f-92b4-a21696e1c288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1748701940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1748701940 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.708051287 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 651544915 ps |
| CPU time | 321.75 seconds |
| Started | Jan 17 01:50:21 PM PST 24 |
| Finished | Jan 17 01:55:48 PM PST 24 |
| Peak memory | 211932 kb |
| Host | smart-0f18edee-1555-4134-bf8b-a27ef27e1405 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=708051287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand _reset.708051287 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3919652501 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1864791260 ps |
| CPU time | 291.45 seconds |
| Started | Jan 17 01:50:21 PM PST 24 |
| Finished | Jan 17 01:55:17 PM PST 24 |
| Peak memory | 211492 kb |
| Host | smart-2815fc4f-fa4d-442c-8b1e-d29c8ce95e7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3919652501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.3919652501 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3987769564 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 475448000 ps |
| CPU time | 17.61 seconds |
| Started | Jan 17 01:50:20 PM PST 24 |
| Finished | Jan 17 01:50:41 PM PST 24 |
| Peak memory | 205096 kb |
| Host | smart-52ba4abc-456e-4997-8a5c-40fd7e1f0a32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3987769564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3987769564 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.772608475 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 61459381447 ps |
| CPU time | 454.72 seconds |
| Started | Jan 17 01:50:31 PM PST 24 |
| Finished | Jan 17 01:58:07 PM PST 24 |
| Peak memory | 206132 kb |
| Host | smart-a58c3f80-f51c-480c-8744-f71a9179760a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=772608475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo w_rsp.772608475 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3041797987 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 95096774 ps |
| CPU time | 4.13 seconds |
| Started | Jan 17 01:50:26 PM PST 24 |
| Finished | Jan 17 01:50:31 PM PST 24 |
| Peak memory | 203904 kb |
| Host | smart-5818748f-eb86-4a2b-bb4b-3afd9f69d8bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3041797987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3041797987 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.3463513445 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 616793116 ps |
| CPU time | 11.12 seconds |
| Started | Jan 17 01:50:28 PM PST 24 |
| Finished | Jan 17 01:50:40 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-fd886160-1df9-44b4-b029-e540b5ca0ad9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3463513445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3463513445 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.3987513314 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 411536496 ps |
| CPU time | 15.44 seconds |
| Started | Jan 17 01:50:29 PM PST 24 |
| Finished | Jan 17 01:50:45 PM PST 24 |
| Peak memory | 211928 kb |
| Host | smart-4e9a31f1-d206-43bc-8222-65f08a8e8f7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3987513314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3987513314 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.2321596077 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 186111228474 ps |
| CPU time | 231.03 seconds |
| Started | Jan 17 01:50:30 PM PST 24 |
| Finished | Jan 17 01:54:22 PM PST 24 |
| Peak memory | 211996 kb |
| Host | smart-2d4909de-77c7-488e-b784-cbf616ac23cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321596077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2321596077 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.912220781 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 14525062019 ps |
| CPU time | 58.02 seconds |
| Started | Jan 17 01:50:26 PM PST 24 |
| Finished | Jan 17 01:51:25 PM PST 24 |
| Peak memory | 211972 kb |
| Host | smart-dc563f00-cd5b-4887-8c54-556a24cb5628 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=912220781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.912220781 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.543569652 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 182316687 ps |
| CPU time | 22.22 seconds |
| Started | Jan 17 01:50:36 PM PST 24 |
| Finished | Jan 17 01:51:04 PM PST 24 |
| Peak memory | 211932 kb |
| Host | smart-5bd08da2-b1e6-40a8-87c9-4268e4d952af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543569652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.543569652 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.3069257039 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 771511268 ps |
| CPU time | 14.14 seconds |
| Started | Jan 17 01:50:28 PM PST 24 |
| Finished | Jan 17 01:50:43 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-86baff2a-9aca-4567-a4d5-8767e2b4d132 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3069257039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3069257039 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.305071030 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 40818119 ps |
| CPU time | 2.45 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:50:24 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-001e2e17-8ba4-48e4-bbbd-807cc424da76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=305071030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.305071030 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.2850817757 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 8104421113 ps |
| CPU time | 33.54 seconds |
| Started | Jan 17 01:50:28 PM PST 24 |
| Finished | Jan 17 01:51:03 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-a56fdb72-95b5-4bab-97ea-183b9b9b0ce0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850817757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2850817757 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2292158891 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 12370929454 ps |
| CPU time | 31.25 seconds |
| Started | Jan 17 01:50:36 PM PST 24 |
| Finished | Jan 17 01:51:14 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-edb8fb25-107a-4c51-8e1c-9a5b2a592440 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2292158891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2292158891 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.1975163082 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 23674886 ps |
| CPU time | 1.84 seconds |
| Started | Jan 17 01:50:19 PM PST 24 |
| Finished | Jan 17 01:50:24 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-e996007c-d066-4550-b171-7cdcf77cd9ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975163082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.1975163082 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1383691841 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1295295750 ps |
| CPU time | 140.28 seconds |
| Started | Jan 17 01:50:27 PM PST 24 |
| Finished | Jan 17 01:52:48 PM PST 24 |
| Peak memory | 208048 kb |
| Host | smart-bc6b605d-9b49-48a1-97d8-68cda92e7cf6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1383691841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1383691841 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3456324212 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1532473204 ps |
| CPU time | 118.4 seconds |
| Started | Jan 17 01:50:26 PM PST 24 |
| Finished | Jan 17 01:52:26 PM PST 24 |
| Peak memory | 205316 kb |
| Host | smart-ee1a3e2e-23ec-445b-9c75-277e676623fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3456324212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3456324212 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.2955266870 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 398868367 ps |
| CPU time | 139.03 seconds |
| Started | Jan 17 01:50:26 PM PST 24 |
| Finished | Jan 17 01:52:46 PM PST 24 |
| Peak memory | 211948 kb |
| Host | smart-cbcfbc82-f006-480c-8a77-4e15390aef88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2955266870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.2955266870 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3860892020 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 700960625 ps |
| CPU time | 168.92 seconds |
| Started | Jan 17 01:50:36 PM PST 24 |
| Finished | Jan 17 01:53:32 PM PST 24 |
| Peak memory | 211820 kb |
| Host | smart-8af42eed-7a79-436f-ad03-12970df6c142 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3860892020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.3860892020 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1295345234 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 137443493 ps |
| CPU time | 6.76 seconds |
| Started | Jan 17 01:50:31 PM PST 24 |
| Finished | Jan 17 01:50:39 PM PST 24 |
| Peak memory | 211896 kb |
| Host | smart-fb8788ec-2043-4696-825d-30a25adac6d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1295345234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1295345234 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.1704496178 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 70107791 ps |
| CPU time | 3.17 seconds |
| Started | Jan 17 01:50:36 PM PST 24 |
| Finished | Jan 17 01:50:46 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-b923e43e-16e7-4290-96d0-aa3c9dc71173 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1704496178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1704496178 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3276664290 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 35459484549 ps |
| CPU time | 230.12 seconds |
| Started | Jan 17 01:50:30 PM PST 24 |
| Finished | Jan 17 01:54:22 PM PST 24 |
| Peak memory | 211952 kb |
| Host | smart-fb29f851-4418-43b5-9a3e-8b264b454fa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3276664290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3276664290 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.213564503 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 594600429 ps |
| CPU time | 18.79 seconds |
| Started | Jan 17 01:50:38 PM PST 24 |
| Finished | Jan 17 01:51:02 PM PST 24 |
| Peak memory | 203928 kb |
| Host | smart-b1b8e265-844f-4c8f-9308-3773d9564ed2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=213564503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.213564503 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.1578403741 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 172578565 ps |
| CPU time | 19.26 seconds |
| Started | Jan 17 01:50:37 PM PST 24 |
| Finished | Jan 17 01:51:02 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-f9dd9696-cf4a-4b07-bc5a-563f4de8f2ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1578403741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1578403741 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.852092001 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 26630291 ps |
| CPU time | 3.63 seconds |
| Started | Jan 17 01:50:37 PM PST 24 |
| Finished | Jan 17 01:50:46 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-7b4c17ec-231b-41a8-8fcf-cb40467d572b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=852092001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.852092001 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.135555640 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 43847696545 ps |
| CPU time | 73.59 seconds |
| Started | Jan 17 01:50:28 PM PST 24 |
| Finished | Jan 17 01:51:43 PM PST 24 |
| Peak memory | 212016 kb |
| Host | smart-4e861c00-d985-4cef-9795-3bd13080021e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=135555640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.135555640 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3176400622 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9612057707 ps |
| CPU time | 85.02 seconds |
| Started | Jan 17 01:50:26 PM PST 24 |
| Finished | Jan 17 01:51:53 PM PST 24 |
| Peak memory | 211984 kb |
| Host | smart-b048b925-6ad8-4a90-adab-990e967dd948 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3176400622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3176400622 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.110170754 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 173231363 ps |
| CPU time | 12.28 seconds |
| Started | Jan 17 01:50:27 PM PST 24 |
| Finished | Jan 17 01:50:40 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-6be09d2d-d4fa-44f7-a421-a17f55f2953f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110170754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.110170754 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.808746613 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1092095395 ps |
| CPU time | 25.23 seconds |
| Started | Jan 17 01:50:42 PM PST 24 |
| Finished | Jan 17 01:51:09 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-7dc54eb5-f567-436b-a1c0-d811083121f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=808746613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.808746613 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.1641287871 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 117786892 ps |
| CPU time | 2.7 seconds |
| Started | Jan 17 01:50:31 PM PST 24 |
| Finished | Jan 17 01:50:35 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-49d315e8-16be-40ad-ae7c-4ec8242a0e9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1641287871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1641287871 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1658692080 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 9744709896 ps |
| CPU time | 37.58 seconds |
| Started | Jan 17 01:50:27 PM PST 24 |
| Finished | Jan 17 01:51:05 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-5db97419-4b31-4c13-b99f-69923ffd0708 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658692080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1658692080 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3164177051 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4103474838 ps |
| CPU time | 32.85 seconds |
| Started | Jan 17 01:50:37 PM PST 24 |
| Finished | Jan 17 01:51:16 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-fbc1e6b5-7666-4e28-ad9c-1eab6d804f25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3164177051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3164177051 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1060096414 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 52034761 ps |
| CPU time | 2.31 seconds |
| Started | Jan 17 01:50:32 PM PST 24 |
| Finished | Jan 17 01:50:37 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-9601838b-5b9a-4b8e-8f04-792ae8367e37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060096414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1060096414 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.2759939290 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 9196838245 ps |
| CPU time | 215.7 seconds |
| Started | Jan 17 01:50:35 PM PST 24 |
| Finished | Jan 17 01:54:17 PM PST 24 |
| Peak memory | 210592 kb |
| Host | smart-445cb831-9e50-4b7b-9de0-b6c2c0a544f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2759939290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2759939290 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.4282439273 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 505962721 ps |
| CPU time | 39.52 seconds |
| Started | Jan 17 01:50:40 PM PST 24 |
| Finished | Jan 17 01:51:22 PM PST 24 |
| Peak memory | 204996 kb |
| Host | smart-abc1c6b1-acb0-4bf9-802f-34cdf1f53d8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4282439273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.4282439273 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3120204895 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 656634421 ps |
| CPU time | 94.2 seconds |
| Started | Jan 17 01:50:37 PM PST 24 |
| Finished | Jan 17 01:52:17 PM PST 24 |
| Peak memory | 211952 kb |
| Host | smart-4b64d6cc-e822-4f2b-bc7d-11d45691298a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3120204895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.3120204895 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.32032965 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 30710665 ps |
| CPU time | 4.58 seconds |
| Started | Jan 17 01:50:34 PM PST 24 |
| Finished | Jan 17 01:50:40 PM PST 24 |
| Peak memory | 211880 kb |
| Host | smart-b031e977-cbd7-4b7e-a0cb-38598be94e23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=32032965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.32032965 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.599985519 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 702241077 ps |
| CPU time | 18.76 seconds |
| Started | Jan 17 01:50:36 PM PST 24 |
| Finished | Jan 17 01:51:02 PM PST 24 |
| Peak memory | 204440 kb |
| Host | smart-b4502baf-de74-4b70-8439-b155dae30a49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=599985519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.599985519 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.603759559 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 576393113 ps |
| CPU time | 22.53 seconds |
| Started | Jan 17 01:51:08 PM PST 24 |
| Finished | Jan 17 01:51:31 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-e86e1a7e-87aa-4aae-a295-dbb3ef08147a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=603759559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.603759559 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.362710860 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 41587571 ps |
| CPU time | 3.21 seconds |
| Started | Jan 17 01:50:58 PM PST 24 |
| Finished | Jan 17 01:51:03 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-e43cca5f-607a-44d1-8394-ec893c1a5776 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=362710860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.362710860 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.313504409 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 736659491 ps |
| CPU time | 23.8 seconds |
| Started | Jan 17 01:50:38 PM PST 24 |
| Finished | Jan 17 01:51:07 PM PST 24 |
| Peak memory | 204804 kb |
| Host | smart-e36b95d1-1380-4542-8442-c6a94f1a90e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=313504409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.313504409 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.3205043435 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 27182892227 ps |
| CPU time | 89.27 seconds |
| Started | Jan 17 01:50:40 PM PST 24 |
| Finished | Jan 17 01:52:12 PM PST 24 |
| Peak memory | 204992 kb |
| Host | smart-7da8251c-fe37-4ba6-9363-e968891449fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205043435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3205043435 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.76211662 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 5380385676 ps |
| CPU time | 27.62 seconds |
| Started | Jan 17 01:50:35 PM PST 24 |
| Finished | Jan 17 01:51:03 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-e7ca652b-82f3-4f59-8b99-035ed0282afd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=76211662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.76211662 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.1262329470 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 175302431 ps |
| CPU time | 11.33 seconds |
| Started | Jan 17 01:50:37 PM PST 24 |
| Finished | Jan 17 01:50:54 PM PST 24 |
| Peak memory | 211888 kb |
| Host | smart-baf79f1d-5176-4f81-93fc-6426e09e4ff9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262329470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.1262329470 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1394035105 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 125476777 ps |
| CPU time | 8.19 seconds |
| Started | Jan 17 01:50:35 PM PST 24 |
| Finished | Jan 17 01:50:50 PM PST 24 |
| Peak memory | 203980 kb |
| Host | smart-2262638a-e525-4998-b8db-1b2db851123b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1394035105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1394035105 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.867806628 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 68416810 ps |
| CPU time | 2.09 seconds |
| Started | Jan 17 01:50:36 PM PST 24 |
| Finished | Jan 17 01:50:44 PM PST 24 |
| Peak memory | 203948 kb |
| Host | smart-883f60c7-9523-4068-bb70-1fbf46a2b7fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=867806628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.867806628 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1708169015 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 18785524652 ps |
| CPU time | 37.89 seconds |
| Started | Jan 17 01:50:37 PM PST 24 |
| Finished | Jan 17 01:51:21 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-bd67ff48-e4af-43f0-814e-f34b7f47fa63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708169015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1708169015 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.4178605051 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 3922220225 ps |
| CPU time | 28.89 seconds |
| Started | Jan 17 01:50:38 PM PST 24 |
| Finished | Jan 17 01:51:12 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-c4f61d0c-341a-4c8a-b337-c2fa03f4dccb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4178605051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4178605051 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3088686544 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 25137653 ps |
| CPU time | 2.09 seconds |
| Started | Jan 17 01:50:37 PM PST 24 |
| Finished | Jan 17 01:50:45 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-ed8efa40-df7f-4832-ad2d-84b34c6a28ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088686544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3088686544 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.1308981806 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1700003167 ps |
| CPU time | 167.36 seconds |
| Started | Jan 17 01:50:56 PM PST 24 |
| Finished | Jan 17 01:53:46 PM PST 24 |
| Peak memory | 207176 kb |
| Host | smart-073dcc01-7fa2-4106-aa88-273b24a8bdff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1308981806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1308981806 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2689691759 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1379812537 ps |
| CPU time | 113.92 seconds |
| Started | Jan 17 01:51:01 PM PST 24 |
| Finished | Jan 17 01:53:02 PM PST 24 |
| Peak memory | 211936 kb |
| Host | smart-c3a301f3-21c0-4818-84df-0102ef958366 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2689691759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2689691759 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3151526608 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4079051395 ps |
| CPU time | 290.95 seconds |
| Started | Jan 17 01:50:54 PM PST 24 |
| Finished | Jan 17 01:55:48 PM PST 24 |
| Peak memory | 210736 kb |
| Host | smart-8599b203-5388-493d-8aaa-6bfada6cb5ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3151526608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.3151526608 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.237731171 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 549943040 ps |
| CPU time | 172.35 seconds |
| Started | Jan 17 01:50:55 PM PST 24 |
| Finished | Jan 17 01:53:50 PM PST 24 |
| Peak memory | 211044 kb |
| Host | smart-2e6ccaa8-2b61-48c9-82b6-cb442daa12bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=237731171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_res et_error.237731171 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.1708556146 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 220612140 ps |
| CPU time | 9.23 seconds |
| Started | Jan 17 01:50:55 PM PST 24 |
| Finished | Jan 17 01:51:06 PM PST 24 |
| Peak memory | 211912 kb |
| Host | smart-d3d138c0-0d19-4b52-b244-2a330bf117b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1708556146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1708556146 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.826655660 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 281506778 ps |
| CPU time | 11.98 seconds |
| Started | Jan 17 01:51:13 PM PST 24 |
| Finished | Jan 17 01:51:26 PM PST 24 |
| Peak memory | 205380 kb |
| Host | smart-e91e4ec0-580d-4110-b3e4-a7bbebeb363f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=826655660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.826655660 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.962872491 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 85244036709 ps |
| CPU time | 514.47 seconds |
| Started | Jan 17 01:50:54 PM PST 24 |
| Finished | Jan 17 01:59:32 PM PST 24 |
| Peak memory | 207296 kb |
| Host | smart-d450a61e-24ee-44ff-a3e7-032993f9bc7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=962872491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slo w_rsp.962872491 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2756290669 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 21237099 ps |
| CPU time | 3.45 seconds |
| Started | Jan 17 01:51:03 PM PST 24 |
| Finished | Jan 17 01:51:11 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-420223b3-8d4e-4749-a4f1-92b629fc4f0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2756290669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2756290669 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.2050120859 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 173546467 ps |
| CPU time | 9.96 seconds |
| Started | Jan 17 01:51:02 PM PST 24 |
| Finished | Jan 17 01:51:18 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-6eceb970-691b-47bd-9670-8520d32c93d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2050120859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2050120859 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.3859765825 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 92146927 ps |
| CPU time | 7.56 seconds |
| Started | Jan 17 01:50:57 PM PST 24 |
| Finished | Jan 17 01:51:07 PM PST 24 |
| Peak memory | 211964 kb |
| Host | smart-f023d549-57be-44d2-927e-9567b54cf4c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3859765825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3859765825 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.705252237 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 66347029876 ps |
| CPU time | 118.02 seconds |
| Started | Jan 17 01:50:48 PM PST 24 |
| Finished | Jan 17 01:52:46 PM PST 24 |
| Peak memory | 204940 kb |
| Host | smart-1f6c5d5b-8dd3-46c2-a885-9b2040491c46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=705252237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.705252237 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3125370883 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 50334843167 ps |
| CPU time | 203.59 seconds |
| Started | Jan 17 01:50:58 PM PST 24 |
| Finished | Jan 17 01:54:24 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-2401d4db-5135-409e-b4a6-b6bfd03c2289 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3125370883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3125370883 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1118327934 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 73012212 ps |
| CPU time | 6.06 seconds |
| Started | Jan 17 01:50:56 PM PST 24 |
| Finished | Jan 17 01:51:05 PM PST 24 |
| Peak memory | 204600 kb |
| Host | smart-1927a504-1e85-42e0-a055-3bd196b6a610 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118327934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1118327934 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.3035366244 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 312712418 ps |
| CPU time | 12.17 seconds |
| Started | Jan 17 01:51:09 PM PST 24 |
| Finished | Jan 17 01:51:21 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-a675de0b-264e-4f6c-9a96-9819f6078415 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3035366244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3035366244 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.3726355895 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 138857687 ps |
| CPU time | 3.5 seconds |
| Started | Jan 17 01:50:52 PM PST 24 |
| Finished | Jan 17 01:50:56 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-5c9e4878-e57c-478c-b3ca-9a302fe54f2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3726355895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3726355895 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1437635657 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 11273917843 ps |
| CPU time | 30.05 seconds |
| Started | Jan 17 01:50:54 PM PST 24 |
| Finished | Jan 17 01:51:25 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-c273851f-4cc5-4da7-9d05-a84bc1d0ca72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437635657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1437635657 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.2794715700 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 11126748411 ps |
| CPU time | 37.97 seconds |
| Started | Jan 17 01:50:50 PM PST 24 |
| Finished | Jan 17 01:51:29 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-f2888bb8-bcc3-4721-94eb-88564db1dbcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2794715700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2794715700 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.255944948 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 79495379 ps |
| CPU time | 2.22 seconds |
| Started | Jan 17 01:50:58 PM PST 24 |
| Finished | Jan 17 01:51:03 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-488f14c0-d470-42fe-9415-99c82c800931 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255944948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.255944948 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1267834791 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1568727339 ps |
| CPU time | 77.48 seconds |
| Started | Jan 17 01:51:06 PM PST 24 |
| Finished | Jan 17 01:52:25 PM PST 24 |
| Peak memory | 207276 kb |
| Host | smart-a66f0a92-9b26-4414-954a-d3788bcb368c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1267834791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1267834791 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3426902227 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 5884977084 ps |
| CPU time | 134.23 seconds |
| Started | Jan 17 01:50:58 PM PST 24 |
| Finished | Jan 17 01:53:14 PM PST 24 |
| Peak memory | 207312 kb |
| Host | smart-0f9816fb-993f-455b-ade0-7fd001a48e8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3426902227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3426902227 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.826812596 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 12059902059 ps |
| CPU time | 435.5 seconds |
| Started | Jan 17 01:50:57 PM PST 24 |
| Finished | Jan 17 01:58:15 PM PST 24 |
| Peak memory | 211864 kb |
| Host | smart-660e2fd4-a2af-461c-bad0-42bd8decdaa3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=826812596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand _reset.826812596 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3960541221 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 239410284 ps |
| CPU time | 84.39 seconds |
| Started | Jan 17 01:50:54 PM PST 24 |
| Finished | Jan 17 01:52:21 PM PST 24 |
| Peak memory | 209016 kb |
| Host | smart-78dc608c-fa1e-4749-b29e-5a805398d7a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3960541221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.3960541221 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3510308643 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 889579852 ps |
| CPU time | 19.95 seconds |
| Started | Jan 17 01:51:04 PM PST 24 |
| Finished | Jan 17 01:51:28 PM PST 24 |
| Peak memory | 211904 kb |
| Host | smart-093cad99-0e4b-46cf-a78d-80fceb7ae526 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3510308643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3510308643 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3347421961 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1776220533 ps |
| CPU time | 39.64 seconds |
| Started | Jan 17 01:49:35 PM PST 24 |
| Finished | Jan 17 01:50:18 PM PST 24 |
| Peak memory | 212008 kb |
| Host | smart-bc4cf185-c79f-4e6d-bb80-153601c26b6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3347421961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3347421961 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3062516678 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 16668883301 ps |
| CPU time | 156.77 seconds |
| Started | Jan 17 01:49:27 PM PST 24 |
| Finished | Jan 17 01:52:05 PM PST 24 |
| Peak memory | 211936 kb |
| Host | smart-a230e7c1-72b5-41ab-9eb3-b6c9f6e18147 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3062516678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.3062516678 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3941686121 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 553478097 ps |
| CPU time | 12.63 seconds |
| Started | Jan 17 01:49:28 PM PST 24 |
| Finished | Jan 17 01:49:42 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-798354e3-e0de-4b07-8b39-968b49db9b62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3941686121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3941686121 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.694467564 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 338267640 ps |
| CPU time | 5.92 seconds |
| Started | Jan 17 01:49:37 PM PST 24 |
| Finished | Jan 17 01:49:45 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-b45e5052-c5af-437f-8806-b7fca1f483c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=694467564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.694467564 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.827002426 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 76319078 ps |
| CPU time | 6.49 seconds |
| Started | Jan 17 01:49:32 PM PST 24 |
| Finished | Jan 17 01:49:41 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-7999b7a9-9298-484f-ac5e-397a1d14fb00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=827002426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.827002426 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.4188113363 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 12237876496 ps |
| CPU time | 75.29 seconds |
| Started | Jan 17 01:49:29 PM PST 24 |
| Finished | Jan 17 01:50:45 PM PST 24 |
| Peak memory | 211988 kb |
| Host | smart-c86868e3-a1c1-4e95-a4ff-bdc5da3daf03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188113363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.4188113363 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1515272717 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 20774473464 ps |
| CPU time | 151.94 seconds |
| Started | Jan 17 01:49:32 PM PST 24 |
| Finished | Jan 17 01:52:08 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-a377a9a8-1406-4698-9007-1c83a4c7e80d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1515272717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1515272717 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.4102684046 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 292770174 ps |
| CPU time | 9.6 seconds |
| Started | Jan 17 01:49:31 PM PST 24 |
| Finished | Jan 17 01:49:41 PM PST 24 |
| Peak memory | 204844 kb |
| Host | smart-6d24a882-b4f9-4026-a0a3-fb79a15b6608 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102684046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4102684046 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.1514939745 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1057575722 ps |
| CPU time | 5.12 seconds |
| Started | Jan 17 01:49:30 PM PST 24 |
| Finished | Jan 17 01:49:36 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-59b0c39f-4bc6-46bb-9ec2-9c5d37cd769e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1514939745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1514939745 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.1795216719 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 43905955 ps |
| CPU time | 2.58 seconds |
| Started | Jan 17 01:49:16 PM PST 24 |
| Finished | Jan 17 01:49:19 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-403bee24-fb30-472c-a5fb-b8bb574f5a00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1795216719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1795216719 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.836259095 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 5789262425 ps |
| CPU time | 30.03 seconds |
| Started | Jan 17 01:49:14 PM PST 24 |
| Finished | Jan 17 01:49:46 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-f98af38e-7eb3-46b4-a074-a0f2e3717862 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=836259095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.836259095 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.276559818 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4228089543 ps |
| CPU time | 25.31 seconds |
| Started | Jan 17 01:49:34 PM PST 24 |
| Finished | Jan 17 01:50:03 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-5865b054-498c-456c-8314-fd40475e433e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=276559818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.276559818 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.4171842247 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 28192346 ps |
| CPU time | 2.23 seconds |
| Started | Jan 17 01:49:16 PM PST 24 |
| Finished | Jan 17 01:49:19 PM PST 24 |
| Peak memory | 202444 kb |
| Host | smart-9f5c60c2-c832-4a29-818e-f31398eb5bb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171842247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.4171842247 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.1749753048 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 6959065660 ps |
| CPU time | 242.27 seconds |
| Started | Jan 17 01:49:38 PM PST 24 |
| Finished | Jan 17 01:53:42 PM PST 24 |
| Peak memory | 207628 kb |
| Host | smart-85c6fd24-568b-41f9-a679-3836907b1118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1749753048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1749753048 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.257166645 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 5597844323 ps |
| CPU time | 109.13 seconds |
| Started | Jan 17 01:49:38 PM PST 24 |
| Finished | Jan 17 01:51:29 PM PST 24 |
| Peak memory | 206708 kb |
| Host | smart-916ab01c-48ca-432d-9899-efc817965f93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=257166645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.257166645 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3519475559 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3307367164 ps |
| CPU time | 249.02 seconds |
| Started | Jan 17 01:49:32 PM PST 24 |
| Finished | Jan 17 01:53:41 PM PST 24 |
| Peak memory | 209296 kb |
| Host | smart-5d6546b8-bae5-4443-a9e0-c79fd74cf1fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3519475559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3519475559 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.809592176 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 98846877 ps |
| CPU time | 8.7 seconds |
| Started | Jan 17 01:49:35 PM PST 24 |
| Finished | Jan 17 01:49:47 PM PST 24 |
| Peak memory | 212096 kb |
| Host | smart-da05dae7-0ce5-4b9f-910f-4a83eb612e61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=809592176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.809592176 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2362859530 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2243673654 ps |
| CPU time | 37.12 seconds |
| Started | Jan 17 01:50:57 PM PST 24 |
| Finished | Jan 17 01:51:37 PM PST 24 |
| Peak memory | 212004 kb |
| Host | smart-9cb07496-3852-408a-b7de-452c3a2f33d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2362859530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2362859530 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2357425155 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 14622175387 ps |
| CPU time | 139.45 seconds |
| Started | Jan 17 01:50:59 PM PST 24 |
| Finished | Jan 17 01:53:20 PM PST 24 |
| Peak memory | 206452 kb |
| Host | smart-16839aab-a11a-4c14-90d1-f7572cb810e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2357425155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.2357425155 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1063321141 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 97565228 ps |
| CPU time | 3.87 seconds |
| Started | Jan 17 01:51:04 PM PST 24 |
| Finished | Jan 17 01:51:12 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-94e3d93c-2c4c-499f-b3fb-83e3ad354b00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1063321141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1063321141 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.3034444464 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 384089664 ps |
| CPU time | 12.86 seconds |
| Started | Jan 17 01:50:57 PM PST 24 |
| Finished | Jan 17 01:51:13 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-56961e16-e444-4e72-afdd-8f62b4ec69ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3034444464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3034444464 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.1666141084 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 4697233801 ps |
| CPU time | 30.5 seconds |
| Started | Jan 17 01:51:03 PM PST 24 |
| Finished | Jan 17 01:51:38 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-1136cd1b-4265-40c3-baa3-f5ff43fdc8fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1666141084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1666141084 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.179842292 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 71582447789 ps |
| CPU time | 228.94 seconds |
| Started | Jan 17 01:50:58 PM PST 24 |
| Finished | Jan 17 01:54:49 PM PST 24 |
| Peak memory | 211984 kb |
| Host | smart-db75241c-614d-40ab-9105-06c2d426ce94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=179842292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.179842292 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3348121194 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 75943746228 ps |
| CPU time | 255.35 seconds |
| Started | Jan 17 01:50:57 PM PST 24 |
| Finished | Jan 17 01:55:15 PM PST 24 |
| Peak memory | 211988 kb |
| Host | smart-d19f7f51-eee1-4c73-9912-8558d396cbc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3348121194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3348121194 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.4076495480 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 3232001314 ps |
| CPU time | 33.68 seconds |
| Started | Jan 17 01:51:07 PM PST 24 |
| Finished | Jan 17 01:51:42 PM PST 24 |
| Peak memory | 204136 kb |
| Host | smart-9f5b6667-4320-49d3-b3e8-d6ddfb51169c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4076495480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.4076495480 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.3077216457 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 152289735 ps |
| CPU time | 3.2 seconds |
| Started | Jan 17 01:50:58 PM PST 24 |
| Finished | Jan 17 01:51:03 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-b40f6594-ee84-4a23-b8f3-895f51e73ce3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3077216457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3077216457 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1860679294 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 5030545644 ps |
| CPU time | 33.09 seconds |
| Started | Jan 17 01:50:59 PM PST 24 |
| Finished | Jan 17 01:51:34 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-38132fcc-6d6d-4796-b0bb-3762293468af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860679294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1860679294 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.431940832 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3244962042 ps |
| CPU time | 29.57 seconds |
| Started | Jan 17 01:50:54 PM PST 24 |
| Finished | Jan 17 01:51:25 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-f3422743-cff7-4f3d-bced-61113804a9ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=431940832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.431940832 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.521159291 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 25295993 ps |
| CPU time | 2.14 seconds |
| Started | Jan 17 01:51:07 PM PST 24 |
| Finished | Jan 17 01:51:10 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-e7580446-f7bd-4c3c-885a-91aa8882fe2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521159291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.521159291 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1333591572 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 58087968 ps |
| CPU time | 7.99 seconds |
| Started | Jan 17 01:51:02 PM PST 24 |
| Finished | Jan 17 01:51:16 PM PST 24 |
| Peak memory | 205580 kb |
| Host | smart-f1c95ff6-bbb2-4f6b-b6ad-6b6d7ee7d08c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1333591572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1333591572 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.4053823526 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1451758334 ps |
| CPU time | 87.4 seconds |
| Started | Jan 17 01:50:54 PM PST 24 |
| Finished | Jan 17 01:52:22 PM PST 24 |
| Peak memory | 211920 kb |
| Host | smart-3b01127a-02ee-442e-bb1a-b64fa935f1d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4053823526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.4053823526 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2464558677 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 45216532 ps |
| CPU time | 38.22 seconds |
| Started | Jan 17 01:51:01 PM PST 24 |
| Finished | Jan 17 01:51:46 PM PST 24 |
| Peak memory | 206996 kb |
| Host | smart-39d57679-cd62-4e36-aeee-86c08a16b156 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2464558677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.2464558677 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.4039315671 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 8740634133 ps |
| CPU time | 298.7 seconds |
| Started | Jan 17 01:51:04 PM PST 24 |
| Finished | Jan 17 01:56:07 PM PST 24 |
| Peak memory | 223420 kb |
| Host | smart-a3c92aa2-db57-4ead-b7a9-7c8db14253d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4039315671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.4039315671 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.2733906172 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 923802203 ps |
| CPU time | 14.12 seconds |
| Started | Jan 17 01:51:09 PM PST 24 |
| Finished | Jan 17 01:51:24 PM PST 24 |
| Peak memory | 204908 kb |
| Host | smart-e32f3fe0-c436-48b3-a2f7-8c9c4fef65ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2733906172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2733906172 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.1367063603 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 363041498 ps |
| CPU time | 36.31 seconds |
| Started | Jan 17 01:51:13 PM PST 24 |
| Finished | Jan 17 01:51:50 PM PST 24 |
| Peak memory | 211732 kb |
| Host | smart-070f89ea-7f09-4dc0-8c85-1498ecdb5255 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1367063603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1367063603 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2580739707 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 145901858684 ps |
| CPU time | 515.84 seconds |
| Started | Jan 17 01:51:13 PM PST 24 |
| Finished | Jan 17 01:59:50 PM PST 24 |
| Peak memory | 205872 kb |
| Host | smart-b949527e-4a32-4841-83ce-faa63a822814 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2580739707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.2580739707 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1004790177 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 579129853 ps |
| CPU time | 8.17 seconds |
| Started | Jan 17 01:51:10 PM PST 24 |
| Finished | Jan 17 01:51:19 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-e28d6413-b0a4-4dfd-b74b-08515f847636 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1004790177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1004790177 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.3567754064 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 38842981 ps |
| CPU time | 5.75 seconds |
| Started | Jan 17 01:51:03 PM PST 24 |
| Finished | Jan 17 01:51:13 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-4decdc1e-c331-480f-9bd0-e4b09393297d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3567754064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3567754064 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.2841869635 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 130360919 ps |
| CPU time | 5.09 seconds |
| Started | Jan 17 01:51:13 PM PST 24 |
| Finished | Jan 17 01:51:20 PM PST 24 |
| Peak memory | 204236 kb |
| Host | smart-bb03918a-60b2-4ee1-89aa-3d3d7fa9f2ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2841869635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2841869635 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3417014285 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 75975159031 ps |
| CPU time | 192.24 seconds |
| Started | Jan 17 01:51:07 PM PST 24 |
| Finished | Jan 17 01:54:20 PM PST 24 |
| Peak memory | 211992 kb |
| Host | smart-d84cf566-a3dc-49f0-accc-73a47fcbaf22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417014285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3417014285 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.716208799 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 11314746685 ps |
| CPU time | 86.26 seconds |
| Started | Jan 17 01:51:06 PM PST 24 |
| Finished | Jan 17 01:52:34 PM PST 24 |
| Peak memory | 204936 kb |
| Host | smart-ef07e6e4-08eb-41f0-9543-1d443def171c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=716208799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.716208799 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.132631720 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 323780608 ps |
| CPU time | 17.81 seconds |
| Started | Jan 17 01:51:08 PM PST 24 |
| Finished | Jan 17 01:51:26 PM PST 24 |
| Peak memory | 211884 kb |
| Host | smart-bad4afc5-6663-48f7-8466-764969fa05f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132631720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.132631720 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.1011768208 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 116758341 ps |
| CPU time | 7.99 seconds |
| Started | Jan 17 01:51:13 PM PST 24 |
| Finished | Jan 17 01:51:22 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-2807d67b-a03c-4339-9d33-1a154e2914f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1011768208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1011768208 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.2759844433 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 145943977 ps |
| CPU time | 3.81 seconds |
| Started | Jan 17 01:50:55 PM PST 24 |
| Finished | Jan 17 01:51:01 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-61f07158-3639-40f6-b377-e53994c2e9ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2759844433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2759844433 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3486877673 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6347756307 ps |
| CPU time | 29.1 seconds |
| Started | Jan 17 01:51:04 PM PST 24 |
| Finished | Jan 17 01:51:37 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-5b95f721-ab98-4ecb-a703-f126dfefe4d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486877673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3486877673 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.71535399 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5621300170 ps |
| CPU time | 29.7 seconds |
| Started | Jan 17 01:51:02 PM PST 24 |
| Finished | Jan 17 01:51:37 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-72246c75-94aa-41d8-b7fa-7ae547752a2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=71535399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.71535399 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3827319915 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 49926767 ps |
| CPU time | 2.54 seconds |
| Started | Jan 17 01:51:03 PM PST 24 |
| Finished | Jan 17 01:51:10 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-583cd245-ca1a-42c9-bcf1-4d811a904d8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827319915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3827319915 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.249681316 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 495997942 ps |
| CPU time | 43.28 seconds |
| Started | Jan 17 01:51:05 PM PST 24 |
| Finished | Jan 17 01:51:51 PM PST 24 |
| Peak memory | 206392 kb |
| Host | smart-7e5030bc-adf1-42ba-b679-a4ab143b969d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=249681316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.249681316 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.4018428882 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1484596323 ps |
| CPU time | 40.04 seconds |
| Started | Jan 17 01:51:02 PM PST 24 |
| Finished | Jan 17 01:51:48 PM PST 24 |
| Peak memory | 204872 kb |
| Host | smart-cc3cd6f5-5e3c-4696-8129-65222bc309a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4018428882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.4018428882 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.3524224171 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 29683323 ps |
| CPU time | 16.36 seconds |
| Started | Jan 17 01:51:01 PM PST 24 |
| Finished | Jan 17 01:51:24 PM PST 24 |
| Peak memory | 205196 kb |
| Host | smart-e0ac5a43-c5ee-41a0-9ebe-2bbf16ca71bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3524224171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.3524224171 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.3900786737 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 103070297 ps |
| CPU time | 3.93 seconds |
| Started | Jan 17 01:51:02 PM PST 24 |
| Finished | Jan 17 01:51:12 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-a751d5ea-98d9-4056-8115-8a2d46b47493 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3900786737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3900786737 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.144092040 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 6250331249 ps |
| CPU time | 42.26 seconds |
| Started | Jan 17 01:51:13 PM PST 24 |
| Finished | Jan 17 01:51:57 PM PST 24 |
| Peak memory | 211980 kb |
| Host | smart-a4494305-7528-49f1-9e23-3bd9113dcd42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=144092040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.144092040 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2830565814 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 70974300133 ps |
| CPU time | 331.98 seconds |
| Started | Jan 17 01:51:09 PM PST 24 |
| Finished | Jan 17 01:56:42 PM PST 24 |
| Peak memory | 211988 kb |
| Host | smart-e13bf420-9115-4dc2-805c-c3de7439695a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2830565814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.2830565814 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.3605218995 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 16274813 ps |
| CPU time | 1.95 seconds |
| Started | Jan 17 01:51:20 PM PST 24 |
| Finished | Jan 17 01:51:23 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-ffe9a2f7-f1ea-430d-bca3-25610a500c8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3605218995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.3605218995 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.3227372813 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 108146070 ps |
| CPU time | 12.91 seconds |
| Started | Jan 17 01:51:08 PM PST 24 |
| Finished | Jan 17 01:51:22 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-b0905e71-f052-48a2-9f7e-e15388bf7d02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3227372813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3227372813 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.2283809294 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 122484507 ps |
| CPU time | 12.52 seconds |
| Started | Jan 17 01:51:08 PM PST 24 |
| Finished | Jan 17 01:51:22 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-cb273d4e-8739-498e-87e2-98ad6dfcc985 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2283809294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2283809294 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3975015977 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 23431671760 ps |
| CPU time | 120.6 seconds |
| Started | Jan 17 01:51:16 PM PST 24 |
| Finished | Jan 17 01:53:17 PM PST 24 |
| Peak memory | 211988 kb |
| Host | smart-d87fe2cc-f536-44d3-90da-1310752e3626 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975015977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3975015977 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2026503442 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 20863346720 ps |
| CPU time | 180.53 seconds |
| Started | Jan 17 01:51:13 PM PST 24 |
| Finished | Jan 17 01:54:15 PM PST 24 |
| Peak memory | 212000 kb |
| Host | smart-5595def2-ab2b-414c-9a02-3a20dc266caf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2026503442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2026503442 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.3789140664 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 896080237 ps |
| CPU time | 25.09 seconds |
| Started | Jan 17 01:51:14 PM PST 24 |
| Finished | Jan 17 01:51:40 PM PST 24 |
| Peak memory | 204784 kb |
| Host | smart-678ad6b2-9078-4121-84bc-f8af9a5fc9d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789140664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.3789140664 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.2939479492 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 353354157 ps |
| CPU time | 20.88 seconds |
| Started | Jan 17 01:51:14 PM PST 24 |
| Finished | Jan 17 01:51:36 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-ecd7e0fc-511f-45f6-b731-1c4c67134456 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2939479492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2939479492 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.2014902696 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 511284501 ps |
| CPU time | 3.78 seconds |
| Started | Jan 17 01:51:09 PM PST 24 |
| Finished | Jan 17 01:51:14 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-c40bb630-37b8-4a21-91d0-378347d84204 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2014902696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2014902696 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2661484724 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 16834465392 ps |
| CPU time | 33.4 seconds |
| Started | Jan 17 01:51:13 PM PST 24 |
| Finished | Jan 17 01:51:47 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-acdd5fb7-3bbf-4536-b505-ae7bd859b11d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661484724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2661484724 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.794641252 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 5743986851 ps |
| CPU time | 30.68 seconds |
| Started | Jan 17 01:51:08 PM PST 24 |
| Finished | Jan 17 01:51:40 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-aa063980-69c8-40f3-aac2-58e30ff77acd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=794641252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.794641252 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2757520398 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 50125552 ps |
| CPU time | 2.57 seconds |
| Started | Jan 17 01:51:04 PM PST 24 |
| Finished | Jan 17 01:51:10 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-332d93d7-7ada-44f1-a36a-6b9ce7130652 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757520398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2757520398 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.323539089 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5386002823 ps |
| CPU time | 184.08 seconds |
| Started | Jan 17 01:51:11 PM PST 24 |
| Finished | Jan 17 01:54:16 PM PST 24 |
| Peak memory | 207440 kb |
| Host | smart-cc60e0e9-4fd2-4a5e-8d7a-81a72a64508c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=323539089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.323539089 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.1505464101 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 9805685068 ps |
| CPU time | 267.98 seconds |
| Started | Jan 17 01:51:13 PM PST 24 |
| Finished | Jan 17 01:55:43 PM PST 24 |
| Peak memory | 210396 kb |
| Host | smart-4b10ddfd-c781-4e7d-a888-ed7635968bfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1505464101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1505464101 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2509009412 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 443143126 ps |
| CPU time | 124.3 seconds |
| Started | Jan 17 01:51:12 PM PST 24 |
| Finished | Jan 17 01:53:17 PM PST 24 |
| Peak memory | 209968 kb |
| Host | smart-484806b2-50d6-46af-ab6b-bdf9fe336fa8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2509009412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.2509009412 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.733972392 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 4981540494 ps |
| CPU time | 34.04 seconds |
| Started | Jan 17 01:51:14 PM PST 24 |
| Finished | Jan 17 01:51:49 PM PST 24 |
| Peak memory | 211956 kb |
| Host | smart-e2c9cc1c-6a71-4d06-a84f-1f91e93b4e68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=733972392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.733972392 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3300768247 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 76938272 ps |
| CPU time | 11.39 seconds |
| Started | Jan 17 01:51:16 PM PST 24 |
| Finished | Jan 17 01:51:28 PM PST 24 |
| Peak memory | 205460 kb |
| Host | smart-d0be2ed2-640d-4398-b61c-70f121142785 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3300768247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3300768247 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1631862876 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 116103501284 ps |
| CPU time | 434.53 seconds |
| Started | Jan 17 01:51:20 PM PST 24 |
| Finished | Jan 17 01:58:36 PM PST 24 |
| Peak memory | 206188 kb |
| Host | smart-ddeef7fe-29d2-4269-91bf-ec42b98d6e8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1631862876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.1631862876 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1645352937 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 341204517 ps |
| CPU time | 16.73 seconds |
| Started | Jan 17 01:51:21 PM PST 24 |
| Finished | Jan 17 01:51:39 PM PST 24 |
| Peak memory | 203916 kb |
| Host | smart-548bdc47-9a46-4e90-a695-61d19dae116b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1645352937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1645352937 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.518342604 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1067294663 ps |
| CPU time | 13.64 seconds |
| Started | Jan 17 01:51:20 PM PST 24 |
| Finished | Jan 17 01:51:34 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-ac99ba8e-b254-4fe0-9eb6-a5cb886d9b16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=518342604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.518342604 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.510817629 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1091672755 ps |
| CPU time | 37.08 seconds |
| Started | Jan 17 01:51:20 PM PST 24 |
| Finished | Jan 17 01:51:58 PM PST 24 |
| Peak memory | 211984 kb |
| Host | smart-247c48cd-6a44-4ec0-9b27-422eadd8ce43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=510817629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.510817629 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.42905464 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 8680632752 ps |
| CPU time | 35.63 seconds |
| Started | Jan 17 01:51:13 PM PST 24 |
| Finished | Jan 17 01:51:50 PM PST 24 |
| Peak memory | 212000 kb |
| Host | smart-d247eed2-13be-4de9-b9fe-d81a56e4ccc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=42905464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.42905464 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1490357323 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4072862218 ps |
| CPU time | 15.52 seconds |
| Started | Jan 17 01:51:11 PM PST 24 |
| Finished | Jan 17 01:51:27 PM PST 24 |
| Peak memory | 203856 kb |
| Host | smart-44231d52-e3f0-4778-8fdb-a62d2af5214d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1490357323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1490357323 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2267884951 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 35774548 ps |
| CPU time | 2.19 seconds |
| Started | Jan 17 01:51:09 PM PST 24 |
| Finished | Jan 17 01:51:12 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-6e6c9f8e-0bb1-451b-b6fe-81d01296a5e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267884951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2267884951 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.2778382992 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3774066283 ps |
| CPU time | 23.39 seconds |
| Started | Jan 17 01:51:16 PM PST 24 |
| Finished | Jan 17 01:51:40 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-df7afa27-89d7-45f1-bd8b-9bcacc2f2404 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2778382992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2778382992 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.2879979737 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 160399361 ps |
| CPU time | 3.15 seconds |
| Started | Jan 17 01:51:09 PM PST 24 |
| Finished | Jan 17 01:51:13 PM PST 24 |
| Peak memory | 203628 kb |
| Host | smart-e085f0be-4c97-403a-b0cb-134712d152fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2879979737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2879979737 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.737048417 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 9913607977 ps |
| CPU time | 29.94 seconds |
| Started | Jan 17 01:51:20 PM PST 24 |
| Finished | Jan 17 01:51:51 PM PST 24 |
| Peak memory | 203872 kb |
| Host | smart-5026bb07-f71a-4b78-8b77-dd1e39c7cd6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=737048417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.737048417 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3611967894 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 8901908660 ps |
| CPU time | 24.29 seconds |
| Started | Jan 17 01:51:11 PM PST 24 |
| Finished | Jan 17 01:51:36 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-c3e24ce8-f9a0-4ea7-a3cb-b3aa38e42506 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3611967894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3611967894 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2804017654 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 103608638 ps |
| CPU time | 2.53 seconds |
| Started | Jan 17 01:51:14 PM PST 24 |
| Finished | Jan 17 01:51:18 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-dc64a464-c564-44f0-93cc-4e5c7f062297 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804017654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2804017654 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2914940323 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 8257898152 ps |
| CPU time | 42.07 seconds |
| Started | Jan 17 01:51:18 PM PST 24 |
| Finished | Jan 17 01:52:00 PM PST 24 |
| Peak memory | 206156 kb |
| Host | smart-a745b027-324d-46ab-9663-083a6a3e2272 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2914940323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2914940323 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2684427086 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2985850534 ps |
| CPU time | 91.6 seconds |
| Started | Jan 17 01:51:23 PM PST 24 |
| Finished | Jan 17 01:52:57 PM PST 24 |
| Peak memory | 206360 kb |
| Host | smart-883addcb-a1e8-4ef8-b516-d68c9dbb112c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2684427086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2684427086 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1577433837 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 6092109239 ps |
| CPU time | 384.8 seconds |
| Started | Jan 17 01:51:19 PM PST 24 |
| Finished | Jan 17 01:57:44 PM PST 24 |
| Peak memory | 211036 kb |
| Host | smart-db5b759e-e398-4997-8709-3105513b3048 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1577433837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.1577433837 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1688052388 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 8422441325 ps |
| CPU time | 391.79 seconds |
| Started | Jan 17 01:51:20 PM PST 24 |
| Finished | Jan 17 01:57:53 PM PST 24 |
| Peak memory | 220280 kb |
| Host | smart-5fc5868b-db78-4f87-88ba-02bd759e6472 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1688052388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.1688052388 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2499843984 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1167921161 ps |
| CPU time | 18.42 seconds |
| Started | Jan 17 01:51:24 PM PST 24 |
| Finished | Jan 17 01:51:46 PM PST 24 |
| Peak memory | 205080 kb |
| Host | smart-1d2ea368-a70d-40cc-8aac-65288e5e6cce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2499843984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2499843984 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.255932501 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 290297859 ps |
| CPU time | 19.38 seconds |
| Started | Jan 17 01:51:25 PM PST 24 |
| Finished | Jan 17 01:51:50 PM PST 24 |
| Peak memory | 205652 kb |
| Host | smart-8614832a-a775-4fb8-851f-1efc5504669d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=255932501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.255932501 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.626371545 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 56852424 ps |
| CPU time | 4.04 seconds |
| Started | Jan 17 01:51:29 PM PST 24 |
| Finished | Jan 17 01:51:36 PM PST 24 |
| Peak memory | 203844 kb |
| Host | smart-01982703-3924-42f3-8e1b-e932791a7333 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=626371545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.626371545 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2967852935 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 454445435 ps |
| CPU time | 11.78 seconds |
| Started | Jan 17 01:51:25 PM PST 24 |
| Finished | Jan 17 01:51:42 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-6557a025-4363-4735-a688-401d37809976 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2967852935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2967852935 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.537530211 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 591072731 ps |
| CPU time | 19.02 seconds |
| Started | Jan 17 01:51:25 PM PST 24 |
| Finished | Jan 17 01:51:47 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-52a00e22-a135-4c78-96b7-bfcf350cc56d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=537530211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.537530211 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2813039487 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 53630346052 ps |
| CPU time | 65.45 seconds |
| Started | Jan 17 01:51:21 PM PST 24 |
| Finished | Jan 17 01:52:27 PM PST 24 |
| Peak memory | 211992 kb |
| Host | smart-620b0bf2-566f-4807-9d75-ea010bc5ad69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813039487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2813039487 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2880199099 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 18064448704 ps |
| CPU time | 148.91 seconds |
| Started | Jan 17 01:51:19 PM PST 24 |
| Finished | Jan 17 01:53:49 PM PST 24 |
| Peak memory | 212008 kb |
| Host | smart-4ba87fe7-1c1c-4b13-a65b-fd96390a2ac8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2880199099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2880199099 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1406379578 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 204591212 ps |
| CPU time | 7.2 seconds |
| Started | Jan 17 01:51:20 PM PST 24 |
| Finished | Jan 17 01:51:27 PM PST 24 |
| Peak memory | 204488 kb |
| Host | smart-e5f9cbd7-981b-4b57-8867-496f7fa7fa10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406379578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1406379578 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.1684470584 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 100906001 ps |
| CPU time | 5.52 seconds |
| Started | Jan 17 01:51:27 PM PST 24 |
| Finished | Jan 17 01:51:37 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-c98312b7-7982-45b5-a90d-6c89e6bfd9fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1684470584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1684470584 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.4016304668 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 46231338 ps |
| CPU time | 2.38 seconds |
| Started | Jan 17 01:51:19 PM PST 24 |
| Finished | Jan 17 01:51:22 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-f1addfef-0409-45e5-9ed4-fa4049e05a21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4016304668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.4016304668 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.4126539724 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 16809441354 ps |
| CPU time | 32.87 seconds |
| Started | Jan 17 01:51:25 PM PST 24 |
| Finished | Jan 17 01:52:01 PM PST 24 |
| Peak memory | 203836 kb |
| Host | smart-7fa0e7e2-5cec-414e-8cdc-ad3cae731341 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126539724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.4126539724 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2905842194 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3864383144 ps |
| CPU time | 26.34 seconds |
| Started | Jan 17 01:51:20 PM PST 24 |
| Finished | Jan 17 01:51:47 PM PST 24 |
| Peak memory | 203844 kb |
| Host | smart-3dde5ca7-f812-413c-a0a2-c424ee13e8f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2905842194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2905842194 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.1388425126 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 24758705 ps |
| CPU time | 2.09 seconds |
| Started | Jan 17 01:51:21 PM PST 24 |
| Finished | Jan 17 01:51:23 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-08208f79-436e-4ec7-a684-d27ba3c96d1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388425126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.1388425126 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.369992078 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1069423023 ps |
| CPU time | 12.08 seconds |
| Started | Jan 17 01:51:27 PM PST 24 |
| Finished | Jan 17 01:51:44 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-df0541f7-56d9-4795-b5ca-f6c56e1786b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=369992078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.369992078 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1505951454 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 587153418 ps |
| CPU time | 205.97 seconds |
| Started | Jan 17 01:51:25 PM PST 24 |
| Finished | Jan 17 01:54:54 PM PST 24 |
| Peak memory | 208364 kb |
| Host | smart-f1e5f10e-eddd-42cd-a5ef-8d8c14594d6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1505951454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.1505951454 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2527705153 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 460520443 ps |
| CPU time | 155.99 seconds |
| Started | Jan 17 01:51:31 PM PST 24 |
| Finished | Jan 17 01:54:08 PM PST 24 |
| Peak memory | 211196 kb |
| Host | smart-1bd4f8f4-d346-4ab0-9835-1f641931984d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2527705153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.2527705153 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1083225799 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 52275133 ps |
| CPU time | 2.6 seconds |
| Started | Jan 17 01:51:26 PM PST 24 |
| Finished | Jan 17 01:51:33 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-f394b019-8299-4e71-921a-335630006e3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1083225799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1083225799 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.358669451 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 330090524 ps |
| CPU time | 21.15 seconds |
| Started | Jan 17 01:51:24 PM PST 24 |
| Finished | Jan 17 01:51:49 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-469bc04f-ab98-424e-9f35-bcb2626a3498 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=358669451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.358669451 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.174252356 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 107577177494 ps |
| CPU time | 614.88 seconds |
| Started | Jan 17 01:51:26 PM PST 24 |
| Finished | Jan 17 02:01:46 PM PST 24 |
| Peak memory | 206248 kb |
| Host | smart-514df180-f3a5-4af6-8600-3280e78170d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=174252356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.174252356 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2384843152 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 664352865 ps |
| CPU time | 23.12 seconds |
| Started | Jan 17 01:51:28 PM PST 24 |
| Finished | Jan 17 01:51:55 PM PST 24 |
| Peak memory | 204120 kb |
| Host | smart-65655bc4-fea8-4946-939e-1769eb0d6ab2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2384843152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2384843152 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.1849565816 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 76236555 ps |
| CPU time | 6.01 seconds |
| Started | Jan 17 01:51:25 PM PST 24 |
| Finished | Jan 17 01:51:34 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-8e48bf1f-4875-4556-8cf1-96671a49b3b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1849565816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1849565816 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.1295066097 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 252290246 ps |
| CPU time | 15.94 seconds |
| Started | Jan 17 01:51:28 PM PST 24 |
| Finished | Jan 17 01:51:48 PM PST 24 |
| Peak memory | 211996 kb |
| Host | smart-076f2f91-b66b-4437-962d-c789700079c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1295066097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.1295066097 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.206034733 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 23409073529 ps |
| CPU time | 101.74 seconds |
| Started | Jan 17 01:51:26 PM PST 24 |
| Finished | Jan 17 01:53:13 PM PST 24 |
| Peak memory | 211992 kb |
| Host | smart-df222481-89d3-4873-a7a1-0c69962a16b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=206034733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.206034733 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2534740236 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 9641794103 ps |
| CPU time | 105.04 seconds |
| Started | Jan 17 01:51:25 PM PST 24 |
| Finished | Jan 17 01:53:13 PM PST 24 |
| Peak memory | 212004 kb |
| Host | smart-2440e330-47d3-4290-a529-0dc84dec4f9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2534740236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2534740236 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.1457601989 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 488714681 ps |
| CPU time | 23.65 seconds |
| Started | Jan 17 01:51:26 PM PST 24 |
| Finished | Jan 17 01:51:54 PM PST 24 |
| Peak memory | 211864 kb |
| Host | smart-cc30550b-3361-411e-8430-be87ec0005bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457601989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1457601989 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.494840579 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3356786563 ps |
| CPU time | 23.41 seconds |
| Started | Jan 17 01:51:26 PM PST 24 |
| Finished | Jan 17 01:51:54 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-0acfb68a-f710-4178-b1eb-460136b2918b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=494840579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.494840579 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.3298054768 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 263540657 ps |
| CPU time | 3.54 seconds |
| Started | Jan 17 01:51:25 PM PST 24 |
| Finished | Jan 17 01:51:32 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-a7dff757-69cf-441d-bd52-52646ea0bf9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3298054768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3298054768 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.313667819 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 8565854611 ps |
| CPU time | 37.29 seconds |
| Started | Jan 17 01:51:27 PM PST 24 |
| Finished | Jan 17 01:52:09 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-b70c4344-30e9-4f3b-ba02-a3069d059df4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=313667819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.313667819 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3089229031 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 6565044671 ps |
| CPU time | 30.84 seconds |
| Started | Jan 17 01:51:31 PM PST 24 |
| Finished | Jan 17 01:52:03 PM PST 24 |
| Peak memory | 203792 kb |
| Host | smart-0dda659b-837c-4bd5-a5bb-9220625499fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3089229031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3089229031 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.477557087 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 39057573 ps |
| CPU time | 2 seconds |
| Started | Jan 17 01:51:24 PM PST 24 |
| Finished | Jan 17 01:51:30 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-37025259-b70d-4e4e-9447-fa4b1e602d3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477557087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.477557087 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.101069769 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 862735759 ps |
| CPU time | 15.04 seconds |
| Started | Jan 17 01:51:26 PM PST 24 |
| Finished | Jan 17 01:51:46 PM PST 24 |
| Peak memory | 205716 kb |
| Host | smart-7be6e425-c11e-45b5-a68e-1c10507e7c4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=101069769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.101069769 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.916196357 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 4096931570 ps |
| CPU time | 99.11 seconds |
| Started | Jan 17 01:51:46 PM PST 24 |
| Finished | Jan 17 01:53:26 PM PST 24 |
| Peak memory | 207148 kb |
| Host | smart-b3766a82-c769-4d01-a4c2-9c4f0ec3eb66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=916196357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.916196357 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.613756889 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2112248801 ps |
| CPU time | 309.09 seconds |
| Started | Jan 17 01:51:30 PM PST 24 |
| Finished | Jan 17 01:56:41 PM PST 24 |
| Peak memory | 220240 kb |
| Host | smart-832a10c3-51ff-4657-8331-32f2d30a13d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=613756889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand _reset.613756889 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3745689328 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3413763085 ps |
| CPU time | 215.12 seconds |
| Started | Jan 17 01:51:37 PM PST 24 |
| Finished | Jan 17 01:55:15 PM PST 24 |
| Peak memory | 212004 kb |
| Host | smart-27b22bfc-5879-494c-ba4f-6ba4a99f1c01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745689328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.3745689328 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.3187087981 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 154844891 ps |
| CPU time | 6.04 seconds |
| Started | Jan 17 01:51:25 PM PST 24 |
| Finished | Jan 17 01:51:34 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-08eee89d-4152-4aea-aa6c-447af12243af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3187087981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3187087981 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.4186435321 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 789410647 ps |
| CPU time | 8.61 seconds |
| Started | Jan 17 01:51:39 PM PST 24 |
| Finished | Jan 17 01:51:48 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-dad63fed-18c4-42ab-8039-9c325bb25545 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4186435321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.4186435321 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1715716515 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 47779029035 ps |
| CPU time | 250.04 seconds |
| Started | Jan 17 01:51:41 PM PST 24 |
| Finished | Jan 17 01:55:52 PM PST 24 |
| Peak memory | 206340 kb |
| Host | smart-4a38648c-8266-4970-a1ce-d34afb95a160 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1715716515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.1715716515 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2694520729 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1641300286 ps |
| CPU time | 25.41 seconds |
| Started | Jan 17 01:51:35 PM PST 24 |
| Finished | Jan 17 01:52:05 PM PST 24 |
| Peak memory | 203928 kb |
| Host | smart-f1fe5739-7939-48ee-9499-432ca816d030 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2694520729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2694520729 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.1762216283 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 722784031 ps |
| CPU time | 22.41 seconds |
| Started | Jan 17 01:51:46 PM PST 24 |
| Finished | Jan 17 01:52:09 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-a4181c57-761f-4d45-ace0-a31927238405 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1762216283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1762216283 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.2493511645 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 132572773 ps |
| CPU time | 5.35 seconds |
| Started | Jan 17 01:51:39 PM PST 24 |
| Finished | Jan 17 01:51:45 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-c533d155-b387-4a29-b7b0-5140590b1571 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2493511645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2493511645 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.3469662544 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 15213310044 ps |
| CPU time | 19.27 seconds |
| Started | Jan 17 01:51:36 PM PST 24 |
| Finished | Jan 17 01:51:59 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-b63474f2-eae5-42ec-b7a5-e851c8c76147 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469662544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3469662544 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1356148884 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 53920337823 ps |
| CPU time | 155.75 seconds |
| Started | Jan 17 01:51:49 PM PST 24 |
| Finished | Jan 17 01:54:25 PM PST 24 |
| Peak memory | 211976 kb |
| Host | smart-8d8f66f1-c215-44ab-926e-8b6ab1a9df91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1356148884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1356148884 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3816700919 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14398274 ps |
| CPU time | 2.51 seconds |
| Started | Jan 17 01:51:37 PM PST 24 |
| Finished | Jan 17 01:51:42 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-970c1a88-7750-4b4d-b99d-5c4eaa4d1b92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816700919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3816700919 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.2174933466 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 106996547 ps |
| CPU time | 7.15 seconds |
| Started | Jan 17 01:51:37 PM PST 24 |
| Finished | Jan 17 01:51:47 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-7aadd651-263a-42db-9b7b-81adac7ff69e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2174933466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2174933466 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.3029485328 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 27093165 ps |
| CPU time | 2.42 seconds |
| Started | Jan 17 01:51:46 PM PST 24 |
| Finished | Jan 17 01:51:49 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-70ff30fd-d7e5-4190-9421-8aa7c9af8055 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3029485328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3029485328 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3120897119 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 23621083647 ps |
| CPU time | 33.23 seconds |
| Started | Jan 17 01:51:37 PM PST 24 |
| Finished | Jan 17 01:52:13 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-371b4399-601e-4a57-9e78-58045a7b2e4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120897119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3120897119 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.4178263992 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4704214253 ps |
| CPU time | 27.82 seconds |
| Started | Jan 17 01:51:37 PM PST 24 |
| Finished | Jan 17 01:52:08 PM PST 24 |
| Peak memory | 203864 kb |
| Host | smart-65677572-17f5-47b5-bf37-bac9279835b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4178263992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.4178263992 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2839202237 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 34896704 ps |
| CPU time | 2.44 seconds |
| Started | Jan 17 01:51:37 PM PST 24 |
| Finished | Jan 17 01:51:42 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-472a5bd9-3882-4920-8b93-f45a7e2c5913 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839202237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2839202237 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2851751778 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4660734351 ps |
| CPU time | 155.2 seconds |
| Started | Jan 17 01:51:36 PM PST 24 |
| Finished | Jan 17 01:54:15 PM PST 24 |
| Peak memory | 207336 kb |
| Host | smart-9274e5fb-4992-44b0-a71f-900074b0c029 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2851751778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2851751778 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3910334097 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2745155483 ps |
| CPU time | 96.24 seconds |
| Started | Jan 17 01:51:40 PM PST 24 |
| Finished | Jan 17 01:53:17 PM PST 24 |
| Peak memory | 207864 kb |
| Host | smart-733648ec-f82b-4d7e-ab5d-29e4b0f10289 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3910334097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3910334097 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3200106913 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1832371895 ps |
| CPU time | 164.79 seconds |
| Started | Jan 17 01:51:46 PM PST 24 |
| Finished | Jan 17 01:54:32 PM PST 24 |
| Peak memory | 210608 kb |
| Host | smart-fe34b9dd-f87f-4246-8c8e-1e8f784a9bb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3200106913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.3200106913 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1983048378 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 18817418 ps |
| CPU time | 2.26 seconds |
| Started | Jan 17 01:51:49 PM PST 24 |
| Finished | Jan 17 01:51:51 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-f4f41b34-876c-4e98-8b30-94e5343d0e09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1983048378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1983048378 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.882017903 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 461967310 ps |
| CPU time | 16.51 seconds |
| Started | Jan 17 01:51:46 PM PST 24 |
| Finished | Jan 17 01:52:04 PM PST 24 |
| Peak memory | 204768 kb |
| Host | smart-f90807fe-2b1e-4a26-99f7-820587318147 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=882017903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.882017903 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.406187261 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 126774923446 ps |
| CPU time | 454.73 seconds |
| Started | Jan 17 01:51:42 PM PST 24 |
| Finished | Jan 17 01:59:18 PM PST 24 |
| Peak memory | 211968 kb |
| Host | smart-b7b8797c-c482-4e53-b05d-b33801c58790 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=406187261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slo w_rsp.406187261 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2492952364 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1942424005 ps |
| CPU time | 22.57 seconds |
| Started | Jan 17 01:51:46 PM PST 24 |
| Finished | Jan 17 01:52:09 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-dbf30531-98b2-4d5d-9004-02c0e9fcabcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2492952364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2492952364 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.3089898192 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 378217438 ps |
| CPU time | 14.5 seconds |
| Started | Jan 17 01:51:50 PM PST 24 |
| Finished | Jan 17 01:52:05 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-1cbe0ef4-c054-456b-b62d-abe41e042cbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3089898192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3089898192 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.2142465636 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 134441417 ps |
| CPU time | 10.24 seconds |
| Started | Jan 17 01:51:48 PM PST 24 |
| Finished | Jan 17 01:51:59 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-a14418f8-1a42-4408-a278-e6033f7fd024 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2142465636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2142465636 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2135716616 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 45214657895 ps |
| CPU time | 118.4 seconds |
| Started | Jan 17 01:51:42 PM PST 24 |
| Finished | Jan 17 01:53:41 PM PST 24 |
| Peak memory | 205272 kb |
| Host | smart-0448599d-4380-4017-a11f-543356510f35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135716616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2135716616 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.55788311 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 29545144262 ps |
| CPU time | 228.63 seconds |
| Started | Jan 17 01:51:50 PM PST 24 |
| Finished | Jan 17 01:55:40 PM PST 24 |
| Peak memory | 211952 kb |
| Host | smart-ab49a137-b439-454e-adfc-b88b965c024e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=55788311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.55788311 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2091350516 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 236672871 ps |
| CPU time | 18.57 seconds |
| Started | Jan 17 01:51:49 PM PST 24 |
| Finished | Jan 17 01:52:08 PM PST 24 |
| Peak memory | 211932 kb |
| Host | smart-0dae5004-0a17-43f2-afa7-624af1859678 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091350516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2091350516 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.360476804 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 81791673 ps |
| CPU time | 2.11 seconds |
| Started | Jan 17 01:51:49 PM PST 24 |
| Finished | Jan 17 01:51:52 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-18458fe2-c85a-4598-8488-bf41645d3b1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=360476804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.360476804 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.466013975 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 170935549 ps |
| CPU time | 3.66 seconds |
| Started | Jan 17 01:51:37 PM PST 24 |
| Finished | Jan 17 01:51:43 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-058a991a-1949-4204-9450-de80972f8c2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=466013975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.466013975 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2089713678 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 20487467217 ps |
| CPU time | 39.78 seconds |
| Started | Jan 17 01:51:46 PM PST 24 |
| Finished | Jan 17 01:52:27 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-6cfb2fc8-b646-45bc-adcf-b1778073c8d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089713678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2089713678 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.796329547 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4078037178 ps |
| CPU time | 33.42 seconds |
| Started | Jan 17 01:51:46 PM PST 24 |
| Finished | Jan 17 01:52:20 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-442e41ee-3193-4f0a-8d1e-b75194a58af8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=796329547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.796329547 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1365708165 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 30097454 ps |
| CPU time | 2.41 seconds |
| Started | Jan 17 01:51:37 PM PST 24 |
| Finished | Jan 17 01:51:42 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-73434083-df31-48f3-9d08-b99ff37118d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365708165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1365708165 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.3349867518 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 6151361562 ps |
| CPU time | 94.15 seconds |
| Started | Jan 17 01:51:42 PM PST 24 |
| Finished | Jan 17 01:53:16 PM PST 24 |
| Peak memory | 207696 kb |
| Host | smart-1994fe50-6fa2-42a5-8bcd-d1c6157f20a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3349867518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3349867518 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2666309520 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2899593769 ps |
| CPU time | 43.17 seconds |
| Started | Jan 17 01:51:53 PM PST 24 |
| Finished | Jan 17 01:52:37 PM PST 24 |
| Peak memory | 205896 kb |
| Host | smart-5c88b8d3-d7be-4d15-b7ea-3ddce4107994 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2666309520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2666309520 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2790343935 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1584915998 ps |
| CPU time | 323.81 seconds |
| Started | Jan 17 01:51:56 PM PST 24 |
| Finished | Jan 17 01:57:21 PM PST 24 |
| Peak memory | 210760 kb |
| Host | smart-8c56e286-df39-43bc-a3c4-30b8cd03ecb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2790343935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.2790343935 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.784451775 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 3928416784 ps |
| CPU time | 164.8 seconds |
| Started | Jan 17 01:51:58 PM PST 24 |
| Finished | Jan 17 01:54:44 PM PST 24 |
| Peak memory | 209900 kb |
| Host | smart-1b30744e-4b38-4cd8-aec7-3a4d2fbd6a98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=784451775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res et_error.784451775 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3254650240 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 35807498 ps |
| CPU time | 2.48 seconds |
| Started | Jan 17 01:51:42 PM PST 24 |
| Finished | Jan 17 01:51:45 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-fd478335-bd9b-42f9-a5b5-a925ef188a22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3254650240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3254650240 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.4266749990 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 775898218 ps |
| CPU time | 50.57 seconds |
| Started | Jan 17 01:51:56 PM PST 24 |
| Finished | Jan 17 01:52:48 PM PST 24 |
| Peak memory | 206440 kb |
| Host | smart-47afe3f6-d44c-4eef-aaf2-4f23214990a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4266749990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.4266749990 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2269876008 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 65981797574 ps |
| CPU time | 454.68 seconds |
| Started | Jan 17 01:51:55 PM PST 24 |
| Finished | Jan 17 01:59:31 PM PST 24 |
| Peak memory | 207176 kb |
| Host | smart-91a1c612-8719-4885-ada5-e8df70cc4caa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2269876008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.2269876008 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2806790101 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 158616051 ps |
| CPU time | 16.92 seconds |
| Started | Jan 17 01:52:04 PM PST 24 |
| Finished | Jan 17 01:52:23 PM PST 24 |
| Peak memory | 203932 kb |
| Host | smart-4075359c-078f-4d82-a0b0-b5009f266152 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2806790101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2806790101 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.3212627206 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 22192433 ps |
| CPU time | 1.91 seconds |
| Started | Jan 17 01:51:55 PM PST 24 |
| Finished | Jan 17 01:51:58 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-19dc5065-9eb6-4778-9844-f4bbab035d2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3212627206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3212627206 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.1731570948 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 186649453 ps |
| CPU time | 3.27 seconds |
| Started | Jan 17 01:51:54 PM PST 24 |
| Finished | Jan 17 01:51:58 PM PST 24 |
| Peak memory | 203944 kb |
| Host | smart-d45ebc5c-7806-40ac-8ffe-b608e6c6c0af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1731570948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1731570948 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1240205106 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 35703216239 ps |
| CPU time | 139.39 seconds |
| Started | Jan 17 01:51:56 PM PST 24 |
| Finished | Jan 17 01:54:16 PM PST 24 |
| Peak memory | 205088 kb |
| Host | smart-008efc3a-eb61-4358-8f36-2c24c368f919 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240205106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1240205106 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2106621341 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 41713336630 ps |
| CPU time | 207.54 seconds |
| Started | Jan 17 01:51:56 PM PST 24 |
| Finished | Jan 17 01:55:25 PM PST 24 |
| Peak memory | 212008 kb |
| Host | smart-d4aa7387-79dd-423b-adbd-c28247883684 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2106621341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2106621341 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2460330630 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 259388362 ps |
| CPU time | 21.2 seconds |
| Started | Jan 17 01:51:55 PM PST 24 |
| Finished | Jan 17 01:52:18 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-c0130037-5501-4a3d-944a-9ca506ddf748 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460330630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2460330630 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.287828703 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 819583483 ps |
| CPU time | 13.04 seconds |
| Started | Jan 17 01:51:57 PM PST 24 |
| Finished | Jan 17 01:52:13 PM PST 24 |
| Peak memory | 204252 kb |
| Host | smart-35dd4858-6ad4-4602-86a8-d08ac98b2fb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=287828703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.287828703 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.2953243467 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 197462852 ps |
| CPU time | 3.76 seconds |
| Started | Jan 17 01:51:55 PM PST 24 |
| Finished | Jan 17 01:52:00 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-522d2353-c528-4e5e-9268-de2fa3ffb66d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2953243467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2953243467 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1473188884 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 6807460216 ps |
| CPU time | 32.05 seconds |
| Started | Jan 17 01:51:58 PM PST 24 |
| Finished | Jan 17 01:52:32 PM PST 24 |
| Peak memory | 203792 kb |
| Host | smart-4763ed24-0f56-46f6-a0ab-d81a0a993118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473188884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1473188884 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2677659182 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 11649220530 ps |
| CPU time | 31.2 seconds |
| Started | Jan 17 01:51:56 PM PST 24 |
| Finished | Jan 17 01:52:28 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-2c11a044-fbf5-477d-9da1-a20567bac768 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2677659182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2677659182 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3586557021 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 33445618 ps |
| CPU time | 2.39 seconds |
| Started | Jan 17 01:51:56 PM PST 24 |
| Finished | Jan 17 01:51:59 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-a06c7115-4458-4b51-bfa4-12cec665e1fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586557021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3586557021 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.1970891915 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 12498683929 ps |
| CPU time | 88.99 seconds |
| Started | Jan 17 01:52:03 PM PST 24 |
| Finished | Jan 17 01:53:36 PM PST 24 |
| Peak memory | 207136 kb |
| Host | smart-5f971ebe-a6c8-4a41-b20b-49a8d7a7d078 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1970891915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1970891915 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1468600521 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 12629051068 ps |
| CPU time | 79.79 seconds |
| Started | Jan 17 01:52:02 PM PST 24 |
| Finished | Jan 17 01:53:26 PM PST 24 |
| Peak memory | 212004 kb |
| Host | smart-a656f9c3-7516-4d58-ae8f-8e7595ed30ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1468600521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1468600521 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.646048102 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 5971885577 ps |
| CPU time | 386.96 seconds |
| Started | Jan 17 01:52:02 PM PST 24 |
| Finished | Jan 17 01:58:34 PM PST 24 |
| Peak memory | 220220 kb |
| Host | smart-b92cad0d-62b0-4827-af88-463718745fce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=646048102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_res et_error.646048102 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.3441914735 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 106967267 ps |
| CPU time | 10.94 seconds |
| Started | Jan 17 01:51:56 PM PST 24 |
| Finished | Jan 17 01:52:09 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-b8e12ba9-d373-4876-abba-e913b034b956 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3441914735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3441914735 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.180338495 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 329804738 ps |
| CPU time | 22.01 seconds |
| Started | Jan 17 01:52:07 PM PST 24 |
| Finished | Jan 17 01:52:29 PM PST 24 |
| Peak memory | 204276 kb |
| Host | smart-f1d9a8a9-ebc6-4d89-8f0d-5ce9ad5b384f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=180338495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.180338495 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.670215591 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 100091754531 ps |
| CPU time | 529.84 seconds |
| Started | Jan 17 01:52:02 PM PST 24 |
| Finished | Jan 17 02:00:56 PM PST 24 |
| Peak memory | 211976 kb |
| Host | smart-7722e519-e7b3-4b96-adcd-f25ad6f9d001 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=670215591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slo w_rsp.670215591 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2581354105 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1104633222 ps |
| CPU time | 22.81 seconds |
| Started | Jan 17 01:52:07 PM PST 24 |
| Finished | Jan 17 01:52:30 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-1bfcda1f-d13d-4e1b-aa0f-fc90720746e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2581354105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2581354105 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.1958661631 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 925429248 ps |
| CPU time | 18.8 seconds |
| Started | Jan 17 01:52:05 PM PST 24 |
| Finished | Jan 17 01:52:25 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-cf0e23aa-f77a-47af-8093-20f71eb2f145 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1958661631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1958661631 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.2395479731 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 714823414 ps |
| CPU time | 31.79 seconds |
| Started | Jan 17 01:52:04 PM PST 24 |
| Finished | Jan 17 01:52:38 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-535300e9-ed9e-4257-8f4b-2299ab2f18e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2395479731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2395479731 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.986421822 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 112923097917 ps |
| CPU time | 278.13 seconds |
| Started | Jan 17 01:52:05 PM PST 24 |
| Finished | Jan 17 01:56:45 PM PST 24 |
| Peak memory | 204888 kb |
| Host | smart-94a34071-0dd2-4c69-8d6a-c3b955eac1a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=986421822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.986421822 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.753594575 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 131569676180 ps |
| CPU time | 203.41 seconds |
| Started | Jan 17 01:52:07 PM PST 24 |
| Finished | Jan 17 01:55:31 PM PST 24 |
| Peak memory | 205184 kb |
| Host | smart-dde3ca77-f4c0-4000-84c6-67348e0251de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=753594575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.753594575 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.1421820749 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 98978979 ps |
| CPU time | 14.49 seconds |
| Started | Jan 17 01:52:03 PM PST 24 |
| Finished | Jan 17 01:52:21 PM PST 24 |
| Peak memory | 211920 kb |
| Host | smart-89152640-fd73-4903-84ed-c356c0d71c9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421820749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1421820749 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.3635977566 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 589731417 ps |
| CPU time | 8.31 seconds |
| Started | Jan 17 01:52:03 PM PST 24 |
| Finished | Jan 17 01:52:15 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-fd595812-31bc-4de0-ab31-eed614caf313 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3635977566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3635977566 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.1114451196 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 31687302 ps |
| CPU time | 2.34 seconds |
| Started | Jan 17 01:52:05 PM PST 24 |
| Finished | Jan 17 01:52:09 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-db08b0c2-1d57-4e31-a3fe-3fd8995c46e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1114451196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1114451196 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3595789914 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 11793808198 ps |
| CPU time | 27.79 seconds |
| Started | Jan 17 01:52:07 PM PST 24 |
| Finished | Jan 17 01:52:35 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-f25a089f-7e74-4941-9a51-1be7a7716cc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595789914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3595789914 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1875675437 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 12487959521 ps |
| CPU time | 38.78 seconds |
| Started | Jan 17 01:52:05 PM PST 24 |
| Finished | Jan 17 01:52:45 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-d9cb90ae-888d-4d2e-afd7-f0cd2844cdfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1875675437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1875675437 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.1454648073 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 31004240 ps |
| CPU time | 2.65 seconds |
| Started | Jan 17 01:52:11 PM PST 24 |
| Finished | Jan 17 01:52:14 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-53c52d5d-c38b-41bb-9b1e-e234bbcf32af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454648073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.1454648073 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.2588762160 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 5246507541 ps |
| CPU time | 212.92 seconds |
| Started | Jan 17 01:52:04 PM PST 24 |
| Finished | Jan 17 01:55:40 PM PST 24 |
| Peak memory | 210940 kb |
| Host | smart-5a695e63-7739-4a21-b2e4-7ef66ba695a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2588762160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2588762160 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.2576456845 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 4907094326 ps |
| CPU time | 157.75 seconds |
| Started | Jan 17 01:52:05 PM PST 24 |
| Finished | Jan 17 01:54:44 PM PST 24 |
| Peak memory | 209260 kb |
| Host | smart-b9ad2c18-919c-4ca8-b349-1567922f82ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2576456845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2576456845 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3482707830 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 712165705 ps |
| CPU time | 123.95 seconds |
| Started | Jan 17 01:52:06 PM PST 24 |
| Finished | Jan 17 01:54:11 PM PST 24 |
| Peak memory | 209032 kb |
| Host | smart-b9c999b1-ed09-4587-98b1-99437eb46232 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3482707830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.3482707830 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2420113945 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 580051095 ps |
| CPU time | 170.2 seconds |
| Started | Jan 17 01:52:07 PM PST 24 |
| Finished | Jan 17 01:54:57 PM PST 24 |
| Peak memory | 211816 kb |
| Host | smart-8c969f36-5501-45e5-934a-0ba0a5bce2de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2420113945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.2420113945 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.4142805170 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 163142571 ps |
| CPU time | 21.54 seconds |
| Started | Jan 17 01:52:05 PM PST 24 |
| Finished | Jan 17 01:52:28 PM PST 24 |
| Peak memory | 211864 kb |
| Host | smart-f8871438-4e81-4ec5-8c8b-9c32ae75e8c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4142805170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.4142805170 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.380654937 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3058435872 ps |
| CPU time | 32.64 seconds |
| Started | Jan 17 01:49:28 PM PST 24 |
| Finished | Jan 17 01:50:02 PM PST 24 |
| Peak memory | 206068 kb |
| Host | smart-fbe92e35-bc4d-4648-b6e0-88ffa9764aa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=380654937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.380654937 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.302586011 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 208682999 ps |
| CPU time | 8.13 seconds |
| Started | Jan 17 01:49:32 PM PST 24 |
| Finished | Jan 17 01:49:43 PM PST 24 |
| Peak memory | 203924 kb |
| Host | smart-a55701b7-9a12-42de-b9f3-af9e289c6bf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=302586011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.302586011 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.1464525003 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1272938949 ps |
| CPU time | 30.13 seconds |
| Started | Jan 17 01:49:36 PM PST 24 |
| Finished | Jan 17 01:50:08 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-d7accb9a-fcc7-48f0-8e82-3a0bbda6de7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1464525003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1464525003 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.1360922503 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 210411313 ps |
| CPU time | 8.17 seconds |
| Started | Jan 17 01:49:38 PM PST 24 |
| Finished | Jan 17 01:49:48 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-a5ee24d4-3402-4ecb-aaec-43f4fa832174 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1360922503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1360922503 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3130728909 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 22882903077 ps |
| CPU time | 131.23 seconds |
| Started | Jan 17 01:49:26 PM PST 24 |
| Finished | Jan 17 01:51:37 PM PST 24 |
| Peak memory | 212056 kb |
| Host | smart-72a87cf4-4fdb-416b-aa10-4d5098f057d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130728909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3130728909 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.10823683 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2029362386 ps |
| CPU time | 12.01 seconds |
| Started | Jan 17 01:49:29 PM PST 24 |
| Finished | Jan 17 01:49:42 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-6fcc53cd-34dd-4e2a-8e06-513d1cf17a12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=10823683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.10823683 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.1670138644 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 579228709 ps |
| CPU time | 30.65 seconds |
| Started | Jan 17 01:49:26 PM PST 24 |
| Finished | Jan 17 01:49:58 PM PST 24 |
| Peak memory | 211880 kb |
| Host | smart-2ed1d7b9-3bd8-4eeb-b4d0-13ae79c07821 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670138644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1670138644 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.2623312579 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 5123753065 ps |
| CPU time | 24.7 seconds |
| Started | Jan 17 01:49:29 PM PST 24 |
| Finished | Jan 17 01:49:54 PM PST 24 |
| Peak memory | 203896 kb |
| Host | smart-1f870ec3-2ebc-4c86-88c4-92258de8f9ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2623312579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2623312579 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.2527917414 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 40199937 ps |
| CPU time | 2.29 seconds |
| Started | Jan 17 01:49:24 PM PST 24 |
| Finished | Jan 17 01:49:27 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-c817839e-efac-49dc-a562-74271f682e4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2527917414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2527917414 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2944543695 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 12638526646 ps |
| CPU time | 35.43 seconds |
| Started | Jan 17 01:49:32 PM PST 24 |
| Finished | Jan 17 01:50:10 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-ce0211ed-5381-4058-9ff3-810f39a61567 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944543695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2944543695 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2722014268 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2690537136 ps |
| CPU time | 19.32 seconds |
| Started | Jan 17 01:49:33 PM PST 24 |
| Finished | Jan 17 01:49:56 PM PST 24 |
| Peak memory | 203872 kb |
| Host | smart-76382505-d1eb-45d9-b965-bca9349ab59c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2722014268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2722014268 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1769807175 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 37467097 ps |
| CPU time | 2.37 seconds |
| Started | Jan 17 01:49:36 PM PST 24 |
| Finished | Jan 17 01:49:41 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-ca30fbb3-9ebd-4d0b-bb3c-829991c68b70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769807175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1769807175 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3417185463 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 6008610993 ps |
| CPU time | 250.85 seconds |
| Started | Jan 17 01:49:33 PM PST 24 |
| Finished | Jan 17 01:53:47 PM PST 24 |
| Peak memory | 208348 kb |
| Host | smart-e017db9f-83eb-4ba3-b0ea-d4a7cfe20e27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3417185463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3417185463 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.1039315164 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2092734318 ps |
| CPU time | 63.59 seconds |
| Started | Jan 17 01:49:33 PM PST 24 |
| Finished | Jan 17 01:50:40 PM PST 24 |
| Peak memory | 205520 kb |
| Host | smart-ebc01c21-b3bc-426d-99eb-f41a7e6f455a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1039315164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1039315164 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1235141546 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 333299947 ps |
| CPU time | 130.14 seconds |
| Started | Jan 17 01:49:30 PM PST 24 |
| Finished | Jan 17 01:51:41 PM PST 24 |
| Peak memory | 208244 kb |
| Host | smart-d212cfe8-5e2c-47bb-8f9e-925d014414dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1235141546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.1235141546 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1775348539 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 324890766 ps |
| CPU time | 98.9 seconds |
| Started | Jan 17 01:49:30 PM PST 24 |
| Finished | Jan 17 01:51:10 PM PST 24 |
| Peak memory | 209236 kb |
| Host | smart-535fc669-8605-4185-a5f8-51b205c664b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1775348539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1775348539 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.2864156627 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 56784760 ps |
| CPU time | 2.44 seconds |
| Started | Jan 17 01:49:32 PM PST 24 |
| Finished | Jan 17 01:49:39 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-88f24f5b-126f-4a75-9e25-e0573ed8ecfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2864156627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2864156627 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.2785607325 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 607711744 ps |
| CPU time | 11.49 seconds |
| Started | Jan 17 01:52:13 PM PST 24 |
| Finished | Jan 17 01:52:25 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-4abf855f-c0e3-4161-98de-f4b49788a344 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2785607325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2785607325 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2398985412 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 193367873620 ps |
| CPU time | 733.66 seconds |
| Started | Jan 17 01:52:12 PM PST 24 |
| Finished | Jan 17 02:04:27 PM PST 24 |
| Peak memory | 207852 kb |
| Host | smart-dc8cf6df-5846-4a2f-88f3-d6ff99775ba3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2398985412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.2398985412 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.740901394 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 381947996 ps |
| CPU time | 12.23 seconds |
| Started | Jan 17 01:52:13 PM PST 24 |
| Finished | Jan 17 01:52:26 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-526365b1-a897-4a11-afca-b00cfea84dad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=740901394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.740901394 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.4123746464 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 405132135 ps |
| CPU time | 9.1 seconds |
| Started | Jan 17 01:52:12 PM PST 24 |
| Finished | Jan 17 01:52:22 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-20d1264a-cfcc-404e-9bed-a1977fb49052 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4123746464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.4123746464 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.2205864823 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 28836554 ps |
| CPU time | 2.11 seconds |
| Started | Jan 17 01:52:13 PM PST 24 |
| Finished | Jan 17 01:52:16 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-d184c9e4-6e65-48a3-a159-5a52394a5839 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2205864823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2205864823 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2153723725 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 15509498425 ps |
| CPU time | 66.83 seconds |
| Started | Jan 17 01:52:11 PM PST 24 |
| Finished | Jan 17 01:53:19 PM PST 24 |
| Peak memory | 211976 kb |
| Host | smart-1bbe0f4b-2e0a-46a1-b311-7262adda394a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153723725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2153723725 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.541563053 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 14807318401 ps |
| CPU time | 134.58 seconds |
| Started | Jan 17 01:52:11 PM PST 24 |
| Finished | Jan 17 01:54:26 PM PST 24 |
| Peak memory | 211992 kb |
| Host | smart-8f49ed56-b21c-4692-afe9-47f0794da232 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=541563053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.541563053 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1222119720 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 216764984 ps |
| CPU time | 26.99 seconds |
| Started | Jan 17 01:52:12 PM PST 24 |
| Finished | Jan 17 01:52:40 PM PST 24 |
| Peak memory | 211936 kb |
| Host | smart-014d832c-5d46-4ba3-8a74-aeb51b05527d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222119720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1222119720 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.3527159005 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 177983265 ps |
| CPU time | 8.36 seconds |
| Started | Jan 17 01:52:11 PM PST 24 |
| Finished | Jan 17 01:52:20 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-72cc118d-ebd0-4587-b005-0b8433e27e52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3527159005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3527159005 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.3553315950 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 112363136 ps |
| CPU time | 2.92 seconds |
| Started | Jan 17 01:52:02 PM PST 24 |
| Finished | Jan 17 01:52:09 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-b81b5c06-c686-4c2e-906e-f0f0bd27d2cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3553315950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3553315950 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2962229886 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 10451520174 ps |
| CPU time | 32.25 seconds |
| Started | Jan 17 01:52:07 PM PST 24 |
| Finished | Jan 17 01:52:40 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-9dfb499e-71fb-42c2-b5bb-0f2e23bd43ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962229886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2962229886 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1644453825 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 7491769130 ps |
| CPU time | 33.63 seconds |
| Started | Jan 17 01:52:06 PM PST 24 |
| Finished | Jan 17 01:52:41 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-0f390315-09aa-48c9-b3b6-befa5ec3261b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1644453825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1644453825 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1522924561 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 29092298 ps |
| CPU time | 2.33 seconds |
| Started | Jan 17 01:52:07 PM PST 24 |
| Finished | Jan 17 01:52:10 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-55620a0f-2dc3-45d2-8a8d-23022811c5c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522924561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1522924561 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.2905063003 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 5314635169 ps |
| CPU time | 90.16 seconds |
| Started | Jan 17 01:52:13 PM PST 24 |
| Finished | Jan 17 01:53:44 PM PST 24 |
| Peak memory | 208156 kb |
| Host | smart-cca8a094-4a67-428f-a2e9-d6d5e02e7e1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2905063003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2905063003 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3588121009 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 15986205100 ps |
| CPU time | 163.55 seconds |
| Started | Jan 17 01:52:13 PM PST 24 |
| Finished | Jan 17 01:54:57 PM PST 24 |
| Peak memory | 211960 kb |
| Host | smart-1069cae2-0021-4040-9178-36dea5cf5fd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3588121009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3588121009 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3988945779 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 451583519 ps |
| CPU time | 166.36 seconds |
| Started | Jan 17 01:52:12 PM PST 24 |
| Finished | Jan 17 01:54:59 PM PST 24 |
| Peak memory | 208912 kb |
| Host | smart-a4a768e5-12f8-42b8-9dec-267998c8b748 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3988945779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.3988945779 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2165394738 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 48766674 ps |
| CPU time | 10.19 seconds |
| Started | Jan 17 01:52:20 PM PST 24 |
| Finished | Jan 17 01:52:31 PM PST 24 |
| Peak memory | 205184 kb |
| Host | smart-4f927cea-9bdc-48f8-8374-fde7b0239e64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2165394738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.2165394738 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.2790570097 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 301884598 ps |
| CPU time | 19.93 seconds |
| Started | Jan 17 01:52:11 PM PST 24 |
| Finished | Jan 17 01:52:31 PM PST 24 |
| Peak memory | 204908 kb |
| Host | smart-cfd8ad71-527b-48fd-a7e5-d13702a029e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2790570097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2790570097 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3397912616 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 482440034 ps |
| CPU time | 31.42 seconds |
| Started | Jan 17 01:52:21 PM PST 24 |
| Finished | Jan 17 01:52:54 PM PST 24 |
| Peak memory | 211904 kb |
| Host | smart-4271f52c-37a1-49d6-b5c2-2d415701c3e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3397912616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3397912616 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3389223215 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 31866534190 ps |
| CPU time | 296.48 seconds |
| Started | Jan 17 01:52:20 PM PST 24 |
| Finished | Jan 17 01:57:17 PM PST 24 |
| Peak memory | 206760 kb |
| Host | smart-31491c2d-f16b-40e0-9fd5-4090ff064120 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3389223215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.3389223215 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.308613991 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 148811313 ps |
| CPU time | 16.9 seconds |
| Started | Jan 17 01:52:23 PM PST 24 |
| Finished | Jan 17 01:52:44 PM PST 24 |
| Peak memory | 204164 kb |
| Host | smart-17b7fc96-5764-4a91-a7f3-e10f48e4fcd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=308613991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.308613991 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.1563160920 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 380874228 ps |
| CPU time | 19.45 seconds |
| Started | Jan 17 01:52:20 PM PST 24 |
| Finished | Jan 17 01:52:40 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-27037fcd-7439-4540-81af-2bf00417bbf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1563160920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1563160920 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.1884719068 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 637278804 ps |
| CPU time | 8.26 seconds |
| Started | Jan 17 01:52:15 PM PST 24 |
| Finished | Jan 17 01:52:24 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-114cf76f-71c7-49aa-bab0-34ca8d16282c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1884719068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1884719068 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3926571912 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 27486295362 ps |
| CPU time | 104.76 seconds |
| Started | Jan 17 01:52:18 PM PST 24 |
| Finished | Jan 17 01:54:03 PM PST 24 |
| Peak memory | 212016 kb |
| Host | smart-3f28cd8e-95ab-405c-8b7d-0139c613914c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926571912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3926571912 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.3229662278 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 19020135062 ps |
| CPU time | 152.98 seconds |
| Started | Jan 17 01:52:18 PM PST 24 |
| Finished | Jan 17 01:54:52 PM PST 24 |
| Peak memory | 212004 kb |
| Host | smart-75bc372b-28f9-4ec3-9e40-80fa4213a006 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3229662278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3229662278 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.4142342884 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 331361621 ps |
| CPU time | 14.87 seconds |
| Started | Jan 17 01:52:16 PM PST 24 |
| Finished | Jan 17 01:52:31 PM PST 24 |
| Peak memory | 204852 kb |
| Host | smart-8d60013d-f5c5-4268-b33b-e16a78a0f3b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142342884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.4142342884 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.742001895 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 133898954 ps |
| CPU time | 2.88 seconds |
| Started | Jan 17 01:52:29 PM PST 24 |
| Finished | Jan 17 01:52:40 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-1f7373c4-e7d3-4c27-ad61-a88fdb41901d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=742001895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.742001895 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.2525529515 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 32002899 ps |
| CPU time | 1.93 seconds |
| Started | Jan 17 01:52:13 PM PST 24 |
| Finished | Jan 17 01:52:15 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-3529528b-73b8-4f02-b5d0-bddb686d864f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2525529515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2525529515 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3721394352 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5578020423 ps |
| CPU time | 29.04 seconds |
| Started | Jan 17 01:52:20 PM PST 24 |
| Finished | Jan 17 01:52:52 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-755b4e59-ca85-4cb4-963d-046169a3d83b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721394352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3721394352 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1578872007 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 20758389483 ps |
| CPU time | 48.75 seconds |
| Started | Jan 17 01:52:20 PM PST 24 |
| Finished | Jan 17 01:53:09 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-e02dda94-5fa2-40f0-ac30-175f03888c30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1578872007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1578872007 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.4174351131 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 23850933 ps |
| CPU time | 2.07 seconds |
| Started | Jan 17 01:52:19 PM PST 24 |
| Finished | Jan 17 01:52:22 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-6db388f9-ec52-4cc0-9b5e-95efee7919de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174351131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.4174351131 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.3137699229 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1694791717 ps |
| CPU time | 94.04 seconds |
| Started | Jan 17 01:52:18 PM PST 24 |
| Finished | Jan 17 01:53:53 PM PST 24 |
| Peak memory | 207316 kb |
| Host | smart-fcf55cd3-f33d-4ce1-8fab-3040a5d10caa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3137699229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3137699229 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3450513928 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 653726966 ps |
| CPU time | 26.31 seconds |
| Started | Jan 17 01:52:20 PM PST 24 |
| Finished | Jan 17 01:52:47 PM PST 24 |
| Peak memory | 204124 kb |
| Host | smart-e610d98f-e1b1-46e4-b300-38e1715efc2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3450513928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3450513928 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.2459215115 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 234727704 ps |
| CPU time | 55.03 seconds |
| Started | Jan 17 01:52:19 PM PST 24 |
| Finished | Jan 17 01:53:15 PM PST 24 |
| Peak memory | 206464 kb |
| Host | smart-2e2e117e-7cbd-4349-a8a3-99619a386b13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2459215115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.2459215115 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.4183543128 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 8468336579 ps |
| CPU time | 280 seconds |
| Started | Jan 17 01:52:19 PM PST 24 |
| Finished | Jan 17 01:57:00 PM PST 24 |
| Peak memory | 220232 kb |
| Host | smart-80f48b7d-fe1c-4c73-b17e-76dc423570b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4183543128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.4183543128 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.3379702922 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 109441206 ps |
| CPU time | 19.56 seconds |
| Started | Jan 17 01:52:14 PM PST 24 |
| Finished | Jan 17 01:52:34 PM PST 24 |
| Peak memory | 211904 kb |
| Host | smart-e502a4a9-e55f-4f25-ab38-6a395016e6fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3379702922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3379702922 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.563116883 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 1496229237 ps |
| CPU time | 36.04 seconds |
| Started | Jan 17 01:52:33 PM PST 24 |
| Finished | Jan 17 01:53:15 PM PST 24 |
| Peak memory | 211904 kb |
| Host | smart-f5c71d3c-691f-4424-9f5b-dbdd850ce20b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=563116883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.563116883 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2154011958 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 102572502311 ps |
| CPU time | 538.64 seconds |
| Started | Jan 17 01:52:32 PM PST 24 |
| Finished | Jan 17 02:01:38 PM PST 24 |
| Peak memory | 206212 kb |
| Host | smart-c3c4ef7c-9196-4e85-a880-989967f2b59b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2154011958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.2154011958 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.325077153 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 74678043 ps |
| CPU time | 7.12 seconds |
| Started | Jan 17 01:52:34 PM PST 24 |
| Finished | Jan 17 01:52:46 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-6a46ddf7-1726-4110-a6a6-a140ae07e93a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=325077153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.325077153 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.3440016743 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 168803959 ps |
| CPU time | 12.37 seconds |
| Started | Jan 17 01:52:30 PM PST 24 |
| Finished | Jan 17 01:52:50 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-a9c7bd39-07f2-4a22-9216-c01f6d273536 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440016743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3440016743 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.686436945 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 137667646 ps |
| CPU time | 14.15 seconds |
| Started | Jan 17 01:52:22 PM PST 24 |
| Finished | Jan 17 01:52:38 PM PST 24 |
| Peak memory | 211868 kb |
| Host | smart-a836b7b4-bf51-49c3-9da9-91a200289c51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=686436945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.686436945 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3857719269 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 35009890079 ps |
| CPU time | 55.98 seconds |
| Started | Jan 17 01:52:33 PM PST 24 |
| Finished | Jan 17 01:53:35 PM PST 24 |
| Peak memory | 211992 kb |
| Host | smart-7a9ef153-44f0-40ec-9793-4e1d564af709 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857719269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3857719269 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.619832716 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 16253474913 ps |
| CPU time | 152.49 seconds |
| Started | Jan 17 01:52:30 PM PST 24 |
| Finished | Jan 17 01:55:10 PM PST 24 |
| Peak memory | 211988 kb |
| Host | smart-0ffbe275-0d1e-4b0a-a0eb-71abfc828453 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=619832716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.619832716 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.3972779074 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 22492041 ps |
| CPU time | 3.59 seconds |
| Started | Jan 17 01:52:44 PM PST 24 |
| Finished | Jan 17 01:52:48 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-6f3c4277-21ff-43c2-8d15-aac3f30d1689 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972779074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3972779074 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.1836620049 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 991075780 ps |
| CPU time | 24.48 seconds |
| Started | Jan 17 01:52:30 PM PST 24 |
| Finished | Jan 17 01:53:03 PM PST 24 |
| Peak memory | 204172 kb |
| Host | smart-60395235-a8cc-4a27-9565-32ff21d49b6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1836620049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1836620049 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.3065488525 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 29305918 ps |
| CPU time | 2.49 seconds |
| Started | Jan 17 01:52:20 PM PST 24 |
| Finished | Jan 17 01:52:25 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-b6834bc6-0a87-4917-9779-69f2e55825fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3065488525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3065488525 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.839425998 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 8244147956 ps |
| CPU time | 33.12 seconds |
| Started | Jan 17 01:52:22 PM PST 24 |
| Finished | Jan 17 01:52:57 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-54b523e6-175c-429d-86bd-1fb88f89face |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=839425998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.839425998 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2111748214 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 7937226033 ps |
| CPU time | 29 seconds |
| Started | Jan 17 01:52:21 PM PST 24 |
| Finished | Jan 17 01:52:52 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-f9c6676c-283a-4f0a-ab26-9dff3557049d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2111748214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2111748214 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2747130449 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 39046261 ps |
| CPU time | 2.26 seconds |
| Started | Jan 17 01:52:21 PM PST 24 |
| Finished | Jan 17 01:52:25 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-3e148fc9-03ce-4f7c-bcdf-8c0c4d556cd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747130449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2747130449 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.201254342 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1141119408 ps |
| CPU time | 41.27 seconds |
| Started | Jan 17 01:52:31 PM PST 24 |
| Finished | Jan 17 01:53:20 PM PST 24 |
| Peak memory | 206156 kb |
| Host | smart-b9d1c867-c99b-44be-afad-c95290a82a3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=201254342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.201254342 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1053016495 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1477996080 ps |
| CPU time | 77.61 seconds |
| Started | Jan 17 01:52:30 PM PST 24 |
| Finished | Jan 17 01:53:56 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-e23b1b27-79cf-426c-9180-9f77c341049e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1053016495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1053016495 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2322525305 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 209889640 ps |
| CPU time | 56.53 seconds |
| Started | Jan 17 01:52:33 PM PST 24 |
| Finished | Jan 17 01:53:35 PM PST 24 |
| Peak memory | 211952 kb |
| Host | smart-6c137e31-da78-420f-8731-5399cede5e7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2322525305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.2322525305 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1761094350 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 194312406 ps |
| CPU time | 85.49 seconds |
| Started | Jan 17 01:52:35 PM PST 24 |
| Finished | Jan 17 01:54:04 PM PST 24 |
| Peak memory | 208948 kb |
| Host | smart-8eafafe5-6f04-4cec-a6e7-d2553c8a1555 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1761094350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.1761094350 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3640823013 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 235401452 ps |
| CPU time | 7.9 seconds |
| Started | Jan 17 01:52:29 PM PST 24 |
| Finished | Jan 17 01:52:45 PM PST 24 |
| Peak memory | 211936 kb |
| Host | smart-1a81e6ac-d921-45b5-be15-9f4de1be9908 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3640823013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3640823013 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.1886744313 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 492818681 ps |
| CPU time | 31.26 seconds |
| Started | Jan 17 01:52:31 PM PST 24 |
| Finished | Jan 17 01:53:10 PM PST 24 |
| Peak memory | 206316 kb |
| Host | smart-7d6c717e-ace7-4a01-b4a9-47c64272c08b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1886744313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1886744313 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3120108530 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 94104379408 ps |
| CPU time | 275.3 seconds |
| Started | Jan 17 01:52:32 PM PST 24 |
| Finished | Jan 17 01:57:14 PM PST 24 |
| Peak memory | 206064 kb |
| Host | smart-760bf80e-00f3-42ee-a863-f588ceab5dfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3120108530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.3120108530 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1213327748 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 759867447 ps |
| CPU time | 14 seconds |
| Started | Jan 17 01:52:30 PM PST 24 |
| Finished | Jan 17 01:52:52 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-83641ac6-e8e9-476c-8f8e-dc3e946cf959 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1213327748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1213327748 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.608976918 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 446194678 ps |
| CPU time | 18.52 seconds |
| Started | Jan 17 01:52:31 PM PST 24 |
| Finished | Jan 17 01:52:57 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-03a45d15-4222-43c5-b91a-d1b9ecdacd68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=608976918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.608976918 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.1060770916 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 141339711 ps |
| CPU time | 16.32 seconds |
| Started | Jan 17 01:52:30 PM PST 24 |
| Finished | Jan 17 01:52:54 PM PST 24 |
| Peak memory | 211952 kb |
| Host | smart-2a12d69b-046d-49af-a75a-aafe796efc51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1060770916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1060770916 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2582608979 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 23110093966 ps |
| CPU time | 101.98 seconds |
| Started | Jan 17 01:52:32 PM PST 24 |
| Finished | Jan 17 01:54:21 PM PST 24 |
| Peak memory | 211984 kb |
| Host | smart-cf537738-3ac6-4c17-9431-7aec7fb983ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582608979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2582608979 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.727379516 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 28450254984 ps |
| CPU time | 220.28 seconds |
| Started | Jan 17 01:52:29 PM PST 24 |
| Finished | Jan 17 01:56:18 PM PST 24 |
| Peak memory | 211900 kb |
| Host | smart-5d529f30-2a57-44e7-8a67-805889252485 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=727379516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.727379516 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1758390628 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 177603890 ps |
| CPU time | 13.11 seconds |
| Started | Jan 17 01:52:35 PM PST 24 |
| Finished | Jan 17 01:52:52 PM PST 24 |
| Peak memory | 204440 kb |
| Host | smart-b0bbde49-cb8e-46a6-a52a-2c72630051b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758390628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1758390628 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.2482319966 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 670448512 ps |
| CPU time | 12.54 seconds |
| Started | Jan 17 01:52:31 PM PST 24 |
| Finished | Jan 17 01:52:51 PM PST 24 |
| Peak memory | 204016 kb |
| Host | smart-0a5f2b36-0556-4fa0-87ca-7fbe8dc79068 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2482319966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2482319966 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.3449815588 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 51416504 ps |
| CPU time | 2.21 seconds |
| Started | Jan 17 01:52:30 PM PST 24 |
| Finished | Jan 17 01:52:40 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-25eed7e9-0990-48ed-88c5-3c0a3cc5c715 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3449815588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3449815588 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.280963880 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 6663812876 ps |
| CPU time | 24.86 seconds |
| Started | Jan 17 01:52:30 PM PST 24 |
| Finished | Jan 17 01:53:03 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-947d9d11-c412-42f5-a565-421fdcbde515 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=280963880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.280963880 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2567502354 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 4096465277 ps |
| CPU time | 28.84 seconds |
| Started | Jan 17 01:52:29 PM PST 24 |
| Finished | Jan 17 01:53:06 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-aa9f3088-6ec0-4911-86e8-2483bf96948f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2567502354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2567502354 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3873240697 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 25085549 ps |
| CPU time | 2.03 seconds |
| Started | Jan 17 01:52:29 PM PST 24 |
| Finished | Jan 17 01:52:40 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-7f220de1-cfa3-4c9b-8506-7e81a7c21c0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873240697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3873240697 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.2179440493 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 595795148 ps |
| CPU time | 60.22 seconds |
| Started | Jan 17 01:52:30 PM PST 24 |
| Finished | Jan 17 01:53:38 PM PST 24 |
| Peak memory | 206780 kb |
| Host | smart-d4f0efb9-4886-4095-afd3-b45420a9727e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2179440493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2179440493 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3822426140 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1265826314 ps |
| CPU time | 110.55 seconds |
| Started | Jan 17 01:52:33 PM PST 24 |
| Finished | Jan 17 01:54:29 PM PST 24 |
| Peak memory | 207820 kb |
| Host | smart-6ba78314-8b02-4844-a50d-12f268628dff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3822426140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3822426140 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.613994421 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 7233325789 ps |
| CPU time | 209.74 seconds |
| Started | Jan 17 01:52:33 PM PST 24 |
| Finished | Jan 17 01:56:09 PM PST 24 |
| Peak memory | 208544 kb |
| Host | smart-0246ed6d-55d3-4338-8b09-61383115224a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=613994421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand _reset.613994421 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3936778520 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 120563690 ps |
| CPU time | 76.99 seconds |
| Started | Jan 17 01:52:38 PM PST 24 |
| Finished | Jan 17 01:53:56 PM PST 24 |
| Peak memory | 209060 kb |
| Host | smart-2df40de6-c4e1-44ec-88bd-4d4b65f82803 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3936778520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.3936778520 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.300176783 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 898330708 ps |
| CPU time | 31.07 seconds |
| Started | Jan 17 01:52:38 PM PST 24 |
| Finished | Jan 17 01:53:10 PM PST 24 |
| Peak memory | 211960 kb |
| Host | smart-05a624b5-72e7-4430-8c1b-39a622f98051 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=300176783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.300176783 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.1752062693 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 146199185 ps |
| CPU time | 13.56 seconds |
| Started | Jan 17 01:52:37 PM PST 24 |
| Finished | Jan 17 01:52:53 PM PST 24 |
| Peak memory | 211916 kb |
| Host | smart-e7d806d1-91b2-457e-9b11-95b489014a27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1752062693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1752062693 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.33835339 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 37319600 ps |
| CPU time | 4.38 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:52:50 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-bc2cd929-57e2-4b58-8bb1-8b269ce13862 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=33835339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.33835339 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.2620584065 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 158905048 ps |
| CPU time | 19.12 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:53:05 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-f5b77c92-38dc-48cd-bdf1-3249e1abad02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2620584065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2620584065 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.1322101403 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 823278839 ps |
| CPU time | 20.9 seconds |
| Started | Jan 17 01:52:43 PM PST 24 |
| Finished | Jan 17 01:53:04 PM PST 24 |
| Peak memory | 204508 kb |
| Host | smart-eacf7fee-15fc-420d-8010-21d4e680e38c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1322101403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.1322101403 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1886510441 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 33716764789 ps |
| CPU time | 91.91 seconds |
| Started | Jan 17 01:52:39 PM PST 24 |
| Finished | Jan 17 01:54:12 PM PST 24 |
| Peak memory | 211896 kb |
| Host | smart-226625e1-87b3-4c57-8ac0-8999638ff18e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886510441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1886510441 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1964615776 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 18493197362 ps |
| CPU time | 166.74 seconds |
| Started | Jan 17 01:52:38 PM PST 24 |
| Finished | Jan 17 01:55:26 PM PST 24 |
| Peak memory | 204960 kb |
| Host | smart-5d126127-a99f-4fce-bd11-f65d626df5ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1964615776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1964615776 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1682133145 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 285544283 ps |
| CPU time | 22.05 seconds |
| Started | Jan 17 01:52:44 PM PST 24 |
| Finished | Jan 17 01:53:07 PM PST 24 |
| Peak memory | 211904 kb |
| Host | smart-715cd7c0-40a1-4869-ad46-b69f6d25c36a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682133145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1682133145 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.626268015 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 516034328 ps |
| CPU time | 13.29 seconds |
| Started | Jan 17 01:52:37 PM PST 24 |
| Finished | Jan 17 01:52:52 PM PST 24 |
| Peak memory | 204304 kb |
| Host | smart-3464ade7-d4f6-40d9-ba82-7e988e4bfb5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=626268015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.626268015 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1027228571 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 35864952 ps |
| CPU time | 2.55 seconds |
| Started | Jan 17 01:52:37 PM PST 24 |
| Finished | Jan 17 01:52:42 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-c050d6c2-c82c-4080-9a2f-30184ce3f5cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1027228571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1027228571 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2465029753 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 11834978428 ps |
| CPU time | 34.46 seconds |
| Started | Jan 17 01:52:37 PM PST 24 |
| Finished | Jan 17 01:53:13 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-26dbcfb8-cace-4258-b60c-8ba9519f3c6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465029753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2465029753 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1869427398 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 9533452597 ps |
| CPU time | 39.61 seconds |
| Started | Jan 17 01:52:39 PM PST 24 |
| Finished | Jan 17 01:53:20 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-990f9dce-0b9a-46e1-999c-05f43e14d719 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1869427398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1869427398 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1881510818 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 35102539 ps |
| CPU time | 2.32 seconds |
| Started | Jan 17 01:52:36 PM PST 24 |
| Finished | Jan 17 01:52:41 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-8972f344-a3a4-43b6-a285-3ba66fd051b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881510818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1881510818 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1554344071 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 4350625370 ps |
| CPU time | 159.51 seconds |
| Started | Jan 17 01:52:38 PM PST 24 |
| Finished | Jan 17 01:55:20 PM PST 24 |
| Peak memory | 209128 kb |
| Host | smart-8c0db4bb-561a-4296-aeaa-602f9f2185f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1554344071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1554344071 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.797966356 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1864968206 ps |
| CPU time | 20.79 seconds |
| Started | Jan 17 01:52:36 PM PST 24 |
| Finished | Jan 17 01:53:00 PM PST 24 |
| Peak memory | 204080 kb |
| Host | smart-10bef1c8-b09c-474b-8489-d41eff83176e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=797966356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.797966356 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.519325541 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 13001683825 ps |
| CPU time | 548.07 seconds |
| Started | Jan 17 01:52:36 PM PST 24 |
| Finished | Jan 17 02:01:47 PM PST 24 |
| Peak memory | 220236 kb |
| Host | smart-2fa16936-f28c-4e6e-b26e-bebfd60ca7c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=519325541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand _reset.519325541 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2195899938 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 149528845 ps |
| CPU time | 62.09 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:53:48 PM PST 24 |
| Peak memory | 208348 kb |
| Host | smart-90faa9da-db59-429e-86ef-f18658d8014f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2195899938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.2195899938 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.75624433 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 129434127 ps |
| CPU time | 5.88 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:52:52 PM PST 24 |
| Peak memory | 211920 kb |
| Host | smart-964d5e41-6d29-455c-aa31-a4c5226603e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=75624433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.75624433 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.3090084182 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 701516947 ps |
| CPU time | 28.38 seconds |
| Started | Jan 17 01:52:38 PM PST 24 |
| Finished | Jan 17 01:53:08 PM PST 24 |
| Peak memory | 211932 kb |
| Host | smart-119b4ef7-fc21-4658-8a24-475189733239 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3090084182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3090084182 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1593003368 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 37853108737 ps |
| CPU time | 197.39 seconds |
| Started | Jan 17 01:52:37 PM PST 24 |
| Finished | Jan 17 01:55:56 PM PST 24 |
| Peak memory | 206356 kb |
| Host | smart-ca7ddc26-3a78-44e5-b425-5062b88e764d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1593003368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.1593003368 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.4283196587 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 350819289 ps |
| CPU time | 9.44 seconds |
| Started | Jan 17 01:52:47 PM PST 24 |
| Finished | Jan 17 01:52:57 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-c7e631a5-fe9d-4a52-9360-b5838b7d04c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4283196587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.4283196587 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.2526443748 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 32014747 ps |
| CPU time | 3.53 seconds |
| Started | Jan 17 01:52:37 PM PST 24 |
| Finished | Jan 17 01:52:43 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-282df7a7-3830-4946-8dd3-1bb11cfcc6ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2526443748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2526443748 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.40102948 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1678947660 ps |
| CPU time | 31.75 seconds |
| Started | Jan 17 01:52:40 PM PST 24 |
| Finished | Jan 17 01:53:13 PM PST 24 |
| Peak memory | 211844 kb |
| Host | smart-05688a9c-25c6-4eba-a104-37043a0f399c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=40102948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.40102948 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3031816614 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 106336904339 ps |
| CPU time | 197.42 seconds |
| Started | Jan 17 01:52:37 PM PST 24 |
| Finished | Jan 17 01:55:57 PM PST 24 |
| Peak memory | 205320 kb |
| Host | smart-d9f6fba7-09a7-45d5-9520-b648659238f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031816614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3031816614 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3667359086 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 82361791520 ps |
| CPU time | 164.2 seconds |
| Started | Jan 17 01:52:44 PM PST 24 |
| Finished | Jan 17 01:55:29 PM PST 24 |
| Peak memory | 205028 kb |
| Host | smart-7efbf954-45b9-4fc7-b036-5e89f83c60e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3667359086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3667359086 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1493743838 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 92116067 ps |
| CPU time | 7.17 seconds |
| Started | Jan 17 01:52:44 PM PST 24 |
| Finished | Jan 17 01:52:52 PM PST 24 |
| Peak memory | 211876 kb |
| Host | smart-72aa844a-fd7b-4ff8-b69d-2d79e5aa9b73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493743838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1493743838 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.276066733 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1047571960 ps |
| CPU time | 17.12 seconds |
| Started | Jan 17 01:52:38 PM PST 24 |
| Finished | Jan 17 01:52:57 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-ebc1f449-078c-4a66-a843-54a658fdf05e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=276066733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.276066733 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.1926127713 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 36438026 ps |
| CPU time | 2.46 seconds |
| Started | Jan 17 01:52:38 PM PST 24 |
| Finished | Jan 17 01:52:42 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-821c363a-b7ef-4bb6-a41c-7286ec68fba1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1926127713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1926127713 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3746883206 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 7412994343 ps |
| CPU time | 30.66 seconds |
| Started | Jan 17 01:52:39 PM PST 24 |
| Finished | Jan 17 01:53:11 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-9052ebec-99fc-402d-8405-d5fb2991cc0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746883206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3746883206 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3656852650 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 4620829766 ps |
| CPU time | 31.28 seconds |
| Started | Jan 17 01:52:38 PM PST 24 |
| Finished | Jan 17 01:53:11 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-98589988-56e0-4f1d-8a94-22c94fd1605a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3656852650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3656852650 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.715806119 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 31232562 ps |
| CPU time | 2.38 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:52:48 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-736ecf00-66fd-4f04-bab8-4f0c7ca6d81b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715806119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.715806119 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.3987051665 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 4104126900 ps |
| CPU time | 107.16 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:54:33 PM PST 24 |
| Peak memory | 205992 kb |
| Host | smart-00d1f28c-9279-4afa-ae92-9844ff808a40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3987051665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3987051665 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2205080926 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1158693403 ps |
| CPU time | 20.41 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:53:06 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-7b08e714-060d-4757-bcaf-080e8df3cd62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2205080926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2205080926 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2328269307 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 514928661 ps |
| CPU time | 185.82 seconds |
| Started | Jan 17 01:52:46 PM PST 24 |
| Finished | Jan 17 01:55:52 PM PST 24 |
| Peak memory | 208656 kb |
| Host | smart-d2ad2ddc-6c13-46e3-a4a5-e29211edea15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2328269307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.2328269307 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1846901151 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 145401482 ps |
| CPU time | 55.47 seconds |
| Started | Jan 17 01:52:47 PM PST 24 |
| Finished | Jan 17 01:53:43 PM PST 24 |
| Peak memory | 206860 kb |
| Host | smart-b76e0c0f-7c1e-4119-8c9a-5a59f6a1cfe0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1846901151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.1846901151 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1117250378 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 580373505 ps |
| CPU time | 14.79 seconds |
| Started | Jan 17 01:52:49 PM PST 24 |
| Finished | Jan 17 01:53:05 PM PST 24 |
| Peak memory | 211968 kb |
| Host | smart-d6c9441d-b75e-4c11-86e3-73eea69291ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1117250378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1117250378 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3518312826 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 246460216 ps |
| CPU time | 36.1 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:53:22 PM PST 24 |
| Peak memory | 211904 kb |
| Host | smart-19969f03-2144-4cbd-b149-cc17f1d6fc8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3518312826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3518312826 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3535753802 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 23723090091 ps |
| CPU time | 203.16 seconds |
| Started | Jan 17 01:52:47 PM PST 24 |
| Finished | Jan 17 01:56:11 PM PST 24 |
| Peak memory | 206356 kb |
| Host | smart-00beeb69-932c-4b97-8652-64a3dbd7952d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3535753802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.3535753802 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3127014438 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1254881486 ps |
| CPU time | 26.85 seconds |
| Started | Jan 17 01:52:51 PM PST 24 |
| Finished | Jan 17 01:53:19 PM PST 24 |
| Peak memory | 204048 kb |
| Host | smart-811efab5-4239-4d99-b554-161afd9e5901 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3127014438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3127014438 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.3343836619 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1159739728 ps |
| CPU time | 27.94 seconds |
| Started | Jan 17 01:52:52 PM PST 24 |
| Finished | Jan 17 01:53:21 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-e25de62c-98ad-40da-bc73-830047e7824b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3343836619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3343836619 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.716141407 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 483986270 ps |
| CPU time | 13.98 seconds |
| Started | Jan 17 01:52:44 PM PST 24 |
| Finished | Jan 17 01:52:59 PM PST 24 |
| Peak memory | 211936 kb |
| Host | smart-d0a17410-adc2-4402-9e67-4b6aef5166ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=716141407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.716141407 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.742116283 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 114276106842 ps |
| CPU time | 249.13 seconds |
| Started | Jan 17 01:52:44 PM PST 24 |
| Finished | Jan 17 01:56:54 PM PST 24 |
| Peak memory | 211980 kb |
| Host | smart-5209ec67-ccd5-4a29-a71d-d827576ff0f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=742116283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.742116283 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3854863207 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 38767534346 ps |
| CPU time | 179.27 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:55:45 PM PST 24 |
| Peak memory | 205420 kb |
| Host | smart-7dcb0170-f891-44d0-a1ec-68630ae64a87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3854863207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3854863207 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.1522904803 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 17960913 ps |
| CPU time | 2.04 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:52:48 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-4fa6e22f-9ca8-45aa-a2dd-5504485f2004 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522904803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1522904803 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.3873109542 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 386867869 ps |
| CPU time | 8.85 seconds |
| Started | Jan 17 01:52:48 PM PST 24 |
| Finished | Jan 17 01:52:58 PM PST 24 |
| Peak memory | 204044 kb |
| Host | smart-f29f53bb-487d-45ac-a9c1-4ce3a0e73eb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3873109542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3873109542 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.1346168487 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 33095208 ps |
| CPU time | 1.78 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:52:48 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-867dc7bd-0bf7-4254-a59e-15cb26a1deb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1346168487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1346168487 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3461713924 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 3539092987 ps |
| CPU time | 22.97 seconds |
| Started | Jan 17 01:52:47 PM PST 24 |
| Finished | Jan 17 01:53:11 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-4f5dd855-1c17-437c-bcb0-ec78c2915d62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461713924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3461713924 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1042382365 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3781515931 ps |
| CPU time | 24.9 seconds |
| Started | Jan 17 01:52:45 PM PST 24 |
| Finished | Jan 17 01:53:10 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-acfffcdd-2c60-4716-8401-596af71d541b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1042382365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1042382365 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2640594754 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 24582974 ps |
| CPU time | 1.88 seconds |
| Started | Jan 17 01:52:48 PM PST 24 |
| Finished | Jan 17 01:52:51 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-2af53707-2750-4237-87e9-9531f29169ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640594754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2640594754 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.2716262033 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 6626987420 ps |
| CPU time | 193.47 seconds |
| Started | Jan 17 01:52:51 PM PST 24 |
| Finished | Jan 17 01:56:06 PM PST 24 |
| Peak memory | 210112 kb |
| Host | smart-e5d63525-6962-4c3a-b2a3-f5ff60d955c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2716262033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2716262033 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1356851795 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 455764234 ps |
| CPU time | 65.65 seconds |
| Started | Jan 17 01:52:53 PM PST 24 |
| Finished | Jan 17 01:53:59 PM PST 24 |
| Peak memory | 204864 kb |
| Host | smart-aeca8252-5a96-4268-a6d2-e395764ffbea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1356851795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1356851795 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1835149897 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1559079906 ps |
| CPU time | 58.11 seconds |
| Started | Jan 17 01:52:52 PM PST 24 |
| Finished | Jan 17 01:53:51 PM PST 24 |
| Peak memory | 207068 kb |
| Host | smart-1ca2cb6c-4ecc-4ae6-9ba4-6b8a68f6a00a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1835149897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.1835149897 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.952113149 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 87910067 ps |
| CPU time | 10.6 seconds |
| Started | Jan 17 01:52:54 PM PST 24 |
| Finished | Jan 17 01:53:06 PM PST 24 |
| Peak memory | 204484 kb |
| Host | smart-158decb0-2feb-4fbb-9e23-b54c43a9d9e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=952113149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_res et_error.952113149 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.2608305731 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 45613862 ps |
| CPU time | 6.48 seconds |
| Started | Jan 17 01:52:51 PM PST 24 |
| Finished | Jan 17 01:52:58 PM PST 24 |
| Peak memory | 205060 kb |
| Host | smart-011d3479-5bc6-4598-8c63-e02e5574a441 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2608305731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2608305731 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3590900132 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1551427232 ps |
| CPU time | 9 seconds |
| Started | Jan 17 01:52:50 PM PST 24 |
| Finished | Jan 17 01:53:00 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-8457737c-e2ff-4dfb-8593-cce4b26592bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3590900132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3590900132 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3025937373 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 117753031491 ps |
| CPU time | 253.4 seconds |
| Started | Jan 17 01:53:04 PM PST 24 |
| Finished | Jan 17 01:57:21 PM PST 24 |
| Peak memory | 206644 kb |
| Host | smart-16cd48ed-b547-4e22-81ae-8508fe3478af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3025937373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.3025937373 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.19717476 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 709755748 ps |
| CPU time | 23.64 seconds |
| Started | Jan 17 01:53:08 PM PST 24 |
| Finished | Jan 17 01:53:32 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-3eb36f4c-b8a1-4862-893b-697b7b227c80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=19717476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.19717476 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.1214163146 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 171523214 ps |
| CPU time | 4.8 seconds |
| Started | Jan 17 01:53:05 PM PST 24 |
| Finished | Jan 17 01:53:12 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-f60e7db0-53b6-4ab5-93b8-c739a92a5a11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1214163146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1214163146 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.1927143628 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1394591483 ps |
| CPU time | 48.97 seconds |
| Started | Jan 17 01:52:51 PM PST 24 |
| Finished | Jan 17 01:53:41 PM PST 24 |
| Peak memory | 211828 kb |
| Host | smart-8a5e3344-a93d-4a92-9ef1-239fd31e57a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1927143628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1927143628 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.580480984 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 48205976133 ps |
| CPU time | 237.18 seconds |
| Started | Jan 17 01:53:00 PM PST 24 |
| Finished | Jan 17 01:57:05 PM PST 24 |
| Peak memory | 205416 kb |
| Host | smart-c4d8b38d-f0f5-4185-a094-ed7d17a1c1e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=580480984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.580480984 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.216849951 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 59066506690 ps |
| CPU time | 217.01 seconds |
| Started | Jan 17 01:52:51 PM PST 24 |
| Finished | Jan 17 01:56:29 PM PST 24 |
| Peak memory | 205176 kb |
| Host | smart-e144b7ae-a30b-44c2-a5e1-c0f201be006c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=216849951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.216849951 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.902490181 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 50860117 ps |
| CPU time | 6.26 seconds |
| Started | Jan 17 01:52:54 PM PST 24 |
| Finished | Jan 17 01:53:02 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-58134e82-ebd9-410e-acc7-2ed13bb2d251 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902490181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.902490181 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.2016659803 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 862308606 ps |
| CPU time | 18.09 seconds |
| Started | Jan 17 01:53:08 PM PST 24 |
| Finished | Jan 17 01:53:27 PM PST 24 |
| Peak memory | 204164 kb |
| Host | smart-c6535d08-c477-4cda-bd0b-41f793699afb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2016659803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2016659803 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.2994852953 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 343211679 ps |
| CPU time | 3.31 seconds |
| Started | Jan 17 01:52:56 PM PST 24 |
| Finished | Jan 17 01:53:01 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-4eec8252-8f1d-438f-a102-5eeedf10ef78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2994852953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2994852953 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.164840983 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8714268054 ps |
| CPU time | 36.29 seconds |
| Started | Jan 17 01:52:56 PM PST 24 |
| Finished | Jan 17 01:53:34 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-bbfe7289-5989-4eb8-87eb-93c41757e530 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=164840983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.164840983 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1652632681 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2007799798 ps |
| CPU time | 19.47 seconds |
| Started | Jan 17 01:52:57 PM PST 24 |
| Finished | Jan 17 01:53:19 PM PST 24 |
| Peak memory | 203796 kb |
| Host | smart-49ae6b74-68e8-4713-85f6-7d57faeaa4da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1652632681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1652632681 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1838837765 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 24240888 ps |
| CPU time | 2.09 seconds |
| Started | Jan 17 01:52:54 PM PST 24 |
| Finished | Jan 17 01:52:57 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-e51e4434-25c9-407c-9e60-6261a7b51246 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838837765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1838837765 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1028323674 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 4989382791 ps |
| CPU time | 93.73 seconds |
| Started | Jan 17 01:53:03 PM PST 24 |
| Finished | Jan 17 01:54:41 PM PST 24 |
| Peak memory | 208224 kb |
| Host | smart-060092b4-1a71-4605-b6a2-33b97d39c1db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1028323674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1028323674 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2578885908 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1262338375 ps |
| CPU time | 75.35 seconds |
| Started | Jan 17 01:53:06 PM PST 24 |
| Finished | Jan 17 01:54:23 PM PST 24 |
| Peak memory | 206360 kb |
| Host | smart-3646dfd6-d86b-4d0f-a02b-ad79116b99e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2578885908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2578885908 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1344013224 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 13867900293 ps |
| CPU time | 454.35 seconds |
| Started | Jan 17 01:53:03 PM PST 24 |
| Finished | Jan 17 02:00:42 PM PST 24 |
| Peak memory | 220176 kb |
| Host | smart-2e9019b7-7616-4e86-bbb0-397afc15e949 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1344013224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1344013224 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1176408278 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 262454132 ps |
| CPU time | 10.85 seconds |
| Started | Jan 17 01:53:08 PM PST 24 |
| Finished | Jan 17 01:53:20 PM PST 24 |
| Peak memory | 211984 kb |
| Host | smart-a723fd33-de8a-446c-b782-c90d326d3ee8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1176408278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1176408278 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2841760876 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 666205521 ps |
| CPU time | 26.3 seconds |
| Started | Jan 17 01:53:03 PM PST 24 |
| Finished | Jan 17 01:53:34 PM PST 24 |
| Peak memory | 211908 kb |
| Host | smart-d13c9909-aa74-4bdb-bdc2-ca0a32e09dd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2841760876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2841760876 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1668257551 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 53200485631 ps |
| CPU time | 398.28 seconds |
| Started | Jan 17 01:53:16 PM PST 24 |
| Finished | Jan 17 01:59:55 PM PST 24 |
| Peak memory | 211976 kb |
| Host | smart-78f4baf7-0282-4082-8c1f-567297232231 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1668257551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.1668257551 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.4095810016 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 78115160 ps |
| CPU time | 11.59 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:53:42 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-43f55c05-1ee3-4126-8802-12fbf1b0a33b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4095810016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.4095810016 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.1981783007 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 160536972 ps |
| CPU time | 6.93 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:53:38 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-bef888a4-9097-4108-9113-20c86a97adc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1981783007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1981783007 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.2718014349 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1698885358 ps |
| CPU time | 11.46 seconds |
| Started | Jan 17 01:53:04 PM PST 24 |
| Finished | Jan 17 01:53:19 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-c60bcdb5-5361-4cbb-969b-7ff3b396ebeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2718014349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2718014349 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.473674156 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 19715990020 ps |
| CPU time | 50.24 seconds |
| Started | Jan 17 01:53:02 PM PST 24 |
| Finished | Jan 17 01:53:58 PM PST 24 |
| Peak memory | 211980 kb |
| Host | smart-3865653e-7260-4f4a-8a89-a23ecb6d3d4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=473674156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.473674156 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.882214772 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 7764883556 ps |
| CPU time | 54.06 seconds |
| Started | Jan 17 01:53:04 PM PST 24 |
| Finished | Jan 17 01:54:01 PM PST 24 |
| Peak memory | 211960 kb |
| Host | smart-17b7b053-7d7c-422d-8abf-dec38b3e1ae7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=882214772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.882214772 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.816921507 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 100959129 ps |
| CPU time | 10.03 seconds |
| Started | Jan 17 01:53:04 PM PST 24 |
| Finished | Jan 17 01:53:17 PM PST 24 |
| Peak memory | 211916 kb |
| Host | smart-eaef09b1-02e6-4f83-8256-e72c5db37312 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816921507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.816921507 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.291188062 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1567990224 ps |
| CPU time | 22.88 seconds |
| Started | Jan 17 01:53:18 PM PST 24 |
| Finished | Jan 17 01:53:41 PM PST 24 |
| Peak memory | 204040 kb |
| Host | smart-01029934-9749-40a5-bbef-6beffcb64db4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=291188062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.291188062 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.4234563551 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 290174515 ps |
| CPU time | 3.76 seconds |
| Started | Jan 17 01:53:03 PM PST 24 |
| Finished | Jan 17 01:53:11 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-c03043f0-8cbb-45d1-bc34-12a0b466e208 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4234563551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.4234563551 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2194245141 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 6517428033 ps |
| CPU time | 28.33 seconds |
| Started | Jan 17 01:53:05 PM PST 24 |
| Finished | Jan 17 01:53:36 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-3ff0ad8c-d8ce-4c09-a7a2-150277c0cdd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194245141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2194245141 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1431918763 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 7521319271 ps |
| CPU time | 41.07 seconds |
| Started | Jan 17 01:53:03 PM PST 24 |
| Finished | Jan 17 01:53:48 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-5fc42758-45eb-424f-a779-84a2886c5256 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1431918763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1431918763 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3806225614 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 84575265 ps |
| CPU time | 2.24 seconds |
| Started | Jan 17 01:53:08 PM PST 24 |
| Finished | Jan 17 01:53:11 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-19a0ccb8-4036-400a-a891-c40949c0825a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806225614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3806225614 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.631806013 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 829846128 ps |
| CPU time | 34.52 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:54:06 PM PST 24 |
| Peak memory | 206060 kb |
| Host | smart-b673464b-928c-4696-b078-033404522be7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=631806013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.631806013 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2891727723 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 864877474 ps |
| CPU time | 42.81 seconds |
| Started | Jan 17 01:53:18 PM PST 24 |
| Finished | Jan 17 01:54:02 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-23cf8301-0dba-4066-8c70-bacb11fb272d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2891727723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2891727723 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1491523246 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 95098050 ps |
| CPU time | 51.93 seconds |
| Started | Jan 17 01:53:17 PM PST 24 |
| Finished | Jan 17 01:54:10 PM PST 24 |
| Peak memory | 207588 kb |
| Host | smart-28ff07ad-23ad-4d3a-ae1c-d7d191f4e36f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1491523246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.1491523246 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2256498952 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 8955576109 ps |
| CPU time | 168.74 seconds |
| Started | Jan 17 01:53:18 PM PST 24 |
| Finished | Jan 17 01:56:08 PM PST 24 |
| Peak memory | 209352 kb |
| Host | smart-ff228fc1-1b0c-4f6c-9ed5-55707d8d05b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2256498952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.2256498952 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.4117788752 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 676997152 ps |
| CPU time | 25.38 seconds |
| Started | Jan 17 01:53:28 PM PST 24 |
| Finished | Jan 17 01:54:04 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-9cd599c9-5128-4906-85dc-0fe540a539dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4117788752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.4117788752 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3252107977 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2312003331 ps |
| CPU time | 23.36 seconds |
| Started | Jan 17 01:53:29 PM PST 24 |
| Finished | Jan 17 01:54:02 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-d659ad0b-2549-4297-9004-da24498fad9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3252107977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3252107977 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1342967625 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 85580450196 ps |
| CPU time | 707.54 seconds |
| Started | Jan 17 01:53:23 PM PST 24 |
| Finished | Jan 17 02:05:13 PM PST 24 |
| Peak memory | 207616 kb |
| Host | smart-e70bfdf9-0f48-40ed-9209-010c4974ff1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1342967625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.1342967625 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2684391200 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 145613529 ps |
| CPU time | 19.33 seconds |
| Started | Jan 17 01:53:26 PM PST 24 |
| Finished | Jan 17 01:53:50 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-240ac4ba-b089-4394-9b2a-e37b52c4f0cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2684391200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2684391200 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.3258708549 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 90726802 ps |
| CPU time | 9.17 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:53:40 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-37f47b91-747b-428b-9d9d-736c69aaf3e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3258708549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3258708549 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.209986237 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 204298868 ps |
| CPU time | 23.96 seconds |
| Started | Jan 17 01:53:28 PM PST 24 |
| Finished | Jan 17 01:54:02 PM PST 24 |
| Peak memory | 211876 kb |
| Host | smart-307d9862-7129-4f43-9afe-ef3cb17a4812 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=209986237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.209986237 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2733626890 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 29945203916 ps |
| CPU time | 213.69 seconds |
| Started | Jan 17 01:53:28 PM PST 24 |
| Finished | Jan 17 01:57:12 PM PST 24 |
| Peak memory | 205008 kb |
| Host | smart-12e831b0-e7de-48d0-96bf-097021632203 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733626890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2733626890 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.879892153 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 30054552997 ps |
| CPU time | 240.95 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:57:32 PM PST 24 |
| Peak memory | 212008 kb |
| Host | smart-3e017637-5444-4733-8fed-31d3ebe1ebd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=879892153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.879892153 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2797867244 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 72498841 ps |
| CPU time | 2.27 seconds |
| Started | Jan 17 01:53:28 PM PST 24 |
| Finished | Jan 17 01:53:40 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-bba4a794-7764-4f28-823a-c0a56978af21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797867244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2797867244 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.3026674278 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 285427429 ps |
| CPU time | 6.03 seconds |
| Started | Jan 17 01:53:28 PM PST 24 |
| Finished | Jan 17 01:53:44 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-3256294f-c4dd-4e9e-8c7e-809cb9ab1cd3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3026674278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3026674278 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.471532151 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 400425702 ps |
| CPU time | 2.95 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:53:34 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-e42e9f2b-4d19-465d-9cf6-4865fe13a871 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=471532151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.471532151 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1683232875 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 4921655634 ps |
| CPU time | 28.66 seconds |
| Started | Jan 17 01:53:19 PM PST 24 |
| Finished | Jan 17 01:53:48 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-a52eb039-8456-4a96-8037-6b6e96e34f0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683232875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1683232875 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3590792470 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5753452968 ps |
| CPU time | 20.22 seconds |
| Started | Jan 17 01:53:19 PM PST 24 |
| Finished | Jan 17 01:53:40 PM PST 24 |
| Peak memory | 203864 kb |
| Host | smart-2415aa6e-ac7c-4609-9876-fa88d00f7ea0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3590792470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3590792470 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2992108770 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 61737021 ps |
| CPU time | 2.56 seconds |
| Started | Jan 17 01:53:17 PM PST 24 |
| Finished | Jan 17 01:53:20 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-62f9b726-362a-40eb-a26c-51d3086f4eb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992108770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2992108770 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.2448742415 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 3335513841 ps |
| CPU time | 75.49 seconds |
| Started | Jan 17 01:53:26 PM PST 24 |
| Finished | Jan 17 01:54:45 PM PST 24 |
| Peak memory | 207252 kb |
| Host | smart-702dd031-8adb-4975-888f-8eedeef0ed35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2448742415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2448742415 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3499796092 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2896895115 ps |
| CPU time | 67.74 seconds |
| Started | Jan 17 01:53:28 PM PST 24 |
| Finished | Jan 17 01:54:46 PM PST 24 |
| Peak memory | 206008 kb |
| Host | smart-5cd37b47-a7b6-4a1b-bfa3-7f117cd6bb1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3499796092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3499796092 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.784726858 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 12763955734 ps |
| CPU time | 363.3 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:59:35 PM PST 24 |
| Peak memory | 220212 kb |
| Host | smart-9832bbf9-ca8f-45ba-92d1-7b7b1fe640fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=784726858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand _reset.784726858 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1473789268 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3627427044 ps |
| CPU time | 252.26 seconds |
| Started | Jan 17 01:53:28 PM PST 24 |
| Finished | Jan 17 01:57:50 PM PST 24 |
| Peak memory | 212012 kb |
| Host | smart-ee2e014f-334e-4e29-b032-902fbc6c2b17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1473789268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.1473789268 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3925609393 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 167869948 ps |
| CPU time | 22.3 seconds |
| Started | Jan 17 01:53:22 PM PST 24 |
| Finished | Jan 17 01:53:46 PM PST 24 |
| Peak memory | 211828 kb |
| Host | smart-c03c6300-754e-4921-bb3e-c2becdee3364 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3925609393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3925609393 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.649316888 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3336990425 ps |
| CPU time | 32.11 seconds |
| Started | Jan 17 01:49:36 PM PST 24 |
| Finished | Jan 17 01:50:10 PM PST 24 |
| Peak memory | 212004 kb |
| Host | smart-348196cd-ea6b-4b0b-914f-77d9aa0206cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=649316888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.649316888 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1585106509 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 509676814 ps |
| CPU time | 5.76 seconds |
| Started | Jan 17 01:49:29 PM PST 24 |
| Finished | Jan 17 01:49:35 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-abc63459-93e7-4757-84f5-24cbde03c376 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1585106509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1585106509 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3193691159 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1597632246 ps |
| CPU time | 11.3 seconds |
| Started | Jan 17 01:49:31 PM PST 24 |
| Finished | Jan 17 01:49:43 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-9fa5bf09-9247-47e8-9c40-ba9f553ab385 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3193691159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3193691159 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.640258298 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 184678500 ps |
| CPU time | 7.56 seconds |
| Started | Jan 17 01:49:31 PM PST 24 |
| Finished | Jan 17 01:49:39 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-171efc00-e4d4-4dc0-bc5c-0fc771e9fb4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=640258298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.640258298 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1851601426 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 53241796634 ps |
| CPU time | 156.32 seconds |
| Started | Jan 17 01:49:30 PM PST 24 |
| Finished | Jan 17 01:52:07 PM PST 24 |
| Peak memory | 205320 kb |
| Host | smart-a3582e90-9a25-446e-a9b8-814e2b92c915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851601426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1851601426 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3355780065 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 21142597175 ps |
| CPU time | 163.97 seconds |
| Started | Jan 17 01:49:35 PM PST 24 |
| Finished | Jan 17 01:52:22 PM PST 24 |
| Peak memory | 212168 kb |
| Host | smart-f42ab70e-361e-4135-86db-f3c97d10d175 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3355780065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3355780065 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.579643259 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 343089354 ps |
| CPU time | 23.65 seconds |
| Started | Jan 17 01:49:34 PM PST 24 |
| Finished | Jan 17 01:50:01 PM PST 24 |
| Peak memory | 204872 kb |
| Host | smart-02335100-0a31-4338-a820-15b30513d219 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579643259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.579643259 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.811489648 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 116268345 ps |
| CPU time | 2.46 seconds |
| Started | Jan 17 01:49:31 PM PST 24 |
| Finished | Jan 17 01:49:33 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-04e499ec-1fda-4627-bbc6-e42e520aed3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=811489648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.811489648 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2429879504 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 368609571 ps |
| CPU time | 4.07 seconds |
| Started | Jan 17 01:49:35 PM PST 24 |
| Finished | Jan 17 01:49:42 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-b83c3734-12fb-4bce-9233-fecfa226dd79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2429879504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2429879504 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3295353947 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 4681537185 ps |
| CPU time | 29.83 seconds |
| Started | Jan 17 01:49:34 PM PST 24 |
| Finished | Jan 17 01:50:07 PM PST 24 |
| Peak memory | 203868 kb |
| Host | smart-577bae34-4729-49fa-b920-ac982116d254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295353947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3295353947 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.170459582 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2576114637 ps |
| CPU time | 23.92 seconds |
| Started | Jan 17 01:49:29 PM PST 24 |
| Finished | Jan 17 01:49:53 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-b6c26e9f-0c58-4e0c-966b-02fa88206a02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=170459582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.170459582 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.924597697 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 29442337 ps |
| CPU time | 2.3 seconds |
| Started | Jan 17 01:49:35 PM PST 24 |
| Finished | Jan 17 01:49:40 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-393257b1-47aa-4b19-8bc1-5c205bc72048 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924597697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.924597697 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.766312051 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1682317775 ps |
| CPU time | 41.94 seconds |
| Started | Jan 17 01:49:32 PM PST 24 |
| Finished | Jan 17 01:50:15 PM PST 24 |
| Peak memory | 206136 kb |
| Host | smart-021732f2-84c4-47e9-bc94-17fa21ac267e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=766312051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.766312051 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1740167447 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 6379522958 ps |
| CPU time | 156.09 seconds |
| Started | Jan 17 01:49:39 PM PST 24 |
| Finished | Jan 17 01:52:17 PM PST 24 |
| Peak memory | 209040 kb |
| Host | smart-6627a0fb-eef2-4564-83ac-6f759cdeb886 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1740167447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1740167447 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1986631381 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1733817426 ps |
| CPU time | 443.48 seconds |
| Started | Jan 17 01:49:35 PM PST 24 |
| Finished | Jan 17 01:57:01 PM PST 24 |
| Peak memory | 209560 kb |
| Host | smart-5402a5d3-c248-4b3e-884b-d09c9c1e75fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1986631381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.1986631381 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.1608752859 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 11457891041 ps |
| CPU time | 233.42 seconds |
| Started | Jan 17 01:49:39 PM PST 24 |
| Finished | Jan 17 01:53:34 PM PST 24 |
| Peak memory | 222188 kb |
| Host | smart-91a2a6d2-ea6d-44bd-9b80-a3e7792dbcec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1608752859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.1608752859 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2404055775 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3799205449 ps |
| CPU time | 25.62 seconds |
| Started | Jan 17 01:49:31 PM PST 24 |
| Finished | Jan 17 01:49:58 PM PST 24 |
| Peak memory | 205208 kb |
| Host | smart-6830d8e2-3b4c-412a-b01d-c3e64c9de922 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2404055775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2404055775 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3128563680 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 780397793 ps |
| CPU time | 10.93 seconds |
| Started | Jan 17 01:53:24 PM PST 24 |
| Finished | Jan 17 01:53:38 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-ff849b49-5947-4496-a361-9b689b46aed0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3128563680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3128563680 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3774544364 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 36835903772 ps |
| CPU time | 156.83 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:56:15 PM PST 24 |
| Peak memory | 212028 kb |
| Host | smart-07ad1f7e-e985-48b9-9fd9-f311142303ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3774544364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.3774544364 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2817957585 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 355128561 ps |
| CPU time | 14.33 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:53:45 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-cfa4aeb8-484a-4480-b9f1-e9199cd506b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2817957585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2817957585 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.555461465 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 72502097 ps |
| CPU time | 5.34 seconds |
| Started | Jan 17 01:53:25 PM PST 24 |
| Finished | Jan 17 01:53:33 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-137aabb3-a706-4351-b332-aacbe9eca4b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=555461465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.555461465 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.2836774953 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 289873728 ps |
| CPU time | 9.87 seconds |
| Started | Jan 17 01:53:29 PM PST 24 |
| Finished | Jan 17 01:53:49 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-654a00c1-7f1d-4044-9630-4953b5efe45b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2836774953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2836774953 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1593614137 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 270259459707 ps |
| CPU time | 415.17 seconds |
| Started | Jan 17 01:53:32 PM PST 24 |
| Finished | Jan 17 02:00:36 PM PST 24 |
| Peak memory | 212004 kb |
| Host | smart-5e6c23f9-313c-4440-8032-cb95891be390 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593614137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1593614137 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3150933978 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 7286489045 ps |
| CPU time | 45.26 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:54:16 PM PST 24 |
| Peak memory | 212032 kb |
| Host | smart-b4e1118d-a90b-4a1d-b76a-a65b94561168 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3150933978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3150933978 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3356418723 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 168828508 ps |
| CPU time | 26.62 seconds |
| Started | Jan 17 01:53:24 PM PST 24 |
| Finished | Jan 17 01:53:54 PM PST 24 |
| Peak memory | 205044 kb |
| Host | smart-4ae43c5e-0509-4603-9775-0e6afd35f457 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356418723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3356418723 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.51934006 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 339679884 ps |
| CPU time | 3.16 seconds |
| Started | Jan 17 01:53:25 PM PST 24 |
| Finished | Jan 17 01:53:31 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-58549086-6f19-4870-bed2-671571edd6b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=51934006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.51934006 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.2149517254 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 46723094 ps |
| CPU time | 2.19 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:53:33 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-1d73c3b2-52ae-441f-9528-11171e1080e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2149517254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2149517254 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.3649425058 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 12860704125 ps |
| CPU time | 30.11 seconds |
| Started | Jan 17 01:53:32 PM PST 24 |
| Finished | Jan 17 01:54:10 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-45b336f3-a753-4ef1-8d06-f4fec713ecc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649425058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3649425058 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1122276218 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 11327713018 ps |
| CPU time | 34.81 seconds |
| Started | Jan 17 01:53:28 PM PST 24 |
| Finished | Jan 17 01:54:13 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-e7a2f63e-fbde-4549-b1e6-12710ebe9244 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1122276218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1122276218 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3082477142 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 29678250 ps |
| CPU time | 2.38 seconds |
| Started | Jan 17 01:53:27 PM PST 24 |
| Finished | Jan 17 01:53:39 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-dd8cc107-2f11-4d55-a0c6-35727d8ad2a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082477142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3082477142 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.1909524459 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2170061963 ps |
| CPU time | 73.41 seconds |
| Started | Jan 17 01:53:34 PM PST 24 |
| Finished | Jan 17 01:54:54 PM PST 24 |
| Peak memory | 206152 kb |
| Host | smart-b623352a-231a-4e99-b52a-227d4762350a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1909524459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1909524459 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1763819585 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 743668364 ps |
| CPU time | 63.31 seconds |
| Started | Jan 17 01:53:34 PM PST 24 |
| Finished | Jan 17 01:54:44 PM PST 24 |
| Peak memory | 204320 kb |
| Host | smart-75d34bb7-8fee-4717-9998-e6de6b89ef0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1763819585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1763819585 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3799162968 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 854197958 ps |
| CPU time | 203.73 seconds |
| Started | Jan 17 01:53:36 PM PST 24 |
| Finished | Jan 17 01:57:04 PM PST 24 |
| Peak memory | 209100 kb |
| Host | smart-03e69edd-9ba0-49f2-9ffb-d9ef48e0df22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3799162968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.3799162968 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.357602433 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1446117129 ps |
| CPU time | 241.34 seconds |
| Started | Jan 17 01:53:35 PM PST 24 |
| Finished | Jan 17 01:57:42 PM PST 24 |
| Peak memory | 220160 kb |
| Host | smart-4f11860b-53aa-4ac6-9cab-b23a2a0de3c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=357602433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res et_error.357602433 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3644017511 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1001131501 ps |
| CPU time | 25.3 seconds |
| Started | Jan 17 01:53:33 PM PST 24 |
| Finished | Jan 17 01:54:06 PM PST 24 |
| Peak memory | 204880 kb |
| Host | smart-5ce01961-0a0a-4e1e-9049-58dd8177ee6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3644017511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3644017511 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1037121678 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 440032861 ps |
| CPU time | 12.16 seconds |
| Started | Jan 17 01:53:34 PM PST 24 |
| Finished | Jan 17 01:53:53 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-571fd6aa-ed34-41ae-ac4d-4e478b70ecc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1037121678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1037121678 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3743946862 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 10951630725 ps |
| CPU time | 44.87 seconds |
| Started | Jan 17 01:53:34 PM PST 24 |
| Finished | Jan 17 01:54:25 PM PST 24 |
| Peak memory | 204992 kb |
| Host | smart-11caa2fa-16c9-4c09-8e28-897b23fc07a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3743946862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.3743946862 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.4942569 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 388220705 ps |
| CPU time | 19.62 seconds |
| Started | Jan 17 01:53:38 PM PST 24 |
| Finished | Jan 17 01:54:00 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-d7c7f6e9-44e0-43ae-9220-60ab847cd5d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4942569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.4942569 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.123621618 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 67689328 ps |
| CPU time | 6.36 seconds |
| Started | Jan 17 01:53:39 PM PST 24 |
| Finished | Jan 17 01:53:48 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-74e901ed-45b3-4fcf-a9f1-b01fccc7376d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=123621618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.123621618 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.4200979923 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 137102626 ps |
| CPU time | 4.95 seconds |
| Started | Jan 17 01:53:33 PM PST 24 |
| Finished | Jan 17 01:53:45 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-8b82750d-b2f6-4aa6-9b60-9c919ef95d41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4200979923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.4200979923 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.234295710 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3228707661 ps |
| CPU time | 14.59 seconds |
| Started | Jan 17 01:53:40 PM PST 24 |
| Finished | Jan 17 01:53:56 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-17f4b691-a84c-4c4f-9fc3-be66df1a7820 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=234295710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.234295710 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3455660401 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 104843172519 ps |
| CPU time | 278.57 seconds |
| Started | Jan 17 01:53:37 PM PST 24 |
| Finished | Jan 17 01:58:19 PM PST 24 |
| Peak memory | 211976 kb |
| Host | smart-fe6ef2db-3bf3-48dc-bfee-3dc51428b311 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3455660401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3455660401 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3814599514 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 245769885 ps |
| CPU time | 11.32 seconds |
| Started | Jan 17 01:53:34 PM PST 24 |
| Finished | Jan 17 01:53:52 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-6481e198-9532-4f2f-a7c9-dc1de06a8e46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814599514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3814599514 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.2366935888 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 3035503803 ps |
| CPU time | 36.4 seconds |
| Started | Jan 17 01:53:40 PM PST 24 |
| Finished | Jan 17 01:54:18 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-5e76c1e0-ac49-46c8-96a6-28b94c809d79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2366935888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2366935888 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.4172037992 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 54525862 ps |
| CPU time | 2.29 seconds |
| Started | Jan 17 01:53:35 PM PST 24 |
| Finished | Jan 17 01:53:43 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-85362da3-b469-47cb-ad72-3c52206f54a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172037992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.4172037992 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.1305062380 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 5887385131 ps |
| CPU time | 32.92 seconds |
| Started | Jan 17 01:53:35 PM PST 24 |
| Finished | Jan 17 01:54:13 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-5dcfacbd-6046-4070-a1bf-f1809e551e8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305062380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1305062380 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1427456243 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1981044440 ps |
| CPU time | 19.12 seconds |
| Started | Jan 17 01:53:35 PM PST 24 |
| Finished | Jan 17 01:54:00 PM PST 24 |
| Peak memory | 203616 kb |
| Host | smart-f5a9e955-8eac-484e-a06e-b20bf8f7eb90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1427456243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1427456243 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.420285412 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 68103556 ps |
| CPU time | 2.16 seconds |
| Started | Jan 17 01:53:35 PM PST 24 |
| Finished | Jan 17 01:53:43 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-301b82b9-162f-454a-9a94-717b024e68e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420285412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.420285412 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.2692482514 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 394131316 ps |
| CPU time | 10.14 seconds |
| Started | Jan 17 01:53:39 PM PST 24 |
| Finished | Jan 17 01:53:51 PM PST 24 |
| Peak memory | 205164 kb |
| Host | smart-96afe8d3-08af-4663-a60f-205a79143018 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2692482514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2692482514 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1501581332 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3361166808 ps |
| CPU time | 30.48 seconds |
| Started | Jan 17 01:53:36 PM PST 24 |
| Finished | Jan 17 01:54:11 PM PST 24 |
| Peak memory | 203840 kb |
| Host | smart-6d4aa7a7-06f6-42f9-a6b9-b03ceda67727 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1501581332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1501581332 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.937475246 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 11808755135 ps |
| CPU time | 333.29 seconds |
| Started | Jan 17 01:53:35 PM PST 24 |
| Finished | Jan 17 01:59:14 PM PST 24 |
| Peak memory | 210840 kb |
| Host | smart-0fb08937-68dc-4dff-ba2a-254a618c81a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=937475246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand _reset.937475246 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2288598308 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 593346709 ps |
| CPU time | 186.58 seconds |
| Started | Jan 17 01:53:36 PM PST 24 |
| Finished | Jan 17 01:56:47 PM PST 24 |
| Peak memory | 210724 kb |
| Host | smart-90212453-1dcc-41a0-b723-78c3301417f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2288598308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.2288598308 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.4075342126 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 106670185 ps |
| CPU time | 10.08 seconds |
| Started | Jan 17 01:53:38 PM PST 24 |
| Finished | Jan 17 01:53:51 PM PST 24 |
| Peak memory | 211868 kb |
| Host | smart-8be59e59-d356-4719-a37c-9daa9b424045 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4075342126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.4075342126 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1902420344 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 223557602 ps |
| CPU time | 16.89 seconds |
| Started | Jan 17 01:53:35 PM PST 24 |
| Finished | Jan 17 01:53:57 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-3c32d3ef-16ba-4f93-8a3f-a92f19bd53d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1902420344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1902420344 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.4003251439 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 80445643882 ps |
| CPU time | 608.28 seconds |
| Started | Jan 17 01:53:38 PM PST 24 |
| Finished | Jan 17 02:03:49 PM PST 24 |
| Peak memory | 206768 kb |
| Host | smart-a4e6406c-a3c1-4392-9b46-b772028b4ad6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4003251439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.4003251439 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.1900596333 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 95696305 ps |
| CPU time | 9.61 seconds |
| Started | Jan 17 01:53:37 PM PST 24 |
| Finished | Jan 17 01:53:50 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-9a768f76-ab32-4fce-b786-47375e86f119 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1900596333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.1900596333 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.613594425 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 114212944 ps |
| CPU time | 2.57 seconds |
| Started | Jan 17 01:53:35 PM PST 24 |
| Finished | Jan 17 01:53:43 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-0969d1f5-68f2-4860-a82f-4c4e032e8bff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=613594425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.613594425 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.2342354125 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 48577576 ps |
| CPU time | 4.92 seconds |
| Started | Jan 17 01:53:36 PM PST 24 |
| Finished | Jan 17 01:53:45 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-3b6454d1-1e1a-4247-8550-4bceffd8a722 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2342354125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2342354125 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3088081957 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4694419270 ps |
| CPU time | 24.82 seconds |
| Started | Jan 17 01:53:35 PM PST 24 |
| Finished | Jan 17 01:54:05 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-49b93d6f-ab2d-416d-a041-438c39ab68a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088081957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3088081957 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2803812573 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 168959712629 ps |
| CPU time | 302.34 seconds |
| Started | Jan 17 01:53:39 PM PST 24 |
| Finished | Jan 17 01:58:44 PM PST 24 |
| Peak memory | 205060 kb |
| Host | smart-02624154-28a0-46af-b9dc-a2c1572cc3d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2803812573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2803812573 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.773411788 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 673854585 ps |
| CPU time | 22.96 seconds |
| Started | Jan 17 01:53:35 PM PST 24 |
| Finished | Jan 17 01:54:03 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-95dad952-db32-487d-a768-c12dd03dd49d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773411788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.773411788 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.400083649 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 360871557 ps |
| CPU time | 7.36 seconds |
| Started | Jan 17 01:53:40 PM PST 24 |
| Finished | Jan 17 01:53:49 PM PST 24 |
| Peak memory | 203984 kb |
| Host | smart-dbd4fda9-987f-4549-aac4-e833b9468617 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=400083649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.400083649 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.152881903 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 136751031 ps |
| CPU time | 3.75 seconds |
| Started | Jan 17 01:53:36 PM PST 24 |
| Finished | Jan 17 01:53:44 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-c254d6d9-2f0d-418c-b638-2525cb34deae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=152881903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.152881903 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.119426113 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 6918239969 ps |
| CPU time | 28.78 seconds |
| Started | Jan 17 01:53:38 PM PST 24 |
| Finished | Jan 17 01:54:10 PM PST 24 |
| Peak memory | 203792 kb |
| Host | smart-f314ef05-8632-4225-bee9-738a3594897a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=119426113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.119426113 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2120867879 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2694656520 ps |
| CPU time | 27.17 seconds |
| Started | Jan 17 01:53:37 PM PST 24 |
| Finished | Jan 17 01:54:08 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-7714b23a-c3e4-41e4-8b97-b281bd1ada55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2120867879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2120867879 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3367655603 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 29060410 ps |
| CPU time | 2.03 seconds |
| Started | Jan 17 01:53:36 PM PST 24 |
| Finished | Jan 17 01:53:43 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-9dca8249-b3bc-4cb8-b490-56ca738b7b50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367655603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3367655603 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.2395896910 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 550355239 ps |
| CPU time | 55.82 seconds |
| Started | Jan 17 01:53:38 PM PST 24 |
| Finished | Jan 17 01:54:36 PM PST 24 |
| Peak memory | 205088 kb |
| Host | smart-897e83ff-22ca-4997-8499-08a801e701e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2395896910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2395896910 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.1111547810 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1416198135 ps |
| CPU time | 123.79 seconds |
| Started | Jan 17 01:53:37 PM PST 24 |
| Finished | Jan 17 01:55:44 PM PST 24 |
| Peak memory | 205696 kb |
| Host | smart-cf1cb7da-25d8-4700-963c-cab519d256a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1111547810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1111547810 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.4268563633 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1362138360 ps |
| CPU time | 285.53 seconds |
| Started | Jan 17 01:53:36 PM PST 24 |
| Finished | Jan 17 01:58:26 PM PST 24 |
| Peak memory | 209732 kb |
| Host | smart-4f07f57e-9d5d-41d7-ae73-a33c41c2a680 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4268563633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.4268563633 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.831238409 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 3000161051 ps |
| CPU time | 216.64 seconds |
| Started | Jan 17 01:53:36 PM PST 24 |
| Finished | Jan 17 01:57:17 PM PST 24 |
| Peak memory | 220836 kb |
| Host | smart-ea7d57b8-8966-42a1-b6dd-ee8d8db67966 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=831238409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_res et_error.831238409 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.2262005283 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1429516335 ps |
| CPU time | 29.36 seconds |
| Started | Jan 17 01:53:36 PM PST 24 |
| Finished | Jan 17 01:54:10 PM PST 24 |
| Peak memory | 205052 kb |
| Host | smart-49f33108-5bac-4da5-b7b7-09101ff7bbf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2262005283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2262005283 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.364033850 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 14827615 ps |
| CPU time | 2.91 seconds |
| Started | Jan 17 01:53:36 PM PST 24 |
| Finished | Jan 17 01:53:44 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-e61e97fe-1d37-4be2-9231-6e970f766e1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=364033850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.364033850 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.894052518 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 86021157386 ps |
| CPU time | 455.36 seconds |
| Started | Jan 17 01:53:40 PM PST 24 |
| Finished | Jan 17 02:01:17 PM PST 24 |
| Peak memory | 206944 kb |
| Host | smart-9e52ad26-febc-435d-883c-154d04c77611 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=894052518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo w_rsp.894052518 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2972990884 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1194311663 ps |
| CPU time | 22.09 seconds |
| Started | Jan 17 01:53:44 PM PST 24 |
| Finished | Jan 17 01:54:07 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-001147a3-8e25-4397-bd24-2f98d5ac1e2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2972990884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2972990884 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.2141012444 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1099603537 ps |
| CPU time | 21.75 seconds |
| Started | Jan 17 01:53:45 PM PST 24 |
| Finished | Jan 17 01:54:07 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-180a3112-e0a9-4b6a-8d5f-a71b4f108b86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2141012444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2141012444 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.1369898179 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1187440156 ps |
| CPU time | 11.78 seconds |
| Started | Jan 17 01:53:38 PM PST 24 |
| Finished | Jan 17 01:53:53 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-1497d25a-4b06-4e45-a204-be42a44fa879 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1369898179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1369898179 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2831322797 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 174201202273 ps |
| CPU time | 239.7 seconds |
| Started | Jan 17 01:53:38 PM PST 24 |
| Finished | Jan 17 01:57:40 PM PST 24 |
| Peak memory | 211960 kb |
| Host | smart-cfdbb6fe-b3f5-472b-b287-36bfb1a137e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831322797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2831322797 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2801227767 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 43265604661 ps |
| CPU time | 224.88 seconds |
| Started | Jan 17 01:53:37 PM PST 24 |
| Finished | Jan 17 01:57:26 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-3de470e4-a8b4-4dce-b5da-3decbc2e706a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2801227767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2801227767 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3037941118 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 612331786 ps |
| CPU time | 21.74 seconds |
| Started | Jan 17 01:53:39 PM PST 24 |
| Finished | Jan 17 01:54:03 PM PST 24 |
| Peak memory | 204768 kb |
| Host | smart-07e081a7-88cd-4f6c-95d2-6c3d52521343 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037941118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3037941118 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.1559326985 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2044424902 ps |
| CPU time | 29.26 seconds |
| Started | Jan 17 01:53:37 PM PST 24 |
| Finished | Jan 17 01:54:10 PM PST 24 |
| Peak memory | 204208 kb |
| Host | smart-b4843aad-6e00-41c4-ac37-b27e5a13eab1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1559326985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1559326985 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.3403034963 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 27834516 ps |
| CPU time | 2.36 seconds |
| Started | Jan 17 01:53:39 PM PST 24 |
| Finished | Jan 17 01:53:44 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-6c8eb658-3b38-4748-8408-18e3a3712be3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3403034963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3403034963 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.473465470 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 5998505118 ps |
| CPU time | 25.45 seconds |
| Started | Jan 17 01:53:34 PM PST 24 |
| Finished | Jan 17 01:54:06 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-a3013f9a-1c1e-4045-ad7b-4fd2bc817862 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=473465470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.473465470 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2128648156 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 3160576077 ps |
| CPU time | 28.39 seconds |
| Started | Jan 17 01:53:34 PM PST 24 |
| Finished | Jan 17 01:54:09 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-d7357a67-53f7-454c-b3d3-18e0c1c0bad0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2128648156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2128648156 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3509650201 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 93635805 ps |
| CPU time | 2.18 seconds |
| Started | Jan 17 01:53:37 PM PST 24 |
| Finished | Jan 17 01:53:43 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-23a21daf-0a8c-4db3-b942-008bca8b3784 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509650201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3509650201 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.894088716 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 8089019849 ps |
| CPU time | 141.32 seconds |
| Started | Jan 17 01:53:47 PM PST 24 |
| Finished | Jan 17 01:56:08 PM PST 24 |
| Peak memory | 207536 kb |
| Host | smart-827df66a-0255-4378-80fe-6df06feacc0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=894088716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.894088716 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.47774282 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1691554580 ps |
| CPU time | 51.27 seconds |
| Started | Jan 17 01:53:45 PM PST 24 |
| Finished | Jan 17 01:54:37 PM PST 24 |
| Peak memory | 211948 kb |
| Host | smart-e2b1e7c7-5234-4b0f-b24e-0f656a176cb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=47774282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.47774282 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3257226546 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 189174986 ps |
| CPU time | 72.52 seconds |
| Started | Jan 17 01:53:45 PM PST 24 |
| Finished | Jan 17 01:54:58 PM PST 24 |
| Peak memory | 208756 kb |
| Host | smart-d98ea4ee-a210-4b05-8b1f-a9579a8cff47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3257226546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3257226546 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3550168165 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 124226742 ps |
| CPU time | 15.83 seconds |
| Started | Jan 17 01:53:48 PM PST 24 |
| Finished | Jan 17 01:54:05 PM PST 24 |
| Peak memory | 205316 kb |
| Host | smart-3c9f7f94-75a7-4f4c-8c9a-ba63623e19c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3550168165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3550168165 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3392547028 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 429247143 ps |
| CPU time | 19.5 seconds |
| Started | Jan 17 01:53:42 PM PST 24 |
| Finished | Jan 17 01:54:03 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-b355fb57-6a5c-452b-b182-0f145287c195 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3392547028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3392547028 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.2906897123 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 81923143715 ps |
| CPU time | 758.6 seconds |
| Started | Jan 17 01:53:42 PM PST 24 |
| Finished | Jan 17 02:06:22 PM PST 24 |
| Peak memory | 206212 kb |
| Host | smart-a8d07248-c31d-4eb2-97e7-843de50cd419 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2906897123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.2906897123 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1092469740 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 196895203 ps |
| CPU time | 21.51 seconds |
| Started | Jan 17 01:54:01 PM PST 24 |
| Finished | Jan 17 01:54:28 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-40f43ae2-88dd-476f-bae7-08c909445175 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1092469740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1092469740 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.1885913959 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 278539536 ps |
| CPU time | 16.88 seconds |
| Started | Jan 17 01:53:59 PM PST 24 |
| Finished | Jan 17 01:54:23 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-6ad2bbfb-3c79-4a62-9029-08fa7689ef19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1885913959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1885913959 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.319202694 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 237522765 ps |
| CPU time | 10.13 seconds |
| Started | Jan 17 01:53:44 PM PST 24 |
| Finished | Jan 17 01:53:55 PM PST 24 |
| Peak memory | 204376 kb |
| Host | smart-3a693ee7-3772-49a5-9616-a29765caa58f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=319202694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.319202694 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2366740424 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 19354138543 ps |
| CPU time | 101.86 seconds |
| Started | Jan 17 01:53:44 PM PST 24 |
| Finished | Jan 17 01:55:27 PM PST 24 |
| Peak memory | 211940 kb |
| Host | smart-d7cdc152-317d-4bdd-aacb-fe79e34d3991 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366740424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2366740424 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3745348266 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 8139989980 ps |
| CPU time | 46.52 seconds |
| Started | Jan 17 01:53:44 PM PST 24 |
| Finished | Jan 17 01:54:31 PM PST 24 |
| Peak memory | 211996 kb |
| Host | smart-a21e51cb-0870-4046-a2a2-8ebca10bc91b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3745348266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3745348266 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1853720255 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 192378141 ps |
| CPU time | 24.95 seconds |
| Started | Jan 17 01:53:42 PM PST 24 |
| Finished | Jan 17 01:54:08 PM PST 24 |
| Peak memory | 211916 kb |
| Host | smart-1177a0c4-287a-4efe-b164-c9f643ef83d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853720255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1853720255 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.794617208 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 203241254 ps |
| CPU time | 11.09 seconds |
| Started | Jan 17 01:53:42 PM PST 24 |
| Finished | Jan 17 01:53:54 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-f6914e2e-9c88-4833-9467-d01d6bf7204c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=794617208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.794617208 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.1524746849 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 40604764 ps |
| CPU time | 2.37 seconds |
| Started | Jan 17 01:53:43 PM PST 24 |
| Finished | Jan 17 01:53:46 PM PST 24 |
| Peak memory | 203692 kb |
| Host | smart-3310c890-ad96-4953-8fa4-3a1a585e4ba4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1524746849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1524746849 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.362409977 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 9722579851 ps |
| CPU time | 33.06 seconds |
| Started | Jan 17 01:53:45 PM PST 24 |
| Finished | Jan 17 01:54:19 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-d7704697-fec4-4fb1-a094-51f6d4876c03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=362409977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.362409977 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2212993373 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 8295764399 ps |
| CPU time | 29.13 seconds |
| Started | Jan 17 01:53:43 PM PST 24 |
| Finished | Jan 17 01:54:12 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-85adcc70-c805-4213-8f55-7246b85ce1d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2212993373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2212993373 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.3919972004 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 29300572 ps |
| CPU time | 2.41 seconds |
| Started | Jan 17 01:53:43 PM PST 24 |
| Finished | Jan 17 01:53:46 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-df65b440-9f31-4389-8d5b-d859c8d1debe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919972004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3919972004 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.4151128985 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 801970088 ps |
| CPU time | 33.75 seconds |
| Started | Jan 17 01:54:05 PM PST 24 |
| Finished | Jan 17 01:54:40 PM PST 24 |
| Peak memory | 206304 kb |
| Host | smart-26a5a68e-c3ca-46e5-9d40-df4593947f49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4151128985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4151128985 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1470036687 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1822142814 ps |
| CPU time | 162.81 seconds |
| Started | Jan 17 01:54:00 PM PST 24 |
| Finished | Jan 17 01:56:49 PM PST 24 |
| Peak memory | 211932 kb |
| Host | smart-6cc3a8de-2f13-47f5-8445-d033d4ca2459 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1470036687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1470036687 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.405920399 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1375131592 ps |
| CPU time | 279.1 seconds |
| Started | Jan 17 01:53:59 PM PST 24 |
| Finished | Jan 17 01:58:45 PM PST 24 |
| Peak memory | 210604 kb |
| Host | smart-10c5d34f-114a-40de-b162-fd17e8042952 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=405920399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand _reset.405920399 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.394551086 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 4240749641 ps |
| CPU time | 262.18 seconds |
| Started | Jan 17 01:54:02 PM PST 24 |
| Finished | Jan 17 01:58:28 PM PST 24 |
| Peak memory | 212064 kb |
| Host | smart-8b85d273-98c3-446b-802a-294e40e152f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=394551086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_res et_error.394551086 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3867379650 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 527175808 ps |
| CPU time | 27.84 seconds |
| Started | Jan 17 01:54:11 PM PST 24 |
| Finished | Jan 17 01:54:39 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-5041bad7-2be8-4d4d-bc21-994883f43134 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3867379650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3867379650 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.645006793 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 75229363220 ps |
| CPU time | 507.66 seconds |
| Started | Jan 17 01:54:08 PM PST 24 |
| Finished | Jan 17 02:02:37 PM PST 24 |
| Peak memory | 211952 kb |
| Host | smart-0a2bfcf4-b593-4457-a8d7-ab7f8559eee7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=645006793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo w_rsp.645006793 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3138565938 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 194575595 ps |
| CPU time | 3.75 seconds |
| Started | Jan 17 01:54:16 PM PST 24 |
| Finished | Jan 17 01:54:21 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-9fbeb7ca-19e1-4266-bd35-52f14b9ca1f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3138565938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3138565938 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.47788098 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 170743554 ps |
| CPU time | 13.97 seconds |
| Started | Jan 17 01:54:10 PM PST 24 |
| Finished | Jan 17 01:54:25 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-08b321f2-25ff-451b-9b68-991204e83780 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=47788098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.47788098 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.2232819397 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 67506049 ps |
| CPU time | 2.52 seconds |
| Started | Jan 17 01:53:58 PM PST 24 |
| Finished | Jan 17 01:54:01 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-71f641dd-26a9-46f0-980a-3f5ecedb0bf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2232819397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2232819397 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1113713924 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 65106518602 ps |
| CPU time | 245.57 seconds |
| Started | Jan 17 01:53:59 PM PST 24 |
| Finished | Jan 17 01:58:12 PM PST 24 |
| Peak memory | 211960 kb |
| Host | smart-9e017fbd-2080-4c8a-94b4-863005518a68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113713924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1113713924 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3670665784 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 10002311303 ps |
| CPU time | 33.16 seconds |
| Started | Jan 17 01:53:59 PM PST 24 |
| Finished | Jan 17 01:54:39 PM PST 24 |
| Peak memory | 212028 kb |
| Host | smart-77c8945d-fbde-4dc2-a934-7c13aab9b5d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3670665784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3670665784 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.951359736 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 203411106 ps |
| CPU time | 20.69 seconds |
| Started | Jan 17 01:53:58 PM PST 24 |
| Finished | Jan 17 01:54:25 PM PST 24 |
| Peak memory | 211924 kb |
| Host | smart-23b79333-d1e8-43f0-a54b-7cdba7a95e01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951359736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.951359736 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.2222940754 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2068280499 ps |
| CPU time | 20.85 seconds |
| Started | Jan 17 01:54:11 PM PST 24 |
| Finished | Jan 17 01:54:32 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-394ee3e9-61be-457f-b3d5-627b0fd33529 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2222940754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2222940754 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.2890907009 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 219843336 ps |
| CPU time | 3.51 seconds |
| Started | Jan 17 01:53:59 PM PST 24 |
| Finished | Jan 17 01:54:10 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-7654034d-3d5f-4df4-baeb-13477e2e3510 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2890907009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2890907009 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.4078100946 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 5905614846 ps |
| CPU time | 25.19 seconds |
| Started | Jan 17 01:54:02 PM PST 24 |
| Finished | Jan 17 01:54:31 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-8c90a8a3-c4d3-4d6c-b655-9db5c3c5ea1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078100946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.4078100946 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.4282914633 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3744450001 ps |
| CPU time | 36.78 seconds |
| Started | Jan 17 01:54:02 PM PST 24 |
| Finished | Jan 17 01:54:43 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-4d742c3f-d311-41e0-adbb-2ef0d6b48036 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4282914633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.4282914633 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1975260187 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 68435461 ps |
| CPU time | 2.68 seconds |
| Started | Jan 17 01:53:59 PM PST 24 |
| Finished | Jan 17 01:54:09 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-3925f20b-f7e1-44a9-b293-8646402e73fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975260187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1975260187 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.4018555984 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 1109630508 ps |
| CPU time | 110.88 seconds |
| Started | Jan 17 01:54:10 PM PST 24 |
| Finished | Jan 17 01:56:02 PM PST 24 |
| Peak memory | 208148 kb |
| Host | smart-1e9410ab-7b9f-464f-a658-e95cc4b8582b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4018555984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4018555984 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.290102229 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 16789984229 ps |
| CPU time | 223.62 seconds |
| Started | Jan 17 01:54:10 PM PST 24 |
| Finished | Jan 17 01:57:54 PM PST 24 |
| Peak memory | 209652 kb |
| Host | smart-89d1ac53-6707-4686-9005-e994b6ea4c27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=290102229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand _reset.290102229 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2338851016 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 232450528 ps |
| CPU time | 86.71 seconds |
| Started | Jan 17 01:54:10 PM PST 24 |
| Finished | Jan 17 01:55:37 PM PST 24 |
| Peak memory | 209104 kb |
| Host | smart-81591cfa-a33f-464b-badb-e678d014b82c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2338851016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.2338851016 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3498023276 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 200445354 ps |
| CPU time | 18.76 seconds |
| Started | Jan 17 01:54:12 PM PST 24 |
| Finished | Jan 17 01:54:32 PM PST 24 |
| Peak memory | 205540 kb |
| Host | smart-bebf2973-70cc-44e4-a436-50b72fd87def |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3498023276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3498023276 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3923946643 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1162543377 ps |
| CPU time | 48.12 seconds |
| Started | Jan 17 01:54:10 PM PST 24 |
| Finished | Jan 17 01:54:59 PM PST 24 |
| Peak memory | 206308 kb |
| Host | smart-8802fe81-bc40-41a3-b3b2-38ee18952a81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3923946643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3923946643 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1131222240 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 13931001934 ps |
| CPU time | 102.56 seconds |
| Started | Jan 17 01:54:11 PM PST 24 |
| Finished | Jan 17 01:55:54 PM PST 24 |
| Peak memory | 206212 kb |
| Host | smart-ea5e78df-0628-4d97-82d6-9082d5e4b55b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1131222240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.1131222240 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2121158252 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 560378980 ps |
| CPU time | 9.02 seconds |
| Started | Jan 17 01:54:09 PM PST 24 |
| Finished | Jan 17 01:54:19 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-fd7ff780-5aa4-4821-a94d-9ab598b594ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2121158252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2121158252 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.53382880 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2263959623 ps |
| CPU time | 18.37 seconds |
| Started | Jan 17 01:54:11 PM PST 24 |
| Finished | Jan 17 01:54:30 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-a1f67fea-aa24-425e-b891-7a02320a6615 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=53382880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.53382880 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.2225518936 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 134681769 ps |
| CPU time | 15.51 seconds |
| Started | Jan 17 01:54:10 PM PST 24 |
| Finished | Jan 17 01:54:27 PM PST 24 |
| Peak memory | 204840 kb |
| Host | smart-749c80b9-9e8d-4ed0-bf34-0bbd5cf36346 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2225518936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2225518936 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1902435724 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 52048417193 ps |
| CPU time | 266.01 seconds |
| Started | Jan 17 01:54:08 PM PST 24 |
| Finished | Jan 17 01:58:35 PM PST 24 |
| Peak memory | 212196 kb |
| Host | smart-cc809eb2-8839-49a1-96cf-cbb744d529c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902435724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1902435724 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2901372979 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 30063000021 ps |
| CPU time | 187.9 seconds |
| Started | Jan 17 01:54:12 PM PST 24 |
| Finished | Jan 17 01:57:21 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-39d4dadc-28c9-4196-9de6-feb44062d3da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2901372979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2901372979 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.871494138 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 126160162 ps |
| CPU time | 16.97 seconds |
| Started | Jan 17 01:54:16 PM PST 24 |
| Finished | Jan 17 01:54:34 PM PST 24 |
| Peak memory | 211980 kb |
| Host | smart-7ba3df67-05a6-4994-9c21-bd824631559f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871494138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.871494138 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.1132664320 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 344942467 ps |
| CPU time | 8.08 seconds |
| Started | Jan 17 01:54:10 PM PST 24 |
| Finished | Jan 17 01:54:19 PM PST 24 |
| Peak memory | 204084 kb |
| Host | smart-9742e5b2-3908-46a5-b90d-10b68bf331f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1132664320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1132664320 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.3154518515 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 137041251 ps |
| CPU time | 3.09 seconds |
| Started | Jan 17 01:54:12 PM PST 24 |
| Finished | Jan 17 01:54:16 PM PST 24 |
| Peak memory | 203796 kb |
| Host | smart-30c70f53-303e-4c26-9cef-fe882681d2a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3154518515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3154518515 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2063412400 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 21990146294 ps |
| CPU time | 33.03 seconds |
| Started | Jan 17 01:54:11 PM PST 24 |
| Finished | Jan 17 01:54:45 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-a8634150-c25f-4312-84b9-69d076653708 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063412400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2063412400 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2597824826 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 4897916438 ps |
| CPU time | 27.19 seconds |
| Started | Jan 17 01:54:10 PM PST 24 |
| Finished | Jan 17 01:54:38 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-7841a52a-9e35-4dc0-af51-e4f04994acee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2597824826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2597824826 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1700014887 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 35187465 ps |
| CPU time | 2.51 seconds |
| Started | Jan 17 01:54:12 PM PST 24 |
| Finished | Jan 17 01:54:15 PM PST 24 |
| Peak memory | 203748 kb |
| Host | smart-73a1b89c-1cf3-4fb3-8596-5939d9f9cb61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700014887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1700014887 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1491752811 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 3308323927 ps |
| CPU time | 68.47 seconds |
| Started | Jan 17 01:54:08 PM PST 24 |
| Finished | Jan 17 01:55:17 PM PST 24 |
| Peak memory | 208248 kb |
| Host | smart-93f31964-1f84-4067-90db-cbee0056e2b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1491752811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1491752811 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.184193217 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1521274921 ps |
| CPU time | 20 seconds |
| Started | Jan 17 01:54:12 PM PST 24 |
| Finished | Jan 17 01:54:32 PM PST 24 |
| Peak memory | 203852 kb |
| Host | smart-eb9d2d43-24bd-402c-8673-3056c38f4a23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=184193217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.184193217 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1356434521 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 246288380 ps |
| CPU time | 77.45 seconds |
| Started | Jan 17 01:54:11 PM PST 24 |
| Finished | Jan 17 01:55:29 PM PST 24 |
| Peak memory | 208400 kb |
| Host | smart-179b7ecd-5b99-46f6-82cf-a1bb9b047471 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1356434521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1356434521 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2179736523 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2744521141 ps |
| CPU time | 281.77 seconds |
| Started | Jan 17 01:54:17 PM PST 24 |
| Finished | Jan 17 01:59:00 PM PST 24 |
| Peak memory | 211996 kb |
| Host | smart-a5fcc7d7-8d90-40e6-83fb-c2aa5920c3d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2179736523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2179736523 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.4294863925 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 498764860 ps |
| CPU time | 21.97 seconds |
| Started | Jan 17 01:54:12 PM PST 24 |
| Finished | Jan 17 01:54:34 PM PST 24 |
| Peak memory | 205280 kb |
| Host | smart-6f9fa3c0-b2cf-46e9-b15a-d7092171e7a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4294863925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4294863925 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.3626782208 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 208091334 ps |
| CPU time | 25.18 seconds |
| Started | Jan 17 01:54:15 PM PST 24 |
| Finished | Jan 17 01:54:41 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-64a6077b-c9ba-4a54-92e6-d661a294b3a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3626782208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3626782208 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2233233531 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 77780552362 ps |
| CPU time | 631.7 seconds |
| Started | Jan 17 01:54:17 PM PST 24 |
| Finished | Jan 17 02:04:50 PM PST 24 |
| Peak memory | 206204 kb |
| Host | smart-6bcdf293-a6cc-443d-95e7-9dbe165b858e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2233233531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.2233233531 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.660154656 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 1570905811 ps |
| CPU time | 9.2 seconds |
| Started | Jan 17 01:54:21 PM PST 24 |
| Finished | Jan 17 01:54:31 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-1c03eb6f-8aac-455d-8283-84f0bd8af37f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=660154656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.660154656 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.866567017 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1822047541 ps |
| CPU time | 34.5 seconds |
| Started | Jan 17 01:54:18 PM PST 24 |
| Finished | Jan 17 01:54:55 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-eeed4de9-0499-401d-bc05-a81ce878087a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=866567017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.866567017 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.3182676507 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1049865265 ps |
| CPU time | 11.33 seconds |
| Started | Jan 17 01:54:17 PM PST 24 |
| Finished | Jan 17 01:54:30 PM PST 24 |
| Peak memory | 204496 kb |
| Host | smart-b7bab23e-27a5-48af-9768-346d15cd1477 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3182676507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3182676507 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.3935904912 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 67712032807 ps |
| CPU time | 203.62 seconds |
| Started | Jan 17 01:54:15 PM PST 24 |
| Finished | Jan 17 01:57:40 PM PST 24 |
| Peak memory | 211944 kb |
| Host | smart-8cd1cbe7-d977-4348-884d-d003070a2be3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935904912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3935904912 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3834041493 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6756688536 ps |
| CPU time | 58.59 seconds |
| Started | Jan 17 01:54:13 PM PST 24 |
| Finished | Jan 17 01:55:12 PM PST 24 |
| Peak memory | 211880 kb |
| Host | smart-73d26344-8f8e-462e-930e-b9f4c09c6fea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3834041493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3834041493 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2354303897 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 143680368 ps |
| CPU time | 7.67 seconds |
| Started | Jan 17 01:54:17 PM PST 24 |
| Finished | Jan 17 01:54:25 PM PST 24 |
| Peak memory | 204384 kb |
| Host | smart-370b5359-6a01-4f45-a55e-936739079be1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354303897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2354303897 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.2256019105 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 71476467 ps |
| CPU time | 4.69 seconds |
| Started | Jan 17 01:54:14 PM PST 24 |
| Finished | Jan 17 01:54:19 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-4663d64f-c346-4815-a3fe-2dc30f2cd875 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2256019105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2256019105 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.3704789355 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 192672990 ps |
| CPU time | 3.05 seconds |
| Started | Jan 17 01:54:11 PM PST 24 |
| Finished | Jan 17 01:54:15 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-8622f9c9-7747-47c1-9604-ca2ebbc13335 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3704789355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3704789355 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2830258559 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 8576440239 ps |
| CPU time | 31.11 seconds |
| Started | Jan 17 01:54:17 PM PST 24 |
| Finished | Jan 17 01:54:48 PM PST 24 |
| Peak memory | 203868 kb |
| Host | smart-f616dfcf-1622-41b3-a84c-16bc2083a89a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830258559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2830258559 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2634604389 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 5945161637 ps |
| CPU time | 29.56 seconds |
| Started | Jan 17 01:54:13 PM PST 24 |
| Finished | Jan 17 01:54:43 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-2eeabbf4-74f3-43ce-b238-c24c606a7fc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2634604389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2634604389 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1838767389 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 125606371 ps |
| CPU time | 2.19 seconds |
| Started | Jan 17 01:54:17 PM PST 24 |
| Finished | Jan 17 01:54:21 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-882076f7-6761-4b6b-b3c2-c917da708775 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838767389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1838767389 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2097364995 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 613524417 ps |
| CPU time | 41.24 seconds |
| Started | Jan 17 01:54:23 PM PST 24 |
| Finished | Jan 17 01:55:05 PM PST 24 |
| Peak memory | 206348 kb |
| Host | smart-27a62c91-a4d7-43a6-a10b-3558a683ec9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2097364995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2097364995 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2951674838 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 27422195851 ps |
| CPU time | 179.08 seconds |
| Started | Jan 17 01:54:21 PM PST 24 |
| Finished | Jan 17 01:57:21 PM PST 24 |
| Peak memory | 206944 kb |
| Host | smart-e98ea79c-c00b-4608-b766-fa7bbf15cff2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2951674838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2951674838 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.889165389 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 70712928 ps |
| CPU time | 18.83 seconds |
| Started | Jan 17 01:54:23 PM PST 24 |
| Finished | Jan 17 01:54:43 PM PST 24 |
| Peak memory | 206276 kb |
| Host | smart-e2853d14-5b6d-4ae0-ad5a-585e24b44426 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=889165389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand _reset.889165389 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.2426175904 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 766589118 ps |
| CPU time | 177.99 seconds |
| Started | Jan 17 01:54:28 PM PST 24 |
| Finished | Jan 17 01:57:30 PM PST 24 |
| Peak memory | 211124 kb |
| Host | smart-8e231b58-1536-47a4-8343-fe36768908b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2426175904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.2426175904 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1461337628 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 243727917 ps |
| CPU time | 7.8 seconds |
| Started | Jan 17 01:54:16 PM PST 24 |
| Finished | Jan 17 01:54:25 PM PST 24 |
| Peak memory | 204952 kb |
| Host | smart-d63f1f67-c288-4ffd-b98e-9c08514b4e0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1461337628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1461337628 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2682448785 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1593207798 ps |
| CPU time | 60.04 seconds |
| Started | Jan 17 01:54:24 PM PST 24 |
| Finished | Jan 17 01:55:25 PM PST 24 |
| Peak memory | 206568 kb |
| Host | smart-e6cf1678-ff49-4d78-ba95-1c377b2bc8f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2682448785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2682448785 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1648679315 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 242328285680 ps |
| CPU time | 769.9 seconds |
| Started | Jan 17 01:54:21 PM PST 24 |
| Finished | Jan 17 02:07:12 PM PST 24 |
| Peak memory | 212020 kb |
| Host | smart-73200fe1-b61e-4cea-ae81-60ec6db1d146 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1648679315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.1648679315 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.817665844 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1635023578 ps |
| CPU time | 22.51 seconds |
| Started | Jan 17 01:54:31 PM PST 24 |
| Finished | Jan 17 01:54:59 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-e6d58852-5c08-4b97-bb65-979be1049358 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=817665844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.817665844 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.1008097963 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 633731688 ps |
| CPU time | 19.15 seconds |
| Started | Jan 17 01:54:28 PM PST 24 |
| Finished | Jan 17 01:54:51 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-8a90a4fc-5092-4265-8eca-1eb26586ad2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1008097963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1008097963 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.1868907040 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1104791034 ps |
| CPU time | 36.02 seconds |
| Started | Jan 17 01:54:28 PM PST 24 |
| Finished | Jan 17 01:55:08 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-aed5b9f8-2060-4ec1-9e19-75a3dc8e6303 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1868907040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1868907040 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2034241084 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 12776691036 ps |
| CPU time | 68.43 seconds |
| Started | Jan 17 01:54:28 PM PST 24 |
| Finished | Jan 17 01:55:40 PM PST 24 |
| Peak memory | 204832 kb |
| Host | smart-0181a642-a729-4e80-929e-cbf1dabb03ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034241084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2034241084 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2591840976 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 5421851965 ps |
| CPU time | 39.65 seconds |
| Started | Jan 17 01:54:20 PM PST 24 |
| Finished | Jan 17 01:55:01 PM PST 24 |
| Peak memory | 211996 kb |
| Host | smart-8dc513bc-ef5d-4894-bc0c-6a47e34111d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2591840976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2591840976 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.589473762 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 39228169 ps |
| CPU time | 2.35 seconds |
| Started | Jan 17 01:54:24 PM PST 24 |
| Finished | Jan 17 01:54:27 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-0a7ac74b-946a-4632-bf5d-d98fb06d25e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589473762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.589473762 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.3962959977 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 121529257 ps |
| CPU time | 9.29 seconds |
| Started | Jan 17 01:54:19 PM PST 24 |
| Finished | Jan 17 01:54:30 PM PST 24 |
| Peak memory | 204196 kb |
| Host | smart-95347577-7b60-4e44-9a9c-c6bfcbe134ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3962959977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3962959977 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.23481725 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 164119014 ps |
| CPU time | 3.84 seconds |
| Started | Jan 17 01:54:22 PM PST 24 |
| Finished | Jan 17 01:54:26 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-a5163e13-cb50-405a-a77b-bf5981ab6817 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=23481725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.23481725 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.484223758 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4856141080 ps |
| CPU time | 29.61 seconds |
| Started | Jan 17 01:54:22 PM PST 24 |
| Finished | Jan 17 01:54:53 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-ab99581c-9804-47ab-961c-6b01573cb8bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=484223758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.484223758 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.4108375614 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 31932621544 ps |
| CPU time | 63.6 seconds |
| Started | Jan 17 01:54:28 PM PST 24 |
| Finished | Jan 17 01:55:35 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-11e67c59-4650-46bc-b22b-cfa30919dd1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4108375614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4108375614 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.488660516 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 29735482 ps |
| CPU time | 2.23 seconds |
| Started | Jan 17 01:54:24 PM PST 24 |
| Finished | Jan 17 01:54:28 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-becbd86f-3e9c-48aa-8174-5796c4ae2dee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488660516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.488660516 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1167500087 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 6558015 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:54:29 PM PST 24 |
| Finished | Jan 17 01:54:33 PM PST 24 |
| Peak memory | 195548 kb |
| Host | smart-c33217fc-73ad-49cd-98dc-d8ed160656a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1167500087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1167500087 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2940137090 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 2079703502 ps |
| CPU time | 48.47 seconds |
| Started | Jan 17 01:54:31 PM PST 24 |
| Finished | Jan 17 01:55:27 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-00608a2b-fef8-49e8-96fe-c24bbc21de9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2940137090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2940137090 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3118783038 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 8541667776 ps |
| CPU time | 274.4 seconds |
| Started | Jan 17 01:54:30 PM PST 24 |
| Finished | Jan 17 01:59:07 PM PST 24 |
| Peak memory | 209812 kb |
| Host | smart-c3186131-bd0b-4482-bdb8-161532f58ae6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3118783038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.3118783038 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.77943901 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1536310631 ps |
| CPU time | 116.31 seconds |
| Started | Jan 17 01:54:35 PM PST 24 |
| Finished | Jan 17 01:56:35 PM PST 24 |
| Peak memory | 209276 kb |
| Host | smart-56570ad2-1c2c-4712-bb2c-6219d902e2d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=77943901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rese t_error.77943901 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2278909286 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 106870984 ps |
| CPU time | 16.58 seconds |
| Started | Jan 17 01:54:31 PM PST 24 |
| Finished | Jan 17 01:54:53 PM PST 24 |
| Peak memory | 205036 kb |
| Host | smart-d83d00f6-4603-4377-97aa-1a867ef35274 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2278909286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2278909286 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.3041588636 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 187397902 ps |
| CPU time | 10.06 seconds |
| Started | Jan 17 01:54:34 PM PST 24 |
| Finished | Jan 17 01:54:49 PM PST 24 |
| Peak memory | 211816 kb |
| Host | smart-ae62f032-be5c-4688-b156-58057435647b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3041588636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3041588636 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1021111740 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 27772346145 ps |
| CPU time | 112.24 seconds |
| Started | Jan 17 01:54:30 PM PST 24 |
| Finished | Jan 17 01:56:24 PM PST 24 |
| Peak memory | 212020 kb |
| Host | smart-d7c88d85-2561-4b27-b203-9243ba20fe9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1021111740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.1021111740 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.4172780534 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 5360993250 ps |
| CPU time | 26.61 seconds |
| Started | Jan 17 01:54:29 PM PST 24 |
| Finished | Jan 17 01:54:58 PM PST 24 |
| Peak memory | 204544 kb |
| Host | smart-c4d85d6b-be19-4d07-a0ee-9c56d8900118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172780534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.4172780534 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.3597386283 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 5993149382 ps |
| CPU time | 40.75 seconds |
| Started | Jan 17 01:54:30 PM PST 24 |
| Finished | Jan 17 01:55:13 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-f0a787a9-331c-492d-89e5-ae2f242282af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3597386283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3597386283 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.2367299697 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3839102301 ps |
| CPU time | 38.04 seconds |
| Started | Jan 17 01:54:33 PM PST 24 |
| Finished | Jan 17 01:55:17 PM PST 24 |
| Peak memory | 212060 kb |
| Host | smart-6a6d6889-f5e4-4bb0-ba70-330eaf8d8e30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2367299697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2367299697 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.67000806 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 16779816184 ps |
| CPU time | 87.42 seconds |
| Started | Jan 17 01:54:33 PM PST 24 |
| Finished | Jan 17 01:56:07 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-8983ef7a-2260-4bd5-b472-fb5f5cca9429 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=67000806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.67000806 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.672264243 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1487582857 ps |
| CPU time | 14.38 seconds |
| Started | Jan 17 01:54:30 PM PST 24 |
| Finished | Jan 17 01:54:46 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-2748a73b-2370-4a3a-830d-99378ce28164 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=672264243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.672264243 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.172011468 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 86800657 ps |
| CPU time | 7.11 seconds |
| Started | Jan 17 01:54:36 PM PST 24 |
| Finished | Jan 17 01:54:46 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-c9a76290-9b72-402c-a78e-f26bbaba70aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172011468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.172011468 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.1247961685 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 816749064 ps |
| CPU time | 7.11 seconds |
| Started | Jan 17 01:54:32 PM PST 24 |
| Finished | Jan 17 01:54:46 PM PST 24 |
| Peak memory | 203848 kb |
| Host | smart-207ff81c-9800-4310-9da1-dfcd200ccfc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1247961685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1247961685 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.546612709 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 37737623 ps |
| CPU time | 2.32 seconds |
| Started | Jan 17 01:54:34 PM PST 24 |
| Finished | Jan 17 01:54:41 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-cccf4389-acdd-4a2c-8894-f823297a6735 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=546612709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.546612709 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1672358240 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 20470815993 ps |
| CPU time | 40.26 seconds |
| Started | Jan 17 01:54:32 PM PST 24 |
| Finished | Jan 17 01:55:19 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-23779149-773e-4b10-9548-738c64567ec2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672358240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1672358240 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.440128564 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 6414877385 ps |
| CPU time | 32.57 seconds |
| Started | Jan 17 01:54:30 PM PST 24 |
| Finished | Jan 17 01:55:05 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-49384259-9e86-4346-9112-83d615ac68eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=440128564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.440128564 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1491658866 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 53384542 ps |
| CPU time | 2.47 seconds |
| Started | Jan 17 01:54:32 PM PST 24 |
| Finished | Jan 17 01:54:41 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-3ccea630-2e88-42b4-b79c-8bb5d4b0aaaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491658866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1491658866 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.117194865 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1196875466 ps |
| CPU time | 96.71 seconds |
| Started | Jan 17 01:54:30 PM PST 24 |
| Finished | Jan 17 01:56:09 PM PST 24 |
| Peak memory | 207060 kb |
| Host | smart-0bbd6374-8210-44fa-9df1-1ec5e6511107 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=117194865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.117194865 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1620540268 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2652556419 ps |
| CPU time | 75.58 seconds |
| Started | Jan 17 01:54:34 PM PST 24 |
| Finished | Jan 17 01:55:55 PM PST 24 |
| Peak memory | 206420 kb |
| Host | smart-d7879e1a-e13b-424f-afab-88c2b4023a22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1620540268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1620540268 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2523870912 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 4024146934 ps |
| CPU time | 360.37 seconds |
| Started | Jan 17 01:54:32 PM PST 24 |
| Finished | Jan 17 02:00:39 PM PST 24 |
| Peak memory | 207812 kb |
| Host | smart-036b89f6-7f62-49e4-93bd-1cc3c3373b79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2523870912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.2523870912 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.1564706199 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 683702561 ps |
| CPU time | 164.6 seconds |
| Started | Jan 17 01:54:28 PM PST 24 |
| Finished | Jan 17 01:57:16 PM PST 24 |
| Peak memory | 211380 kb |
| Host | smart-9381738a-2c67-4040-be5c-05f32f2b21ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1564706199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.1564706199 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.105973951 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 401006903 ps |
| CPU time | 16.59 seconds |
| Started | Jan 17 01:54:30 PM PST 24 |
| Finished | Jan 17 01:54:49 PM PST 24 |
| Peak memory | 211888 kb |
| Host | smart-24555d32-ea69-4cb7-97e5-571b2c34bdac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=105973951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.105973951 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1826220246 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 337156087 ps |
| CPU time | 43.19 seconds |
| Started | Jan 17 01:49:40 PM PST 24 |
| Finished | Jan 17 01:50:24 PM PST 24 |
| Peak memory | 204296 kb |
| Host | smart-621129b3-33a5-48a9-a29c-eeffc74ac40f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1826220246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1826220246 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3156230874 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3675224917 ps |
| CPU time | 32.82 seconds |
| Started | Jan 17 01:49:41 PM PST 24 |
| Finished | Jan 17 01:50:15 PM PST 24 |
| Peak memory | 202764 kb |
| Host | smart-dccfdd6f-64dc-49eb-9fe4-54bf4f164e70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3156230874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.3156230874 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1521958083 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 194337387 ps |
| CPU time | 4.59 seconds |
| Started | Jan 17 01:49:41 PM PST 24 |
| Finished | Jan 17 01:49:47 PM PST 24 |
| Peak memory | 203796 kb |
| Host | smart-4c858862-e368-4177-9bc8-cf69e5b07950 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1521958083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1521958083 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.4213959272 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 578777948 ps |
| CPU time | 13.33 seconds |
| Started | Jan 17 01:49:37 PM PST 24 |
| Finished | Jan 17 01:49:52 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-fa21d67a-2a4a-481a-acf5-d2aa5898da5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4213959272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.4213959272 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.3276911053 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 853284490 ps |
| CPU time | 30.33 seconds |
| Started | Jan 17 01:49:38 PM PST 24 |
| Finished | Jan 17 01:50:10 PM PST 24 |
| Peak memory | 211928 kb |
| Host | smart-16c762dc-649f-4cc6-983a-60c56b94072b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3276911053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3276911053 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.4227814611 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 78798116939 ps |
| CPU time | 263.32 seconds |
| Started | Jan 17 01:49:40 PM PST 24 |
| Finished | Jan 17 01:54:04 PM PST 24 |
| Peak memory | 211992 kb |
| Host | smart-60fa2ec1-0f9b-4c1d-a7ca-f5fe33db238f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227814611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4227814611 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.4235200414 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 18199464138 ps |
| CPU time | 90.6 seconds |
| Started | Jan 17 01:49:34 PM PST 24 |
| Finished | Jan 17 01:51:08 PM PST 24 |
| Peak memory | 212004 kb |
| Host | smart-c72ab111-7212-4874-97f5-d608bfc4e543 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4235200414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4235200414 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.2246201016 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 28300343 ps |
| CPU time | 4.31 seconds |
| Started | Jan 17 01:49:39 PM PST 24 |
| Finished | Jan 17 01:49:45 PM PST 24 |
| Peak memory | 204140 kb |
| Host | smart-e6c6c5f5-fcc4-48c9-9615-09560d4683d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246201016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2246201016 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.3223913564 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 162045975 ps |
| CPU time | 2.42 seconds |
| Started | Jan 17 01:49:35 PM PST 24 |
| Finished | Jan 17 01:49:40 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-e1be299e-7c52-4f53-9890-fe8831cbb833 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3223913564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3223913564 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.341102783 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 132215050 ps |
| CPU time | 3.06 seconds |
| Started | Jan 17 01:49:40 PM PST 24 |
| Finished | Jan 17 01:49:44 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-8bb82272-c243-4196-a3c8-6d18e784deb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=341102783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.341102783 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3537559916 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 5298788284 ps |
| CPU time | 32.22 seconds |
| Started | Jan 17 01:49:37 PM PST 24 |
| Finished | Jan 17 01:50:11 PM PST 24 |
| Peak memory | 203836 kb |
| Host | smart-d9e87bac-a125-4be9-8556-373edf2bed5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537559916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3537559916 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.150909455 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 14831799090 ps |
| CPU time | 43.82 seconds |
| Started | Jan 17 01:49:36 PM PST 24 |
| Finished | Jan 17 01:50:22 PM PST 24 |
| Peak memory | 203792 kb |
| Host | smart-f37216f7-a35d-42ee-9353-f3e13eaa7f82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=150909455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.150909455 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.4238110606 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 37043297 ps |
| CPU time | 2.07 seconds |
| Started | Jan 17 01:49:44 PM PST 24 |
| Finished | Jan 17 01:49:46 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-512d5d40-968c-4ded-9c31-36d6e0e0893a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238110606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.4238110606 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.247505803 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2507157876 ps |
| CPU time | 67.6 seconds |
| Started | Jan 17 01:49:39 PM PST 24 |
| Finished | Jan 17 01:50:49 PM PST 24 |
| Peak memory | 206200 kb |
| Host | smart-8d3aba14-85b6-4521-9db6-5c6b1cc193e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=247505803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.247505803 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2048399383 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 5172154688 ps |
| CPU time | 125.27 seconds |
| Started | Jan 17 01:49:38 PM PST 24 |
| Finished | Jan 17 01:51:45 PM PST 24 |
| Peak memory | 206872 kb |
| Host | smart-ffed0894-5f03-4278-99f7-14091709c72a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2048399383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2048399383 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.4155977996 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 498878445 ps |
| CPU time | 129.86 seconds |
| Started | Jan 17 01:49:39 PM PST 24 |
| Finished | Jan 17 01:51:51 PM PST 24 |
| Peak memory | 208400 kb |
| Host | smart-fbea80f2-e864-487b-9d3b-a82342c04fa7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4155977996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.4155977996 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.772892888 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 6956423407 ps |
| CPU time | 427.89 seconds |
| Started | Jan 17 01:49:38 PM PST 24 |
| Finished | Jan 17 01:56:48 PM PST 24 |
| Peak memory | 228012 kb |
| Host | smart-b490d2bf-9311-4896-9083-5707bb70cce8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=772892888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese t_error.772892888 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3070044945 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1006576471 ps |
| CPU time | 9.71 seconds |
| Started | Jan 17 01:49:43 PM PST 24 |
| Finished | Jan 17 01:49:54 PM PST 24 |
| Peak memory | 211884 kb |
| Host | smart-afc773f9-6ae9-48b6-ac25-f06ccfe3b6ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3070044945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3070044945 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.25266327 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 89351207 ps |
| CPU time | 4.68 seconds |
| Started | Jan 17 01:49:36 PM PST 24 |
| Finished | Jan 17 01:49:43 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-f9139f80-b637-4c9d-80d9-1ec728a8845b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=25266327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.25266327 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2392504134 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 57127183239 ps |
| CPU time | 533.49 seconds |
| Started | Jan 17 01:49:38 PM PST 24 |
| Finished | Jan 17 01:58:33 PM PST 24 |
| Peak memory | 207492 kb |
| Host | smart-fac33c8a-0021-4de9-b8b2-5ce4c7d959fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2392504134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.2392504134 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3523347942 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 535866370 ps |
| CPU time | 3.96 seconds |
| Started | Jan 17 01:49:40 PM PST 24 |
| Finished | Jan 17 01:49:45 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-8c06b8a5-ec00-4ce3-8cf5-ea20553390ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3523347942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3523347942 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.1249723919 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 808671466 ps |
| CPU time | 25.31 seconds |
| Started | Jan 17 01:49:42 PM PST 24 |
| Finished | Jan 17 01:50:08 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-99a428cb-3c18-479e-a330-8f86d0dc8949 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1249723919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1249723919 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.2249217411 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 172142170 ps |
| CPU time | 8.7 seconds |
| Started | Jan 17 01:49:39 PM PST 24 |
| Finished | Jan 17 01:49:50 PM PST 24 |
| Peak memory | 210872 kb |
| Host | smart-4e5f36e5-435b-4661-be44-4171327d75f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2249217411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2249217411 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2683775445 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 24677972725 ps |
| CPU time | 138.9 seconds |
| Started | Jan 17 01:49:42 PM PST 24 |
| Finished | Jan 17 01:52:01 PM PST 24 |
| Peak memory | 205268 kb |
| Host | smart-862cbddb-3cc4-4614-9963-2269a8c30c49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683775445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2683775445 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2566930691 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 19033667116 ps |
| CPU time | 130.58 seconds |
| Started | Jan 17 01:49:37 PM PST 24 |
| Finished | Jan 17 01:51:49 PM PST 24 |
| Peak memory | 211872 kb |
| Host | smart-87a60d96-fbdf-4fcd-a6e8-bfbbaeee4d6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2566930691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2566930691 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1524640791 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 267907244 ps |
| CPU time | 22.35 seconds |
| Started | Jan 17 01:49:39 PM PST 24 |
| Finished | Jan 17 01:50:03 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-722d0694-4a9c-4101-b887-9b1f19813e6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524640791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1524640791 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.101667739 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1514764783 ps |
| CPU time | 17.56 seconds |
| Started | Jan 17 01:49:38 PM PST 24 |
| Finished | Jan 17 01:49:58 PM PST 24 |
| Peak memory | 204204 kb |
| Host | smart-932afa5f-762a-4883-a007-3845caa909da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=101667739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.101667739 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.915220573 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 35040818 ps |
| CPU time | 2.6 seconds |
| Started | Jan 17 01:49:36 PM PST 24 |
| Finished | Jan 17 01:49:41 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-f1436065-3670-4deb-9a69-d27837e73c9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=915220573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.915220573 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.97898874 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 11099514511 ps |
| CPU time | 28.48 seconds |
| Started | Jan 17 01:49:38 PM PST 24 |
| Finished | Jan 17 01:50:09 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-e00ffbe8-8ef7-4d45-a1de-6d2a476eb8d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=97898874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.97898874 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.743676731 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 4149859765 ps |
| CPU time | 29.87 seconds |
| Started | Jan 17 01:49:35 PM PST 24 |
| Finished | Jan 17 01:50:08 PM PST 24 |
| Peak memory | 203820 kb |
| Host | smart-21836bd6-2e87-4aab-962d-4ae4fd2b3709 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=743676731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.743676731 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2329111241 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 68899862 ps |
| CPU time | 2.26 seconds |
| Started | Jan 17 01:49:41 PM PST 24 |
| Finished | Jan 17 01:49:44 PM PST 24 |
| Peak memory | 202708 kb |
| Host | smart-b9427b23-ee23-4cfe-86db-699f3171c7a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329111241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2329111241 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.4198342908 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 11148379276 ps |
| CPU time | 175.66 seconds |
| Started | Jan 17 01:49:41 PM PST 24 |
| Finished | Jan 17 01:52:38 PM PST 24 |
| Peak memory | 208968 kb |
| Host | smart-cad3f0a6-37aa-440c-861d-415b2578aa80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4198342908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.4198342908 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1853449190 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 7480061664 ps |
| CPU time | 81.29 seconds |
| Started | Jan 17 01:49:35 PM PST 24 |
| Finished | Jan 17 01:51:00 PM PST 24 |
| Peak memory | 211972 kb |
| Host | smart-5e051b8c-64ca-4b72-ac63-5e97a815e881 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1853449190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1853449190 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.503652202 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 136342314 ps |
| CPU time | 25.62 seconds |
| Started | Jan 17 01:49:39 PM PST 24 |
| Finished | Jan 17 01:50:06 PM PST 24 |
| Peak memory | 206648 kb |
| Host | smart-3719f21f-320c-498c-a11f-e2a81e442812 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=503652202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_ reset.503652202 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1618646820 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 10304334 ps |
| CPU time | 4.84 seconds |
| Started | Jan 17 01:49:38 PM PST 24 |
| Finished | Jan 17 01:49:45 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-d0e31f7d-ec7b-4a4f-9ff9-6220f83abcf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1618646820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.1618646820 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.321093369 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 326758560 ps |
| CPU time | 13.96 seconds |
| Started | Jan 17 01:49:37 PM PST 24 |
| Finished | Jan 17 01:49:53 PM PST 24 |
| Peak memory | 205028 kb |
| Host | smart-125cda11-5784-4d98-b88a-1d02bf82f5fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=321093369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.321093369 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.3080732642 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2655934691 ps |
| CPU time | 36.71 seconds |
| Started | Jan 17 01:49:47 PM PST 24 |
| Finished | Jan 17 01:50:25 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-c4a26a24-6a43-4465-9b26-a2abdb71bfa9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3080732642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3080732642 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2465697320 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 99973917795 ps |
| CPU time | 701.42 seconds |
| Started | Jan 17 01:49:49 PM PST 24 |
| Finished | Jan 17 02:01:31 PM PST 24 |
| Peak memory | 211996 kb |
| Host | smart-00d6e04f-9b5b-4b79-b084-663195a90faf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2465697320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.2465697320 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1427995871 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 210924971 ps |
| CPU time | 9.63 seconds |
| Started | Jan 17 01:49:49 PM PST 24 |
| Finished | Jan 17 01:49:59 PM PST 24 |
| Peak memory | 203928 kb |
| Host | smart-59055dd1-d0e3-491c-86dd-a7511f51e6b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1427995871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1427995871 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2201001501 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 61958635 ps |
| CPU time | 6.81 seconds |
| Started | Jan 17 01:49:49 PM PST 24 |
| Finished | Jan 17 01:49:57 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-dd3b9073-73fe-4365-a9f7-2ecb13e17c34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2201001501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2201001501 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.2983317272 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1123729035 ps |
| CPU time | 27.07 seconds |
| Started | Jan 17 01:49:46 PM PST 24 |
| Finished | Jan 17 01:50:14 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-e8f52294-bc36-4689-9ac7-13024fb13f3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2983317272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2983317272 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2150273067 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 58356447115 ps |
| CPU time | 206.06 seconds |
| Started | Jan 17 01:49:47 PM PST 24 |
| Finished | Jan 17 01:53:14 PM PST 24 |
| Peak memory | 211912 kb |
| Host | smart-270eabbc-aa6b-442a-8e2b-21c15c2e2cad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150273067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2150273067 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3014610829 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 9825135150 ps |
| CPU time | 76.62 seconds |
| Started | Jan 17 01:49:49 PM PST 24 |
| Finished | Jan 17 01:51:07 PM PST 24 |
| Peak memory | 211980 kb |
| Host | smart-f9c9e2b8-bdb8-41c4-b579-70c140236ecb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3014610829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3014610829 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.521525990 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 88832166 ps |
| CPU time | 12.4 seconds |
| Started | Jan 17 01:49:51 PM PST 24 |
| Finished | Jan 17 01:50:07 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-ed4564e8-35c6-4eb2-b385-af51d043d079 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521525990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.521525990 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.2304034769 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1060824267 ps |
| CPU time | 14.97 seconds |
| Started | Jan 17 01:49:45 PM PST 24 |
| Finished | Jan 17 01:50:00 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-d3932313-7a2a-4a98-afb4-12d27de308ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2304034769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2304034769 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.4097455937 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 24413527 ps |
| CPU time | 2.17 seconds |
| Started | Jan 17 01:49:37 PM PST 24 |
| Finished | Jan 17 01:49:41 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-8fd4dbc2-1c91-49bd-8f19-05d2c023ef2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4097455937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.4097455937 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.91632030 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 4675156003 ps |
| CPU time | 27.04 seconds |
| Started | Jan 17 01:49:44 PM PST 24 |
| Finished | Jan 17 01:50:11 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-b7c5c520-3efd-41bd-aca6-3b0f2a0f3353 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=91632030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.91632030 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3579125830 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 6258322883 ps |
| CPU time | 29.76 seconds |
| Started | Jan 17 01:49:44 PM PST 24 |
| Finished | Jan 17 01:50:14 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-7c06b70b-97b2-49f8-b415-041802f72cd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3579125830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3579125830 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2109630088 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 43566981 ps |
| CPU time | 2.39 seconds |
| Started | Jan 17 01:49:36 PM PST 24 |
| Finished | Jan 17 01:49:41 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-b55e52de-a080-4e95-8ebb-b2806b4f0b91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109630088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2109630088 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2866854145 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 17383672626 ps |
| CPU time | 147.01 seconds |
| Started | Jan 17 01:49:46 PM PST 24 |
| Finished | Jan 17 01:52:14 PM PST 24 |
| Peak memory | 209704 kb |
| Host | smart-1078bce2-2375-4cae-9adc-ef701e61695b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2866854145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2866854145 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1241118594 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 36947812489 ps |
| CPU time | 232.27 seconds |
| Started | Jan 17 01:49:47 PM PST 24 |
| Finished | Jan 17 01:53:39 PM PST 24 |
| Peak memory | 208156 kb |
| Host | smart-1465b842-235b-446b-b27a-fbe67bd423dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1241118594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1241118594 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.695537743 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2327808971 ps |
| CPU time | 193.89 seconds |
| Started | Jan 17 01:49:46 PM PST 24 |
| Finished | Jan 17 01:53:01 PM PST 24 |
| Peak memory | 211028 kb |
| Host | smart-2401c87f-2c22-40fe-a148-ea924ada7f51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=695537743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rese t_error.695537743 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.3395796016 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 450094837 ps |
| CPU time | 21.7 seconds |
| Started | Jan 17 01:49:53 PM PST 24 |
| Finished | Jan 17 01:50:17 PM PST 24 |
| Peak memory | 211952 kb |
| Host | smart-bbd05c03-db73-479d-9534-9eb7894fcd73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3395796016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3395796016 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3648307126 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 731324681 ps |
| CPU time | 22.73 seconds |
| Started | Jan 17 01:49:46 PM PST 24 |
| Finished | Jan 17 01:50:10 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-13050644-6c43-49e1-9bc5-68452cd3c633 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3648307126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3648307126 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3609201155 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 68805735863 ps |
| CPU time | 563.38 seconds |
| Started | Jan 17 01:49:49 PM PST 24 |
| Finished | Jan 17 01:59:13 PM PST 24 |
| Peak memory | 211960 kb |
| Host | smart-49a63b98-ffc4-44e1-b642-def8dda39719 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3609201155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.3609201155 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3096622688 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2347182188 ps |
| CPU time | 25.58 seconds |
| Started | Jan 17 01:49:48 PM PST 24 |
| Finished | Jan 17 01:50:14 PM PST 24 |
| Peak memory | 203792 kb |
| Host | smart-0d5a8d1b-2ba1-4311-8e75-192b2fbcd671 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3096622688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3096622688 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.1615413754 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 85722370 ps |
| CPU time | 3.21 seconds |
| Started | Jan 17 01:49:46 PM PST 24 |
| Finished | Jan 17 01:49:50 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-8eccc2e0-90e4-49b1-80cd-b3068d06d192 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1615413754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1615413754 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.3152500157 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 194329504 ps |
| CPU time | 21.38 seconds |
| Started | Jan 17 01:49:46 PM PST 24 |
| Finished | Jan 17 01:50:08 PM PST 24 |
| Peak memory | 211896 kb |
| Host | smart-202c13f3-8403-472f-997b-cd37301aa860 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3152500157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3152500157 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2051022369 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 35051876023 ps |
| CPU time | 194.91 seconds |
| Started | Jan 17 01:49:49 PM PST 24 |
| Finished | Jan 17 01:53:05 PM PST 24 |
| Peak memory | 205012 kb |
| Host | smart-f5ae1e60-52fc-4f5d-b5cc-d074a7e91b7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051022369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2051022369 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3809888118 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1604511466 ps |
| CPU time | 13.01 seconds |
| Started | Jan 17 01:49:49 PM PST 24 |
| Finished | Jan 17 01:50:03 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-66817614-88af-4069-a420-d66779efef03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3809888118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3809888118 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.2608925060 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 171670562 ps |
| CPU time | 19.11 seconds |
| Started | Jan 17 01:49:47 PM PST 24 |
| Finished | Jan 17 01:50:06 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-e09bbc44-6ceb-4340-a81d-bb5728ae26e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608925060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2608925060 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.3251964437 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 83253745 ps |
| CPU time | 5 seconds |
| Started | Jan 17 01:49:50 PM PST 24 |
| Finished | Jan 17 01:49:56 PM PST 24 |
| Peak memory | 203944 kb |
| Host | smart-2144f606-cf74-40e2-b847-356b0ecc4daf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3251964437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3251964437 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.1238936065 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 151792139 ps |
| CPU time | 3.5 seconds |
| Started | Jan 17 01:49:48 PM PST 24 |
| Finished | Jan 17 01:49:52 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-bcb2f418-285e-4656-ba74-61416a342ad1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1238936065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1238936065 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2543588454 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 8310019418 ps |
| CPU time | 28.45 seconds |
| Started | Jan 17 01:49:50 PM PST 24 |
| Finished | Jan 17 01:50:19 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-3f9ad9d4-ef83-4154-8c35-81df3c9cc297 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543588454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2543588454 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2608234802 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3141928421 ps |
| CPU time | 28.72 seconds |
| Started | Jan 17 01:49:47 PM PST 24 |
| Finished | Jan 17 01:50:16 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-bd6be0e7-9858-46c7-aff6-0c70a6f5d0ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2608234802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2608234802 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2821248269 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 34470070 ps |
| CPU time | 2.17 seconds |
| Started | Jan 17 01:49:47 PM PST 24 |
| Finished | Jan 17 01:49:50 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-c3c3b61e-0dd2-44bd-8f96-d4082dfbd255 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821248269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2821248269 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.1501045730 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 10531218688 ps |
| CPU time | 153.92 seconds |
| Started | Jan 17 01:49:47 PM PST 24 |
| Finished | Jan 17 01:52:22 PM PST 24 |
| Peak memory | 207888 kb |
| Host | smart-54304b66-fee5-4fd6-8306-5b256556897e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1501045730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1501045730 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.2394412377 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 9384621624 ps |
| CPU time | 158.15 seconds |
| Started | Jan 17 01:49:50 PM PST 24 |
| Finished | Jan 17 01:52:29 PM PST 24 |
| Peak memory | 209060 kb |
| Host | smart-b4c83b48-0d54-4a3f-b8e4-5fd2c0af7116 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2394412377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2394412377 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3435924515 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 828028633 ps |
| CPU time | 85.06 seconds |
| Started | Jan 17 01:49:48 PM PST 24 |
| Finished | Jan 17 01:51:13 PM PST 24 |
| Peak memory | 209008 kb |
| Host | smart-a6a9f93e-11fc-4d3a-a07e-4217c8cbadbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3435924515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.3435924515 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.860392246 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2233476289 ps |
| CPU time | 170.18 seconds |
| Started | Jan 17 01:49:46 PM PST 24 |
| Finished | Jan 17 01:52:37 PM PST 24 |
| Peak memory | 211232 kb |
| Host | smart-055f2c47-d17d-41f5-b8b4-8f099914dba4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=860392246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rese t_error.860392246 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.968512513 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 210438882 ps |
| CPU time | 12.67 seconds |
| Started | Jan 17 01:49:50 PM PST 24 |
| Finished | Jan 17 01:50:03 PM PST 24 |
| Peak memory | 211940 kb |
| Host | smart-98c21a38-d3d9-432c-9552-3f6b69c87e40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=968512513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.968512513 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1996918949 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 907843206 ps |
| CPU time | 35.07 seconds |
| Started | Jan 17 01:50:01 PM PST 24 |
| Finished | Jan 17 01:50:41 PM PST 24 |
| Peak memory | 206248 kb |
| Host | smart-5f09722c-a7a6-4680-a438-0f92ba704a71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1996918949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1996918949 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2970404751 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 10450103070 ps |
| CPU time | 97.04 seconds |
| Started | Jan 17 01:50:00 PM PST 24 |
| Finished | Jan 17 01:51:43 PM PST 24 |
| Peak memory | 205936 kb |
| Host | smart-c74a016e-b7ce-493a-9ba0-1286ad3b45cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2970404751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2970404751 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.37449644 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 116259210 ps |
| CPU time | 13.52 seconds |
| Started | Jan 17 01:50:00 PM PST 24 |
| Finished | Jan 17 01:50:20 PM PST 24 |
| Peak memory | 203924 kb |
| Host | smart-d7e0ad84-e989-4fc3-ac7f-3cb3ea5a11e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=37449644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.37449644 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.4885635 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 401179406 ps |
| CPU time | 11.88 seconds |
| Started | Jan 17 01:49:55 PM PST 24 |
| Finished | Jan 17 01:50:09 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-45d54a3c-17a2-444a-aced-bd3fd18f615e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4885635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.4885635 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.2944567723 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 254699260 ps |
| CPU time | 8.99 seconds |
| Started | Jan 17 01:50:04 PM PST 24 |
| Finished | Jan 17 01:50:15 PM PST 24 |
| Peak memory | 211968 kb |
| Host | smart-c0cf1d6a-85ff-4241-90bc-b2fdc3c17d21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2944567723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2944567723 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1805273293 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 31140064539 ps |
| CPU time | 254.12 seconds |
| Started | Jan 17 01:50:01 PM PST 24 |
| Finished | Jan 17 01:54:20 PM PST 24 |
| Peak memory | 212024 kb |
| Host | smart-26e4775c-493f-4b10-b633-cb3035369f81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1805273293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1805273293 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1180910511 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 29080736 ps |
| CPU time | 3.63 seconds |
| Started | Jan 17 01:50:00 PM PST 24 |
| Finished | Jan 17 01:50:10 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-d93a44d0-54f7-4569-93fd-0a0c0e28ee2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180910511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1180910511 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.3082055071 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1207842451 ps |
| CPU time | 19 seconds |
| Started | Jan 17 01:49:59 PM PST 24 |
| Finished | Jan 17 01:50:25 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-faa5eda0-6485-4297-9f34-4864a0a3b0bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3082055071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3082055071 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3032296548 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 513475636 ps |
| CPU time | 3.71 seconds |
| Started | Jan 17 01:49:49 PM PST 24 |
| Finished | Jan 17 01:49:54 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-00795322-42b7-4307-a583-3035db15fbf6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3032296548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3032296548 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3928613634 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 6246552064 ps |
| CPU time | 29.6 seconds |
| Started | Jan 17 01:50:00 PM PST 24 |
| Finished | Jan 17 01:50:36 PM PST 24 |
| Peak memory | 203856 kb |
| Host | smart-625e1af9-e52b-4b5b-890e-34607c1cc42b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928613634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3928613634 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.363499640 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 11675558802 ps |
| CPU time | 36.25 seconds |
| Started | Jan 17 01:50:03 PM PST 24 |
| Finished | Jan 17 01:50:42 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-ee98468f-b054-452a-bdbc-6f497f7a5ade |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=363499640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.363499640 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3708498670 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 41628242 ps |
| CPU time | 2.1 seconds |
| Started | Jan 17 01:49:48 PM PST 24 |
| Finished | Jan 17 01:49:51 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-1b652394-4891-481b-b514-8b03e7a52bf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708498670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3708498670 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.746868760 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1368321231 ps |
| CPU time | 36.43 seconds |
| Started | Jan 17 01:50:03 PM PST 24 |
| Finished | Jan 17 01:50:42 PM PST 24 |
| Peak memory | 205320 kb |
| Host | smart-797c3844-da3e-46da-862c-dad567da6dcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=746868760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.746868760 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.742496009 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 5228178180 ps |
| CPU time | 156 seconds |
| Started | Jan 17 01:49:58 PM PST 24 |
| Finished | Jan 17 01:52:42 PM PST 24 |
| Peak memory | 211964 kb |
| Host | smart-344058a0-1f7c-49c5-95ea-63eaeb2698cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=742496009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.742496009 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1369022779 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 180307152 ps |
| CPU time | 68.18 seconds |
| Started | Jan 17 01:50:01 PM PST 24 |
| Finished | Jan 17 01:51:14 PM PST 24 |
| Peak memory | 207504 kb |
| Host | smart-441bd630-d452-4f33-9a89-badd8bfd363c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1369022779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1369022779 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.320466415 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 361686118 ps |
| CPU time | 139.03 seconds |
| Started | Jan 17 01:50:01 PM PST 24 |
| Finished | Jan 17 01:52:25 PM PST 24 |
| Peak memory | 210932 kb |
| Host | smart-d5066443-4f48-48e4-a88c-3903fcee3ebb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=320466415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese t_error.320466415 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.564937630 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 887063817 ps |
| CPU time | 23.13 seconds |
| Started | Jan 17 01:49:54 PM PST 24 |
| Finished | Jan 17 01:50:20 PM PST 24 |
| Peak memory | 205248 kb |
| Host | smart-0816b898-2dad-4dd8-85a9-f93312e4ecc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=564937630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.564937630 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |