Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 545 1 T5 8 T6 1 T8 3
all_values[1] 507 1 T5 5 T6 1 T8 1
all_values[2] 500 1 T5 5 T7 1 T15 10
all_values[3] 492 1 T5 10 T6 1 T7 1
all_values[4] 501 1 T5 5 T28 2 T15 10
all_values[5] 551 1 T5 8 T7 1 T8 5
all_values[6] 495 1 T5 8 T6 2 T8 2
all_values[7] 510 1 T5 2 T6 1 T8 4
all_values[8] 503 1 T5 6 T6 1 T8 1
all_values[9] 505 1 T5 10 T6 1 T7 1
all_values[10] 514 1 T5 9 T7 1 T8 1
all_values[11] 476 1 T5 6 T6 1 T8 2
all_values[12] 477 1 T5 3 T6 1 T8 3
all_values[13] 527 1 T5 5 T7 1 T9 1
all_values[14] 490 1 T5 6 T6 1 T8 1
all_values[15] 488 1 T5 3 T8 1 T15 2
all_values[16] 477 1 T5 6 T7 1 T8 2
all_values[17] 499 1 T5 8 T6 2 T8 1
all_values[18] 503 1 T5 7 T7 1 T15 7
all_values[19] 511 1 T5 9 T6 1 T8 1
all_values[20] 540 1 T5 5 T6 1 T7 3
all_values[21] 502 1 T5 7 T6 2 T8 1
all_values[22] 507 1 T5 5 T6 1 T8 1
all_values[23] 511 1 T5 7 T8 2 T9 2

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