| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.21 | 99.26 | 90.10 | 98.80 | 95.82 | 99.26 | 100.00 |
| T764 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1990134612 | Jan 21 10:44:54 PM PST 24 | Jan 21 10:46:01 PM PST 24 | 2610587964 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.988458230 | Jan 21 10:45:48 PM PST 24 | Jan 21 10:49:35 PM PST 24 | 122114361915 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.398931251 | Jan 21 11:21:41 PM PST 24 | Jan 21 11:22:06 PM PST 24 | 494352671 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.851017540 | Jan 21 10:37:59 PM PST 24 | Jan 21 10:40:48 PM PST 24 | 6796448836 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/42.xbar_same_source.201750323 | Jan 21 10:43:39 PM PST 24 | Jan 21 10:44:11 PM PST 24 | 1682206989 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.9513672 | Jan 21 10:34:41 PM PST 24 | Jan 21 10:38:54 PM PST 24 | 7630868308 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2267331677 | Jan 21 10:39:49 PM PST 24 | Jan 21 10:41:32 PM PST 24 | 21128420742 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1664779842 | Jan 21 10:37:49 PM PST 24 | Jan 21 10:38:17 PM PST 24 | 831698447 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2352338274 | Jan 21 10:36:55 PM PST 24 | Jan 21 10:37:07 PM PST 24 | 46103393 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.417750439 | Jan 21 10:34:41 PM PST 24 | Jan 21 10:37:16 PM PST 24 | 26524478956 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/39.xbar_error_random.3784402783 | Jan 21 10:42:54 PM PST 24 | Jan 21 10:43:08 PM PST 24 | 279006173 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3230008748 | Jan 21 10:35:26 PM PST 24 | Jan 21 10:39:47 PM PST 24 | 186862578608 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2283560513 | Jan 21 10:32:10 PM PST 24 | Jan 21 10:32:41 PM PST 24 | 158353424 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3085088684 | Jan 21 10:35:19 PM PST 24 | Jan 21 10:41:15 PM PST 24 | 21503404228 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/35.xbar_random.4082232121 | Jan 21 10:41:37 PM PST 24 | Jan 21 10:42:01 PM PST 24 | 148219942 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2445964320 | Jan 21 10:41:52 PM PST 24 | Jan 21 10:42:26 PM PST 24 | 8172351888 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1972798026 | Jan 21 11:08:38 PM PST 24 | Jan 21 11:08:41 PM PST 24 | 50974205 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1482273965 | Jan 21 10:38:30 PM PST 24 | Jan 21 10:38:45 PM PST 24 | 326312214 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2840892744 | Jan 21 10:41:44 PM PST 24 | Jan 21 10:42:26 PM PST 24 | 34100086 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2379472304 | Jan 21 11:01:13 PM PST 24 | Jan 21 11:07:47 PM PST 24 | 53578751767 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3931819218 | Jan 21 10:35:41 PM PST 24 | Jan 21 10:36:19 PM PST 24 | 11094878399 ps | ||
| T111 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2945134646 | Jan 21 10:36:58 PM PST 24 | Jan 21 10:48:46 PM PST 24 | 14055303217 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2288513779 | Jan 21 10:36:38 PM PST 24 | Jan 21 10:41:46 PM PST 24 | 55611362711 ps | ||
| T61 | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3304681908 | Jan 21 10:42:54 PM PST 24 | Jan 21 10:50:30 PM PST 24 | 55986662148 ps | ||
| T62 | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.124758228 | Jan 21 10:39:08 PM PST 24 | Jan 21 10:42:43 PM PST 24 | 27725567204 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/14.xbar_random.3813809350 | Jan 21 10:35:45 PM PST 24 | Jan 21 10:36:39 PM PST 24 | 2798350907 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2984204376 | Jan 21 10:53:43 PM PST 24 | Jan 21 10:55:42 PM PST 24 | 22378422415 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1291702177 | Jan 21 10:32:33 PM PST 24 | Jan 21 10:34:35 PM PST 24 | 30840148071 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2091522711 | Jan 21 10:40:17 PM PST 24 | Jan 21 10:40:47 PM PST 24 | 99752910 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3807428441 | Jan 21 10:41:36 PM PST 24 | Jan 21 10:42:31 PM PST 24 | 39390383427 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/6.xbar_random.2633973690 | Jan 21 10:33:12 PM PST 24 | Jan 21 10:33:30 PM PST 24 | 171764893 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.4252621542 | Jan 21 10:32:34 PM PST 24 | Jan 21 10:33:00 PM PST 24 | 146742527 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3887001589 | Jan 21 10:32:22 PM PST 24 | Jan 21 10:33:54 PM PST 24 | 4352186817 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1362532823 | Jan 21 10:33:03 PM PST 24 | Jan 21 10:33:30 PM PST 24 | 7619504428 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.933826111 | Jan 21 10:41:24 PM PST 24 | Jan 21 10:51:21 PM PST 24 | 316987176628 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2017270472 | Jan 21 11:24:45 PM PST 24 | Jan 21 11:25:44 PM PST 24 | 4236602605 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.950719411 | Jan 21 10:34:43 PM PST 24 | Jan 21 10:39:03 PM PST 24 | 102181303087 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/2.xbar_random.4213354389 | Jan 21 10:32:11 PM PST 24 | Jan 21 10:32:32 PM PST 24 | 120127507 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3301667117 | Jan 21 10:41:44 PM PST 24 | Jan 21 10:45:18 PM PST 24 | 792616089 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2633966534 | Jan 21 10:35:35 PM PST 24 | Jan 21 10:38:21 PM PST 24 | 24497150656 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.430898980 | Jan 21 10:44:19 PM PST 24 | Jan 21 10:44:58 PM PST 24 | 11506379639 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.268947690 | Jan 21 10:43:18 PM PST 24 | Jan 21 10:46:25 PM PST 24 | 38126634937 ps | ||
| T63 | /workspace/coverage/xbar_build_mode/25.xbar_random.3794945538 | Jan 21 10:38:43 PM PST 24 | Jan 21 10:39:06 PM PST 24 | 705360373 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2117139370 | Jan 21 10:39:55 PM PST 24 | Jan 21 10:40:23 PM PST 24 | 1124337441 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/26.xbar_error_random.1695102615 | Jan 21 10:39:09 PM PST 24 | Jan 21 10:39:49 PM PST 24 | 2131801999 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.4258322052 | Jan 21 10:38:50 PM PST 24 | Jan 21 10:39:02 PM PST 24 | 97033578 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3961792170 | Jan 21 10:40:02 PM PST 24 | Jan 21 10:40:38 PM PST 24 | 10487545570 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.4173402948 | Jan 21 10:39:56 PM PST 24 | Jan 21 10:40:04 PM PST 24 | 107295118 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/44.xbar_error_random.991481407 | Jan 21 10:44:17 PM PST 24 | Jan 21 10:44:42 PM PST 24 | 302968041 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/6.xbar_smoke.1173396977 | Jan 21 10:33:15 PM PST 24 | Jan 21 10:33:23 PM PST 24 | 136139034 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1766158177 | Jan 21 11:03:43 PM PST 24 | Jan 21 11:03:54 PM PST 24 | 154967389 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/11.xbar_error_random.2545449575 | Jan 21 10:34:56 PM PST 24 | Jan 21 10:35:18 PM PST 24 | 270663530 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.4013549489 | Jan 21 10:35:35 PM PST 24 | Jan 21 10:36:01 PM PST 24 | 643843974 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/10.xbar_random.4177334483 | Jan 21 10:34:32 PM PST 24 | Jan 21 10:34:56 PM PST 24 | 2143743898 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/23.xbar_same_source.3269810397 | Jan 21 10:50:14 PM PST 24 | Jan 21 10:50:44 PM PST 24 | 992453516 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.433133325 | Jan 21 10:42:27 PM PST 24 | Jan 21 10:42:31 PM PST 24 | 76392852 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1482055298 | Jan 21 10:40:21 PM PST 24 | Jan 21 10:40:25 PM PST 24 | 81552290 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1812186181 | Jan 21 10:35:35 PM PST 24 | Jan 21 10:35:38 PM PST 24 | 34608771 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.4154914427 | Jan 21 10:35:33 PM PST 24 | Jan 21 10:38:40 PM PST 24 | 7185425526 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/47.xbar_random.2825093614 | Jan 21 10:44:52 PM PST 24 | Jan 21 10:44:57 PM PST 24 | 720624820 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/37.xbar_error_random.1709735211 | Jan 21 10:42:24 PM PST 24 | Jan 21 10:42:32 PM PST 24 | 70866782 ps | ||
| T130 | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2126486368 | Jan 21 11:10:00 PM PST 24 | Jan 21 11:11:35 PM PST 24 | 9714364126 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.536592242 | Jan 21 10:38:52 PM PST 24 | Jan 21 10:39:00 PM PST 24 | 269821655 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3009435390 | Jan 21 10:40:02 PM PST 24 | Jan 21 10:46:04 PM PST 24 | 2971343367 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2329898839 | Jan 21 10:31:55 PM PST 24 | Jan 21 10:32:35 PM PST 24 | 18239961954 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/47.xbar_smoke.912667355 | Jan 21 10:44:56 PM PST 24 | Jan 21 10:45:01 PM PST 24 | 216042892 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.765471294 | Jan 21 10:45:48 PM PST 24 | Jan 21 10:49:15 PM PST 24 | 37561199026 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3973614107 | Jan 21 10:40:36 PM PST 24 | Jan 21 10:45:22 PM PST 24 | 31485405069 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3193483146 | Jan 21 10:34:44 PM PST 24 | Jan 21 10:35:26 PM PST 24 | 20876495770 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.91703281 | Jan 21 11:16:19 PM PST 24 | Jan 21 11:16:46 PM PST 24 | 3369117153 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3097246123 | Jan 21 10:38:17 PM PST 24 | Jan 21 10:38:21 PM PST 24 | 30566092 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2631115717 | Jan 21 10:33:38 PM PST 24 | Jan 21 10:37:36 PM PST 24 | 13265825639 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2568777834 | Jan 21 10:38:10 PM PST 24 | Jan 21 10:38:28 PM PST 24 | 1080116343 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1283579945 | Jan 21 10:39:27 PM PST 24 | Jan 21 10:40:01 PM PST 24 | 15316016417 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.4065946271 | Jan 21 10:52:19 PM PST 24 | Jan 21 10:52:53 PM PST 24 | 5503249691 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.681880592 | Jan 21 10:43:33 PM PST 24 | Jan 21 10:44:08 PM PST 24 | 5586478831 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2093114040 | Jan 21 10:31:55 PM PST 24 | Jan 21 10:32:06 PM PST 24 | 110854036 ps | ||
| T211 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.992129100 | Jan 21 10:44:27 PM PST 24 | Jan 21 10:48:46 PM PST 24 | 3405996574 ps | ||
| T140 | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.40821984 | Jan 21 10:37:48 PM PST 24 | Jan 21 10:43:11 PM PST 24 | 42933754713 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.4025393494 | Jan 21 10:40:13 PM PST 24 | Jan 21 10:40:45 PM PST 24 | 675301571 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/22.xbar_random.3462865319 | Jan 21 10:37:45 PM PST 24 | Jan 21 10:37:57 PM PST 24 | 21917624 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3382495162 | Jan 21 10:36:22 PM PST 24 | Jan 21 10:37:00 PM PST 24 | 11800660092 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3216994690 | Jan 21 10:35:09 PM PST 24 | Jan 21 10:40:50 PM PST 24 | 4319556896 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.345107068 | Jan 21 10:36:42 PM PST 24 | Jan 21 10:36:53 PM PST 24 | 7064477 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.147650097 | Jan 21 10:32:30 PM PST 24 | Jan 21 10:33:03 PM PST 24 | 8459614575 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.950859175 | Jan 21 10:33:48 PM PST 24 | Jan 21 10:34:10 PM PST 24 | 754263636 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3948540961 | Jan 21 10:45:34 PM PST 24 | Jan 21 10:45:38 PM PST 24 | 77760086 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3706775591 | Jan 21 10:40:37 PM PST 24 | Jan 21 10:42:23 PM PST 24 | 280639625 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3539546563 | Jan 21 10:35:10 PM PST 24 | Jan 21 10:36:17 PM PST 24 | 1697757163 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1627901878 | Jan 21 10:33:56 PM PST 24 | Jan 21 10:34:08 PM PST 24 | 79884226 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3131111597 | Jan 21 10:41:51 PM PST 24 | Jan 21 10:41:55 PM PST 24 | 34124126 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.465514641 | Jan 21 10:40:02 PM PST 24 | Jan 21 10:45:50 PM PST 24 | 764891776 ps | ||
| T162 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1433278762 | Jan 21 10:38:52 PM PST 24 | Jan 21 10:48:24 PM PST 24 | 2591375436 ps | ||
| T131 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.1645165561 | Jan 21 10:38:28 PM PST 24 | Jan 21 10:40:54 PM PST 24 | 7304229859 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.642639105 | Jan 21 10:41:37 PM PST 24 | Jan 21 10:42:42 PM PST 24 | 6837208006 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1650071344 | Jan 21 10:35:24 PM PST 24 | Jan 21 10:36:58 PM PST 24 | 257906550 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3115829084 | Jan 21 10:43:35 PM PST 24 | Jan 21 10:43:59 PM PST 24 | 436397798 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1784933897 | Jan 21 10:33:56 PM PST 24 | Jan 21 10:34:43 PM PST 24 | 330501926 ps | ||
| T183 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3810333535 | Jan 21 10:38:13 PM PST 24 | Jan 21 10:39:28 PM PST 24 | 442511517 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3339856962 | Jan 21 10:41:40 PM PST 24 | Jan 21 10:41:51 PM PST 24 | 52610999 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/30.xbar_error_random.385527379 | Jan 21 10:56:35 PM PST 24 | Jan 21 10:56:54 PM PST 24 | 247132677 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/27.xbar_same_source.513545941 | Jan 21 10:39:23 PM PST 24 | Jan 21 10:39:30 PM PST 24 | 544727343 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.3776066595 | Jan 21 10:40:17 PM PST 24 | Jan 21 10:41:04 PM PST 24 | 578923508 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/35.xbar_same_source.3572160845 | Jan 21 10:41:40 PM PST 24 | Jan 21 10:42:01 PM PST 24 | 678211893 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/1.xbar_random.2717227271 | Jan 21 10:56:29 PM PST 24 | Jan 21 10:56:42 PM PST 24 | 85614561 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3881381948 | Jan 21 10:38:17 PM PST 24 | Jan 21 10:39:04 PM PST 24 | 2020247006 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3235982041 | Jan 21 11:18:05 PM PST 24 | Jan 21 11:18:11 PM PST 24 | 36464141 ps | ||
| T163 | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1261805379 | Jan 21 10:35:03 PM PST 24 | Jan 21 10:43:58 PM PST 24 | 91217111379 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1563511842 | Jan 21 10:44:52 PM PST 24 | Jan 21 10:45:20 PM PST 24 | 82827202 ps | ||
| T35 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3686312553 | Jan 21 10:44:19 PM PST 24 | Jan 21 10:54:37 PM PST 24 | 4317442486 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/0.xbar_random.2279032323 | Jan 21 10:31:52 PM PST 24 | Jan 21 10:32:12 PM PST 24 | 721854431 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1504984646 | Jan 21 10:41:13 PM PST 24 | Jan 21 10:41:39 PM PST 24 | 5661630007 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1555806225 | Jan 21 10:37:48 PM PST 24 | Jan 21 10:41:42 PM PST 24 | 3773237004 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3018966010 | Jan 21 10:43:17 PM PST 24 | Jan 21 10:50:42 PM PST 24 | 63379686334 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2386466369 | Jan 21 10:33:03 PM PST 24 | Jan 21 10:35:54 PM PST 24 | 43505501509 ps | ||
| T132 | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.467602451 | Jan 21 10:45:08 PM PST 24 | Jan 21 10:46:15 PM PST 24 | 2784891681 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2329739113 | Jan 21 10:36:51 PM PST 24 | Jan 21 10:37:25 PM PST 24 | 3644253062 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.4228935663 | Jan 21 10:35:34 PM PST 24 | Jan 21 10:36:14 PM PST 24 | 218034837 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1301116179 | Jan 21 10:34:41 PM PST 24 | Jan 21 10:35:06 PM PST 24 | 122529062 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.2866696571 | Jan 21 10:43:02 PM PST 24 | Jan 21 10:47:58 PM PST 24 | 9892088596 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3089545704 | Jan 21 10:33:16 PM PST 24 | Jan 21 10:33:27 PM PST 24 | 134149224 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3059643552 | Jan 21 10:39:35 PM PST 24 | Jan 21 10:41:57 PM PST 24 | 29072350469 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.163685807 | Jan 21 10:41:10 PM PST 24 | Jan 21 10:42:32 PM PST 24 | 4902392998 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1323644622 | Jan 21 10:35:59 PM PST 24 | Jan 21 10:36:31 PM PST 24 | 12187025998 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2017292573 | Jan 21 10:34:56 PM PST 24 | Jan 21 10:35:04 PM PST 24 | 320246192 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.4241376752 | Jan 21 10:37:35 PM PST 24 | Jan 21 10:38:20 PM PST 24 | 7167762358 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/27.xbar_random.207313862 | Jan 21 10:39:10 PM PST 24 | Jan 21 10:39:18 PM PST 24 | 294982250 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3124846286 | Jan 21 10:32:29 PM PST 24 | Jan 21 10:32:56 PM PST 24 | 9839459463 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/15.xbar_same_source.541041150 | Jan 21 10:35:59 PM PST 24 | Jan 21 10:36:18 PM PST 24 | 145870915 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.1748313525 | Jan 21 10:38:52 PM PST 24 | Jan 21 10:39:03 PM PST 24 | 67268338 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3968504771 | Jan 21 10:31:49 PM PST 24 | Jan 21 10:32:43 PM PST 24 | 7793242787 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/12.xbar_smoke.2072608657 | Jan 21 10:34:56 PM PST 24 | Jan 21 10:35:01 PM PST 24 | 153160100 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/26.xbar_random.3819404430 | Jan 21 10:38:54 PM PST 24 | Jan 21 10:39:01 PM PST 24 | 33108492 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1513728917 | Jan 21 10:36:48 PM PST 24 | Jan 21 10:40:32 PM PST 24 | 33059062751 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/30.xbar_smoke.3950012620 | Jan 21 10:40:06 PM PST 24 | Jan 21 10:40:14 PM PST 24 | 143800920 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2089095954 | Jan 21 10:37:39 PM PST 24 | Jan 21 10:39:17 PM PST 24 | 15163361814 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.734650258 | Jan 21 10:39:38 PM PST 24 | Jan 21 10:39:59 PM PST 24 | 525129546 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3557567339 | Jan 21 10:36:27 PM PST 24 | Jan 21 10:36:59 PM PST 24 | 249158194 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.823822125 | Jan 21 10:37:02 PM PST 24 | Jan 21 10:37:38 PM PST 24 | 617477635 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/46.xbar_same_source.399931629 | Jan 21 10:44:41 PM PST 24 | Jan 21 10:45:10 PM PST 24 | 1571736832 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2612465070 | Jan 21 10:37:17 PM PST 24 | Jan 21 10:42:17 PM PST 24 | 60992896485 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/5.xbar_random.335833532 | Jan 21 10:33:06 PM PST 24 | Jan 21 10:33:47 PM PST 24 | 1570937277 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3050471362 | Jan 21 10:36:02 PM PST 24 | Jan 21 10:36:11 PM PST 24 | 37333897 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3384451712 | Jan 21 11:09:48 PM PST 24 | Jan 21 11:10:20 PM PST 24 | 5286798634 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/21.xbar_same_source.2233005698 | Jan 21 10:37:47 PM PST 24 | Jan 21 10:38:13 PM PST 24 | 1734713400 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.521560409 | Jan 21 10:33:18 PM PST 24 | Jan 21 10:33:57 PM PST 24 | 15870606257 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/24.xbar_smoke.3025166432 | Jan 21 10:38:17 PM PST 24 | Jan 21 10:38:22 PM PST 24 | 341765394 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2847187385 | Jan 21 10:35:58 PM PST 24 | Jan 21 10:39:45 PM PST 24 | 2092800689 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/10.xbar_smoke.330728013 | Jan 21 10:34:22 PM PST 24 | Jan 21 10:34:26 PM PST 24 | 436267494 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.1488845512 | Jan 21 10:50:13 PM PST 24 | Jan 21 10:50:33 PM PST 24 | 309340349 ps |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.2957495547 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7821180590 ps |
| CPU time | 211.85 seconds |
| Started | Jan 21 10:43:26 PM PST 24 |
| Finished | Jan 21 10:46:59 PM PST 24 |
| Peak memory | 211644 kb |
| Host | smart-d3d1a7f3-f805-4d37-8a83-2d7cb2cc71f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2957495547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2957495547 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2093329648 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 82362467011 ps |
| CPU time | 639.82 seconds |
| Started | Jan 21 10:32:10 PM PST 24 |
| Finished | Jan 21 10:42:56 PM PST 24 |
| Peak memory | 205744 kb |
| Host | smart-9ed10408-8014-47f7-9ef0-c51f1b3bf510 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2093329648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.2093329648 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1618517517 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 126594975679 ps |
| CPU time | 726.07 seconds |
| Started | Jan 21 10:45:47 PM PST 24 |
| Finished | Jan 21 10:57:54 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-dca2518a-df9c-4384-a0cf-ccf4d9a1ede3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1618517517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.1618517517 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1721042943 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 236710728046 ps |
| CPU time | 562.16 seconds |
| Started | Jan 21 10:32:29 PM PST 24 |
| Finished | Jan 21 10:41:54 PM PST 24 |
| Peak memory | 206732 kb |
| Host | smart-25d7973e-1ba9-434c-a15d-e661950ccac4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1721042943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1721042943 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.878175899 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 713305115 ps |
| CPU time | 75.32 seconds |
| Started | Jan 21 10:32:10 PM PST 24 |
| Finished | Jan 21 10:33:32 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-291d729a-32c5-4a48-b2df-c1a229fb0998 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=878175899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.878175899 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3649463845 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6490315640 ps |
| CPU time | 333.75 seconds |
| Started | Jan 21 10:33:11 PM PST 24 |
| Finished | Jan 21 10:38:46 PM PST 24 |
| Peak memory | 209616 kb |
| Host | smart-a6a6c2de-844f-4870-bb21-489102fedab4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3649463845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.3649463845 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.621244583 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5591629594 ps |
| CPU time | 33.04 seconds |
| Started | Jan 21 10:34:56 PM PST 24 |
| Finished | Jan 21 10:35:31 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-56f400fb-9f7f-45e3-a1fa-1ec1a2bbba67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=621244583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.621244583 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1871029286 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 23508244943 ps |
| CPU time | 820.15 seconds |
| Started | Jan 21 10:43:58 PM PST 24 |
| Finished | Jan 21 10:57:40 PM PST 24 |
| Peak memory | 219952 kb |
| Host | smart-28079b3b-c2aa-4283-8f13-36268707888c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1871029286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.1871029286 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3659704153 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 6483673371 ps |
| CPU time | 409.31 seconds |
| Started | Jan 21 10:39:08 PM PST 24 |
| Finished | Jan 21 10:45:58 PM PST 24 |
| Peak memory | 219872 kb |
| Host | smart-5438ec24-59b0-4e4e-a328-597361855573 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3659704153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.3659704153 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2960308911 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 4655160947 ps |
| CPU time | 343.29 seconds |
| Started | Jan 21 10:37:27 PM PST 24 |
| Finished | Jan 21 10:43:21 PM PST 24 |
| Peak memory | 209836 kb |
| Host | smart-47a3a930-4154-42ce-87ed-b5331fac3ebc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2960308911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.2960308911 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.609949472 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2452582392 ps |
| CPU time | 283.48 seconds |
| Started | Jan 21 10:32:56 PM PST 24 |
| Finished | Jan 21 10:37:45 PM PST 24 |
| Peak memory | 219844 kb |
| Host | smart-c68964a6-895c-415d-b8bf-c9393592c003 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=609949472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rese t_error.609949472 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.40821984 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 42933754713 ps |
| CPU time | 316.07 seconds |
| Started | Jan 21 10:37:48 PM PST 24 |
| Finished | Jan 21 10:43:11 PM PST 24 |
| Peak memory | 211612 kb |
| Host | smart-a6cb33c4-8865-4f41-be36-a5cc2e0a676a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=40821984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow _rsp.40821984 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1954182395 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9574706586 ps |
| CPU time | 517.85 seconds |
| Started | Jan 21 10:34:41 PM PST 24 |
| Finished | Jan 21 10:43:21 PM PST 24 |
| Peak memory | 219844 kb |
| Host | smart-644eedeb-4b7a-4dd7-a5f9-621c06c59a83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1954182395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1954182395 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3062563741 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 188262610 ps |
| CPU time | 98.15 seconds |
| Started | Jan 21 10:36:35 PM PST 24 |
| Finished | Jan 21 10:38:20 PM PST 24 |
| Peak memory | 207684 kb |
| Host | smart-189a4e48-a41d-4e09-b6a8-ff7c88f75cd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3062563741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.3062563741 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3686312553 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4317442486 ps |
| CPU time | 616.24 seconds |
| Started | Jan 21 10:44:19 PM PST 24 |
| Finished | Jan 21 10:54:37 PM PST 24 |
| Peak memory | 219956 kb |
| Host | smart-ab0775c5-8f38-466e-b5f8-e9f145b051c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3686312553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3686312553 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.787085557 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4682506497 ps |
| CPU time | 150.32 seconds |
| Started | Jan 21 10:44:54 PM PST 24 |
| Finished | Jan 21 10:47:26 PM PST 24 |
| Peak memory | 209096 kb |
| Host | smart-5c4f808a-6e71-42e5-997c-24ba42ffff1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=787085557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res et_error.787085557 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3148318755 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 886428391 ps |
| CPU time | 385.58 seconds |
| Started | Jan 21 10:45:15 PM PST 24 |
| Finished | Jan 21 10:51:45 PM PST 24 |
| Peak memory | 208716 kb |
| Host | smart-04d8881b-e1d3-480d-8e8e-9a637fd47c06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3148318755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.3148318755 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.136997735 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4074694113 ps |
| CPU time | 264.62 seconds |
| Started | Jan 21 10:45:12 PM PST 24 |
| Finished | Jan 21 10:49:44 PM PST 24 |
| Peak memory | 219880 kb |
| Host | smart-839ef877-30c5-44c0-a45f-255264faa193 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=136997735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_res et_error.136997735 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2083149892 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 150516391160 ps |
| CPU time | 675.61 seconds |
| Started | Jan 21 10:57:19 PM PST 24 |
| Finished | Jan 21 11:08:36 PM PST 24 |
| Peak memory | 211696 kb |
| Host | smart-e04b65b3-e84b-4ec0-b29a-1fd74176883d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2083149892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.2083149892 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3651345519 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 106759737 ps |
| CPU time | 9.87 seconds |
| Started | Jan 21 10:31:55 PM PST 24 |
| Finished | Jan 21 10:32:08 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-217a85f0-c247-44e9-be95-929be94ba94d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3651345519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3651345519 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3968504771 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 7793242787 ps |
| CPU time | 51.77 seconds |
| Started | Jan 21 10:31:49 PM PST 24 |
| Finished | Jan 21 10:32:43 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-c32807f7-ad40-4b98-b01f-cc14d9fb83e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3968504771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.3968504771 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.806898339 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 79178142 ps |
| CPU time | 2.49 seconds |
| Started | Jan 21 10:49:16 PM PST 24 |
| Finished | Jan 21 10:49:20 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-8adc53ee-dced-4bcf-b3b9-15e91f94d5c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=806898339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.806898339 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.2584503617 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 998652472 ps |
| CPU time | 37.77 seconds |
| Started | Jan 21 10:31:51 PM PST 24 |
| Finished | Jan 21 10:32:31 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-0b40fce1-157e-4a0e-9c3c-bcb85a9143b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2584503617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2584503617 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.2279032323 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 721854431 ps |
| CPU time | 18.88 seconds |
| Started | Jan 21 10:31:52 PM PST 24 |
| Finished | Jan 21 10:32:12 PM PST 24 |
| Peak memory | 211576 kb |
| Host | smart-1a54e01a-ee98-40ba-b160-d5fc52408267 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2279032323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.2279032323 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3685616617 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 81474972637 ps |
| CPU time | 228.34 seconds |
| Started | Jan 21 10:31:54 PM PST 24 |
| Finished | Jan 21 10:35:44 PM PST 24 |
| Peak memory | 204580 kb |
| Host | smart-4395988b-7360-4737-8c09-5750fe8886da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685616617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3685616617 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3894943299 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 13264963518 ps |
| CPU time | 108.35 seconds |
| Started | Jan 21 10:31:55 PM PST 24 |
| Finished | Jan 21 10:33:47 PM PST 24 |
| Peak memory | 204332 kb |
| Host | smart-5804185b-a96f-407b-95a1-839ce70a3066 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3894943299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3894943299 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3005155153 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 175762453 ps |
| CPU time | 24.66 seconds |
| Started | Jan 21 10:31:50 PM PST 24 |
| Finished | Jan 21 10:32:17 PM PST 24 |
| Peak memory | 211620 kb |
| Host | smart-1cc3bb41-89b8-4499-aed5-a828bb95646e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005155153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3005155153 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2093114040 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 110854036 ps |
| CPU time | 8.14 seconds |
| Started | Jan 21 10:31:55 PM PST 24 |
| Finished | Jan 21 10:32:06 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-8ba3bb16-b419-4306-a854-c1e627d832da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2093114040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2093114040 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.3861371297 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 128612177 ps |
| CPU time | 3.61 seconds |
| Started | Jan 21 10:31:48 PM PST 24 |
| Finished | Jan 21 10:31:54 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-a11b5b9d-94f7-48be-ad1c-7d468692477a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3861371297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3861371297 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2329898839 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 18239961954 ps |
| CPU time | 37.12 seconds |
| Started | Jan 21 10:31:55 PM PST 24 |
| Finished | Jan 21 10:32:35 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-de3757a2-c6d6-4a55-ba68-bf68000389b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329898839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2329898839 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.125451509 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 13919097766 ps |
| CPU time | 30.48 seconds |
| Started | Jan 21 10:31:55 PM PST 24 |
| Finished | Jan 21 10:32:29 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-156db289-d535-4a50-bfde-36fb83b1911b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=125451509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.125451509 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3925689958 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 42193483 ps |
| CPU time | 2.45 seconds |
| Started | Jan 21 10:31:55 PM PST 24 |
| Finished | Jan 21 10:32:01 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-3a0450be-33ae-44b3-9e55-9d405760f09b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925689958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3925689958 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.4064882647 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 2632723191 ps |
| CPU time | 152.27 seconds |
| Started | Jan 21 10:31:58 PM PST 24 |
| Finished | Jan 21 10:34:37 PM PST 24 |
| Peak memory | 207928 kb |
| Host | smart-320e566e-8d73-4005-a0e2-fdfe8162b30e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4064882647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.4064882647 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1942652787 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1242356744 ps |
| CPU time | 119.96 seconds |
| Started | Jan 21 10:31:57 PM PST 24 |
| Finished | Jan 21 10:34:00 PM PST 24 |
| Peak memory | 209180 kb |
| Host | smart-4bde23c9-d16a-478c-9506-3ef79272573d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1942652787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1942652787 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3254021870 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 767629841 ps |
| CPU time | 191.66 seconds |
| Started | Jan 21 10:31:56 PM PST 24 |
| Finished | Jan 21 10:35:11 PM PST 24 |
| Peak memory | 208128 kb |
| Host | smart-ad8a31f7-b362-4842-bd08-3c3f0f292b47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3254021870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.3254021870 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2885139775 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 164144216 ps |
| CPU time | 36.85 seconds |
| Started | Jan 21 10:31:58 PM PST 24 |
| Finished | Jan 21 10:32:40 PM PST 24 |
| Peak memory | 207512 kb |
| Host | smart-fb184018-3f1c-45eb-98ef-3d89081bd544 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2885139775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.2885139775 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3071002647 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 780004097 ps |
| CPU time | 25.17 seconds |
| Started | Jan 21 10:31:51 PM PST 24 |
| Finished | Jan 21 10:32:17 PM PST 24 |
| Peak memory | 204892 kb |
| Host | smart-1bd43e7f-b59f-4a4b-954e-55d36462b6e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3071002647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3071002647 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.759752059 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 58914421 ps |
| CPU time | 8.88 seconds |
| Started | Jan 21 10:32:06 PM PST 24 |
| Finished | Jan 21 10:32:23 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-7441071a-4717-4a4c-adb9-df663120258a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=759752059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.759752059 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3805845741 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 566354050 ps |
| CPU time | 13.42 seconds |
| Started | Jan 21 10:50:56 PM PST 24 |
| Finished | Jan 21 10:51:10 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-e11185c7-2fa7-40aa-aaab-676da1cf6d11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3805845741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3805845741 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.2998360066 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 170501576 ps |
| CPU time | 9.36 seconds |
| Started | Jan 21 10:32:09 PM PST 24 |
| Finished | Jan 21 10:32:25 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-e6388366-a3b9-47fd-b7da-fb17961b3fc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2998360066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2998360066 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.2717227271 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 85614561 ps |
| CPU time | 12.59 seconds |
| Started | Jan 21 10:56:29 PM PST 24 |
| Finished | Jan 21 10:56:42 PM PST 24 |
| Peak memory | 211576 kb |
| Host | smart-eaa2ca87-08a3-4272-849a-56e94fcfe01e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2717227271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2717227271 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3113144364 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 33656933405 ps |
| CPU time | 203.07 seconds |
| Started | Jan 21 10:31:58 PM PST 24 |
| Finished | Jan 21 10:35:26 PM PST 24 |
| Peak memory | 204608 kb |
| Host | smart-6ad3be81-84d7-42c1-8093-10ddce093fba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113144364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3113144364 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.290438777 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 4302449258 ps |
| CPU time | 43.96 seconds |
| Started | Jan 21 10:31:56 PM PST 24 |
| Finished | Jan 21 10:32:44 PM PST 24 |
| Peak memory | 204608 kb |
| Host | smart-4071973b-e29c-430f-8501-696831c28365 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=290438777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.290438777 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2515038710 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 767054068 ps |
| CPU time | 18.78 seconds |
| Started | Jan 21 10:32:00 PM PST 24 |
| Finished | Jan 21 10:32:26 PM PST 24 |
| Peak memory | 211596 kb |
| Host | smart-894becb1-d836-4051-b774-5c8d36747d38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515038710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2515038710 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.1492704978 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 225620330 ps |
| CPU time | 15.41 seconds |
| Started | Jan 21 10:32:09 PM PST 24 |
| Finished | Jan 21 10:32:31 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-3c04fa69-f323-400f-bbe9-0a2859a3fd5b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1492704978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1492704978 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.3594476470 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 27440678 ps |
| CPU time | 2.38 seconds |
| Started | Jan 21 10:31:56 PM PST 24 |
| Finished | Jan 21 10:32:02 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-58e12ee2-e6f9-4785-a3d6-787da2c0b13c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3594476470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3594476470 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.54183934 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 11547964349 ps |
| CPU time | 34.3 seconds |
| Started | Jan 21 10:31:55 PM PST 24 |
| Finished | Jan 21 10:32:33 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-2a4cde3f-f465-4a2a-9c64-51b3a8dd4de0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=54183934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.54183934 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.764800755 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3169556130 ps |
| CPU time | 27.24 seconds |
| Started | Jan 21 10:31:59 PM PST 24 |
| Finished | Jan 21 10:32:33 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-d2746752-81fd-48bb-bc3d-c071390fbf3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=764800755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.764800755 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3849703975 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 45064289 ps |
| CPU time | 2.44 seconds |
| Started | Jan 21 10:31:59 PM PST 24 |
| Finished | Jan 21 10:32:09 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-a4af0dcd-2d2b-4514-84bd-d47b5f18ce71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849703975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3849703975 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2283560513 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 158353424 ps |
| CPU time | 24.69 seconds |
| Started | Jan 21 10:32:10 PM PST 24 |
| Finished | Jan 21 10:32:41 PM PST 24 |
| Peak memory | 205552 kb |
| Host | smart-85d2cfd6-c8de-4d57-a2c1-9f6b61c65b7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2283560513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2283560513 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1746868012 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 400808727 ps |
| CPU time | 169.54 seconds |
| Started | Jan 21 10:32:08 PM PST 24 |
| Finished | Jan 21 10:35:05 PM PST 24 |
| Peak memory | 208088 kb |
| Host | smart-9966bcf3-3d27-4835-af30-0b5a3d16d03d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1746868012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.1746868012 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3216184243 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 874359760 ps |
| CPU time | 183.07 seconds |
| Started | Jan 21 10:32:17 PM PST 24 |
| Finished | Jan 21 10:35:23 PM PST 24 |
| Peak memory | 211552 kb |
| Host | smart-c30a69f6-05fc-424c-9576-720c516542f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3216184243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.3216184243 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.4125346810 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 66795392 ps |
| CPU time | 7.97 seconds |
| Started | Jan 21 10:32:07 PM PST 24 |
| Finished | Jan 21 10:32:23 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-f972e854-e3fd-48bb-9d4a-f63c66b5029d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4125346810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.4125346810 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.568259611 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 7328868569 ps |
| CPU time | 41.25 seconds |
| Started | Jan 21 10:34:36 PM PST 24 |
| Finished | Jan 21 10:35:19 PM PST 24 |
| Peak memory | 205612 kb |
| Host | smart-430ad164-2b01-4c3b-ad2d-8e4d76ae9d47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=568259611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.568259611 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1867584586 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 92002431571 ps |
| CPU time | 788.84 seconds |
| Started | Jan 21 10:34:36 PM PST 24 |
| Finished | Jan 21 10:47:47 PM PST 24 |
| Peak memory | 205764 kb |
| Host | smart-c7fc5e46-804a-43ca-a36c-3b8c350850de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1867584586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1867584586 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1624940540 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 188488068 ps |
| CPU time | 15.26 seconds |
| Started | Jan 21 10:34:36 PM PST 24 |
| Finished | Jan 21 10:34:53 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-292c6b30-4116-46d5-8959-0d5b4df463f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1624940540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1624940540 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.798538459 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 100024390 ps |
| CPU time | 4.81 seconds |
| Started | Jan 21 10:34:35 PM PST 24 |
| Finished | Jan 21 10:34:41 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-34516221-d337-4b5f-9748-497e71e6f055 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=798538459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.798538459 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.4177334483 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2143743898 ps |
| CPU time | 22.09 seconds |
| Started | Jan 21 10:34:32 PM PST 24 |
| Finished | Jan 21 10:34:56 PM PST 24 |
| Peak memory | 204156 kb |
| Host | smart-999dec8e-c1db-4087-ae43-f0fc4d1c3b26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4177334483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.4177334483 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.417750439 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 26524478956 ps |
| CPU time | 153.33 seconds |
| Started | Jan 21 10:34:41 PM PST 24 |
| Finished | Jan 21 10:37:16 PM PST 24 |
| Peak memory | 211580 kb |
| Host | smart-53f86df7-682f-4019-8570-c79a85d1d918 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=417750439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.417750439 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2456065976 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 29088825965 ps |
| CPU time | 194.11 seconds |
| Started | Jan 21 10:34:32 PM PST 24 |
| Finished | Jan 21 10:37:48 PM PST 24 |
| Peak memory | 211660 kb |
| Host | smart-79404313-ff6e-4221-bac8-f3b440ecbb37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2456065976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2456065976 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3836315553 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 219169260 ps |
| CPU time | 24.28 seconds |
| Started | Jan 21 10:34:41 PM PST 24 |
| Finished | Jan 21 10:35:07 PM PST 24 |
| Peak memory | 211540 kb |
| Host | smart-65309a1e-a739-4cd5-9057-1e41908d37f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836315553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3836315553 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.3859860231 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 590865547 ps |
| CPU time | 8.41 seconds |
| Started | Jan 21 10:34:36 PM PST 24 |
| Finished | Jan 21 10:34:46 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-395265d8-9da6-4c55-ad97-f0f494976151 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3859860231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3859860231 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.330728013 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 436267494 ps |
| CPU time | 3.15 seconds |
| Started | Jan 21 10:34:22 PM PST 24 |
| Finished | Jan 21 10:34:26 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-ddb47d66-2bba-4028-b450-519ad1882199 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=330728013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.330728013 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.721535913 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 23299424177 ps |
| CPU time | 38.2 seconds |
| Started | Jan 21 10:34:23 PM PST 24 |
| Finished | Jan 21 10:35:03 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-3254cfcb-cb1d-4faf-a71e-9d71621062f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=721535913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.721535913 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.923623811 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3744368347 ps |
| CPU time | 30.96 seconds |
| Started | Jan 21 10:34:34 PM PST 24 |
| Finished | Jan 21 10:35:06 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-c38b5a81-8780-47af-801e-896ff935320f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=923623811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.923623811 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.1754243386 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 41032576 ps |
| CPU time | 2.3 seconds |
| Started | Jan 21 10:34:23 PM PST 24 |
| Finished | Jan 21 10:34:27 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-6940f798-8ed9-4652-81d4-ae8f52e26fbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754243386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1754243386 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.2680801406 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4509786852 ps |
| CPU time | 122.72 seconds |
| Started | Jan 21 10:34:32 PM PST 24 |
| Finished | Jan 21 10:36:36 PM PST 24 |
| Peak memory | 208472 kb |
| Host | smart-6bd6f6d7-2c80-4bec-989b-9231429bfb59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2680801406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2680801406 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.9513672 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 7630868308 ps |
| CPU time | 252.27 seconds |
| Started | Jan 21 10:34:41 PM PST 24 |
| Finished | Jan 21 10:38:54 PM PST 24 |
| Peak memory | 210768 kb |
| Host | smart-90f8347f-10d2-4c9f-ab5f-91cf2b0e4968 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=9513672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.9513672 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1573749387 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 365770056 ps |
| CPU time | 131.38 seconds |
| Started | Jan 21 10:34:41 PM PST 24 |
| Finished | Jan 21 10:36:54 PM PST 24 |
| Peak memory | 207916 kb |
| Host | smart-aac656c4-0204-432c-9133-ce349c3a3adb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1573749387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.1573749387 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1301116179 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 122529062 ps |
| CPU time | 23.12 seconds |
| Started | Jan 21 10:34:41 PM PST 24 |
| Finished | Jan 21 10:35:06 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-4b5ccc4e-c8f6-49e1-b4df-ad47b698bcc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1301116179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1301116179 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3706519172 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2807447824 ps |
| CPU time | 31.21 seconds |
| Started | Jan 21 10:35:03 PM PST 24 |
| Finished | Jan 21 10:35:38 PM PST 24 |
| Peak memory | 211644 kb |
| Host | smart-fe42bb67-c139-48af-82b7-5955f9dd313e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3706519172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3706519172 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.1261805379 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 91217111379 ps |
| CPU time | 531.12 seconds |
| Started | Jan 21 10:35:03 PM PST 24 |
| Finished | Jan 21 10:43:58 PM PST 24 |
| Peak memory | 205876 kb |
| Host | smart-3c8c57c4-c276-4105-ba00-dc1630490b81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1261805379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.1261805379 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.430636464 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 119281533 ps |
| CPU time | 8.14 seconds |
| Started | Jan 21 10:34:56 PM PST 24 |
| Finished | Jan 21 10:35:06 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-2d8a7770-777d-4df3-8c7d-a18bf4b832d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=430636464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.430636464 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.2545449575 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 270663530 ps |
| CPU time | 20.35 seconds |
| Started | Jan 21 10:34:56 PM PST 24 |
| Finished | Jan 21 10:35:18 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-ff784d5a-c7c7-4625-b3b7-eb30bf192263 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2545449575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2545449575 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.667461272 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 104976342 ps |
| CPU time | 8.56 seconds |
| Started | Jan 21 10:34:45 PM PST 24 |
| Finished | Jan 21 10:34:57 PM PST 24 |
| Peak memory | 204684 kb |
| Host | smart-0e904125-0717-4a34-bbda-e8f2dd553a56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=667461272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.667461272 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.105498579 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 18498541529 ps |
| CPU time | 67.1 seconds |
| Started | Jan 21 10:34:47 PM PST 24 |
| Finished | Jan 21 10:35:58 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-9ac1fb09-4d4b-4863-a94f-eb9576ab9e32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=105498579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.105498579 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.950719411 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 102181303087 ps |
| CPU time | 257.42 seconds |
| Started | Jan 21 10:34:43 PM PST 24 |
| Finished | Jan 21 10:39:03 PM PST 24 |
| Peak memory | 204768 kb |
| Host | smart-248b4da2-c1ef-4f9b-ad42-0efd633e6bfb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=950719411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.950719411 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.2290407594 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 234400537 ps |
| CPU time | 11.73 seconds |
| Started | Jan 21 10:34:46 PM PST 24 |
| Finished | Jan 21 10:35:02 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-2feb8e54-a7e2-4fc9-8b4d-086fd19e6ebc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290407594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2290407594 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.2277757000 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 4334842662 ps |
| CPU time | 24.09 seconds |
| Started | Jan 21 10:34:57 PM PST 24 |
| Finished | Jan 21 10:35:22 PM PST 24 |
| Peak memory | 211620 kb |
| Host | smart-47318d67-04c9-4e79-9004-02a88eb05085 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2277757000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2277757000 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2147645405 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 315035395 ps |
| CPU time | 4.18 seconds |
| Started | Jan 21 10:34:41 PM PST 24 |
| Finished | Jan 21 10:34:47 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-d2195419-518a-4f6f-9225-d2f49cb4a343 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2147645405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2147645405 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.143763744 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 6089747222 ps |
| CPU time | 29.73 seconds |
| Started | Jan 21 10:34:48 PM PST 24 |
| Finished | Jan 21 10:35:21 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-3845ce3b-9849-450e-8c38-22d3a18d80c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=143763744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.143763744 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3193483146 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 20876495770 ps |
| CPU time | 37.46 seconds |
| Started | Jan 21 10:34:44 PM PST 24 |
| Finished | Jan 21 10:35:26 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-84ccc208-8918-4521-ac33-2ed4a5b39cba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3193483146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3193483146 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.900012317 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 82407337 ps |
| CPU time | 2.61 seconds |
| Started | Jan 21 10:34:47 PM PST 24 |
| Finished | Jan 21 10:34:53 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-2b56c160-c0a5-41e9-8385-8fd01e87c127 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900012317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.900012317 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.973606128 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 979039731 ps |
| CPU time | 91.01 seconds |
| Started | Jan 21 10:34:55 PM PST 24 |
| Finished | Jan 21 10:36:27 PM PST 24 |
| Peak memory | 208676 kb |
| Host | smart-66788687-1efc-4de3-8e91-fb360138e1df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=973606128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.973606128 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.31710521 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1854503271 ps |
| CPU time | 167.35 seconds |
| Started | Jan 21 10:34:55 PM PST 24 |
| Finished | Jan 21 10:37:44 PM PST 24 |
| Peak memory | 206612 kb |
| Host | smart-57f96e96-fc0b-441f-9942-407cee29d0c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=31710521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.31710521 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3216994690 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 4319556896 ps |
| CPU time | 338.51 seconds |
| Started | Jan 21 10:35:09 PM PST 24 |
| Finished | Jan 21 10:40:50 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-54ece8de-8c2b-4210-ad28-a5a34a431e92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3216994690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.3216994690 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3461719832 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 4936471338 ps |
| CPU time | 279.79 seconds |
| Started | Jan 21 10:34:53 PM PST 24 |
| Finished | Jan 21 10:39:34 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-a4c8a8a8-736e-4b8e-ae29-06e57391a7a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3461719832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.3461719832 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2017292573 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 320246192 ps |
| CPU time | 5.8 seconds |
| Started | Jan 21 10:34:56 PM PST 24 |
| Finished | Jan 21 10:35:04 PM PST 24 |
| Peak memory | 211600 kb |
| Host | smart-29c32a4f-7d00-4be3-b4bc-d2032aa9781b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2017292573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2017292573 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3539546563 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1697757163 ps |
| CPU time | 64.43 seconds |
| Started | Jan 21 10:35:10 PM PST 24 |
| Finished | Jan 21 10:36:17 PM PST 24 |
| Peak memory | 211588 kb |
| Host | smart-914e3984-7103-4893-a6ca-e5022dc4e6bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3539546563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3539546563 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3812613611 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 21479500645 ps |
| CPU time | 198.76 seconds |
| Started | Jan 21 10:35:11 PM PST 24 |
| Finished | Jan 21 10:38:32 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-af66be47-5e00-4900-aed9-66f4ba6c0224 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3812613611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.3812613611 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.671636779 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 113624924 ps |
| CPU time | 15.68 seconds |
| Started | Jan 21 10:55:55 PM PST 24 |
| Finished | Jan 21 10:56:12 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-4509dd89-afed-4d31-a113-87db05128ba3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=671636779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.671636779 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.3968137745 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 870407378 ps |
| CPU time | 24.05 seconds |
| Started | Jan 21 10:35:11 PM PST 24 |
| Finished | Jan 21 10:35:38 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-4650a2bf-192b-4cbd-95ab-45f2c57372a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3968137745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3968137745 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.2170939319 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 248206797 ps |
| CPU time | 9.74 seconds |
| Started | Jan 21 10:35:03 PM PST 24 |
| Finished | Jan 21 10:35:16 PM PST 24 |
| Peak memory | 204508 kb |
| Host | smart-a9787b2c-393d-4b5d-9489-debbc22e2c46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2170939319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2170939319 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3843196684 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 122469889963 ps |
| CPU time | 231.56 seconds |
| Started | Jan 21 11:20:27 PM PST 24 |
| Finished | Jan 21 11:24:21 PM PST 24 |
| Peak memory | 205112 kb |
| Host | smart-94e17a3e-148c-4646-b030-a32e5145633c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843196684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3843196684 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2352489725 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 30518065272 ps |
| CPU time | 219.12 seconds |
| Started | Jan 21 10:35:02 PM PST 24 |
| Finished | Jan 21 10:38:44 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-7ee87013-4ea2-4f07-98ce-1350a50324ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2352489725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2352489725 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.643528728 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 323337672 ps |
| CPU time | 15.4 seconds |
| Started | Jan 21 10:35:12 PM PST 24 |
| Finished | Jan 21 10:35:29 PM PST 24 |
| Peak memory | 211592 kb |
| Host | smart-4ac835e6-8ffa-43a4-bb81-da1c0cc1e0d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643528728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.643528728 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.726983311 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1466097753 ps |
| CPU time | 16.47 seconds |
| Started | Jan 21 11:10:51 PM PST 24 |
| Finished | Jan 21 11:11:09 PM PST 24 |
| Peak memory | 203548 kb |
| Host | smart-a3270279-fdc1-48f5-9f50-97bd8399a258 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=726983311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.726983311 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.2072608657 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 153160100 ps |
| CPU time | 3.57 seconds |
| Started | Jan 21 10:34:56 PM PST 24 |
| Finished | Jan 21 10:35:01 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-c7e80e39-23d6-4dd9-a2f4-e30381c25a97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2072608657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2072608657 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.4285748968 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3998145874 ps |
| CPU time | 30.69 seconds |
| Started | Jan 21 10:35:09 PM PST 24 |
| Finished | Jan 21 10:35:42 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-a77dcaa1-8f09-4951-a5e4-f4d205cb3c9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4285748968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.4285748968 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.1898111991 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 55922997 ps |
| CPU time | 2 seconds |
| Started | Jan 21 10:35:02 PM PST 24 |
| Finished | Jan 21 10:35:07 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-28c9fca5-b057-421f-87cd-d70eb9d74d64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898111991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.1898111991 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.3142724403 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 6225911727 ps |
| CPU time | 132.64 seconds |
| Started | Jan 21 10:57:49 PM PST 24 |
| Finished | Jan 21 11:00:09 PM PST 24 |
| Peak memory | 208592 kb |
| Host | smart-16b503a7-0afb-47c9-9bc7-f2b8f6229481 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3142724403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3142724403 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3085088684 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 21503404228 ps |
| CPU time | 353.38 seconds |
| Started | Jan 21 10:35:19 PM PST 24 |
| Finished | Jan 21 10:41:15 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-3a334f61-f041-4393-8f78-b4eea5f1c94b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3085088684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3085088684 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2916265949 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 765999068 ps |
| CPU time | 352.75 seconds |
| Started | Jan 21 10:35:35 PM PST 24 |
| Finished | Jan 21 10:41:29 PM PST 24 |
| Peak memory | 209568 kb |
| Host | smart-2315d70e-13a3-45d9-b84c-d7613f908dcd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2916265949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.2916265949 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1650071344 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 257906550 ps |
| CPU time | 92.18 seconds |
| Started | Jan 21 10:35:24 PM PST 24 |
| Finished | Jan 21 10:36:58 PM PST 24 |
| Peak memory | 209260 kb |
| Host | smart-7d096c3f-ea1f-482a-8af1-702e9777e4c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1650071344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.1650071344 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1500097423 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 122623664 ps |
| CPU time | 11.78 seconds |
| Started | Jan 21 11:07:46 PM PST 24 |
| Finished | Jan 21 11:07:59 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-2b13f727-69df-4713-8f97-3b8926328304 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1500097423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1500097423 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.4013549489 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 643843974 ps |
| CPU time | 25.32 seconds |
| Started | Jan 21 10:35:35 PM PST 24 |
| Finished | Jan 21 10:36:01 PM PST 24 |
| Peak memory | 211508 kb |
| Host | smart-c28d40a4-5d45-4755-92ad-25b0ab6630e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4013549489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.4013549489 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.3230008748 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 186862578608 ps |
| CPU time | 259.1 seconds |
| Started | Jan 21 10:35:26 PM PST 24 |
| Finished | Jan 21 10:39:47 PM PST 24 |
| Peak memory | 206064 kb |
| Host | smart-03aa1009-9f17-40a0-86eb-a59ac15878d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3230008748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.3230008748 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3137366223 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 232169491 ps |
| CPU time | 8.7 seconds |
| Started | Jan 21 10:35:35 PM PST 24 |
| Finished | Jan 21 10:35:45 PM PST 24 |
| Peak memory | 203312 kb |
| Host | smart-830147d2-5095-4a02-a0f5-a52c27ee4cba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3137366223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3137366223 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.2227202365 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 265785468 ps |
| CPU time | 9.37 seconds |
| Started | Jan 21 10:35:35 PM PST 24 |
| Finished | Jan 21 10:35:46 PM PST 24 |
| Peak memory | 203324 kb |
| Host | smart-32737392-94f5-4c1d-8160-69cb607c7829 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2227202365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2227202365 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.493382427 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 90470532 ps |
| CPU time | 9.71 seconds |
| Started | Jan 21 10:35:34 PM PST 24 |
| Finished | Jan 21 10:35:45 PM PST 24 |
| Peak memory | 204500 kb |
| Host | smart-656980e8-3fba-4839-bc52-5fff88fcdf52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=493382427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.493382427 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.30845835 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 154407626242 ps |
| CPU time | 275.96 seconds |
| Started | Jan 21 10:35:22 PM PST 24 |
| Finished | Jan 21 10:40:00 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-bece6098-5a10-43a3-a249-3205190741bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=30845835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.30845835 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2633966534 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 24497150656 ps |
| CPU time | 164.67 seconds |
| Started | Jan 21 10:35:35 PM PST 24 |
| Finished | Jan 21 10:38:21 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-f650cb3b-4d1d-48b8-8b14-919552acde49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2633966534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2633966534 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3894312369 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 189858113 ps |
| CPU time | 29.35 seconds |
| Started | Jan 21 10:35:24 PM PST 24 |
| Finished | Jan 21 10:35:55 PM PST 24 |
| Peak memory | 211772 kb |
| Host | smart-8dd311d5-e041-4b2c-9b0f-a513d580d882 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894312369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3894312369 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.2449234151 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 6544353541 ps |
| CPU time | 24 seconds |
| Started | Jan 21 10:35:24 PM PST 24 |
| Finished | Jan 21 10:35:50 PM PST 24 |
| Peak memory | 211640 kb |
| Host | smart-df23a53f-8bf0-4005-902e-7da55f76317b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2449234151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2449234151 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1942832376 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 54278023 ps |
| CPU time | 2.3 seconds |
| Started | Jan 21 10:35:18 PM PST 24 |
| Finished | Jan 21 10:35:23 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-e8b630d9-1d6f-479d-b366-6b5590be6374 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1942832376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1942832376 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.7591808 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 13109621411 ps |
| CPU time | 34.77 seconds |
| Started | Jan 21 10:35:34 PM PST 24 |
| Finished | Jan 21 10:36:10 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-6cb0439d-a3cb-4960-88a8-28d3898763d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=7591808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.7591808 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.267925378 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 18836524744 ps |
| CPU time | 43.35 seconds |
| Started | Jan 21 10:35:21 PM PST 24 |
| Finished | Jan 21 10:36:06 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-f54aa9c2-1384-4b4c-835e-e466177a40d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=267925378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.267925378 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1812186181 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 34608771 ps |
| CPU time | 2.24 seconds |
| Started | Jan 21 10:35:35 PM PST 24 |
| Finished | Jan 21 10:35:38 PM PST 24 |
| Peak memory | 203304 kb |
| Host | smart-89db18c3-a3c9-4162-a8f5-99515c44b191 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812186181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1812186181 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.4176381069 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 4147029040 ps |
| CPU time | 134.68 seconds |
| Started | Jan 21 10:35:38 PM PST 24 |
| Finished | Jan 21 10:37:54 PM PST 24 |
| Peak memory | 206984 kb |
| Host | smart-2dcf9223-e65a-4cec-b7dc-fd8b2855c389 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4176381069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.4176381069 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.4154914427 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 7185425526 ps |
| CPU time | 186.34 seconds |
| Started | Jan 21 10:35:33 PM PST 24 |
| Finished | Jan 21 10:38:40 PM PST 24 |
| Peak memory | 208360 kb |
| Host | smart-5106ae83-64ad-4303-80fe-a8bcd5dec6e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4154914427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4154914427 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.194153773 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1514784924 ps |
| CPU time | 178.23 seconds |
| Started | Jan 21 10:35:38 PM PST 24 |
| Finished | Jan 21 10:38:38 PM PST 24 |
| Peak memory | 211116 kb |
| Host | smart-2859900d-3379-4214-bfe7-d393aacdee29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=194153773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand _reset.194153773 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.4228935663 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 218034837 ps |
| CPU time | 38.82 seconds |
| Started | Jan 21 10:35:34 PM PST 24 |
| Finished | Jan 21 10:36:14 PM PST 24 |
| Peak memory | 207236 kb |
| Host | smart-c879ce0f-5f75-4c18-95c1-1cbc2dc611d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4228935663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.4228935663 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.1723234882 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 85225247 ps |
| CPU time | 14.65 seconds |
| Started | Jan 21 10:35:31 PM PST 24 |
| Finished | Jan 21 10:35:47 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-cf3dceab-2cd7-4e26-9a3d-81b6b8022c19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1723234882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1723234882 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2608976415 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1455985988 ps |
| CPU time | 47.3 seconds |
| Started | Jan 21 10:35:45 PM PST 24 |
| Finished | Jan 21 10:36:41 PM PST 24 |
| Peak memory | 204616 kb |
| Host | smart-cf91411e-7fd7-47b1-b7a1-2147257f4440 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2608976415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2608976415 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3909209904 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1132461533 ps |
| CPU time | 19.49 seconds |
| Started | Jan 21 10:35:51 PM PST 24 |
| Finished | Jan 21 10:36:21 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-f351adc7-f209-4142-aa90-aa6abbab0c90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3909209904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3909209904 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.2681314847 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1984245982 ps |
| CPU time | 29.23 seconds |
| Started | Jan 21 10:35:48 PM PST 24 |
| Finished | Jan 21 10:36:25 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-c37528d0-5a94-4b75-8683-72770ebfb897 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2681314847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2681314847 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.3813809350 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 2798350907 ps |
| CPU time | 45.28 seconds |
| Started | Jan 21 10:35:45 PM PST 24 |
| Finished | Jan 21 10:36:39 PM PST 24 |
| Peak memory | 205012 kb |
| Host | smart-c950dfd9-7975-4d96-8575-8f3e6329551c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3813809350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3813809350 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.630610457 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 48122189353 ps |
| CPU time | 60.77 seconds |
| Started | Jan 21 10:54:52 PM PST 24 |
| Finished | Jan 21 10:55:59 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-9a4ada00-f5ba-4854-ae5f-6bfeb5f7ade6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=630610457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.630610457 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.2751831589 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 23742445269 ps |
| CPU time | 213.6 seconds |
| Started | Jan 21 10:55:39 PM PST 24 |
| Finished | Jan 21 10:59:13 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-7607a5e7-9371-4a08-aa5c-3537e3e9abc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2751831589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2751831589 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2695061915 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 214050948 ps |
| CPU time | 26.34 seconds |
| Started | Jan 21 10:55:35 PM PST 24 |
| Finished | Jan 21 10:56:04 PM PST 24 |
| Peak memory | 211588 kb |
| Host | smart-95940c4e-5b93-4e06-b745-338e7544d737 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695061915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2695061915 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.1459810150 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 183607122 ps |
| CPU time | 14.54 seconds |
| Started | Jan 21 10:35:48 PM PST 24 |
| Finished | Jan 21 10:36:11 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-d6aab1e9-f649-4bd5-82ee-ee1a68fe5dd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1459810150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1459810150 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.1618728629 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 339930108 ps |
| CPU time | 3.83 seconds |
| Started | Jan 21 10:35:34 PM PST 24 |
| Finished | Jan 21 10:35:39 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-bf1d0892-1c2e-4193-93f9-4cd0dacdda86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1618728629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1618728629 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3931819218 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 11094878399 ps |
| CPU time | 35.83 seconds |
| Started | Jan 21 10:35:41 PM PST 24 |
| Finished | Jan 21 10:36:19 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-ecfef6ae-589f-44b4-9db7-528adf8cf50b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931819218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3931819218 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3762183538 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 5625078012 ps |
| CPU time | 31.9 seconds |
| Started | Jan 21 10:35:41 PM PST 24 |
| Finished | Jan 21 10:36:15 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-af2deead-aaec-44ff-a1d5-32aedbcf0285 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3762183538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3762183538 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3311860294 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 31825266 ps |
| CPU time | 2.28 seconds |
| Started | Jan 21 10:35:34 PM PST 24 |
| Finished | Jan 21 10:35:37 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-9c881871-9c7b-45ec-a3d8-0a376b9e34fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311860294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3311860294 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.1350440847 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2179775556 ps |
| CPU time | 60.87 seconds |
| Started | Jan 21 10:35:49 PM PST 24 |
| Finished | Jan 21 10:36:59 PM PST 24 |
| Peak memory | 205224 kb |
| Host | smart-45c6154c-0440-4ba7-9cb8-7dbdce20bdc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1350440847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1350440847 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.693662882 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2933384897 ps |
| CPU time | 142.58 seconds |
| Started | Jan 21 10:35:48 PM PST 24 |
| Finished | Jan 21 10:38:19 PM PST 24 |
| Peak memory | 207276 kb |
| Host | smart-4a57cd5d-0c12-4c06-a6cc-2e2317bf4676 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=693662882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.693662882 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2847187385 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 2092800689 ps |
| CPU time | 220.06 seconds |
| Started | Jan 21 10:35:58 PM PST 24 |
| Finished | Jan 21 10:39:45 PM PST 24 |
| Peak memory | 209152 kb |
| Host | smart-bd4ef598-5bd0-4b21-ac5e-31fe60dbe7ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2847187385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.2847187385 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.2549715916 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 895496914 ps |
| CPU time | 200.34 seconds |
| Started | Jan 21 10:35:51 PM PST 24 |
| Finished | Jan 21 10:39:21 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-3a8c1af8-1dfc-463b-bb79-d1368a6ad984 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2549715916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.2549715916 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.3939777138 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 449275416 ps |
| CPU time | 17.37 seconds |
| Started | Jan 21 10:35:58 PM PST 24 |
| Finished | Jan 21 10:36:22 PM PST 24 |
| Peak memory | 211512 kb |
| Host | smart-ca50f3aa-4da1-48fb-ab4c-523fac19dfdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3939777138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3939777138 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.1582373755 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2076517550 ps |
| CPU time | 23.14 seconds |
| Started | Jan 21 10:49:44 PM PST 24 |
| Finished | Jan 21 10:50:09 PM PST 24 |
| Peak memory | 204104 kb |
| Host | smart-4d0a066f-5a0d-4ec9-8145-25334cc0655d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1582373755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1582373755 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2379472304 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 53578751767 ps |
| CPU time | 392.27 seconds |
| Started | Jan 21 11:01:13 PM PST 24 |
| Finished | Jan 21 11:07:47 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-c611d53b-aa79-41b7-bfa8-6826070ea3e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2379472304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.2379472304 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.430763073 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 66743881 ps |
| CPU time | 7.72 seconds |
| Started | Jan 21 10:36:03 PM PST 24 |
| Finished | Jan 21 10:36:17 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-362e30bc-4581-4455-9895-0da48f903933 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=430763073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.430763073 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2325555946 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 635614086 ps |
| CPU time | 6.65 seconds |
| Started | Jan 21 10:35:58 PM PST 24 |
| Finished | Jan 21 10:36:12 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-d1c47f90-8610-48d1-a6dc-bd2aa704862a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2325555946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2325555946 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.1579001320 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 308008414 ps |
| CPU time | 7.47 seconds |
| Started | Jan 21 10:35:57 PM PST 24 |
| Finished | Jan 21 10:36:12 PM PST 24 |
| Peak memory | 204020 kb |
| Host | smart-2f2740af-d510-4fbf-b2e8-ac549e99a9e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1579001320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1579001320 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.456626078 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 17438668535 ps |
| CPU time | 103.97 seconds |
| Started | Jan 21 10:35:59 PM PST 24 |
| Finished | Jan 21 10:37:50 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-2a1fe71c-b92a-4d2b-9545-056f68cd3a49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=456626078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.456626078 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.747895184 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 14753683772 ps |
| CPU time | 103.79 seconds |
| Started | Jan 21 10:35:56 PM PST 24 |
| Finished | Jan 21 10:37:48 PM PST 24 |
| Peak memory | 204608 kb |
| Host | smart-68e5eaae-4f0c-4203-a46a-3a6a85fd833d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=747895184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.747895184 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.330387764 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 36820035 ps |
| CPU time | 3.89 seconds |
| Started | Jan 21 10:36:03 PM PST 24 |
| Finished | Jan 21 10:36:13 PM PST 24 |
| Peak memory | 203900 kb |
| Host | smart-01c7ce83-d342-4dce-b86f-5112f2776bff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330387764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.330387764 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.541041150 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 145870915 ps |
| CPU time | 12.49 seconds |
| Started | Jan 21 10:35:59 PM PST 24 |
| Finished | Jan 21 10:36:18 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-c6fbb3a6-75b0-48ab-9cc9-997f9f6dbdbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=541041150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.541041150 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.2041258455 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 117521207 ps |
| CPU time | 3.25 seconds |
| Started | Jan 21 10:35:49 PM PST 24 |
| Finished | Jan 21 10:36:02 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-dfbbe0e0-86ae-4e12-9520-ca3c4e6c6bd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2041258455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2041258455 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1323644622 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 12187025998 ps |
| CPU time | 24.92 seconds |
| Started | Jan 21 10:35:59 PM PST 24 |
| Finished | Jan 21 10:36:31 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-952f7449-b07a-4c94-89ae-b69068a959e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323644622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1323644622 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.404796814 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 9222447686 ps |
| CPU time | 38.15 seconds |
| Started | Jan 21 10:35:57 PM PST 24 |
| Finished | Jan 21 10:36:43 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-e66aefd0-7f4f-4f98-b8e2-c91c8c99e25a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=404796814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.404796814 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3603893890 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 109041457 ps |
| CPU time | 2.29 seconds |
| Started | Jan 21 10:35:57 PM PST 24 |
| Finished | Jan 21 10:36:06 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-8f873277-5a32-457d-ae3a-48e554955486 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603893890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3603893890 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.1995901372 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 106354620 ps |
| CPU time | 12.55 seconds |
| Started | Jan 21 10:36:05 PM PST 24 |
| Finished | Jan 21 10:36:22 PM PST 24 |
| Peak memory | 205100 kb |
| Host | smart-0b9b993b-2e4e-4189-9d16-09e142b67712 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1995901372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1995901372 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.4065946271 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 5503249691 ps |
| CPU time | 30.37 seconds |
| Started | Jan 21 10:52:19 PM PST 24 |
| Finished | Jan 21 10:52:53 PM PST 24 |
| Peak memory | 205132 kb |
| Host | smart-dde6faf0-190a-45bd-9cf8-17d0820f7963 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4065946271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.4065946271 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.434287283 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4988212897 ps |
| CPU time | 226.1 seconds |
| Started | Jan 21 10:56:10 PM PST 24 |
| Finished | Jan 21 10:59:58 PM PST 24 |
| Peak memory | 209508 kb |
| Host | smart-7afc31e0-4834-4d88-a323-9be1706ee2da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=434287283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand _reset.434287283 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.1680631502 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 262343764 ps |
| CPU time | 70.83 seconds |
| Started | Jan 21 10:57:28 PM PST 24 |
| Finished | Jan 21 10:58:44 PM PST 24 |
| Peak memory | 208128 kb |
| Host | smart-6491d46e-6c02-43a4-89e0-0f2787eb49f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1680631502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.1680631502 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3730210605 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 900137712 ps |
| CPU time | 27.72 seconds |
| Started | Jan 21 10:36:06 PM PST 24 |
| Finished | Jan 21 10:36:38 PM PST 24 |
| Peak memory | 204760 kb |
| Host | smart-816cfc00-1333-4093-ba3e-f3d36a3c9d86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3730210605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3730210605 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.4016842885 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 705121093 ps |
| CPU time | 39.9 seconds |
| Started | Jan 21 11:36:36 PM PST 24 |
| Finished | Jan 21 11:37:19 PM PST 24 |
| Peak memory | 211712 kb |
| Host | smart-1d19f53b-9edb-4cd2-ba39-1c7ede3b7821 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4016842885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.4016842885 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3278744090 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 13884175466 ps |
| CPU time | 87.28 seconds |
| Started | Jan 21 10:36:12 PM PST 24 |
| Finished | Jan 21 10:37:41 PM PST 24 |
| Peak memory | 205744 kb |
| Host | smart-e1ffbd53-38b2-4df9-8432-0e263f3a7540 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3278744090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.3278744090 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1515333235 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1806934849 ps |
| CPU time | 23.01 seconds |
| Started | Jan 21 10:53:43 PM PST 24 |
| Finished | Jan 21 10:54:07 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-9193074e-767a-403d-83d6-4d38cd6200fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1515333235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1515333235 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.1168618340 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 758971456 ps |
| CPU time | 19.13 seconds |
| Started | Jan 21 10:36:12 PM PST 24 |
| Finished | Jan 21 10:36:33 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-3d784d0c-d0a3-4cf5-a3db-71ec8e50da32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1168618340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1168618340 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.3843453792 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 224024374 ps |
| CPU time | 16.29 seconds |
| Started | Jan 21 10:50:05 PM PST 24 |
| Finished | Jan 21 10:50:22 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-9cf96db5-1cd1-4e8c-a056-6cd07f2129e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3843453792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3843453792 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3145076846 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 42138035419 ps |
| CPU time | 211.37 seconds |
| Started | Jan 21 10:50:02 PM PST 24 |
| Finished | Jan 21 10:53:34 PM PST 24 |
| Peak memory | 211696 kb |
| Host | smart-0e0ac1ee-8962-4c78-8dd5-2d18edb74bbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145076846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3145076846 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1834599063 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 120489297023 ps |
| CPU time | 352.32 seconds |
| Started | Jan 21 10:36:13 PM PST 24 |
| Finished | Jan 21 10:42:06 PM PST 24 |
| Peak memory | 211600 kb |
| Host | smart-dec8bf19-dcad-43cd-8d3f-001d7a20597a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1834599063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1834599063 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2873975426 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 63976827 ps |
| CPU time | 4.48 seconds |
| Started | Jan 21 10:55:51 PM PST 24 |
| Finished | Jan 21 10:55:57 PM PST 24 |
| Peak memory | 203980 kb |
| Host | smart-a1d66190-f3ce-485b-911f-901327dc2b1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873975426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2873975426 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.1011444050 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 638397042 ps |
| CPU time | 6.34 seconds |
| Started | Jan 21 10:36:13 PM PST 24 |
| Finished | Jan 21 10:36:21 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-3aa65362-53ea-4307-a3c9-430e36c2d6b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1011444050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1011444050 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.72070614 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 349941218 ps |
| CPU time | 3.44 seconds |
| Started | Jan 21 10:36:01 PM PST 24 |
| Finished | Jan 21 10:36:11 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-3e278d08-472d-4a9f-bb46-5bcfcb9b7330 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=72070614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.72070614 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1516281926 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 11404656913 ps |
| CPU time | 34.46 seconds |
| Started | Jan 21 10:36:03 PM PST 24 |
| Finished | Jan 21 10:36:43 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-3499173b-a8c8-453f-b9bb-4f4d9b9173dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516281926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1516281926 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3043879771 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 14155035025 ps |
| CPU time | 38.51 seconds |
| Started | Jan 21 10:36:03 PM PST 24 |
| Finished | Jan 21 10:36:47 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-7ab7adf2-1fe2-470d-910d-f95cf24d13df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3043879771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3043879771 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3050471362 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 37333897 ps |
| CPU time | 2.41 seconds |
| Started | Jan 21 10:36:02 PM PST 24 |
| Finished | Jan 21 10:36:11 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-aae74130-e415-4e26-83b5-c95ce9f8e2e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050471362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3050471362 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3474068772 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1356500808 ps |
| CPU time | 69.29 seconds |
| Started | Jan 21 10:42:06 PM PST 24 |
| Finished | Jan 21 10:43:16 PM PST 24 |
| Peak memory | 207264 kb |
| Host | smart-70042616-947c-42db-9fc5-10dd1f3eb27c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3474068772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3474068772 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.419010536 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1028049543 ps |
| CPU time | 102.25 seconds |
| Started | Jan 21 10:36:24 PM PST 24 |
| Finished | Jan 21 10:38:12 PM PST 24 |
| Peak memory | 207968 kb |
| Host | smart-8cda6385-a984-4577-a592-fb9c727253b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=419010536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.419010536 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1187337675 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 905522550 ps |
| CPU time | 332.73 seconds |
| Started | Jan 21 10:36:16 PM PST 24 |
| Finished | Jan 21 10:41:49 PM PST 24 |
| Peak memory | 209456 kb |
| Host | smart-e5964771-ee11-41cc-88e3-ac7c4230d281 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1187337675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.1187337675 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2072204831 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 104830913 ps |
| CPU time | 62.48 seconds |
| Started | Jan 21 10:36:24 PM PST 24 |
| Finished | Jan 21 10:37:32 PM PST 24 |
| Peak memory | 207352 kb |
| Host | smart-3bd1fc5f-9aad-4efa-aae0-a1cc9ee2ad24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2072204831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.2072204831 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1405296433 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 788854102 ps |
| CPU time | 18.12 seconds |
| Started | Jan 21 11:16:12 PM PST 24 |
| Finished | Jan 21 11:16:31 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-6d7ffe74-1c76-4a62-a14a-1e160bf449ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1405296433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1405296433 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.1488845512 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 309340349 ps |
| CPU time | 15.64 seconds |
| Started | Jan 21 10:50:13 PM PST 24 |
| Finished | Jan 21 10:50:33 PM PST 24 |
| Peak memory | 204060 kb |
| Host | smart-a5c95fc4-8460-40c7-970a-a45700915d17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1488845512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1488845512 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2288513779 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 55611362711 ps |
| CPU time | 301.48 seconds |
| Started | Jan 21 10:36:38 PM PST 24 |
| Finished | Jan 21 10:41:46 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-90387288-9f4f-4cbb-b693-983a6455c180 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2288513779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.2288513779 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3911035353 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 167637924 ps |
| CPU time | 16.98 seconds |
| Started | Jan 21 10:36:39 PM PST 24 |
| Finished | Jan 21 10:37:02 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-088ff6f4-b2fb-4494-a518-30c40e0400b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3911035353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3911035353 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.2525809330 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 219974021 ps |
| CPU time | 23.1 seconds |
| Started | Jan 21 10:36:37 PM PST 24 |
| Finished | Jan 21 10:37:07 PM PST 24 |
| Peak memory | 203592 kb |
| Host | smart-45d0291a-c67f-4b88-882c-c01c2c609c17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2525809330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2525809330 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.986273287 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1797203245 ps |
| CPU time | 23.42 seconds |
| Started | Jan 21 10:36:28 PM PST 24 |
| Finished | Jan 21 10:37:00 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-66383138-2fbc-401b-86df-4aa315d6815e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=986273287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.986273287 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3279868970 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 6352332120 ps |
| CPU time | 39.81 seconds |
| Started | Jan 21 10:36:29 PM PST 24 |
| Finished | Jan 21 10:37:18 PM PST 24 |
| Peak memory | 204500 kb |
| Host | smart-163ac074-2626-4973-96ac-36c8d293b78d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279868970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3279868970 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2737943720 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 52654515642 ps |
| CPU time | 186.81 seconds |
| Started | Jan 21 10:36:30 PM PST 24 |
| Finished | Jan 21 10:39:45 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-c948d1e6-57e4-44e4-8a89-8d0c94cab9ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2737943720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2737943720 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3557567339 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 249158194 ps |
| CPU time | 27.01 seconds |
| Started | Jan 21 10:36:27 PM PST 24 |
| Finished | Jan 21 10:36:59 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-64adf1bf-b171-4ebb-ac2d-6283a86347de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557567339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3557567339 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.2742752768 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 116419043 ps |
| CPU time | 9.12 seconds |
| Started | Jan 21 10:36:35 PM PST 24 |
| Finished | Jan 21 10:36:52 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-0825487e-ff6f-4597-9c78-9fa206aea465 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2742752768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2742752768 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.1336557041 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 32675615 ps |
| CPU time | 2.38 seconds |
| Started | Jan 21 10:36:22 PM PST 24 |
| Finished | Jan 21 10:36:32 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-6876b275-4996-4ee4-8ab4-cedcf7914be1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1336557041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1336557041 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2843303148 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 6287808773 ps |
| CPU time | 36.08 seconds |
| Started | Jan 21 10:36:22 PM PST 24 |
| Finished | Jan 21 10:37:05 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-47afe803-51ea-4690-b2b2-1d77e2b5930e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843303148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2843303148 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3382495162 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 11800660092 ps |
| CPU time | 30.98 seconds |
| Started | Jan 21 10:36:22 PM PST 24 |
| Finished | Jan 21 10:37:00 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-200bf0f4-f0d7-4a8d-85c2-56313ff0da4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3382495162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3382495162 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.692098790 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 62155045 ps |
| CPU time | 2.12 seconds |
| Started | Jan 21 10:52:15 PM PST 24 |
| Finished | Jan 21 10:52:19 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-87c6dc46-189a-48e8-bed6-858728a3ebfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692098790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.692098790 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.635857691 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 10316040166 ps |
| CPU time | 198.64 seconds |
| Started | Jan 21 10:36:33 PM PST 24 |
| Finished | Jan 21 10:39:59 PM PST 24 |
| Peak memory | 206072 kb |
| Host | smart-5a41a40f-7dde-480a-a9c1-44591db8f987 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=635857691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.635857691 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.334856523 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1175538050 ps |
| CPU time | 54.46 seconds |
| Started | Jan 21 11:29:29 PM PST 24 |
| Finished | Jan 21 11:30:27 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-2f03a36c-05ea-4b7a-aca2-9f60793c2393 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=334856523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.334856523 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.345107068 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 7064477 ps |
| CPU time | 4.92 seconds |
| Started | Jan 21 10:36:42 PM PST 24 |
| Finished | Jan 21 10:36:53 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-d73d42db-3228-4edf-994f-9e1a438a6bc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=345107068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res et_error.345107068 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.476130206 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 616552867 ps |
| CPU time | 25.73 seconds |
| Started | Jan 21 11:20:01 PM PST 24 |
| Finished | Jan 21 11:20:28 PM PST 24 |
| Peak memory | 211712 kb |
| Host | smart-c4df66b1-0aab-4cb2-9d3b-6d9f063d8c55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=476130206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.476130206 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2323366322 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1705979416 ps |
| CPU time | 30.51 seconds |
| Started | Jan 21 10:36:54 PM PST 24 |
| Finished | Jan 21 10:37:31 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-abacdb57-840b-404c-9f32-4e2e4fb2a859 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2323366322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2323366322 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1513728917 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 33059062751 ps |
| CPU time | 216.81 seconds |
| Started | Jan 21 10:36:48 PM PST 24 |
| Finished | Jan 21 10:40:32 PM PST 24 |
| Peak memory | 211640 kb |
| Host | smart-8f49690f-b4d1-46e4-9863-f4c076cf8a07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1513728917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.1513728917 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2329739113 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 3644253062 ps |
| CPU time | 28.56 seconds |
| Started | Jan 21 10:36:51 PM PST 24 |
| Finished | Jan 21 10:37:25 PM PST 24 |
| Peak memory | 203508 kb |
| Host | smart-4967e57e-9ef3-4316-9482-df8899e14564 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2329739113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2329739113 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.1446811623 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 151250835 ps |
| CPU time | 7.87 seconds |
| Started | Jan 21 10:36:54 PM PST 24 |
| Finished | Jan 21 10:37:08 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-25f54379-5897-4782-8b97-4f40db9d4f35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1446811623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1446811623 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.1726814740 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 281502736 ps |
| CPU time | 10.93 seconds |
| Started | Jan 21 10:36:41 PM PST 24 |
| Finished | Jan 21 10:36:58 PM PST 24 |
| Peak memory | 204136 kb |
| Host | smart-0db552eb-d62b-441e-a595-3b1a12276729 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1726814740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1726814740 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.530746081 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 24838610795 ps |
| CPU time | 139.99 seconds |
| Started | Jan 21 10:36:51 PM PST 24 |
| Finished | Jan 21 10:39:16 PM PST 24 |
| Peak memory | 204576 kb |
| Host | smart-5395c334-fe32-4988-8cef-174e6cda7620 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=530746081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.530746081 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1724926877 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2568468269 ps |
| CPU time | 12.66 seconds |
| Started | Jan 21 10:36:50 PM PST 24 |
| Finished | Jan 21 10:37:09 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-b26ef31f-cbd4-4eed-8b0f-397cdf802349 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1724926877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1724926877 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2840376767 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 97587308 ps |
| CPU time | 10.42 seconds |
| Started | Jan 21 10:36:43 PM PST 24 |
| Finished | Jan 21 10:37:00 PM PST 24 |
| Peak memory | 211568 kb |
| Host | smart-152da5a5-d308-4ae5-8318-33e2fd95e9e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840376767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2840376767 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.630094522 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1790710672 ps |
| CPU time | 25.63 seconds |
| Started | Jan 21 10:36:50 PM PST 24 |
| Finished | Jan 21 10:37:22 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-4a3e135f-8524-42cf-9f34-d7fa45513c8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=630094522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.630094522 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.2420353950 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 27123114 ps |
| CPU time | 2.17 seconds |
| Started | Jan 21 11:08:59 PM PST 24 |
| Finished | Jan 21 11:09:01 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-6a853ce1-0e5d-4883-a705-00c3a16fda56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2420353950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2420353950 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.776362525 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 6832018276 ps |
| CPU time | 33.16 seconds |
| Started | Jan 21 10:36:40 PM PST 24 |
| Finished | Jan 21 10:37:19 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-355556e2-06bf-4521-a60a-385987435750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=776362525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.776362525 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3057823388 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 6608029286 ps |
| CPU time | 20.75 seconds |
| Started | Jan 21 10:36:42 PM PST 24 |
| Finished | Jan 21 10:37:09 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-2e29370d-b5e1-488e-b57a-9cd3a92bdcc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3057823388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3057823388 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.816595633 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 28016894 ps |
| CPU time | 2.54 seconds |
| Started | Jan 21 10:36:42 PM PST 24 |
| Finished | Jan 21 10:36:51 PM PST 24 |
| Peak memory | 203584 kb |
| Host | smart-1bc05c2c-bdf2-4616-992c-a175917301c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816595633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.816595633 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.1649790954 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8211017316 ps |
| CPU time | 150.86 seconds |
| Started | Jan 21 10:36:59 PM PST 24 |
| Finished | Jan 21 10:39:40 PM PST 24 |
| Peak memory | 208204 kb |
| Host | smart-d9dda252-3f56-4007-a932-c093ae024afe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1649790954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1649790954 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3445702175 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2192847527 ps |
| CPU time | 57.6 seconds |
| Started | Jan 21 10:49:29 PM PST 24 |
| Finished | Jan 21 10:50:27 PM PST 24 |
| Peak memory | 204496 kb |
| Host | smart-d5f2824f-c21d-41bd-af79-f30df6e798fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3445702175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3445702175 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.2945134646 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 14055303217 ps |
| CPU time | 697.35 seconds |
| Started | Jan 21 10:36:58 PM PST 24 |
| Finished | Jan 21 10:48:46 PM PST 24 |
| Peak memory | 209496 kb |
| Host | smart-7b814cbc-8d00-48e8-a438-d96fbcb9b044 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2945134646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.2945134646 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2649207340 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1096252310 ps |
| CPU time | 163.57 seconds |
| Started | Jan 21 10:36:52 PM PST 24 |
| Finished | Jan 21 10:39:42 PM PST 24 |
| Peak memory | 210872 kb |
| Host | smart-2f5d9d27-5c40-4fcc-9ea1-56a0d0eb63a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2649207340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.2649207340 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.695253723 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 135530329 ps |
| CPU time | 8.79 seconds |
| Started | Jan 21 10:36:54 PM PST 24 |
| Finished | Jan 21 10:37:09 PM PST 24 |
| Peak memory | 204608 kb |
| Host | smart-126e52be-08f2-42ef-9ad8-d3af03e66f36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=695253723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.695253723 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.271626229 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 197076290 ps |
| CPU time | 15.28 seconds |
| Started | Jan 21 10:37:06 PM PST 24 |
| Finished | Jan 21 10:37:32 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-9a40dd64-6660-4e45-be6c-1b29e4533c75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=271626229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.271626229 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1062499269 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 140930770432 ps |
| CPU time | 544.7 seconds |
| Started | Jan 21 10:37:00 PM PST 24 |
| Finished | Jan 21 10:46:19 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-f060b892-f448-4f99-a24e-28ae0456e290 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1062499269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.1062499269 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.4245327500 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 14762609 ps |
| CPU time | 1.93 seconds |
| Started | Jan 21 10:37:01 PM PST 24 |
| Finished | Jan 21 10:37:17 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-fb9bad11-619d-418c-9cd8-0c5e72289d07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4245327500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.4245327500 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.2082988220 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 31941631 ps |
| CPU time | 3.03 seconds |
| Started | Jan 21 10:37:01 PM PST 24 |
| Finished | Jan 21 10:37:18 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-af559a86-dc52-4842-99a3-72f4aadbbc37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2082988220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2082988220 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.2364788024 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 16805619 ps |
| CPU time | 2.21 seconds |
| Started | Jan 21 10:37:06 PM PST 24 |
| Finished | Jan 21 10:37:19 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-125dc804-72b2-4fa3-8c78-0cec4122bd54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2364788024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2364788024 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.783075148 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9109505161 ps |
| CPU time | 40.14 seconds |
| Started | Jan 21 10:37:04 PM PST 24 |
| Finished | Jan 21 10:37:56 PM PST 24 |
| Peak memory | 204216 kb |
| Host | smart-62c4a000-3a6f-47d8-9d8c-65ffc48c2616 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=783075148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.783075148 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.792517526 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 14812196877 ps |
| CPU time | 89.35 seconds |
| Started | Jan 21 10:37:03 PM PST 24 |
| Finished | Jan 21 10:38:45 PM PST 24 |
| Peak memory | 204728 kb |
| Host | smart-6a38b76c-5b4e-4e46-8020-941a2bb43719 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=792517526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.792517526 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1748441819 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 88633493 ps |
| CPU time | 10.66 seconds |
| Started | Jan 21 10:37:01 PM PST 24 |
| Finished | Jan 21 10:37:25 PM PST 24 |
| Peak memory | 211524 kb |
| Host | smart-712b0082-32d2-4b69-91f6-7e5eed2f6ba0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748441819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1748441819 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.3640817800 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 881861934 ps |
| CPU time | 20.53 seconds |
| Started | Jan 21 10:37:02 PM PST 24 |
| Finished | Jan 21 10:37:36 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-0cb89c09-7c8d-4385-845d-002350c5f812 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3640817800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3640817800 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.3246155043 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1039340752 ps |
| CPU time | 4.17 seconds |
| Started | Jan 21 10:36:56 PM PST 24 |
| Finished | Jan 21 10:37:12 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-f4cf2583-349c-49d0-b1c8-342fe913dcea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3246155043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3246155043 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.4226640297 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 8410346842 ps |
| CPU time | 30.08 seconds |
| Started | Jan 21 10:36:51 PM PST 24 |
| Finished | Jan 21 10:37:27 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-1cbbf311-e601-4bfc-affa-42690993e92c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226640297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.4226640297 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3648002024 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3195250310 ps |
| CPU time | 27.9 seconds |
| Started | Jan 21 10:36:53 PM PST 24 |
| Finished | Jan 21 10:37:27 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-9270b1d6-19ef-48a3-acd9-95e2f00f8875 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3648002024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3648002024 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2352338274 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 46103393 ps |
| CPU time | 2.05 seconds |
| Started | Jan 21 10:36:55 PM PST 24 |
| Finished | Jan 21 10:37:07 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-d5938035-6471-4bf9-8eac-2cb7a0bfe8af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352338274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2352338274 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.772056986 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3619573844 ps |
| CPU time | 142.5 seconds |
| Started | Jan 21 10:37:03 PM PST 24 |
| Finished | Jan 21 10:39:38 PM PST 24 |
| Peak memory | 206804 kb |
| Host | smart-eb3b7589-0106-45b9-bf30-5edb0921121e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=772056986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.772056986 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.3306708293 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3160816453 ps |
| CPU time | 59.13 seconds |
| Started | Jan 21 10:37:11 PM PST 24 |
| Finished | Jan 21 10:38:20 PM PST 24 |
| Peak memory | 211660 kb |
| Host | smart-c909826b-a4c2-44be-983c-69b54196269b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3306708293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3306708293 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2211897440 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 20480022 ps |
| CPU time | 37.22 seconds |
| Started | Jan 21 10:37:12 PM PST 24 |
| Finished | Jan 21 10:37:58 PM PST 24 |
| Peak memory | 206452 kb |
| Host | smart-61f1efed-9fc7-44c6-9af1-6e0df0365b49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2211897440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.2211897440 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2823890507 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3848896280 ps |
| CPU time | 298.34 seconds |
| Started | Jan 21 10:37:12 PM PST 24 |
| Finished | Jan 21 10:42:19 PM PST 24 |
| Peak memory | 219884 kb |
| Host | smart-34d65497-67c8-4ecb-b936-ff265723ab8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2823890507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.2823890507 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.823822125 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 617477635 ps |
| CPU time | 23.34 seconds |
| Started | Jan 21 10:37:02 PM PST 24 |
| Finished | Jan 21 10:37:38 PM PST 24 |
| Peak memory | 204820 kb |
| Host | smart-887178cc-2344-426f-9f3b-ddfdf242efc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=823822125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.823822125 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.3171974773 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 79642149 ps |
| CPU time | 12.2 seconds |
| Started | Jan 21 10:32:09 PM PST 24 |
| Finished | Jan 21 10:32:28 PM PST 24 |
| Peak memory | 211568 kb |
| Host | smart-ce23d3b6-c6ff-4c87-81ce-abcb3a697296 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3171974773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3171974773 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1189861592 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 23565429587 ps |
| CPU time | 180.95 seconds |
| Started | Jan 21 10:32:10 PM PST 24 |
| Finished | Jan 21 10:35:17 PM PST 24 |
| Peak memory | 206052 kb |
| Host | smart-685deddc-386b-4def-b80e-b6f332c9ba11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1189861592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.1189861592 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2738262944 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 194012090 ps |
| CPU time | 10.95 seconds |
| Started | Jan 21 10:32:21 PM PST 24 |
| Finished | Jan 21 10:32:34 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-37200db0-e919-4053-a46b-d68d4d194840 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2738262944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2738262944 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.2665517073 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 170912648 ps |
| CPU time | 6.79 seconds |
| Started | Jan 21 10:55:59 PM PST 24 |
| Finished | Jan 21 10:56:08 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-5dbd3378-4eb6-4a62-b738-451429163cc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2665517073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2665517073 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.4213354389 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 120127507 ps |
| CPU time | 14.46 seconds |
| Started | Jan 21 10:32:11 PM PST 24 |
| Finished | Jan 21 10:32:32 PM PST 24 |
| Peak memory | 211588 kb |
| Host | smart-9f9bfc28-12ee-4c62-88bb-6d9efe442173 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4213354389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.4213354389 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1191476493 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 20854696694 ps |
| CPU time | 111.63 seconds |
| Started | Jan 21 10:32:10 PM PST 24 |
| Finished | Jan 21 10:34:08 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-716dd6b8-81ea-4ad0-a63f-ba5cf1c69e4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191476493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1191476493 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3879816401 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 25991958509 ps |
| CPU time | 243.89 seconds |
| Started | Jan 21 10:32:17 PM PST 24 |
| Finished | Jan 21 10:36:23 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-c1f078f6-2940-40e5-a5e7-94b01b96b660 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3879816401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3879816401 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.989190057 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 210046632 ps |
| CPU time | 11.76 seconds |
| Started | Jan 21 10:32:11 PM PST 24 |
| Finished | Jan 21 10:32:29 PM PST 24 |
| Peak memory | 211592 kb |
| Host | smart-5dc3df8a-74f8-46b1-8d29-bd23210ffb68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989190057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.989190057 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.3186498981 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1179849256 ps |
| CPU time | 27.86 seconds |
| Started | Jan 21 10:32:22 PM PST 24 |
| Finished | Jan 21 10:32:52 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-6e42b833-494a-492c-87e7-4d9129904104 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3186498981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3186498981 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.1996417637 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 37678728 ps |
| CPU time | 2.31 seconds |
| Started | Jan 21 10:32:12 PM PST 24 |
| Finished | Jan 21 10:32:20 PM PST 24 |
| Peak memory | 203332 kb |
| Host | smart-c0b0aca0-326a-40d5-ba9f-1b02af0ff35f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1996417637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1996417637 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1433669926 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 7106152761 ps |
| CPU time | 32.86 seconds |
| Started | Jan 21 10:32:12 PM PST 24 |
| Finished | Jan 21 10:32:50 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-4b1d2a63-990b-4c56-baec-189e4659961b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433669926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1433669926 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3087770545 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3359212353 ps |
| CPU time | 27.56 seconds |
| Started | Jan 21 10:32:12 PM PST 24 |
| Finished | Jan 21 10:32:45 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-29b0ddd4-743e-49d8-a1f9-6671938f3df6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3087770545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3087770545 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2497499920 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 29952614 ps |
| CPU time | 2.65 seconds |
| Started | Jan 21 10:32:11 PM PST 24 |
| Finished | Jan 21 10:32:19 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-3245ccb0-ea07-4308-990a-a43930f132ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497499920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2497499920 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3887001589 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4352186817 ps |
| CPU time | 90.29 seconds |
| Started | Jan 21 10:32:22 PM PST 24 |
| Finished | Jan 21 10:33:54 PM PST 24 |
| Peak memory | 205812 kb |
| Host | smart-f6cf59a1-d8c0-4143-ab34-b0843573ab13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3887001589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3887001589 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1646291213 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 1795873366 ps |
| CPU time | 199.55 seconds |
| Started | Jan 21 10:32:18 PM PST 24 |
| Finished | Jan 21 10:35:40 PM PST 24 |
| Peak memory | 206784 kb |
| Host | smart-3bb94d96-59f1-4422-a49c-0ce701dfe771 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1646291213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1646291213 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.4269814232 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1209156345 ps |
| CPU time | 203.19 seconds |
| Started | Jan 21 11:14:09 PM PST 24 |
| Finished | Jan 21 11:17:34 PM PST 24 |
| Peak memory | 209036 kb |
| Host | smart-80311371-4c2d-4b39-9e6e-eb90200515ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4269814232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.4269814232 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.490813172 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 213981074 ps |
| CPU time | 67.21 seconds |
| Started | Jan 21 10:52:18 PM PST 24 |
| Finished | Jan 21 10:53:29 PM PST 24 |
| Peak memory | 206812 kb |
| Host | smart-eebf8508-16e1-4ea3-af99-bfe8d11a1d73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=490813172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese t_error.490813172 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.1766158177 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 154967389 ps |
| CPU time | 7.58 seconds |
| Started | Jan 21 11:03:43 PM PST 24 |
| Finished | Jan 21 11:03:54 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-9d1928cc-2dbf-4c37-be31-9de03c157f17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1766158177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1766158177 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.925481049 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 276452019 ps |
| CPU time | 7.01 seconds |
| Started | Jan 21 10:37:14 PM PST 24 |
| Finished | Jan 21 10:37:28 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-bb5df7b6-eda4-4587-8a62-02fcf53855fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=925481049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.925481049 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.1459336810 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 62053054480 ps |
| CPU time | 343.06 seconds |
| Started | Jan 21 10:37:16 PM PST 24 |
| Finished | Jan 21 10:43:08 PM PST 24 |
| Peak memory | 211604 kb |
| Host | smart-f6f0a921-62c4-4ee7-b5f6-a905be192eb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1459336810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.1459336810 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2588546119 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 51372579 ps |
| CPU time | 2.09 seconds |
| Started | Jan 21 10:37:22 PM PST 24 |
| Finished | Jan 21 10:37:35 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-534e73a3-6e18-45db-9442-add344287e98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2588546119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2588546119 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.1824047616 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 1590784111 ps |
| CPU time | 27.9 seconds |
| Started | Jan 21 10:37:23 PM PST 24 |
| Finished | Jan 21 10:38:02 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-95fb50a2-32b5-41e9-8407-f6b94395e362 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1824047616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1824047616 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.3083939022 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 312453910 ps |
| CPU time | 13.72 seconds |
| Started | Jan 21 10:37:13 PM PST 24 |
| Finished | Jan 21 10:37:35 PM PST 24 |
| Peak memory | 204532 kb |
| Host | smart-4b23d4ba-faef-4bc1-bcc5-1006e3112439 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3083939022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3083939022 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.2612465070 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 60992896485 ps |
| CPU time | 287.29 seconds |
| Started | Jan 21 10:37:17 PM PST 24 |
| Finished | Jan 21 10:42:17 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-80713890-8e7c-47e8-b2d0-531261a99419 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612465070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2612465070 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2934073501 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 18239465947 ps |
| CPU time | 155.95 seconds |
| Started | Jan 21 10:37:14 PM PST 24 |
| Finished | Jan 21 10:39:57 PM PST 24 |
| Peak memory | 211692 kb |
| Host | smart-088f9929-62ae-4863-b4de-7fd316b8f463 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2934073501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2934073501 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.2109427858 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 246882588 ps |
| CPU time | 18.7 seconds |
| Started | Jan 21 10:37:12 PM PST 24 |
| Finished | Jan 21 10:37:39 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-fa7a8156-a69b-4d66-a74e-a36f0a8f7bdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109427858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2109427858 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.545284222 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1555515219 ps |
| CPU time | 34.16 seconds |
| Started | Jan 21 10:37:15 PM PST 24 |
| Finished | Jan 21 10:37:58 PM PST 24 |
| Peak memory | 203768 kb |
| Host | smart-c5f5d42b-39c0-4c7a-b438-c4002290ffea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=545284222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.545284222 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.734288323 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 362058592 ps |
| CPU time | 3.8 seconds |
| Started | Jan 21 10:37:12 PM PST 24 |
| Finished | Jan 21 10:37:24 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-b4b751e9-3e62-4d8f-8e59-0771306897b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=734288323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.734288323 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.917166844 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 10410647798 ps |
| CPU time | 33.76 seconds |
| Started | Jan 21 10:37:15 PM PST 24 |
| Finished | Jan 21 10:37:57 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-2611c2cb-57c7-4c4c-8aef-7a568d576fe8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=917166844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.917166844 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2390461480 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3438749845 ps |
| CPU time | 28.33 seconds |
| Started | Jan 21 10:37:09 PM PST 24 |
| Finished | Jan 21 10:37:48 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-929b72ce-fe95-4d06-98d3-824c0cfdf9c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2390461480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2390461480 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2431687819 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 30096198 ps |
| CPU time | 2.41 seconds |
| Started | Jan 21 10:37:10 PM PST 24 |
| Finished | Jan 21 10:37:23 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-c60c9c7d-514b-40c2-bfec-24937b746749 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431687819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2431687819 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.647490181 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 413979790 ps |
| CPU time | 37.46 seconds |
| Started | Jan 21 10:37:20 PM PST 24 |
| Finished | Jan 21 10:38:10 PM PST 24 |
| Peak memory | 205900 kb |
| Host | smart-5aa1f66f-10be-4097-857b-0443067aa693 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647490181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.647490181 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2221613518 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 4493370851 ps |
| CPU time | 150.7 seconds |
| Started | Jan 21 10:37:29 PM PST 24 |
| Finished | Jan 21 10:40:14 PM PST 24 |
| Peak memory | 209016 kb |
| Host | smart-f59c6769-c6dd-43af-ad04-99bc85c521ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2221613518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2221613518 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1117302974 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 490755785 ps |
| CPU time | 175.09 seconds |
| Started | Jan 21 10:37:30 PM PST 24 |
| Finished | Jan 21 10:40:40 PM PST 24 |
| Peak memory | 210780 kb |
| Host | smart-9ba351e8-b39b-46c9-909e-f7148d4cef30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1117302974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.1117302974 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.2031513729 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 573668620 ps |
| CPU time | 7.08 seconds |
| Started | Jan 21 10:37:23 PM PST 24 |
| Finished | Jan 21 10:37:41 PM PST 24 |
| Peak memory | 211560 kb |
| Host | smart-6dd6a968-34a3-4b87-a2a5-2e0a1fff39f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2031513729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2031513729 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3499854205 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 866560783 ps |
| CPU time | 32.1 seconds |
| Started | Jan 21 10:37:40 PM PST 24 |
| Finished | Jan 21 10:38:25 PM PST 24 |
| Peak memory | 211608 kb |
| Host | smart-36173938-3a68-4253-a1c8-76ba5d6c606e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3499854205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3499854205 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3541091506 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 202141741 ps |
| CPU time | 19.51 seconds |
| Started | Jan 21 10:37:47 PM PST 24 |
| Finished | Jan 21 10:38:14 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-c5453e11-7eb6-44dd-b336-5c58ad918d13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3541091506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3541091506 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.4041590346 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1142384242 ps |
| CPU time | 24.34 seconds |
| Started | Jan 21 10:52:15 PM PST 24 |
| Finished | Jan 21 10:52:42 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-0ed2aa51-3571-41fb-a5b6-91f76f89aaca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4041590346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.4041590346 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.897222500 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 681081184 ps |
| CPU time | 13.49 seconds |
| Started | Jan 21 10:55:36 PM PST 24 |
| Finished | Jan 21 10:55:51 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-0451e081-47ae-46e4-9c75-7d0e1464e3ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=897222500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.897222500 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.4076501081 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 43248232599 ps |
| CPU time | 154.77 seconds |
| Started | Jan 21 11:03:44 PM PST 24 |
| Finished | Jan 21 11:06:22 PM PST 24 |
| Peak memory | 211736 kb |
| Host | smart-5a750294-ebec-4c2f-9800-8b1e6679af95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076501081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.4076501081 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2089095954 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 15163361814 ps |
| CPU time | 84.32 seconds |
| Started | Jan 21 10:37:39 PM PST 24 |
| Finished | Jan 21 10:39:17 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-42b06329-8194-4cf2-b28b-ac8309c5f4cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2089095954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2089095954 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1561969073 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 65683544 ps |
| CPU time | 9.43 seconds |
| Started | Jan 21 10:37:40 PM PST 24 |
| Finished | Jan 21 10:38:03 PM PST 24 |
| Peak memory | 211776 kb |
| Host | smart-8506e2a3-b9b7-47a6-9e25-19b18e261523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561969073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1561969073 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.2233005698 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1734713400 ps |
| CPU time | 18.2 seconds |
| Started | Jan 21 10:37:47 PM PST 24 |
| Finished | Jan 21 10:38:13 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-fef80bd4-212e-42f3-8bc9-3b4b93d7a9c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2233005698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2233005698 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.2913332092 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 106452308 ps |
| CPU time | 2.05 seconds |
| Started | Jan 21 10:37:28 PM PST 24 |
| Finished | Jan 21 10:37:42 PM PST 24 |
| Peak memory | 203564 kb |
| Host | smart-420888f2-a796-454d-9ef3-2543bb645217 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2913332092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2913332092 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.4241376752 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 7167762358 ps |
| CPU time | 28.66 seconds |
| Started | Jan 21 10:37:35 PM PST 24 |
| Finished | Jan 21 10:38:20 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-48cbb087-8e3d-4db5-a251-366cc10ee925 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241376752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.4241376752 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3482554646 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2883007493 ps |
| CPU time | 27.13 seconds |
| Started | Jan 21 10:37:36 PM PST 24 |
| Finished | Jan 21 10:38:19 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-2e3b8e3d-8872-4ea1-a9a0-8800baf06d19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3482554646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3482554646 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1365270678 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 97545975 ps |
| CPU time | 2.32 seconds |
| Started | Jan 21 10:37:36 PM PST 24 |
| Finished | Jan 21 10:37:54 PM PST 24 |
| Peak memory | 203344 kb |
| Host | smart-d89f97a6-84d3-4799-88b3-d8dfa227990b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365270678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1365270678 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.106677332 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1021671794 ps |
| CPU time | 30.16 seconds |
| Started | Jan 21 11:03:51 PM PST 24 |
| Finished | Jan 21 11:04:23 PM PST 24 |
| Peak memory | 205600 kb |
| Host | smart-d660dbbb-3b8b-471c-ba71-0335395279f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=106677332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.106677332 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.737901660 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4088188212 ps |
| CPU time | 109.81 seconds |
| Started | Jan 21 10:37:52 PM PST 24 |
| Finished | Jan 21 10:39:46 PM PST 24 |
| Peak memory | 204712 kb |
| Host | smart-76f7bf40-c9c3-4ba5-91ef-67ce79d295b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=737901660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.737901660 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.932777683 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2511569675 ps |
| CPU time | 289.14 seconds |
| Started | Jan 21 10:37:46 PM PST 24 |
| Finished | Jan 21 10:42:44 PM PST 24 |
| Peak memory | 209984 kb |
| Host | smart-8928dbc5-03f4-4b45-9ec9-a4564aa294cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=932777683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand _reset.932777683 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1555806225 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 3773237004 ps |
| CPU time | 226.64 seconds |
| Started | Jan 21 10:37:48 PM PST 24 |
| Finished | Jan 21 10:41:42 PM PST 24 |
| Peak memory | 210600 kb |
| Host | smart-086d0c88-55af-4e9f-b260-6ad67fdb76a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555806225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.1555806225 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1664779842 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 831698447 ps |
| CPU time | 21.6 seconds |
| Started | Jan 21 10:37:49 PM PST 24 |
| Finished | Jan 21 10:38:17 PM PST 24 |
| Peak memory | 204540 kb |
| Host | smart-42cefbc0-fe39-4b02-846a-f12426e845d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1664779842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1664779842 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1451675196 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 854625153 ps |
| CPU time | 28.25 seconds |
| Started | Jan 21 10:50:17 PM PST 24 |
| Finished | Jan 21 10:50:49 PM PST 24 |
| Peak memory | 211640 kb |
| Host | smart-fc8bc54a-5f5e-43a1-ae17-4983aafb1e03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1451675196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1451675196 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2539927195 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 128113799421 ps |
| CPU time | 676.5 seconds |
| Started | Jan 21 10:37:58 PM PST 24 |
| Finished | Jan 21 10:49:16 PM PST 24 |
| Peak memory | 205788 kb |
| Host | smart-9f116c49-23dc-40e0-8e7f-7765f938fc24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2539927195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.2539927195 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.87247345 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 27289986 ps |
| CPU time | 4.15 seconds |
| Started | Jan 21 10:37:58 PM PST 24 |
| Finished | Jan 21 10:38:04 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-b1b2b39e-f019-4c9a-a36f-ae96e663bc53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=87247345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.87247345 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.2217587917 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1120820275 ps |
| CPU time | 26.8 seconds |
| Started | Jan 21 10:37:55 PM PST 24 |
| Finished | Jan 21 10:38:24 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-3eae3fcc-eb1d-4114-a9b1-a95b9098f8c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2217587917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2217587917 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.3462865319 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 21917624 ps |
| CPU time | 2.37 seconds |
| Started | Jan 21 10:37:45 PM PST 24 |
| Finished | Jan 21 10:37:57 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-1e8760ec-596d-4816-94a0-f92dacb133e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3462865319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3462865319 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.2824278173 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 69443637865 ps |
| CPU time | 89.59 seconds |
| Started | Jan 21 10:37:56 PM PST 24 |
| Finished | Jan 21 10:39:27 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-85b162e6-525f-4840-b5f6-eaebd3b02db7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824278173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2824278173 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1672988684 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 112220686096 ps |
| CPU time | 311.4 seconds |
| Started | Jan 21 10:55:34 PM PST 24 |
| Finished | Jan 21 11:00:48 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-fd3821bb-6dd8-42fd-993b-d5b91f6cbe65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1672988684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1672988684 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.2613533389 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 174975264 ps |
| CPU time | 17.52 seconds |
| Started | Jan 21 10:37:53 PM PST 24 |
| Finished | Jan 21 10:38:14 PM PST 24 |
| Peak memory | 211604 kb |
| Host | smart-48196ea6-64d0-4092-8726-096eab86bd17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613533389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2613533389 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.1658370920 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1046409023 ps |
| CPU time | 9.14 seconds |
| Started | Jan 21 10:37:54 PM PST 24 |
| Finished | Jan 21 10:38:06 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-ed8a6ee5-6ab3-490e-aa34-51e738b8b08c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1658370920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1658370920 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.2533042836 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 696115224 ps |
| CPU time | 4.07 seconds |
| Started | Jan 21 10:37:48 PM PST 24 |
| Finished | Jan 21 10:37:59 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-a08bd8e6-ad8f-4d48-affd-b041a76544a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2533042836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2533042836 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1950342884 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 6071502852 ps |
| CPU time | 31.24 seconds |
| Started | Jan 21 10:37:51 PM PST 24 |
| Finished | Jan 21 10:38:27 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-a154910c-5c8c-43a9-b125-adfd1e2b649b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950342884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1950342884 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1969601047 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3887588947 ps |
| CPU time | 25.99 seconds |
| Started | Jan 21 10:37:45 PM PST 24 |
| Finished | Jan 21 10:38:20 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-d9d532b0-e4f3-4075-a70d-adcdfb049b4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1969601047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1969601047 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3170635692 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 35678858 ps |
| CPU time | 2.41 seconds |
| Started | Jan 21 10:37:46 PM PST 24 |
| Finished | Jan 21 10:37:57 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-ebf0b845-7c06-4f52-b8c5-709b17ecdd06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170635692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3170635692 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.1113264138 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3871292766 ps |
| CPU time | 108.36 seconds |
| Started | Jan 21 10:37:59 PM PST 24 |
| Finished | Jan 21 10:39:50 PM PST 24 |
| Peak memory | 207152 kb |
| Host | smart-6eb2bb2f-1757-42e4-ab00-1afea97659bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1113264138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1113264138 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.851017540 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 6796448836 ps |
| CPU time | 167.01 seconds |
| Started | Jan 21 10:37:59 PM PST 24 |
| Finished | Jan 21 10:40:48 PM PST 24 |
| Peak memory | 208444 kb |
| Host | smart-9166df3e-708e-4320-a04a-3262dde09a8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=851017540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.851017540 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1830972545 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 576492651 ps |
| CPU time | 252.13 seconds |
| Started | Jan 21 10:37:59 PM PST 24 |
| Finished | Jan 21 10:42:14 PM PST 24 |
| Peak memory | 208096 kb |
| Host | smart-81eb1ac9-3830-4d9a-add6-609837b96f8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1830972545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.1830972545 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3611231792 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2045135308 ps |
| CPU time | 294.12 seconds |
| Started | Jan 21 10:38:02 PM PST 24 |
| Finished | Jan 21 10:42:58 PM PST 24 |
| Peak memory | 211380 kb |
| Host | smart-86b583d8-0178-4b81-934a-b94e84113ce8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3611231792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3611231792 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.2885108982 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 487089331 ps |
| CPU time | 17.9 seconds |
| Started | Jan 21 11:15:16 PM PST 24 |
| Finished | Jan 21 11:15:35 PM PST 24 |
| Peak memory | 204664 kb |
| Host | smart-a383f578-7b5c-403d-9d5f-e656c79ff791 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2885108982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2885108982 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.464767766 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3362259901 ps |
| CPU time | 34.11 seconds |
| Started | Jan 21 10:38:13 PM PST 24 |
| Finished | Jan 21 10:38:49 PM PST 24 |
| Peak memory | 211644 kb |
| Host | smart-4dc13d5e-a5ec-4d1d-b78f-ba4f63ec575b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=464767766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.464767766 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3117540442 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 175530955210 ps |
| CPU time | 742.84 seconds |
| Started | Jan 21 10:57:56 PM PST 24 |
| Finished | Jan 21 11:10:22 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-47097cab-a901-4781-a59e-48bf9fe2f5d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3117540442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.3117540442 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2568777834 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1080116343 ps |
| CPU time | 16.31 seconds |
| Started | Jan 21 10:38:10 PM PST 24 |
| Finished | Jan 21 10:38:28 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-ed34e402-aba2-424d-8f7b-406b1e2da832 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2568777834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2568777834 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.3742709849 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 980381376 ps |
| CPU time | 28.05 seconds |
| Started | Jan 21 10:38:13 PM PST 24 |
| Finished | Jan 21 10:38:43 PM PST 24 |
| Peak memory | 203332 kb |
| Host | smart-7cc77022-2785-429f-a26d-f6862623bfd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3742709849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3742709849 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.4284638753 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 701720256 ps |
| CPU time | 23.93 seconds |
| Started | Jan 21 10:38:08 PM PST 24 |
| Finished | Jan 21 10:38:33 PM PST 24 |
| Peak memory | 204588 kb |
| Host | smart-be1132c1-56d8-4462-ae53-e71db03afcc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4284638753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.4284638753 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.325504196 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 102006887980 ps |
| CPU time | 184.39 seconds |
| Started | Jan 21 10:38:07 PM PST 24 |
| Finished | Jan 21 10:41:13 PM PST 24 |
| Peak memory | 211640 kb |
| Host | smart-85121813-529a-4d17-8ca2-daa021bcc798 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=325504196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.325504196 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3793765600 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 26878473721 ps |
| CPU time | 223.24 seconds |
| Started | Jan 21 11:00:15 PM PST 24 |
| Finished | Jan 21 11:04:00 PM PST 24 |
| Peak memory | 211736 kb |
| Host | smart-541c0dc6-c9dd-4aa3-9274-6be03b2d7b44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3793765600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3793765600 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.4192801555 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 238066105 ps |
| CPU time | 24.48 seconds |
| Started | Jan 21 10:54:57 PM PST 24 |
| Finished | Jan 21 10:55:24 PM PST 24 |
| Peak memory | 211592 kb |
| Host | smart-0715177e-a9f2-4dfa-95eb-862ec34356d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192801555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.4192801555 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.3269810397 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 992453516 ps |
| CPU time | 24.96 seconds |
| Started | Jan 21 10:50:14 PM PST 24 |
| Finished | Jan 21 10:50:44 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-d158d0e7-6966-406d-9f2c-516458e48944 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3269810397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3269810397 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.4075536903 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 321425071 ps |
| CPU time | 3.77 seconds |
| Started | Jan 21 10:37:59 PM PST 24 |
| Finished | Jan 21 10:38:05 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-858b3dc4-cb7e-4ffb-a28c-51565d23ee9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4075536903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.4075536903 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3384451712 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 5286798634 ps |
| CPU time | 29.65 seconds |
| Started | Jan 21 11:09:48 PM PST 24 |
| Finished | Jan 21 11:10:20 PM PST 24 |
| Peak memory | 203528 kb |
| Host | smart-41355dfc-0eb0-49e5-ad6f-019dee910b40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384451712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3384451712 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3996742205 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5633954879 ps |
| CPU time | 29.27 seconds |
| Started | Jan 21 10:38:12 PM PST 24 |
| Finished | Jan 21 10:38:43 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-125124cb-cc3a-478a-8d81-0b45b74aa176 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3996742205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3996742205 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3931238148 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 33184556 ps |
| CPU time | 2.08 seconds |
| Started | Jan 21 10:38:03 PM PST 24 |
| Finished | Jan 21 10:38:07 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-1947be95-336f-4b1a-b13c-d7dc3442e61f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931238148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3931238148 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.3810333535 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 442511517 ps |
| CPU time | 73.47 seconds |
| Started | Jan 21 10:38:13 PM PST 24 |
| Finished | Jan 21 10:39:28 PM PST 24 |
| Peak memory | 206704 kb |
| Host | smart-17a21fc6-c1b0-49f0-b9fd-231817e384ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3810333535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3810333535 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.3881381948 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2020247006 ps |
| CPU time | 45.83 seconds |
| Started | Jan 21 10:38:17 PM PST 24 |
| Finished | Jan 21 10:39:04 PM PST 24 |
| Peak memory | 203640 kb |
| Host | smart-97956db2-be62-4a4c-bfc0-a1fa1a8ff5d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3881381948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3881381948 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2513679406 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3936128152 ps |
| CPU time | 188.52 seconds |
| Started | Jan 21 10:38:12 PM PST 24 |
| Finished | Jan 21 10:41:23 PM PST 24 |
| Peak memory | 208948 kb |
| Host | smart-92edd3df-ad55-4c5b-b174-0418dd4f3100 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2513679406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.2513679406 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2774489037 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3213072991 ps |
| CPU time | 183.12 seconds |
| Started | Jan 21 10:54:13 PM PST 24 |
| Finished | Jan 21 10:57:17 PM PST 24 |
| Peak memory | 210168 kb |
| Host | smart-6edae864-16ed-4e8c-b070-8a1000692ca3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2774489037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.2774489037 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3329762772 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 447398827 ps |
| CPU time | 21.22 seconds |
| Started | Jan 21 10:38:14 PM PST 24 |
| Finished | Jan 21 10:38:36 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-cdeea88b-ac1f-49b9-938a-eb78c1a7e2c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3329762772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3329762772 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2005066668 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 488547702 ps |
| CPU time | 10.06 seconds |
| Started | Jan 21 10:38:23 PM PST 24 |
| Finished | Jan 21 10:38:35 PM PST 24 |
| Peak memory | 203348 kb |
| Host | smart-764eaeb7-04a7-4119-ab2a-8e08f0669f35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2005066668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2005066668 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1404136658 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 44671269801 ps |
| CPU time | 312.72 seconds |
| Started | Jan 21 11:27:59 PM PST 24 |
| Finished | Jan 21 11:33:14 PM PST 24 |
| Peak memory | 211768 kb |
| Host | smart-435dc63a-8f43-4e29-8a10-6c94e1f093f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1404136658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.1404136658 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2837429239 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1704413635 ps |
| CPU time | 22.49 seconds |
| Started | Jan 21 10:38:29 PM PST 24 |
| Finished | Jan 21 10:38:55 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-198fbf86-ef28-452d-83a2-fad0a5f23ead |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2837429239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2837429239 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2101718597 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1215764300 ps |
| CPU time | 17.59 seconds |
| Started | Jan 21 10:38:29 PM PST 24 |
| Finished | Jan 21 10:38:51 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-4f6472e3-fb93-41c5-8af3-d1b9f0a1fa59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2101718597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2101718597 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.1182860678 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 876989541 ps |
| CPU time | 28 seconds |
| Started | Jan 21 11:20:57 PM PST 24 |
| Finished | Jan 21 11:21:28 PM PST 24 |
| Peak memory | 211676 kb |
| Host | smart-6ec7c9d3-fe81-42de-8a4a-5983f401ce99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1182860678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1182860678 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2593092441 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 41978055873 ps |
| CPU time | 145.67 seconds |
| Started | Jan 21 10:38:24 PM PST 24 |
| Finished | Jan 21 10:40:51 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-1a289d85-b44e-4d0a-8d02-8b1f323621e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593092441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2593092441 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3557026740 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 17395966204 ps |
| CPU time | 90.78 seconds |
| Started | Jan 21 10:55:51 PM PST 24 |
| Finished | Jan 21 10:57:23 PM PST 24 |
| Peak memory | 204560 kb |
| Host | smart-07c12818-46f8-4cc6-a780-41e5d05fd308 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3557026740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3557026740 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3376340677 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 29444180 ps |
| CPU time | 3.39 seconds |
| Started | Jan 21 10:51:09 PM PST 24 |
| Finished | Jan 21 10:51:14 PM PST 24 |
| Peak memory | 204000 kb |
| Host | smart-5cc6d152-4123-47ae-96a1-10c8fb5f7739 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376340677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3376340677 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.3480941555 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 239832159 ps |
| CPU time | 5.78 seconds |
| Started | Jan 21 10:42:11 PM PST 24 |
| Finished | Jan 21 10:42:18 PM PST 24 |
| Peak memory | 203356 kb |
| Host | smart-61089bdb-6c68-43a2-85ab-6d7e81b5920f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3480941555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3480941555 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.3025166432 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 341765394 ps |
| CPU time | 4 seconds |
| Started | Jan 21 10:38:17 PM PST 24 |
| Finished | Jan 21 10:38:22 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-76f2a1b6-f79a-4eae-abe6-f14022386a21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3025166432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3025166432 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3695032192 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 5761421652 ps |
| CPU time | 27.79 seconds |
| Started | Jan 21 10:38:16 PM PST 24 |
| Finished | Jan 21 10:38:45 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-df5cb459-3c18-4c5e-a012-279ff1a83d87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695032192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3695032192 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.3106494153 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 23261389599 ps |
| CPU time | 51.88 seconds |
| Started | Jan 21 10:38:22 PM PST 24 |
| Finished | Jan 21 10:39:16 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-e17210c5-d884-4554-af8b-a2f97a1e9bb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3106494153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3106494153 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3097246123 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 30566092 ps |
| CPU time | 2.18 seconds |
| Started | Jan 21 10:38:17 PM PST 24 |
| Finished | Jan 21 10:38:21 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-de418a68-e3b5-48d5-84eb-f62a7c041944 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097246123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3097246123 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.1645165561 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 7304229859 ps |
| CPU time | 142.4 seconds |
| Started | Jan 21 10:38:28 PM PST 24 |
| Finished | Jan 21 10:40:54 PM PST 24 |
| Peak memory | 208536 kb |
| Host | smart-c74dd3f8-f755-4273-abbb-7373da2afa2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1645165561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1645165561 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2348750677 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 129386463 ps |
| CPU time | 12.04 seconds |
| Started | Jan 21 10:38:30 PM PST 24 |
| Finished | Jan 21 10:38:46 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-3e86c2d5-9abf-4e2c-ba38-c9a954835d13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2348750677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2348750677 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.380161069 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 390580301 ps |
| CPU time | 122.25 seconds |
| Started | Jan 21 10:55:51 PM PST 24 |
| Finished | Jan 21 10:57:54 PM PST 24 |
| Peak memory | 208272 kb |
| Host | smart-8f17c8ef-e63e-44e5-896b-b24640a40797 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=380161069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand _reset.380161069 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3557447742 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 313820809 ps |
| CPU time | 113.53 seconds |
| Started | Jan 21 10:38:35 PM PST 24 |
| Finished | Jan 21 10:40:31 PM PST 24 |
| Peak memory | 209340 kb |
| Host | smart-e2b934dd-6559-4d3b-8e97-30b7802bef7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3557447742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.3557447742 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1482273965 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 326312214 ps |
| CPU time | 11.45 seconds |
| Started | Jan 21 10:38:30 PM PST 24 |
| Finished | Jan 21 10:38:45 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-66b32901-e0db-4fd4-9c6c-914739a65903 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1482273965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1482273965 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2047124490 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 6438586173 ps |
| CPU time | 59.22 seconds |
| Started | Jan 21 10:38:42 PM PST 24 |
| Finished | Jan 21 10:39:44 PM PST 24 |
| Peak memory | 205448 kb |
| Host | smart-e5b80f4a-7542-4209-8f5d-9ed53330e039 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2047124490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2047124490 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.3431345915 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 263494198144 ps |
| CPU time | 752.71 seconds |
| Started | Jan 21 10:38:43 PM PST 24 |
| Finished | Jan 21 10:51:18 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-4fcfa615-a77f-43eb-8bcc-977a48bcaba2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3431345915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.3431345915 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.536592242 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 269821655 ps |
| CPU time | 6.27 seconds |
| Started | Jan 21 10:38:52 PM PST 24 |
| Finished | Jan 21 10:39:00 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-61d4a05e-eda3-4b7b-af07-8b6adc68e621 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=536592242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.536592242 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.1976666684 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 445707748 ps |
| CPU time | 9.2 seconds |
| Started | Jan 21 10:38:42 PM PST 24 |
| Finished | Jan 21 10:38:53 PM PST 24 |
| Peak memory | 203344 kb |
| Host | smart-baaaff0d-6906-4bc9-9aef-b9da8a44f40b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1976666684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1976666684 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.3794945538 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 705360373 ps |
| CPU time | 21.26 seconds |
| Started | Jan 21 10:38:43 PM PST 24 |
| Finished | Jan 21 10:39:06 PM PST 24 |
| Peak memory | 211584 kb |
| Host | smart-6102ab3c-a635-4ecc-b8e7-ed317f510961 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3794945538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3794945538 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2301541103 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 145965992478 ps |
| CPU time | 234.02 seconds |
| Started | Jan 21 10:38:45 PM PST 24 |
| Finished | Jan 21 10:42:41 PM PST 24 |
| Peak memory | 204984 kb |
| Host | smart-759218ff-d50c-4612-a250-daafead0d14c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301541103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2301541103 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3857651336 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 11551774310 ps |
| CPU time | 93.76 seconds |
| Started | Jan 21 10:38:44 PM PST 24 |
| Finished | Jan 21 10:40:20 PM PST 24 |
| Peak memory | 211576 kb |
| Host | smart-013685eb-d656-473b-b939-27ed88f095d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3857651336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3857651336 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2241879136 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 50498705 ps |
| CPU time | 7.87 seconds |
| Started | Jan 21 10:38:45 PM PST 24 |
| Finished | Jan 21 10:38:55 PM PST 24 |
| Peak memory | 204504 kb |
| Host | smart-4c7ec2be-8400-412f-8823-7fcfde896543 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241879136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2241879136 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.1309231087 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2862632807 ps |
| CPU time | 22.88 seconds |
| Started | Jan 21 10:38:41 PM PST 24 |
| Finished | Jan 21 10:39:05 PM PST 24 |
| Peak memory | 204044 kb |
| Host | smart-0288bf0a-6ec7-43af-ac3b-127bc3053982 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1309231087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1309231087 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.634990470 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 244845122 ps |
| CPU time | 3.86 seconds |
| Started | Jan 21 10:38:35 PM PST 24 |
| Finished | Jan 21 10:38:41 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-6afeb527-4bf1-45ab-855a-df460ebf2999 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=634990470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.634990470 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2311309698 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 11241670005 ps |
| CPU time | 40.16 seconds |
| Started | Jan 21 10:38:34 PM PST 24 |
| Finished | Jan 21 10:39:17 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-60dffe28-a46f-4631-abaf-11700946abc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311309698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2311309698 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1678724858 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 25680902728 ps |
| CPU time | 45.27 seconds |
| Started | Jan 21 10:38:43 PM PST 24 |
| Finished | Jan 21 10:39:30 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-354230cd-8035-48d0-900f-4d55268d8af7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1678724858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1678724858 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2900827741 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 52861736 ps |
| CPU time | 2.14 seconds |
| Started | Jan 21 10:38:35 PM PST 24 |
| Finished | Jan 21 10:38:39 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-f4d2cb2a-e26c-4fae-b874-f55ee633c316 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900827741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2900827741 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3088107822 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 5454238188 ps |
| CPU time | 122.68 seconds |
| Started | Jan 21 10:38:48 PM PST 24 |
| Finished | Jan 21 10:40:52 PM PST 24 |
| Peak memory | 208888 kb |
| Host | smart-ffcf7bcb-9509-4169-b943-58b4e8805391 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3088107822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3088107822 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.4258322052 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 97033578 ps |
| CPU time | 11.48 seconds |
| Started | Jan 21 10:38:50 PM PST 24 |
| Finished | Jan 21 10:39:02 PM PST 24 |
| Peak memory | 203900 kb |
| Host | smart-1f512f7b-661e-49d1-9704-edac07c2c6de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4258322052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.4258322052 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1433278762 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2591375436 ps |
| CPU time | 570.63 seconds |
| Started | Jan 21 10:38:52 PM PST 24 |
| Finished | Jan 21 10:48:24 PM PST 24 |
| Peak memory | 209140 kb |
| Host | smart-5db545c4-0e14-4745-9ebb-9970cc776c8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1433278762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.1433278762 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.391474343 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 107051212 ps |
| CPU time | 23.51 seconds |
| Started | Jan 21 10:38:49 PM PST 24 |
| Finished | Jan 21 10:39:14 PM PST 24 |
| Peak memory | 205568 kb |
| Host | smart-35443318-c03a-4bec-ae13-6a2160cce9e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=391474343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res et_error.391474343 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.1748313525 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 67268338 ps |
| CPU time | 9.16 seconds |
| Started | Jan 21 10:38:52 PM PST 24 |
| Finished | Jan 21 10:39:03 PM PST 24 |
| Peak memory | 204636 kb |
| Host | smart-0718c836-be01-4cb9-bb8f-1620431b6ef8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1748313525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1748313525 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3538249910 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 202548346 ps |
| CPU time | 14.3 seconds |
| Started | Jan 21 10:39:02 PM PST 24 |
| Finished | Jan 21 10:39:17 PM PST 24 |
| Peak memory | 203848 kb |
| Host | smart-0438bc4e-9c22-4507-a7ad-61687c6f4f6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3538249910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3538249910 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1503902087 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 26355777675 ps |
| CPU time | 224.07 seconds |
| Started | Jan 21 10:39:00 PM PST 24 |
| Finished | Jan 21 10:42:46 PM PST 24 |
| Peak memory | 206256 kb |
| Host | smart-ccadd6e5-2e11-4f53-90d5-fefda94c5b7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1503902087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.1503902087 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1146499160 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 774435626 ps |
| CPU time | 30.87 seconds |
| Started | Jan 21 10:39:12 PM PST 24 |
| Finished | Jan 21 10:39:45 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-7e31be23-5616-43f1-926b-975aba81325f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1146499160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1146499160 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.1695102615 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2131801999 ps |
| CPU time | 39.17 seconds |
| Started | Jan 21 10:39:09 PM PST 24 |
| Finished | Jan 21 10:39:49 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-04e77d29-c0f7-4109-b4ac-778b1812415b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1695102615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1695102615 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.3819404430 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 33108492 ps |
| CPU time | 4.82 seconds |
| Started | Jan 21 10:38:54 PM PST 24 |
| Finished | Jan 21 10:39:01 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-9a3d0bec-ed93-4361-8615-fd995f8c3834 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3819404430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3819404430 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.336372494 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 37214979754 ps |
| CPU time | 186.47 seconds |
| Started | Jan 21 10:39:04 PM PST 24 |
| Finished | Jan 21 10:42:12 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-7a06e581-60d2-4346-ad30-b39d230671aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=336372494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.336372494 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.124758228 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27725567204 ps |
| CPU time | 213.55 seconds |
| Started | Jan 21 10:39:08 PM PST 24 |
| Finished | Jan 21 10:42:43 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-1c1b15e0-f46e-4098-ba18-4cd7e58af697 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=124758228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.124758228 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.28429298 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 208329463 ps |
| CPU time | 16.21 seconds |
| Started | Jan 21 10:38:54 PM PST 24 |
| Finished | Jan 21 10:39:13 PM PST 24 |
| Peak memory | 204092 kb |
| Host | smart-17876257-dcab-4b00-992b-825d331ab054 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28429298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.28429298 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.1392688367 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 467177313 ps |
| CPU time | 16.87 seconds |
| Started | Jan 21 10:39:00 PM PST 24 |
| Finished | Jan 21 10:39:19 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-2dc47e87-d0b2-41e6-ba8d-89938a0f3aff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1392688367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1392688367 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.2639197172 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 130011344 ps |
| CPU time | 3.34 seconds |
| Started | Jan 21 10:38:49 PM PST 24 |
| Finished | Jan 21 10:38:53 PM PST 24 |
| Peak memory | 203564 kb |
| Host | smart-ec352836-b280-48d7-bb7f-a13c055fa608 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639197172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2639197172 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2975415319 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 18573079451 ps |
| CPU time | 35.69 seconds |
| Started | Jan 21 10:38:54 PM PST 24 |
| Finished | Jan 21 10:39:32 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-8ec8092f-00d7-475b-b4a1-311f34fdae98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975415319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2975415319 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.727094517 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3394359968 ps |
| CPU time | 28.25 seconds |
| Started | Jan 21 10:38:54 PM PST 24 |
| Finished | Jan 21 10:39:25 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-636a5693-5efd-4281-a6bc-b8345e710b8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=727094517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.727094517 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.244357750 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 24368833 ps |
| CPU time | 2.01 seconds |
| Started | Jan 21 10:38:56 PM PST 24 |
| Finished | Jan 21 10:39:00 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-170a1d6d-1ff9-4aa4-ab55-7541c2566ec4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244357750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.244357750 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2602806363 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 843345702 ps |
| CPU time | 87.89 seconds |
| Started | Jan 21 10:39:09 PM PST 24 |
| Finished | Jan 21 10:40:39 PM PST 24 |
| Peak memory | 206988 kb |
| Host | smart-63e1e120-018a-420e-933e-e69d2a6068b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2602806363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2602806363 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1487629354 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1398528438 ps |
| CPU time | 45.04 seconds |
| Started | Jan 21 10:39:10 PM PST 24 |
| Finished | Jan 21 10:39:57 PM PST 24 |
| Peak memory | 204684 kb |
| Host | smart-603112c2-8e76-4c4b-90e4-27eba6a06be6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1487629354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1487629354 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2126518304 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2086691167 ps |
| CPU time | 231.8 seconds |
| Started | Jan 21 10:39:10 PM PST 24 |
| Finished | Jan 21 10:43:03 PM PST 24 |
| Peak memory | 208880 kb |
| Host | smart-fdd057cf-78d0-47fb-bc1b-067cf5be87f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2126518304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.2126518304 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2854423874 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 108289576 ps |
| CPU time | 12.42 seconds |
| Started | Jan 21 10:39:09 PM PST 24 |
| Finished | Jan 21 10:39:23 PM PST 24 |
| Peak memory | 211508 kb |
| Host | smart-7782d4a7-840e-4b72-9416-4482c217d1f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2854423874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2854423874 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.3627009449 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 316831767 ps |
| CPU time | 34.64 seconds |
| Started | Jan 21 10:39:14 PM PST 24 |
| Finished | Jan 21 10:39:49 PM PST 24 |
| Peak memory | 204376 kb |
| Host | smart-336da103-f702-48f4-af78-14505f356c87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3627009449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3627009449 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3422771301 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 15166316330 ps |
| CPU time | 59.91 seconds |
| Started | Jan 21 10:39:14 PM PST 24 |
| Finished | Jan 21 10:40:15 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-8f7ee672-5f01-42eb-89b2-e04d2a9b8ae6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3422771301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.3422771301 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2395486557 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 692087163 ps |
| CPU time | 27.2 seconds |
| Started | Jan 21 10:39:24 PM PST 24 |
| Finished | Jan 21 10:39:53 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-95de6881-10f6-4a24-9551-b2fd58a83e8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2395486557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2395486557 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.2536365983 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2418029741 ps |
| CPU time | 31.25 seconds |
| Started | Jan 21 10:39:21 PM PST 24 |
| Finished | Jan 21 10:39:54 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-c7e8986a-9a2f-4576-82ee-d661e8388566 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2536365983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2536365983 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.207313862 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 294982250 ps |
| CPU time | 6.04 seconds |
| Started | Jan 21 10:39:10 PM PST 24 |
| Finished | Jan 21 10:39:18 PM PST 24 |
| Peak memory | 203920 kb |
| Host | smart-5b3fb559-4832-4fe7-b520-2742f12247da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=207313862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.207313862 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.366410519 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 121049067215 ps |
| CPU time | 251.28 seconds |
| Started | Jan 21 10:39:16 PM PST 24 |
| Finished | Jan 21 10:43:29 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-3050a499-3f66-4139-b656-cc7ded54d29a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=366410519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.366410519 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3562391476 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 145906309103 ps |
| CPU time | 392.78 seconds |
| Started | Jan 21 10:39:14 PM PST 24 |
| Finished | Jan 21 10:45:48 PM PST 24 |
| Peak memory | 204604 kb |
| Host | smart-027ea65a-f42c-44ac-be0e-31f948dc7dd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3562391476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3562391476 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1927536214 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 996173561 ps |
| CPU time | 25.3 seconds |
| Started | Jan 21 10:39:10 PM PST 24 |
| Finished | Jan 21 10:39:37 PM PST 24 |
| Peak memory | 211608 kb |
| Host | smart-90ee0a98-65a4-4f14-8e6d-e409dd6a90b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927536214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1927536214 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.513545941 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 544727343 ps |
| CPU time | 5.38 seconds |
| Started | Jan 21 10:39:23 PM PST 24 |
| Finished | Jan 21 10:39:30 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-af70fba5-8455-4e8a-aed3-2e0437627cc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=513545941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.513545941 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.3390316278 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 377082161 ps |
| CPU time | 4.08 seconds |
| Started | Jan 21 10:39:10 PM PST 24 |
| Finished | Jan 21 10:39:16 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-8e439f8c-579e-4ea4-bf96-0a6ebec095be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3390316278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3390316278 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2249671590 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 6975823163 ps |
| CPU time | 27.03 seconds |
| Started | Jan 21 10:39:12 PM PST 24 |
| Finished | Jan 21 10:39:41 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-042bea91-aade-4e22-aeb0-912b05f35753 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249671590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2249671590 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.4176637520 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 4678181267 ps |
| CPU time | 33.61 seconds |
| Started | Jan 21 10:39:11 PM PST 24 |
| Finished | Jan 21 10:39:46 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-d4b658d7-8542-4040-8893-9e1f8751ec85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4176637520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.4176637520 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3048529774 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 42574897 ps |
| CPU time | 2.24 seconds |
| Started | Jan 21 10:39:11 PM PST 24 |
| Finished | Jan 21 10:39:15 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-fc6ce59b-69bd-4911-aeb5-4a2d940c10bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048529774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3048529774 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.3271633987 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 201359155 ps |
| CPU time | 19.08 seconds |
| Started | Jan 21 10:53:34 PM PST 24 |
| Finished | Jan 21 10:53:54 PM PST 24 |
| Peak memory | 204580 kb |
| Host | smart-3cdc05f3-f7d0-4de9-be13-644c50bbe120 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3271633987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3271633987 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2436695011 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 774463548 ps |
| CPU time | 95.61 seconds |
| Started | Jan 21 10:39:29 PM PST 24 |
| Finished | Jan 21 10:41:06 PM PST 24 |
| Peak memory | 211584 kb |
| Host | smart-9545eba0-7d49-4293-bcf8-ab9ef84ff056 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2436695011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2436695011 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3450198291 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1403413738 ps |
| CPU time | 318.61 seconds |
| Started | Jan 21 10:39:25 PM PST 24 |
| Finished | Jan 21 10:44:45 PM PST 24 |
| Peak memory | 210888 kb |
| Host | smart-befafee3-88ae-4e94-9acb-2c346acd44c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3450198291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.3450198291 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3811912082 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 235054238 ps |
| CPU time | 44.41 seconds |
| Started | Jan 21 10:39:29 PM PST 24 |
| Finished | Jan 21 10:40:14 PM PST 24 |
| Peak memory | 206080 kb |
| Host | smart-1106da56-bc1c-4632-88cc-1714ee6b0425 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3811912082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.3811912082 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3094630930 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 993722635 ps |
| CPU time | 17.96 seconds |
| Started | Jan 21 10:39:21 PM PST 24 |
| Finished | Jan 21 10:39:41 PM PST 24 |
| Peak memory | 211588 kb |
| Host | smart-8a97714c-509a-4a5d-aa5a-ddc0a72b9ef7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3094630930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3094630930 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2448716303 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1823851754 ps |
| CPU time | 19.84 seconds |
| Started | Jan 21 10:39:34 PM PST 24 |
| Finished | Jan 21 10:39:55 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-dd049864-60b5-4626-ace1-cc520bd23529 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2448716303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2448716303 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.3614142578 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 75391610893 ps |
| CPU time | 313.74 seconds |
| Started | Jan 21 10:39:35 PM PST 24 |
| Finished | Jan 21 10:44:49 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-58335ee9-747c-4d29-b18f-2a28b84a0da2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3614142578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.3614142578 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2599423070 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 103218062 ps |
| CPU time | 16.35 seconds |
| Started | Jan 21 10:39:39 PM PST 24 |
| Finished | Jan 21 10:39:57 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-1ccbbc35-6b7d-4b5b-b11b-2d81b78f6d39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2599423070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2599423070 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.2971026370 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1255855806 ps |
| CPU time | 27.85 seconds |
| Started | Jan 21 10:39:38 PM PST 24 |
| Finished | Jan 21 10:40:06 PM PST 24 |
| Peak memory | 203592 kb |
| Host | smart-239822d8-6cf7-481c-b4ee-eb63ab529e81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2971026370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2971026370 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.1025538186 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 574322717 ps |
| CPU time | 20.61 seconds |
| Started | Jan 21 10:39:34 PM PST 24 |
| Finished | Jan 21 10:39:55 PM PST 24 |
| Peak memory | 204528 kb |
| Host | smart-8c10b43e-a88e-4f9a-96ed-96fc7dbcb6d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1025538186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1025538186 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3059643552 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 29072350469 ps |
| CPU time | 141.5 seconds |
| Started | Jan 21 10:39:35 PM PST 24 |
| Finished | Jan 21 10:41:57 PM PST 24 |
| Peak memory | 204788 kb |
| Host | smart-aec8c05a-1842-4875-b446-c4b0dd19ac10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059643552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3059643552 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.712130616 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 37673488828 ps |
| CPU time | 230.98 seconds |
| Started | Jan 21 10:39:35 PM PST 24 |
| Finished | Jan 21 10:43:27 PM PST 24 |
| Peak memory | 211696 kb |
| Host | smart-66a78fc4-e790-4df9-bfe7-f135f88d7325 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=712130616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.712130616 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2234380415 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 181545159 ps |
| CPU time | 20.42 seconds |
| Started | Jan 21 10:39:35 PM PST 24 |
| Finished | Jan 21 10:39:56 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-b7987a67-1ae2-4cc6-a56f-ea6ba39d8eea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234380415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2234380415 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.1376603490 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 291038830 ps |
| CPU time | 5.93 seconds |
| Started | Jan 21 10:39:34 PM PST 24 |
| Finished | Jan 21 10:39:41 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-2da49188-ecff-49b3-92a8-358bff964ae3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1376603490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1376603490 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.3347588418 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 33075544 ps |
| CPU time | 2.12 seconds |
| Started | Jan 21 10:39:29 PM PST 24 |
| Finished | Jan 21 10:39:33 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-5a9f4efc-2a43-4999-89dc-ee69296e2daa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3347588418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3347588418 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1283579945 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 15316016417 ps |
| CPU time | 33.12 seconds |
| Started | Jan 21 10:39:27 PM PST 24 |
| Finished | Jan 21 10:40:01 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-ac981a34-25c1-4802-9874-c2925863302a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283579945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1283579945 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.4127069131 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 5071162841 ps |
| CPU time | 34.09 seconds |
| Started | Jan 21 10:39:29 PM PST 24 |
| Finished | Jan 21 10:40:05 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-5d3bb3cb-b551-42b2-b457-936983742e4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4127069131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4127069131 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1896595254 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 27213825 ps |
| CPU time | 2.44 seconds |
| Started | Jan 21 10:39:27 PM PST 24 |
| Finished | Jan 21 10:39:31 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-8353ad9e-fdb6-4777-a702-37e6ce1adec4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896595254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1896595254 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.2339759209 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1886223529 ps |
| CPU time | 131.76 seconds |
| Started | Jan 21 10:39:38 PM PST 24 |
| Finished | Jan 21 10:41:50 PM PST 24 |
| Peak memory | 207068 kb |
| Host | smart-fd69410e-91fa-4e19-87b3-769fc317cd1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2339759209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2339759209 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1876920451 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1638547911 ps |
| CPU time | 142.28 seconds |
| Started | Jan 21 10:39:46 PM PST 24 |
| Finished | Jan 21 10:42:09 PM PST 24 |
| Peak memory | 208704 kb |
| Host | smart-0de8b0a4-d907-4142-b216-25a37fb77ea2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1876920451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1876920451 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2247873120 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1078540784 ps |
| CPU time | 81.62 seconds |
| Started | Jan 21 10:39:39 PM PST 24 |
| Finished | Jan 21 10:41:01 PM PST 24 |
| Peak memory | 206936 kb |
| Host | smart-bdaf20c3-adab-4ef6-ae01-8556e1263dc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2247873120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.2247873120 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3998365594 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 410289729 ps |
| CPU time | 159.94 seconds |
| Started | Jan 21 10:39:48 PM PST 24 |
| Finished | Jan 21 10:42:29 PM PST 24 |
| Peak memory | 210772 kb |
| Host | smart-f1926009-f0a7-4792-9b95-253b1deace24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3998365594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.3998365594 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.734650258 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 525129546 ps |
| CPU time | 19.56 seconds |
| Started | Jan 21 10:39:38 PM PST 24 |
| Finished | Jan 21 10:39:59 PM PST 24 |
| Peak memory | 211548 kb |
| Host | smart-889c501d-753e-4d4b-b2fb-75ac70394619 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=734650258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.734650258 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.294305475 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 27065906 ps |
| CPU time | 3.06 seconds |
| Started | Jan 21 10:39:48 PM PST 24 |
| Finished | Jan 21 10:39:53 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-9892c9af-3a6e-49ac-9c18-8c50da804656 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=294305475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.294305475 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1111306212 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 126249452334 ps |
| CPU time | 526.58 seconds |
| Started | Jan 21 10:39:51 PM PST 24 |
| Finished | Jan 21 10:48:39 PM PST 24 |
| Peak memory | 211840 kb |
| Host | smart-bd9c7302-d179-446e-9066-45d56e69e492 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1111306212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.1111306212 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2117139370 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1124337441 ps |
| CPU time | 26.48 seconds |
| Started | Jan 21 10:39:55 PM PST 24 |
| Finished | Jan 21 10:40:23 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-3e5db215-87f4-442e-9c9c-829e757ea85a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2117139370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2117139370 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.4033132562 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 98947686 ps |
| CPU time | 2.85 seconds |
| Started | Jan 21 10:39:56 PM PST 24 |
| Finished | Jan 21 10:40:00 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-87c7666c-cf38-4bb0-8aea-0bebd433ca72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4033132562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.4033132562 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.1936828412 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2008954539 ps |
| CPU time | 37.6 seconds |
| Started | Jan 21 10:39:50 PM PST 24 |
| Finished | Jan 21 10:40:29 PM PST 24 |
| Peak memory | 204040 kb |
| Host | smart-aad039ca-f28f-4598-8261-1cee688739c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1936828412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1936828412 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2267331677 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 21128420742 ps |
| CPU time | 102.2 seconds |
| Started | Jan 21 10:39:49 PM PST 24 |
| Finished | Jan 21 10:41:32 PM PST 24 |
| Peak memory | 204604 kb |
| Host | smart-6af6f9b8-f440-446d-ab81-af34dbf4df22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267331677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2267331677 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.981367994 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4210510993 ps |
| CPU time | 23.43 seconds |
| Started | Jan 21 10:39:53 PM PST 24 |
| Finished | Jan 21 10:40:17 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-db80806e-3a55-41bf-a6d9-48c952cdffda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=981367994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.981367994 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.2503055856 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28530074 ps |
| CPU time | 3.4 seconds |
| Started | Jan 21 10:39:50 PM PST 24 |
| Finished | Jan 21 10:39:55 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-219fdf22-d8fa-40d3-8aac-ad2a42ad76fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503055856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2503055856 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.4168526594 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 400981707 ps |
| CPU time | 9.24 seconds |
| Started | Jan 21 10:39:53 PM PST 24 |
| Finished | Jan 21 10:40:03 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-7831a409-9185-46a6-aabd-5e42a75cf69d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4168526594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4168526594 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.2231464968 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 156815957 ps |
| CPU time | 3.64 seconds |
| Started | Jan 21 10:39:44 PM PST 24 |
| Finished | Jan 21 10:39:49 PM PST 24 |
| Peak memory | 203340 kb |
| Host | smart-bdd12091-ac7b-490c-86f3-203c88642cd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2231464968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2231464968 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2836247164 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 5351695261 ps |
| CPU time | 26.64 seconds |
| Started | Jan 21 10:39:46 PM PST 24 |
| Finished | Jan 21 10:40:14 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-00283d00-dc26-4dce-a4f6-c8082c611b42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836247164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2836247164 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.729130009 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 7068326162 ps |
| CPU time | 37.11 seconds |
| Started | Jan 21 10:39:46 PM PST 24 |
| Finished | Jan 21 10:40:24 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-da4d18f5-a968-41ed-8991-1e4887c35d29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=729130009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.729130009 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.880424481 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 76633009 ps |
| CPU time | 2.44 seconds |
| Started | Jan 21 10:39:46 PM PST 24 |
| Finished | Jan 21 10:39:49 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-66b1e410-26e7-4120-9aa6-500ad9889fa3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880424481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.880424481 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.164436936 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1659565475 ps |
| CPU time | 47.79 seconds |
| Started | Jan 21 10:40:01 PM PST 24 |
| Finished | Jan 21 10:40:54 PM PST 24 |
| Peak memory | 211556 kb |
| Host | smart-c4edc6b5-87fd-44f6-bd76-5f08d2ddd271 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=164436936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.164436936 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1509876679 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 4432690418 ps |
| CPU time | 159.23 seconds |
| Started | Jan 21 10:40:04 PM PST 24 |
| Finished | Jan 21 10:42:49 PM PST 24 |
| Peak memory | 208036 kb |
| Host | smart-b632eaf5-59ab-4e39-a13a-58f74c67a07b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1509876679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1509876679 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.465514641 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 764891776 ps |
| CPU time | 342.38 seconds |
| Started | Jan 21 10:40:02 PM PST 24 |
| Finished | Jan 21 10:45:50 PM PST 24 |
| Peak memory | 207904 kb |
| Host | smart-e17f3401-2a77-4b88-a160-0f92c2eeaaac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=465514641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand _reset.465514641 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3009435390 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2971343367 ps |
| CPU time | 357.32 seconds |
| Started | Jan 21 10:40:02 PM PST 24 |
| Finished | Jan 21 10:46:04 PM PST 24 |
| Peak memory | 219856 kb |
| Host | smart-06927715-2aca-4048-bcf2-cbe472984eb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3009435390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.3009435390 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.4173402948 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 107295118 ps |
| CPU time | 7.49 seconds |
| Started | Jan 21 10:39:56 PM PST 24 |
| Finished | Jan 21 10:40:04 PM PST 24 |
| Peak memory | 211604 kb |
| Host | smart-7587ffd8-e830-4c3f-8f6e-481effdde762 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4173402948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.4173402948 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.804441930 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2255599094 ps |
| CPU time | 64.72 seconds |
| Started | Jan 21 10:32:30 PM PST 24 |
| Finished | Jan 21 10:33:37 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-618478f0-ea38-4e56-8aed-e555fa3c1a38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=804441930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.804441930 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3230222441 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 526843213 ps |
| CPU time | 19.26 seconds |
| Started | Jan 21 10:32:31 PM PST 24 |
| Finished | Jan 21 10:32:53 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-7c4eb59e-621b-46fc-8dca-354eb337f3a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3230222441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3230222441 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2748856753 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 347472182 ps |
| CPU time | 10.26 seconds |
| Started | Jan 21 10:32:30 PM PST 24 |
| Finished | Jan 21 10:32:43 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-e180d5e3-c2ad-4143-b983-3b6a2760fe6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2748856753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2748856753 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.2711124914 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 67160553 ps |
| CPU time | 7.35 seconds |
| Started | Jan 21 10:32:28 PM PST 24 |
| Finished | Jan 21 10:32:38 PM PST 24 |
| Peak memory | 211556 kb |
| Host | smart-c054c94c-03e1-437b-8864-545cca320459 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2711124914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2711124914 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3802273069 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 73636279744 ps |
| CPU time | 274.24 seconds |
| Started | Jan 21 10:32:30 PM PST 24 |
| Finished | Jan 21 10:37:08 PM PST 24 |
| Peak memory | 204516 kb |
| Host | smart-9c453ff8-c7c6-4f39-9530-b949a7db5c9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802273069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3802273069 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3033248678 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 35958843712 ps |
| CPU time | 172.53 seconds |
| Started | Jan 21 10:32:31 PM PST 24 |
| Finished | Jan 21 10:35:26 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-eac7595f-8a64-4597-8142-5e2269d58d4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3033248678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3033248678 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.229973440 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 159585166 ps |
| CPU time | 19.38 seconds |
| Started | Jan 21 10:32:26 PM PST 24 |
| Finished | Jan 21 10:32:47 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-769aa6e7-2b0b-4f96-98b2-7513d49039fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229973440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.229973440 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3726102196 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 91916860 ps |
| CPU time | 5.86 seconds |
| Started | Jan 21 10:32:28 PM PST 24 |
| Finished | Jan 21 10:32:37 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-61106d37-4604-4591-96f7-ce6a816cc02c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3726102196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3726102196 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.3804983412 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 128296277 ps |
| CPU time | 3.92 seconds |
| Started | Jan 21 10:32:27 PM PST 24 |
| Finished | Jan 21 10:32:32 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-ab20baa6-9206-4596-8dad-6cdb9079f2ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3804983412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3804983412 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.147650097 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 8459614575 ps |
| CPU time | 30.76 seconds |
| Started | Jan 21 10:32:30 PM PST 24 |
| Finished | Jan 21 10:33:03 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-6677c4d3-0585-4e3e-a136-6993e30846c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=147650097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.147650097 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3124846286 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 9839459463 ps |
| CPU time | 24.95 seconds |
| Started | Jan 21 10:32:29 PM PST 24 |
| Finished | Jan 21 10:32:56 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-936b61ed-a3d9-4ab5-9a9e-0801e27c6dab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3124846286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3124846286 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1038940958 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 62196170 ps |
| CPU time | 2.38 seconds |
| Started | Jan 21 10:32:27 PM PST 24 |
| Finished | Jan 21 10:32:31 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-deefcdf0-975d-4f91-a06e-1c773b489172 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038940958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1038940958 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.3773294938 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4382154102 ps |
| CPU time | 86.54 seconds |
| Started | Jan 21 10:32:28 PM PST 24 |
| Finished | Jan 21 10:33:56 PM PST 24 |
| Peak memory | 206584 kb |
| Host | smart-e58e78c7-5bc6-4c17-8335-4fc6a3849521 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3773294938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3773294938 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.4204035911 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1179562895 ps |
| CPU time | 88.3 seconds |
| Started | Jan 21 10:32:30 PM PST 24 |
| Finished | Jan 21 10:34:01 PM PST 24 |
| Peak memory | 206064 kb |
| Host | smart-e6accdcc-be1a-4d80-872d-64e56011d4b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4204035911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4204035911 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.848920147 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 300213414 ps |
| CPU time | 104.52 seconds |
| Started | Jan 21 10:32:27 PM PST 24 |
| Finished | Jan 21 10:34:12 PM PST 24 |
| Peak memory | 208280 kb |
| Host | smart-d6cf5cdd-1c51-4c7a-874d-8123c2aa37d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=848920147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_ reset.848920147 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1267788055 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1354807629 ps |
| CPU time | 332.38 seconds |
| Started | Jan 21 10:32:29 PM PST 24 |
| Finished | Jan 21 10:38:04 PM PST 24 |
| Peak memory | 219820 kb |
| Host | smart-9bfc66bb-46cd-43c4-9d80-ef888907b58f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1267788055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1267788055 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.38415319 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 90194091 ps |
| CPU time | 10.42 seconds |
| Started | Jan 21 10:32:29 PM PST 24 |
| Finished | Jan 21 10:32:42 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-b0b09365-94af-4bf0-9059-b5c6950dbfce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=38415319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.38415319 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1374118712 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 768411528 ps |
| CPU time | 7.61 seconds |
| Started | Jan 21 10:40:10 PM PST 24 |
| Finished | Jan 21 10:40:20 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-f7f6bca3-5a63-458c-b46f-75b2605330c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1374118712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1374118712 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3425757299 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 212010962941 ps |
| CPU time | 588.05 seconds |
| Started | Jan 21 10:40:07 PM PST 24 |
| Finished | Jan 21 10:50:00 PM PST 24 |
| Peak memory | 206648 kb |
| Host | smart-22d95952-5dac-43a4-ab0f-4640c9251b33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3425757299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.3425757299 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2622398812 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1043031943 ps |
| CPU time | 13.92 seconds |
| Started | Jan 21 10:40:16 PM PST 24 |
| Finished | Jan 21 10:40:32 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-b08fd4f3-c8ee-467a-a9f8-8e1e345b8b79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2622398812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2622398812 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.385527379 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 247132677 ps |
| CPU time | 18.37 seconds |
| Started | Jan 21 10:56:35 PM PST 24 |
| Finished | Jan 21 10:56:54 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-9ad43034-c565-442e-ab50-a3001c63cc59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=385527379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.385527379 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.1303252843 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1587202243 ps |
| CPU time | 29.41 seconds |
| Started | Jan 21 10:40:01 PM PST 24 |
| Finished | Jan 21 10:40:36 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-306b67dc-29fe-4afb-be47-63cca00a90f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1303252843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1303252843 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1784221354 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 6232259686 ps |
| CPU time | 29.57 seconds |
| Started | Jan 21 10:40:15 PM PST 24 |
| Finished | Jan 21 10:40:46 PM PST 24 |
| Peak memory | 204224 kb |
| Host | smart-aa039f17-32bc-4269-8c7c-f71af46a9726 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784221354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1784221354 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1791276270 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 21126983152 ps |
| CPU time | 106.47 seconds |
| Started | Jan 21 10:40:11 PM PST 24 |
| Finished | Jan 21 10:42:00 PM PST 24 |
| Peak memory | 211692 kb |
| Host | smart-05422a00-7840-4b8b-8d59-24ecd833e19b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1791276270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1791276270 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1919942047 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 288433713 ps |
| CPU time | 22.95 seconds |
| Started | Jan 21 10:40:01 PM PST 24 |
| Finished | Jan 21 10:40:29 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-a35f05e0-7ba5-4cfb-83da-3f1e590f95fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919942047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1919942047 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.1718347052 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1019040823 ps |
| CPU time | 17.55 seconds |
| Started | Jan 21 10:40:17 PM PST 24 |
| Finished | Jan 21 10:40:36 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-057b4387-8dcd-4078-a833-c6df8d1c9504 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1718347052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1718347052 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.3950012620 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 143800920 ps |
| CPU time | 3.62 seconds |
| Started | Jan 21 10:40:06 PM PST 24 |
| Finished | Jan 21 10:40:14 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-16ce4b5b-22b3-4153-ad7d-522ee39b8f3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3950012620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3950012620 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3961792170 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 10487545570 ps |
| CPU time | 30.6 seconds |
| Started | Jan 21 10:40:02 PM PST 24 |
| Finished | Jan 21 10:40:38 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-ff766570-28aa-4f50-935d-5537e906afbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961792170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3961792170 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1184203542 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4995259761 ps |
| CPU time | 29.7 seconds |
| Started | Jan 21 10:40:05 PM PST 24 |
| Finished | Jan 21 10:40:39 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-4c7fb1ae-b58b-4008-af00-52c4ebdd67aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1184203542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1184203542 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3235982041 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 36464141 ps |
| CPU time | 2.49 seconds |
| Started | Jan 21 11:18:05 PM PST 24 |
| Finished | Jan 21 11:18:11 PM PST 24 |
| Peak memory | 203512 kb |
| Host | smart-81781c7f-f07f-47bf-b8f9-c2a720803fb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235982041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3235982041 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.3776066595 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 578923508 ps |
| CPU time | 45.72 seconds |
| Started | Jan 21 10:40:17 PM PST 24 |
| Finished | Jan 21 10:41:04 PM PST 24 |
| Peak memory | 205600 kb |
| Host | smart-a489af54-5e64-489b-aac4-1bc0cd3f53c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3776066595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3776066595 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3684924171 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 5968955512 ps |
| CPU time | 112.34 seconds |
| Started | Jan 21 10:40:15 PM PST 24 |
| Finished | Jan 21 10:42:09 PM PST 24 |
| Peak memory | 206784 kb |
| Host | smart-8a303799-4b99-42fc-87d9-0dbe4081ced2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3684924171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3684924171 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2091522711 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 99752910 ps |
| CPU time | 28.43 seconds |
| Started | Jan 21 10:40:17 PM PST 24 |
| Finished | Jan 21 10:40:47 PM PST 24 |
| Peak memory | 206112 kb |
| Host | smart-0bec936f-be2e-47f1-b4c7-50414de97447 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2091522711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2091522711 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.4164979463 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2287683610 ps |
| CPU time | 159.63 seconds |
| Started | Jan 21 10:40:20 PM PST 24 |
| Finished | Jan 21 10:43:01 PM PST 24 |
| Peak memory | 211100 kb |
| Host | smart-cc8b1430-1262-49c0-8b10-046c7063ebc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4164979463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.4164979463 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.4025393494 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 675301571 ps |
| CPU time | 29.43 seconds |
| Started | Jan 21 10:40:13 PM PST 24 |
| Finished | Jan 21 10:40:45 PM PST 24 |
| Peak memory | 205068 kb |
| Host | smart-7dd0c9f1-02fa-4c95-aaf0-4463236dc537 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4025393494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4025393494 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2073627857 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1852463100 ps |
| CPU time | 64.89 seconds |
| Started | Jan 21 10:40:26 PM PST 24 |
| Finished | Jan 21 10:41:32 PM PST 24 |
| Peak memory | 211576 kb |
| Host | smart-559f5ca9-7e9a-463e-870c-5bde085ca079 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2073627857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2073627857 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3973614107 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 31485405069 ps |
| CPU time | 279.37 seconds |
| Started | Jan 21 10:40:36 PM PST 24 |
| Finished | Jan 21 10:45:22 PM PST 24 |
| Peak memory | 205796 kb |
| Host | smart-25bcc39a-6896-4f94-9ff2-b3073b41897f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3973614107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.3973614107 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.297518205 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 363085582 ps |
| CPU time | 9 seconds |
| Started | Jan 21 10:40:36 PM PST 24 |
| Finished | Jan 21 10:40:53 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-3948dc24-2f3f-418f-bbf0-736628aae95c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=297518205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.297518205 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.3797424818 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 714704203 ps |
| CPU time | 23.83 seconds |
| Started | Jan 21 10:40:37 PM PST 24 |
| Finished | Jan 21 10:41:08 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-487bb9d4-be53-4933-ad4a-ca4e72fd3948 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3797424818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3797424818 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.4025054107 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 464551580 ps |
| CPU time | 4.61 seconds |
| Started | Jan 21 11:13:59 PM PST 24 |
| Finished | Jan 21 11:14:06 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-4a2e259b-49ad-4ea8-9f3e-43d662a83340 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4025054107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.4025054107 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1682960413 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 8278728602 ps |
| CPU time | 37.78 seconds |
| Started | Jan 21 10:40:34 PM PST 24 |
| Finished | Jan 21 10:41:18 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-458b9138-5e50-460c-8b5b-39b8ab56552a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682960413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1682960413 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.621174018 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 36636060924 ps |
| CPU time | 127.69 seconds |
| Started | Jan 21 10:40:26 PM PST 24 |
| Finished | Jan 21 10:42:34 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-a97062ae-a112-4178-83bc-031d170d4f54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=621174018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.621174018 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.3450282534 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 191069581 ps |
| CPU time | 27.48 seconds |
| Started | Jan 21 10:58:16 PM PST 24 |
| Finished | Jan 21 10:58:45 PM PST 24 |
| Peak memory | 211592 kb |
| Host | smart-f722d4a6-140f-42cc-b943-e1ba7504615f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450282534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3450282534 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.1406265090 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 427258181 ps |
| CPU time | 7.61 seconds |
| Started | Jan 21 10:40:36 PM PST 24 |
| Finished | Jan 21 10:40:51 PM PST 24 |
| Peak memory | 203592 kb |
| Host | smart-a21c04d0-aba9-41ab-a56a-c5363606f64e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1406265090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1406265090 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.2910777229 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 42737654 ps |
| CPU time | 2.37 seconds |
| Started | Jan 21 10:40:19 PM PST 24 |
| Finished | Jan 21 10:40:23 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-0d49da29-93ae-43ef-a6d5-8cc62925a083 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2910777229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2910777229 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.507751748 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 13580896141 ps |
| CPU time | 28.62 seconds |
| Started | Jan 21 10:40:25 PM PST 24 |
| Finished | Jan 21 10:40:55 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-c5726e00-811b-4cca-8984-e7b12c58ba0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=507751748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.507751748 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.639851875 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 7343839552 ps |
| CPU time | 24.18 seconds |
| Started | Jan 21 10:55:55 PM PST 24 |
| Finished | Jan 21 10:56:21 PM PST 24 |
| Peak memory | 203536 kb |
| Host | smart-68197d46-c3a0-42d3-9891-95d1cfb678f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=639851875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.639851875 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1482055298 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 81552290 ps |
| CPU time | 2.4 seconds |
| Started | Jan 21 10:40:21 PM PST 24 |
| Finished | Jan 21 10:40:25 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-ff3d9c25-81a2-4f53-a204-a8f2c3779803 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482055298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1482055298 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.4225071848 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 7805051127 ps |
| CPU time | 275.54 seconds |
| Started | Jan 21 10:40:36 PM PST 24 |
| Finished | Jan 21 10:45:19 PM PST 24 |
| Peak memory | 206064 kb |
| Host | smart-1c38f891-027f-4be8-a5e1-a974af2ee83a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4225071848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.4225071848 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1699533141 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 6774855757 ps |
| CPU time | 144.09 seconds |
| Started | Jan 21 10:40:36 PM PST 24 |
| Finished | Jan 21 10:43:07 PM PST 24 |
| Peak memory | 205144 kb |
| Host | smart-7e556a23-e453-4d2a-8116-521fb5db13d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1699533141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1699533141 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.4257089688 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 55019691 ps |
| CPU time | 3.5 seconds |
| Started | Jan 21 10:40:36 PM PST 24 |
| Finished | Jan 21 10:40:47 PM PST 24 |
| Peak memory | 204324 kb |
| Host | smart-3a4ee92e-60da-40b4-bacd-0681ea8271e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4257089688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.4257089688 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.3706775591 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 280639625 ps |
| CPU time | 99.51 seconds |
| Started | Jan 21 10:40:37 PM PST 24 |
| Finished | Jan 21 10:42:23 PM PST 24 |
| Peak memory | 209088 kb |
| Host | smart-778676f0-c69c-4893-b7cf-a844d84712c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3706775591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.3706775591 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.2927340876 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 101007671 ps |
| CPU time | 13.81 seconds |
| Started | Jan 21 10:40:38 PM PST 24 |
| Finished | Jan 21 10:40:58 PM PST 24 |
| Peak memory | 211604 kb |
| Host | smart-fb1528b7-c699-48b7-8826-b7bff8798335 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2927340876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2927340876 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3497682980 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1479454831 ps |
| CPU time | 49.36 seconds |
| Started | Jan 21 10:40:39 PM PST 24 |
| Finished | Jan 21 10:41:33 PM PST 24 |
| Peak memory | 205096 kb |
| Host | smart-8632489e-c990-49f8-a679-9169d516a44d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3497682980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3497682980 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.50753071 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 224721350585 ps |
| CPU time | 829.2 seconds |
| Started | Jan 21 10:40:42 PM PST 24 |
| Finished | Jan 21 10:54:38 PM PST 24 |
| Peak memory | 207328 kb |
| Host | smart-2dfa9125-9f65-4d72-be6e-8ee071246f2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=50753071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow _rsp.50753071 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1685788194 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1986178134 ps |
| CPU time | 15.59 seconds |
| Started | Jan 21 11:13:42 PM PST 24 |
| Finished | Jan 21 11:13:58 PM PST 24 |
| Peak memory | 203540 kb |
| Host | smart-2977e7e3-8ad3-41c8-89f1-0f53bd214665 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1685788194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1685788194 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.846309341 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1022141496 ps |
| CPU time | 32.89 seconds |
| Started | Jan 21 10:40:45 PM PST 24 |
| Finished | Jan 21 10:41:23 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-77ee0f92-f62c-4f29-b3e7-3483a9ada74c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=846309341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.846309341 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.4113012862 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 399081076 ps |
| CPU time | 21.07 seconds |
| Started | Jan 21 10:40:40 PM PST 24 |
| Finished | Jan 21 10:41:05 PM PST 24 |
| Peak memory | 204816 kb |
| Host | smart-3c1ad1a7-bd7e-4e27-ac38-647415355122 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4113012862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.4113012862 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.3059781494 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 50054173902 ps |
| CPU time | 178.05 seconds |
| Started | Jan 21 10:40:47 PM PST 24 |
| Finished | Jan 21 10:43:49 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-a97cb0d1-3260-4f75-b0c3-c6e3d391ff27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059781494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3059781494 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2576980527 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 15487297872 ps |
| CPU time | 71.08 seconds |
| Started | Jan 21 10:40:40 PM PST 24 |
| Finished | Jan 21 10:41:55 PM PST 24 |
| Peak memory | 204608 kb |
| Host | smart-8d1f352c-33cc-45df-8da5-8b068b599f2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2576980527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2576980527 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1040126773 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 90099616 ps |
| CPU time | 11.45 seconds |
| Started | Jan 21 10:40:44 PM PST 24 |
| Finished | Jan 21 10:41:01 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-14711e7d-b1b3-4896-acbd-e847196ec244 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040126773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1040126773 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.2126013751 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 8005146806 ps |
| CPU time | 35.99 seconds |
| Started | Jan 21 10:40:41 PM PST 24 |
| Finished | Jan 21 10:41:22 PM PST 24 |
| Peak memory | 204056 kb |
| Host | smart-4aa79f2c-6aca-47b3-b3db-0195b8a42f69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2126013751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2126013751 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.2811572862 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 155471994 ps |
| CPU time | 3.5 seconds |
| Started | Jan 21 10:40:36 PM PST 24 |
| Finished | Jan 21 10:40:47 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-5cc9a8d1-d479-4cd5-afeb-d16ffcbb81f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2811572862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2811572862 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.533276524 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 10674718120 ps |
| CPU time | 35.66 seconds |
| Started | Jan 21 10:40:40 PM PST 24 |
| Finished | Jan 21 10:41:20 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-26b4ac7b-bf39-4f35-8294-e3ef7d27e283 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=533276524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.533276524 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3410935869 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4359134720 ps |
| CPU time | 32.52 seconds |
| Started | Jan 21 10:40:47 PM PST 24 |
| Finished | Jan 21 10:41:23 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-27d1ab8e-7f52-4fc7-847a-6dd108f3e295 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3410935869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3410935869 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2940176269 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 27990593 ps |
| CPU time | 2.18 seconds |
| Started | Jan 21 10:40:40 PM PST 24 |
| Finished | Jan 21 10:40:46 PM PST 24 |
| Peak memory | 203368 kb |
| Host | smart-212f1909-c2fe-4a40-90f2-955cc66b8eec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940176269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2940176269 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2916466318 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 425405605 ps |
| CPU time | 4.02 seconds |
| Started | Jan 21 10:40:55 PM PST 24 |
| Finished | Jan 21 10:41:07 PM PST 24 |
| Peak memory | 203576 kb |
| Host | smart-376c914b-dcbd-4f76-98c8-5b2aa86af9be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2916466318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2916466318 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.2404083835 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 15494295303 ps |
| CPU time | 147.66 seconds |
| Started | Jan 21 10:40:53 PM PST 24 |
| Finished | Jan 21 10:43:28 PM PST 24 |
| Peak memory | 208040 kb |
| Host | smart-e902be8e-1ce0-466b-b55b-766913a54477 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2404083835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2404083835 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.300107306 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 197987781 ps |
| CPU time | 69.21 seconds |
| Started | Jan 21 11:22:14 PM PST 24 |
| Finished | Jan 21 11:23:33 PM PST 24 |
| Peak memory | 208132 kb |
| Host | smart-7ca68979-79dc-4084-aa46-0f42afb11927 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=300107306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand _reset.300107306 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2532291329 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 11538947328 ps |
| CPU time | 568.36 seconds |
| Started | Jan 21 10:40:48 PM PST 24 |
| Finished | Jan 21 10:50:19 PM PST 24 |
| Peak memory | 220888 kb |
| Host | smart-56455713-baaa-46bf-97ab-8e3e4b257c9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2532291329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.2532291329 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1836234241 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 521719024 ps |
| CPU time | 22.24 seconds |
| Started | Jan 21 10:40:39 PM PST 24 |
| Finished | Jan 21 10:41:06 PM PST 24 |
| Peak memory | 211508 kb |
| Host | smart-89e3effe-9c24-4e9c-a1d7-fed28966ab21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1836234241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1836234241 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.1714507874 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3232750741 ps |
| CPU time | 62.18 seconds |
| Started | Jan 21 10:41:00 PM PST 24 |
| Finished | Jan 21 10:42:10 PM PST 24 |
| Peak memory | 206324 kb |
| Host | smart-db2ff1d6-b060-40a8-bc38-daaab4929030 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1714507874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1714507874 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1169061492 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 127167778326 ps |
| CPU time | 404.95 seconds |
| Started | Jan 21 10:41:01 PM PST 24 |
| Finished | Jan 21 10:47:53 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-e02b9c31-3db2-409a-92cb-f72a25f29e55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1169061492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.1169061492 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3082114440 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2778691931 ps |
| CPU time | 30.93 seconds |
| Started | Jan 21 10:41:07 PM PST 24 |
| Finished | Jan 21 10:41:42 PM PST 24 |
| Peak memory | 203540 kb |
| Host | smart-84ab881b-c742-4ed3-b8d1-0d8e16f209bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3082114440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3082114440 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.1973642700 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 4511086425 ps |
| CPU time | 29.99 seconds |
| Started | Jan 21 10:41:02 PM PST 24 |
| Finished | Jan 21 10:41:39 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-333336b5-3fa5-4245-b076-c98fd89b655f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1973642700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1973642700 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2222264878 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1375488054 ps |
| CPU time | 41.38 seconds |
| Started | Jan 21 11:06:18 PM PST 24 |
| Finished | Jan 21 11:07:08 PM PST 24 |
| Peak memory | 211672 kb |
| Host | smart-79e23a9c-d3b4-49b8-8bc5-42cc116e857c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2222264878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2222264878 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.4139389272 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 21146791298 ps |
| CPU time | 104.14 seconds |
| Started | Jan 21 10:41:02 PM PST 24 |
| Finished | Jan 21 10:42:53 PM PST 24 |
| Peak memory | 204696 kb |
| Host | smart-160b233b-765f-4465-8874-ac9f97f58b01 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139389272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.4139389272 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3914734873 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8859353062 ps |
| CPU time | 40.83 seconds |
| Started | Jan 21 10:41:01 PM PST 24 |
| Finished | Jan 21 10:41:49 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-39d48550-e24c-4b12-83bd-cb04feda3637 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3914734873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3914734873 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.1191425393 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 191254162 ps |
| CPU time | 21.83 seconds |
| Started | Jan 21 10:40:57 PM PST 24 |
| Finished | Jan 21 10:41:27 PM PST 24 |
| Peak memory | 211772 kb |
| Host | smart-1f540065-1827-4e69-a84a-d2e148d5a658 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191425393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1191425393 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.2093829163 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2061778824 ps |
| CPU time | 30.02 seconds |
| Started | Jan 21 10:41:04 PM PST 24 |
| Finished | Jan 21 10:41:39 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-971e4336-0969-4fe3-b86c-262338ecd499 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2093829163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2093829163 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.157650221 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 134500268 ps |
| CPU time | 3.31 seconds |
| Started | Jan 21 10:40:55 PM PST 24 |
| Finished | Jan 21 10:41:06 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-b1a76930-6646-458e-98a5-2bde3bce5e42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=157650221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.157650221 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2512133635 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 16556729177 ps |
| CPU time | 38.1 seconds |
| Started | Jan 21 10:40:48 PM PST 24 |
| Finished | Jan 21 10:41:29 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-5d442024-a7f1-4e70-8e5b-5ca81f241632 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512133635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2512133635 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.91703281 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3369117153 ps |
| CPU time | 24.92 seconds |
| Started | Jan 21 11:16:19 PM PST 24 |
| Finished | Jan 21 11:16:46 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-d44c66f0-6b4a-4275-b720-3ad164b1eb03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=91703281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.91703281 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1483587055 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 34043674 ps |
| CPU time | 2.13 seconds |
| Started | Jan 21 10:40:51 PM PST 24 |
| Finished | Jan 21 10:41:01 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-446bacc1-a7a4-48db-a23c-2083b2632319 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483587055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1483587055 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.2621921973 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 6851673439 ps |
| CPU time | 230.38 seconds |
| Started | Jan 21 10:41:04 PM PST 24 |
| Finished | Jan 21 10:45:00 PM PST 24 |
| Peak memory | 207000 kb |
| Host | smart-18130847-208d-4623-b939-fbfcefddfa45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2621921973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2621921973 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.163685807 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 4902392998 ps |
| CPU time | 79.36 seconds |
| Started | Jan 21 10:41:10 PM PST 24 |
| Finished | Jan 21 10:42:32 PM PST 24 |
| Peak memory | 205876 kb |
| Host | smart-d9bab8ae-bdef-420d-9909-62f89257acc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=163685807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.163685807 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1644155410 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 171367308 ps |
| CPU time | 97.57 seconds |
| Started | Jan 21 10:41:06 PM PST 24 |
| Finished | Jan 21 10:42:49 PM PST 24 |
| Peak memory | 208572 kb |
| Host | smart-3b2ef3a2-b9f3-437f-9fc7-eeafcfd4c739 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1644155410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.1644155410 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3915430511 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 83432150 ps |
| CPU time | 24.18 seconds |
| Started | Jan 21 10:41:16 PM PST 24 |
| Finished | Jan 21 10:41:41 PM PST 24 |
| Peak memory | 205384 kb |
| Host | smart-768a6e2f-03de-4195-bf81-eab5404c92aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3915430511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.3915430511 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.1724114178 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 81539152 ps |
| CPU time | 10.06 seconds |
| Started | Jan 21 10:41:10 PM PST 24 |
| Finished | Jan 21 10:41:23 PM PST 24 |
| Peak memory | 211584 kb |
| Host | smart-0f89b745-e11b-4039-a71b-a44eac93abc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1724114178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1724114178 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2520700135 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 845582453 ps |
| CPU time | 36.01 seconds |
| Started | Jan 21 11:09:26 PM PST 24 |
| Finished | Jan 21 11:10:02 PM PST 24 |
| Peak memory | 211712 kb |
| Host | smart-b3c1e216-6d58-4470-87b8-1e98ab7aff22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2520700135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2520700135 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.933826111 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 316987176628 ps |
| CPU time | 596.47 seconds |
| Started | Jan 21 10:41:24 PM PST 24 |
| Finished | Jan 21 10:51:21 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-1efde9fc-5b48-40de-b058-5aec3e670db1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=933826111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo w_rsp.933826111 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1702980370 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 138420408 ps |
| CPU time | 1.87 seconds |
| Started | Jan 21 10:41:28 PM PST 24 |
| Finished | Jan 21 10:41:31 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-9ce4f5fe-2eb6-43f4-8e6e-a1eaabaa231d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1702980370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1702980370 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.1815951786 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 337252436 ps |
| CPU time | 11.86 seconds |
| Started | Jan 21 10:41:24 PM PST 24 |
| Finished | Jan 21 10:41:37 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-36024720-7f33-4e16-a214-c90e9a83997e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1815951786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1815951786 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.2658014048 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 338962056 ps |
| CPU time | 8.5 seconds |
| Started | Jan 21 10:41:14 PM PST 24 |
| Finished | Jan 21 10:41:24 PM PST 24 |
| Peak memory | 203368 kb |
| Host | smart-db48ad66-7e42-4949-b567-87fa2af16a25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2658014048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2658014048 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.613768994 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 28662955848 ps |
| CPU time | 122.89 seconds |
| Started | Jan 21 10:41:19 PM PST 24 |
| Finished | Jan 21 10:43:24 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-36a55588-2534-4aec-a247-d6b965878a4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=613768994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.613768994 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3351912854 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 30513747915 ps |
| CPU time | 146.26 seconds |
| Started | Jan 21 10:41:21 PM PST 24 |
| Finished | Jan 21 10:43:48 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-88c143b3-1f0a-48c0-a9d4-fe6ae8d27209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3351912854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3351912854 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1692052625 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 132010588 ps |
| CPU time | 17 seconds |
| Started | Jan 21 10:41:20 PM PST 24 |
| Finished | Jan 21 10:41:38 PM PST 24 |
| Peak memory | 211604 kb |
| Host | smart-b4274166-66ae-413d-8493-a48538f8b2b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692052625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1692052625 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.2673828811 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 322212679 ps |
| CPU time | 4.39 seconds |
| Started | Jan 21 10:41:31 PM PST 24 |
| Finished | Jan 21 10:41:38 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-61a41082-0d66-4994-9056-428b5e6a933b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2673828811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2673828811 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.3646155979 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 123494025 ps |
| CPU time | 2.45 seconds |
| Started | Jan 21 10:41:15 PM PST 24 |
| Finished | Jan 21 10:41:19 PM PST 24 |
| Peak memory | 203300 kb |
| Host | smart-3a6096a0-3dd7-4fc6-8c5f-6016630e2556 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3646155979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3646155979 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1504984646 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 5661630007 ps |
| CPU time | 25.17 seconds |
| Started | Jan 21 10:41:13 PM PST 24 |
| Finished | Jan 21 10:41:39 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-9ecc3eb4-3275-46ec-b30f-1acb0adc16f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504984646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1504984646 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1669104188 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3607597405 ps |
| CPU time | 29.07 seconds |
| Started | Jan 21 10:41:12 PM PST 24 |
| Finished | Jan 21 10:41:43 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-60764764-949f-42c3-84b5-822bf3bd1dd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1669104188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1669104188 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.4061819277 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 23235921 ps |
| CPU time | 2.16 seconds |
| Started | Jan 21 10:41:12 PM PST 24 |
| Finished | Jan 21 10:41:16 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-27b9d657-d2f7-4166-b47f-bd0d4358e8a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061819277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.4061819277 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.3248900637 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 5940658310 ps |
| CPU time | 113.5 seconds |
| Started | Jan 21 11:42:52 PM PST 24 |
| Finished | Jan 21 11:44:46 PM PST 24 |
| Peak memory | 207012 kb |
| Host | smart-4acf0eb9-35ea-4eed-bf73-89db2b625239 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3248900637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3248900637 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1291468822 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 7920196806 ps |
| CPU time | 185.97 seconds |
| Started | Jan 21 10:41:39 PM PST 24 |
| Finished | Jan 21 10:44:52 PM PST 24 |
| Peak memory | 209008 kb |
| Host | smart-fc8be9e3-0f55-4c89-93ac-12109179b2df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1291468822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1291468822 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2758949238 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 423894130 ps |
| CPU time | 189.45 seconds |
| Started | Jan 21 10:41:38 PM PST 24 |
| Finished | Jan 21 10:44:52 PM PST 24 |
| Peak memory | 208656 kb |
| Host | smart-d0bbc029-04cf-41a0-a8ab-5e09639bb2cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2758949238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.2758949238 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.652711143 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5378322834 ps |
| CPU time | 86.3 seconds |
| Started | Jan 21 10:41:36 PM PST 24 |
| Finished | Jan 21 10:43:07 PM PST 24 |
| Peak memory | 205080 kb |
| Host | smart-e43df7bb-98f5-427b-9d2e-39b9f0c3ccbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=652711143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.652711143 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2541441539 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 113191182 ps |
| CPU time | 13.27 seconds |
| Started | Jan 21 10:41:24 PM PST 24 |
| Finished | Jan 21 10:41:38 PM PST 24 |
| Peak memory | 204552 kb |
| Host | smart-93dea883-42e4-442e-8d8a-acda71d9b1ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2541441539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2541441539 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.1529192475 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 68912859 ps |
| CPU time | 9.61 seconds |
| Started | Jan 21 10:41:37 PM PST 24 |
| Finished | Jan 21 10:41:51 PM PST 24 |
| Peak memory | 211552 kb |
| Host | smart-fd2e8a32-7cbe-4c63-8117-3664aaa5b994 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1529192475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1529192475 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2618595182 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3276691567 ps |
| CPU time | 31.43 seconds |
| Started | Jan 21 10:57:22 PM PST 24 |
| Finished | Jan 21 10:57:59 PM PST 24 |
| Peak memory | 203512 kb |
| Host | smart-7ba0d956-f65d-46cb-82e0-ec5f5f7f2dd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2618595182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.2618595182 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.59661404 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1664810904 ps |
| CPU time | 12.56 seconds |
| Started | Jan 21 11:05:54 PM PST 24 |
| Finished | Jan 21 11:06:08 PM PST 24 |
| Peak memory | 203616 kb |
| Host | smart-9fddb1f5-1bd3-4726-9106-7edee5eaaff9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=59661404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.59661404 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.1364090484 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1757880584 ps |
| CPU time | 39.7 seconds |
| Started | Jan 21 11:08:58 PM PST 24 |
| Finished | Jan 21 11:09:38 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-dceb42e0-0b7a-41bf-a91b-4d1b2d795f22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1364090484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1364090484 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.4082232121 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 148219942 ps |
| CPU time | 19.94 seconds |
| Started | Jan 21 10:41:37 PM PST 24 |
| Finished | Jan 21 10:42:01 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-32500c67-7396-468e-a4d6-05a942abe51d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4082232121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.4082232121 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.1465256037 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 26528703925 ps |
| CPU time | 36.89 seconds |
| Started | Jan 21 10:41:36 PM PST 24 |
| Finished | Jan 21 10:42:18 PM PST 24 |
| Peak memory | 204152 kb |
| Host | smart-3a62d3ee-19af-4528-ab5b-2a52931e6019 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465256037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1465256037 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.642639105 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 6837208006 ps |
| CPU time | 60.4 seconds |
| Started | Jan 21 10:41:37 PM PST 24 |
| Finished | Jan 21 10:42:42 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-4e294618-d5cc-499a-a818-53ca2191d5b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=642639105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.642639105 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.2971201159 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 780288791 ps |
| CPU time | 21.69 seconds |
| Started | Jan 21 10:41:38 PM PST 24 |
| Finished | Jan 21 10:42:04 PM PST 24 |
| Peak memory | 204672 kb |
| Host | smart-7a4efae4-ce9f-4f3e-8cf9-5f56172854ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971201159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2971201159 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.3572160845 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 678211893 ps |
| CPU time | 15.12 seconds |
| Started | Jan 21 10:41:40 PM PST 24 |
| Finished | Jan 21 10:42:01 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-1fdfa4a9-79ec-4cf7-bdbf-0188ea9d277e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3572160845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3572160845 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.2854895313 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 182061702 ps |
| CPU time | 3.97 seconds |
| Started | Jan 21 10:41:36 PM PST 24 |
| Finished | Jan 21 10:41:45 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-8ab82d10-fe51-4bb0-90f8-c7987436c751 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2854895313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2854895313 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3807428441 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 39390383427 ps |
| CPU time | 49.89 seconds |
| Started | Jan 21 10:41:36 PM PST 24 |
| Finished | Jan 21 10:42:31 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-d20bd078-1794-4cb4-93dd-62eaa55a3c5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807428441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3807428441 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2011335599 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5195196682 ps |
| CPU time | 21.13 seconds |
| Started | Jan 21 11:20:48 PM PST 24 |
| Finished | Jan 21 11:21:17 PM PST 24 |
| Peak memory | 203556 kb |
| Host | smart-985fffd7-7229-4cb8-9f24-e0e1109b85f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2011335599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2011335599 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2018965560 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 36281116 ps |
| CPU time | 2.31 seconds |
| Started | Jan 21 10:41:39 PM PST 24 |
| Finished | Jan 21 10:41:48 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-469dfa73-9958-45b2-847f-cf39bb6416b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018965560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2018965560 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1541737214 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2681832180 ps |
| CPU time | 187.93 seconds |
| Started | Jan 21 10:41:45 PM PST 24 |
| Finished | Jan 21 10:44:55 PM PST 24 |
| Peak memory | 208352 kb |
| Host | smart-e9e364b9-56dc-4e4b-8abc-f2a6a7cbed57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1541737214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1541737214 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.960167448 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 915413654 ps |
| CPU time | 18.84 seconds |
| Started | Jan 21 10:41:45 PM PST 24 |
| Finished | Jan 21 10:42:06 PM PST 24 |
| Peak memory | 203872 kb |
| Host | smart-4208eafb-425a-450a-affc-fe50e390aab6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960167448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.960167448 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3301667117 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 792616089 ps |
| CPU time | 211.64 seconds |
| Started | Jan 21 10:41:44 PM PST 24 |
| Finished | Jan 21 10:45:18 PM PST 24 |
| Peak memory | 208452 kb |
| Host | smart-49120494-ffb1-444e-a676-66cd75337048 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3301667117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.3301667117 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2840892744 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 34100086 ps |
| CPU time | 39.81 seconds |
| Started | Jan 21 10:41:44 PM PST 24 |
| Finished | Jan 21 10:42:26 PM PST 24 |
| Peak memory | 205748 kb |
| Host | smart-c52a23e9-29c9-4801-a2b5-e6f464011829 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2840892744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.2840892744 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3339856962 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 52610999 ps |
| CPU time | 5.03 seconds |
| Started | Jan 21 10:41:40 PM PST 24 |
| Finished | Jan 21 10:41:51 PM PST 24 |
| Peak memory | 211756 kb |
| Host | smart-cf73cae6-ff58-42d0-a801-a8e62d6a2f63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3339856962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3339856962 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1499729256 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 228302897 ps |
| CPU time | 9.77 seconds |
| Started | Jan 21 10:41:54 PM PST 24 |
| Finished | Jan 21 10:42:05 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-364bedb6-3ec8-42bc-b3ee-eb628a57b9db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1499729256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1499729256 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.381501750 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 111944210310 ps |
| CPU time | 824.18 seconds |
| Started | Jan 21 10:42:01 PM PST 24 |
| Finished | Jan 21 10:55:47 PM PST 24 |
| Peak memory | 211660 kb |
| Host | smart-7dc89ac3-4547-4590-ba80-078afd9fcfb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=381501750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo w_rsp.381501750 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2790844709 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 526809280 ps |
| CPU time | 18.1 seconds |
| Started | Jan 21 10:42:06 PM PST 24 |
| Finished | Jan 21 10:42:25 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-d84a278d-4547-4d98-a817-448ab7c1fae2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2790844709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2790844709 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.1147035138 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 756852219 ps |
| CPU time | 22.9 seconds |
| Started | Jan 21 10:42:01 PM PST 24 |
| Finished | Jan 21 10:42:25 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-d73061bc-b357-4f4c-9423-e80465f752ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1147035138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1147035138 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.4017386382 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1810247748 ps |
| CPU time | 44.72 seconds |
| Started | Jan 21 10:41:54 PM PST 24 |
| Finished | Jan 21 10:42:40 PM PST 24 |
| Peak memory | 204560 kb |
| Host | smart-648e12a8-5597-4063-a78d-6e877b9c8ea9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4017386382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.4017386382 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2897719612 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 46946593467 ps |
| CPU time | 114.94 seconds |
| Started | Jan 21 10:41:52 PM PST 24 |
| Finished | Jan 21 10:43:49 PM PST 24 |
| Peak memory | 211620 kb |
| Host | smart-f748dda6-0082-4e73-97be-4f59516084cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897719612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2897719612 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.3589424852 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 24492045837 ps |
| CPU time | 228.03 seconds |
| Started | Jan 21 10:41:53 PM PST 24 |
| Finished | Jan 21 10:45:42 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-456930b8-d78b-451f-9d4b-df0e79ff0209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3589424852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3589424852 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2052289858 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 13962398 ps |
| CPU time | 2.47 seconds |
| Started | Jan 21 10:41:56 PM PST 24 |
| Finished | Jan 21 10:42:00 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-4e2fa00e-04ed-4f79-9277-0bac7d701b6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052289858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2052289858 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.2053714031 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1367920002 ps |
| CPU time | 31.72 seconds |
| Started | Jan 21 10:41:59 PM PST 24 |
| Finished | Jan 21 10:42:32 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-48c509e7-3533-49aa-b1f8-92d82ca031df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2053714031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2053714031 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.4184816645 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 211480322 ps |
| CPU time | 3.67 seconds |
| Started | Jan 21 10:41:52 PM PST 24 |
| Finished | Jan 21 10:41:57 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-32b0179b-0f27-41ff-882b-f9c3276f1452 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4184816645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4184816645 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2445964320 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 8172351888 ps |
| CPU time | 33.01 seconds |
| Started | Jan 21 10:41:52 PM PST 24 |
| Finished | Jan 21 10:42:26 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-556befd7-2398-49a8-bf21-cacfeb8780a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445964320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2445964320 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.2955652024 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 5683990915 ps |
| CPU time | 33.34 seconds |
| Started | Jan 21 10:41:51 PM PST 24 |
| Finished | Jan 21 10:42:26 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-18710cd4-96ad-4ec0-8ab8-9d4524c21ce4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2955652024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2955652024 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3131111597 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 34124126 ps |
| CPU time | 2.34 seconds |
| Started | Jan 21 10:41:51 PM PST 24 |
| Finished | Jan 21 10:41:55 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-92093eb4-94a4-45df-af55-d1de964df6aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131111597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3131111597 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.1568651661 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 6300466222 ps |
| CPU time | 53.29 seconds |
| Started | Jan 21 10:42:12 PM PST 24 |
| Finished | Jan 21 10:43:06 PM PST 24 |
| Peak memory | 206008 kb |
| Host | smart-4c9e0dec-6c2c-4c4a-96ff-cb65254150c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1568651661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1568651661 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.4253307383 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 635895813 ps |
| CPU time | 13.11 seconds |
| Started | Jan 21 10:42:12 PM PST 24 |
| Finished | Jan 21 10:42:27 PM PST 24 |
| Peak memory | 202980 kb |
| Host | smart-d4b60d24-96ea-4dfb-bdca-9579e6222c2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4253307383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.4253307383 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1488607709 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 77384091 ps |
| CPU time | 70.94 seconds |
| Started | Jan 21 10:42:12 PM PST 24 |
| Finished | Jan 21 10:43:25 PM PST 24 |
| Peak memory | 206472 kb |
| Host | smart-4c7a640d-8989-495d-9cd5-06ef182b7e6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1488607709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.1488607709 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.1432885210 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 576787925 ps |
| CPU time | 143.42 seconds |
| Started | Jan 21 10:42:12 PM PST 24 |
| Finished | Jan 21 10:44:38 PM PST 24 |
| Peak memory | 209132 kb |
| Host | smart-39cad2ce-d360-4af2-a32e-2e9c5400791e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1432885210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.1432885210 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.669415555 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 34906324 ps |
| CPU time | 2.2 seconds |
| Started | Jan 21 10:42:00 PM PST 24 |
| Finished | Jan 21 10:42:04 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-de0a3399-47b4-44c1-9189-23cf774924e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=669415555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.669415555 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.1097085224 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 492563162 ps |
| CPU time | 4.45 seconds |
| Started | Jan 21 10:42:27 PM PST 24 |
| Finished | Jan 21 10:42:33 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-3a28b62d-08b4-4f12-95e2-e6bd1096c1a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1097085224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1097085224 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.535480316 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 56976991408 ps |
| CPU time | 512.48 seconds |
| Started | Jan 21 10:42:25 PM PST 24 |
| Finished | Jan 21 10:50:58 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-b982fd6a-effd-4c5d-ba38-b63b431be768 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=535480316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slo w_rsp.535480316 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1006097469 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 69249711 ps |
| CPU time | 8.7 seconds |
| Started | Jan 21 10:42:26 PM PST 24 |
| Finished | Jan 21 10:42:35 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-96099d4b-7017-460c-a723-e2da938dae64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1006097469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1006097469 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.1709735211 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 70866782 ps |
| CPU time | 6.88 seconds |
| Started | Jan 21 10:42:24 PM PST 24 |
| Finished | Jan 21 10:42:32 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-ddcdb797-b722-4522-ba24-eeea3f3b5362 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1709735211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1709735211 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.1826764782 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 143476948 ps |
| CPU time | 25.26 seconds |
| Started | Jan 21 10:42:16 PM PST 24 |
| Finished | Jan 21 10:42:43 PM PST 24 |
| Peak memory | 204760 kb |
| Host | smart-e7433611-1307-43b8-bbca-b18f96468f1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1826764782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1826764782 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2110059696 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 45617760488 ps |
| CPU time | 234.36 seconds |
| Started | Jan 21 10:42:16 PM PST 24 |
| Finished | Jan 21 10:46:12 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-6f6bbcd1-7bcb-4f66-98cf-927de23bde97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110059696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2110059696 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.73057431 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 9678361757 ps |
| CPU time | 88.91 seconds |
| Started | Jan 21 10:52:21 PM PST 24 |
| Finished | Jan 21 10:53:53 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-d3a0b395-a8ac-4825-863a-2b15ec688ea5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=73057431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.73057431 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.2673652764 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 35300143 ps |
| CPU time | 5.14 seconds |
| Started | Jan 21 11:18:20 PM PST 24 |
| Finished | Jan 21 11:18:26 PM PST 24 |
| Peak memory | 203528 kb |
| Host | smart-724a03ff-425c-4712-9364-c7eedce727de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673652764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.2673652764 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.1133994521 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2201369506 ps |
| CPU time | 31.68 seconds |
| Started | Jan 21 10:42:24 PM PST 24 |
| Finished | Jan 21 10:42:57 PM PST 24 |
| Peak memory | 204000 kb |
| Host | smart-c7b402d5-5190-4957-b94e-1da62706b5c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1133994521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1133994521 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.3981455440 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 130693328 ps |
| CPU time | 3.45 seconds |
| Started | Jan 21 11:06:50 PM PST 24 |
| Finished | Jan 21 11:06:57 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-233f47e4-ada6-4b97-a253-28d394a94138 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3981455440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3981455440 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1011644310 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 7307011079 ps |
| CPU time | 24.99 seconds |
| Started | Jan 21 10:42:06 PM PST 24 |
| Finished | Jan 21 10:42:32 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-a5386de1-fcc6-4741-94ff-19660987bd59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011644310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1011644310 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.463029948 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 10951723013 ps |
| CPU time | 39.56 seconds |
| Started | Jan 21 11:03:00 PM PST 24 |
| Finished | Jan 21 11:03:49 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-8b1bdb1e-16a0-4bbe-b639-729e212e3314 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=463029948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.463029948 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1147157732 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 45173442 ps |
| CPU time | 2.75 seconds |
| Started | Jan 21 10:42:12 PM PST 24 |
| Finished | Jan 21 10:42:17 PM PST 24 |
| Peak memory | 202816 kb |
| Host | smart-a3099496-eda1-4e93-859f-dd16187ad2c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147157732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1147157732 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.2619401621 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 525173481 ps |
| CPU time | 10.6 seconds |
| Started | Jan 21 10:42:31 PM PST 24 |
| Finished | Jan 21 10:42:44 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-e998fc6c-89f2-4b6a-bdc4-9698e5304152 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2619401621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2619401621 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2100918449 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 18089297161 ps |
| CPU time | 241.1 seconds |
| Started | Jan 21 10:42:25 PM PST 24 |
| Finished | Jan 21 10:46:27 PM PST 24 |
| Peak memory | 211452 kb |
| Host | smart-a52cfa62-d83e-401e-bf18-d533c5fb61d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2100918449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2100918449 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.3046034159 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 403541982 ps |
| CPU time | 198.11 seconds |
| Started | Jan 21 10:42:24 PM PST 24 |
| Finished | Jan 21 10:45:43 PM PST 24 |
| Peak memory | 208048 kb |
| Host | smart-2467a6c1-33b9-487b-9b61-cf95a810308a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3046034159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.3046034159 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.70203520 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 235989445 ps |
| CPU time | 63.99 seconds |
| Started | Jan 21 10:42:27 PM PST 24 |
| Finished | Jan 21 10:43:33 PM PST 24 |
| Peak memory | 207984 kb |
| Host | smart-666448fd-238b-4334-a885-6151fc173603 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=70203520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rese t_error.70203520 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1270608326 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 948822729 ps |
| CPU time | 32.89 seconds |
| Started | Jan 21 10:42:23 PM PST 24 |
| Finished | Jan 21 10:42:57 PM PST 24 |
| Peak memory | 204804 kb |
| Host | smart-83571652-c82b-4e59-bf27-2b7587644244 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1270608326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1270608326 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2006097692 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 543445326 ps |
| CPU time | 30.54 seconds |
| Started | Jan 21 10:42:32 PM PST 24 |
| Finished | Jan 21 10:43:04 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-c3a60d1a-c005-4e04-8f1e-508611e62795 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2006097692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2006097692 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3775227259 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 6609042209 ps |
| CPU time | 62.05 seconds |
| Started | Jan 21 10:42:33 PM PST 24 |
| Finished | Jan 21 10:43:37 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-691fe746-f99b-456b-aeee-0d6f45a370f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3775227259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.3775227259 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2658669979 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 71800368 ps |
| CPU time | 8.36 seconds |
| Started | Jan 21 11:28:05 PM PST 24 |
| Finished | Jan 21 11:28:19 PM PST 24 |
| Peak memory | 203568 kb |
| Host | smart-f1494dc1-8ee5-4d46-a185-f377887bcb76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2658669979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2658669979 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2713214075 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 143660847 ps |
| CPU time | 13.34 seconds |
| Started | Jan 21 10:42:32 PM PST 24 |
| Finished | Jan 21 10:42:47 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-5bd2aff0-b9fd-4503-ba37-45bd9d72af8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2713214075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2713214075 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.2703577431 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 959924393 ps |
| CPU time | 32.86 seconds |
| Started | Jan 21 10:42:27 PM PST 24 |
| Finished | Jan 21 10:43:02 PM PST 24 |
| Peak memory | 211568 kb |
| Host | smart-bdea3a6c-4bcd-4a58-a9c0-afcec4884e46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2703577431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2703577431 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1469394917 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 32787242111 ps |
| CPU time | 156.07 seconds |
| Started | Jan 21 11:21:40 PM PST 24 |
| Finished | Jan 21 11:24:26 PM PST 24 |
| Peak memory | 204844 kb |
| Host | smart-8a02f3c4-f30c-4ff4-8ec1-5dfd68d8018f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469394917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1469394917 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1381239703 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 22021171974 ps |
| CPU time | 102.78 seconds |
| Started | Jan 21 10:42:33 PM PST 24 |
| Finished | Jan 21 10:44:18 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-a8716ede-8a23-49ca-8b11-55dfc037fd64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1381239703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1381239703 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.4159713833 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 298075912 ps |
| CPU time | 18.57 seconds |
| Started | Jan 21 10:42:27 PM PST 24 |
| Finished | Jan 21 10:42:47 PM PST 24 |
| Peak memory | 211532 kb |
| Host | smart-44198065-10a3-4c08-8a7d-076b8ffb306a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159713833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.4159713833 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.1468395299 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 1905814376 ps |
| CPU time | 21.6 seconds |
| Started | Jan 21 10:42:31 PM PST 24 |
| Finished | Jan 21 10:42:55 PM PST 24 |
| Peak memory | 203780 kb |
| Host | smart-5a41b482-6f41-4924-8509-191183108f35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1468395299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1468395299 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.310432574 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 33676694 ps |
| CPU time | 2.41 seconds |
| Started | Jan 21 10:42:27 PM PST 24 |
| Finished | Jan 21 10:42:31 PM PST 24 |
| Peak memory | 203332 kb |
| Host | smart-3cdde22d-bfb5-4df2-92d7-eccf28b193dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=310432574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.310432574 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3411842122 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 26904892468 ps |
| CPU time | 36.03 seconds |
| Started | Jan 21 11:15:19 PM PST 24 |
| Finished | Jan 21 11:15:56 PM PST 24 |
| Peak memory | 203544 kb |
| Host | smart-77f4c074-7220-4b22-836e-61969273e6df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411842122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3411842122 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.3211588560 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 9446022450 ps |
| CPU time | 32.44 seconds |
| Started | Jan 21 10:42:26 PM PST 24 |
| Finished | Jan 21 10:42:59 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-b33847f2-c814-4763-81af-47efc3ecb311 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3211588560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3211588560 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.433133325 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 76392852 ps |
| CPU time | 2.31 seconds |
| Started | Jan 21 10:42:27 PM PST 24 |
| Finished | Jan 21 10:42:31 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-c4e1c153-dedb-40e3-91e9-41c2848446fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433133325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.433133325 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2475587782 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 7994908293 ps |
| CPU time | 201.04 seconds |
| Started | Jan 21 10:42:40 PM PST 24 |
| Finished | Jan 21 10:46:07 PM PST 24 |
| Peak memory | 210524 kb |
| Host | smart-6f9fb292-2292-4e53-b033-337468137cf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2475587782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2475587782 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.2017270472 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4236602605 ps |
| CPU time | 57.75 seconds |
| Started | Jan 21 11:24:45 PM PST 24 |
| Finished | Jan 21 11:25:44 PM PST 24 |
| Peak memory | 206048 kb |
| Host | smart-7b6d6fe3-f005-4b61-91b9-42959f07a0bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2017270472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2017270472 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.178432316 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 661057838 ps |
| CPU time | 224.44 seconds |
| Started | Jan 21 10:42:40 PM PST 24 |
| Finished | Jan 21 10:46:29 PM PST 24 |
| Peak memory | 208208 kb |
| Host | smart-403b0f36-2604-4f77-adc3-722f0d2d02f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=178432316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand _reset.178432316 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2210520190 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 76984503 ps |
| CPU time | 9.85 seconds |
| Started | Jan 21 10:42:40 PM PST 24 |
| Finished | Jan 21 10:42:55 PM PST 24 |
| Peak memory | 204500 kb |
| Host | smart-809643cc-0c4e-4c92-bdb0-5f5fce044e03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2210520190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.2210520190 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3284247268 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 239056373 ps |
| CPU time | 21.38 seconds |
| Started | Jan 21 10:42:32 PM PST 24 |
| Finished | Jan 21 10:42:55 PM PST 24 |
| Peak memory | 211548 kb |
| Host | smart-10c40e2c-3d20-4682-98ab-ca7aa133ae63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3284247268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3284247268 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3708468360 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 287680785 ps |
| CPU time | 20.36 seconds |
| Started | Jan 21 10:43:01 PM PST 24 |
| Finished | Jan 21 10:43:23 PM PST 24 |
| Peak memory | 204796 kb |
| Host | smart-526b0817-99bd-4f03-9e1a-1663f25f4724 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3708468360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3708468360 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3304681908 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 55986662148 ps |
| CPU time | 453.71 seconds |
| Started | Jan 21 10:42:54 PM PST 24 |
| Finished | Jan 21 10:50:30 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-4679fa2f-0311-422c-9e46-a6d8066e30d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3304681908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3304681908 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.167360186 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1053403268 ps |
| CPU time | 24.28 seconds |
| Started | Jan 21 10:42:59 PM PST 24 |
| Finished | Jan 21 10:43:24 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-c461ff5d-06f2-416a-87ca-ec27fa9f6327 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=167360186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.167360186 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.3784402783 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 279006173 ps |
| CPU time | 11.33 seconds |
| Started | Jan 21 10:42:54 PM PST 24 |
| Finished | Jan 21 10:43:08 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-c19684b8-2023-4aa0-9376-e189c8d67150 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3784402783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3784402783 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.1942439866 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 238414205 ps |
| CPU time | 24.79 seconds |
| Started | Jan 21 10:42:53 PM PST 24 |
| Finished | Jan 21 10:43:20 PM PST 24 |
| Peak memory | 204216 kb |
| Host | smart-9bc98b9d-46b8-41fb-8cd1-96fc5671fd4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1942439866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.1942439866 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2838938170 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 21957988335 ps |
| CPU time | 64.2 seconds |
| Started | Jan 21 10:42:49 PM PST 24 |
| Finished | Jan 21 10:43:58 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-923cb393-f96c-4b16-8d5c-a8ebcaa7c65b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838938170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2838938170 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.3354493874 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 41775284479 ps |
| CPU time | 164.22 seconds |
| Started | Jan 21 10:42:54 PM PST 24 |
| Finished | Jan 21 10:45:40 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-10575de5-2e5b-4e9b-a48a-838dfdf28ff0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3354493874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3354493874 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.1344591199 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 659310510 ps |
| CPU time | 18.85 seconds |
| Started | Jan 21 10:42:48 PM PST 24 |
| Finished | Jan 21 10:43:13 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-78ad6daa-41a9-4358-8c36-75c6eb7527bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344591199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1344591199 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.577392492 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2921768660 ps |
| CPU time | 14.05 seconds |
| Started | Jan 21 11:00:48 PM PST 24 |
| Finished | Jan 21 11:01:04 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-7c898886-cba8-4709-a620-c4753c7887ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=577392492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.577392492 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.2801699239 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 147020532 ps |
| CPU time | 3.47 seconds |
| Started | Jan 21 10:42:40 PM PST 24 |
| Finished | Jan 21 10:42:49 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-282fda70-a180-43ad-837b-ea07e354b670 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2801699239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2801699239 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.1336604097 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 11151873224 ps |
| CPU time | 34.52 seconds |
| Started | Jan 21 10:42:52 PM PST 24 |
| Finished | Jan 21 10:43:30 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-09689800-2046-45f5-814e-81c28cb2dca0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336604097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1336604097 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.321057965 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 6924250771 ps |
| CPU time | 26.39 seconds |
| Started | Jan 21 11:12:14 PM PST 24 |
| Finished | Jan 21 11:12:41 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-445c4e5a-3269-4d92-bf4c-ba8aed4f869e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=321057965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.321057965 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.895784589 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 31517456 ps |
| CPU time | 2.34 seconds |
| Started | Jan 21 10:42:39 PM PST 24 |
| Finished | Jan 21 10:42:45 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-c9042196-1646-4352-8de0-87065c437b1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895784589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.895784589 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.2866696571 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 9892088596 ps |
| CPU time | 295.05 seconds |
| Started | Jan 21 10:43:02 PM PST 24 |
| Finished | Jan 21 10:47:58 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-7ba4ba79-02c9-45ae-af42-10c2f4876629 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2866696571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2866696571 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.4273905522 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 12495657815 ps |
| CPU time | 177.92 seconds |
| Started | Jan 21 10:43:00 PM PST 24 |
| Finished | Jan 21 10:46:00 PM PST 24 |
| Peak memory | 209800 kb |
| Host | smart-18e53869-a1d6-473f-98e4-c8fbacd8b100 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4273905522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.4273905522 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1777202100 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 626011720 ps |
| CPU time | 182.24 seconds |
| Started | Jan 21 10:43:01 PM PST 24 |
| Finished | Jan 21 10:46:05 PM PST 24 |
| Peak memory | 209204 kb |
| Host | smart-30942e91-2ad1-42ca-93c6-cfeaf40bf959 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1777202100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.1777202100 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3231326111 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1455986613 ps |
| CPU time | 232.74 seconds |
| Started | Jan 21 10:42:59 PM PST 24 |
| Finished | Jan 21 10:46:53 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-f5fc3305-e9d5-4f7e-b39d-9dff17b2351c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3231326111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.3231326111 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.398931251 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 494352671 ps |
| CPU time | 15.02 seconds |
| Started | Jan 21 11:21:41 PM PST 24 |
| Finished | Jan 21 11:22:06 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-20c03faf-668c-4d1e-9755-5f16a04df333 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=398931251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.398931251 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.1238807281 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 545655683 ps |
| CPU time | 26.08 seconds |
| Started | Jan 21 10:32:37 PM PST 24 |
| Finished | Jan 21 10:33:04 PM PST 24 |
| Peak memory | 205864 kb |
| Host | smart-cd5d05a4-7a2b-482f-81b8-ce74a0f94998 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1238807281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1238807281 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.495745193 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 101255321588 ps |
| CPU time | 396.54 seconds |
| Started | Jan 21 10:32:49 PM PST 24 |
| Finished | Jan 21 10:39:31 PM PST 24 |
| Peak memory | 206536 kb |
| Host | smart-10768c60-f7e8-4fd5-addb-f114cf91edc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=495745193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow _rsp.495745193 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1317333391 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 128277289 ps |
| CPU time | 14.21 seconds |
| Started | Jan 21 10:32:53 PM PST 24 |
| Finished | Jan 21 10:33:13 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-81d642f9-2248-4e2f-8c20-62054fa1518a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1317333391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1317333391 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.2172118208 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1554057462 ps |
| CPU time | 29.32 seconds |
| Started | Jan 21 10:32:50 PM PST 24 |
| Finished | Jan 21 10:33:26 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-aa7262c4-8139-4db8-8b1c-662b9d35ae4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2172118208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2172118208 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.3088375525 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 400039977 ps |
| CPU time | 14.83 seconds |
| Started | Jan 21 10:32:35 PM PST 24 |
| Finished | Jan 21 10:32:51 PM PST 24 |
| Peak memory | 211580 kb |
| Host | smart-9385451f-b5d8-4804-aff6-dd62353716cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3088375525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3088375525 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1291702177 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 30840148071 ps |
| CPU time | 119.24 seconds |
| Started | Jan 21 10:32:33 PM PST 24 |
| Finished | Jan 21 10:34:35 PM PST 24 |
| Peak memory | 204808 kb |
| Host | smart-a08c153b-24bf-48ba-b38f-e1362c022fbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291702177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1291702177 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3101343778 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 54044055450 ps |
| CPU time | 191.12 seconds |
| Started | Jan 21 10:32:35 PM PST 24 |
| Finished | Jan 21 10:35:47 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-14ad4f94-9b58-4347-8dfc-e0b1eb6293fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3101343778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3101343778 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.4252621542 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 146742527 ps |
| CPU time | 23.84 seconds |
| Started | Jan 21 10:32:34 PM PST 24 |
| Finished | Jan 21 10:33:00 PM PST 24 |
| Peak memory | 211572 kb |
| Host | smart-6a86f221-e80c-45ab-9c20-cbcd7ac01057 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252621542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.4252621542 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.2781670334 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1040901317 ps |
| CPU time | 20.1 seconds |
| Started | Jan 21 10:32:41 PM PST 24 |
| Finished | Jan 21 10:33:04 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-95cb0969-f9c0-4b10-9dff-34741878bd59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2781670334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2781670334 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.124124141 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 64238997 ps |
| CPU time | 2.39 seconds |
| Started | Jan 21 10:32:29 PM PST 24 |
| Finished | Jan 21 10:32:34 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-c64417eb-f987-4d17-9ec6-55bb72af2173 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=124124141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.124124141 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1791492174 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10395007209 ps |
| CPU time | 35.35 seconds |
| Started | Jan 21 10:32:36 PM PST 24 |
| Finished | Jan 21 10:33:13 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-cd69dc82-dfca-4f4f-9e05-cbb212e1b930 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791492174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1791492174 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.615280025 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 14096617112 ps |
| CPU time | 28.73 seconds |
| Started | Jan 21 10:32:33 PM PST 24 |
| Finished | Jan 21 10:33:04 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-577b5cb3-065b-4f07-bf98-bfa4f17165d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=615280025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.615280025 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.8512671 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 107445738 ps |
| CPU time | 2.75 seconds |
| Started | Jan 21 10:32:30 PM PST 24 |
| Finished | Jan 21 10:32:35 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-1afa7a95-3707-430a-8ad7-337c29bc1c9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8512671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.8512671 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.388296856 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 271642220 ps |
| CPU time | 11.01 seconds |
| Started | Jan 21 10:32:50 PM PST 24 |
| Finished | Jan 21 10:33:08 PM PST 24 |
| Peak memory | 211560 kb |
| Host | smart-52599c19-c11c-4ae4-8cfd-0f939638e347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=388296856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.388296856 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.286709463 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 22593989351 ps |
| CPU time | 248.98 seconds |
| Started | Jan 21 10:32:57 PM PST 24 |
| Finished | Jan 21 10:37:11 PM PST 24 |
| Peak memory | 209024 kb |
| Host | smart-e09c315a-f8a5-4e36-b320-1a77d9b7da2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=286709463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.286709463 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1774993750 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 67481408 ps |
| CPU time | 48.91 seconds |
| Started | Jan 21 10:57:56 PM PST 24 |
| Finished | Jan 21 10:58:49 PM PST 24 |
| Peak memory | 207044 kb |
| Host | smart-0e581c91-1bd0-49f1-8865-99ddb3e74250 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1774993750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.1774993750 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2590679824 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 286804975 ps |
| CPU time | 21.47 seconds |
| Started | Jan 21 10:32:42 PM PST 24 |
| Finished | Jan 21 10:33:09 PM PST 24 |
| Peak memory | 204504 kb |
| Host | smart-82d83838-8fd9-454d-9015-611decfe6d92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2590679824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2590679824 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.1697043108 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1154510368 ps |
| CPU time | 9.56 seconds |
| Started | Jan 21 10:43:03 PM PST 24 |
| Finished | Jan 21 10:43:14 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-dde6dfc0-3dd9-4c5d-a62f-17f8bde5644b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1697043108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1697043108 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3228228390 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 102465388152 ps |
| CPU time | 644.4 seconds |
| Started | Jan 21 10:43:04 PM PST 24 |
| Finished | Jan 21 10:53:50 PM PST 24 |
| Peak memory | 207284 kb |
| Host | smart-a674ea6b-7ea0-4906-a520-fcf24ae05b80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3228228390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.3228228390 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1135897512 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 158930012 ps |
| CPU time | 7.11 seconds |
| Started | Jan 21 10:43:09 PM PST 24 |
| Finished | Jan 21 10:43:18 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-f8e7885d-fd37-42e6-b804-daac40fb7821 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1135897512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1135897512 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.216024486 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 104568494 ps |
| CPU time | 6.52 seconds |
| Started | Jan 21 10:43:14 PM PST 24 |
| Finished | Jan 21 10:43:22 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-c667b252-8302-495d-9cf6-9217750e159c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=216024486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.216024486 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.2434088219 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1412831532 ps |
| CPU time | 41.45 seconds |
| Started | Jan 21 10:43:05 PM PST 24 |
| Finished | Jan 21 10:43:48 PM PST 24 |
| Peak memory | 205072 kb |
| Host | smart-a9711d84-db41-48d5-991f-6414efa65bd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2434088219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2434088219 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.251858660 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 85181535575 ps |
| CPU time | 195.18 seconds |
| Started | Jan 21 10:43:04 PM PST 24 |
| Finished | Jan 21 10:46:20 PM PST 24 |
| Peak memory | 204984 kb |
| Host | smart-91ed63bd-6892-410f-a4a8-4762ffb79f20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=251858660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.251858660 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2123798469 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 27177130425 ps |
| CPU time | 234.26 seconds |
| Started | Jan 21 10:43:04 PM PST 24 |
| Finished | Jan 21 10:46:59 PM PST 24 |
| Peak memory | 205044 kb |
| Host | smart-823832d5-35b0-415f-96d0-37a099b509aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2123798469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2123798469 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.462837464 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 113803211 ps |
| CPU time | 16.7 seconds |
| Started | Jan 21 10:43:04 PM PST 24 |
| Finished | Jan 21 10:43:22 PM PST 24 |
| Peak memory | 211592 kb |
| Host | smart-809fc082-8de2-4f6a-be80-8a0a27a483d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462837464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.462837464 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.2200694735 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1647675109 ps |
| CPU time | 25.09 seconds |
| Started | Jan 21 10:43:15 PM PST 24 |
| Finished | Jan 21 10:43:42 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-183c1aa6-d9f6-4dd2-b015-7a25fa6ec9b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2200694735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2200694735 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.1784736870 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 131216458 ps |
| CPU time | 3.57 seconds |
| Started | Jan 21 10:43:00 PM PST 24 |
| Finished | Jan 21 10:43:06 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-167c281d-dd69-4967-b6d5-126649f51aa1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1784736870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1784736870 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2129800493 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 6603772813 ps |
| CPU time | 35.24 seconds |
| Started | Jan 21 10:43:00 PM PST 24 |
| Finished | Jan 21 10:43:38 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-3c1da733-7f28-4f48-b338-059552f0df8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129800493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2129800493 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3119448177 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 10866642816 ps |
| CPU time | 40.47 seconds |
| Started | Jan 21 10:43:06 PM PST 24 |
| Finished | Jan 21 10:43:48 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-348b0c77-4658-4431-94f5-e9c5544af064 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3119448177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3119448177 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.776031098 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 27672737 ps |
| CPU time | 2.57 seconds |
| Started | Jan 21 10:43:01 PM PST 24 |
| Finished | Jan 21 10:43:05 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-a33ba3c2-cb55-4493-810d-bf9936a7e89a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776031098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.776031098 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3528751214 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 8169385758 ps |
| CPU time | 198.25 seconds |
| Started | Jan 21 10:43:11 PM PST 24 |
| Finished | Jan 21 10:46:30 PM PST 24 |
| Peak memory | 208176 kb |
| Host | smart-8926e2ec-d44d-438a-85de-70f329724923 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3528751214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3528751214 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2473465681 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 3786381103 ps |
| CPU time | 116.69 seconds |
| Started | Jan 21 10:43:11 PM PST 24 |
| Finished | Jan 21 10:45:08 PM PST 24 |
| Peak memory | 207364 kb |
| Host | smart-b7d91669-10e0-4211-a10e-839e2b4f9ecd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2473465681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2473465681 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2062682645 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 110159731 ps |
| CPU time | 72.01 seconds |
| Started | Jan 21 10:43:14 PM PST 24 |
| Finished | Jan 21 10:44:29 PM PST 24 |
| Peak memory | 207736 kb |
| Host | smart-674c5a2e-6ea8-4473-a4c4-b23db0cbeacf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2062682645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.2062682645 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.711137037 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 254513361 ps |
| CPU time | 58.91 seconds |
| Started | Jan 21 10:43:12 PM PST 24 |
| Finished | Jan 21 10:44:12 PM PST 24 |
| Peak memory | 207748 kb |
| Host | smart-56415c1e-0ae7-4fe8-95f2-6beacf6768f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=711137037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res et_error.711137037 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1244878059 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 134189321 ps |
| CPU time | 5.61 seconds |
| Started | Jan 21 10:43:12 PM PST 24 |
| Finished | Jan 21 10:43:18 PM PST 24 |
| Peak memory | 204608 kb |
| Host | smart-cfa10e46-0115-452d-841c-7a1f38bee6f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1244878059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1244878059 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.748655631 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3408655205 ps |
| CPU time | 51.49 seconds |
| Started | Jan 21 10:43:17 PM PST 24 |
| Finished | Jan 21 10:44:10 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-8679f3d2-58a4-4521-83d4-392dc8d86971 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=748655631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.748655631 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3018966010 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 63379686334 ps |
| CPU time | 443.43 seconds |
| Started | Jan 21 10:43:17 PM PST 24 |
| Finished | Jan 21 10:50:42 PM PST 24 |
| Peak memory | 206988 kb |
| Host | smart-76d51a89-0756-4dc3-a924-d3b810bc89a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3018966010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.3018966010 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2570083921 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2221759925 ps |
| CPU time | 21.88 seconds |
| Started | Jan 21 10:43:29 PM PST 24 |
| Finished | Jan 21 10:43:53 PM PST 24 |
| Peak memory | 203584 kb |
| Host | smart-8f147f97-4f2b-4cc2-86cb-36f1a51f4896 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2570083921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2570083921 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.1686887001 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 452868287 ps |
| CPU time | 6.23 seconds |
| Started | Jan 21 10:43:26 PM PST 24 |
| Finished | Jan 21 10:43:33 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-b4f7ec8a-948e-40d1-991c-f2618bb9f2f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1686887001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1686887001 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.1759448258 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 89006616 ps |
| CPU time | 14.53 seconds |
| Started | Jan 21 10:43:17 PM PST 24 |
| Finished | Jan 21 10:43:33 PM PST 24 |
| Peak memory | 211596 kb |
| Host | smart-c28d2c92-44fa-433c-ab4c-ed15f322eb9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1759448258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1759448258 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.268947690 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 38126634937 ps |
| CPU time | 185.91 seconds |
| Started | Jan 21 10:43:18 PM PST 24 |
| Finished | Jan 21 10:46:25 PM PST 24 |
| Peak memory | 205052 kb |
| Host | smart-73de37d9-2726-4388-8c82-c683530f965c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=268947690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.268947690 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1559308352 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 31238829195 ps |
| CPU time | 178.24 seconds |
| Started | Jan 21 10:43:16 PM PST 24 |
| Finished | Jan 21 10:46:16 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-fb73c037-f0aa-460e-9b0c-6afba59df3dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1559308352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1559308352 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1782628387 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 20382955 ps |
| CPU time | 2.35 seconds |
| Started | Jan 21 10:43:20 PM PST 24 |
| Finished | Jan 21 10:43:23 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-43eaae67-a480-44ed-8e65-a5442676a735 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782628387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1782628387 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.3981754294 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 87614031 ps |
| CPU time | 6.7 seconds |
| Started | Jan 21 10:43:19 PM PST 24 |
| Finished | Jan 21 10:43:27 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-0366a544-f3fe-4c06-a554-227ac52a4fea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3981754294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3981754294 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.3684582835 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 140776265 ps |
| CPU time | 4.13 seconds |
| Started | Jan 21 10:43:19 PM PST 24 |
| Finished | Jan 21 10:43:24 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-ca08a7c7-9808-457a-ba0c-4e0062df068e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3684582835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3684582835 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.4217938486 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 9777422526 ps |
| CPU time | 29.8 seconds |
| Started | Jan 21 10:43:19 PM PST 24 |
| Finished | Jan 21 10:43:50 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-2e3272de-a766-4829-a1f6-0e5111f8441f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217938486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.4217938486 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2860068214 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4232906014 ps |
| CPU time | 24.29 seconds |
| Started | Jan 21 10:43:19 PM PST 24 |
| Finished | Jan 21 10:43:44 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-f549ef5b-7ddc-4db4-aba1-d47d839be882 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2860068214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2860068214 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.4133285916 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 146131802 ps |
| CPU time | 2.52 seconds |
| Started | Jan 21 10:43:17 PM PST 24 |
| Finished | Jan 21 10:43:21 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-d68f5f39-14f6-4fe2-92ad-78b22a161434 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133285916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.4133285916 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1484764381 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 26202279623 ps |
| CPU time | 221.18 seconds |
| Started | Jan 21 10:43:38 PM PST 24 |
| Finished | Jan 21 10:47:20 PM PST 24 |
| Peak memory | 208188 kb |
| Host | smart-612ed67f-0016-4577-946f-3905acc69857 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1484764381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1484764381 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1711176636 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 25565803242 ps |
| CPU time | 670.85 seconds |
| Started | Jan 21 10:43:35 PM PST 24 |
| Finished | Jan 21 10:54:47 PM PST 24 |
| Peak memory | 221588 kb |
| Host | smart-af2d17fe-6368-4225-9abf-c9bc16800481 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1711176636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.1711176636 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.434480348 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 67868308 ps |
| CPU time | 14.14 seconds |
| Started | Jan 21 10:43:33 PM PST 24 |
| Finished | Jan 21 10:43:48 PM PST 24 |
| Peak memory | 205280 kb |
| Host | smart-09c58797-fa47-4a70-b961-1be9a2a3123b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=434480348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res et_error.434480348 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2830592097 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 141790463 ps |
| CPU time | 13.91 seconds |
| Started | Jan 21 10:43:27 PM PST 24 |
| Finished | Jan 21 10:43:42 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-3f744764-2ca4-498c-9926-2ceaf23c8557 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2830592097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2830592097 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.239375278 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 163860312 ps |
| CPU time | 18.9 seconds |
| Started | Jan 21 10:43:35 PM PST 24 |
| Finished | Jan 21 10:43:55 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-68b6cee3-faa6-4d42-a64e-8f5879d402bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=239375278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.239375278 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.798402936 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 74846650553 ps |
| CPU time | 358.94 seconds |
| Started | Jan 21 10:43:34 PM PST 24 |
| Finished | Jan 21 10:49:34 PM PST 24 |
| Peak memory | 211720 kb |
| Host | smart-fa5b8344-dac7-47e1-a0ec-af6380979779 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=798402936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slo w_rsp.798402936 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3894248664 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 251222603 ps |
| CPU time | 2.45 seconds |
| Started | Jan 21 10:43:37 PM PST 24 |
| Finished | Jan 21 10:43:41 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-088edcda-42e4-4c81-b5d3-f63d29e3aed4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3894248664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3894248664 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.2610291342 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 496240775 ps |
| CPU time | 13.89 seconds |
| Started | Jan 21 10:43:38 PM PST 24 |
| Finished | Jan 21 10:43:53 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-c38dc611-1549-4f73-9991-c1d78497cb99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2610291342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2610291342 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.1087997558 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1148720520 ps |
| CPU time | 29.56 seconds |
| Started | Jan 21 10:43:36 PM PST 24 |
| Finished | Jan 21 10:44:07 PM PST 24 |
| Peak memory | 211596 kb |
| Host | smart-c85760b0-c849-46d2-a4f6-0f88f5dda8c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1087997558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1087997558 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1830877408 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 28172874945 ps |
| CPU time | 131.05 seconds |
| Started | Jan 21 10:43:33 PM PST 24 |
| Finished | Jan 21 10:45:45 PM PST 24 |
| Peak memory | 204684 kb |
| Host | smart-31cc32bb-4b19-4389-b1dc-14cf760d6447 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830877408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1830877408 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2723033151 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 29305881888 ps |
| CPU time | 67.48 seconds |
| Started | Jan 21 10:43:36 PM PST 24 |
| Finished | Jan 21 10:44:45 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-fff48708-ec09-40d0-a32c-6f870cea8d09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2723033151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2723033151 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.3115829084 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 436397798 ps |
| CPU time | 23.2 seconds |
| Started | Jan 21 10:43:35 PM PST 24 |
| Finished | Jan 21 10:43:59 PM PST 24 |
| Peak memory | 204744 kb |
| Host | smart-e47a53d7-49b8-44c1-b7ba-c7eeed243b1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115829084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3115829084 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.201750323 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1682206989 ps |
| CPU time | 31.23 seconds |
| Started | Jan 21 10:43:39 PM PST 24 |
| Finished | Jan 21 10:44:11 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-0e7079f7-9a43-4acb-9edf-47e8179ccebf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=201750323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.201750323 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.4200216554 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 126761840 ps |
| CPU time | 2.68 seconds |
| Started | Jan 21 10:43:36 PM PST 24 |
| Finished | Jan 21 10:43:40 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-3581e424-60f7-4d5f-a6ec-34adb6604aeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4200216554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.4200216554 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3861267671 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 19971315497 ps |
| CPU time | 31.42 seconds |
| Started | Jan 21 10:43:37 PM PST 24 |
| Finished | Jan 21 10:44:09 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-e61a9658-6935-477e-9ced-305028a258ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861267671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3861267671 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.681880592 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 5586478831 ps |
| CPU time | 33.53 seconds |
| Started | Jan 21 10:43:33 PM PST 24 |
| Finished | Jan 21 10:44:08 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-0f307bf5-7da4-4ae7-a625-9eba43a96f3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=681880592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.681880592 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.1587613756 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 42422619 ps |
| CPU time | 2.17 seconds |
| Started | Jan 21 10:43:34 PM PST 24 |
| Finished | Jan 21 10:43:37 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-1fd75e59-c978-4810-8f1a-463c7556d2f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587613756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.1587613756 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1649551235 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1935688689 ps |
| CPU time | 71.48 seconds |
| Started | Jan 21 10:43:45 PM PST 24 |
| Finished | Jan 21 10:45:00 PM PST 24 |
| Peak memory | 206024 kb |
| Host | smart-ee9142a2-19fe-4d5b-b1b3-557aab8285be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1649551235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1649551235 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3665766148 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 3437479447 ps |
| CPU time | 72.18 seconds |
| Started | Jan 21 10:43:44 PM PST 24 |
| Finished | Jan 21 10:45:00 PM PST 24 |
| Peak memory | 205888 kb |
| Host | smart-6f13e7ce-9d25-4600-9320-010c28545873 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3665766148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3665766148 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.373450068 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1022429171 ps |
| CPU time | 269.48 seconds |
| Started | Jan 21 10:43:44 PM PST 24 |
| Finished | Jan 21 10:48:17 PM PST 24 |
| Peak memory | 209668 kb |
| Host | smart-c6fc10f0-b528-4e4d-88a1-39e6cb0ae9ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=373450068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand _reset.373450068 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.3958308253 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 572180362 ps |
| CPU time | 113.88 seconds |
| Started | Jan 21 10:43:45 PM PST 24 |
| Finished | Jan 21 10:45:43 PM PST 24 |
| Peak memory | 209720 kb |
| Host | smart-e87365ae-32de-4790-8aaa-7912e8fa178a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3958308253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.3958308253 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1445729999 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 86477067 ps |
| CPU time | 13.35 seconds |
| Started | Jan 21 10:43:40 PM PST 24 |
| Finished | Jan 21 10:43:56 PM PST 24 |
| Peak memory | 204480 kb |
| Host | smart-65a49246-c67e-4e31-b8ff-39ede4cb941d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1445729999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1445729999 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1941462274 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 508158946 ps |
| CPU time | 30.63 seconds |
| Started | Jan 21 10:43:50 PM PST 24 |
| Finished | Jan 21 10:44:24 PM PST 24 |
| Peak memory | 203972 kb |
| Host | smart-7f46faf1-0ca4-40cc-9658-7afcefa433c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941462274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1941462274 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.4023068901 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 77625460938 ps |
| CPU time | 511.67 seconds |
| Started | Jan 21 10:43:52 PM PST 24 |
| Finished | Jan 21 10:52:25 PM PST 24 |
| Peak memory | 206920 kb |
| Host | smart-bc1a0e7b-c554-46a8-b676-bca2957297ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4023068901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.4023068901 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3289586244 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 122388721 ps |
| CPU time | 2.02 seconds |
| Started | Jan 21 10:43:55 PM PST 24 |
| Finished | Jan 21 10:43:58 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-448dfb48-456e-4bdc-b859-ef7a5cce9377 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3289586244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3289586244 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.1136136139 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3565114764 ps |
| CPU time | 24.12 seconds |
| Started | Jan 21 10:43:52 PM PST 24 |
| Finished | Jan 21 10:44:18 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-32d65bce-6ff0-4e55-834a-ca6ef405cd40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1136136139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1136136139 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.245038098 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2717655248 ps |
| CPU time | 31.97 seconds |
| Started | Jan 21 11:01:13 PM PST 24 |
| Finished | Jan 21 11:01:47 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-f87cde2a-3f2b-47b7-b126-6a51a74de1b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=245038098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.245038098 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.778199339 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 33599405013 ps |
| CPU time | 167.58 seconds |
| Started | Jan 21 10:43:52 PM PST 24 |
| Finished | Jan 21 10:46:42 PM PST 24 |
| Peak memory | 204728 kb |
| Host | smart-97c0a2f5-34ad-4320-83e9-1ec04f2ea26b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=778199339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.778199339 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3503951842 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 7131849338 ps |
| CPU time | 60.05 seconds |
| Started | Jan 21 10:43:50 PM PST 24 |
| Finished | Jan 21 10:44:53 PM PST 24 |
| Peak memory | 204584 kb |
| Host | smart-129f5e07-5565-4941-b4b5-f81a5cd90036 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3503951842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3503951842 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.3962661172 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 484722535 ps |
| CPU time | 24.84 seconds |
| Started | Jan 21 10:43:51 PM PST 24 |
| Finished | Jan 21 10:44:18 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-70d14d09-aa9e-4361-812d-a3be8236ce03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962661172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.3962661172 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.464444061 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1528748924 ps |
| CPU time | 14.76 seconds |
| Started | Jan 21 10:43:52 PM PST 24 |
| Finished | Jan 21 10:44:09 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-73e94f63-5281-4ea1-ac7a-ac73e460549c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=464444061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.464444061 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.2707223729 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 325642110 ps |
| CPU time | 3.37 seconds |
| Started | Jan 21 10:43:43 PM PST 24 |
| Finished | Jan 21 10:43:50 PM PST 24 |
| Peak memory | 203572 kb |
| Host | smart-7d308d5b-3d67-4969-b079-08577ae634dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2707223729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2707223729 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2911706719 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 33924391453 ps |
| CPU time | 45.76 seconds |
| Started | Jan 21 10:43:45 PM PST 24 |
| Finished | Jan 21 10:44:35 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-5221692b-16c5-4d68-b57a-0b142c7fc25a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911706719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2911706719 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2525129680 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 7380058556 ps |
| CPU time | 32.49 seconds |
| Started | Jan 21 11:43:37 PM PST 24 |
| Finished | Jan 21 11:44:10 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-e50f8361-f658-46bf-845d-a83136220c06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2525129680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2525129680 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1972798026 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 50974205 ps |
| CPU time | 2.2 seconds |
| Started | Jan 21 11:08:38 PM PST 24 |
| Finished | Jan 21 11:08:41 PM PST 24 |
| Peak memory | 203512 kb |
| Host | smart-a290ece5-adcc-4bc4-9ddf-537ca8333430 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972798026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1972798026 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.2808195125 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3732601862 ps |
| CPU time | 153.82 seconds |
| Started | Jan 21 10:43:55 PM PST 24 |
| Finished | Jan 21 10:46:30 PM PST 24 |
| Peak memory | 205748 kb |
| Host | smart-6fc30d28-046e-46b7-9abb-0cd9ad13c524 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2808195125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2808195125 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2070453612 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4063202339 ps |
| CPU time | 93.63 seconds |
| Started | Jan 21 10:43:57 PM PST 24 |
| Finished | Jan 21 10:45:32 PM PST 24 |
| Peak memory | 211644 kb |
| Host | smart-6078de40-6871-44f1-ad35-c7b99e821072 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2070453612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2070453612 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1108851526 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 69424558 ps |
| CPU time | 41.04 seconds |
| Started | Jan 21 10:44:07 PM PST 24 |
| Finished | Jan 21 10:44:49 PM PST 24 |
| Peak memory | 205636 kb |
| Host | smart-9450885d-995e-4089-9d18-55866bac2083 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1108851526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.1108851526 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2365345947 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 936042903 ps |
| CPU time | 14.68 seconds |
| Started | Jan 21 10:43:54 PM PST 24 |
| Finished | Jan 21 10:44:09 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-25d15090-3d68-49b2-981f-3219f236f7b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2365345947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2365345947 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.1210845045 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 747608415 ps |
| CPU time | 34.22 seconds |
| Started | Jan 21 10:44:19 PM PST 24 |
| Finished | Jan 21 10:44:56 PM PST 24 |
| Peak memory | 204368 kb |
| Host | smart-bfe9217a-ab6b-4fc5-aee4-481e0ba9c9f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1210845045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.1210845045 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1459190541 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 30319722358 ps |
| CPU time | 260.65 seconds |
| Started | Jan 21 10:44:16 PM PST 24 |
| Finished | Jan 21 10:48:37 PM PST 24 |
| Peak memory | 205736 kb |
| Host | smart-f27523e9-17b6-4672-8cf9-a0e0267ced98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1459190541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.1459190541 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.4055395234 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 511649301 ps |
| CPU time | 17.07 seconds |
| Started | Jan 21 10:44:13 PM PST 24 |
| Finished | Jan 21 10:44:31 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-6fbda90a-675d-40cb-b5ee-7e37819e2fea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4055395234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.4055395234 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.991481407 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 302968041 ps |
| CPU time | 23.37 seconds |
| Started | Jan 21 10:44:17 PM PST 24 |
| Finished | Jan 21 10:44:42 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-960050c7-f7a2-4e9f-a9c0-baea83227cdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=991481407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.991481407 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.2126570540 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 908252857 ps |
| CPU time | 36.43 seconds |
| Started | Jan 21 10:44:09 PM PST 24 |
| Finished | Jan 21 10:44:47 PM PST 24 |
| Peak memory | 204600 kb |
| Host | smart-9a0c164a-bac8-45cc-b3a2-b57dbfce15f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2126570540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2126570540 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2534255231 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 149209978544 ps |
| CPU time | 300.57 seconds |
| Started | Jan 21 10:44:03 PM PST 24 |
| Finished | Jan 21 10:49:05 PM PST 24 |
| Peak memory | 211720 kb |
| Host | smart-f759b734-744f-4921-bc0e-aa67f0b2facb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534255231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2534255231 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3276945276 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 62402849557 ps |
| CPU time | 197.43 seconds |
| Started | Jan 21 11:13:41 PM PST 24 |
| Finished | Jan 21 11:17:00 PM PST 24 |
| Peak memory | 211724 kb |
| Host | smart-1e9195d7-b017-4262-a2c6-d75f3a6868f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3276945276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3276945276 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.3387484623 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 43402716 ps |
| CPU time | 3.67 seconds |
| Started | Jan 21 10:44:10 PM PST 24 |
| Finished | Jan 21 10:44:15 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-3767946f-7b73-4688-83eb-ac7d210565f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387484623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3387484623 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.2187351388 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1185275563 ps |
| CPU time | 14.94 seconds |
| Started | Jan 21 10:44:16 PM PST 24 |
| Finished | Jan 21 10:44:32 PM PST 24 |
| Peak memory | 203792 kb |
| Host | smart-218e039d-0ca3-463c-b42a-710fb4c35412 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2187351388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2187351388 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.823837172 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 369659087 ps |
| CPU time | 3.87 seconds |
| Started | Jan 21 10:44:10 PM PST 24 |
| Finished | Jan 21 10:44:15 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-810c27a9-32f7-4c51-86c8-392280abc00a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=823837172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.823837172 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2578001760 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 24960553551 ps |
| CPU time | 41.56 seconds |
| Started | Jan 21 10:44:07 PM PST 24 |
| Finished | Jan 21 10:44:50 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-726e82eb-33f1-421e-8ac7-c1fa530f2870 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578001760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2578001760 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2224192742 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 6391676866 ps |
| CPU time | 21.94 seconds |
| Started | Jan 21 10:44:10 PM PST 24 |
| Finished | Jan 21 10:44:33 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-1f647d72-e22c-47f7-8c4f-392abf0193df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2224192742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2224192742 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1089114523 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 36269385 ps |
| CPU time | 2.55 seconds |
| Started | Jan 21 10:44:04 PM PST 24 |
| Finished | Jan 21 10:44:08 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-1304dbcd-e735-4e3e-952f-7269262ff122 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089114523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1089114523 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3605983784 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 4527684271 ps |
| CPU time | 145.04 seconds |
| Started | Jan 21 10:44:19 PM PST 24 |
| Finished | Jan 21 10:46:45 PM PST 24 |
| Peak memory | 207236 kb |
| Host | smart-005d1369-d96b-40f5-84f1-e7d4a39da820 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3605983784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3605983784 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3689310258 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2366660857 ps |
| CPU time | 95.67 seconds |
| Started | Jan 21 10:44:18 PM PST 24 |
| Finished | Jan 21 10:45:54 PM PST 24 |
| Peak memory | 206428 kb |
| Host | smart-ccd7cca9-8961-4c6d-be3f-8ee1870cca86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3689310258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3689310258 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3822963314 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 172240474 ps |
| CPU time | 40.41 seconds |
| Started | Jan 21 10:44:17 PM PST 24 |
| Finished | Jan 21 10:44:58 PM PST 24 |
| Peak memory | 207536 kb |
| Host | smart-4ee9bee4-8e9e-4715-ba67-293bb98c3c2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3822963314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.3822963314 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2845230297 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 24085931 ps |
| CPU time | 2.86 seconds |
| Started | Jan 21 10:44:19 PM PST 24 |
| Finished | Jan 21 10:44:23 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-5df03bbf-9721-4387-964e-5cfe44a91c0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2845230297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2845230297 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1905217861 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2839353405 ps |
| CPU time | 34.56 seconds |
| Started | Jan 21 10:44:18 PM PST 24 |
| Finished | Jan 21 10:44:55 PM PST 24 |
| Peak memory | 205880 kb |
| Host | smart-a3665608-98ce-45d9-a746-479cf0742c70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1905217861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1905217861 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2174394540 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 75215935851 ps |
| CPU time | 268.82 seconds |
| Started | Jan 21 11:09:27 PM PST 24 |
| Finished | Jan 21 11:13:57 PM PST 24 |
| Peak memory | 211728 kb |
| Host | smart-a0ec8167-0e4a-4a52-bfd7-c9d25333881e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2174394540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.2174394540 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1647775599 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 659144744 ps |
| CPU time | 19.37 seconds |
| Started | Jan 21 10:44:26 PM PST 24 |
| Finished | Jan 21 10:44:57 PM PST 24 |
| Peak memory | 203564 kb |
| Host | smart-1cbe5a94-677e-4ab9-92be-dbdf16807572 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1647775599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1647775599 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.732165735 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 341473344 ps |
| CPU time | 14.52 seconds |
| Started | Jan 21 10:44:22 PM PST 24 |
| Finished | Jan 21 10:44:43 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-0e2eff20-a583-449b-b7f4-6f41a2284e48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=732165735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.732165735 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.576639980 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 178022036 ps |
| CPU time | 7.17 seconds |
| Started | Jan 21 10:44:19 PM PST 24 |
| Finished | Jan 21 10:44:28 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-5190821c-700e-4db3-a6e1-efa20af0a059 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=576639980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.576639980 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.340390786 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 22856750458 ps |
| CPU time | 40.57 seconds |
| Started | Jan 21 11:16:37 PM PST 24 |
| Finished | Jan 21 11:17:21 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-8b01b263-9b48-4b20-b848-bca559b95e94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=340390786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.340390786 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.430898980 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 11506379639 ps |
| CPU time | 36.65 seconds |
| Started | Jan 21 10:44:19 PM PST 24 |
| Finished | Jan 21 10:44:58 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-0c8772a0-62be-4240-8302-ac695cbcc1c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=430898980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.430898980 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2518588333 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 502718139 ps |
| CPU time | 25.54 seconds |
| Started | Jan 21 11:15:22 PM PST 24 |
| Finished | Jan 21 11:15:49 PM PST 24 |
| Peak memory | 211708 kb |
| Host | smart-381b5071-44e2-4bff-b8f4-24ef1a3a1dd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518588333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2518588333 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.1450561137 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 49382353 ps |
| CPU time | 3.52 seconds |
| Started | Jan 21 11:19:47 PM PST 24 |
| Finished | Jan 21 11:19:55 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-dcaa90d2-b28f-40d7-a7f9-f4caafc11878 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1450561137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1450561137 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.3684093647 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 320467592 ps |
| CPU time | 4.48 seconds |
| Started | Jan 21 10:44:19 PM PST 24 |
| Finished | Jan 21 10:44:26 PM PST 24 |
| Peak memory | 203292 kb |
| Host | smart-8fd5329b-e507-4c97-9712-f8ee3bd654fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3684093647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3684093647 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.4077935866 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 8936165879 ps |
| CPU time | 38.11 seconds |
| Started | Jan 21 11:06:49 PM PST 24 |
| Finished | Jan 21 11:07:29 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-802ae04a-9fb9-4454-8a19-3125e099db95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077935866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.4077935866 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3375998276 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 6060900129 ps |
| CPU time | 35.95 seconds |
| Started | Jan 21 10:44:19 PM PST 24 |
| Finished | Jan 21 10:44:58 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-426c5cb4-46ae-488d-8034-7fbb8f00f5f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3375998276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3375998276 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1574062527 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 77366662 ps |
| CPU time | 2.34 seconds |
| Started | Jan 21 10:44:18 PM PST 24 |
| Finished | Jan 21 10:44:22 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-87f886e4-ffec-4ecc-8d52-c75394967b9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574062527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1574062527 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1330713441 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 546575757 ps |
| CPU time | 55.68 seconds |
| Started | Jan 21 10:44:29 PM PST 24 |
| Finished | Jan 21 10:45:36 PM PST 24 |
| Peak memory | 205416 kb |
| Host | smart-e0893cb9-a864-4c37-95ef-ade9ff6fa74b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1330713441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1330713441 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1323298073 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 6552898763 ps |
| CPU time | 145.14 seconds |
| Started | Jan 21 10:44:29 PM PST 24 |
| Finished | Jan 21 10:47:05 PM PST 24 |
| Peak memory | 208748 kb |
| Host | smart-7256b137-f790-484a-8d67-63e9e40aad2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1323298073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1323298073 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.992129100 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3405996574 ps |
| CPU time | 248.06 seconds |
| Started | Jan 21 10:44:27 PM PST 24 |
| Finished | Jan 21 10:48:46 PM PST 24 |
| Peak memory | 208008 kb |
| Host | smart-ebfad7c3-58bd-4f1d-bb91-89eacd448fae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=992129100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand _reset.992129100 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.316030611 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 130214676 ps |
| CPU time | 59.86 seconds |
| Started | Jan 21 10:44:36 PM PST 24 |
| Finished | Jan 21 10:45:45 PM PST 24 |
| Peak memory | 208036 kb |
| Host | smart-c10102fa-b910-4614-aa1d-1a4fa3f93724 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=316030611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_res et_error.316030611 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3157418789 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 820239598 ps |
| CPU time | 26.27 seconds |
| Started | Jan 21 10:44:21 PM PST 24 |
| Finished | Jan 21 10:44:50 PM PST 24 |
| Peak memory | 204524 kb |
| Host | smart-2b35735d-ea94-4acb-b0da-4930553433d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3157418789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3157418789 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3498511641 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 10177927098 ps |
| CPU time | 77.68 seconds |
| Started | Jan 21 10:44:44 PM PST 24 |
| Finished | Jan 21 10:46:06 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-61adb8e0-9147-41d1-8290-edaa65c2869a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3498511641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3498511641 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4235179207 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 113532518174 ps |
| CPU time | 550.57 seconds |
| Started | Jan 21 10:44:44 PM PST 24 |
| Finished | Jan 21 10:53:59 PM PST 24 |
| Peak memory | 211620 kb |
| Host | smart-9420bb8d-91e2-4e37-92cc-8fb5a2f0467e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4235179207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.4235179207 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1163940319 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 46662958 ps |
| CPU time | 5.81 seconds |
| Started | Jan 21 10:44:47 PM PST 24 |
| Finished | Jan 21 10:44:56 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-040143ff-6fab-41e8-bfbe-906ab2d1f45f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1163940319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1163940319 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.1583089521 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2020782595 ps |
| CPU time | 24.75 seconds |
| Started | Jan 21 10:44:41 PM PST 24 |
| Finished | Jan 21 10:45:12 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-176f9b4b-3516-4390-9429-917eacdc4b20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1583089521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1583089521 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.1306795348 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 50455665 ps |
| CPU time | 7.01 seconds |
| Started | Jan 21 10:44:35 PM PST 24 |
| Finished | Jan 21 10:44:50 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-5fd4e6e0-1845-4736-9ee8-131a184b52ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1306795348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1306795348 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.4008054092 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 17944600809 ps |
| CPU time | 106.08 seconds |
| Started | Jan 21 10:44:33 PM PST 24 |
| Finished | Jan 21 10:46:29 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-c87e722e-df79-46d1-92d3-42112d717a36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008054092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.4008054092 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2258910164 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 30091251050 ps |
| CPU time | 214.78 seconds |
| Started | Jan 21 10:44:41 PM PST 24 |
| Finished | Jan 21 10:48:22 PM PST 24 |
| Peak memory | 204836 kb |
| Host | smart-c1038e2d-79e2-45c2-8daa-3265b374dd3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2258910164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2258910164 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2717237271 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 189477170 ps |
| CPU time | 23.03 seconds |
| Started | Jan 21 10:44:36 PM PST 24 |
| Finished | Jan 21 10:45:08 PM PST 24 |
| Peak memory | 204556 kb |
| Host | smart-5e00f505-9be7-4d12-8e5b-1805819a9d2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717237271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2717237271 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.399931629 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1571736832 ps |
| CPU time | 22.64 seconds |
| Started | Jan 21 10:44:41 PM PST 24 |
| Finished | Jan 21 10:45:10 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-c80ca2b8-e83d-453d-85a8-c938b6d4c5c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=399931629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.399931629 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.2331490504 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 100234468 ps |
| CPU time | 3.34 seconds |
| Started | Jan 21 10:44:35 PM PST 24 |
| Finished | Jan 21 10:44:48 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-311b95f5-bfbc-4491-9c2a-e8f60a69d06f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2331490504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2331490504 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.474123259 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 6553527597 ps |
| CPU time | 22.38 seconds |
| Started | Jan 21 10:44:36 PM PST 24 |
| Finished | Jan 21 10:45:08 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-d303b87e-3b0b-4e25-b80a-a9973d0c4a8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=474123259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.474123259 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1222004973 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2688169526 ps |
| CPU time | 22.44 seconds |
| Started | Jan 21 10:44:35 PM PST 24 |
| Finished | Jan 21 10:45:07 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-87ff04d6-7e96-458f-bd48-9d2f5cc44fc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1222004973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1222004973 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3979306664 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 22419959 ps |
| CPU time | 1.9 seconds |
| Started | Jan 21 10:44:33 PM PST 24 |
| Finished | Jan 21 10:44:45 PM PST 24 |
| Peak memory | 203580 kb |
| Host | smart-0a905ed1-ed0b-44ef-97e8-00579c5abc12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979306664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3979306664 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1401809600 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2012502670 ps |
| CPU time | 49.77 seconds |
| Started | Jan 21 11:18:46 PM PST 24 |
| Finished | Jan 21 11:19:39 PM PST 24 |
| Peak memory | 211684 kb |
| Host | smart-768e6d38-2807-4837-9731-7eb8280376a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1401809600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1401809600 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1990134612 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 2610587964 ps |
| CPU time | 65.57 seconds |
| Started | Jan 21 10:44:54 PM PST 24 |
| Finished | Jan 21 10:46:01 PM PST 24 |
| Peak memory | 205628 kb |
| Host | smart-14326b15-3378-4a70-8eb1-588632e3503c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1990134612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1990134612 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1563511842 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 82827202 ps |
| CPU time | 27.09 seconds |
| Started | Jan 21 10:44:52 PM PST 24 |
| Finished | Jan 21 10:45:20 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-43609e5f-3a16-4b22-8407-81f5b0e00dfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1563511842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1563511842 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2844945372 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1708119262 ps |
| CPU time | 21.7 seconds |
| Started | Jan 21 10:44:41 PM PST 24 |
| Finished | Jan 21 10:45:09 PM PST 24 |
| Peak memory | 204580 kb |
| Host | smart-760c21e9-fb64-46cb-83c9-3571903f3bca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2844945372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2844945372 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.467602451 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2784891681 ps |
| CPU time | 65.62 seconds |
| Started | Jan 21 10:45:08 PM PST 24 |
| Finished | Jan 21 10:46:15 PM PST 24 |
| Peak memory | 206556 kb |
| Host | smart-31cdca74-746e-4e7e-a131-dae30777150a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=467602451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.467602451 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2302691246 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 192206069868 ps |
| CPU time | 557.97 seconds |
| Started | Jan 21 11:09:48 PM PST 24 |
| Finished | Jan 21 11:19:09 PM PST 24 |
| Peak memory | 206748 kb |
| Host | smart-9e1ff749-c465-4084-8bf7-f1494c3e3078 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2302691246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.2302691246 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.814047912 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 640877304 ps |
| CPU time | 19.49 seconds |
| Started | Jan 21 10:45:09 PM PST 24 |
| Finished | Jan 21 10:45:30 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-6f723b73-cc9f-49f5-b439-cda0b272c4ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=814047912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.814047912 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.3074966833 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1627059838 ps |
| CPU time | 19.89 seconds |
| Started | Jan 21 10:45:06 PM PST 24 |
| Finished | Jan 21 10:45:28 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-fcf4d8f6-b7a8-4093-97e2-616e2baa3d47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3074966833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3074966833 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.2825093614 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 720624820 ps |
| CPU time | 4.65 seconds |
| Started | Jan 21 10:44:52 PM PST 24 |
| Finished | Jan 21 10:44:57 PM PST 24 |
| Peak memory | 203664 kb |
| Host | smart-2b630d16-26fd-4d95-bd85-b6e9c9aac97e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2825093614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2825093614 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.431852368 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 63321553984 ps |
| CPU time | 211.38 seconds |
| Started | Jan 21 10:45:00 PM PST 24 |
| Finished | Jan 21 10:48:34 PM PST 24 |
| Peak memory | 211648 kb |
| Host | smart-43475a03-8d5a-49c2-9aff-b83412986d08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=431852368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.431852368 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2014045709 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 41367083411 ps |
| CPU time | 233.95 seconds |
| Started | Jan 21 11:35:42 PM PST 24 |
| Finished | Jan 21 11:39:40 PM PST 24 |
| Peak memory | 211776 kb |
| Host | smart-ed8cdba7-d57b-41c9-9e20-81bf6f52bfd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2014045709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2014045709 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.902497700 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 379166362 ps |
| CPU time | 18.68 seconds |
| Started | Jan 21 10:44:56 PM PST 24 |
| Finished | Jan 21 10:45:16 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-51722875-5168-48fc-8ba0-a289e15b9bc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902497700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.902497700 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.734899846 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1766876179 ps |
| CPU time | 29.18 seconds |
| Started | Jan 21 10:45:05 PM PST 24 |
| Finished | Jan 21 10:45:36 PM PST 24 |
| Peak memory | 203628 kb |
| Host | smart-9b4c435e-5139-4ee4-99d1-9c520f5c3770 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=734899846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.734899846 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.912667355 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 216042892 ps |
| CPU time | 3.68 seconds |
| Started | Jan 21 10:44:56 PM PST 24 |
| Finished | Jan 21 10:45:01 PM PST 24 |
| Peak memory | 203244 kb |
| Host | smart-4451cddd-5f80-4a37-a72a-fbea3ea778d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=912667355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.912667355 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1849075298 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 28956805697 ps |
| CPU time | 40.76 seconds |
| Started | Jan 21 10:44:54 PM PST 24 |
| Finished | Jan 21 10:45:37 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-d9809d4d-e1f5-4046-84ad-9d4746d56f98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849075298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1849075298 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3014652035 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2928012967 ps |
| CPU time | 27.23 seconds |
| Started | Jan 21 10:44:54 PM PST 24 |
| Finished | Jan 21 10:45:23 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-299c6b11-d696-4c7f-a253-afbd7fccdb2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3014652035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3014652035 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3461253056 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 27498131 ps |
| CPU time | 2.2 seconds |
| Started | Jan 21 11:01:11 PM PST 24 |
| Finished | Jan 21 11:01:15 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-a606d79e-3313-4618-9f5c-613c0c92568b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461253056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3461253056 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.3589864947 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2968246250 ps |
| CPU time | 92.35 seconds |
| Started | Jan 21 10:45:15 PM PST 24 |
| Finished | Jan 21 10:46:52 PM PST 24 |
| Peak memory | 205584 kb |
| Host | smart-2fac3a8b-b294-41cc-8ed7-80d81a392d99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3589864947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3589864947 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4054233179 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1012111726 ps |
| CPU time | 88.41 seconds |
| Started | Jan 21 10:45:11 PM PST 24 |
| Finished | Jan 21 10:46:45 PM PST 24 |
| Peak memory | 206648 kb |
| Host | smart-5bed5ef3-7b66-47e5-9a58-5eb2d8d29428 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4054233179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.4054233179 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.1557442352 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1123391293 ps |
| CPU time | 28.26 seconds |
| Started | Jan 21 10:45:08 PM PST 24 |
| Finished | Jan 21 10:45:38 PM PST 24 |
| Peak memory | 211604 kb |
| Host | smart-523ec30c-1b5e-4e8a-8db7-80992a49675a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1557442352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1557442352 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.715562544 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 376239866 ps |
| CPU time | 48.42 seconds |
| Started | Jan 21 10:45:37 PM PST 24 |
| Finished | Jan 21 10:46:26 PM PST 24 |
| Peak memory | 205132 kb |
| Host | smart-1066c113-957c-416b-a15f-d7578f4709b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=715562544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.715562544 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2126486368 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 9714364126 ps |
| CPU time | 91.89 seconds |
| Started | Jan 21 11:10:00 PM PST 24 |
| Finished | Jan 21 11:11:35 PM PST 24 |
| Peak memory | 211716 kb |
| Host | smart-0c652a8c-6930-48cf-b349-e57658e48fa7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2126486368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.2126486368 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3310749799 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1003295711 ps |
| CPU time | 17.45 seconds |
| Started | Jan 21 10:45:32 PM PST 24 |
| Finished | Jan 21 10:45:51 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-f65446b2-5a7c-423b-bc65-8757b24bf465 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3310749799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3310749799 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.3583634790 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 882087473 ps |
| CPU time | 31.91 seconds |
| Started | Jan 21 10:45:33 PM PST 24 |
| Finished | Jan 21 10:46:07 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-842df66a-2a42-4714-971a-2a1ed273cd93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3583634790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3583634790 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.1518773318 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2064283912 ps |
| CPU time | 20.73 seconds |
| Started | Jan 21 10:45:18 PM PST 24 |
| Finished | Jan 21 10:45:43 PM PST 24 |
| Peak memory | 211620 kb |
| Host | smart-9510d91b-9d4e-48d4-9f9e-daa05522d1cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1518773318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1518773318 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2591888107 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 72142602928 ps |
| CPU time | 92.4 seconds |
| Started | Jan 21 10:45:32 PM PST 24 |
| Finished | Jan 21 10:47:06 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-5c34bf14-5980-4c1c-a656-875e945f8c2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591888107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2591888107 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1371742798 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 57389778927 ps |
| CPU time | 118.5 seconds |
| Started | Jan 21 10:45:37 PM PST 24 |
| Finished | Jan 21 10:47:36 PM PST 24 |
| Peak memory | 211660 kb |
| Host | smart-65e15cd9-acf6-44e3-8f4e-984bebdf6567 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1371742798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1371742798 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.1487813351 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 197891262 ps |
| CPU time | 23.41 seconds |
| Started | Jan 21 10:45:26 PM PST 24 |
| Finished | Jan 21 10:45:54 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-a9546234-bfb1-4e79-8909-44c7ce4aa1d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487813351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1487813351 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1736386137 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2376384968 ps |
| CPU time | 34.51 seconds |
| Started | Jan 21 11:14:48 PM PST 24 |
| Finished | Jan 21 11:15:26 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-988e3a47-7783-4f71-b02a-db540296cefb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1736386137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1736386137 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.2114982448 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 220186404 ps |
| CPU time | 4.09 seconds |
| Started | Jan 21 10:45:17 PM PST 24 |
| Finished | Jan 21 10:45:25 PM PST 24 |
| Peak memory | 203368 kb |
| Host | smart-095a7b86-0c6c-4e88-94c9-153067510d0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2114982448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2114982448 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2984265661 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 11916005883 ps |
| CPU time | 32.32 seconds |
| Started | Jan 21 10:45:18 PM PST 24 |
| Finished | Jan 21 10:45:55 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-d894aa8b-667b-4453-9043-8a62ad23a61d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984265661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2984265661 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1036020693 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 20997989547 ps |
| CPU time | 46.57 seconds |
| Started | Jan 21 10:45:21 PM PST 24 |
| Finished | Jan 21 10:46:15 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-25400960-5675-4934-be69-4d470162f574 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1036020693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1036020693 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1144600603 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 25437609 ps |
| CPU time | 2.45 seconds |
| Started | Jan 21 10:45:20 PM PST 24 |
| Finished | Jan 21 10:45:30 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-094495d2-ee32-4d15-a44d-92993f6d5535 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144600603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1144600603 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2144741717 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 778404551 ps |
| CPU time | 28.68 seconds |
| Started | Jan 21 10:45:34 PM PST 24 |
| Finished | Jan 21 10:46:04 PM PST 24 |
| Peak memory | 211592 kb |
| Host | smart-0f4693bf-3887-437c-b486-65a74df3dc31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2144741717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2144741717 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1011268470 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3074549510 ps |
| CPU time | 48.34 seconds |
| Started | Jan 21 10:45:36 PM PST 24 |
| Finished | Jan 21 10:46:26 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-4e59ef75-7162-42f0-8a04-c6bb5223f65c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1011268470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1011268470 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2899117014 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 9364835437 ps |
| CPU time | 279.57 seconds |
| Started | Jan 21 11:30:10 PM PST 24 |
| Finished | Jan 21 11:34:51 PM PST 24 |
| Peak memory | 209840 kb |
| Host | smart-f6e56568-e95e-4994-bded-2c34865fec9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2899117014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.2899117014 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3390815288 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 12678352087 ps |
| CPU time | 166.24 seconds |
| Started | Jan 21 10:45:37 PM PST 24 |
| Finished | Jan 21 10:48:24 PM PST 24 |
| Peak memory | 208884 kb |
| Host | smart-d2c4ee56-2232-458b-b9e0-76b516390c51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3390815288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.3390815288 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.154634084 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 123739679 ps |
| CPU time | 14.32 seconds |
| Started | Jan 21 10:45:33 PM PST 24 |
| Finished | Jan 21 10:45:49 PM PST 24 |
| Peak memory | 211556 kb |
| Host | smart-a08f953a-4ec2-4056-ab7c-60fdee98b54a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=154634084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.154634084 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2990155677 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 109932961 ps |
| CPU time | 14.64 seconds |
| Started | Jan 21 10:45:43 PM PST 24 |
| Finished | Jan 21 10:45:59 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-702b2589-bace-4c01-bac9-e1c83353b891 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2990155677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2990155677 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3558322755 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1666980116 ps |
| CPU time | 20.31 seconds |
| Started | Jan 21 10:45:48 PM PST 24 |
| Finished | Jan 21 10:46:09 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-b2f5c4d9-4812-4f56-bf90-aea26a683843 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3558322755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3558322755 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.2120131076 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 434000003 ps |
| CPU time | 11.09 seconds |
| Started | Jan 21 10:45:45 PM PST 24 |
| Finished | Jan 21 10:45:57 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-890f0e0d-65f3-4f18-aae8-a8b574b43737 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2120131076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2120131076 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.944720405 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 961105648 ps |
| CPU time | 23.72 seconds |
| Started | Jan 21 10:45:36 PM PST 24 |
| Finished | Jan 21 10:46:01 PM PST 24 |
| Peak memory | 204196 kb |
| Host | smart-464f290f-3963-4f55-899b-9eb2f879fa40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=944720405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.944720405 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.4036792441 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 45717530071 ps |
| CPU time | 201.35 seconds |
| Started | Jan 21 10:45:44 PM PST 24 |
| Finished | Jan 21 10:49:07 PM PST 24 |
| Peak memory | 204984 kb |
| Host | smart-7e960c64-1985-41e0-b225-76f6cb3d188e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036792441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.4036792441 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.988458230 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 122114361915 ps |
| CPU time | 226.23 seconds |
| Started | Jan 21 10:45:48 PM PST 24 |
| Finished | Jan 21 10:49:35 PM PST 24 |
| Peak memory | 205028 kb |
| Host | smart-8a248220-e7a7-4147-8b20-ec262a657081 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=988458230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.988458230 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.4131685932 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 182009789 ps |
| CPU time | 26.9 seconds |
| Started | Jan 21 10:45:41 PM PST 24 |
| Finished | Jan 21 10:46:10 PM PST 24 |
| Peak memory | 204820 kb |
| Host | smart-06d20623-c598-4026-874c-fb3129646838 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131685932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.4131685932 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.1283575726 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 214687713 ps |
| CPU time | 4.56 seconds |
| Started | Jan 21 10:45:49 PM PST 24 |
| Finished | Jan 21 10:45:54 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-ba790e75-3ad5-4549-b6b2-25af9094f1f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1283575726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1283575726 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.3086313971 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 152363792 ps |
| CPU time | 3.58 seconds |
| Started | Jan 21 10:45:34 PM PST 24 |
| Finished | Jan 21 10:45:39 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-1dc0fd7c-6779-4c84-a387-f5d23cb1ae3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3086313971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3086313971 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1211878367 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 5824371190 ps |
| CPU time | 29.65 seconds |
| Started | Jan 21 10:45:36 PM PST 24 |
| Finished | Jan 21 10:46:06 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-7653bbf3-c78b-4d7c-bb49-2ab2b8eb7159 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211878367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1211878367 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.676598541 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 6078552033 ps |
| CPU time | 33.93 seconds |
| Started | Jan 21 10:45:38 PM PST 24 |
| Finished | Jan 21 10:46:13 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-c698cba1-7f9a-4615-aeb5-51a7566fc04f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=676598541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.676598541 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3948540961 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 77760086 ps |
| CPU time | 2.5 seconds |
| Started | Jan 21 10:45:34 PM PST 24 |
| Finished | Jan 21 10:45:38 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-da58a2e9-45e7-4802-a393-bdaffcd80173 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948540961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3948540961 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.2572442327 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 801400622 ps |
| CPU time | 58.61 seconds |
| Started | Jan 21 10:45:44 PM PST 24 |
| Finished | Jan 21 10:46:44 PM PST 24 |
| Peak memory | 206568 kb |
| Host | smart-07c393a8-3890-490c-bf16-47ab6b0cd993 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2572442327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2572442327 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.765471294 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 37561199026 ps |
| CPU time | 206.21 seconds |
| Started | Jan 21 10:45:48 PM PST 24 |
| Finished | Jan 21 10:49:15 PM PST 24 |
| Peak memory | 211648 kb |
| Host | smart-5486d8ea-6764-43df-b9ee-1f8642177a45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=765471294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.765471294 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2664978824 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 6138174893 ps |
| CPU time | 138.65 seconds |
| Started | Jan 21 10:45:48 PM PST 24 |
| Finished | Jan 21 10:48:08 PM PST 24 |
| Peak memory | 208616 kb |
| Host | smart-b03fca9a-27d4-406e-bd2c-4fcc59e14d20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2664978824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.2664978824 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4222036791 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 14390178277 ps |
| CPU time | 528.74 seconds |
| Started | Jan 21 10:45:53 PM PST 24 |
| Finished | Jan 21 10:54:43 PM PST 24 |
| Peak memory | 224856 kb |
| Host | smart-50927690-8b9f-46e8-b83a-95b598df03b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4222036791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.4222036791 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1881188238 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 619361811 ps |
| CPU time | 19.47 seconds |
| Started | Jan 21 10:45:49 PM PST 24 |
| Finished | Jan 21 10:46:09 PM PST 24 |
| Peak memory | 211556 kb |
| Host | smart-f93fa24f-18dc-45e6-8cd9-0f9d03c957af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1881188238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1881188238 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3048377432 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 825645164 ps |
| CPU time | 36.77 seconds |
| Started | Jan 21 10:46:16 PM PST 24 |
| Finished | Jan 21 10:46:54 PM PST 24 |
| Peak memory | 211608 kb |
| Host | smart-d0d1ff5b-01f5-4f5e-9016-7d29b5621da3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3048377432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3048377432 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1518832599 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 241786508629 ps |
| CPU time | 692.09 seconds |
| Started | Jan 21 10:33:15 PM PST 24 |
| Finished | Jan 21 10:44:50 PM PST 24 |
| Peak memory | 211644 kb |
| Host | smart-ee38f463-f444-4781-8d72-293ddae0693d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1518832599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.1518832599 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.159543451 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 235139292 ps |
| CPU time | 15.96 seconds |
| Started | Jan 21 10:33:11 PM PST 24 |
| Finished | Jan 21 10:33:28 PM PST 24 |
| Peak memory | 203744 kb |
| Host | smart-53d2b4bc-39c8-4dad-887e-e0fe62b00dba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=159543451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.159543451 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.1417668716 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 268214014 ps |
| CPU time | 19.12 seconds |
| Started | Jan 21 10:33:10 PM PST 24 |
| Finished | Jan 21 10:33:31 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-3a381983-093d-4883-9305-fc81d5a6d33d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1417668716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1417668716 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.335833532 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 1570937277 ps |
| CPU time | 37.87 seconds |
| Started | Jan 21 10:33:06 PM PST 24 |
| Finished | Jan 21 10:33:47 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-d764ba01-ac5d-42d4-abcb-4b19b28c406d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=335833532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.335833532 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2386466369 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 43505501509 ps |
| CPU time | 165.86 seconds |
| Started | Jan 21 10:33:03 PM PST 24 |
| Finished | Jan 21 10:35:54 PM PST 24 |
| Peak memory | 211672 kb |
| Host | smart-b9957a60-0c08-4cff-8de0-698d25073dc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386466369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2386466369 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.3425632914 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 32876478984 ps |
| CPU time | 185 seconds |
| Started | Jan 21 10:52:17 PM PST 24 |
| Finished | Jan 21 10:55:25 PM PST 24 |
| Peak memory | 211700 kb |
| Host | smart-244f0269-7bde-4b6e-b61a-39269827a9f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3425632914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3425632914 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3935419313 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1102062941 ps |
| CPU time | 32.29 seconds |
| Started | Jan 21 10:33:02 PM PST 24 |
| Finished | Jan 21 10:33:39 PM PST 24 |
| Peak memory | 211776 kb |
| Host | smart-47b375b1-8bb1-498f-b741-4a54230f7a76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935419313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3935419313 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.1257265338 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 229561933 ps |
| CPU time | 5.11 seconds |
| Started | Jan 21 10:33:10 PM PST 24 |
| Finished | Jan 21 10:33:17 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-9cd4ecf7-1b21-449e-aa2d-2228a4157991 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1257265338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1257265338 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.2522948504 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 118385165 ps |
| CPU time | 2.31 seconds |
| Started | Jan 21 10:32:56 PM PST 24 |
| Finished | Jan 21 10:33:04 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-e318bc1d-725f-4a25-8b43-78ccd88abd6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2522948504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2522948504 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.141621118 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 10016274414 ps |
| CPU time | 28.49 seconds |
| Started | Jan 21 10:32:57 PM PST 24 |
| Finished | Jan 21 10:33:30 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-70135d4f-9be2-45d2-9f3a-afbbd163f9f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=141621118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.141621118 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1362532823 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 7619504428 ps |
| CPU time | 22.37 seconds |
| Started | Jan 21 10:33:03 PM PST 24 |
| Finished | Jan 21 10:33:30 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-d5fabcb1-5ac4-4635-965d-45433b91cde0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1362532823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1362532823 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.3004469912 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 56350451 ps |
| CPU time | 1.91 seconds |
| Started | Jan 21 10:32:58 PM PST 24 |
| Finished | Jan 21 10:33:04 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-94228f55-c010-443f-a252-89c8e7d21077 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004469912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3004469912 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.3087320421 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 12822683083 ps |
| CPU time | 311.7 seconds |
| Started | Jan 21 10:33:11 PM PST 24 |
| Finished | Jan 21 10:38:24 PM PST 24 |
| Peak memory | 207264 kb |
| Host | smart-38149835-45ea-4016-9e4f-7cfd02452802 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3087320421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3087320421 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3340461790 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 12126453967 ps |
| CPU time | 159.65 seconds |
| Started | Jan 21 10:33:16 PM PST 24 |
| Finished | Jan 21 10:36:00 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-30ce2e8c-75e8-461c-a2cb-27e9790b13c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3340461790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3340461790 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3089545704 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 134149224 ps |
| CPU time | 5.64 seconds |
| Started | Jan 21 10:33:16 PM PST 24 |
| Finished | Jan 21 10:33:27 PM PST 24 |
| Peak memory | 204432 kb |
| Host | smart-5f63b37a-cec7-4f9f-8d8e-1cd5d7d64925 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3089545704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.3089545704 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.1092060983 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 294357729 ps |
| CPU time | 17.01 seconds |
| Started | Jan 21 10:33:09 PM PST 24 |
| Finished | Jan 21 10:33:29 PM PST 24 |
| Peak memory | 211592 kb |
| Host | smart-d84804c4-7a95-4b3b-8a45-b29fbe60e730 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1092060983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1092060983 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.2762089723 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 331417528 ps |
| CPU time | 7.18 seconds |
| Started | Jan 21 10:33:17 PM PST 24 |
| Finished | Jan 21 10:33:30 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-ae14f40a-6a4c-4a2d-8b26-849c035a6820 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2762089723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2762089723 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.521560409 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 15870606257 ps |
| CPU time | 33.45 seconds |
| Started | Jan 21 10:33:18 PM PST 24 |
| Finished | Jan 21 10:33:57 PM PST 24 |
| Peak memory | 203888 kb |
| Host | smart-fa3376f7-c38a-427b-bd4d-589e875c1768 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=521560409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow _rsp.521560409 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3766421309 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 3379346898 ps |
| CPU time | 22.76 seconds |
| Started | Jan 21 10:33:17 PM PST 24 |
| Finished | Jan 21 10:33:46 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-96308b4b-ca1a-4e0d-8222-0a0614b74a1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3766421309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3766421309 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.2313219244 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 411824261 ps |
| CPU time | 11.9 seconds |
| Started | Jan 21 10:33:18 PM PST 24 |
| Finished | Jan 21 10:33:35 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-dcdd4c87-a313-4361-8e7b-89213e22fb9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2313219244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2313219244 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.2633973690 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 171764893 ps |
| CPU time | 16.49 seconds |
| Started | Jan 21 10:33:12 PM PST 24 |
| Finished | Jan 21 10:33:30 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-624f2a5d-29b7-46cc-a795-3b43211cac40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2633973690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2633973690 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.2640404629 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 62455443700 ps |
| CPU time | 232.3 seconds |
| Started | Jan 21 10:33:19 PM PST 24 |
| Finished | Jan 21 10:37:17 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-2cce2bd2-304a-4573-87a1-b482c905ed50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640404629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2640404629 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3494336505 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 14168109102 ps |
| CPU time | 117.47 seconds |
| Started | Jan 21 10:33:19 PM PST 24 |
| Finished | Jan 21 10:35:24 PM PST 24 |
| Peak memory | 204784 kb |
| Host | smart-1e54f0f2-cd5a-42e8-bf13-098a2bbc9915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3494336505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3494336505 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3125039632 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 99654837 ps |
| CPU time | 8.93 seconds |
| Started | Jan 21 10:33:19 PM PST 24 |
| Finished | Jan 21 10:33:33 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-2fef1722-9c71-434b-9911-369af8ec4f6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125039632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3125039632 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.821325231 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1128771885 ps |
| CPU time | 16.43 seconds |
| Started | Jan 21 10:33:19 PM PST 24 |
| Finished | Jan 21 10:33:43 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-6e318cb7-2b31-4022-a6c3-a7556e3d4cb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=821325231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.821325231 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.1173396977 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 136139034 ps |
| CPU time | 3.27 seconds |
| Started | Jan 21 10:33:15 PM PST 24 |
| Finished | Jan 21 10:33:23 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-45d25b12-6bc4-4ee0-9ba7-ac7aee80b821 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1173396977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1173396977 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.4128868009 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 5034061780 ps |
| CPU time | 27.79 seconds |
| Started | Jan 21 10:33:16 PM PST 24 |
| Finished | Jan 21 10:33:49 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-7b41f9c6-537c-466e-9cde-f7951ee4a5b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128868009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4128868009 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1981753858 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 5740877170 ps |
| CPU time | 27.72 seconds |
| Started | Jan 21 10:33:16 PM PST 24 |
| Finished | Jan 21 10:33:49 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-1e4cf55b-4938-450e-b3e5-31511dd12e14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1981753858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1981753858 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.1235036426 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 49733973 ps |
| CPU time | 2.19 seconds |
| Started | Jan 21 10:33:13 PM PST 24 |
| Finished | Jan 21 10:33:18 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-7d4f39b3-35ab-4ff1-83fe-b3f78fd94f57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235036426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.1235036426 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1527443532 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 639912154 ps |
| CPU time | 59.57 seconds |
| Started | Jan 21 10:33:19 PM PST 24 |
| Finished | Jan 21 10:34:24 PM PST 24 |
| Peak memory | 206068 kb |
| Host | smart-f5e6e4ee-a24e-4ebb-9a34-7728836b3bea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1527443532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1527443532 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.4020482394 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1108568137 ps |
| CPU time | 27.6 seconds |
| Started | Jan 21 10:33:24 PM PST 24 |
| Finished | Jan 21 10:33:57 PM PST 24 |
| Peak memory | 204500 kb |
| Host | smart-a2831c86-54be-4494-8ae7-9794373c5a0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4020482394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.4020482394 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3161892364 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1359065637 ps |
| CPU time | 213.98 seconds |
| Started | Jan 21 10:33:18 PM PST 24 |
| Finished | Jan 21 10:36:58 PM PST 24 |
| Peak memory | 208312 kb |
| Host | smart-9010d52e-ab54-4614-ae09-f698f164e872 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3161892364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.3161892364 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2431923471 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 232071819 ps |
| CPU time | 46.68 seconds |
| Started | Jan 21 10:33:34 PM PST 24 |
| Finished | Jan 21 10:34:22 PM PST 24 |
| Peak memory | 206676 kb |
| Host | smart-2bd79310-2b44-41ea-84fe-37b6d944afb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2431923471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.2431923471 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.548744320 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 209502916 ps |
| CPU time | 4.85 seconds |
| Started | Jan 21 10:56:35 PM PST 24 |
| Finished | Jan 21 10:56:41 PM PST 24 |
| Peak memory | 211520 kb |
| Host | smart-1ba2fd6f-4567-402b-96b0-6292bd0a8614 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=548744320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.548744320 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.2631912200 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2723159913 ps |
| CPU time | 50.32 seconds |
| Started | Jan 21 10:33:34 PM PST 24 |
| Finished | Jan 21 10:34:26 PM PST 24 |
| Peak memory | 206256 kb |
| Host | smart-186554fc-7edf-400d-bf1c-fccbbfbcd841 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2631912200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.2631912200 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3581625227 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2813859195 ps |
| CPU time | 25.85 seconds |
| Started | Jan 21 10:33:36 PM PST 24 |
| Finished | Jan 21 10:34:03 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-615e083b-fa6e-4bc0-877c-bd65eec8cc52 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3581625227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.3581625227 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2030216710 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 634210652 ps |
| CPU time | 10.3 seconds |
| Started | Jan 21 10:33:31 PM PST 24 |
| Finished | Jan 21 10:33:43 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-e8ff4152-943f-4e31-999f-361b820aaa8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2030216710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2030216710 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.703850256 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 394732870 ps |
| CPU time | 12.65 seconds |
| Started | Jan 21 11:09:48 PM PST 24 |
| Finished | Jan 21 11:10:03 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-81f0760e-5818-4570-b856-3a2b1c0a163f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=703850256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.703850256 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.4163912866 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1014956936 ps |
| CPU time | 38.57 seconds |
| Started | Jan 21 10:33:30 PM PST 24 |
| Finished | Jan 21 10:34:10 PM PST 24 |
| Peak memory | 204424 kb |
| Host | smart-4a8f4de1-10d4-4b97-b4b1-c2e2d59b3e34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4163912866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.4163912866 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.2984204376 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 22378422415 ps |
| CPU time | 118.62 seconds |
| Started | Jan 21 10:53:43 PM PST 24 |
| Finished | Jan 21 10:55:42 PM PST 24 |
| Peak memory | 211696 kb |
| Host | smart-e13676fa-7f63-4279-81dc-5533c427de87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984204376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2984204376 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2703172048 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 9412367932 ps |
| CPU time | 80.65 seconds |
| Started | Jan 21 10:33:33 PM PST 24 |
| Finished | Jan 21 10:34:55 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-efcfcefe-2bd7-4cd2-9c7e-e66d460352b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2703172048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2703172048 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3143012999 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 119791621 ps |
| CPU time | 13.11 seconds |
| Started | Jan 21 10:33:33 PM PST 24 |
| Finished | Jan 21 10:33:47 PM PST 24 |
| Peak memory | 204460 kb |
| Host | smart-a30c49d4-c1f6-4b5a-aa08-506bc5d1b0ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143012999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3143012999 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.2361286528 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1740380748 ps |
| CPU time | 11.68 seconds |
| Started | Jan 21 10:33:31 PM PST 24 |
| Finished | Jan 21 10:33:44 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-61ff4e52-2ebc-4cc3-b809-434221dcf598 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2361286528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2361286528 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.3036568732 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 497582492 ps |
| CPU time | 3.46 seconds |
| Started | Jan 21 10:33:33 PM PST 24 |
| Finished | Jan 21 10:33:37 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-4efe55a2-74df-4747-8124-ebd98823e599 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3036568732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3036568732 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.271116783 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 6413130721 ps |
| CPU time | 28.25 seconds |
| Started | Jan 21 10:33:30 PM PST 24 |
| Finished | Jan 21 10:34:00 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-8a676267-85ca-4646-8565-692e3d949f96 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=271116783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.271116783 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2325419777 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9046179215 ps |
| CPU time | 36.39 seconds |
| Started | Jan 21 10:33:30 PM PST 24 |
| Finished | Jan 21 10:34:09 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-845cbb86-d3c3-4057-9f93-d7dd329ef746 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2325419777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2325419777 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.815332941 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 36507650 ps |
| CPU time | 2.26 seconds |
| Started | Jan 21 10:33:35 PM PST 24 |
| Finished | Jan 21 10:33:39 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-2b516338-e1c1-4f9c-8d33-309ce9febb53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815332941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.815332941 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2967080488 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 805293651 ps |
| CPU time | 73.81 seconds |
| Started | Jan 21 10:33:50 PM PST 24 |
| Finished | Jan 21 10:35:05 PM PST 24 |
| Peak memory | 205576 kb |
| Host | smart-1f0167a8-78ea-4190-8057-9a5a7b91b9bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2967080488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2967080488 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2732502113 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 798864242 ps |
| CPU time | 59.57 seconds |
| Started | Jan 21 10:33:39 PM PST 24 |
| Finished | Jan 21 10:34:40 PM PST 24 |
| Peak memory | 204528 kb |
| Host | smart-0fdc13cd-b6fa-4a94-8362-17f2deb585d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2732502113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2732502113 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2631115717 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 13265825639 ps |
| CPU time | 236.85 seconds |
| Started | Jan 21 10:33:38 PM PST 24 |
| Finished | Jan 21 10:37:36 PM PST 24 |
| Peak memory | 208476 kb |
| Host | smart-8db55b14-d1a3-431f-9898-a0ecc8dfefed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2631115717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.2631115717 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.2016430585 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 6975273 ps |
| CPU time | 12.35 seconds |
| Started | Jan 21 10:33:39 PM PST 24 |
| Finished | Jan 21 10:33:52 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-b1df22be-087d-432f-929f-796cc3b6f051 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2016430585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.2016430585 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.580044089 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 544706245 ps |
| CPU time | 22 seconds |
| Started | Jan 21 10:33:33 PM PST 24 |
| Finished | Jan 21 10:33:57 PM PST 24 |
| Peak memory | 211772 kb |
| Host | smart-2991fe5e-9045-46cd-b220-ec526ff0d689 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=580044089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.580044089 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2992468369 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 356805007 ps |
| CPU time | 37.98 seconds |
| Started | Jan 21 10:33:53 PM PST 24 |
| Finished | Jan 21 10:34:33 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-d902248c-e8b0-4bf1-8336-7b2780ffd6c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2992468369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2992468369 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.1636582902 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 16779599395 ps |
| CPU time | 126.83 seconds |
| Started | Jan 21 10:33:47 PM PST 24 |
| Finished | Jan 21 10:35:56 PM PST 24 |
| Peak memory | 211676 kb |
| Host | smart-9f69f099-9e98-4015-b6ec-4b88218b43a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1636582902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.1636582902 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1627901878 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 79884226 ps |
| CPU time | 10.31 seconds |
| Started | Jan 21 10:33:56 PM PST 24 |
| Finished | Jan 21 10:34:08 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-996e76d7-bc17-4c30-b890-775427e47ec7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1627901878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1627901878 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.2385192216 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 100383388 ps |
| CPU time | 10.45 seconds |
| Started | Jan 21 10:33:53 PM PST 24 |
| Finished | Jan 21 10:34:06 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-6d9acd2e-da02-4e02-99d7-3ce66aa97a1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2385192216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2385192216 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.51850066 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1253660776 ps |
| CPU time | 14.4 seconds |
| Started | Jan 21 10:33:47 PM PST 24 |
| Finished | Jan 21 10:34:04 PM PST 24 |
| Peak memory | 204052 kb |
| Host | smart-ec9e1731-b1e5-46f8-9544-d37dc5a35b3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=51850066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.51850066 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1147213586 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 29868797117 ps |
| CPU time | 137.62 seconds |
| Started | Jan 21 10:33:53 PM PST 24 |
| Finished | Jan 21 10:36:13 PM PST 24 |
| Peak memory | 204704 kb |
| Host | smart-438757bb-3bec-4d2c-92c8-4813296d89fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147213586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1147213586 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.495181873 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 10781496378 ps |
| CPU time | 80.21 seconds |
| Started | Jan 21 10:33:48 PM PST 24 |
| Finished | Jan 21 10:35:11 PM PST 24 |
| Peak memory | 211620 kb |
| Host | smart-5cb057fe-9f92-4de1-b9a1-8160d537ccae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=495181873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.495181873 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.950859175 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 754263636 ps |
| CPU time | 19.33 seconds |
| Started | Jan 21 10:33:48 PM PST 24 |
| Finished | Jan 21 10:34:10 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-ebcd938b-c799-40e5-a530-82769dee8e1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950859175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.950859175 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.2759450962 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 511260040 ps |
| CPU time | 18.75 seconds |
| Started | Jan 21 10:33:48 PM PST 24 |
| Finished | Jan 21 10:34:09 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-6cbd7eac-f315-4fc5-9637-77001d526396 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2759450962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2759450962 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.2086338664 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 188980423 ps |
| CPU time | 3.49 seconds |
| Started | Jan 21 10:33:39 PM PST 24 |
| Finished | Jan 21 10:33:44 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-fb0da7fc-ff9f-480c-b347-27ec8daef32a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2086338664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2086338664 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3734126282 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 20833518433 ps |
| CPU time | 37.56 seconds |
| Started | Jan 21 10:33:39 PM PST 24 |
| Finished | Jan 21 10:34:18 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-3cb372a5-31b5-4257-a6b3-667aef2807a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734126282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3734126282 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2978788903 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 3830369727 ps |
| CPU time | 23.59 seconds |
| Started | Jan 21 10:33:48 PM PST 24 |
| Finished | Jan 21 10:34:14 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-e77512b0-e4d8-42a3-8f9a-4e851b027968 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2978788903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2978788903 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.4243448945 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 30231493 ps |
| CPU time | 2.44 seconds |
| Started | Jan 21 10:33:41 PM PST 24 |
| Finished | Jan 21 10:33:45 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-aec02dbf-ca77-45f6-9456-58f80647e252 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243448945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.4243448945 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.48892871 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 975879201 ps |
| CPU time | 111.12 seconds |
| Started | Jan 21 10:33:56 PM PST 24 |
| Finished | Jan 21 10:35:49 PM PST 24 |
| Peak memory | 206548 kb |
| Host | smart-43faf328-d3af-4969-8830-c0abfbee8cca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=48892871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.48892871 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.200723372 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1233260817 ps |
| CPU time | 87.93 seconds |
| Started | Jan 21 10:33:55 PM PST 24 |
| Finished | Jan 21 10:35:24 PM PST 24 |
| Peak memory | 206004 kb |
| Host | smart-661aa52b-db17-4518-9da9-f79daec70df5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=200723372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.200723372 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3937676472 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3943002899 ps |
| CPU time | 368.58 seconds |
| Started | Jan 21 10:34:00 PM PST 24 |
| Finished | Jan 21 10:40:11 PM PST 24 |
| Peak memory | 209112 kb |
| Host | smart-07e640ae-b662-4650-9430-08ebc12f537f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3937676472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.3937676472 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1784933897 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 330501926 ps |
| CPU time | 45.31 seconds |
| Started | Jan 21 10:33:56 PM PST 24 |
| Finished | Jan 21 10:34:43 PM PST 24 |
| Peak memory | 206376 kb |
| Host | smart-d2d66e7a-1830-486c-9c09-3e8e5aae9c9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1784933897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.1784933897 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.294544265 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 73754532 ps |
| CPU time | 12.29 seconds |
| Started | Jan 21 10:33:59 PM PST 24 |
| Finished | Jan 21 10:34:12 PM PST 24 |
| Peak memory | 211608 kb |
| Host | smart-8d86105c-c567-48c2-b5e0-172d0d183aba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=294544265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.294544265 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2413337572 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1695338335 ps |
| CPU time | 62.16 seconds |
| Started | Jan 21 10:34:15 PM PST 24 |
| Finished | Jan 21 10:35:18 PM PST 24 |
| Peak memory | 205236 kb |
| Host | smart-96f1b059-7a57-4d7f-84bf-06c9c21730ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2413337572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2413337572 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2062908813 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 194724247653 ps |
| CPU time | 495.56 seconds |
| Started | Jan 21 10:34:15 PM PST 24 |
| Finished | Jan 21 10:42:31 PM PST 24 |
| Peak memory | 205688 kb |
| Host | smart-321753c9-dd5d-4ab0-aad1-1b1cf31e55fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2062908813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2062908813 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1656118208 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1456847326 ps |
| CPU time | 15.74 seconds |
| Started | Jan 21 10:34:21 PM PST 24 |
| Finished | Jan 21 10:34:38 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-8b1e9b20-8f7f-4c65-b334-328835576240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1656118208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1656118208 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.1295913364 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1321836205 ps |
| CPU time | 29.94 seconds |
| Started | Jan 21 10:34:22 PM PST 24 |
| Finished | Jan 21 10:34:53 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-0d94f4e0-3810-426d-ae2c-2fef81f4dcc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1295913364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1295913364 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.75949990 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 26283192 ps |
| CPU time | 3.76 seconds |
| Started | Jan 21 10:34:05 PM PST 24 |
| Finished | Jan 21 10:34:11 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-6ce994f0-d590-4e6d-ba24-73fcfaf51fe6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=75949990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.75949990 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3647511440 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 40394496500 ps |
| CPU time | 180.01 seconds |
| Started | Jan 21 10:34:12 PM PST 24 |
| Finished | Jan 21 10:37:13 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-942078d5-af24-4e81-a8d8-640e2925aa74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647511440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3647511440 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2801546593 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 23383199166 ps |
| CPU time | 212.37 seconds |
| Started | Jan 21 10:34:06 PM PST 24 |
| Finished | Jan 21 10:37:40 PM PST 24 |
| Peak memory | 204620 kb |
| Host | smart-8074e1fc-bd43-4bc6-af25-6c9edae03e39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2801546593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2801546593 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.3683620154 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 61837627 ps |
| CPU time | 9.16 seconds |
| Started | Jan 21 10:34:12 PM PST 24 |
| Finished | Jan 21 10:34:22 PM PST 24 |
| Peak memory | 204100 kb |
| Host | smart-670c509d-1c0c-4f3f-8480-57d9482c0e02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683620154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3683620154 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.2596377546 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1877591406 ps |
| CPU time | 20.76 seconds |
| Started | Jan 21 10:34:14 PM PST 24 |
| Finished | Jan 21 10:34:36 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-de440f6a-d5a3-4446-85d9-a752454c7c87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2596377546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2596377546 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.1540055076 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 641544069 ps |
| CPU time | 3.63 seconds |
| Started | Jan 21 10:33:55 PM PST 24 |
| Finished | Jan 21 10:34:00 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-ae879831-c301-4b85-b4c8-d511d776607d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1540055076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1540055076 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.4437036 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 6853822673 ps |
| CPU time | 27.27 seconds |
| Started | Jan 21 10:33:56 PM PST 24 |
| Finished | Jan 21 10:34:25 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-fd120320-1879-474f-bfdd-adf64136b483 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4437036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4437036 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3926137692 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6874090869 ps |
| CPU time | 26.01 seconds |
| Started | Jan 21 10:33:58 PM PST 24 |
| Finished | Jan 21 10:34:25 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-bfbfba82-e068-4688-87fd-1f4f0f4d292e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3926137692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3926137692 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3030002708 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 163265429 ps |
| CPU time | 2.45 seconds |
| Started | Jan 21 10:33:56 PM PST 24 |
| Finished | Jan 21 10:34:00 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-086a5485-0640-49da-b0c8-1a0e841e8364 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030002708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3030002708 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3276097629 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 3999379874 ps |
| CPU time | 123.25 seconds |
| Started | Jan 21 10:34:25 PM PST 24 |
| Finished | Jan 21 10:36:31 PM PST 24 |
| Peak memory | 206392 kb |
| Host | smart-358868ba-fabc-40b6-b52f-13bbf80759c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3276097629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3276097629 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.998954612 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1922520773 ps |
| CPU time | 157.84 seconds |
| Started | Jan 21 10:34:22 PM PST 24 |
| Finished | Jan 21 10:37:01 PM PST 24 |
| Peak memory | 209216 kb |
| Host | smart-9b9512d6-9403-4245-a987-f8e9fbcc9556 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=998954612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.998954612 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.551076558 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 6490780887 ps |
| CPU time | 378.79 seconds |
| Started | Jan 21 10:34:25 PM PST 24 |
| Finished | Jan 21 10:40:46 PM PST 24 |
| Peak memory | 211224 kb |
| Host | smart-be4b5bf0-1d0a-4354-b486-361a7cceff4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=551076558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_ reset.551076558 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3028262271 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 14647242755 ps |
| CPU time | 425.49 seconds |
| Started | Jan 21 10:34:25 PM PST 24 |
| Finished | Jan 21 10:41:31 PM PST 24 |
| Peak memory | 224288 kb |
| Host | smart-cf19a642-a264-4dff-9a2b-a1f2625a4738 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3028262271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.3028262271 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.3601506188 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 129591150 ps |
| CPU time | 7.18 seconds |
| Started | Jan 21 10:34:24 PM PST 24 |
| Finished | Jan 21 10:34:33 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-f981b43e-8210-4376-8426-eb0646422073 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3601506188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3601506188 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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