Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1698	1			T3	25		T9	4		T14	24
all_values[1]	1843	1			T3	21		T6	1		T7	3
all_values[2]	1810	1			T3	28		T6	2		T7	3
all_values[3]	1823	1			T3	37		T6	1		T7	2
all_values[4]	1800	1			T3	22		T6	1		T7	4
all_values[5]	1818	1			T3	38		T6	2		T7	6
all_values[6]	1758	1			T3	22		T6	3		T7	3
all_values[7]	1719	1			T3	41		T6	2		T7	4
all_values[8]	1775	1			T3	34		T6	1		T7	2
all_values[9]	1771	1			T3	33		T6	2		T9	4
all_values[10]	1781	1			T3	33		T6	1		T7	2
all_values[11]	1753	1			T3	33		T7	2		T14	31
all_values[12]	1823	1			T3	20		T6	1		T7	3
all_values[13]	1789	1			T3	26		T6	1		T7	3
all_values[14]	1718	1			T3	22		T7	1		T9	4
all_values[15]	1711	1			T3	25		T6	3		T7	3
all_values[16]	1796	1			T3	28		T6	4		T7	4
all_values[17]	1742	1			T3	18		T6	2		T7	2
all_values[18]	1770	1			T3	27		T6	1		T9	1
all_values[19]	1685	1			T3	26		T7	3		T9	2
all_values[20]	1803	1			T3	23		T6	1		T7	3
all_values[21]	1785	1			T3	26		T6	2		T7	3
all_values[22]	1820	1			T3	35		T6	2		T7	4
all_values[23]	1825	1			T3	27		T6	1		T7	4
all_values[24]	1814	1			T3	26		T6	2		T7	3
all_values[25]	1769	1			T3	36		T6	2		T7	4
all_values[26]	1809	1			T3	29		T6	4		T7	1
all_values[27]	1832	1			T3	26		T6	5		T7	3
all_values[28]	1736	1			T3	29		T6	2		T7	3
all_values[29]	1742	1			T3	19		T6	3		T7	4
all_values[30]	1851	1			T3	38		T6	2		T7	3
all_values[31]	1746	1			T3	32		T6	1		T7	1
all_values[32]	1748	1			T3	34		T6	1		T7	2
all_values[33]	1802	1			T3	24		T7	4		T9	2
all_values[34]	1784	1			T3	26		T6	2		T7	5
all_values[35]	1777	1			T3	41		T6	3		T7	1
all_values[36]	1703	1			T3	19		T6	1		T7	1
all_values[37]	1758	1			T3	28		T6	5		T7	1
all_values[38]	1739	1			T3	31		T7	5		T9	3
all_values[39]	1812	1			T3	27		T6	1		T7	1
all_values[40]	1755	1			T3	41		T6	1		T7	4
all_values[41]	1797	1			T3	27		T6	2		T7	1
all_values[42]	1780	1			T3	28		T6	1		T9	4
all_values[43]	1772	1			T3	26		T6	1		T9	2
all_values[44]	1819	1			T3	28		T6	1		T9	3
all_values[45]	1745	1			T3	17		T6	1		T7	3
all_values[46]	1784	1			T3	28		T6	2		T7	2
all_values[47]	1748	1			T3	36		T7	5		T9	4
all_values[48]	1784	1			T3	28		T6	2		T7	1
all_values[49]	1743	1			T3	26		T6	1		T7	2
all_values[50]	1702	1			T3	34		T6	1		T7	4
all_values[51]	1773	1			T3	24		T6	1		T7	5
all_values[52]	1740	1			T3	26		T6	2		T7	1
all_values[53]	1767	1			T3	31		T6	1		T7	3
all_values[54]	1861	1			T3	33		T6	4		T7	3
all_values[55]	1740	1			T3	27		T6	5		T7	2
all_values[56]	1823	1			T3	28		T6	3		T7	2
all_values[57]	1818	1			T3	34		T6	5		T7	1
all_values[58]	1778	1			T3	32		T6	3		T7	2
all_values[59]	1706	1			T3	30		T6	3		T9	2
all_values[60]	1758	1			T3	36		T6	3		T7	4
all_values[61]	1765	1			T3	30		T7	2		T9	5
all_values[62]	1741	1			T3	26		T6	3		T7	1
all_values[63]	1766	1			T3	23		T6	3		T7	3