Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1752	1			T1	2		T11	8		T12	5
all_values[1]	1702	1			T11	7		T12	4		T23	8
all_values[2]	1840	1			T1	1		T11	2		T12	2
all_values[3]	1770	1			T11	9		T12	5		T23	10
all_values[4]	1773	1			T11	5		T12	3		T23	14
all_values[5]	1703	1			T1	1		T11	6		T23	11
all_values[6]	1880	1			T1	1		T11	8		T12	4
all_values[7]	1745	1			T1	1		T11	9		T12	5
all_values[8]	1820	1			T1	1		T11	4		T12	1
all_values[9]	1704	1			T11	5		T12	4		T23	12
all_values[10]	1752	1			T1	1		T11	5		T12	2
all_values[11]	1765	1			T1	1		T11	4		T12	4
all_values[12]	1752	1			T1	1		T11	8		T12	6
all_values[13]	1756	1			T1	1		T11	6		T12	2
all_values[14]	1840	1			T1	1		T11	5		T12	2
all_values[15]	1735	1			T11	4		T12	4		T23	5
all_values[16]	1735	1			T1	1		T11	6		T12	1
all_values[17]	1784	1			T11	6		T12	5		T23	8
all_values[18]	1791	1			T11	3		T12	4		T23	8
all_values[19]	1784	1			T11	6		T12	3		T23	20
all_values[20]	1843	1			T1	1		T11	3		T12	6
all_values[21]	1776	1			T11	5		T12	6		T23	12
all_values[22]	1779	1			T11	4		T12	5		T23	13
all_values[23]	1780	1			T1	1		T11	3		T23	8
all_values[24]	1804	1			T11	5		T12	3		T23	6
all_values[25]	1807	1			T1	2		T11	7		T12	3
all_values[26]	1706	1			T11	5		T12	2		T23	9
all_values[27]	1843	1			T11	5		T12	5		T23	12
all_values[28]	1697	1			T1	1		T11	5		T12	4
all_values[29]	1737	1			T11	5		T12	4		T23	12
all_values[30]	1742	1			T1	1		T11	6		T23	8
all_values[31]	1691	1			T11	7		T12	2		T23	7
all_values[32]	1819	1			T1	1		T11	7		T12	5
all_values[33]	1731	1			T1	2		T11	7		T12	5
all_values[34]	1890	1			T11	10		T12	1		T23	8
all_values[35]	1755	1			T1	1		T11	6		T12	6
all_values[36]	1740	1			T11	5		T12	3		T23	11
all_values[37]	1803	1			T1	1		T11	3		T12	3
all_values[38]	1673	1			T1	1		T11	5		T12	4
all_values[39]	1742	1			T1	1		T11	5		T23	7
all_values[40]	1755	1			T11	5		T12	4		T23	12
all_values[41]	1865	1			T1	1		T11	10		T12	8
all_values[42]	1821	1			T11	7		T12	8		T23	11
all_values[43]	1742	1			T1	1		T11	4		T12	3
all_values[44]	1759	1			T11	6		T12	6		T23	7
all_values[45]	1736	1			T1	1		T11	5		T12	6
all_values[46]	1754	1			T1	1		T11	5		T12	5
all_values[47]	1728	1			T11	4		T23	13		T19	33
all_values[48]	1820	1			T1	1		T11	3		T12	3
all_values[49]	1791	1			T1	2		T11	3		T12	5
all_values[50]	1799	1			T11	5		T12	2		T23	3
all_values[51]	1683	1			T11	6		T12	5		T23	7
all_values[52]	1749	1			T1	1		T11	7		T12	1
all_values[53]	1804	1			T11	5		T12	4		T23	14
all_values[54]	1780	1			T11	8		T12	8		T23	10
all_values[55]	1831	1			T11	7		T12	3		T23	7
all_values[56]	1733	1			T1	1		T11	9		T12	1
all_values[57]	1719	1			T11	8		T12	5		T23	9
all_values[58]	1773	1			T1	1		T11	6		T12	1
all_values[59]	1731	1			T1	1		T11	5		T12	6
all_values[60]	1772	1			T1	2		T11	5		T12	3
all_values[61]	1870	1			T11	6		T12	1		T23	13
all_values[62]	1805	1			T11	7		T12	5		T23	8
all_values[63]	1727	1			T11	6		T12	1		T23	11