Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1839	1			T3	8		T21	2		T15	21
all_values[1]	1823	1			T3	6		T7	3		T15	11
all_values[2]	1916	1			T3	4		T7	1		T21	1
all_values[3]	1840	1			T3	13		T7	3		T21	1
all_values[4]	1833	1			T3	8		T7	1		T21	1
all_values[5]	1817	1			T3	6		T7	1		T21	1
all_values[6]	1779	1			T3	8		T7	1		T21	2
all_values[7]	1888	1			T3	6		T7	2		T21	3
all_values[8]	1882	1			T3	7		T7	2		T15	18
all_values[9]	1801	1			T3	6		T21	3		T15	16
all_values[10]	1783	1			T3	14		T21	1		T15	13
all_values[11]	1878	1			T3	5		T7	4		T21	2
all_values[12]	1846	1			T3	7		T7	1		T21	3
all_values[13]	1768	1			T3	6		T7	1		T15	12
all_values[14]	1871	1			T3	8		T21	2		T15	13
all_values[15]	1899	1			T3	6		T21	4		T15	14
all_values[16]	1880	1			T3	12		T15	12		T16	2
all_values[17]	1814	1			T3	6		T7	3		T15	15
all_values[18]	1753	1			T3	9		T7	3		T15	14
all_values[19]	1900	1			T3	9		T7	2		T21	2
all_values[20]	1905	1			T3	5		T7	2		T21	1
all_values[21]	1810	1			T3	4		T21	1		T15	16
all_values[22]	1881	1			T3	12		T7	1		T21	2
all_values[23]	1909	1			T3	11		T7	1		T21	2
all_values[24]	1786	1			T3	8		T7	1		T21	1
all_values[25]	1933	1			T3	12		T15	18		T16	1
all_values[26]	1850	1			T3	4		T7	2		T21	1
all_values[27]	1908	1			T3	8		T7	3		T15	12
all_values[28]	1828	1			T3	7		T7	1		T15	12
all_values[29]	1808	1			T3	5		T7	1		T15	12
all_values[30]	1825	1			T3	4		T21	2		T15	13
all_values[31]	1902	1			T3	7		T7	2		T15	15
all_values[32]	1792	1			T3	9		T7	5		T15	16
all_values[33]	1866	1			T3	4		T7	1		T21	1
all_values[34]	1798	1			T3	8		T7	2		T21	2
all_values[35]	1824	1			T3	5		T7	1		T21	4
all_values[36]	1771	1			T3	7		T7	1		T21	2
all_values[37]	1914	1			T3	5		T7	1		T15	19
all_values[38]	1796	1			T3	8		T21	1		T15	23
all_values[39]	1873	1			T3	8		T7	2		T21	2
all_values[40]	1815	1			T3	11		T7	1		T21	1
all_values[41]	1894	1			T3	6		T7	3		T21	1
all_values[42]	1835	1			T3	7		T7	5		T21	1
all_values[43]	1860	1			T3	3		T7	1		T21	1
all_values[44]	1839	1			T3	6		T21	1		T15	21
all_values[45]	1869	1			T3	6		T7	1		T21	1
all_values[46]	1891	1			T3	5		T7	1		T21	1
all_values[47]	1893	1			T3	7		T21	2		T15	15
all_values[48]	1819	1			T3	7		T7	2		T15	17
all_values[49]	1841	1			T3	12		T7	1		T15	13
all_values[50]	1838	1			T3	4		T7	2		T21	1
all_values[51]	1825	1			T3	8		T7	3		T21	1
all_values[52]	1898	1			T3	5		T7	2		T15	18
all_values[53]	1798	1			T3	4		T7	2		T21	1
all_values[54]	1817	1			T3	6		T15	17		T16	4
all_values[55]	1880	1			T3	7		T7	2		T15	13
all_values[56]	1787	1			T3	9		T7	1		T21	2
all_values[57]	1889	1			T3	3		T7	1		T21	7
all_values[58]	1942	1			T3	5		T7	1		T21	1
all_values[59]	1920	1			T3	3		T7	3		T21	3
all_values[60]	1811	1			T3	2		T7	2		T15	12
all_values[61]	1856	1			T3	11		T15	18		T16	1
all_values[62]	1812	1			T3	7		T7	1		T21	2
all_values[63]	1820	1			T3	4		T7	2		T21	1