| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.20 | 99.26 | 90.04 | 98.80 | 95.82 | 99.26 | 100.00 |
| T760 | /workspace/coverage/xbar_build_mode/28.xbar_same_source.4261777422 | Feb 07 03:44:07 PM PST 24 | Feb 07 03:44:14 PM PST 24 | 561076091 ps | ||
| T761 | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1645605860 | Feb 07 03:41:11 PM PST 24 | Feb 07 03:42:52 PM PST 24 | 31581387210 ps | ||
| T63 | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1726810372 | Feb 07 03:40:09 PM PST 24 | Feb 07 03:48:58 PM PST 24 | 211041034934 ps | ||
| T762 | /workspace/coverage/xbar_build_mode/16.xbar_random.1121829706 | Feb 07 03:41:33 PM PST 24 | Feb 07 03:42:00 PM PST 24 | 260800359 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1561387591 | Feb 07 03:43:08 PM PST 24 | Feb 07 03:43:21 PM PST 24 | 86858489 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2664682314 | Feb 07 03:40:17 PM PST 24 | Feb 07 03:40:58 PM PST 24 | 335447409 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2060522262 | Feb 07 03:43:17 PM PST 24 | Feb 07 03:47:41 PM PST 24 | 71454256460 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3362524266 | Feb 07 03:37:41 PM PST 24 | Feb 07 03:38:15 PM PST 24 | 8993345631 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1814065532 | Feb 07 03:45:08 PM PST 24 | Feb 07 03:45:34 PM PST 24 | 4348835443 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2961450908 | Feb 07 03:46:55 PM PST 24 | Feb 07 03:50:39 PM PST 24 | 49644349748 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.974232183 | Feb 07 03:46:27 PM PST 24 | Feb 07 03:50:01 PM PST 24 | 24529958688 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.151605457 | Feb 07 03:44:47 PM PST 24 | Feb 07 03:45:08 PM PST 24 | 4068379149 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/28.xbar_random.2937544515 | Feb 07 03:44:00 PM PST 24 | Feb 07 03:44:11 PM PST 24 | 288332662 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/47.xbar_error_random.2414394836 | Feb 07 03:47:09 PM PST 24 | Feb 07 03:47:12 PM PST 24 | 63328493 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/42.xbar_random.544699463 | Feb 07 03:46:20 PM PST 24 | Feb 07 03:46:39 PM PST 24 | 114697551 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/5.xbar_same_source.2829700570 | Feb 07 03:38:54 PM PST 24 | Feb 07 03:39:05 PM PST 24 | 578126401 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3712943011 | Feb 07 03:38:29 PM PST 24 | Feb 07 03:40:01 PM PST 24 | 16574329518 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1169959483 | Feb 07 03:38:03 PM PST 24 | Feb 07 03:38:07 PM PST 24 | 131912379 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1895989709 | Feb 07 03:43:08 PM PST 24 | Feb 07 03:43:12 PM PST 24 | 25888823 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3687566676 | Feb 07 03:41:00 PM PST 24 | Feb 07 03:42:16 PM PST 24 | 871362974 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/11.xbar_same_source.1031307058 | Feb 07 03:40:33 PM PST 24 | Feb 07 03:40:49 PM PST 24 | 1120480747 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1518459762 | Feb 07 03:37:17 PM PST 24 | Feb 07 03:38:49 PM PST 24 | 14627943815 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1117155076 | Feb 07 03:42:05 PM PST 24 | Feb 07 03:45:22 PM PST 24 | 79087913259 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.416109796 | Feb 07 03:44:33 PM PST 24 | Feb 07 03:45:11 PM PST 24 | 8088054410 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.657156586 | Feb 07 03:41:18 PM PST 24 | Feb 07 03:43:10 PM PST 24 | 353744689 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2121398255 | Feb 07 03:38:42 PM PST 24 | Feb 07 03:38:45 PM PST 24 | 61351718 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/49.xbar_random.3783433676 | Feb 07 03:47:22 PM PST 24 | Feb 07 03:47:47 PM PST 24 | 242255332 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/33.xbar_same_source.2580945192 | Feb 07 03:45:02 PM PST 24 | Feb 07 03:45:08 PM PST 24 | 186032675 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3440745302 | Feb 07 03:37:08 PM PST 24 | Feb 07 03:43:21 PM PST 24 | 4644279927 ps | ||
| T133 | /workspace/coverage/xbar_build_mode/2.xbar_smoke.2238200680 | Feb 07 03:37:36 PM PST 24 | Feb 07 03:37:40 PM PST 24 | 117516249 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1595006162 | Feb 07 03:40:57 PM PST 24 | Feb 07 03:45:33 PM PST 24 | 1274568400 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1909802981 | Feb 07 03:45:08 PM PST 24 | Feb 07 03:47:47 PM PST 24 | 1095882822 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3873217666 | Feb 07 03:46:30 PM PST 24 | Feb 07 03:54:08 PM PST 24 | 49993934595 ps | ||
| T127 | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.6744191 | Feb 07 03:45:10 PM PST 24 | Feb 07 03:49:40 PM PST 24 | 7935950595 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1456004733 | Feb 07 03:40:31 PM PST 24 | Feb 07 03:40:52 PM PST 24 | 565943260 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2138402060 | Feb 07 03:37:20 PM PST 24 | Feb 07 03:37:41 PM PST 24 | 269338689 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/27.xbar_same_source.3206814387 | Feb 07 03:43:53 PM PST 24 | Feb 07 03:44:22 PM PST 24 | 1423440385 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2668984730 | Feb 07 03:47:08 PM PST 24 | Feb 07 03:50:19 PM PST 24 | 42349243810 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3436768443 | Feb 07 03:44:09 PM PST 24 | Feb 07 03:46:29 PM PST 24 | 24812307622 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.652133568 | Feb 07 03:43:27 PM PST 24 | Feb 07 03:45:15 PM PST 24 | 6553579515 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2353220687 | Feb 07 03:44:18 PM PST 24 | Feb 07 03:45:52 PM PST 24 | 10023344487 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.4182793047 | Feb 07 03:46:10 PM PST 24 | Feb 07 03:48:27 PM PST 24 | 2201633002 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.1638391449 | Feb 07 03:43:18 PM PST 24 | Feb 07 03:47:20 PM PST 24 | 11391008424 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2967431519 | Feb 07 03:44:40 PM PST 24 | Feb 07 03:45:11 PM PST 24 | 6500888418 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1931801548 | Feb 07 03:41:12 PM PST 24 | Feb 07 03:41:31 PM PST 24 | 185415653 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2943606818 | Feb 07 03:44:34 PM PST 24 | Feb 07 03:48:37 PM PST 24 | 77844458468 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2726073814 | Feb 07 03:47:21 PM PST 24 | Feb 07 03:47:48 PM PST 24 | 921269772 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.700628125 | Feb 07 03:42:13 PM PST 24 | Feb 07 03:42:46 PM PST 24 | 4094946486 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2257293300 | Feb 07 03:41:36 PM PST 24 | Feb 07 03:50:25 PM PST 24 | 14617538168 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/33.xbar_random.3082732041 | Feb 07 03:44:57 PM PST 24 | Feb 07 03:45:30 PM PST 24 | 1185183367 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1912233443 | Feb 07 03:42:05 PM PST 24 | Feb 07 03:42:08 PM PST 24 | 35736503 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.317500530 | Feb 07 03:45:19 PM PST 24 | Feb 07 03:45:28 PM PST 24 | 78803234 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3819264103 | Feb 07 03:43:08 PM PST 24 | Feb 07 03:43:11 PM PST 24 | 233833377 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2143031112 | Feb 07 03:42:18 PM PST 24 | Feb 07 03:42:51 PM PST 24 | 876358261 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1756513524 | Feb 07 03:41:19 PM PST 24 | Feb 07 03:48:26 PM PST 24 | 46883450974 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.349157333 | Feb 07 03:43:58 PM PST 24 | Feb 07 03:44:26 PM PST 24 | 6624553758 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.3177104632 | Feb 07 03:44:12 PM PST 24 | Feb 07 03:44:52 PM PST 24 | 299262070 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2781791255 | Feb 07 03:39:15 PM PST 24 | Feb 07 03:39:35 PM PST 24 | 338882504 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3688359511 | Feb 07 03:43:26 PM PST 24 | Feb 07 03:44:04 PM PST 24 | 214844248 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3163272503 | Feb 07 03:47:19 PM PST 24 | Feb 07 03:47:33 PM PST 24 | 443679650 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.803381255 | Feb 07 03:40:39 PM PST 24 | Feb 07 03:44:01 PM PST 24 | 14323506985 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1860195267 | Feb 07 03:46:44 PM PST 24 | Feb 07 03:48:53 PM PST 24 | 20682851257 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1464367846 | Feb 07 03:41:19 PM PST 24 | Feb 07 03:41:42 PM PST 24 | 2364463626 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3116296308 | Feb 07 03:45:18 PM PST 24 | Feb 07 03:48:49 PM PST 24 | 32961740016 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.436911957 | Feb 07 03:46:59 PM PST 24 | Feb 07 03:49:35 PM PST 24 | 14888963515 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1325536643 | Feb 07 03:43:06 PM PST 24 | Feb 07 03:44:35 PM PST 24 | 17395717565 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.4233908362 | Feb 07 03:46:30 PM PST 24 | Feb 07 03:46:34 PM PST 24 | 39688739 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4126368903 | Feb 07 03:43:05 PM PST 24 | Feb 07 03:43:08 PM PST 24 | 15139075 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2143983280 | Feb 07 03:45:10 PM PST 24 | Feb 07 03:45:13 PM PST 24 | 65294150 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2066950058 | Feb 07 03:47:21 PM PST 24 | Feb 07 03:50:18 PM PST 24 | 53191228886 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.3442504788 | Feb 07 03:40:34 PM PST 24 | Feb 07 03:40:47 PM PST 24 | 141430593 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/48.xbar_error_random.4023423876 | Feb 07 03:47:16 PM PST 24 | Feb 07 03:47:43 PM PST 24 | 818932992 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3312569732 | Feb 07 03:44:04 PM PST 24 | Feb 07 03:49:55 PM PST 24 | 6773855737 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1085684485 | Feb 07 03:39:43 PM PST 24 | Feb 07 03:40:15 PM PST 24 | 293478957 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/39.xbar_random.718047519 | Feb 07 03:45:55 PM PST 24 | Feb 07 03:46:01 PM PST 24 | 318614206 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1242555543 | Feb 07 03:40:10 PM PST 24 | Feb 07 03:41:11 PM PST 24 | 138226647 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/11.xbar_error_random.61687304 | Feb 07 03:40:34 PM PST 24 | Feb 07 03:40:41 PM PST 24 | 223899977 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3031404088 | Feb 07 03:40:32 PM PST 24 | Feb 07 03:41:04 PM PST 24 | 4401902433 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1242545572 | Feb 07 03:39:54 PM PST 24 | Feb 07 03:40:21 PM PST 24 | 4148376660 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3039670025 | Feb 07 03:43:06 PM PST 24 | Feb 07 03:46:37 PM PST 24 | 1628782707 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/21.xbar_smoke.460012549 | Feb 07 03:42:39 PM PST 24 | Feb 07 03:42:42 PM PST 24 | 80381224 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.718092128 | Feb 07 03:42:15 PM PST 24 | Feb 07 03:43:35 PM PST 24 | 212688617 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.543216727 | Feb 07 03:39:35 PM PST 24 | Feb 07 03:40:15 PM PST 24 | 1157595035 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2269525539 | Feb 07 03:41:36 PM PST 24 | Feb 07 03:41:57 PM PST 24 | 1174137102 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/38.xbar_error_random.551222494 | Feb 07 03:45:56 PM PST 24 | Feb 07 03:46:01 PM PST 24 | 89979627 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/31.xbar_error_random.260352808 | Feb 07 03:44:42 PM PST 24 | Feb 07 03:44:53 PM PST 24 | 661028189 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/30.xbar_error_random.1739761360 | Feb 07 03:44:32 PM PST 24 | Feb 07 03:44:35 PM PST 24 | 31418335 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.3446806837 | Feb 07 03:39:49 PM PST 24 | Feb 07 03:40:48 PM PST 24 | 3303636753 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1148401990 | Feb 07 03:42:21 PM PST 24 | Feb 07 03:42:30 PM PST 24 | 166601145 ps | ||
| T238 | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1839336860 | Feb 07 03:45:03 PM PST 24 | Feb 07 03:47:59 PM PST 24 | 41149996840 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1754811598 | Feb 07 03:41:18 PM PST 24 | Feb 07 03:43:07 PM PST 24 | 950395359 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1785448979 | Feb 07 03:47:13 PM PST 24 | Feb 07 03:47:34 PM PST 24 | 2029984121 ps | ||
| T215 | /workspace/coverage/xbar_build_mode/29.xbar_random.1206222425 | Feb 07 03:44:17 PM PST 24 | Feb 07 03:44:25 PM PST 24 | 329360893 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/40.xbar_smoke.3312027095 | Feb 07 03:46:02 PM PST 24 | Feb 07 03:46:06 PM PST 24 | 570150098 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2927240573 | Feb 07 03:43:55 PM PST 24 | Feb 07 03:44:55 PM PST 24 | 8910015952 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/14.xbar_same_source.223191450 | Feb 07 03:41:15 PM PST 24 | Feb 07 03:41:23 PM PST 24 | 318329443 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/22.xbar_same_source.1487165860 | Feb 07 03:42:51 PM PST 24 | Feb 07 03:43:24 PM PST 24 | 2104491904 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2898040739 | Feb 07 03:38:47 PM PST 24 | Feb 07 03:39:27 PM PST 24 | 5826489926 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2912953803 | Feb 07 03:42:30 PM PST 24 | Feb 07 03:42:40 PM PST 24 | 527702306 ps | ||
| T128 | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.565404643 | Feb 07 03:39:33 PM PST 24 | Feb 07 03:44:34 PM PST 24 | 17617490728 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.362934001 | Feb 07 03:44:50 PM PST 24 | Feb 07 03:46:42 PM PST 24 | 364408296 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1672680628 | Feb 07 03:41:38 PM PST 24 | Feb 07 03:42:08 PM PST 24 | 4339019546 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/0.xbar_smoke.33774968 | Feb 07 03:37:07 PM PST 24 | Feb 07 03:37:10 PM PST 24 | 24872515 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3782128484 | Feb 07 03:42:38 PM PST 24 | Feb 07 03:45:33 PM PST 24 | 66371210085 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1329462611 | Feb 07 03:46:02 PM PST 24 | Feb 07 03:46:44 PM PST 24 | 5601544174 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.2510296235 | Feb 07 03:45:04 PM PST 24 | Feb 07 03:48:32 PM PST 24 | 33107419516 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3335952694 | Feb 07 03:45:44 PM PST 24 | Feb 07 03:45:56 PM PST 24 | 266173015 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2522598273 | Feb 07 03:39:03 PM PST 24 | Feb 07 03:39:06 PM PST 24 | 29191615 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/44.xbar_smoke.1056827078 | Feb 07 03:46:37 PM PST 24 | Feb 07 03:46:43 PM PST 24 | 263912224 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1730970222 | Feb 07 03:44:05 PM PST 24 | Feb 07 03:46:00 PM PST 24 | 1209080084 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3517947443 | Feb 07 03:42:20 PM PST 24 | Feb 07 03:44:29 PM PST 24 | 25965948522 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/44.xbar_error_random.2130510339 | Feb 07 03:46:39 PM PST 24 | Feb 07 03:46:44 PM PST 24 | 54015276 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.323541231 | Feb 07 03:40:11 PM PST 24 | Feb 07 03:40:27 PM PST 24 | 2897455979 ps | ||
| T28 | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.2025295651 | Feb 07 03:41:40 PM PST 24 | Feb 07 03:44:06 PM PST 24 | 763978083 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/7.xbar_smoke.1107843430 | Feb 07 03:39:31 PM PST 24 | Feb 07 03:39:37 PM PST 24 | 179578495 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/16.xbar_same_source.1528110961 | Feb 07 03:41:39 PM PST 24 | Feb 07 03:42:08 PM PST 24 | 1906341875 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.4218176398 | Feb 07 03:42:05 PM PST 24 | Feb 07 03:42:30 PM PST 24 | 257584931 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2526476205 | Feb 07 03:46:10 PM PST 24 | Feb 07 03:46:45 PM PST 24 | 381070207 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/48.xbar_smoke.1319296885 | Feb 07 03:47:12 PM PST 24 | Feb 07 03:47:16 PM PST 24 | 133931615 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/19.xbar_same_source.3546238816 | Feb 07 03:42:21 PM PST 24 | Feb 07 03:42:29 PM PST 24 | 378191453 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3789402235 | Feb 07 03:41:56 PM PST 24 | Feb 07 03:44:34 PM PST 24 | 2256428501 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2600478887 | Feb 07 03:44:50 PM PST 24 | Feb 07 03:49:33 PM PST 24 | 1295437684 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1605298193 | Feb 07 03:43:30 PM PST 24 | Feb 07 03:44:05 PM PST 24 | 9163357155 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2804738741 | Feb 07 03:42:13 PM PST 24 | Feb 07 03:42:45 PM PST 24 | 15671602096 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1577411286 | Feb 07 03:42:28 PM PST 24 | Feb 07 03:46:58 PM PST 24 | 1836983893 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3151880713 | Feb 07 03:42:47 PM PST 24 | Feb 07 03:42:50 PM PST 24 | 18028008 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3927520041 | Feb 07 03:38:10 PM PST 24 | Feb 07 03:38:39 PM PST 24 | 5079165526 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3838845155 | Feb 07 03:42:47 PM PST 24 | Feb 07 03:43:01 PM PST 24 | 133293759 ps | ||
| T235 | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.302872486 | Feb 07 03:41:16 PM PST 24 | Feb 07 03:41:34 PM PST 24 | 332145294 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1939002949 | Feb 07 03:42:14 PM PST 24 | Feb 07 03:42:22 PM PST 24 | 320434980 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3604104455 | Feb 07 03:41:12 PM PST 24 | Feb 07 03:41:15 PM PST 24 | 130374431 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1868657804 | Feb 07 03:44:31 PM PST 24 | Feb 07 03:44:39 PM PST 24 | 53877006 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.605848718 | Feb 07 03:44:01 PM PST 24 | Feb 07 03:50:26 PM PST 24 | 6198348694 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1829935849 | Feb 07 03:37:11 PM PST 24 | Feb 07 03:37:13 PM PST 24 | 35489918 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3428029171 | Feb 07 03:46:38 PM PST 24 | Feb 07 03:51:26 PM PST 24 | 2938904708 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/12.xbar_same_source.392358962 | Feb 07 03:40:48 PM PST 24 | Feb 07 03:41:17 PM PST 24 | 3520628358 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/32.xbar_error_random.3403046374 | Feb 07 03:44:48 PM PST 24 | Feb 07 03:45:11 PM PST 24 | 779141627 ps | ||
| T132 | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1324267487 | Feb 07 03:46:25 PM PST 24 | Feb 07 03:51:33 PM PST 24 | 8533272316 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2481257336 | Feb 07 03:40:16 PM PST 24 | Feb 07 03:40:54 PM PST 24 | 28083280866 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/10.xbar_smoke.883295191 | Feb 07 03:40:19 PM PST 24 | Feb 07 03:40:23 PM PST 24 | 123875506 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.427413494 | Feb 07 03:41:17 PM PST 24 | Feb 07 03:42:58 PM PST 24 | 338656087 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1642760126 | Feb 07 03:40:09 PM PST 24 | Feb 07 03:40:18 PM PST 24 | 75509904 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.673357699 | Feb 07 03:46:10 PM PST 24 | Feb 07 03:46:58 PM PST 24 | 1852999527 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.4074234357 | Feb 07 03:47:19 PM PST 24 | Feb 07 03:48:14 PM PST 24 | 31850879576 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/14.xbar_smoke.647145737 | Feb 07 03:41:13 PM PST 24 | Feb 07 03:41:17 PM PST 24 | 167564144 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/24.xbar_smoke.1482071636 | Feb 07 03:43:18 PM PST 24 | Feb 07 03:43:22 PM PST 24 | 113936775 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1122872949 | Feb 07 03:44:33 PM PST 24 | Feb 07 03:45:12 PM PST 24 | 238664189 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/12.xbar_smoke.858132181 | Feb 07 03:40:44 PM PST 24 | Feb 07 03:40:48 PM PST 24 | 128333826 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.4261083919 | Feb 07 03:40:58 PM PST 24 | Feb 07 03:41:25 PM PST 24 | 3873534925 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/13.xbar_same_source.4190022 | Feb 07 03:41:08 PM PST 24 | Feb 07 03:41:38 PM PST 24 | 1285996717 ps |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.2062144901 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3621151777 ps |
| CPU time | 160.82 seconds |
| Started | Feb 07 03:47:25 PM PST 24 |
| Finished | Feb 07 03:50:06 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-85bebc90-09ed-4e7d-869d-e9b2fb278636 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2062144901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2062144901 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1591459264 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 245967632717 ps |
| CPU time | 757.17 seconds |
| Started | Feb 07 03:44:02 PM PST 24 |
| Finished | Feb 07 03:56:40 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-c0f7ca0e-c03f-4365-82de-2052edffd41c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1591459264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.1591459264 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1206375760 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 241195849181 ps |
| CPU time | 740.61 seconds |
| Started | Feb 07 03:40:19 PM PST 24 |
| Finished | Feb 07 03:52:40 PM PST 24 |
| Peak memory | 207384 kb |
| Host | smart-674f92b5-cf18-41ec-897e-5350def39075 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1206375760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.1206375760 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.4060891193 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2416297579 ps |
| CPU time | 163.58 seconds |
| Started | Feb 07 03:46:37 PM PST 24 |
| Finished | Feb 07 03:49:23 PM PST 24 |
| Peak memory | 209580 kb |
| Host | smart-920e001c-77ce-480f-bf9d-0865cc99cea5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4060891193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.4060891193 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.2298093637 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 76971647962 ps |
| CPU time | 591.58 seconds |
| Started | Feb 07 03:42:49 PM PST 24 |
| Finished | Feb 07 03:52:41 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-a43e3fdb-302a-4098-9151-50ed96514bea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2298093637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.2298093637 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.141052886 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 15324025837 ps |
| CPU time | 897.61 seconds |
| Started | Feb 07 03:44:19 PM PST 24 |
| Finished | Feb 07 03:59:17 PM PST 24 |
| Peak memory | 219876 kb |
| Host | smart-ed2ee433-17d1-46d2-bbc6-48368e69b9ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=141052886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand _reset.141052886 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2639071609 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 374868374 ps |
| CPU time | 32.89 seconds |
| Started | Feb 07 03:37:11 PM PST 24 |
| Finished | Feb 07 03:37:44 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-9ffef37b-12ab-407f-890f-28f3e1df57b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639071609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2639071609 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1872881654 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 130406625508 ps |
| CPU time | 553.56 seconds |
| Started | Feb 07 03:39:20 PM PST 24 |
| Finished | Feb 07 03:48:34 PM PST 24 |
| Peak memory | 207060 kb |
| Host | smart-453d5a69-db4e-4670-9c21-517c3acf44a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1872881654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.1872881654 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2422167423 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 44646178146 ps |
| CPU time | 250.28 seconds |
| Started | Feb 07 03:38:05 PM PST 24 |
| Finished | Feb 07 03:42:16 PM PST 24 |
| Peak memory | 204756 kb |
| Host | smart-e943bffb-a5f5-4c38-b144-12d44013ed58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422167423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2422167423 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.2205307793 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 9423668794 ps |
| CPU time | 533.48 seconds |
| Started | Feb 07 03:43:09 PM PST 24 |
| Finished | Feb 07 03:52:04 PM PST 24 |
| Peak memory | 221348 kb |
| Host | smart-fecf06e0-f635-43b5-a039-e7c949998fb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2205307793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.2205307793 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1668256342 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3234683738 ps |
| CPU time | 714.86 seconds |
| Started | Feb 07 03:45:46 PM PST 24 |
| Finished | Feb 07 03:57:42 PM PST 24 |
| Peak memory | 224204 kb |
| Host | smart-bca2aa00-c536-4c51-a989-c8f7762d514f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1668256342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.1668256342 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.481353663 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 44277141443 ps |
| CPU time | 397.97 seconds |
| Started | Feb 07 03:40:15 PM PST 24 |
| Finished | Feb 07 03:46:53 PM PST 24 |
| Peak memory | 207264 kb |
| Host | smart-1996e514-9325-4e50-9021-49f502cd9a11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=481353663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.481353663 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2028746392 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 959811227 ps |
| CPU time | 236.97 seconds |
| Started | Feb 07 03:43:17 PM PST 24 |
| Finished | Feb 07 03:47:15 PM PST 24 |
| Peak memory | 211700 kb |
| Host | smart-58ef83b1-c285-415d-a526-1f4ff5cc6697 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2028746392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.2028746392 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3086625507 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1536001289 ps |
| CPU time | 430.61 seconds |
| Started | Feb 07 03:43:58 PM PST 24 |
| Finished | Feb 07 03:51:09 PM PST 24 |
| Peak memory | 211596 kb |
| Host | smart-239c884c-b178-4d33-aaca-4cc80b94f8d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3086625507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.3086625507 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2265253457 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 93665807065 ps |
| CPU time | 549.39 seconds |
| Started | Feb 07 03:43:36 PM PST 24 |
| Finished | Feb 07 03:52:46 PM PST 24 |
| Peak memory | 211588 kb |
| Host | smart-c50430c4-179c-439d-bb63-65910d4c58f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2265253457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.2265253457 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.2025295651 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 763978083 ps |
| CPU time | 145.86 seconds |
| Started | Feb 07 03:41:40 PM PST 24 |
| Finished | Feb 07 03:44:06 PM PST 24 |
| Peak memory | 208212 kb |
| Host | smart-535bb17d-2281-4b96-b139-68403f2feec0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2025295651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.2025295651 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3064974674 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2577537105 ps |
| CPU time | 105.23 seconds |
| Started | Feb 07 03:37:21 PM PST 24 |
| Finished | Feb 07 03:39:07 PM PST 24 |
| Peak memory | 209024 kb |
| Host | smart-26e36d82-de66-47d4-b20a-6da21725dde9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3064974674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3064974674 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3354296544 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1075320500 ps |
| CPU time | 362.44 seconds |
| Started | Feb 07 03:40:32 PM PST 24 |
| Finished | Feb 07 03:46:35 PM PST 24 |
| Peak memory | 209464 kb |
| Host | smart-1eb00e11-04a5-4dc6-9710-00fea20bb927 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3354296544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.3354296544 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1160157455 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11680742330 ps |
| CPU time | 31.39 seconds |
| Started | Feb 07 03:40:47 PM PST 24 |
| Finished | Feb 07 03:41:19 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-a6b0fb0b-733a-4466-b7ce-f4f5346d7f25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1160157455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1160157455 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.703052279 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 55845318834 ps |
| CPU time | 547.88 seconds |
| Started | Feb 07 03:37:11 PM PST 24 |
| Finished | Feb 07 03:46:19 PM PST 24 |
| Peak memory | 205896 kb |
| Host | smart-1663bee9-3b0a-48e0-b97e-d90459f6d5c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=703052279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow _rsp.703052279 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.2455853593 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1015284086 ps |
| CPU time | 12.35 seconds |
| Started | Feb 07 03:37:12 PM PST 24 |
| Finished | Feb 07 03:37:25 PM PST 24 |
| Peak memory | 203340 kb |
| Host | smart-60f2179d-7c72-4a1b-a8b2-233babfb0b4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2455853593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.2455853593 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.30230893 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 104847716 ps |
| CPU time | 4.26 seconds |
| Started | Feb 07 03:37:12 PM PST 24 |
| Finished | Feb 07 03:37:17 PM PST 24 |
| Peak memory | 203276 kb |
| Host | smart-fb8c7e0f-72af-4a2b-b203-69e232a905ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=30230893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.30230893 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.1515381532 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 218172696 ps |
| CPU time | 4.3 seconds |
| Started | Feb 07 03:37:07 PM PST 24 |
| Finished | Feb 07 03:37:12 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-b4235ac0-02d1-4420-803e-9d49e34b87c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1515381532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1515381532 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.2106084284 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 34812956337 ps |
| CPU time | 117.88 seconds |
| Started | Feb 07 03:37:10 PM PST 24 |
| Finished | Feb 07 03:39:09 PM PST 24 |
| Peak memory | 204696 kb |
| Host | smart-d4b9c50b-de75-489d-bf41-2e5dc0ba3f86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106084284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2106084284 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2642773566 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 20944234686 ps |
| CPU time | 152.6 seconds |
| Started | Feb 07 03:37:21 PM PST 24 |
| Finished | Feb 07 03:39:54 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-61c99a6e-0048-405b-89a9-a10c89e4f596 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2642773566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2642773566 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1295231503 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 64679857 ps |
| CPU time | 6.64 seconds |
| Started | Feb 07 03:37:09 PM PST 24 |
| Finished | Feb 07 03:37:16 PM PST 24 |
| Peak memory | 204552 kb |
| Host | smart-e7d5553e-45b7-4ee3-b329-7f62ff8499eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295231503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1295231503 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2755717243 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1654185636 ps |
| CPU time | 9.73 seconds |
| Started | Feb 07 03:37:08 PM PST 24 |
| Finished | Feb 07 03:37:18 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-c4e2982d-425e-4968-ad5a-2edbdc65f3f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2755717243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2755717243 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.33774968 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 24872515 ps |
| CPU time | 2.19 seconds |
| Started | Feb 07 03:37:07 PM PST 24 |
| Finished | Feb 07 03:37:10 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-c9ae922d-8366-4300-b1d5-4f942183e47e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=33774968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.33774968 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1249897071 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5044127076 ps |
| CPU time | 28.35 seconds |
| Started | Feb 07 03:37:06 PM PST 24 |
| Finished | Feb 07 03:37:35 PM PST 24 |
| Peak memory | 203524 kb |
| Host | smart-39fd2de5-fb0e-47bf-bed5-6a5df30083bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249897071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1249897071 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2666614514 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 6875594871 ps |
| CPU time | 30.83 seconds |
| Started | Feb 07 03:37:21 PM PST 24 |
| Finished | Feb 07 03:37:52 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-5c774744-4157-4c92-a4f2-d6b4fd82d90b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2666614514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2666614514 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.94831177 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 40710416 ps |
| CPU time | 2.55 seconds |
| Started | Feb 07 03:37:07 PM PST 24 |
| Finished | Feb 07 03:37:10 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-9b102605-18d3-48c8-b534-57af4e5a2df2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94831177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.94831177 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.396959462 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 8558989154 ps |
| CPU time | 282.38 seconds |
| Started | Feb 07 03:37:21 PM PST 24 |
| Finished | Feb 07 03:42:04 PM PST 24 |
| Peak memory | 211436 kb |
| Host | smart-e24a5f7e-6800-476c-9e1d-7e780236cf69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=396959462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.396959462 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3102176570 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 6645145506 ps |
| CPU time | 119.24 seconds |
| Started | Feb 07 03:37:21 PM PST 24 |
| Finished | Feb 07 03:39:20 PM PST 24 |
| Peak memory | 208032 kb |
| Host | smart-77dddebc-b900-4542-8550-dba16fa31b94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3102176570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3102176570 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3440745302 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4644279927 ps |
| CPU time | 372.31 seconds |
| Started | Feb 07 03:37:08 PM PST 24 |
| Finished | Feb 07 03:43:21 PM PST 24 |
| Peak memory | 209504 kb |
| Host | smart-eb09402c-613e-4a1f-8f7e-852e507fa640 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440745302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.3440745302 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2267292670 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 567352169 ps |
| CPU time | 9.35 seconds |
| Started | Feb 07 03:37:08 PM PST 24 |
| Finished | Feb 07 03:37:17 PM PST 24 |
| Peak memory | 211564 kb |
| Host | smart-b57c79d4-0c1a-4f62-a2db-990da76b39ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2267292670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2267292670 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2484784627 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1201849036 ps |
| CPU time | 15.58 seconds |
| Started | Feb 07 03:37:18 PM PST 24 |
| Finished | Feb 07 03:37:34 PM PST 24 |
| Peak memory | 205272 kb |
| Host | smart-25a7cdb0-7669-45cd-90f0-366184d9b3a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2484784627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2484784627 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1518459762 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 14627943815 ps |
| CPU time | 91.44 seconds |
| Started | Feb 07 03:37:17 PM PST 24 |
| Finished | Feb 07 03:38:49 PM PST 24 |
| Peak memory | 211640 kb |
| Host | smart-6dc611d2-ff50-4947-bc72-7802721fb252 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1518459762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.1518459762 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3635618361 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 77081415 ps |
| CPU time | 10.23 seconds |
| Started | Feb 07 03:37:36 PM PST 24 |
| Finished | Feb 07 03:37:48 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-f40b8898-b0be-47c9-a473-31018bb3044a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3635618361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3635618361 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.313667219 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 51057668 ps |
| CPU time | 4.79 seconds |
| Started | Feb 07 03:37:18 PM PST 24 |
| Finished | Feb 07 03:37:24 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-23a760de-eec5-443b-8f19-1aa7c94cbdda |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=313667219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.313667219 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.2933635649 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 128035211 ps |
| CPU time | 19.73 seconds |
| Started | Feb 07 03:37:21 PM PST 24 |
| Finished | Feb 07 03:37:41 PM PST 24 |
| Peak memory | 204732 kb |
| Host | smart-ca3598fb-5314-49b6-9559-8e338c10ac7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2933635649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2933635649 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2463693301 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 96255925568 ps |
| CPU time | 170.17 seconds |
| Started | Feb 07 03:37:09 PM PST 24 |
| Finished | Feb 07 03:39:59 PM PST 24 |
| Peak memory | 211700 kb |
| Host | smart-b7f5c20e-b74e-4c3b-a850-2aceec91503b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463693301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2463693301 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3242018716 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 14460287480 ps |
| CPU time | 79.1 seconds |
| Started | Feb 07 03:37:17 PM PST 24 |
| Finished | Feb 07 03:38:37 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-1d8faf16-adca-4719-a1ee-ad86fec7baaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3242018716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3242018716 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2138402060 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 269338689 ps |
| CPU time | 20.8 seconds |
| Started | Feb 07 03:37:20 PM PST 24 |
| Finished | Feb 07 03:37:41 PM PST 24 |
| Peak memory | 204424 kb |
| Host | smart-383eebd4-810d-4e34-ab9d-3d90b3f65d42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138402060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2138402060 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2863548664 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 601437612 ps |
| CPU time | 16.21 seconds |
| Started | Feb 07 03:37:12 PM PST 24 |
| Finished | Feb 07 03:37:29 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-4e3d2790-013a-404c-880f-5c3f69939750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2863548664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2863548664 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.1446433573 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 116804270 ps |
| CPU time | 3.21 seconds |
| Started | Feb 07 03:37:08 PM PST 24 |
| Finished | Feb 07 03:37:12 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-3113793b-aecc-4b76-8801-02d666884acc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1446433573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1446433573 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.1815875983 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 11358229593 ps |
| CPU time | 34.06 seconds |
| Started | Feb 07 03:37:10 PM PST 24 |
| Finished | Feb 07 03:37:45 PM PST 24 |
| Peak memory | 203524 kb |
| Host | smart-5d9d2d6d-7534-4ef0-89b2-2746a460aeff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815875983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1815875983 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3999572532 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3717896951 ps |
| CPU time | 24.07 seconds |
| Started | Feb 07 03:37:11 PM PST 24 |
| Finished | Feb 07 03:37:36 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-57b7d8ea-d9e9-4da2-a7c0-fdc59158c0cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3999572532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3999572532 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1829935849 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 35489918 ps |
| CPU time | 2.4 seconds |
| Started | Feb 07 03:37:11 PM PST 24 |
| Finished | Feb 07 03:37:13 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-7f73b1b3-add1-4e69-8d49-5d950ecc382c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829935849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1829935849 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.1272892734 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1082876005 ps |
| CPU time | 160.2 seconds |
| Started | Feb 07 03:37:36 PM PST 24 |
| Finished | Feb 07 03:40:18 PM PST 24 |
| Peak memory | 208728 kb |
| Host | smart-e2bcaf80-521a-4fd7-96b4-fc2dce61953d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1272892734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1272892734 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2397998787 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1968923667 ps |
| CPU time | 121.93 seconds |
| Started | Feb 07 03:37:32 PM PST 24 |
| Finished | Feb 07 03:39:34 PM PST 24 |
| Peak memory | 206784 kb |
| Host | smart-b1efdf7d-142b-493a-a7d8-6ec2b295140d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2397998787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2397998787 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2504784702 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3502411059 ps |
| CPU time | 389.17 seconds |
| Started | Feb 07 03:37:36 PM PST 24 |
| Finished | Feb 07 03:44:07 PM PST 24 |
| Peak memory | 209888 kb |
| Host | smart-b4598f6b-ac18-4a35-9642-f5d039468e88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2504784702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.2504784702 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2396473887 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 94373889 ps |
| CPU time | 2.65 seconds |
| Started | Feb 07 03:37:32 PM PST 24 |
| Finished | Feb 07 03:37:35 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-47f9ae93-1939-4f84-9208-9979c652b6e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2396473887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.2396473887 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.932691894 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 993794581 ps |
| CPU time | 34.79 seconds |
| Started | Feb 07 03:37:23 PM PST 24 |
| Finished | Feb 07 03:37:58 PM PST 24 |
| Peak memory | 205104 kb |
| Host | smart-531743f8-61f4-4b3d-ad7f-e73856281870 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=932691894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.932691894 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2664682314 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 335447409 ps |
| CPU time | 40.13 seconds |
| Started | Feb 07 03:40:17 PM PST 24 |
| Finished | Feb 07 03:40:58 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-928c6988-bd83-4b4d-a464-fe066b13de60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2664682314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2664682314 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.833556240 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 178783418 ps |
| CPU time | 17.28 seconds |
| Started | Feb 07 03:40:21 PM PST 24 |
| Finished | Feb 07 03:40:39 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-2cdbdcad-37c3-46fb-b97e-543c9d785a69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=833556240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.833556240 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.3462795847 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1180601354 ps |
| CPU time | 16.8 seconds |
| Started | Feb 07 03:40:16 PM PST 24 |
| Finished | Feb 07 03:40:34 PM PST 24 |
| Peak memory | 203324 kb |
| Host | smart-90fcc6a4-797f-4904-9e67-4c8d1f5ecc8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3462795847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3462795847 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.688425681 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 217908746 ps |
| CPU time | 5.87 seconds |
| Started | Feb 07 03:40:16 PM PST 24 |
| Finished | Feb 07 03:40:22 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-11ae667d-e633-4bf6-afbe-ce98aaa3aade |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=688425681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.688425681 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1685154055 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 263787887094 ps |
| CPU time | 328.63 seconds |
| Started | Feb 07 03:40:24 PM PST 24 |
| Finished | Feb 07 03:45:53 PM PST 24 |
| Peak memory | 205248 kb |
| Host | smart-7f557e31-92b0-4789-bf4f-170a61b422b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685154055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1685154055 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3345730709 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 11058458190 ps |
| CPU time | 82.39 seconds |
| Started | Feb 07 03:40:16 PM PST 24 |
| Finished | Feb 07 03:41:39 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-9db7417a-7815-4ae5-8fc5-12f0179ab08d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3345730709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3345730709 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.2583888215 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 53359026 ps |
| CPU time | 6.96 seconds |
| Started | Feb 07 03:40:19 PM PST 24 |
| Finished | Feb 07 03:40:26 PM PST 24 |
| Peak memory | 211576 kb |
| Host | smart-af9aeeba-f358-4e96-a7d6-0d3cf5e50efe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583888215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.2583888215 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.3579758174 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1492020847 ps |
| CPU time | 22.27 seconds |
| Started | Feb 07 03:40:16 PM PST 24 |
| Finished | Feb 07 03:40:39 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-b9b924ff-db2d-4683-8cf7-44e848c746c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3579758174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3579758174 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.883295191 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 123875506 ps |
| CPU time | 3.73 seconds |
| Started | Feb 07 03:40:19 PM PST 24 |
| Finished | Feb 07 03:40:23 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-540e58c5-33f9-4c75-abe4-9fa8327f2270 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=883295191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.883295191 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.2481257336 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 28083280866 ps |
| CPU time | 37.76 seconds |
| Started | Feb 07 03:40:16 PM PST 24 |
| Finished | Feb 07 03:40:54 PM PST 24 |
| Peak memory | 203512 kb |
| Host | smart-f04609c6-dc21-4fa5-8623-1f0bd06f8935 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481257336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2481257336 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.2189059755 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 6444711313 ps |
| CPU time | 27.86 seconds |
| Started | Feb 07 03:40:19 PM PST 24 |
| Finished | Feb 07 03:40:47 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-b570efb6-61db-4751-a93d-de2e726b980b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2189059755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2189059755 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3531548258 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 38202630 ps |
| CPU time | 2.44 seconds |
| Started | Feb 07 03:40:15 PM PST 24 |
| Finished | Feb 07 03:40:19 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-171b8f4b-b3f5-4d71-8235-b046af5df4c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531548258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3531548258 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.466564776 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 362038686 ps |
| CPU time | 2.69 seconds |
| Started | Feb 07 03:40:31 PM PST 24 |
| Finished | Feb 07 03:40:34 PM PST 24 |
| Peak memory | 203304 kb |
| Host | smart-a482d78b-0079-475a-90ad-ee81886fc690 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=466564776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.466564776 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.3852326822 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1756433204 ps |
| CPU time | 333.99 seconds |
| Started | Feb 07 03:40:32 PM PST 24 |
| Finished | Feb 07 03:46:07 PM PST 24 |
| Peak memory | 220152 kb |
| Host | smart-0412425a-7962-43a7-b3b0-71b76d097bcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3852326822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.3852326822 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.176363375 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 980091982 ps |
| CPU time | 22.81 seconds |
| Started | Feb 07 03:40:15 PM PST 24 |
| Finished | Feb 07 03:40:39 PM PST 24 |
| Peak memory | 211584 kb |
| Host | smart-2999c1ee-67bc-4107-9b86-5947115cfe65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=176363375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.176363375 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2925225837 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 248876371 ps |
| CPU time | 20.24 seconds |
| Started | Feb 07 03:40:33 PM PST 24 |
| Finished | Feb 07 03:40:54 PM PST 24 |
| Peak memory | 205172 kb |
| Host | smart-d0a3dd08-0147-4b76-8fbd-5b03beb959fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2925225837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2925225837 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3780378105 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 53264280542 ps |
| CPU time | 176.01 seconds |
| Started | Feb 07 03:40:30 PM PST 24 |
| Finished | Feb 07 03:43:27 PM PST 24 |
| Peak memory | 205736 kb |
| Host | smart-d608d836-fc3b-4ffa-9809-e5d125749c1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3780378105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3780378105 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1378405574 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1184854501 ps |
| CPU time | 27.06 seconds |
| Started | Feb 07 03:40:39 PM PST 24 |
| Finished | Feb 07 03:41:07 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-c7301b85-3316-414c-b8a3-12099347ce4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1378405574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1378405574 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.61687304 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 223899977 ps |
| CPU time | 6.01 seconds |
| Started | Feb 07 03:40:34 PM PST 24 |
| Finished | Feb 07 03:40:41 PM PST 24 |
| Peak memory | 203296 kb |
| Host | smart-d7b17331-e9d7-4545-9a3d-2f390cb70ccf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=61687304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.61687304 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.334345176 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2441121592 ps |
| CPU time | 41.62 seconds |
| Started | Feb 07 03:40:35 PM PST 24 |
| Finished | Feb 07 03:41:17 PM PST 24 |
| Peak memory | 211728 kb |
| Host | smart-e0da6b16-db4c-489e-934e-d36698d1d8a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=334345176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.334345176 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.304868300 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 22062180962 ps |
| CPU time | 86.62 seconds |
| Started | Feb 07 03:40:34 PM PST 24 |
| Finished | Feb 07 03:42:02 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-c776ff39-b649-4fda-a5a1-f092563554c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=304868300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.304868300 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1660975787 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2878941792 ps |
| CPU time | 20.7 seconds |
| Started | Feb 07 03:40:37 PM PST 24 |
| Finished | Feb 07 03:40:58 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-f61e5b05-3bcf-472a-a525-b927a1415b4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1660975787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1660975787 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.3442504788 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 141430593 ps |
| CPU time | 11.87 seconds |
| Started | Feb 07 03:40:34 PM PST 24 |
| Finished | Feb 07 03:40:47 PM PST 24 |
| Peak memory | 204352 kb |
| Host | smart-76c3de65-0c50-4d4a-831d-2b2eedbf744b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442504788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3442504788 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.1031307058 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 1120480747 ps |
| CPU time | 16.07 seconds |
| Started | Feb 07 03:40:33 PM PST 24 |
| Finished | Feb 07 03:40:49 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-83d7bca6-e060-4d23-90b3-d2c99523901a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1031307058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1031307058 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.335023648 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 40951272 ps |
| CPU time | 2.29 seconds |
| Started | Feb 07 03:40:33 PM PST 24 |
| Finished | Feb 07 03:40:36 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-f536d50a-a033-4cca-bf42-cc43fecdd0c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=335023648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.335023648 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3001966624 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5261945317 ps |
| CPU time | 29.66 seconds |
| Started | Feb 07 03:40:30 PM PST 24 |
| Finished | Feb 07 03:41:00 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-458624ce-7aca-48af-b658-ddd8fe2bbc35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001966624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3001966624 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3031404088 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4401902433 ps |
| CPU time | 31.28 seconds |
| Started | Feb 07 03:40:32 PM PST 24 |
| Finished | Feb 07 03:41:04 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-529a5127-c0a9-429d-ae7f-20da25073c4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3031404088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3031404088 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.933750788 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 45404794 ps |
| CPU time | 2.4 seconds |
| Started | Feb 07 03:40:26 PM PST 24 |
| Finished | Feb 07 03:40:29 PM PST 24 |
| Peak memory | 203320 kb |
| Host | smart-285074e3-aa49-42d5-a5a9-53a8253a7f2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933750788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.933750788 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.3719345118 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1445270226 ps |
| CPU time | 109.6 seconds |
| Started | Feb 07 03:40:38 PM PST 24 |
| Finished | Feb 07 03:42:28 PM PST 24 |
| Peak memory | 207128 kb |
| Host | smart-d91e267c-a8c5-4963-ba42-480abdec594f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3719345118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3719345118 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.803381255 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 14323506985 ps |
| CPU time | 202.13 seconds |
| Started | Feb 07 03:40:39 PM PST 24 |
| Finished | Feb 07 03:44:01 PM PST 24 |
| Peak memory | 209696 kb |
| Host | smart-ab001e4b-7c4c-43c0-b61b-43ed9faf734e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=803381255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.803381255 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1359465477 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 656011612 ps |
| CPU time | 198.35 seconds |
| Started | Feb 07 03:40:40 PM PST 24 |
| Finished | Feb 07 03:43:59 PM PST 24 |
| Peak memory | 209004 kb |
| Host | smart-bd032594-6d5f-453e-ae43-6a0872eaf07c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1359465477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.1359465477 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2664429851 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 650692757 ps |
| CPU time | 217.71 seconds |
| Started | Feb 07 03:40:43 PM PST 24 |
| Finished | Feb 07 03:44:21 PM PST 24 |
| Peak memory | 211604 kb |
| Host | smart-e0908e16-6d50-472c-8c73-a3463d018627 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2664429851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.2664429851 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1456004733 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 565943260 ps |
| CPU time | 20.44 seconds |
| Started | Feb 07 03:40:31 PM PST 24 |
| Finished | Feb 07 03:40:52 PM PST 24 |
| Peak memory | 204868 kb |
| Host | smart-5dacb824-cec5-4821-9803-c27f1c640453 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1456004733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1456004733 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1887324021 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 289689920 ps |
| CPU time | 44.81 seconds |
| Started | Feb 07 03:40:57 PM PST 24 |
| Finished | Feb 07 03:41:42 PM PST 24 |
| Peak memory | 211620 kb |
| Host | smart-a3b44295-9a33-4cd6-9a2f-1061d28882c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1887324021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1887324021 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2838244972 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 37054862135 ps |
| CPU time | 284.57 seconds |
| Started | Feb 07 03:40:49 PM PST 24 |
| Finished | Feb 07 03:45:34 PM PST 24 |
| Peak memory | 206344 kb |
| Host | smart-062679e2-d764-49e9-a12c-d29e5b00b699 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2838244972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.2838244972 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1544586913 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 82253119 ps |
| CPU time | 6.32 seconds |
| Started | Feb 07 03:41:03 PM PST 24 |
| Finished | Feb 07 03:41:09 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-11cf1cc2-56a9-4bcb-a130-4c21a9e21b95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1544586913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1544586913 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.3253157113 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 314133268 ps |
| CPU time | 26.06 seconds |
| Started | Feb 07 03:40:50 PM PST 24 |
| Finished | Feb 07 03:41:16 PM PST 24 |
| Peak memory | 203508 kb |
| Host | smart-12c4e9fc-f147-44e9-a0fb-22c7ac7d7539 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3253157113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3253157113 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.2990513707 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 24291685 ps |
| CPU time | 2.48 seconds |
| Started | Feb 07 03:40:50 PM PST 24 |
| Finished | Feb 07 03:40:53 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-c8a13297-dfec-4b13-bc90-720ca7a0a578 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2990513707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2990513707 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.2729950484 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 19122493474 ps |
| CPU time | 64.97 seconds |
| Started | Feb 07 03:40:49 PM PST 24 |
| Finished | Feb 07 03:41:54 PM PST 24 |
| Peak memory | 211684 kb |
| Host | smart-8355786e-fefa-4b5a-a126-de483bfb014a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729950484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2729950484 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.194819756 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 17233413325 ps |
| CPU time | 112.84 seconds |
| Started | Feb 07 03:40:48 PM PST 24 |
| Finished | Feb 07 03:42:41 PM PST 24 |
| Peak memory | 204836 kb |
| Host | smart-3206d438-0870-40f8-bfd0-3df149cc4e7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=194819756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.194819756 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.370269930 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 130513256 ps |
| CPU time | 16.97 seconds |
| Started | Feb 07 03:40:50 PM PST 24 |
| Finished | Feb 07 03:41:07 PM PST 24 |
| Peak memory | 204584 kb |
| Host | smart-7bc00d45-fcaa-46fd-8b2c-dd40bdd0d66d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370269930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.370269930 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.392358962 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 3520628358 ps |
| CPU time | 28.38 seconds |
| Started | Feb 07 03:40:48 PM PST 24 |
| Finished | Feb 07 03:41:17 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-15ec6ad2-0d69-4a0f-bdda-1a928a54d61d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=392358962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.392358962 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.858132181 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 128333826 ps |
| CPU time | 3.48 seconds |
| Started | Feb 07 03:40:44 PM PST 24 |
| Finished | Feb 07 03:40:48 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-afb4463e-2a94-446e-b0dd-7d9ea44adfb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=858132181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.858132181 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.1299181816 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 11215301038 ps |
| CPU time | 32.72 seconds |
| Started | Feb 07 03:40:51 PM PST 24 |
| Finished | Feb 07 03:41:25 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-cb843016-f1a9-4af8-9f2e-898562f2e6f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299181816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1299181816 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.87843292 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 31249056 ps |
| CPU time | 2.44 seconds |
| Started | Feb 07 03:40:53 PM PST 24 |
| Finished | Feb 07 03:40:56 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-0bc711f2-4789-43c1-be90-7ddffc12f7fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87843292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.87843292 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.744812092 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 513945976 ps |
| CPU time | 64.48 seconds |
| Started | Feb 07 03:40:58 PM PST 24 |
| Finished | Feb 07 03:42:03 PM PST 24 |
| Peak memory | 207036 kb |
| Host | smart-49649515-278e-4a3c-84a7-2568960b5f59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=744812092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.744812092 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.3687566676 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 871362974 ps |
| CPU time | 76.08 seconds |
| Started | Feb 07 03:41:00 PM PST 24 |
| Finished | Feb 07 03:42:16 PM PST 24 |
| Peak memory | 205040 kb |
| Host | smart-2dea6ce4-78e0-4e95-b2ea-d7117eee61c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3687566676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3687566676 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1595006162 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1274568400 ps |
| CPU time | 274.85 seconds |
| Started | Feb 07 03:40:57 PM PST 24 |
| Finished | Feb 07 03:45:33 PM PST 24 |
| Peak memory | 208464 kb |
| Host | smart-85e446fc-56a7-4187-8d2e-924b99eb9745 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1595006162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.1595006162 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3830174385 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4486204447 ps |
| CPU time | 201.7 seconds |
| Started | Feb 07 03:41:00 PM PST 24 |
| Finished | Feb 07 03:44:22 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-8d1cb43a-bf5e-4157-a9ee-cf24364dd758 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3830174385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.3830174385 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.4223908628 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 333726961 ps |
| CPU time | 16.24 seconds |
| Started | Feb 07 03:40:59 PM PST 24 |
| Finished | Feb 07 03:41:16 PM PST 24 |
| Peak memory | 211620 kb |
| Host | smart-67c2f55b-e966-4240-a899-6ac55e29234e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4223908628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.4223908628 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.1980513336 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 720175496 ps |
| CPU time | 15.12 seconds |
| Started | Feb 07 03:41:07 PM PST 24 |
| Finished | Feb 07 03:41:23 PM PST 24 |
| Peak memory | 204520 kb |
| Host | smart-855bd08e-5ad8-4fa3-8f3e-1a658caf00f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1980513336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1980513336 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.379979694 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 104050516546 ps |
| CPU time | 646.77 seconds |
| Started | Feb 07 03:41:08 PM PST 24 |
| Finished | Feb 07 03:51:55 PM PST 24 |
| Peak memory | 211644 kb |
| Host | smart-366d4721-ee88-492d-baac-ef09095ea4bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=379979694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slo w_rsp.379979694 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.3411667085 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 221964953 ps |
| CPU time | 3.23 seconds |
| Started | Feb 07 03:41:08 PM PST 24 |
| Finished | Feb 07 03:41:12 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-a86920ab-d2a5-4abd-a69d-ee556c665a3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3411667085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3411667085 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.2939640615 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1767230277 ps |
| CPU time | 39.93 seconds |
| Started | Feb 07 03:41:06 PM PST 24 |
| Finished | Feb 07 03:41:46 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-8412fbb4-9135-4d90-b74b-14c0c04320c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2939640615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2939640615 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.1452164403 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1213258593 ps |
| CPU time | 36.63 seconds |
| Started | Feb 07 03:41:12 PM PST 24 |
| Finished | Feb 07 03:41:49 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-9ab6656c-da45-465e-9174-9486cad861cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1452164403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1452164403 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.1517991371 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 19507217361 ps |
| CPU time | 124.5 seconds |
| Started | Feb 07 03:41:08 PM PST 24 |
| Finished | Feb 07 03:43:13 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-832be837-3dbc-4462-885d-da5bae09f2d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517991371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1517991371 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1645605860 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 31581387210 ps |
| CPU time | 100.38 seconds |
| Started | Feb 07 03:41:11 PM PST 24 |
| Finished | Feb 07 03:42:52 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-127d1cb1-ca73-47d2-a5f6-d87d649d0532 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1645605860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1645605860 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.1931801548 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 185415653 ps |
| CPU time | 19.11 seconds |
| Started | Feb 07 03:41:12 PM PST 24 |
| Finished | Feb 07 03:41:31 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-b44c774e-647b-4bc5-935f-baffb9e15c25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931801548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1931801548 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.4190022 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1285996717 ps |
| CPU time | 28.8 seconds |
| Started | Feb 07 03:41:08 PM PST 24 |
| Finished | Feb 07 03:41:38 PM PST 24 |
| Peak memory | 203908 kb |
| Host | smart-63a45aca-ffaa-49ba-9bee-cc41758e1259 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4190022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.4190022 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.1033901951 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 27635081 ps |
| CPU time | 2.16 seconds |
| Started | Feb 07 03:40:58 PM PST 24 |
| Finished | Feb 07 03:41:01 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-7625eace-5ad7-4437-a38d-dd6332aff9a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1033901951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1033901951 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.889400977 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 5907412485 ps |
| CPU time | 30.93 seconds |
| Started | Feb 07 03:40:58 PM PST 24 |
| Finished | Feb 07 03:41:30 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-1fc43c85-eaf4-4aad-a4b6-c69c638b9180 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=889400977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.889400977 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.4261083919 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 3873534925 ps |
| CPU time | 26.09 seconds |
| Started | Feb 07 03:40:58 PM PST 24 |
| Finished | Feb 07 03:41:25 PM PST 24 |
| Peak memory | 203260 kb |
| Host | smart-cf998f32-c29f-4e7a-875e-d020051e26e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4261083919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4261083919 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.310143186 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 106748089 ps |
| CPU time | 2.44 seconds |
| Started | Feb 07 03:41:03 PM PST 24 |
| Finished | Feb 07 03:41:05 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-04a13999-1229-42b9-bd09-cfbf2753d4d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310143186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.310143186 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.2192245502 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 1468946125 ps |
| CPU time | 68.08 seconds |
| Started | Feb 07 03:41:16 PM PST 24 |
| Finished | Feb 07 03:42:24 PM PST 24 |
| Peak memory | 207696 kb |
| Host | smart-1ccd34be-d4c4-40e7-aff6-00dfdbe5cac4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2192245502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2192245502 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.1754811598 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 950395359 ps |
| CPU time | 108.47 seconds |
| Started | Feb 07 03:41:18 PM PST 24 |
| Finished | Feb 07 03:43:07 PM PST 24 |
| Peak memory | 206652 kb |
| Host | smart-a2c08a10-6e85-4511-8347-3b9570e7b176 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1754811598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1754811598 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.3608913579 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 15339496 ps |
| CPU time | 13.8 seconds |
| Started | Feb 07 03:41:13 PM PST 24 |
| Finished | Feb 07 03:41:27 PM PST 24 |
| Peak memory | 205764 kb |
| Host | smart-ba283fbd-d4f9-41b3-b346-19eef37a60ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3608913579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.3608913579 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.427413494 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 338656087 ps |
| CPU time | 100.51 seconds |
| Started | Feb 07 03:41:17 PM PST 24 |
| Finished | Feb 07 03:42:58 PM PST 24 |
| Peak memory | 209460 kb |
| Host | smart-284d2c34-f71c-4d7a-b450-f75a0644427f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=427413494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_res et_error.427413494 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.4064390138 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 115031363 ps |
| CPU time | 20.55 seconds |
| Started | Feb 07 03:41:11 PM PST 24 |
| Finished | Feb 07 03:41:32 PM PST 24 |
| Peak memory | 205124 kb |
| Host | smart-0d8c7476-59d6-4f98-9b75-2acf560263bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4064390138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.4064390138 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.302872486 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 332145294 ps |
| CPU time | 18.3 seconds |
| Started | Feb 07 03:41:16 PM PST 24 |
| Finished | Feb 07 03:41:34 PM PST 24 |
| Peak memory | 204072 kb |
| Host | smart-12f7e4c1-63d6-4e97-acfa-d562630ed78b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=302872486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.302872486 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1756513524 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 46883450974 ps |
| CPU time | 426.72 seconds |
| Started | Feb 07 03:41:19 PM PST 24 |
| Finished | Feb 07 03:48:26 PM PST 24 |
| Peak memory | 206752 kb |
| Host | smart-042970e0-76d7-4c86-8436-7ea0b4065fc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1756513524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1756513524 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.656972453 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 593517210 ps |
| CPU time | 14.15 seconds |
| Started | Feb 07 03:41:21 PM PST 24 |
| Finished | Feb 07 03:41:36 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-e8280692-e221-48cc-9bdd-a5d2585df2fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=656972453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.656972453 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.3423036128 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 135015201 ps |
| CPU time | 14.73 seconds |
| Started | Feb 07 03:41:12 PM PST 24 |
| Finished | Feb 07 03:41:28 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-741c0265-5816-48b4-bf8d-959a16db6f5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3423036128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3423036128 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.2100038588 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 344094570 ps |
| CPU time | 19.62 seconds |
| Started | Feb 07 03:41:22 PM PST 24 |
| Finished | Feb 07 03:41:45 PM PST 24 |
| Peak memory | 211580 kb |
| Host | smart-ea458f61-9074-41cf-856a-526b83ce1ce2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2100038588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2100038588 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.367637087 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 49635096885 ps |
| CPU time | 259.37 seconds |
| Started | Feb 07 03:41:23 PM PST 24 |
| Finished | Feb 07 03:45:45 PM PST 24 |
| Peak memory | 205236 kb |
| Host | smart-4975e5f4-8d04-448d-87e0-bde06492437a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=367637087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.367637087 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3307993800 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 113392559803 ps |
| CPU time | 309 seconds |
| Started | Feb 07 03:41:17 PM PST 24 |
| Finished | Feb 07 03:46:26 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-9d00c3f1-46bf-454d-887e-b22bdac21e09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3307993800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3307993800 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2162497468 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 110972649 ps |
| CPU time | 12.8 seconds |
| Started | Feb 07 03:41:15 PM PST 24 |
| Finished | Feb 07 03:41:28 PM PST 24 |
| Peak memory | 211584 kb |
| Host | smart-8acbc22a-39b6-454c-87ec-94f9f0b802df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162497468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2162497468 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.223191450 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 318329443 ps |
| CPU time | 7.97 seconds |
| Started | Feb 07 03:41:15 PM PST 24 |
| Finished | Feb 07 03:41:23 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-b4f0b96e-6358-44d4-9d8f-8875da47fe50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=223191450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.223191450 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.647145737 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 167564144 ps |
| CPU time | 3.92 seconds |
| Started | Feb 07 03:41:13 PM PST 24 |
| Finished | Feb 07 03:41:17 PM PST 24 |
| Peak memory | 203344 kb |
| Host | smart-2ab474a2-2e6d-45b1-9e65-ef879ec5f212 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647145737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.647145737 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1826139956 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 6273273877 ps |
| CPU time | 33.61 seconds |
| Started | Feb 07 03:41:18 PM PST 24 |
| Finished | Feb 07 03:41:53 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-6d652809-82a4-4214-8ca5-2e09141b1449 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826139956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1826139956 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2467739696 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 2653551846 ps |
| CPU time | 25.32 seconds |
| Started | Feb 07 03:41:16 PM PST 24 |
| Finished | Feb 07 03:41:41 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-3cdd0bb1-16ab-4840-82d6-7496b2c4a4a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2467739696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2467739696 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3604104455 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 130374431 ps |
| CPU time | 2.8 seconds |
| Started | Feb 07 03:41:12 PM PST 24 |
| Finished | Feb 07 03:41:15 PM PST 24 |
| Peak memory | 203368 kb |
| Host | smart-7b909371-80b1-45e0-bfee-b9162b2787ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604104455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3604104455 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.1924908457 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1987478291 ps |
| CPU time | 82.19 seconds |
| Started | Feb 07 03:41:18 PM PST 24 |
| Finished | Feb 07 03:42:40 PM PST 24 |
| Peak memory | 207884 kb |
| Host | smart-b25da406-1ad9-4ffc-976e-67a354dddb47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1924908457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1924908457 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.383367277 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 19461361769 ps |
| CPU time | 284.67 seconds |
| Started | Feb 07 03:41:15 PM PST 24 |
| Finished | Feb 07 03:46:00 PM PST 24 |
| Peak memory | 206940 kb |
| Host | smart-f4d35c67-f5ed-42ab-b560-1f575fc8bc26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=383367277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.383367277 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2277085561 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 739055701 ps |
| CPU time | 193.9 seconds |
| Started | Feb 07 03:41:20 PM PST 24 |
| Finished | Feb 07 03:44:34 PM PST 24 |
| Peak memory | 209184 kb |
| Host | smart-f8f56aff-719f-4ba0-ba8f-24da5268af25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2277085561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.2277085561 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.657156586 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 353744689 ps |
| CPU time | 111.96 seconds |
| Started | Feb 07 03:41:18 PM PST 24 |
| Finished | Feb 07 03:43:10 PM PST 24 |
| Peak memory | 209212 kb |
| Host | smart-b49cbf3d-fa91-492e-affe-178939dd6c8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=657156586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res et_error.657156586 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.1464367846 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2364463626 ps |
| CPU time | 23.13 seconds |
| Started | Feb 07 03:41:19 PM PST 24 |
| Finished | Feb 07 03:41:42 PM PST 24 |
| Peak memory | 204720 kb |
| Host | smart-4ccece19-b05c-44f9-bf69-b0240d32e821 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1464367846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1464367846 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3838781987 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 22648512 ps |
| CPU time | 3.42 seconds |
| Started | Feb 07 03:41:24 PM PST 24 |
| Finished | Feb 07 03:41:29 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-a88679d5-384e-4d1a-bb95-0ff5f8471e15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3838781987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3838781987 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.575774899 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 91531108530 ps |
| CPU time | 492.76 seconds |
| Started | Feb 07 03:41:40 PM PST 24 |
| Finished | Feb 07 03:49:53 PM PST 24 |
| Peak memory | 211660 kb |
| Host | smart-2b8abc80-b0b6-498f-96b8-a99843c6e9fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=575774899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slo w_rsp.575774899 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2650212031 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 46908144 ps |
| CPU time | 6.49 seconds |
| Started | Feb 07 03:41:41 PM PST 24 |
| Finished | Feb 07 03:41:48 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-0c1a29b6-e928-40cf-b30b-b60960bf0401 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2650212031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2650212031 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.2269525539 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 1174137102 ps |
| CPU time | 20.41 seconds |
| Started | Feb 07 03:41:36 PM PST 24 |
| Finished | Feb 07 03:41:57 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-3679c2b3-bb7b-4a6b-b852-a13252bc82b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2269525539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2269525539 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.2491422564 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2459769365 ps |
| CPU time | 22.94 seconds |
| Started | Feb 07 03:41:23 PM PST 24 |
| Finished | Feb 07 03:41:49 PM PST 24 |
| Peak memory | 204508 kb |
| Host | smart-014ca215-1896-4716-b61f-03d3b8db28f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2491422564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2491422564 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2568995910 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 43520522801 ps |
| CPU time | 254.1 seconds |
| Started | Feb 07 03:41:26 PM PST 24 |
| Finished | Feb 07 03:45:41 PM PST 24 |
| Peak memory | 205108 kb |
| Host | smart-7df8097e-a353-43a8-a220-790d98baca1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568995910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2568995910 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1709536589 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 181331575280 ps |
| CPU time | 323.57 seconds |
| Started | Feb 07 03:41:24 PM PST 24 |
| Finished | Feb 07 03:46:50 PM PST 24 |
| Peak memory | 211648 kb |
| Host | smart-a5c68bae-301f-4481-83e3-324f515df6ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1709536589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1709536589 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.1801455256 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 277937688 ps |
| CPU time | 28.93 seconds |
| Started | Feb 07 03:41:24 PM PST 24 |
| Finished | Feb 07 03:41:55 PM PST 24 |
| Peak memory | 204544 kb |
| Host | smart-f75594af-6eca-42ec-82c7-4ca30352f897 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801455256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1801455256 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.527819993 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1287447427 ps |
| CPU time | 32.26 seconds |
| Started | Feb 07 03:41:36 PM PST 24 |
| Finished | Feb 07 03:42:09 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-fc1961b4-87a0-446c-976e-95e91d9c6e30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=527819993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.527819993 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.3810980376 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 24995285 ps |
| CPU time | 2.14 seconds |
| Started | Feb 07 03:41:14 PM PST 24 |
| Finished | Feb 07 03:41:16 PM PST 24 |
| Peak memory | 203368 kb |
| Host | smart-4e7934af-3499-4314-8df5-95de8233050d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3810980376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3810980376 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1904808218 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 5086090552 ps |
| CPU time | 28.58 seconds |
| Started | Feb 07 03:41:22 PM PST 24 |
| Finished | Feb 07 03:41:55 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-beee653d-1545-4c93-bdaa-27402fec2165 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904808218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1904808218 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2592374204 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 10655255995 ps |
| CPU time | 39.15 seconds |
| Started | Feb 07 03:41:22 PM PST 24 |
| Finished | Feb 07 03:42:05 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-8c04ab77-cbd8-4e43-9777-b54b78a1070d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2592374204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2592374204 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1915141366 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 39880829 ps |
| CPU time | 2.68 seconds |
| Started | Feb 07 03:41:24 PM PST 24 |
| Finished | Feb 07 03:41:29 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-2e49b7fd-0ba1-47cd-88be-886c65c7a233 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915141366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1915141366 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.812306163 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1161388021 ps |
| CPU time | 95.75 seconds |
| Started | Feb 07 03:41:36 PM PST 24 |
| Finished | Feb 07 03:43:12 PM PST 24 |
| Peak memory | 205852 kb |
| Host | smart-e63be3ae-384f-4e31-929a-7997ef052d02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=812306163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.812306163 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2999391326 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 275664818 ps |
| CPU time | 28.71 seconds |
| Started | Feb 07 03:41:35 PM PST 24 |
| Finished | Feb 07 03:42:05 PM PST 24 |
| Peak memory | 204052 kb |
| Host | smart-f4a50ff6-bfbb-402a-a84b-9843dd06bd11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2999391326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2999391326 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2257293300 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 14617538168 ps |
| CPU time | 528.76 seconds |
| Started | Feb 07 03:41:36 PM PST 24 |
| Finished | Feb 07 03:50:25 PM PST 24 |
| Peak memory | 222724 kb |
| Host | smart-97f23329-5021-4cfa-91a0-cc7260b48b40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2257293300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.2257293300 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3663684022 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 628316967 ps |
| CPU time | 140.57 seconds |
| Started | Feb 07 03:41:37 PM PST 24 |
| Finished | Feb 07 03:43:58 PM PST 24 |
| Peak memory | 210360 kb |
| Host | smart-30ad3240-2652-4f88-945e-3bb494601af0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3663684022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.3663684022 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.949078079 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 93569944 ps |
| CPU time | 3.98 seconds |
| Started | Feb 07 03:41:34 PM PST 24 |
| Finished | Feb 07 03:41:39 PM PST 24 |
| Peak memory | 211512 kb |
| Host | smart-3c7203d5-3d40-4b6f-b4f4-7e71ec53f32c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=949078079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.949078079 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.456521912 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 998145352 ps |
| CPU time | 42.57 seconds |
| Started | Feb 07 03:41:40 PM PST 24 |
| Finished | Feb 07 03:42:23 PM PST 24 |
| Peak memory | 206120 kb |
| Host | smart-489f4bd0-f4ad-42f5-bb9d-390f8de542e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=456521912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.456521912 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.465519666 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 28169329145 ps |
| CPU time | 257.11 seconds |
| Started | Feb 07 03:41:37 PM PST 24 |
| Finished | Feb 07 03:45:55 PM PST 24 |
| Peak memory | 211684 kb |
| Host | smart-1f571a37-5d71-4efb-b868-6e99b7f77537 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=465519666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo w_rsp.465519666 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3938668442 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 59502232 ps |
| CPU time | 4.47 seconds |
| Started | Feb 07 03:41:39 PM PST 24 |
| Finished | Feb 07 03:41:44 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-ef4065e4-1b3d-432b-bff5-82acf33f6840 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3938668442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3938668442 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.652275614 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 4668470556 ps |
| CPU time | 28.87 seconds |
| Started | Feb 07 03:41:40 PM PST 24 |
| Finished | Feb 07 03:42:09 PM PST 24 |
| Peak memory | 203556 kb |
| Host | smart-0b81a478-37fa-4504-92de-1b5808a6db24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=652275614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.652275614 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.1121829706 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 260800359 ps |
| CPU time | 26.22 seconds |
| Started | Feb 07 03:41:33 PM PST 24 |
| Finished | Feb 07 03:42:00 PM PST 24 |
| Peak memory | 204488 kb |
| Host | smart-f165b5f6-7554-4725-924c-c9f9be967644 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1121829706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1121829706 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.770208173 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 65957415178 ps |
| CPU time | 217 seconds |
| Started | Feb 07 03:41:33 PM PST 24 |
| Finished | Feb 07 03:45:11 PM PST 24 |
| Peak memory | 205176 kb |
| Host | smart-1c11b4a7-1583-4985-8ef9-ba68218397a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=770208173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.770208173 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.575717261 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 21664670393 ps |
| CPU time | 186.39 seconds |
| Started | Feb 07 03:41:35 PM PST 24 |
| Finished | Feb 07 03:44:43 PM PST 24 |
| Peak memory | 204552 kb |
| Host | smart-aed8cf6c-7ffa-4e12-991a-9c832bbfcdca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=575717261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.575717261 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3813706678 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 100534133 ps |
| CPU time | 10.88 seconds |
| Started | Feb 07 03:41:31 PM PST 24 |
| Finished | Feb 07 03:41:44 PM PST 24 |
| Peak memory | 211560 kb |
| Host | smart-dbb1442f-f9bf-4673-abbb-ff977e3025e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813706678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3813706678 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.1528110961 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1906341875 ps |
| CPU time | 28.69 seconds |
| Started | Feb 07 03:41:39 PM PST 24 |
| Finished | Feb 07 03:42:08 PM PST 24 |
| Peak memory | 203856 kb |
| Host | smart-b05897ea-c96d-4755-bed0-e1caec33f8b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1528110961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1528110961 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.1365391197 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 27242967 ps |
| CPU time | 2.43 seconds |
| Started | Feb 07 03:41:34 PM PST 24 |
| Finished | Feb 07 03:41:37 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-87946245-f422-4ea3-ace0-9f1dc298fce0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1365391197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1365391197 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3450688473 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 16361185823 ps |
| CPU time | 31.19 seconds |
| Started | Feb 07 03:41:37 PM PST 24 |
| Finished | Feb 07 03:42:08 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-3b0e5aa8-4b18-4b7b-8e30-6f6218169d15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450688473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3450688473 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1672680628 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 4339019546 ps |
| CPU time | 30.06 seconds |
| Started | Feb 07 03:41:38 PM PST 24 |
| Finished | Feb 07 03:42:08 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-8a96fd26-df25-4aab-a746-328cc02e7333 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1672680628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1672680628 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.799122325 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 51823016 ps |
| CPU time | 2.69 seconds |
| Started | Feb 07 03:41:37 PM PST 24 |
| Finished | Feb 07 03:41:40 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-9bc8ca32-c589-44ac-91da-aceb5d108229 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799122325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.799122325 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.1844144242 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 639603673 ps |
| CPU time | 96.93 seconds |
| Started | Feb 07 03:41:37 PM PST 24 |
| Finished | Feb 07 03:43:14 PM PST 24 |
| Peak memory | 206784 kb |
| Host | smart-e57a1888-af0e-4ddb-b9f9-80063688253f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1844144242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1844144242 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2778816544 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 12977043096 ps |
| CPU time | 122.98 seconds |
| Started | Feb 07 03:41:44 PM PST 24 |
| Finished | Feb 07 03:43:48 PM PST 24 |
| Peak memory | 207980 kb |
| Host | smart-57d925cf-bfb7-4c37-8c0b-dde640b5a359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2778816544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2778816544 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3783139859 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 3014513134 ps |
| CPU time | 289.15 seconds |
| Started | Feb 07 03:41:43 PM PST 24 |
| Finished | Feb 07 03:46:33 PM PST 24 |
| Peak memory | 219860 kb |
| Host | smart-715c587e-eb5e-47b3-b0ed-4de45804194a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3783139859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.3783139859 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.3500543409 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 145797837 ps |
| CPU time | 7.08 seconds |
| Started | Feb 07 03:41:38 PM PST 24 |
| Finished | Feb 07 03:41:46 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-d8e109d7-7080-4712-a86c-4ac0ff23d1fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3500543409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3500543409 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.3888472861 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 750170424 ps |
| CPU time | 32.26 seconds |
| Started | Feb 07 03:41:57 PM PST 24 |
| Finished | Feb 07 03:42:30 PM PST 24 |
| Peak memory | 205912 kb |
| Host | smart-2e857365-b05c-489b-8208-96fbe2a53dd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3888472861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3888472861 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3817464064 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 5567395385 ps |
| CPU time | 31.91 seconds |
| Started | Feb 07 03:41:57 PM PST 24 |
| Finished | Feb 07 03:42:29 PM PST 24 |
| Peak memory | 203540 kb |
| Host | smart-53630520-90ad-47ef-ba69-d594bb21256f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3817464064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.3817464064 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.42790570 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 120287540 ps |
| CPU time | 11.74 seconds |
| Started | Feb 07 03:42:01 PM PST 24 |
| Finished | Feb 07 03:42:13 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-6e24b9bb-cb9a-44ee-a2bc-0bcebc627f34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=42790570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.42790570 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.3855300472 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 465870390 ps |
| CPU time | 11.7 seconds |
| Started | Feb 07 03:41:59 PM PST 24 |
| Finished | Feb 07 03:42:11 PM PST 24 |
| Peak memory | 203364 kb |
| Host | smart-5e905170-3997-451c-bb31-a6f1211ad819 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3855300472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3855300472 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.3505871493 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 893499073 ps |
| CPU time | 26.53 seconds |
| Started | Feb 07 03:41:56 PM PST 24 |
| Finished | Feb 07 03:42:23 PM PST 24 |
| Peak memory | 204544 kb |
| Host | smart-0fc43bfa-64ee-431a-b2ed-9146886f7c12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3505871493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3505871493 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3692089343 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 31643606013 ps |
| CPU time | 188.87 seconds |
| Started | Feb 07 03:41:54 PM PST 24 |
| Finished | Feb 07 03:45:03 PM PST 24 |
| Peak memory | 204732 kb |
| Host | smart-f93270f2-3b45-4757-abd7-1195b854586c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692089343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3692089343 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2805185828 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14749487014 ps |
| CPU time | 117.5 seconds |
| Started | Feb 07 03:41:54 PM PST 24 |
| Finished | Feb 07 03:43:52 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-87e57dcf-6483-424e-820c-ff22239e65df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2805185828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2805185828 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.3843407530 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 138388745 ps |
| CPU time | 17.23 seconds |
| Started | Feb 07 03:41:58 PM PST 24 |
| Finished | Feb 07 03:42:16 PM PST 24 |
| Peak memory | 204496 kb |
| Host | smart-28ede6f7-a466-4446-b19d-84fe61713c87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843407530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.3843407530 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.292411604 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 894792507 ps |
| CPU time | 13.52 seconds |
| Started | Feb 07 03:41:58 PM PST 24 |
| Finished | Feb 07 03:42:12 PM PST 24 |
| Peak memory | 203856 kb |
| Host | smart-d2034375-e798-48a6-95c5-9974af2b43cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=292411604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.292411604 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.2955920121 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 143564119 ps |
| CPU time | 3.45 seconds |
| Started | Feb 07 03:41:44 PM PST 24 |
| Finished | Feb 07 03:41:49 PM PST 24 |
| Peak memory | 203320 kb |
| Host | smart-a0cdbb69-23c1-4503-baea-1733abd9bd0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2955920121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2955920121 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.1669968847 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 5472027850 ps |
| CPU time | 28.74 seconds |
| Started | Feb 07 03:41:43 PM PST 24 |
| Finished | Feb 07 03:42:13 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-399d579f-cd35-4c29-b58e-1d8589644e73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669968847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1669968847 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.411260746 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 7479085730 ps |
| CPU time | 34.5 seconds |
| Started | Feb 07 03:41:53 PM PST 24 |
| Finished | Feb 07 03:42:28 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-c4d0bc67-b29e-4b52-bbb5-30e91c3ddf91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=411260746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.411260746 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1526097657 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 38217788 ps |
| CPU time | 2.49 seconds |
| Started | Feb 07 03:41:41 PM PST 24 |
| Finished | Feb 07 03:41:44 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-2c7fdd25-c219-4b81-bfb2-b94d9c4eb0a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526097657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1526097657 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3789402235 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2256428501 ps |
| CPU time | 157.83 seconds |
| Started | Feb 07 03:41:56 PM PST 24 |
| Finished | Feb 07 03:44:34 PM PST 24 |
| Peak memory | 211704 kb |
| Host | smart-c9f0e733-7553-42cf-a3cd-8bb753e9c161 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3789402235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3789402235 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3423319431 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1196702041 ps |
| CPU time | 89.86 seconds |
| Started | Feb 07 03:41:56 PM PST 24 |
| Finished | Feb 07 03:43:26 PM PST 24 |
| Peak memory | 207836 kb |
| Host | smart-2fe88025-031b-4834-a2b4-15097546337c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3423319431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3423319431 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.571906418 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 922749256 ps |
| CPU time | 272.03 seconds |
| Started | Feb 07 03:41:57 PM PST 24 |
| Finished | Feb 07 03:46:29 PM PST 24 |
| Peak memory | 209788 kb |
| Host | smart-ef861ae1-b699-4f95-8209-9df141bd9c25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=571906418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand _reset.571906418 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.364488918 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 221479054 ps |
| CPU time | 42.73 seconds |
| Started | Feb 07 03:41:56 PM PST 24 |
| Finished | Feb 07 03:42:39 PM PST 24 |
| Peak memory | 206716 kb |
| Host | smart-15edd09a-5b2a-4850-b86a-4d22500ecf9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=364488918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res et_error.364488918 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.2480846165 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 46537783 ps |
| CPU time | 6.92 seconds |
| Started | Feb 07 03:41:57 PM PST 24 |
| Finished | Feb 07 03:42:05 PM PST 24 |
| Peak memory | 211604 kb |
| Host | smart-6a87cbae-f3c0-465a-90ab-d819963a9ed3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2480846165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2480846165 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1171540591 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 401326153 ps |
| CPU time | 45.25 seconds |
| Started | Feb 07 03:42:18 PM PST 24 |
| Finished | Feb 07 03:43:03 PM PST 24 |
| Peak memory | 211596 kb |
| Host | smart-44b4ca5c-7646-4dc2-9274-96af1a2d19e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1171540591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1171540591 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1806818070 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 56743982448 ps |
| CPU time | 270.79 seconds |
| Started | Feb 07 03:42:15 PM PST 24 |
| Finished | Feb 07 03:46:46 PM PST 24 |
| Peak memory | 211620 kb |
| Host | smart-14dcff6a-7a24-4c3d-bce9-829446c66be3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1806818070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.1806818070 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1719720762 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 120360407 ps |
| CPU time | 6.06 seconds |
| Started | Feb 07 03:42:14 PM PST 24 |
| Finished | Feb 07 03:42:21 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-7746f8c2-fc52-407d-915d-9eed97fc889e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1719720762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1719720762 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.3022770737 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1094568676 ps |
| CPU time | 10.76 seconds |
| Started | Feb 07 03:42:26 PM PST 24 |
| Finished | Feb 07 03:42:37 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-3ff3898d-95d1-495c-ac89-d3095fcdaa03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3022770737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3022770737 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.2767155209 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 523628393 ps |
| CPU time | 12.32 seconds |
| Started | Feb 07 03:42:06 PM PST 24 |
| Finished | Feb 07 03:42:19 PM PST 24 |
| Peak memory | 211544 kb |
| Host | smart-0c3de1a8-8450-4b7c-8eff-f8b0acf6ed53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2767155209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2767155209 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1117155076 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 79087913259 ps |
| CPU time | 196.79 seconds |
| Started | Feb 07 03:42:05 PM PST 24 |
| Finished | Feb 07 03:45:22 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-f77d2620-c861-4ca6-8ca5-ac8ab4605a23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117155076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1117155076 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3933504850 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 20163054897 ps |
| CPU time | 126.2 seconds |
| Started | Feb 07 03:42:09 PM PST 24 |
| Finished | Feb 07 03:44:15 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-783eb43c-1f30-407f-add3-540ffcfb73c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3933504850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3933504850 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.4218176398 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 257584931 ps |
| CPU time | 24.71 seconds |
| Started | Feb 07 03:42:05 PM PST 24 |
| Finished | Feb 07 03:42:30 PM PST 24 |
| Peak memory | 204688 kb |
| Host | smart-c1d40498-9854-4dd5-b9f5-02eb4ad4456e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218176398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.4218176398 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1939002949 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 320434980 ps |
| CPU time | 6.61 seconds |
| Started | Feb 07 03:42:14 PM PST 24 |
| Finished | Feb 07 03:42:22 PM PST 24 |
| Peak memory | 203324 kb |
| Host | smart-3e919384-7e21-49b0-a66d-d349ff0c8270 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1939002949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1939002949 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.861411936 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 291786310 ps |
| CPU time | 3.8 seconds |
| Started | Feb 07 03:42:06 PM PST 24 |
| Finished | Feb 07 03:42:10 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-4663b412-aa23-4e26-a45e-452479804603 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=861411936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.861411936 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2804738741 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 15671602096 ps |
| CPU time | 32.21 seconds |
| Started | Feb 07 03:42:13 PM PST 24 |
| Finished | Feb 07 03:42:45 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-843d0677-71f5-490d-8d8a-557b79eab77e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804738741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2804738741 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.700628125 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 4094946486 ps |
| CPU time | 32.03 seconds |
| Started | Feb 07 03:42:13 PM PST 24 |
| Finished | Feb 07 03:42:46 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-3ac9ec55-8f9d-4c6a-af85-ea48933ec209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=700628125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.700628125 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1912233443 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 35736503 ps |
| CPU time | 2.61 seconds |
| Started | Feb 07 03:42:05 PM PST 24 |
| Finished | Feb 07 03:42:08 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-c2239e66-f418-48ec-9e31-679004360488 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912233443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1912233443 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.3158219734 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2046655595 ps |
| CPU time | 38.16 seconds |
| Started | Feb 07 03:42:15 PM PST 24 |
| Finished | Feb 07 03:42:53 PM PST 24 |
| Peak memory | 206180 kb |
| Host | smart-0fc04fdc-0103-4c96-924f-1d54806d44c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3158219734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3158219734 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3114958321 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 8865073930 ps |
| CPU time | 201.49 seconds |
| Started | Feb 07 03:42:14 PM PST 24 |
| Finished | Feb 07 03:45:37 PM PST 24 |
| Peak memory | 209160 kb |
| Host | smart-e1cb12b5-5b35-402d-9ea3-a3e0fc14e6dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3114958321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3114958321 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.718092128 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 212688617 ps |
| CPU time | 79.58 seconds |
| Started | Feb 07 03:42:15 PM PST 24 |
| Finished | Feb 07 03:43:35 PM PST 24 |
| Peak memory | 207788 kb |
| Host | smart-5f64bf15-f7f4-4dd8-9538-afa535632bff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=718092128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand _reset.718092128 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1934933003 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 114586235 ps |
| CPU time | 15.97 seconds |
| Started | Feb 07 03:42:16 PM PST 24 |
| Finished | Feb 07 03:42:32 PM PST 24 |
| Peak memory | 211608 kb |
| Host | smart-2ad666bb-574f-489b-839a-76a4f8352352 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1934933003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.1934933003 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.694965433 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 61450794 ps |
| CPU time | 6.95 seconds |
| Started | Feb 07 03:42:14 PM PST 24 |
| Finished | Feb 07 03:42:22 PM PST 24 |
| Peak memory | 204612 kb |
| Host | smart-32fac1bc-8603-44bd-bf64-8908e32ab637 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=694965433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.694965433 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2143031112 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 876358261 ps |
| CPU time | 33.38 seconds |
| Started | Feb 07 03:42:18 PM PST 24 |
| Finished | Feb 07 03:42:51 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-0f6b2a84-3fb3-40e2-955d-0cecfa2cccc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2143031112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2143031112 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3854518358 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 41631834094 ps |
| CPU time | 313.35 seconds |
| Started | Feb 07 03:43:11 PM PST 24 |
| Finished | Feb 07 03:48:24 PM PST 24 |
| Peak memory | 211688 kb |
| Host | smart-327193b6-c5ec-42fe-8b09-20a12066235e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3854518358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.3854518358 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2912953803 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 527702306 ps |
| CPU time | 9.9 seconds |
| Started | Feb 07 03:42:30 PM PST 24 |
| Finished | Feb 07 03:42:40 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-fbccb085-0297-4908-8b4e-383b116b78c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2912953803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2912953803 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.555181498 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 832160471 ps |
| CPU time | 32.6 seconds |
| Started | Feb 07 03:42:31 PM PST 24 |
| Finished | Feb 07 03:43:04 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-ee9a5ecb-4f55-48b8-a2d1-f973e6543762 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=555181498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.555181498 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.65528698 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1090222952 ps |
| CPU time | 38.4 seconds |
| Started | Feb 07 03:42:20 PM PST 24 |
| Finished | Feb 07 03:42:58 PM PST 24 |
| Peak memory | 211576 kb |
| Host | smart-914b6b95-0377-41bb-bed6-6f4275385317 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=65528698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.65528698 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.939177185 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 21427909310 ps |
| CPU time | 41.08 seconds |
| Started | Feb 07 03:42:21 PM PST 24 |
| Finished | Feb 07 03:43:02 PM PST 24 |
| Peak memory | 204584 kb |
| Host | smart-fae66936-a4a7-4b1f-b3e8-f353088a9ce0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=939177185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.939177185 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3517947443 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 25965948522 ps |
| CPU time | 128.74 seconds |
| Started | Feb 07 03:42:20 PM PST 24 |
| Finished | Feb 07 03:44:29 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-e46f883e-6260-4d2f-ab94-5379a765221b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3517947443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3517947443 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1148401990 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 166601145 ps |
| CPU time | 9 seconds |
| Started | Feb 07 03:42:21 PM PST 24 |
| Finished | Feb 07 03:42:30 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-4e3031f4-a0a6-4489-8061-5b46c3812e3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148401990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1148401990 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.3546238816 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 378191453 ps |
| CPU time | 8.04 seconds |
| Started | Feb 07 03:42:21 PM PST 24 |
| Finished | Feb 07 03:42:29 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-c0977d0e-a5ac-4be0-b703-f28cf39381fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3546238816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3546238816 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.666261072 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 43957981 ps |
| CPU time | 2.11 seconds |
| Started | Feb 07 03:42:15 PM PST 24 |
| Finished | Feb 07 03:42:17 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-30bbe0cb-6293-4901-ac5e-d3a3060c4e1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=666261072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.666261072 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2375768019 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7123133567 ps |
| CPU time | 33.5 seconds |
| Started | Feb 07 03:42:16 PM PST 24 |
| Finished | Feb 07 03:42:50 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-91048361-5abb-4713-8889-e4436b44f7a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375768019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2375768019 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.939271834 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 4975563158 ps |
| CPU time | 33.44 seconds |
| Started | Feb 07 03:42:21 PM PST 24 |
| Finished | Feb 07 03:42:54 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-bac2925e-5e2b-4728-8874-0f21b0660214 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=939271834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.939271834 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.998995186 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 29925523 ps |
| CPU time | 2.74 seconds |
| Started | Feb 07 03:42:14 PM PST 24 |
| Finished | Feb 07 03:42:17 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-36e32843-ba95-463c-b12b-0b058ca33a79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998995186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.998995186 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.1965254820 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 10423872661 ps |
| CPU time | 164.07 seconds |
| Started | Feb 07 03:42:29 PM PST 24 |
| Finished | Feb 07 03:45:13 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-1a86b4ec-c49e-443b-9ee9-177c25d2d894 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1965254820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1965254820 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1668704493 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 7917943418 ps |
| CPU time | 157.02 seconds |
| Started | Feb 07 03:42:28 PM PST 24 |
| Finished | Feb 07 03:45:05 PM PST 24 |
| Peak memory | 208740 kb |
| Host | smart-d41051a1-b7c3-43a6-9263-fc94b29dd93c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1668704493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1668704493 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1814617201 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 18271062590 ps |
| CPU time | 331.99 seconds |
| Started | Feb 07 03:42:28 PM PST 24 |
| Finished | Feb 07 03:48:01 PM PST 24 |
| Peak memory | 208896 kb |
| Host | smart-a667bf43-d7ca-4dfd-afae-b383215a0198 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1814617201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.1814617201 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.1577411286 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 1836983893 ps |
| CPU time | 269.59 seconds |
| Started | Feb 07 03:42:28 PM PST 24 |
| Finished | Feb 07 03:46:58 PM PST 24 |
| Peak memory | 221352 kb |
| Host | smart-44d19d3d-a248-4828-a752-bf313dce929f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1577411286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.1577411286 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.1847579795 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 213612148 ps |
| CPU time | 5.06 seconds |
| Started | Feb 07 03:42:28 PM PST 24 |
| Finished | Feb 07 03:42:34 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-7ea1de18-c54b-43e2-b652-1d8693a02dd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1847579795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1847579795 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.4201766697 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1591423170 ps |
| CPU time | 57.25 seconds |
| Started | Feb 07 03:37:47 PM PST 24 |
| Finished | Feb 07 03:38:45 PM PST 24 |
| Peak memory | 206228 kb |
| Host | smart-10058f6b-a5de-427c-b7df-d85d69b3ca25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4201766697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.4201766697 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3484981632 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 4280560371 ps |
| CPU time | 30.53 seconds |
| Started | Feb 07 03:37:52 PM PST 24 |
| Finished | Feb 07 03:38:25 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-9c0d81a2-22a3-421f-94a1-3344d0c01e4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3484981632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.3484981632 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1830122940 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 3592761472 ps |
| CPU time | 34.3 seconds |
| Started | Feb 07 03:37:53 PM PST 24 |
| Finished | Feb 07 03:38:29 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-b179eb87-05ad-42a2-905a-089fa73ecf84 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1830122940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1830122940 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.4134368242 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 368254808 ps |
| CPU time | 11.68 seconds |
| Started | Feb 07 03:37:51 PM PST 24 |
| Finished | Feb 07 03:38:03 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-16472514-27ec-43b2-a415-1616673c0672 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4134368242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.4134368242 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.4112253592 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1470746947 ps |
| CPU time | 14.12 seconds |
| Started | Feb 07 03:37:47 PM PST 24 |
| Finished | Feb 07 03:38:02 PM PST 24 |
| Peak memory | 211516 kb |
| Host | smart-914d358f-b677-4395-b25c-10beb28b4330 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4112253592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.4112253592 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3472693861 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 66683146689 ps |
| CPU time | 254.37 seconds |
| Started | Feb 07 03:37:50 PM PST 24 |
| Finished | Feb 07 03:42:06 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-0ed637d2-f8b3-41e1-932a-e70fdedb85da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472693861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3472693861 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.3773699559 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 49075946110 ps |
| CPU time | 284.44 seconds |
| Started | Feb 07 03:37:47 PM PST 24 |
| Finished | Feb 07 03:42:32 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-e08c59cb-776a-441f-b3e8-edf73531ce4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3773699559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3773699559 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2188375071 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 299063232 ps |
| CPU time | 22.21 seconds |
| Started | Feb 07 03:37:49 PM PST 24 |
| Finished | Feb 07 03:38:14 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-cb3fce91-bd16-4482-9206-ed9b349c21d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188375071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2188375071 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.1038600347 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2308499579 ps |
| CPU time | 15.87 seconds |
| Started | Feb 07 03:37:49 PM PST 24 |
| Finished | Feb 07 03:38:08 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-13d0ad68-0283-4a5a-8bed-bec15dbb57b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1038600347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1038600347 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.2238200680 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 117516249 ps |
| CPU time | 3.49 seconds |
| Started | Feb 07 03:37:36 PM PST 24 |
| Finished | Feb 07 03:37:40 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-266daa44-d3fc-4f42-abf7-7d939a6b51b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2238200680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2238200680 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3362524266 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 8993345631 ps |
| CPU time | 33.84 seconds |
| Started | Feb 07 03:37:41 PM PST 24 |
| Finished | Feb 07 03:38:15 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-7e4c4da0-a8d4-4af2-9d4e-31de397a5a13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362524266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3362524266 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.4168737045 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3183441189 ps |
| CPU time | 28.67 seconds |
| Started | Feb 07 03:37:50 PM PST 24 |
| Finished | Feb 07 03:38:20 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-45c359c8-828b-4f36-a904-b8f1e6b40c3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4168737045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.4168737045 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.62279951 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 23295251 ps |
| CPU time | 2.32 seconds |
| Started | Feb 07 03:37:36 PM PST 24 |
| Finished | Feb 07 03:37:40 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-179659ee-45a3-48aa-9e83-dcac75f609fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62279951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.62279951 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.451995068 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 7576824006 ps |
| CPU time | 264.28 seconds |
| Started | Feb 07 03:37:59 PM PST 24 |
| Finished | Feb 07 03:42:26 PM PST 24 |
| Peak memory | 207320 kb |
| Host | smart-c7324adc-5762-4125-8225-0fc80a1f830f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=451995068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.451995068 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.2586701742 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 578168550 ps |
| CPU time | 57.15 seconds |
| Started | Feb 07 03:37:53 PM PST 24 |
| Finished | Feb 07 03:38:52 PM PST 24 |
| Peak memory | 205684 kb |
| Host | smart-187f4d8f-18cd-4115-a7f8-d5141a8ee22b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2586701742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2586701742 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.2085433156 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 986079829 ps |
| CPU time | 316.28 seconds |
| Started | Feb 07 03:37:51 PM PST 24 |
| Finished | Feb 07 03:43:08 PM PST 24 |
| Peak memory | 211528 kb |
| Host | smart-f024195a-8314-42d7-9cd4-3883368e8d37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2085433156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.2085433156 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.560505271 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 108007562 ps |
| CPU time | 16.15 seconds |
| Started | Feb 07 03:37:50 PM PST 24 |
| Finished | Feb 07 03:38:08 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-eeb01338-6cc9-4cd2-b721-cf644a6b094d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=560505271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese t_error.560505271 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.57905875 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 102983440 ps |
| CPU time | 13.42 seconds |
| Started | Feb 07 03:37:59 PM PST 24 |
| Finished | Feb 07 03:38:15 PM PST 24 |
| Peak memory | 204616 kb |
| Host | smart-755bb492-449f-4e57-ae5a-8489c5d0ec9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=57905875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.57905875 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.1941032783 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1100884257 ps |
| CPU time | 46.48 seconds |
| Started | Feb 07 03:42:32 PM PST 24 |
| Finished | Feb 07 03:43:19 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-3d52f3df-4de9-42c5-bdf1-ed869e1869f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941032783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.1941032783 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3782128484 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 66371210085 ps |
| CPU time | 174.98 seconds |
| Started | Feb 07 03:42:38 PM PST 24 |
| Finished | Feb 07 03:45:33 PM PST 24 |
| Peak memory | 211492 kb |
| Host | smart-e292737e-6517-4b96-9436-85424aae55a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3782128484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.3782128484 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.713844761 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 14620320 ps |
| CPU time | 1.62 seconds |
| Started | Feb 07 03:42:39 PM PST 24 |
| Finished | Feb 07 03:42:41 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-d44cc5ac-2786-4abc-995d-e99d61f0d068 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=713844761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.713844761 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.2416512212 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 270434570 ps |
| CPU time | 9.88 seconds |
| Started | Feb 07 03:42:36 PM PST 24 |
| Finished | Feb 07 03:42:46 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-cd84d29b-db38-4464-873c-bffbebb18ec3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2416512212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2416512212 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.1164339911 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 554135536 ps |
| CPU time | 13.01 seconds |
| Started | Feb 07 03:42:27 PM PST 24 |
| Finished | Feb 07 03:42:41 PM PST 24 |
| Peak memory | 211600 kb |
| Host | smart-157f6ccc-f73e-4f83-835f-621019bfea49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1164339911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1164339911 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.753357516 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 26292139713 ps |
| CPU time | 171.07 seconds |
| Started | Feb 07 03:42:30 PM PST 24 |
| Finished | Feb 07 03:45:21 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-e62e376b-82ef-487a-8e8c-dafdc60180b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=753357516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.753357516 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1658704123 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 40530773755 ps |
| CPU time | 192.18 seconds |
| Started | Feb 07 03:42:38 PM PST 24 |
| Finished | Feb 07 03:45:51 PM PST 24 |
| Peak memory | 211468 kb |
| Host | smart-fb6525e1-39c4-4b82-92b6-5cddcd606e14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1658704123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1658704123 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.1173268523 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 105665156 ps |
| CPU time | 7.7 seconds |
| Started | Feb 07 03:42:28 PM PST 24 |
| Finished | Feb 07 03:42:36 PM PST 24 |
| Peak memory | 211600 kb |
| Host | smart-900018d5-472a-41cb-bce7-fddc025431d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173268523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1173268523 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.235479058 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1814719024 ps |
| CPU time | 25.69 seconds |
| Started | Feb 07 03:42:31 PM PST 24 |
| Finished | Feb 07 03:42:57 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-6abbd70b-3103-4ffc-9af7-83b99c07dd89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=235479058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.235479058 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.3936448290 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 795757948 ps |
| CPU time | 4.35 seconds |
| Started | Feb 07 03:42:27 PM PST 24 |
| Finished | Feb 07 03:42:32 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-9617bcf9-2b62-40c5-b3fa-bfa34eb8d11d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3936448290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3936448290 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.167248559 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 11301158395 ps |
| CPU time | 34.26 seconds |
| Started | Feb 07 03:42:26 PM PST 24 |
| Finished | Feb 07 03:43:01 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-6b424755-2287-4109-8add-e1bc2315305c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=167248559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.167248559 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3105078246 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 3520624223 ps |
| CPU time | 27.86 seconds |
| Started | Feb 07 03:42:31 PM PST 24 |
| Finished | Feb 07 03:42:59 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-8f73dadb-7605-4a39-ad7d-7bae06cb1e39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3105078246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3105078246 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1554970840 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 37052272 ps |
| CPU time | 2.5 seconds |
| Started | Feb 07 03:42:30 PM PST 24 |
| Finished | Feb 07 03:42:33 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-07c4ab75-d8e4-44bf-9346-e33830dfa442 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554970840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1554970840 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1931334260 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2127859208 ps |
| CPU time | 216.91 seconds |
| Started | Feb 07 03:42:31 PM PST 24 |
| Finished | Feb 07 03:46:09 PM PST 24 |
| Peak memory | 208492 kb |
| Host | smart-e10bdc85-6ec9-43cc-bbf8-e5e34f6efa03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1931334260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1931334260 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3926324164 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1205377251 ps |
| CPU time | 140.44 seconds |
| Started | Feb 07 03:42:39 PM PST 24 |
| Finished | Feb 07 03:44:59 PM PST 24 |
| Peak memory | 208476 kb |
| Host | smart-f3665860-de0d-4fa2-b778-ec8f70051d17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3926324164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3926324164 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.360446315 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1124212676 ps |
| CPU time | 226.38 seconds |
| Started | Feb 07 03:42:38 PM PST 24 |
| Finished | Feb 07 03:46:25 PM PST 24 |
| Peak memory | 208232 kb |
| Host | smart-e605fde7-75be-4d7e-8b22-c6b2b236e5e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=360446315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand _reset.360446315 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1620516001 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 12948289484 ps |
| CPU time | 547.74 seconds |
| Started | Feb 07 03:42:41 PM PST 24 |
| Finished | Feb 07 03:51:49 PM PST 24 |
| Peak memory | 225960 kb |
| Host | smart-8ef1fd91-8e32-4df8-9144-068ed6d9e6a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1620516001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.1620516001 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.1708772100 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 274970272 ps |
| CPU time | 9.11 seconds |
| Started | Feb 07 03:42:40 PM PST 24 |
| Finished | Feb 07 03:42:50 PM PST 24 |
| Peak memory | 204688 kb |
| Host | smart-79792059-d05b-42dc-9aeb-73b732c609ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1708772100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1708772100 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3151880713 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 18028008 ps |
| CPU time | 2.74 seconds |
| Started | Feb 07 03:42:47 PM PST 24 |
| Finished | Feb 07 03:42:50 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-d8a0a1b6-8741-4bcc-8795-cf681b15a8c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3151880713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3151880713 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3838845155 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 133293759 ps |
| CPU time | 13.83 seconds |
| Started | Feb 07 03:42:47 PM PST 24 |
| Finished | Feb 07 03:43:01 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-c25db5be-08a3-4ac1-8d0f-b73f53d4745c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3838845155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3838845155 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.3524558591 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 242847948 ps |
| CPU time | 6.35 seconds |
| Started | Feb 07 03:42:48 PM PST 24 |
| Finished | Feb 07 03:42:54 PM PST 24 |
| Peak memory | 203368 kb |
| Host | smart-30216bbe-b569-4864-b94c-9b6099df3142 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3524558591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3524558591 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.3321183596 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 881401844 ps |
| CPU time | 19.95 seconds |
| Started | Feb 07 03:42:48 PM PST 24 |
| Finished | Feb 07 03:43:08 PM PST 24 |
| Peak memory | 204376 kb |
| Host | smart-4a1f6f37-0a81-4aa5-abbf-96a230219e73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3321183596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3321183596 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2024240943 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4775662430 ps |
| CPU time | 29.34 seconds |
| Started | Feb 07 03:42:50 PM PST 24 |
| Finished | Feb 07 03:43:20 PM PST 24 |
| Peak memory | 211644 kb |
| Host | smart-c37c8be9-e54c-44f2-ac2b-0d559255951b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024240943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2024240943 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3443748830 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 42264060590 ps |
| CPU time | 213.04 seconds |
| Started | Feb 07 03:42:53 PM PST 24 |
| Finished | Feb 07 03:46:26 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-d7fb8de5-ea74-4e36-b29f-01d22678a5c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3443748830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3443748830 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1077049974 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 15799586 ps |
| CPU time | 2.09 seconds |
| Started | Feb 07 03:42:51 PM PST 24 |
| Finished | Feb 07 03:42:54 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-8825e83c-f165-4cc7-adb5-28f2f54050f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077049974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1077049974 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.884356927 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 5172487320 ps |
| CPU time | 19.87 seconds |
| Started | Feb 07 03:42:52 PM PST 24 |
| Finished | Feb 07 03:43:12 PM PST 24 |
| Peak memory | 204428 kb |
| Host | smart-d70d4121-6176-4938-97e4-b3001140a234 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=884356927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.884356927 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.460012549 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 80381224 ps |
| CPU time | 2.56 seconds |
| Started | Feb 07 03:42:39 PM PST 24 |
| Finished | Feb 07 03:42:42 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-dbe3312d-133b-4877-a8e5-7ac98899b222 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=460012549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.460012549 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3746691054 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 20909522671 ps |
| CPU time | 40.29 seconds |
| Started | Feb 07 03:42:39 PM PST 24 |
| Finished | Feb 07 03:43:19 PM PST 24 |
| Peak memory | 203520 kb |
| Host | smart-f9b67584-f067-4381-aa58-78ddf1e2aab3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746691054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3746691054 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2588127596 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3642847089 ps |
| CPU time | 27.82 seconds |
| Started | Feb 07 03:42:47 PM PST 24 |
| Finished | Feb 07 03:43:15 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-77e747ca-8fd6-4bc2-a4d2-bdbec5de1f71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2588127596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2588127596 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3042586133 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 49103679 ps |
| CPU time | 2.47 seconds |
| Started | Feb 07 03:42:39 PM PST 24 |
| Finished | Feb 07 03:42:42 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-bd8cba7f-466f-441f-95f2-032894bbd9ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042586133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3042586133 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.1835034944 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 432505619 ps |
| CPU time | 20.3 seconds |
| Started | Feb 07 03:42:48 PM PST 24 |
| Finished | Feb 07 03:43:09 PM PST 24 |
| Peak memory | 205276 kb |
| Host | smart-9e3fda11-0648-438e-b37f-7d4b29e4223f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1835034944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1835034944 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3422603885 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2285014958 ps |
| CPU time | 28.15 seconds |
| Started | Feb 07 03:42:53 PM PST 24 |
| Finished | Feb 07 03:43:22 PM PST 24 |
| Peak memory | 203952 kb |
| Host | smart-c67efd12-6b1a-4397-b2d0-692fdf276f00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3422603885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3422603885 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2649621246 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 617290202 ps |
| CPU time | 223.1 seconds |
| Started | Feb 07 03:42:52 PM PST 24 |
| Finished | Feb 07 03:46:36 PM PST 24 |
| Peak memory | 208476 kb |
| Host | smart-09b49f84-db0a-41aa-b5ea-3b7848d86f80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2649621246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.2649621246 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.1746185414 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 738771257 ps |
| CPU time | 123.29 seconds |
| Started | Feb 07 03:42:51 PM PST 24 |
| Finished | Feb 07 03:44:55 PM PST 24 |
| Peak memory | 209656 kb |
| Host | smart-f701c02f-4e17-488b-b1a4-01ca8e4d3f7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1746185414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.1746185414 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.617821302 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 34110902 ps |
| CPU time | 2.12 seconds |
| Started | Feb 07 03:42:48 PM PST 24 |
| Finished | Feb 07 03:42:50 PM PST 24 |
| Peak memory | 203308 kb |
| Host | smart-d2ad9dfb-1f11-434a-b559-1ef134f3dc4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=617821302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.617821302 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1700926811 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 333214628 ps |
| CPU time | 31.54 seconds |
| Started | Feb 07 03:43:02 PM PST 24 |
| Finished | Feb 07 03:43:35 PM PST 24 |
| Peak memory | 205912 kb |
| Host | smart-0535cfa0-bc49-4016-bae0-55948ba74119 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1700926811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1700926811 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1743021006 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 60129499962 ps |
| CPU time | 538.89 seconds |
| Started | Feb 07 03:42:54 PM PST 24 |
| Finished | Feb 07 03:51:53 PM PST 24 |
| Peak memory | 206832 kb |
| Host | smart-8658b1f2-763d-4a32-bca4-7f219772d703 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1743021006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.1743021006 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4126368903 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 15139075 ps |
| CPU time | 1.82 seconds |
| Started | Feb 07 03:43:05 PM PST 24 |
| Finished | Feb 07 03:43:08 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-d3247c16-2402-4ef6-af99-e9c8cdb438d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4126368903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.4126368903 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.4105088515 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 336238328 ps |
| CPU time | 22.4 seconds |
| Started | Feb 07 03:43:05 PM PST 24 |
| Finished | Feb 07 03:43:29 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-9c985843-b51e-4fd3-a5f7-31b93f4fea97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4105088515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.4105088515 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.1771491654 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 11938149 ps |
| CPU time | 2.02 seconds |
| Started | Feb 07 03:42:55 PM PST 24 |
| Finished | Feb 07 03:42:57 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-524909b4-832f-43f2-b773-28345b15f63c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1771491654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1771491654 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3078633910 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 65070285216 ps |
| CPU time | 104.36 seconds |
| Started | Feb 07 03:42:53 PM PST 24 |
| Finished | Feb 07 03:44:38 PM PST 24 |
| Peak memory | 204680 kb |
| Host | smart-7dc551f9-25cd-49b0-9f4c-6bad9855a2f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078633910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3078633910 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.441865 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 20941425599 ps |
| CPU time | 156.59 seconds |
| Started | Feb 07 03:42:55 PM PST 24 |
| Finished | Feb 07 03:45:32 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-ce4e1d34-1137-41f0-95d0-0d0b9e3ccad6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=441865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.441865 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.535329493 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 412520814 ps |
| CPU time | 23.17 seconds |
| Started | Feb 07 03:42:54 PM PST 24 |
| Finished | Feb 07 03:43:18 PM PST 24 |
| Peak memory | 204788 kb |
| Host | smart-0c9cfbe7-22b9-4e4d-9803-55ed1e9cf1b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535329493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.535329493 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.1487165860 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2104491904 ps |
| CPU time | 32.68 seconds |
| Started | Feb 07 03:42:51 PM PST 24 |
| Finished | Feb 07 03:43:24 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-84febfcd-762f-4b7c-a415-ade477903cca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1487165860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1487165860 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.522258813 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 25537531 ps |
| CPU time | 2.21 seconds |
| Started | Feb 07 03:42:57 PM PST 24 |
| Finished | Feb 07 03:43:00 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-4e528dc0-539e-495a-b3dd-1e6977b6bd20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=522258813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.522258813 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3249113565 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 4575675691 ps |
| CPU time | 27.69 seconds |
| Started | Feb 07 03:42:55 PM PST 24 |
| Finished | Feb 07 03:43:23 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-3b768a4e-ca71-4b6b-9727-36c3c3778dfd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249113565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3249113565 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.4264001335 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 6084702204 ps |
| CPU time | 30.11 seconds |
| Started | Feb 07 03:42:56 PM PST 24 |
| Finished | Feb 07 03:43:26 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-9fb697fa-3a24-40c9-b84b-8dfbd6764298 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4264001335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.4264001335 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1918716991 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 24567293 ps |
| CPU time | 2.25 seconds |
| Started | Feb 07 03:42:57 PM PST 24 |
| Finished | Feb 07 03:43:00 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-912620ca-02bd-4e39-934f-ca570a191f82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918716991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1918716991 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3020639535 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 787205543 ps |
| CPU time | 84.37 seconds |
| Started | Feb 07 03:43:06 PM PST 24 |
| Finished | Feb 07 03:44:31 PM PST 24 |
| Peak memory | 206924 kb |
| Host | smart-414655ba-89af-4bce-9273-92cdf46b00c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3020639535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3020639535 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2205915558 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 14559350887 ps |
| CPU time | 285.49 seconds |
| Started | Feb 07 03:43:06 PM PST 24 |
| Finished | Feb 07 03:47:52 PM PST 24 |
| Peak memory | 207160 kb |
| Host | smart-3f8012bb-6c8a-448f-bd72-97c5c8024a39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2205915558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2205915558 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3039670025 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 1628782707 ps |
| CPU time | 210.24 seconds |
| Started | Feb 07 03:43:06 PM PST 24 |
| Finished | Feb 07 03:46:37 PM PST 24 |
| Peak memory | 211388 kb |
| Host | smart-efeeca74-74a7-4cd3-9907-926a5b9cd6e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3039670025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3039670025 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.3819264103 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 233833377 ps |
| CPU time | 2.92 seconds |
| Started | Feb 07 03:43:08 PM PST 24 |
| Finished | Feb 07 03:43:11 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-768422d4-f02b-4709-9c7e-ce6403eb27f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3819264103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3819264103 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1561387591 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 86858489 ps |
| CPU time | 12.46 seconds |
| Started | Feb 07 03:43:08 PM PST 24 |
| Finished | Feb 07 03:43:21 PM PST 24 |
| Peak memory | 204552 kb |
| Host | smart-24cca088-9b32-43b7-8e9b-77cdfc3f2b5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1561387591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1561387591 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2060522262 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 71454256460 ps |
| CPU time | 262.39 seconds |
| Started | Feb 07 03:43:17 PM PST 24 |
| Finished | Feb 07 03:47:41 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-8a6f82c9-a878-438c-8e38-f07736906903 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2060522262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.2060522262 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1895989709 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 25888823 ps |
| CPU time | 3.4 seconds |
| Started | Feb 07 03:43:08 PM PST 24 |
| Finished | Feb 07 03:43:12 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-51f0e3ac-668f-48d7-a1a1-eb0dc74ce76c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1895989709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1895989709 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.1748739304 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1280678218 ps |
| CPU time | 18.89 seconds |
| Started | Feb 07 03:43:07 PM PST 24 |
| Finished | Feb 07 03:43:27 PM PST 24 |
| Peak memory | 203288 kb |
| Host | smart-fef93385-80b0-4570-9f84-c7cba9ff8904 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1748739304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1748739304 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.2951132037 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1336750898 ps |
| CPU time | 36.29 seconds |
| Started | Feb 07 03:43:09 PM PST 24 |
| Finished | Feb 07 03:43:46 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-1811287f-7f23-4bca-9f19-ab2dd9f89e08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2951132037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2951132037 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.598021668 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 9744183551 ps |
| CPU time | 34.3 seconds |
| Started | Feb 07 03:43:07 PM PST 24 |
| Finished | Feb 07 03:43:42 PM PST 24 |
| Peak memory | 211644 kb |
| Host | smart-8a08a5a2-4d28-4c91-8054-eb3fc0bde15e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=598021668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.598021668 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1325536643 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 17395717565 ps |
| CPU time | 88.3 seconds |
| Started | Feb 07 03:43:06 PM PST 24 |
| Finished | Feb 07 03:44:35 PM PST 24 |
| Peak memory | 211676 kb |
| Host | smart-30ac0395-b8f3-4f4a-babf-b6fc3396659e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1325536643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1325536643 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2165248183 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 836279812 ps |
| CPU time | 26.45 seconds |
| Started | Feb 07 03:43:07 PM PST 24 |
| Finished | Feb 07 03:43:34 PM PST 24 |
| Peak memory | 204460 kb |
| Host | smart-cbf7075f-d83f-4d09-adf3-428b13bda64e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165248183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2165248183 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.3860115505 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 1027626410 ps |
| CPU time | 21.96 seconds |
| Started | Feb 07 03:43:07 PM PST 24 |
| Finished | Feb 07 03:43:30 PM PST 24 |
| Peak memory | 203908 kb |
| Host | smart-b7b0429c-c109-484a-8229-9e04ac74adcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3860115505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3860115505 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.285760022 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 53275193 ps |
| CPU time | 2.23 seconds |
| Started | Feb 07 03:43:06 PM PST 24 |
| Finished | Feb 07 03:43:09 PM PST 24 |
| Peak memory | 203344 kb |
| Host | smart-d59f8231-d516-44c0-9580-39b1d0932920 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=285760022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.285760022 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2569114394 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 7648735218 ps |
| CPU time | 32.22 seconds |
| Started | Feb 07 03:43:08 PM PST 24 |
| Finished | Feb 07 03:43:41 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-5adb3c34-5dcc-4ec5-9470-3bcb9e61cd0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569114394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2569114394 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.4133856962 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 6630605353 ps |
| CPU time | 33.82 seconds |
| Started | Feb 07 03:43:09 PM PST 24 |
| Finished | Feb 07 03:43:43 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-8fa0cc3e-be19-44f0-807c-459dcab53633 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4133856962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4133856962 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.793672990 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 38199886 ps |
| CPU time | 2.75 seconds |
| Started | Feb 07 03:43:09 PM PST 24 |
| Finished | Feb 07 03:43:13 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-aa8f2210-2850-42d3-9d4a-25ea834f8098 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793672990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.793672990 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.1638391449 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 11391008424 ps |
| CPU time | 241.29 seconds |
| Started | Feb 07 03:43:18 PM PST 24 |
| Finished | Feb 07 03:47:20 PM PST 24 |
| Peak memory | 209116 kb |
| Host | smart-56c2a095-fb1b-4963-a645-7645ae159a28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1638391449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1638391449 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1080537959 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 932869857 ps |
| CPU time | 130.69 seconds |
| Started | Feb 07 03:43:17 PM PST 24 |
| Finished | Feb 07 03:45:29 PM PST 24 |
| Peak memory | 209620 kb |
| Host | smart-16e61813-e8fb-40a0-9480-cb952ec02c5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1080537959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1080537959 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3888107098 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 138326004 ps |
| CPU time | 61.63 seconds |
| Started | Feb 07 03:43:18 PM PST 24 |
| Finished | Feb 07 03:44:20 PM PST 24 |
| Peak memory | 206924 kb |
| Host | smart-aa2da757-f7a9-4679-b2fd-679609cf837d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3888107098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.3888107098 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.2979611123 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1204434444 ps |
| CPU time | 30.6 seconds |
| Started | Feb 07 03:43:08 PM PST 24 |
| Finished | Feb 07 03:43:39 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-d660b887-12bb-463f-8570-270877facf36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2979611123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2979611123 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1261323307 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1621989623 ps |
| CPU time | 54.12 seconds |
| Started | Feb 07 03:43:24 PM PST 24 |
| Finished | Feb 07 03:44:19 PM PST 24 |
| Peak memory | 206368 kb |
| Host | smart-70434265-0256-48d6-863f-999827ca7c89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1261323307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1261323307 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3703870267 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 36596781505 ps |
| CPU time | 105.05 seconds |
| Started | Feb 07 03:43:23 PM PST 24 |
| Finished | Feb 07 03:45:09 PM PST 24 |
| Peak memory | 204732 kb |
| Host | smart-d22f396a-4f58-4d51-9a02-c13c55fe0cbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3703870267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.3703870267 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.885158001 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 382874796 ps |
| CPU time | 3.7 seconds |
| Started | Feb 07 03:43:22 PM PST 24 |
| Finished | Feb 07 03:43:26 PM PST 24 |
| Peak memory | 203336 kb |
| Host | smart-0199d739-87e7-49a3-8ab6-917ef072da55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=885158001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.885158001 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.3698542659 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 270786595 ps |
| CPU time | 20.93 seconds |
| Started | Feb 07 03:43:24 PM PST 24 |
| Finished | Feb 07 03:43:46 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-61337e79-106b-49a4-9388-cdb53038d4b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3698542659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3698542659 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.1854059749 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 103720057 ps |
| CPU time | 17.37 seconds |
| Started | Feb 07 03:43:24 PM PST 24 |
| Finished | Feb 07 03:43:42 PM PST 24 |
| Peak memory | 204612 kb |
| Host | smart-0b41cab9-62b6-44c1-853b-52b700718a28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1854059749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1854059749 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.3848181065 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 14766668100 ps |
| CPU time | 88.86 seconds |
| Started | Feb 07 03:43:21 PM PST 24 |
| Finished | Feb 07 03:44:50 PM PST 24 |
| Peak memory | 211672 kb |
| Host | smart-9537e8dd-3402-4aa4-86e0-4e4c2bd3fea0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848181065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3848181065 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3521347989 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1498249579 ps |
| CPU time | 12.64 seconds |
| Started | Feb 07 03:43:26 PM PST 24 |
| Finished | Feb 07 03:43:42 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-582b7dee-4ade-4321-ac83-5a72ccc5b93d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3521347989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3521347989 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3688359511 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 214844248 ps |
| CPU time | 33.98 seconds |
| Started | Feb 07 03:43:26 PM PST 24 |
| Finished | Feb 07 03:44:04 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-700ecac8-2572-4a86-84a0-0d59d4694813 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688359511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3688359511 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.1742184755 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1027163046 ps |
| CPU time | 22.44 seconds |
| Started | Feb 07 03:43:23 PM PST 24 |
| Finished | Feb 07 03:43:46 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-11ef5161-be90-4e92-9464-e8cf4eda0e3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1742184755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1742184755 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.1482071636 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 113936775 ps |
| CPU time | 3.31 seconds |
| Started | Feb 07 03:43:18 PM PST 24 |
| Finished | Feb 07 03:43:22 PM PST 24 |
| Peak memory | 203296 kb |
| Host | smart-f319c630-5519-47ab-9283-7b73baffece8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1482071636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1482071636 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3147707661 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 19383104830 ps |
| CPU time | 32.24 seconds |
| Started | Feb 07 03:43:17 PM PST 24 |
| Finished | Feb 07 03:43:51 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-c62175c7-dc61-46db-9616-8c4499c510f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147707661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3147707661 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2746908612 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 15256184686 ps |
| CPU time | 36.89 seconds |
| Started | Feb 07 03:43:23 PM PST 24 |
| Finished | Feb 07 03:44:01 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-13c6f54f-6814-4629-8c79-ef0d3a6d3479 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2746908612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2746908612 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2819089236 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 35204483 ps |
| CPU time | 2.32 seconds |
| Started | Feb 07 03:43:19 PM PST 24 |
| Finished | Feb 07 03:43:23 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-b77c60a4-583d-467b-9324-25cfc60c6597 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819089236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2819089236 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.652133568 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 6553579515 ps |
| CPU time | 104.87 seconds |
| Started | Feb 07 03:43:27 PM PST 24 |
| Finished | Feb 07 03:45:15 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-b2c39109-211d-47ef-b7e9-c7d2457149e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=652133568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.652133568 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3861066848 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1495571127 ps |
| CPU time | 115.65 seconds |
| Started | Feb 07 03:43:35 PM PST 24 |
| Finished | Feb 07 03:45:31 PM PST 24 |
| Peak memory | 210108 kb |
| Host | smart-4de1f535-2c9c-4ffd-8813-3e9124042979 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3861066848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3861066848 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2709818038 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 6128645619 ps |
| CPU time | 106.32 seconds |
| Started | Feb 07 03:43:26 PM PST 24 |
| Finished | Feb 07 03:45:16 PM PST 24 |
| Peak memory | 208720 kb |
| Host | smart-450c6ae0-82b2-4ac8-9572-4db5698593a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2709818038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.2709818038 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2825087599 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 342388155 ps |
| CPU time | 74.67 seconds |
| Started | Feb 07 03:43:36 PM PST 24 |
| Finished | Feb 07 03:44:51 PM PST 24 |
| Peak memory | 208404 kb |
| Host | smart-f03d3ba4-8e8b-4ed1-adbd-b9c635c153e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2825087599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.2825087599 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.1517659155 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 149630849 ps |
| CPU time | 5.81 seconds |
| Started | Feb 07 03:43:22 PM PST 24 |
| Finished | Feb 07 03:43:28 PM PST 24 |
| Peak memory | 204480 kb |
| Host | smart-a81e2efd-6c83-402d-8950-fafc6a506fdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1517659155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1517659155 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2245265090 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 480177042 ps |
| CPU time | 6.9 seconds |
| Started | Feb 07 03:43:33 PM PST 24 |
| Finished | Feb 07 03:43:41 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-97924d25-6b98-4617-bf1e-06ba92f2e51a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2245265090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2245265090 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.839963063 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 656339412 ps |
| CPU time | 12.31 seconds |
| Started | Feb 07 03:43:38 PM PST 24 |
| Finished | Feb 07 03:43:51 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-78058e92-14d8-4884-a696-62d5a5b10a8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=839963063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.839963063 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.1294761977 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 45788779 ps |
| CPU time | 5.27 seconds |
| Started | Feb 07 03:43:30 PM PST 24 |
| Finished | Feb 07 03:43:36 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-b210f7f0-1a53-40c7-ac22-91e7422ba2c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1294761977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1294761977 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.2187662638 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 76316987 ps |
| CPU time | 10.46 seconds |
| Started | Feb 07 03:43:35 PM PST 24 |
| Finished | Feb 07 03:43:46 PM PST 24 |
| Peak memory | 211560 kb |
| Host | smart-d9443fef-4dde-4d3c-b58b-5d1058e22bd4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2187662638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2187662638 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.2569971760 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 138331271233 ps |
| CPU time | 192.51 seconds |
| Started | Feb 07 03:43:31 PM PST 24 |
| Finished | Feb 07 03:46:45 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-84657e75-94eb-4483-9527-9f10a3e2f36a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569971760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2569971760 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.2139714809 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 6544787382 ps |
| CPU time | 48 seconds |
| Started | Feb 07 03:43:35 PM PST 24 |
| Finished | Feb 07 03:44:24 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-45cdf2a0-29d2-448d-b473-e42760a2c625 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2139714809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2139714809 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.2318814775 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 178173341 ps |
| CPU time | 4.25 seconds |
| Started | Feb 07 03:43:36 PM PST 24 |
| Finished | Feb 07 03:43:41 PM PST 24 |
| Peak memory | 203600 kb |
| Host | smart-35522053-e286-4466-b47c-c47e57ec68ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318814775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.2318814775 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.1293552278 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 185647007 ps |
| CPU time | 3 seconds |
| Started | Feb 07 03:43:35 PM PST 24 |
| Finished | Feb 07 03:43:39 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-553bc9cf-cecd-409c-a0da-c020820e6293 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1293552278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1293552278 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.115977446 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 422160048 ps |
| CPU time | 3.55 seconds |
| Started | Feb 07 03:43:33 PM PST 24 |
| Finished | Feb 07 03:43:38 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-004b50fe-abef-4202-a7a1-248a5d3a59e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=115977446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.115977446 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1605298193 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 9163357155 ps |
| CPU time | 33.87 seconds |
| Started | Feb 07 03:43:30 PM PST 24 |
| Finished | Feb 07 03:44:05 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-569d77d1-b9e0-47fd-a8de-f229300c027a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605298193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1605298193 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2809420456 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 5925892161 ps |
| CPU time | 29.23 seconds |
| Started | Feb 07 03:43:29 PM PST 24 |
| Finished | Feb 07 03:43:59 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-6b345694-f9de-40c1-baae-02b7ab044b6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2809420456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2809420456 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2262509505 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 176317110 ps |
| CPU time | 2.55 seconds |
| Started | Feb 07 03:43:29 PM PST 24 |
| Finished | Feb 07 03:43:33 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-13bcb6a0-9618-41e0-9a2a-ff12f1efef28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262509505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2262509505 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.883344540 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1312920213 ps |
| CPU time | 119.83 seconds |
| Started | Feb 07 03:43:43 PM PST 24 |
| Finished | Feb 07 03:45:43 PM PST 24 |
| Peak memory | 207996 kb |
| Host | smart-0c784b65-172c-4eb3-860a-0973427706dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=883344540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.883344540 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.251872125 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3288755714 ps |
| CPU time | 108.13 seconds |
| Started | Feb 07 03:43:39 PM PST 24 |
| Finished | Feb 07 03:45:27 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-c74156d9-9da6-4dbd-828d-d9148b243e98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=251872125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.251872125 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1871477779 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 206396997 ps |
| CPU time | 108.07 seconds |
| Started | Feb 07 03:43:42 PM PST 24 |
| Finished | Feb 07 03:45:30 PM PST 24 |
| Peak memory | 207964 kb |
| Host | smart-a463d759-5dda-4342-ab2d-f1ecd32d77b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1871477779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.1871477779 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.23160161 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 6444560429 ps |
| CPU time | 434.69 seconds |
| Started | Feb 07 03:43:38 PM PST 24 |
| Finished | Feb 07 03:50:53 PM PST 24 |
| Peak memory | 219908 kb |
| Host | smart-4ccc847a-3e7f-4c94-9fd2-6e9fbc583b86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=23160161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rese t_error.23160161 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.2226871560 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 46054476 ps |
| CPU time | 2.31 seconds |
| Started | Feb 07 03:43:35 PM PST 24 |
| Finished | Feb 07 03:43:38 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-70609a88-733c-49df-8590-0b9aeb3df997 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2226871560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2226871560 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.4013837483 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 24840808 ps |
| CPU time | 3.56 seconds |
| Started | Feb 07 03:43:46 PM PST 24 |
| Finished | Feb 07 03:43:50 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-ac08f715-a71c-4009-8505-78860f53e5d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4013837483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.4013837483 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.2298703282 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 52990231238 ps |
| CPU time | 131.91 seconds |
| Started | Feb 07 03:43:46 PM PST 24 |
| Finished | Feb 07 03:45:58 PM PST 24 |
| Peak memory | 205984 kb |
| Host | smart-089f6cc9-919b-46df-8e5f-382664bbc72f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2298703282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.2298703282 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2654608499 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 104968226 ps |
| CPU time | 14.1 seconds |
| Started | Feb 07 03:43:46 PM PST 24 |
| Finished | Feb 07 03:44:01 PM PST 24 |
| Peak memory | 203756 kb |
| Host | smart-49ad969b-a78e-4fb5-b3ac-d649293e71a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2654608499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2654608499 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.2079772249 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 23078295 ps |
| CPU time | 3.1 seconds |
| Started | Feb 07 03:43:49 PM PST 24 |
| Finished | Feb 07 03:43:53 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-7ab5c29a-5cde-4078-9ae7-5d51df0ee365 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2079772249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2079772249 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.2256682247 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 396609264 ps |
| CPU time | 9.85 seconds |
| Started | Feb 07 03:43:42 PM PST 24 |
| Finished | Feb 07 03:43:53 PM PST 24 |
| Peak memory | 204296 kb |
| Host | smart-0eb7e1fd-099a-4b91-b324-eab1eb084bfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2256682247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2256682247 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.2510814105 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 25787328652 ps |
| CPU time | 99.09 seconds |
| Started | Feb 07 03:43:42 PM PST 24 |
| Finished | Feb 07 03:45:22 PM PST 24 |
| Peak memory | 211672 kb |
| Host | smart-28201f4a-e35f-4d6e-b967-62cc4ca0014b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510814105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2510814105 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.194389078 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 4476094405 ps |
| CPU time | 30.9 seconds |
| Started | Feb 07 03:43:41 PM PST 24 |
| Finished | Feb 07 03:44:12 PM PST 24 |
| Peak memory | 211692 kb |
| Host | smart-e6dad2a0-b8ff-46fe-a5b8-18eab0c36f8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=194389078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.194389078 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.1518733226 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 53977427 ps |
| CPU time | 7.58 seconds |
| Started | Feb 07 03:43:42 PM PST 24 |
| Finished | Feb 07 03:43:50 PM PST 24 |
| Peak memory | 204376 kb |
| Host | smart-d3a18fff-5d39-4111-bda2-340de37ebea2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518733226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1518733226 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.869277792 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 372515925 ps |
| CPU time | 15.87 seconds |
| Started | Feb 07 03:43:51 PM PST 24 |
| Finished | Feb 07 03:44:07 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-9274d88a-e6b4-41c8-8005-e5b42408edf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=869277792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.869277792 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.1959644770 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 242894503 ps |
| CPU time | 4.27 seconds |
| Started | Feb 07 03:43:41 PM PST 24 |
| Finished | Feb 07 03:43:46 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-d83a278a-3157-46d1-b803-95f0ba6a7034 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1959644770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1959644770 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.259950853 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 8012555779 ps |
| CPU time | 38.06 seconds |
| Started | Feb 07 03:43:42 PM PST 24 |
| Finished | Feb 07 03:44:21 PM PST 24 |
| Peak memory | 203296 kb |
| Host | smart-2dbe722a-0c16-4094-86f3-9415f4a62ee0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=259950853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.259950853 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1884530345 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 6395927557 ps |
| CPU time | 34.66 seconds |
| Started | Feb 07 03:43:41 PM PST 24 |
| Finished | Feb 07 03:44:16 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-a111de05-df30-4c72-ba9c-722b3a4e3723 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1884530345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1884530345 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1101094199 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 27498595 ps |
| CPU time | 2.24 seconds |
| Started | Feb 07 03:43:42 PM PST 24 |
| Finished | Feb 07 03:43:45 PM PST 24 |
| Peak memory | 203364 kb |
| Host | smart-158e1c4e-fcdb-4dd6-ab08-dd9a85176782 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101094199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1101094199 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3235080033 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 11296770795 ps |
| CPU time | 195.67 seconds |
| Started | Feb 07 03:43:48 PM PST 24 |
| Finished | Feb 07 03:47:04 PM PST 24 |
| Peak memory | 206272 kb |
| Host | smart-12cf60f5-c62f-4df3-afcf-0ce07ffb5afe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3235080033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3235080033 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1930806951 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 5219834170 ps |
| CPU time | 71.4 seconds |
| Started | Feb 07 03:43:50 PM PST 24 |
| Finished | Feb 07 03:45:02 PM PST 24 |
| Peak memory | 205064 kb |
| Host | smart-f7624a23-85c5-48e1-bb6b-2ab3aa9f3640 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1930806951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1930806951 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2720187298 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3227719438 ps |
| CPU time | 582.61 seconds |
| Started | Feb 07 03:43:51 PM PST 24 |
| Finished | Feb 07 03:53:34 PM PST 24 |
| Peak memory | 224184 kb |
| Host | smart-7e0e1302-db2a-474e-8482-91a71982c169 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2720187298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.2720187298 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3249561532 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4412109016 ps |
| CPU time | 307.31 seconds |
| Started | Feb 07 03:43:45 PM PST 24 |
| Finished | Feb 07 03:48:52 PM PST 24 |
| Peak memory | 219888 kb |
| Host | smart-559884fe-b3b1-4fae-aca1-aebd35aaa671 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3249561532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.3249561532 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.3981789872 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 233972625 ps |
| CPU time | 8.23 seconds |
| Started | Feb 07 03:43:55 PM PST 24 |
| Finished | Feb 07 03:44:04 PM PST 24 |
| Peak memory | 211536 kb |
| Host | smart-d541176b-477e-4f2c-9ce5-5db2c94dc04e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3981789872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3981789872 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.1511062030 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 137636288 ps |
| CPU time | 16.01 seconds |
| Started | Feb 07 03:43:53 PM PST 24 |
| Finished | Feb 07 03:44:09 PM PST 24 |
| Peak memory | 204552 kb |
| Host | smart-8c85b3d6-8f5d-4160-8124-cad49070810d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1511062030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.1511062030 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2927240573 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 8910015952 ps |
| CPU time | 59.52 seconds |
| Started | Feb 07 03:43:55 PM PST 24 |
| Finished | Feb 07 03:44:55 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-dc871d81-56cf-443d-ba6d-2ef546cf3cbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2927240573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2927240573 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.832699941 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2796169956 ps |
| CPU time | 28.64 seconds |
| Started | Feb 07 03:44:09 PM PST 24 |
| Finished | Feb 07 03:44:38 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-85b51597-3832-4010-a0ef-9fe58e67e7c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=832699941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.832699941 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.3919988299 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 646482868 ps |
| CPU time | 14.26 seconds |
| Started | Feb 07 03:43:54 PM PST 24 |
| Finished | Feb 07 03:44:08 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-c42cb89a-7ec9-4df5-a5c4-6bf6c955a74f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3919988299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3919988299 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.4264848181 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 161949715 ps |
| CPU time | 15.73 seconds |
| Started | Feb 07 03:43:54 PM PST 24 |
| Finished | Feb 07 03:44:10 PM PST 24 |
| Peak memory | 204548 kb |
| Host | smart-88ed248d-0a92-4e3d-b2b3-088879fdc44f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4264848181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.4264848181 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.3168505959 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3657459032 ps |
| CPU time | 11.64 seconds |
| Started | Feb 07 03:43:55 PM PST 24 |
| Finished | Feb 07 03:44:07 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-1a3de211-d1f0-40d4-8dac-b38e5eb0113d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168505959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3168505959 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.4239345401 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 19258909507 ps |
| CPU time | 118.91 seconds |
| Started | Feb 07 03:43:52 PM PST 24 |
| Finished | Feb 07 03:45:51 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-4f887720-9abc-4213-88b0-0a530954d326 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4239345401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.4239345401 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.1239507657 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 190082694 ps |
| CPU time | 24.39 seconds |
| Started | Feb 07 03:43:56 PM PST 24 |
| Finished | Feb 07 03:44:21 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-dc7211db-1d21-4019-805b-ce0bc609ee23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239507657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1239507657 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.3206814387 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1423440385 ps |
| CPU time | 28.05 seconds |
| Started | Feb 07 03:43:53 PM PST 24 |
| Finished | Feb 07 03:44:22 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-06982990-ef7a-4aac-9916-261b4a8c06e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3206814387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3206814387 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.92495509 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 31924056 ps |
| CPU time | 2.53 seconds |
| Started | Feb 07 03:43:46 PM PST 24 |
| Finished | Feb 07 03:43:49 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-34cc08a2-f7a7-46e1-bad1-c1177d8a7a95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=92495509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.92495509 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3184637559 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 9602979590 ps |
| CPU time | 31.6 seconds |
| Started | Feb 07 03:43:52 PM PST 24 |
| Finished | Feb 07 03:44:24 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-276337a0-1153-4fad-a0f9-22f5a5c2d619 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184637559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3184637559 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3838452475 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4673888335 ps |
| CPU time | 29.6 seconds |
| Started | Feb 07 03:43:46 PM PST 24 |
| Finished | Feb 07 03:44:17 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-21c60c80-0bc5-4348-895a-48701e5384ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3838452475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3838452475 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1232733161 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 33943324 ps |
| CPU time | 2.45 seconds |
| Started | Feb 07 03:43:53 PM PST 24 |
| Finished | Feb 07 03:43:56 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-c5365ae4-770c-4883-a062-858c8f33fcee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232733161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1232733161 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.859464596 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1111948285 ps |
| CPU time | 24.11 seconds |
| Started | Feb 07 03:44:11 PM PST 24 |
| Finished | Feb 07 03:44:35 PM PST 24 |
| Peak memory | 205344 kb |
| Host | smart-6e59b1e4-d65b-4178-bfde-b008508d4bc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=859464596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.859464596 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.798452284 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1373765273 ps |
| CPU time | 49.07 seconds |
| Started | Feb 07 03:44:00 PM PST 24 |
| Finished | Feb 07 03:44:49 PM PST 24 |
| Peak memory | 203992 kb |
| Host | smart-23672073-9ced-4c0d-bf2b-79f2a7f5458f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=798452284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.798452284 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.605848718 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 6198348694 ps |
| CPU time | 384.34 seconds |
| Started | Feb 07 03:44:01 PM PST 24 |
| Finished | Feb 07 03:50:26 PM PST 24 |
| Peak memory | 219972 kb |
| Host | smart-1734c5f1-9cc5-47b2-a72f-6995c938c3cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=605848718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res et_error.605848718 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.3001400500 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 334204741 ps |
| CPU time | 7.27 seconds |
| Started | Feb 07 03:43:52 PM PST 24 |
| Finished | Feb 07 03:44:00 PM PST 24 |
| Peak memory | 204764 kb |
| Host | smart-bdb73a68-93a3-4266-94fc-daa2b4d8165b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3001400500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3001400500 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.489491996 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 426785881 ps |
| CPU time | 12.72 seconds |
| Started | Feb 07 03:44:00 PM PST 24 |
| Finished | Feb 07 03:44:13 PM PST 24 |
| Peak memory | 204500 kb |
| Host | smart-94e3bc46-c547-44bb-9089-b21b80f3edf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=489491996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.489491996 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1097426145 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 418017039 ps |
| CPU time | 4.48 seconds |
| Started | Feb 07 03:44:07 PM PST 24 |
| Finished | Feb 07 03:44:12 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-ea480157-e33f-4b63-a0fa-b1c9e778be2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1097426145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1097426145 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.2473765365 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 49123395 ps |
| CPU time | 2.75 seconds |
| Started | Feb 07 03:44:06 PM PST 24 |
| Finished | Feb 07 03:44:09 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-739036cd-2a4d-4724-b577-963a4238561e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2473765365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2473765365 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.2937544515 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 288332662 ps |
| CPU time | 10.53 seconds |
| Started | Feb 07 03:44:00 PM PST 24 |
| Finished | Feb 07 03:44:11 PM PST 24 |
| Peak memory | 211608 kb |
| Host | smart-fcaf3c99-a63b-49d6-b43a-4ef831057232 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2937544515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2937544515 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3436768443 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 24812307622 ps |
| CPU time | 139.83 seconds |
| Started | Feb 07 03:44:09 PM PST 24 |
| Finished | Feb 07 03:46:29 PM PST 24 |
| Peak memory | 204692 kb |
| Host | smart-d48852ce-4fdb-4242-8fa2-c29e2e67863d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436768443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3436768443 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2892092341 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 37011534796 ps |
| CPU time | 154.4 seconds |
| Started | Feb 07 03:44:09 PM PST 24 |
| Finished | Feb 07 03:46:43 PM PST 24 |
| Peak memory | 204528 kb |
| Host | smart-27ef71f8-3903-4e8e-9482-4f067014899e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2892092341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2892092341 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.1257314710 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 97561956 ps |
| CPU time | 14.15 seconds |
| Started | Feb 07 03:43:57 PM PST 24 |
| Finished | Feb 07 03:44:12 PM PST 24 |
| Peak memory | 204472 kb |
| Host | smart-e49b347b-fdc6-4b53-ac67-5886ddcc6186 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257314710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1257314710 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.4261777422 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 561076091 ps |
| CPU time | 6.92 seconds |
| Started | Feb 07 03:44:07 PM PST 24 |
| Finished | Feb 07 03:44:14 PM PST 24 |
| Peak memory | 203624 kb |
| Host | smart-6d5ccc7a-a7d7-42cd-9bda-6ecd9a1c3f60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4261777422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.4261777422 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.4069507489 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 227443578 ps |
| CPU time | 3.42 seconds |
| Started | Feb 07 03:43:58 PM PST 24 |
| Finished | Feb 07 03:44:02 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-2c4c28e4-412d-4f06-8ae5-0e6fb96553ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4069507489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.4069507489 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3695820702 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 6873578639 ps |
| CPU time | 34.63 seconds |
| Started | Feb 07 03:43:59 PM PST 24 |
| Finished | Feb 07 03:44:34 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-e69448f0-75b5-4f38-ac70-be19c87b4bd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695820702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3695820702 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.349157333 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 6624553758 ps |
| CPU time | 27.67 seconds |
| Started | Feb 07 03:43:58 PM PST 24 |
| Finished | Feb 07 03:44:26 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-83d8691f-ce66-4173-b631-e917f206b483 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=349157333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.349157333 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.501619174 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 81689714 ps |
| CPU time | 2.27 seconds |
| Started | Feb 07 03:43:58 PM PST 24 |
| Finished | Feb 07 03:44:01 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-5b6e763e-aef7-44a4-9d83-df2741fed4e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501619174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.501619174 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.2079810670 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 6515781 ps |
| CPU time | 0.84 seconds |
| Started | Feb 07 03:44:05 PM PST 24 |
| Finished | Feb 07 03:44:06 PM PST 24 |
| Peak memory | 195196 kb |
| Host | smart-d109d3d9-6857-48ef-baa5-90a1b20580e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2079810670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2079810670 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1730970222 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1209080084 ps |
| CPU time | 114.49 seconds |
| Started | Feb 07 03:44:05 PM PST 24 |
| Finished | Feb 07 03:46:00 PM PST 24 |
| Peak memory | 207264 kb |
| Host | smart-c83a6dfc-38fe-484f-a2ca-a4023348d768 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1730970222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1730970222 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1697232369 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 204171759 ps |
| CPU time | 101.32 seconds |
| Started | Feb 07 03:44:06 PM PST 24 |
| Finished | Feb 07 03:45:47 PM PST 24 |
| Peak memory | 207576 kb |
| Host | smart-8494e2f7-2b5d-4b2f-bd71-9b27adacadbe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1697232369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.1697232369 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3312569732 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 6773855737 ps |
| CPU time | 350.14 seconds |
| Started | Feb 07 03:44:04 PM PST 24 |
| Finished | Feb 07 03:49:55 PM PST 24 |
| Peak memory | 219952 kb |
| Host | smart-56d8c9ed-aacb-4a3d-af32-c9882842a788 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3312569732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.3312569732 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.798700597 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 666409128 ps |
| CPU time | 22.38 seconds |
| Started | Feb 07 03:44:06 PM PST 24 |
| Finished | Feb 07 03:44:29 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-ff1c68aa-6333-4f52-a1d9-eddcbb7ecbdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=798700597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.798700597 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.3177104632 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 299262070 ps |
| CPU time | 39.97 seconds |
| Started | Feb 07 03:44:12 PM PST 24 |
| Finished | Feb 07 03:44:52 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-838ca162-9b42-4528-b542-f772d5810483 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3177104632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3177104632 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.884634444 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 21000358730 ps |
| CPU time | 106.15 seconds |
| Started | Feb 07 03:44:12 PM PST 24 |
| Finished | Feb 07 03:45:58 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-a2bc22b6-f842-4a80-8125-ee18b724a083 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=884634444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slo w_rsp.884634444 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.419027137 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2885577525 ps |
| CPU time | 25.19 seconds |
| Started | Feb 07 03:44:18 PM PST 24 |
| Finished | Feb 07 03:44:44 PM PST 24 |
| Peak memory | 203912 kb |
| Host | smart-bb728747-87f6-41d2-a040-1730e9338092 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=419027137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.419027137 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.2540876459 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 168105212 ps |
| CPU time | 9.6 seconds |
| Started | Feb 07 03:44:19 PM PST 24 |
| Finished | Feb 07 03:44:29 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-475559a8-36f2-4896-80fc-0c678c1ee9ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2540876459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2540876459 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.1206222425 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 329360893 ps |
| CPU time | 7.52 seconds |
| Started | Feb 07 03:44:17 PM PST 24 |
| Finished | Feb 07 03:44:25 PM PST 24 |
| Peak memory | 203892 kb |
| Host | smart-8686e259-de40-486f-a3a2-049e951fa58a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1206222425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.1206222425 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2546792309 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 43318726097 ps |
| CPU time | 218.98 seconds |
| Started | Feb 07 03:44:12 PM PST 24 |
| Finished | Feb 07 03:47:52 PM PST 24 |
| Peak memory | 211740 kb |
| Host | smart-a0631260-c4a8-45b7-a104-2482a84a0214 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546792309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2546792309 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.2353220687 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 10023344487 ps |
| CPU time | 93.76 seconds |
| Started | Feb 07 03:44:18 PM PST 24 |
| Finished | Feb 07 03:45:52 PM PST 24 |
| Peak memory | 204840 kb |
| Host | smart-bfaf0289-2ebf-46b9-b01e-5a3f6f928811 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2353220687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2353220687 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3268851998 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 79318214 ps |
| CPU time | 14.46 seconds |
| Started | Feb 07 03:44:14 PM PST 24 |
| Finished | Feb 07 03:44:29 PM PST 24 |
| Peak memory | 211596 kb |
| Host | smart-fd22c1a8-c7af-439b-a6c8-4e61f520dd54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268851998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3268851998 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.2288097444 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 102484825 ps |
| CPU time | 6.06 seconds |
| Started | Feb 07 03:44:13 PM PST 24 |
| Finished | Feb 07 03:44:19 PM PST 24 |
| Peak memory | 203568 kb |
| Host | smart-40ddddc0-a437-46bc-b26a-b691c2622f9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2288097444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2288097444 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.3305909048 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 130071846 ps |
| CPU time | 2.75 seconds |
| Started | Feb 07 03:44:11 PM PST 24 |
| Finished | Feb 07 03:44:14 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-bcc64a06-457b-4f51-95e7-0f1bd5148ac0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3305909048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3305909048 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3064234840 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4968282604 ps |
| CPU time | 31.08 seconds |
| Started | Feb 07 03:44:04 PM PST 24 |
| Finished | Feb 07 03:44:36 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-67d6b581-c6aa-4285-b8f6-f4f5f2b4e392 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064234840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3064234840 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1948145260 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 11860383178 ps |
| CPU time | 40.95 seconds |
| Started | Feb 07 03:44:17 PM PST 24 |
| Finished | Feb 07 03:44:58 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-bf1f6adb-736d-4c9e-83de-c8264d283b92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1948145260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1948145260 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.265858402 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 57655384 ps |
| CPU time | 2.16 seconds |
| Started | Feb 07 03:44:07 PM PST 24 |
| Finished | Feb 07 03:44:10 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-208a0f9f-04c3-4c0e-b6ae-9eecdf108edf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265858402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.265858402 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.2518328701 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 21835046895 ps |
| CPU time | 167.65 seconds |
| Started | Feb 07 03:44:18 PM PST 24 |
| Finished | Feb 07 03:47:06 PM PST 24 |
| Peak memory | 207656 kb |
| Host | smart-044008cb-d3cd-46bf-8403-434ef1fc1c0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2518328701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2518328701 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3652117622 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1067706119 ps |
| CPU time | 23.52 seconds |
| Started | Feb 07 03:44:20 PM PST 24 |
| Finished | Feb 07 03:44:44 PM PST 24 |
| Peak memory | 204436 kb |
| Host | smart-244d677a-5658-4b9b-85c3-10e3931be0fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3652117622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3652117622 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2581951536 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 272043051 ps |
| CPU time | 70.02 seconds |
| Started | Feb 07 03:44:20 PM PST 24 |
| Finished | Feb 07 03:45:30 PM PST 24 |
| Peak memory | 208164 kb |
| Host | smart-b5465e3b-50c1-441b-9c07-ec7e660b9292 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2581951536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.2581951536 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.1248973158 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 378193084 ps |
| CPU time | 5.71 seconds |
| Started | Feb 07 03:44:20 PM PST 24 |
| Finished | Feb 07 03:44:26 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-9dc12396-1b51-496e-89f2-60603b978700 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1248973158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1248973158 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1251367435 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1185514798 ps |
| CPU time | 41.69 seconds |
| Started | Feb 07 03:38:09 PM PST 24 |
| Finished | Feb 07 03:38:51 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-39327dd9-ffd3-4bbd-b2f6-e16fb3cda93e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1251367435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1251367435 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1599294173 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 130375233400 ps |
| CPU time | 689.79 seconds |
| Started | Feb 07 03:38:15 PM PST 24 |
| Finished | Feb 07 03:49:46 PM PST 24 |
| Peak memory | 211580 kb |
| Host | smart-bd509766-6d06-41e7-b97a-a7396ca012f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1599294173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1599294173 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.251466076 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 272258569 ps |
| CPU time | 12.27 seconds |
| Started | Feb 07 03:38:12 PM PST 24 |
| Finished | Feb 07 03:38:29 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-731d99ed-5f83-4ef2-ad00-57034aad1574 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=251466076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.251466076 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.1567425638 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 126566425 ps |
| CPU time | 16.38 seconds |
| Started | Feb 07 03:38:11 PM PST 24 |
| Finished | Feb 07 03:38:28 PM PST 24 |
| Peak memory | 203368 kb |
| Host | smart-9475c573-cd0f-4a4c-81f7-e39f7589ae67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1567425638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1567425638 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.4182973477 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 1232286533 ps |
| CPU time | 38.61 seconds |
| Started | Feb 07 03:38:03 PM PST 24 |
| Finished | Feb 07 03:38:42 PM PST 24 |
| Peak memory | 204384 kb |
| Host | smart-77b279d1-5214-4f3f-922b-615a3234ee40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4182973477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.4182973477 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3488225496 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 12786279615 ps |
| CPU time | 101.58 seconds |
| Started | Feb 07 03:38:03 PM PST 24 |
| Finished | Feb 07 03:39:46 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-e98d8b3a-df55-42d4-888e-f8fad7e1067d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3488225496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3488225496 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3706542830 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 502198697 ps |
| CPU time | 17.37 seconds |
| Started | Feb 07 03:38:06 PM PST 24 |
| Finished | Feb 07 03:38:24 PM PST 24 |
| Peak memory | 204520 kb |
| Host | smart-da3e105c-946b-4a1d-9708-a91e960913e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706542830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3706542830 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.1976037150 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 716703741 ps |
| CPU time | 15 seconds |
| Started | Feb 07 03:38:13 PM PST 24 |
| Finished | Feb 07 03:38:32 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-5501d9ef-daa6-4ada-a4c5-e2b777b95409 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1976037150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1976037150 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.2089304907 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 28255992 ps |
| CPU time | 2.09 seconds |
| Started | Feb 07 03:37:53 PM PST 24 |
| Finished | Feb 07 03:37:57 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-513a6421-989f-461f-89cb-5cd85cd3dc17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2089304907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2089304907 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3927520041 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 5079165526 ps |
| CPU time | 28.11 seconds |
| Started | Feb 07 03:38:10 PM PST 24 |
| Finished | Feb 07 03:38:39 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-6430515a-8738-4fc4-a3b9-fcbec4faa5bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927520041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3927520041 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3534249465 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4010675615 ps |
| CPU time | 29.24 seconds |
| Started | Feb 07 03:38:03 PM PST 24 |
| Finished | Feb 07 03:38:34 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-541cb571-1fed-47c9-8148-005787cd35ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3534249465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3534249465 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1169959483 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 131912379 ps |
| CPU time | 2.2 seconds |
| Started | Feb 07 03:38:03 PM PST 24 |
| Finished | Feb 07 03:38:07 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-a0d41c13-45dc-4993-a5b4-8ea8401c6903 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169959483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1169959483 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.243801 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 6885861624 ps |
| CPU time | 204.67 seconds |
| Started | Feb 07 03:38:11 PM PST 24 |
| Finished | Feb 07 03:41:36 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-dfe83a4f-ee39-4c12-bedb-80dc1ff1ee39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=243801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.243801 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.254438299 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2185771217 ps |
| CPU time | 52.48 seconds |
| Started | Feb 07 03:38:19 PM PST 24 |
| Finished | Feb 07 03:39:12 PM PST 24 |
| Peak memory | 205608 kb |
| Host | smart-7250d12b-2690-4e66-9cbd-a4b09f84adce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=254438299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.254438299 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3894460533 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 647406324 ps |
| CPU time | 240.78 seconds |
| Started | Feb 07 03:38:19 PM PST 24 |
| Finished | Feb 07 03:42:21 PM PST 24 |
| Peak memory | 208704 kb |
| Host | smart-7b8b67e0-8c64-4df7-8765-6fb11616cfa0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3894460533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.3894460533 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1418417271 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3902364166 ps |
| CPU time | 161.73 seconds |
| Started | Feb 07 03:38:18 PM PST 24 |
| Finished | Feb 07 03:41:02 PM PST 24 |
| Peak memory | 210288 kb |
| Host | smart-982b7dcb-27f9-4a57-b0c9-295ad1d0d8e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1418417271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1418417271 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.3806090968 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 548654146 ps |
| CPU time | 21.38 seconds |
| Started | Feb 07 03:38:12 PM PST 24 |
| Finished | Feb 07 03:38:38 PM PST 24 |
| Peak memory | 204660 kb |
| Host | smart-f1dd6926-c598-4a75-9a24-2e5a98203b04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3806090968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3806090968 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3538267315 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2301372992 ps |
| CPU time | 47.58 seconds |
| Started | Feb 07 03:44:30 PM PST 24 |
| Finished | Feb 07 03:45:18 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-bf9fc8ba-b6ac-4b0b-8988-646b5f73f21f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3538267315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3538267315 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2758855678 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 29780006459 ps |
| CPU time | 221.96 seconds |
| Started | Feb 07 03:44:32 PM PST 24 |
| Finished | Feb 07 03:48:14 PM PST 24 |
| Peak memory | 211612 kb |
| Host | smart-fb32a92a-37ba-49a1-9f8a-38bd0b348c03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2758855678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.2758855678 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.1868657804 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 53877006 ps |
| CPU time | 7.68 seconds |
| Started | Feb 07 03:44:31 PM PST 24 |
| Finished | Feb 07 03:44:39 PM PST 24 |
| Peak memory | 203572 kb |
| Host | smart-b2c8a867-db03-441f-8a5a-bb02ad661b47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1868657804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.1868657804 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.1739761360 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 31418335 ps |
| CPU time | 2.98 seconds |
| Started | Feb 07 03:44:32 PM PST 24 |
| Finished | Feb 07 03:44:35 PM PST 24 |
| Peak memory | 203356 kb |
| Host | smart-fe92b25f-1acf-4cb2-9dd7-84cbd3b9e439 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1739761360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1739761360 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.3880734640 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 670674208 ps |
| CPU time | 21.18 seconds |
| Started | Feb 07 03:44:18 PM PST 24 |
| Finished | Feb 07 03:44:39 PM PST 24 |
| Peak memory | 204552 kb |
| Host | smart-1497b58a-52d3-4794-842a-dfabe1141518 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3880734640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3880734640 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1517751659 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 80779729488 ps |
| CPU time | 216.17 seconds |
| Started | Feb 07 03:44:19 PM PST 24 |
| Finished | Feb 07 03:47:55 PM PST 24 |
| Peak memory | 211728 kb |
| Host | smart-4271d24b-b818-4629-8eb8-3c673e5fc62f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517751659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1517751659 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.934084610 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 21150559503 ps |
| CPU time | 106.14 seconds |
| Started | Feb 07 03:44:30 PM PST 24 |
| Finished | Feb 07 03:46:17 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-29cc03c8-31b8-4ef5-827f-c43026fe0f17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=934084610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.934084610 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.768523229 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 95528478 ps |
| CPU time | 5.13 seconds |
| Started | Feb 07 03:44:18 PM PST 24 |
| Finished | Feb 07 03:44:24 PM PST 24 |
| Peak memory | 204000 kb |
| Host | smart-ad7be251-a83a-4ec5-a6b2-a3a8d2953137 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768523229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.768523229 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.603621393 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 266402356 ps |
| CPU time | 5.25 seconds |
| Started | Feb 07 03:44:32 PM PST 24 |
| Finished | Feb 07 03:44:37 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-37d55c51-302f-4051-b9b9-e677261178a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=603621393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.603621393 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.3209854633 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 39400557 ps |
| CPU time | 2.55 seconds |
| Started | Feb 07 03:44:19 PM PST 24 |
| Finished | Feb 07 03:44:22 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-5b0def33-cfe7-4fea-b3e8-fbfbe8a0d117 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3209854633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3209854633 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.278948680 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 7126369938 ps |
| CPU time | 29.47 seconds |
| Started | Feb 07 03:44:20 PM PST 24 |
| Finished | Feb 07 03:44:50 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-57a8d634-3f02-47e2-8189-14e3aa2aca0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=278948680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.278948680 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.4271820278 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 6404001823 ps |
| CPU time | 32.58 seconds |
| Started | Feb 07 03:44:20 PM PST 24 |
| Finished | Feb 07 03:44:53 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-a0c4a57a-75f5-469d-aaaf-5251c7bf84ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4271820278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.4271820278 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2231090890 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 72158659 ps |
| CPU time | 2.75 seconds |
| Started | Feb 07 03:44:19 PM PST 24 |
| Finished | Feb 07 03:44:22 PM PST 24 |
| Peak memory | 203292 kb |
| Host | smart-145488d0-e0d2-4b8d-b43c-00c7262954e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231090890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2231090890 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1122872949 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 238664189 ps |
| CPU time | 38.65 seconds |
| Started | Feb 07 03:44:33 PM PST 24 |
| Finished | Feb 07 03:45:12 PM PST 24 |
| Peak memory | 205376 kb |
| Host | smart-aeb483f3-76a6-4d9d-9b57-d775d48e9fff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1122872949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1122872949 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.213702019 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 623093048 ps |
| CPU time | 68.89 seconds |
| Started | Feb 07 03:44:33 PM PST 24 |
| Finished | Feb 07 03:45:42 PM PST 24 |
| Peak memory | 204608 kb |
| Host | smart-65b8aec1-f5e6-4375-bc52-611b625dfd7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=213702019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.213702019 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3976460258 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 352277822 ps |
| CPU time | 109.87 seconds |
| Started | Feb 07 03:44:31 PM PST 24 |
| Finished | Feb 07 03:46:21 PM PST 24 |
| Peak memory | 208064 kb |
| Host | smart-ad762b7a-e863-4f6e-90ab-3f5b90206408 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3976460258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.3976460258 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1367826385 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 330260257 ps |
| CPU time | 176.23 seconds |
| Started | Feb 07 03:44:31 PM PST 24 |
| Finished | Feb 07 03:47:27 PM PST 24 |
| Peak memory | 210568 kb |
| Host | smart-6582f3b4-bdb3-4778-981e-3e07befd912b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1367826385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.1367826385 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.662696795 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 4630733385 ps |
| CPU time | 29.87 seconds |
| Started | Feb 07 03:44:30 PM PST 24 |
| Finished | Feb 07 03:45:00 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-e9463dd7-1094-47df-9db3-92b0913901c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=662696795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.662696795 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3212006499 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3572440340 ps |
| CPU time | 82.39 seconds |
| Started | Feb 07 03:44:35 PM PST 24 |
| Finished | Feb 07 03:45:58 PM PST 24 |
| Peak memory | 206760 kb |
| Host | smart-c9e8d53e-eb2c-4351-a745-7a34c173e1c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3212006499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3212006499 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2943606818 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 77844458468 ps |
| CPU time | 243.25 seconds |
| Started | Feb 07 03:44:34 PM PST 24 |
| Finished | Feb 07 03:48:37 PM PST 24 |
| Peak memory | 206144 kb |
| Host | smart-ad87a540-89ce-4398-b53c-01a0083232bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2943606818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.2943606818 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1405339411 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 84728204 ps |
| CPU time | 11.19 seconds |
| Started | Feb 07 03:44:42 PM PST 24 |
| Finished | Feb 07 03:44:54 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-e1b774a6-1b4a-4a58-a9d6-516b2ef24f82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1405339411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1405339411 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.260352808 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 661028189 ps |
| CPU time | 10.45 seconds |
| Started | Feb 07 03:44:42 PM PST 24 |
| Finished | Feb 07 03:44:53 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-12abb662-b31f-4ee1-8e9f-32fb19ae128e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=260352808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.260352808 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.4172152106 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 133496334 ps |
| CPU time | 5.3 seconds |
| Started | Feb 07 03:44:32 PM PST 24 |
| Finished | Feb 07 03:44:38 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-0040c8b8-863a-4cc0-a64e-d9f05052b108 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4172152106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.4172152106 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1989661292 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 19753829830 ps |
| CPU time | 93.99 seconds |
| Started | Feb 07 03:44:31 PM PST 24 |
| Finished | Feb 07 03:46:06 PM PST 24 |
| Peak memory | 211456 kb |
| Host | smart-79d7a0e1-b9bc-4e48-894d-daa80fd47442 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989661292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1989661292 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.433542382 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 33854602831 ps |
| CPU time | 260.19 seconds |
| Started | Feb 07 03:44:35 PM PST 24 |
| Finished | Feb 07 03:48:55 PM PST 24 |
| Peak memory | 205256 kb |
| Host | smart-74738787-19a9-4607-b95c-4f38bff7ee83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=433542382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.433542382 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.2988079844 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 33694444 ps |
| CPU time | 5.54 seconds |
| Started | Feb 07 03:44:34 PM PST 24 |
| Finished | Feb 07 03:44:40 PM PST 24 |
| Peak memory | 203908 kb |
| Host | smart-bc02cab2-b6c2-4e15-b2cc-706b0eaf9a41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988079844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2988079844 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.785434871 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 372327833 ps |
| CPU time | 9.14 seconds |
| Started | Feb 07 03:44:41 PM PST 24 |
| Finished | Feb 07 03:44:51 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-1d4a43ee-a368-4186-8c2d-bd7a51399962 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=785434871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.785434871 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.1721804645 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 160996007 ps |
| CPU time | 3.41 seconds |
| Started | Feb 07 03:44:30 PM PST 24 |
| Finished | Feb 07 03:44:34 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-1b7a5c5a-d10a-45f6-b425-29cfb5660044 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1721804645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1721804645 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2095638898 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 25396258028 ps |
| CPU time | 43.1 seconds |
| Started | Feb 07 03:44:34 PM PST 24 |
| Finished | Feb 07 03:45:17 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-90685ccc-903e-4eef-aae4-3d9c260b5582 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095638898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2095638898 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.416109796 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 8088054410 ps |
| CPU time | 37.19 seconds |
| Started | Feb 07 03:44:33 PM PST 24 |
| Finished | Feb 07 03:45:11 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-ef2be259-0b2a-4bc1-8fe8-30129a29cac2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=416109796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.416109796 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1837127232 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 32560172 ps |
| CPU time | 2.09 seconds |
| Started | Feb 07 03:44:30 PM PST 24 |
| Finished | Feb 07 03:44:33 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-5be4ee0b-6e94-4c21-8f91-11a692f5edaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837127232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1837127232 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1840869080 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 319560458 ps |
| CPU time | 31.89 seconds |
| Started | Feb 07 03:44:43 PM PST 24 |
| Finished | Feb 07 03:45:15 PM PST 24 |
| Peak memory | 205844 kb |
| Host | smart-f55cf61d-d4f3-4261-9d8d-0301f2a52802 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840869080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1840869080 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.1708106687 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1036084645 ps |
| CPU time | 32.25 seconds |
| Started | Feb 07 03:44:42 PM PST 24 |
| Finished | Feb 07 03:45:15 PM PST 24 |
| Peak memory | 205052 kb |
| Host | smart-4eec94cc-e853-4d53-ae77-50c23b58df08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1708106687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1708106687 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3127960280 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 15260107589 ps |
| CPU time | 694.98 seconds |
| Started | Feb 07 03:44:39 PM PST 24 |
| Finished | Feb 07 03:56:14 PM PST 24 |
| Peak memory | 225156 kb |
| Host | smart-c5a15952-db90-4784-bc84-03cd487efa03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3127960280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.3127960280 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2164382617 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 6577208590 ps |
| CPU time | 184.73 seconds |
| Started | Feb 07 03:44:41 PM PST 24 |
| Finished | Feb 07 03:47:46 PM PST 24 |
| Peak memory | 211336 kb |
| Host | smart-928e5b0e-c424-46d9-9402-dd2b7122838d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2164382617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.2164382617 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.2515255547 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1024589306 ps |
| CPU time | 10.19 seconds |
| Started | Feb 07 03:44:42 PM PST 24 |
| Finished | Feb 07 03:44:53 PM PST 24 |
| Peak memory | 204532 kb |
| Host | smart-fdbd4ac6-d443-4283-ad4a-48bdbe3fa50b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2515255547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2515255547 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.712896532 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4262658997 ps |
| CPU time | 30.42 seconds |
| Started | Feb 07 03:44:48 PM PST 24 |
| Finished | Feb 07 03:45:20 PM PST 24 |
| Peak memory | 211672 kb |
| Host | smart-f1deeda2-9ae7-4cd3-aa68-ef68dd5353ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=712896532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.712896532 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.251057920 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 222458693373 ps |
| CPU time | 682.26 seconds |
| Started | Feb 07 03:44:48 PM PST 24 |
| Finished | Feb 07 03:56:12 PM PST 24 |
| Peak memory | 211688 kb |
| Host | smart-60e8c235-03f7-4d9f-9631-73a7634bddbb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=251057920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slo w_rsp.251057920 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2940184029 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 538469691 ps |
| CPU time | 13.55 seconds |
| Started | Feb 07 03:44:49 PM PST 24 |
| Finished | Feb 07 03:45:06 PM PST 24 |
| Peak memory | 203584 kb |
| Host | smart-dc339b1e-53b3-45fc-b584-0e640a438ac9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2940184029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2940184029 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.3403046374 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 779141627 ps |
| CPU time | 22.02 seconds |
| Started | Feb 07 03:44:48 PM PST 24 |
| Finished | Feb 07 03:45:11 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-66e7db69-0182-4872-887d-4c4ae7f37a04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3403046374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3403046374 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.3740869676 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 98072498 ps |
| CPU time | 17.19 seconds |
| Started | Feb 07 03:44:48 PM PST 24 |
| Finished | Feb 07 03:45:06 PM PST 24 |
| Peak memory | 204548 kb |
| Host | smart-8e21e877-97fb-4293-8b2b-e14d28a894ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3740869676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3740869676 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.2809500248 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 11609678791 ps |
| CPU time | 63.33 seconds |
| Started | Feb 07 03:44:46 PM PST 24 |
| Finished | Feb 07 03:45:50 PM PST 24 |
| Peak memory | 204664 kb |
| Host | smart-1c52ee07-c271-4fe3-9da6-a0cbb2fa1d0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809500248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2809500248 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3251523618 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 22434423910 ps |
| CPU time | 179.12 seconds |
| Started | Feb 07 03:44:48 PM PST 24 |
| Finished | Feb 07 03:47:48 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-13a1c95f-f781-4294-acc6-d36b9f9fb899 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3251523618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3251523618 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.2006443882 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 82462550 ps |
| CPU time | 9.18 seconds |
| Started | Feb 07 03:44:47 PM PST 24 |
| Finished | Feb 07 03:44:57 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-be5991c0-d53e-4855-aad8-db06d907b78e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006443882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2006443882 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.1639693815 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 719651779 ps |
| CPU time | 13.77 seconds |
| Started | Feb 07 03:44:49 PM PST 24 |
| Finished | Feb 07 03:45:03 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-07cefae0-b3e2-4a7b-a13e-2876c822f55a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1639693815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1639693815 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.989401389 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 35447983 ps |
| CPU time | 2.14 seconds |
| Started | Feb 07 03:44:40 PM PST 24 |
| Finished | Feb 07 03:44:42 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-f696751e-16ac-4a94-8347-60c042831196 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=989401389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.989401389 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2967431519 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 6500888418 ps |
| CPU time | 31 seconds |
| Started | Feb 07 03:44:40 PM PST 24 |
| Finished | Feb 07 03:45:11 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-c00aff42-d86f-49d6-9044-ba07d72bb9cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967431519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2967431519 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3104216529 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4154864570 ps |
| CPU time | 36.16 seconds |
| Started | Feb 07 03:44:42 PM PST 24 |
| Finished | Feb 07 03:45:19 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-682f9b26-dbdf-4190-a42e-51bd1f1de77b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3104216529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3104216529 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1688400382 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 25333306 ps |
| CPU time | 2.1 seconds |
| Started | Feb 07 03:44:40 PM PST 24 |
| Finished | Feb 07 03:44:43 PM PST 24 |
| Peak memory | 203336 kb |
| Host | smart-c56b809a-d560-4386-aeb3-a9c7ffe49148 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688400382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1688400382 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.1431223086 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2255170515 ps |
| CPU time | 82.21 seconds |
| Started | Feb 07 03:44:47 PM PST 24 |
| Finished | Feb 07 03:46:10 PM PST 24 |
| Peak memory | 207440 kb |
| Host | smart-61e350e3-6a52-4616-8524-929d5926c9eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1431223086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1431223086 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1178135641 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 15918163379 ps |
| CPU time | 128.97 seconds |
| Started | Feb 07 03:44:47 PM PST 24 |
| Finished | Feb 07 03:46:56 PM PST 24 |
| Peak memory | 208216 kb |
| Host | smart-a8c05873-f7d2-45ba-bace-bac22f98225d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1178135641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1178135641 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.362934001 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 364408296 ps |
| CPU time | 108.2 seconds |
| Started | Feb 07 03:44:50 PM PST 24 |
| Finished | Feb 07 03:46:42 PM PST 24 |
| Peak memory | 208260 kb |
| Host | smart-8841fb34-4e17-4f01-bc56-6719f01f0005 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=362934001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand _reset.362934001 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.2600478887 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1295437684 ps |
| CPU time | 279.91 seconds |
| Started | Feb 07 03:44:50 PM PST 24 |
| Finished | Feb 07 03:49:33 PM PST 24 |
| Peak memory | 222780 kb |
| Host | smart-38b91916-98ca-45af-a0bc-b52811806463 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2600478887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.2600478887 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.2871290061 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1054528782 ps |
| CPU time | 13.37 seconds |
| Started | Feb 07 03:44:49 PM PST 24 |
| Finished | Feb 07 03:45:07 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-77f47e99-290b-4479-84bb-da911f479e28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2871290061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2871290061 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.4214935848 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 206356951 ps |
| CPU time | 31.15 seconds |
| Started | Feb 07 03:44:55 PM PST 24 |
| Finished | Feb 07 03:45:27 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-22d37f01-9d51-49ea-bede-d5cab92946fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4214935848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.4214935848 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1547371767 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 94054441363 ps |
| CPU time | 820.08 seconds |
| Started | Feb 07 03:44:55 PM PST 24 |
| Finished | Feb 07 03:58:36 PM PST 24 |
| Peak memory | 207268 kb |
| Host | smart-eba53237-686f-4469-8893-d0f6d77d100f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1547371767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.1547371767 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3725328053 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 399214830 ps |
| CPU time | 11.93 seconds |
| Started | Feb 07 03:45:05 PM PST 24 |
| Finished | Feb 07 03:45:21 PM PST 24 |
| Peak memory | 203552 kb |
| Host | smart-738354a3-e828-4223-bf14-e08237cbdeb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3725328053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3725328053 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.1275965608 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 102625144 ps |
| CPU time | 15.56 seconds |
| Started | Feb 07 03:45:05 PM PST 24 |
| Finished | Feb 07 03:45:25 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-d4b1bceb-e170-46cb-b4f2-d1b80900d3a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1275965608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1275965608 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.3082732041 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 1185183367 ps |
| CPU time | 28.88 seconds |
| Started | Feb 07 03:44:57 PM PST 24 |
| Finished | Feb 07 03:45:30 PM PST 24 |
| Peak memory | 211560 kb |
| Host | smart-d19e0fed-084c-441c-ab8c-82d0675b8240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3082732041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3082732041 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.1792381119 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4669110683 ps |
| CPU time | 24.9 seconds |
| Started | Feb 07 03:45:00 PM PST 24 |
| Finished | Feb 07 03:45:26 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-9d095a1c-e574-4201-bd77-a9003920ded3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792381119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1792381119 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2235451760 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 24033848429 ps |
| CPU time | 223.11 seconds |
| Started | Feb 07 03:45:00 PM PST 24 |
| Finished | Feb 07 03:48:45 PM PST 24 |
| Peak memory | 211656 kb |
| Host | smart-ca25f47f-317a-41f5-ab03-9b23029cccb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2235451760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2235451760 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2889679347 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 113536668 ps |
| CPU time | 7.57 seconds |
| Started | Feb 07 03:44:57 PM PST 24 |
| Finished | Feb 07 03:45:08 PM PST 24 |
| Peak memory | 204588 kb |
| Host | smart-0ad446af-f54d-49c7-b4ea-91d5df2e3671 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889679347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2889679347 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.2580945192 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 186032675 ps |
| CPU time | 4.04 seconds |
| Started | Feb 07 03:45:02 PM PST 24 |
| Finished | Feb 07 03:45:08 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-b04115ee-b3a9-41a1-b63e-ccf395fad0e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2580945192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2580945192 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.2646216909 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 28350552 ps |
| CPU time | 1.97 seconds |
| Started | Feb 07 03:44:48 PM PST 24 |
| Finished | Feb 07 03:44:51 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-3bd61382-0a4f-4cfd-835e-fce094007b31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2646216909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2646216909 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.151605457 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4068379149 ps |
| CPU time | 20.53 seconds |
| Started | Feb 07 03:44:47 PM PST 24 |
| Finished | Feb 07 03:45:08 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-e8ea4aa1-4281-4476-9a0b-b30d322ffda3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=151605457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.151605457 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2414357871 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3768172732 ps |
| CPU time | 33.35 seconds |
| Started | Feb 07 03:44:55 PM PST 24 |
| Finished | Feb 07 03:45:31 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-82fe4740-d67f-49e8-9d3d-4605c16695cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2414357871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2414357871 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.978576942 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 31845624 ps |
| CPU time | 2.43 seconds |
| Started | Feb 07 03:44:47 PM PST 24 |
| Finished | Feb 07 03:44:49 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-fd5afac6-afa5-45c2-ac0e-3ad3c741d9f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978576942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.978576942 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.2453061045 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 2344981697 ps |
| CPU time | 84.51 seconds |
| Started | Feb 07 03:45:06 PM PST 24 |
| Finished | Feb 07 03:46:34 PM PST 24 |
| Peak memory | 207508 kb |
| Host | smart-ae00f3f6-6102-475f-8d79-954125d506b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2453061045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2453061045 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3378346683 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 11925528960 ps |
| CPU time | 229.81 seconds |
| Started | Feb 07 03:45:10 PM PST 24 |
| Finished | Feb 07 03:49:01 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-01cd3806-9642-4f76-821e-82a93a44cb34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3378346683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3378346683 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1171397313 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 64348179 ps |
| CPU time | 4.56 seconds |
| Started | Feb 07 03:45:04 PM PST 24 |
| Finished | Feb 07 03:45:13 PM PST 24 |
| Peak memory | 204472 kb |
| Host | smart-a82a9630-b6f6-4b5f-8aed-d4ca333d297e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1171397313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.1171397313 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3269657156 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3744841534 ps |
| CPU time | 358.1 seconds |
| Started | Feb 07 03:45:04 PM PST 24 |
| Finished | Feb 07 03:51:04 PM PST 24 |
| Peak memory | 211692 kb |
| Host | smart-e3c25537-2b11-44ab-80b3-3145e37779f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3269657156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.3269657156 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.151492912 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 290746877 ps |
| CPU time | 12.96 seconds |
| Started | Feb 07 03:45:05 PM PST 24 |
| Finished | Feb 07 03:45:22 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-c15c6eec-319d-47d4-80eb-70dba88b0ac4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=151492912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.151492912 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.652743380 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1934791690 ps |
| CPU time | 48.29 seconds |
| Started | Feb 07 03:45:06 PM PST 24 |
| Finished | Feb 07 03:45:58 PM PST 24 |
| Peak memory | 211608 kb |
| Host | smart-0c397588-61e1-47aa-ab2c-061502d18e21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=652743380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.652743380 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.965424144 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 121535009724 ps |
| CPU time | 324.99 seconds |
| Started | Feb 07 03:45:08 PM PST 24 |
| Finished | Feb 07 03:50:35 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-b31177e9-381f-40b9-8e66-3b84840bb102 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=965424144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slo w_rsp.965424144 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1948605822 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 428244183 ps |
| CPU time | 19.08 seconds |
| Started | Feb 07 03:45:08 PM PST 24 |
| Finished | Feb 07 03:45:29 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-66bd97fe-f39e-40ee-a4fe-950c3bf3f178 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1948605822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1948605822 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.1957694544 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 145814605 ps |
| CPU time | 14.59 seconds |
| Started | Feb 07 03:45:08 PM PST 24 |
| Finished | Feb 07 03:45:24 PM PST 24 |
| Peak memory | 203336 kb |
| Host | smart-5ed28beb-b142-47ab-a041-a08cc809d4c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1957694544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1957694544 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.149180829 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 93873058 ps |
| CPU time | 11.32 seconds |
| Started | Feb 07 03:45:07 PM PST 24 |
| Finished | Feb 07 03:45:21 PM PST 24 |
| Peak memory | 204480 kb |
| Host | smart-3f968331-7bd6-48bd-9fcd-0276676e1872 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=149180829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.149180829 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.2510296235 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 33107419516 ps |
| CPU time | 203.16 seconds |
| Started | Feb 07 03:45:04 PM PST 24 |
| Finished | Feb 07 03:48:32 PM PST 24 |
| Peak memory | 211684 kb |
| Host | smart-96473b1a-b471-492e-aac2-577761e399ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510296235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2510296235 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1839336860 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 41149996840 ps |
| CPU time | 173.89 seconds |
| Started | Feb 07 03:45:03 PM PST 24 |
| Finished | Feb 07 03:47:59 PM PST 24 |
| Peak memory | 204984 kb |
| Host | smart-60171623-4055-4a2b-ab61-b2961b7fb857 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1839336860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1839336860 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3119097727 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 33446691 ps |
| CPU time | 4.76 seconds |
| Started | Feb 07 03:45:08 PM PST 24 |
| Finished | Feb 07 03:45:15 PM PST 24 |
| Peak memory | 211584 kb |
| Host | smart-e7d7d5dd-8e81-4dd8-add9-931a67307cb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119097727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3119097727 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.2193348286 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 4830713932 ps |
| CPU time | 32.83 seconds |
| Started | Feb 07 03:45:10 PM PST 24 |
| Finished | Feb 07 03:45:44 PM PST 24 |
| Peak memory | 211504 kb |
| Host | smart-51a42bd6-2453-4226-8885-a6518dee91bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2193348286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2193348286 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.3617112287 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 177318242 ps |
| CPU time | 3.34 seconds |
| Started | Feb 07 03:45:05 PM PST 24 |
| Finished | Feb 07 03:45:12 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-256d8f40-75e4-4ddd-b647-fa174b422027 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3617112287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3617112287 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2868022711 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 12336859287 ps |
| CPU time | 38.47 seconds |
| Started | Feb 07 03:45:09 PM PST 24 |
| Finished | Feb 07 03:45:48 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-4843ca0d-c6b6-4165-9e60-939c2958dc8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868022711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2868022711 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1814065532 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 4348835443 ps |
| CPU time | 24.79 seconds |
| Started | Feb 07 03:45:08 PM PST 24 |
| Finished | Feb 07 03:45:34 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-9bf0592d-481f-4b3e-a7a6-1c945960fcd8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1814065532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1814065532 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3857974065 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 33704007 ps |
| CPU time | 2.51 seconds |
| Started | Feb 07 03:45:05 PM PST 24 |
| Finished | Feb 07 03:45:12 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-5d9045c8-8746-476a-ab86-9a83e81ef639 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857974065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3857974065 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1909802981 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1095882822 ps |
| CPU time | 156.87 seconds |
| Started | Feb 07 03:45:08 PM PST 24 |
| Finished | Feb 07 03:47:47 PM PST 24 |
| Peak memory | 210364 kb |
| Host | smart-3ceb58ee-187f-4db6-9ec4-667899828310 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1909802981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1909802981 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2546746284 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 13024311467 ps |
| CPU time | 184.64 seconds |
| Started | Feb 07 03:45:10 PM PST 24 |
| Finished | Feb 07 03:48:16 PM PST 24 |
| Peak memory | 208648 kb |
| Host | smart-4207cfab-2c2f-4b91-91c6-1b2aac02b9df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2546746284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2546746284 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.6744191 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 7935950595 ps |
| CPU time | 269.51 seconds |
| Started | Feb 07 03:45:10 PM PST 24 |
| Finished | Feb 07 03:49:40 PM PST 24 |
| Peak memory | 208044 kb |
| Host | smart-473a2c97-7904-4ff9-a45f-ba2abbb127bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=6744191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_r eset.6744191 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.160576638 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 696385437 ps |
| CPU time | 166.14 seconds |
| Started | Feb 07 03:45:10 PM PST 24 |
| Finished | Feb 07 03:47:57 PM PST 24 |
| Peak memory | 211196 kb |
| Host | smart-24897bcf-7a62-4016-a1ed-afe6317bb202 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=160576638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.160576638 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.939459424 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 224128224 ps |
| CPU time | 8.24 seconds |
| Started | Feb 07 03:45:09 PM PST 24 |
| Finished | Feb 07 03:45:18 PM PST 24 |
| Peak memory | 204804 kb |
| Host | smart-e403fd79-d99e-48b1-8b78-01b29642fc27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=939459424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.939459424 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.317500530 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 78803234 ps |
| CPU time | 8.56 seconds |
| Started | Feb 07 03:45:19 PM PST 24 |
| Finished | Feb 07 03:45:28 PM PST 24 |
| Peak memory | 211648 kb |
| Host | smart-bb32f15c-fd6c-4622-a56b-35ed5df863db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=317500530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.317500530 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1222885542 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 20310515857 ps |
| CPU time | 72.41 seconds |
| Started | Feb 07 03:45:17 PM PST 24 |
| Finished | Feb 07 03:46:30 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-c9de6812-550a-4e76-a2a5-bb9fac72c78d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1222885542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.1222885542 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1938095887 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 410773776 ps |
| CPU time | 4.71 seconds |
| Started | Feb 07 03:45:16 PM PST 24 |
| Finished | Feb 07 03:45:22 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-862ef7f6-61a8-4728-a7b3-7e46d399e3c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1938095887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1938095887 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.820592041 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 208052964 ps |
| CPU time | 4.29 seconds |
| Started | Feb 07 03:45:21 PM PST 24 |
| Finished | Feb 07 03:45:26 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-f8ba2dde-a339-4bcc-a76b-1da4a72680b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=820592041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.820592041 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.2569891241 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2759434454 ps |
| CPU time | 36.49 seconds |
| Started | Feb 07 03:45:17 PM PST 24 |
| Finished | Feb 07 03:45:54 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-28d72aa4-09e5-4319-95c9-190e5a58c64a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2569891241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2569891241 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3116296308 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 32961740016 ps |
| CPU time | 210.2 seconds |
| Started | Feb 07 03:45:18 PM PST 24 |
| Finished | Feb 07 03:48:49 PM PST 24 |
| Peak memory | 205116 kb |
| Host | smart-88c53875-bcc9-4342-8f78-c281e08fc7f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116296308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3116296308 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1640596843 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 88686791545 ps |
| CPU time | 268.64 seconds |
| Started | Feb 07 03:45:20 PM PST 24 |
| Finished | Feb 07 03:49:49 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-8ad59502-4b24-4830-94fe-73b073956964 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1640596843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1640596843 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.695584219 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 14447878 ps |
| CPU time | 2.23 seconds |
| Started | Feb 07 03:45:20 PM PST 24 |
| Finished | Feb 07 03:45:23 PM PST 24 |
| Peak memory | 203276 kb |
| Host | smart-e9e5b4d1-204d-43a6-b29e-f99a31798da9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695584219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.695584219 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.3750887492 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 667705716 ps |
| CPU time | 21.44 seconds |
| Started | Feb 07 03:45:20 PM PST 24 |
| Finished | Feb 07 03:45:42 PM PST 24 |
| Peak memory | 203252 kb |
| Host | smart-a29ca335-dea6-41fd-96c5-54b60768492a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3750887492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3750887492 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.4148460780 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 176636077 ps |
| CPU time | 3.99 seconds |
| Started | Feb 07 03:45:09 PM PST 24 |
| Finished | Feb 07 03:45:14 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-85b22fb0-d86f-4dcb-ae7f-da5cbacb8347 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4148460780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.4148460780 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.821030112 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 12212618988 ps |
| CPU time | 35.66 seconds |
| Started | Feb 07 03:45:18 PM PST 24 |
| Finished | Feb 07 03:45:55 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-b2bccec4-018d-4a74-9893-5f3f72efc1fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=821030112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.821030112 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3089364201 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3422937100 ps |
| CPU time | 26.5 seconds |
| Started | Feb 07 03:45:18 PM PST 24 |
| Finished | Feb 07 03:45:46 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-0321b628-0ac5-400b-9917-2846636e45b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3089364201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3089364201 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2143983280 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 65294150 ps |
| CPU time | 2.28 seconds |
| Started | Feb 07 03:45:10 PM PST 24 |
| Finished | Feb 07 03:45:13 PM PST 24 |
| Peak memory | 203340 kb |
| Host | smart-59840f66-cabe-4f0e-be16-c05cc52dfb39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143983280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2143983280 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1003905234 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 22412853701 ps |
| CPU time | 160.38 seconds |
| Started | Feb 07 03:45:15 PM PST 24 |
| Finished | Feb 07 03:47:56 PM PST 24 |
| Peak memory | 209012 kb |
| Host | smart-e5c35023-1cec-48ad-a5e2-f9fb8f184b5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1003905234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1003905234 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.594325965 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2676145425 ps |
| CPU time | 84.15 seconds |
| Started | Feb 07 03:45:21 PM PST 24 |
| Finished | Feb 07 03:46:46 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-e002725d-916c-41c4-a4ea-eaecae489918 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=594325965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.594325965 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1323915777 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 429635613 ps |
| CPU time | 138.67 seconds |
| Started | Feb 07 03:45:17 PM PST 24 |
| Finished | Feb 07 03:47:37 PM PST 24 |
| Peak memory | 208648 kb |
| Host | smart-cbc0ad3c-2134-4792-861a-35630470af49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1323915777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.1323915777 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3772778734 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 251327247 ps |
| CPU time | 59.98 seconds |
| Started | Feb 07 03:45:20 PM PST 24 |
| Finished | Feb 07 03:46:21 PM PST 24 |
| Peak memory | 206808 kb |
| Host | smart-8538238e-3880-4c2b-bece-a0c11967611a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3772778734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.3772778734 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3093411858 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 800321179 ps |
| CPU time | 28.54 seconds |
| Started | Feb 07 03:45:15 PM PST 24 |
| Finished | Feb 07 03:45:44 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-6932bbe8-ea01-4cf9-a893-712e72574fff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3093411858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3093411858 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3946754287 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 4413770512 ps |
| CPU time | 59.74 seconds |
| Started | Feb 07 03:45:35 PM PST 24 |
| Finished | Feb 07 03:46:35 PM PST 24 |
| Peak memory | 205348 kb |
| Host | smart-975f8fdb-2673-47f3-b201-aac74430d467 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3946754287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3946754287 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.112385625 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 162584710310 ps |
| CPU time | 309.95 seconds |
| Started | Feb 07 03:45:32 PM PST 24 |
| Finished | Feb 07 03:50:42 PM PST 24 |
| Peak memory | 211688 kb |
| Host | smart-c1c6e2ea-d321-4b41-93ff-939fd56aadc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=112385625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slo w_rsp.112385625 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1124428860 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 760096443 ps |
| CPU time | 7.08 seconds |
| Started | Feb 07 03:45:33 PM PST 24 |
| Finished | Feb 07 03:45:40 PM PST 24 |
| Peak memory | 203356 kb |
| Host | smart-6deb5e13-fc34-4602-95fe-157f6024a9d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1124428860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1124428860 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.1409929870 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 830309590 ps |
| CPU time | 13.91 seconds |
| Started | Feb 07 03:45:34 PM PST 24 |
| Finished | Feb 07 03:45:48 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-b4c27c15-a780-4bed-9584-1af65a7c3eb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1409929870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1409929870 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.4210588123 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3961248608 ps |
| CPU time | 40.97 seconds |
| Started | Feb 07 03:45:26 PM PST 24 |
| Finished | Feb 07 03:46:08 PM PST 24 |
| Peak memory | 205140 kb |
| Host | smart-5562f7b3-b5a1-4f95-994b-37d10e187bcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4210588123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.4210588123 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.3654512771 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 7273043587 ps |
| CPU time | 45.33 seconds |
| Started | Feb 07 03:45:26 PM PST 24 |
| Finished | Feb 07 03:46:12 PM PST 24 |
| Peak memory | 211672 kb |
| Host | smart-e66eacc3-b9cd-47f3-8478-169b140606ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654512771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3654512771 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.409240819 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 35820767665 ps |
| CPU time | 292.63 seconds |
| Started | Feb 07 03:45:26 PM PST 24 |
| Finished | Feb 07 03:50:19 PM PST 24 |
| Peak memory | 211592 kb |
| Host | smart-332bf457-4623-4f5c-901c-1e40784cae13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=409240819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.409240819 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2402608531 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 22975088 ps |
| CPU time | 3.63 seconds |
| Started | Feb 07 03:45:27 PM PST 24 |
| Finished | Feb 07 03:45:31 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-c6870161-d99c-41d6-8f66-9e478b27bc89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402608531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2402608531 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.858891924 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 493494960 ps |
| CPU time | 10.84 seconds |
| Started | Feb 07 03:45:31 PM PST 24 |
| Finished | Feb 07 03:45:43 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-878f86a9-202b-4e81-b2f0-d607c30967e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=858891924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.858891924 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.3733030921 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 323136941 ps |
| CPU time | 4.05 seconds |
| Started | Feb 07 03:45:20 PM PST 24 |
| Finished | Feb 07 03:45:25 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-804d009e-b78e-4b7d-84b2-bb06a0e74036 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3733030921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3733030921 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2656352021 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 6487376404 ps |
| CPU time | 31.06 seconds |
| Started | Feb 07 03:45:17 PM PST 24 |
| Finished | Feb 07 03:45:49 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-0dabb005-8c91-49fa-a86d-38d982de4fb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656352021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2656352021 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.1943037543 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 23058494555 ps |
| CPU time | 51.15 seconds |
| Started | Feb 07 03:45:26 PM PST 24 |
| Finished | Feb 07 03:46:18 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-1759277e-2b2a-4b44-916a-3cc157decc9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1943037543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1943037543 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.2883212907 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 24885499 ps |
| CPU time | 2.16 seconds |
| Started | Feb 07 03:45:19 PM PST 24 |
| Finished | Feb 07 03:45:22 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-5b0a3de1-ad81-41f1-baf1-32fc5200c01c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883212907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.2883212907 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.188427448 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 9618623195 ps |
| CPU time | 192.81 seconds |
| Started | Feb 07 03:45:30 PM PST 24 |
| Finished | Feb 07 03:48:44 PM PST 24 |
| Peak memory | 211648 kb |
| Host | smart-278d7ef9-8245-4761-b0e7-06941301f21b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=188427448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.188427448 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2580417526 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 256296433 ps |
| CPU time | 3.26 seconds |
| Started | Feb 07 03:45:33 PM PST 24 |
| Finished | Feb 07 03:45:37 PM PST 24 |
| Peak memory | 203264 kb |
| Host | smart-24d943e2-1578-404f-95c2-436e13d18180 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2580417526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2580417526 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.237932459 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 58878982 ps |
| CPU time | 5.76 seconds |
| Started | Feb 07 03:45:34 PM PST 24 |
| Finished | Feb 07 03:45:40 PM PST 24 |
| Peak memory | 205240 kb |
| Host | smart-dfe691d3-0398-41d3-8a35-db95040983a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=237932459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand _reset.237932459 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.808545972 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 156357674 ps |
| CPU time | 56.69 seconds |
| Started | Feb 07 03:45:31 PM PST 24 |
| Finished | Feb 07 03:46:28 PM PST 24 |
| Peak memory | 211548 kb |
| Host | smart-d92a5a66-07cf-4957-b727-176226f647be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=808545972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_res et_error.808545972 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.1772172772 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 842393392 ps |
| CPU time | 8.47 seconds |
| Started | Feb 07 03:45:33 PM PST 24 |
| Finished | Feb 07 03:45:42 PM PST 24 |
| Peak memory | 204712 kb |
| Host | smart-0cf0f149-6445-408a-a83a-3a4a5bf7adc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1772172772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1772172772 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3641346083 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2013719877 ps |
| CPU time | 69.46 seconds |
| Started | Feb 07 03:45:44 PM PST 24 |
| Finished | Feb 07 03:46:54 PM PST 24 |
| Peak memory | 206332 kb |
| Host | smart-0284fd2d-3a17-4d76-a30a-f4146d406b0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3641346083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3641346083 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.978334222 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 52263087214 ps |
| CPU time | 359.89 seconds |
| Started | Feb 07 03:45:45 PM PST 24 |
| Finished | Feb 07 03:51:45 PM PST 24 |
| Peak memory | 211688 kb |
| Host | smart-1dcb69bf-3a4c-4305-a2b8-8d7de2ba4b28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=978334222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slo w_rsp.978334222 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2759744036 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 92169094 ps |
| CPU time | 9.57 seconds |
| Started | Feb 07 03:45:44 PM PST 24 |
| Finished | Feb 07 03:45:54 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-9652dc8c-3649-4506-84b6-42075134a089 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2759744036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2759744036 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.1635219521 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1300472999 ps |
| CPU time | 21.58 seconds |
| Started | Feb 07 03:45:49 PM PST 24 |
| Finished | Feb 07 03:46:12 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-415c50fb-1289-4a0f-a4c0-1d00df564280 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1635219521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1635219521 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.2999830146 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 399446715 ps |
| CPU time | 25.81 seconds |
| Started | Feb 07 03:45:32 PM PST 24 |
| Finished | Feb 07 03:45:58 PM PST 24 |
| Peak memory | 204864 kb |
| Host | smart-509e1f2b-965c-4578-aa11-b1843ba32344 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2999830146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2999830146 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.2332377606 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 16375746918 ps |
| CPU time | 32.97 seconds |
| Started | Feb 07 03:45:33 PM PST 24 |
| Finished | Feb 07 03:46:06 PM PST 24 |
| Peak memory | 204064 kb |
| Host | smart-98f984ed-21a7-4684-a520-f19e9049a1b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332377606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2332377606 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.40488860 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 43616422460 ps |
| CPU time | 188.65 seconds |
| Started | Feb 07 03:45:30 PM PST 24 |
| Finished | Feb 07 03:48:40 PM PST 24 |
| Peak memory | 211664 kb |
| Host | smart-0fcacbf7-c9ce-41b9-af17-fb72b60af3e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=40488860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.40488860 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1136725301 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 295610485 ps |
| CPU time | 25.8 seconds |
| Started | Feb 07 03:45:32 PM PST 24 |
| Finished | Feb 07 03:45:58 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-5fa1672a-196b-45e9-9d50-b21f36fe72cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136725301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1136725301 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.85472062 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 330030441 ps |
| CPU time | 5.64 seconds |
| Started | Feb 07 03:45:44 PM PST 24 |
| Finished | Feb 07 03:45:50 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-779c7eb2-7539-4b9e-851a-085cdbd97b95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=85472062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.85472062 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.729946833 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 288015955 ps |
| CPU time | 3.71 seconds |
| Started | Feb 07 03:45:30 PM PST 24 |
| Finished | Feb 07 03:45:34 PM PST 24 |
| Peak memory | 203192 kb |
| Host | smart-f8fb7342-0be3-42c6-b01f-7de9a0e73d04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=729946833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.729946833 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.4109989064 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 8942766720 ps |
| CPU time | 30.97 seconds |
| Started | Feb 07 03:45:30 PM PST 24 |
| Finished | Feb 07 03:46:02 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-a8831fa9-d693-4ac0-9e76-c5ca9621cfe5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109989064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.4109989064 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3217951760 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4206993510 ps |
| CPU time | 26.17 seconds |
| Started | Feb 07 03:45:31 PM PST 24 |
| Finished | Feb 07 03:45:57 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-0c6a7438-4950-406f-93dc-32a981a9de59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3217951760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3217951760 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2264104543 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 32977739 ps |
| CPU time | 2.31 seconds |
| Started | Feb 07 03:45:31 PM PST 24 |
| Finished | Feb 07 03:45:34 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-ede8004a-6df6-4291-9176-4cd760f34bdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264104543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2264104543 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3335509350 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 23772931582 ps |
| CPU time | 127.9 seconds |
| Started | Feb 07 03:45:43 PM PST 24 |
| Finished | Feb 07 03:47:52 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-3055318a-6bf7-4eaa-863a-3a0886ff18a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3335509350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3335509350 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.210909575 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 15886716789 ps |
| CPU time | 162.54 seconds |
| Started | Feb 07 03:45:46 PM PST 24 |
| Finished | Feb 07 03:48:29 PM PST 24 |
| Peak memory | 208792 kb |
| Host | smart-f393a86e-b34f-44e2-9340-a96d2b6c40e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=210909575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.210909575 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3283960454 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2490624979 ps |
| CPU time | 161.21 seconds |
| Started | Feb 07 03:45:45 PM PST 24 |
| Finished | Feb 07 03:48:27 PM PST 24 |
| Peak memory | 211168 kb |
| Host | smart-0aad8433-244b-4718-86d0-b36d1198fd15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3283960454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.3283960454 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3335952694 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 266173015 ps |
| CPU time | 11.98 seconds |
| Started | Feb 07 03:45:44 PM PST 24 |
| Finished | Feb 07 03:45:56 PM PST 24 |
| Peak memory | 204656 kb |
| Host | smart-46d3ae84-93c4-4321-8cab-72ec3dc6dcd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3335952694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3335952694 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.4071416498 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 139301335 ps |
| CPU time | 12.33 seconds |
| Started | Feb 07 03:45:45 PM PST 24 |
| Finished | Feb 07 03:45:58 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-7b9305e5-a2c9-4d07-ac5a-642039b99503 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4071416498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.4071416498 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2313916346 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 219183736784 ps |
| CPU time | 554.34 seconds |
| Started | Feb 07 03:45:49 PM PST 24 |
| Finished | Feb 07 03:55:04 PM PST 24 |
| Peak memory | 211644 kb |
| Host | smart-1eb5da2e-ee1e-4527-8aec-61977cf9b515 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2313916346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.2313916346 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1676555224 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 698128582 ps |
| CPU time | 22.26 seconds |
| Started | Feb 07 03:45:59 PM PST 24 |
| Finished | Feb 07 03:46:21 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-782964cd-3c37-42f6-a5ae-6e130fa21745 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1676555224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1676555224 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.551222494 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 89979627 ps |
| CPU time | 4.42 seconds |
| Started | Feb 07 03:45:56 PM PST 24 |
| Finished | Feb 07 03:46:01 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-687906e7-3c38-432c-9c1f-56dedae124b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=551222494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.551222494 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.1689553298 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 37524690 ps |
| CPU time | 4.8 seconds |
| Started | Feb 07 03:45:49 PM PST 24 |
| Finished | Feb 07 03:45:55 PM PST 24 |
| Peak memory | 203316 kb |
| Host | smart-5b2b8a36-1961-49ea-b90c-6b55ac5143bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1689553298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1689553298 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.231713795 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 122271100846 ps |
| CPU time | 238.69 seconds |
| Started | Feb 07 03:45:45 PM PST 24 |
| Finished | Feb 07 03:49:45 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-65504f73-03f3-4e7e-a9e9-a097c299a1ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=231713795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.231713795 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3443395498 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 31795512201 ps |
| CPU time | 255.67 seconds |
| Started | Feb 07 03:45:49 PM PST 24 |
| Finished | Feb 07 03:50:06 PM PST 24 |
| Peak memory | 204684 kb |
| Host | smart-2238ca9f-8d81-4df3-95b6-55b620baf247 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3443395498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3443395498 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.495186256 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 15180091 ps |
| CPU time | 2.15 seconds |
| Started | Feb 07 03:45:47 PM PST 24 |
| Finished | Feb 07 03:45:49 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-690fbdd5-d36a-464c-9229-b9348a0e3757 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495186256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.495186256 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.1520434333 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 193638601 ps |
| CPU time | 14.98 seconds |
| Started | Feb 07 03:45:53 PM PST 24 |
| Finished | Feb 07 03:46:09 PM PST 24 |
| Peak memory | 203876 kb |
| Host | smart-eb2dddad-446f-47a3-99ea-5182924a6278 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1520434333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1520434333 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.2439402416 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 264588146 ps |
| CPU time | 3.61 seconds |
| Started | Feb 07 03:45:47 PM PST 24 |
| Finished | Feb 07 03:45:51 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-158cc5c0-2f47-435e-bd78-26f78cbb068f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2439402416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2439402416 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3485085838 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 21522620928 ps |
| CPU time | 40.28 seconds |
| Started | Feb 07 03:45:46 PM PST 24 |
| Finished | Feb 07 03:46:27 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-50ece497-d320-4f5e-87ab-6c7fd7434e1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485085838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3485085838 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2584746210 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 7706615515 ps |
| CPU time | 27.06 seconds |
| Started | Feb 07 03:45:46 PM PST 24 |
| Finished | Feb 07 03:46:13 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-a73bc4f6-9c5a-4a2b-a6db-133995a15bfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2584746210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2584746210 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2875659652 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 33681432 ps |
| CPU time | 2.3 seconds |
| Started | Feb 07 03:45:46 PM PST 24 |
| Finished | Feb 07 03:45:48 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-d58f8d10-5159-4c0c-8f70-45e22b0f4619 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875659652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2875659652 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.141264308 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1099245358 ps |
| CPU time | 85.14 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:47:21 PM PST 24 |
| Peak memory | 205520 kb |
| Host | smart-bb9454ed-18e2-42b4-b4de-98572fcd6854 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=141264308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.141264308 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3054120262 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 112263206 ps |
| CPU time | 2.15 seconds |
| Started | Feb 07 03:45:56 PM PST 24 |
| Finished | Feb 07 03:45:58 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-ff89aaa7-8bfd-42dc-a3c7-40bf83d63eaa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3054120262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3054120262 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3093528950 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4112052868 ps |
| CPU time | 430.82 seconds |
| Started | Feb 07 03:45:56 PM PST 24 |
| Finished | Feb 07 03:53:07 PM PST 24 |
| Peak memory | 208332 kb |
| Host | smart-b6da4aaa-9ce3-4419-a925-6311904d4e4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3093528950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.3093528950 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2079726143 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 7113717119 ps |
| CPU time | 389.9 seconds |
| Started | Feb 07 03:45:57 PM PST 24 |
| Finished | Feb 07 03:52:28 PM PST 24 |
| Peak memory | 220404 kb |
| Host | smart-a2517652-90cb-44e2-8109-0e922326c72b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2079726143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.2079726143 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3039932836 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 79856430 ps |
| CPU time | 12.84 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:46:09 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-9d7477d3-688e-4093-892e-5c66b12ae925 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3039932836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3039932836 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.2994100246 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2767534099 ps |
| CPU time | 66.91 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:47:02 PM PST 24 |
| Peak memory | 206716 kb |
| Host | smart-b5d055ff-1b46-4a45-94ca-58a4b5f77971 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2994100246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2994100246 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2305666043 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 56350236419 ps |
| CPU time | 333.46 seconds |
| Started | Feb 07 03:45:57 PM PST 24 |
| Finished | Feb 07 03:51:31 PM PST 24 |
| Peak memory | 206504 kb |
| Host | smart-a129fca4-2956-498f-8ec5-2eae018021b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2305666043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.2305666043 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3706743581 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 631807340 ps |
| CPU time | 20.18 seconds |
| Started | Feb 07 03:45:59 PM PST 24 |
| Finished | Feb 07 03:46:19 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-94cf75cb-0650-4aa2-bee0-40e930d9426f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3706743581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3706743581 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.805750741 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 73103946 ps |
| CPU time | 5.12 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:46:01 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-a123e3b6-c237-44b9-9351-ca0f3572f1ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=805750741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.805750741 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.718047519 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 318614206 ps |
| CPU time | 5.57 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:46:01 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-6dd52b97-48e6-443c-b26b-16367b8dce49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=718047519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.718047519 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2559678693 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 60224164287 ps |
| CPU time | 171.34 seconds |
| Started | Feb 07 03:45:56 PM PST 24 |
| Finished | Feb 07 03:48:48 PM PST 24 |
| Peak memory | 204620 kb |
| Host | smart-13bacc00-3b25-46d8-b529-0179b2faa129 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559678693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2559678693 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.530544290 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 35643021735 ps |
| CPU time | 211.24 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:49:26 PM PST 24 |
| Peak memory | 211660 kb |
| Host | smart-1d9fcec5-2d54-4e17-91e0-62c0c7ee9eff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=530544290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.530544290 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.114610903 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 320656545 ps |
| CPU time | 30.08 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:46:25 PM PST 24 |
| Peak memory | 204692 kb |
| Host | smart-faf9050c-9afe-4364-889d-75979b2689a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114610903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.114610903 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.3687590106 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1526778083 ps |
| CPU time | 14.17 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:46:09 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-9526837c-5837-4104-aa44-2dcd20b6535e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3687590106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3687590106 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.698236205 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 62871444 ps |
| CPU time | 2.55 seconds |
| Started | Feb 07 03:45:54 PM PST 24 |
| Finished | Feb 07 03:45:58 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-8dbdd502-9894-4545-8781-522263c69fc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=698236205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.698236205 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2634509380 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 7046045692 ps |
| CPU time | 30.8 seconds |
| Started | Feb 07 03:45:53 PM PST 24 |
| Finished | Feb 07 03:46:25 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-d2a34f03-19cf-4acb-8f15-a81aa4688d5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634509380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2634509380 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1148540782 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4852593216 ps |
| CPU time | 30.86 seconds |
| Started | Feb 07 03:45:57 PM PST 24 |
| Finished | Feb 07 03:46:29 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-648a5405-fea8-4a23-b72c-2da4b56fdb20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1148540782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1148540782 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2585761351 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 40299905 ps |
| CPU time | 2.58 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:45:58 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-0eadd9e5-18ed-4a9c-bd57-61e83a636181 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585761351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2585761351 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.844617405 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2051688358 ps |
| CPU time | 61.87 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:46:57 PM PST 24 |
| Peak memory | 206484 kb |
| Host | smart-ceb59370-d72e-4e9d-bdd9-1face6367720 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=844617405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.844617405 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1757864712 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1780729522 ps |
| CPU time | 78.75 seconds |
| Started | Feb 07 03:46:06 PM PST 24 |
| Finished | Feb 07 03:47:26 PM PST 24 |
| Peak memory | 204624 kb |
| Host | smart-3294edcd-d675-4536-bed0-942e5d5c202a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1757864712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1757864712 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1118554851 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 9155765357 ps |
| CPU time | 376.83 seconds |
| Started | Feb 07 03:46:03 PM PST 24 |
| Finished | Feb 07 03:52:20 PM PST 24 |
| Peak memory | 210136 kb |
| Host | smart-db8cc916-6dc0-4dbf-a4ef-c9d9bc0d11bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1118554851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.1118554851 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1620021931 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 458231832 ps |
| CPU time | 214.96 seconds |
| Started | Feb 07 03:46:02 PM PST 24 |
| Finished | Feb 07 03:49:37 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-ea381534-6afa-4175-b915-d028169eefc7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1620021931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.1620021931 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.1296124058 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 75140709 ps |
| CPU time | 3.73 seconds |
| Started | Feb 07 03:45:55 PM PST 24 |
| Finished | Feb 07 03:45:59 PM PST 24 |
| Peak memory | 211644 kb |
| Host | smart-67cb27e8-609e-4e92-ba2b-f2b9a9fe8b0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1296124058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1296124058 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.1724881502 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 556179374 ps |
| CPU time | 45.7 seconds |
| Started | Feb 07 03:38:28 PM PST 24 |
| Finished | Feb 07 03:39:15 PM PST 24 |
| Peak memory | 204804 kb |
| Host | smart-ec61f1cb-6087-416a-920c-8c8c7b8b098e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1724881502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1724881502 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.670712477 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 69978887144 ps |
| CPU time | 629.18 seconds |
| Started | Feb 07 03:38:30 PM PST 24 |
| Finished | Feb 07 03:49:00 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-dfca00a0-3107-4914-8e0e-779fd1edb8ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=670712477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow _rsp.670712477 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.995016886 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 864929346 ps |
| CPU time | 11.65 seconds |
| Started | Feb 07 03:38:36 PM PST 24 |
| Finished | Feb 07 03:38:49 PM PST 24 |
| Peak memory | 203264 kb |
| Host | smart-172fcdba-bce9-4015-afac-2dfb91bd6bb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=995016886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.995016886 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3770886764 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 276854767 ps |
| CPU time | 27.4 seconds |
| Started | Feb 07 03:38:29 PM PST 24 |
| Finished | Feb 07 03:38:57 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-fb49c29e-c3fc-4d34-8e16-910366ef4ba0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3770886764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3770886764 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.3808822151 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 543609833 ps |
| CPU time | 17.02 seconds |
| Started | Feb 07 03:38:25 PM PST 24 |
| Finished | Feb 07 03:38:43 PM PST 24 |
| Peak memory | 204428 kb |
| Host | smart-ccf96be7-c0de-474d-b0e1-88f96f1704c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3808822151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3808822151 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3712943011 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 16574329518 ps |
| CPU time | 90.94 seconds |
| Started | Feb 07 03:38:29 PM PST 24 |
| Finished | Feb 07 03:40:01 PM PST 24 |
| Peak memory | 211684 kb |
| Host | smart-490eed80-ba33-4314-b3e1-d32a251c62d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712943011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3712943011 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.322758834 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 28255738277 ps |
| CPU time | 126.68 seconds |
| Started | Feb 07 03:38:24 PM PST 24 |
| Finished | Feb 07 03:40:32 PM PST 24 |
| Peak memory | 211672 kb |
| Host | smart-475090fb-cdc5-4116-9829-22589f0ce3da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=322758834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.322758834 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1483492362 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 176623855 ps |
| CPU time | 25.22 seconds |
| Started | Feb 07 03:38:27 PM PST 24 |
| Finished | Feb 07 03:38:52 PM PST 24 |
| Peak memory | 204468 kb |
| Host | smart-b8504e81-5679-467b-aa7b-084e82167714 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483492362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1483492362 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.1570315031 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2118849647 ps |
| CPU time | 26.32 seconds |
| Started | Feb 07 03:38:30 PM PST 24 |
| Finished | Feb 07 03:38:57 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-b9ec605e-4e54-4365-a1ed-95e66b35d2e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1570315031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1570315031 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2422279283 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 106861321 ps |
| CPU time | 2.86 seconds |
| Started | Feb 07 03:38:17 PM PST 24 |
| Finished | Feb 07 03:38:22 PM PST 24 |
| Peak memory | 203320 kb |
| Host | smart-fb65457e-bc4b-4647-bf43-d55c0bcfe1dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2422279283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2422279283 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3597816073 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 7125920326 ps |
| CPU time | 39.71 seconds |
| Started | Feb 07 03:38:17 PM PST 24 |
| Finished | Feb 07 03:38:59 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-dc0eb1be-d428-4cd1-8bb8-617474cb9465 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597816073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3597816073 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.4281707179 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 4248618341 ps |
| CPU time | 30.01 seconds |
| Started | Feb 07 03:38:29 PM PST 24 |
| Finished | Feb 07 03:39:00 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-23582861-4cc2-423d-8ccd-eb3847f9b500 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4281707179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.4281707179 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2734882155 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 107704275 ps |
| CPU time | 2.2 seconds |
| Started | Feb 07 03:38:18 PM PST 24 |
| Finished | Feb 07 03:38:22 PM PST 24 |
| Peak memory | 203332 kb |
| Host | smart-9d503e85-329e-4e74-a482-165aa4bf7674 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734882155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2734882155 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.893109837 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 6233420630 ps |
| CPU time | 200.75 seconds |
| Started | Feb 07 03:38:44 PM PST 24 |
| Finished | Feb 07 03:42:05 PM PST 24 |
| Peak memory | 208128 kb |
| Host | smart-2f004c9a-189b-412e-bbb1-7513eef77a43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=893109837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.893109837 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.4257961706 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 21994650542 ps |
| CPU time | 189.39 seconds |
| Started | Feb 07 03:38:43 PM PST 24 |
| Finished | Feb 07 03:41:53 PM PST 24 |
| Peak memory | 206724 kb |
| Host | smart-01b4c145-fdcd-43ae-95e7-525ad659a9fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4257961706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.4257961706 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.966853260 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 3400338159 ps |
| CPU time | 385.87 seconds |
| Started | Feb 07 03:38:46 PM PST 24 |
| Finished | Feb 07 03:45:13 PM PST 24 |
| Peak memory | 219880 kb |
| Host | smart-4eba2c28-a5e4-435d-a097-24ea4c265c27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=966853260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_ reset.966853260 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.56977861 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 347081405 ps |
| CPU time | 72.98 seconds |
| Started | Feb 07 03:38:41 PM PST 24 |
| Finished | Feb 07 03:39:55 PM PST 24 |
| Peak memory | 207996 kb |
| Host | smart-bb77cfce-b955-4e45-9388-b975c915c896 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=56977861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset _error.56977861 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1897186035 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 656535360 ps |
| CPU time | 19.3 seconds |
| Started | Feb 07 03:38:42 PM PST 24 |
| Finished | Feb 07 03:39:02 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-8567f24c-ec53-426a-98e7-99903bbe870d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1897186035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1897186035 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.673357699 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1852999527 ps |
| CPU time | 47.9 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:46:58 PM PST 24 |
| Peak memory | 205036 kb |
| Host | smart-52f811cf-0f89-48ac-bbeb-4510d6790c0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=673357699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.673357699 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2011284585 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 91042435230 ps |
| CPU time | 630.23 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:56:41 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-9aed01e1-f059-423d-9775-d0db65e6ca45 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2011284585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.2011284585 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1070160986 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 223470502 ps |
| CPU time | 7.78 seconds |
| Started | Feb 07 03:46:11 PM PST 24 |
| Finished | Feb 07 03:46:19 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-33c9b4d9-b347-42b5-9b05-a4a5380b98d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1070160986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1070160986 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.3333877394 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 774047287 ps |
| CPU time | 26.1 seconds |
| Started | Feb 07 03:46:05 PM PST 24 |
| Finished | Feb 07 03:46:32 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-9840baf1-d703-4f81-b4bd-dd4bb9490fb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3333877394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3333877394 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.11349342 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1068123734 ps |
| CPU time | 15.87 seconds |
| Started | Feb 07 03:46:05 PM PST 24 |
| Finished | Feb 07 03:46:21 PM PST 24 |
| Peak memory | 204500 kb |
| Host | smart-39bd9370-e079-4e7b-b364-8b71a888a01c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=11349342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.11349342 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1618658100 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 6199607696 ps |
| CPU time | 39.16 seconds |
| Started | Feb 07 03:46:04 PM PST 24 |
| Finished | Feb 07 03:46:44 PM PST 24 |
| Peak memory | 204496 kb |
| Host | smart-c0606a85-a3ac-4587-b300-1c423c293f17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618658100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1618658100 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1329462611 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 5601544174 ps |
| CPU time | 41.41 seconds |
| Started | Feb 07 03:46:02 PM PST 24 |
| Finished | Feb 07 03:46:44 PM PST 24 |
| Peak memory | 211632 kb |
| Host | smart-84ee9f89-18fc-4f09-a0cd-7379c57d84df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1329462611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1329462611 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.1523792223 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 161830956 ps |
| CPU time | 17.02 seconds |
| Started | Feb 07 03:46:01 PM PST 24 |
| Finished | Feb 07 03:46:18 PM PST 24 |
| Peak memory | 204428 kb |
| Host | smart-800112da-ad6a-4969-ba3a-e1e805f7a111 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523792223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.1523792223 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.99636519 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2288127990 ps |
| CPU time | 32.7 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:46:43 PM PST 24 |
| Peak memory | 203464 kb |
| Host | smart-9fd2ac72-14ab-410c-b5e4-087c1b16d9ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=99636519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.99636519 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.3312027095 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 570150098 ps |
| CPU time | 3.45 seconds |
| Started | Feb 07 03:46:02 PM PST 24 |
| Finished | Feb 07 03:46:06 PM PST 24 |
| Peak memory | 203324 kb |
| Host | smart-3c68435f-9fa2-4c17-888f-2a3079484544 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3312027095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3312027095 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2987336471 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 6021174984 ps |
| CPU time | 33.44 seconds |
| Started | Feb 07 03:46:04 PM PST 24 |
| Finished | Feb 07 03:46:38 PM PST 24 |
| Peak memory | 203304 kb |
| Host | smart-6fdf66fb-a494-4112-a39e-027a0daa2044 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987336471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2987336471 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1746721425 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3517001255 ps |
| CPU time | 29.82 seconds |
| Started | Feb 07 03:46:01 PM PST 24 |
| Finished | Feb 07 03:46:32 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-5ef7a898-3ed1-4b7f-a159-9ffee40f5e6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1746721425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1746721425 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3601618576 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 30908339 ps |
| CPU time | 2.18 seconds |
| Started | Feb 07 03:46:07 PM PST 24 |
| Finished | Feb 07 03:46:09 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-0f99f248-6614-43a3-bc8c-6faade4b0b4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601618576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3601618576 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.4182793047 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2201633002 ps |
| CPU time | 136.75 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:48:27 PM PST 24 |
| Peak memory | 206672 kb |
| Host | smart-46c7314e-905e-4c42-8497-5f4a825e0cc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4182793047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.4182793047 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3016528392 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 3011145015 ps |
| CPU time | 81.19 seconds |
| Started | Feb 07 03:46:08 PM PST 24 |
| Finished | Feb 07 03:47:30 PM PST 24 |
| Peak memory | 206344 kb |
| Host | smart-0679148f-dc75-4b70-ac82-72ea898e90c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3016528392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3016528392 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2347827521 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 122300585 ps |
| CPU time | 33.87 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:46:45 PM PST 24 |
| Peak memory | 206528 kb |
| Host | smart-cff97c57-16bc-43b8-b796-98fa0697dde7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2347827521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.2347827521 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1742660265 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 64543444 ps |
| CPU time | 41.42 seconds |
| Started | Feb 07 03:46:11 PM PST 24 |
| Finished | Feb 07 03:46:53 PM PST 24 |
| Peak memory | 206484 kb |
| Host | smart-001b4939-25cf-4785-b576-b408c27b448e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1742660265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.1742660265 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1817658533 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 354062050 ps |
| CPU time | 20.74 seconds |
| Started | Feb 07 03:46:04 PM PST 24 |
| Finished | Feb 07 03:46:26 PM PST 24 |
| Peak memory | 211640 kb |
| Host | smart-973bb982-2e53-4975-a71c-66c4e6eed3ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1817658533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1817658533 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.2526476205 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 381070207 ps |
| CPU time | 34.52 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:46:45 PM PST 24 |
| Peak memory | 204508 kb |
| Host | smart-2d97ea0c-71fd-4161-8265-808db93c4b57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2526476205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2526476205 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1251696097 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 45265412610 ps |
| CPU time | 287.1 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:50:57 PM PST 24 |
| Peak memory | 211512 kb |
| Host | smart-8098dd77-bc16-45c8-b0b6-42cd4700cb00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1251696097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1251696097 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3807645008 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 646929333 ps |
| CPU time | 21.51 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:46:32 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-cbba9952-f5b1-4f9b-9924-b55f666c7473 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3807645008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3807645008 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.884591533 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1118106726 ps |
| CPU time | 35.21 seconds |
| Started | Feb 07 03:46:09 PM PST 24 |
| Finished | Feb 07 03:46:45 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-537f4526-a2ca-4012-89e4-3541baa820d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=884591533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.884591533 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.3549686039 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 244854519 ps |
| CPU time | 26.41 seconds |
| Started | Feb 07 03:46:09 PM PST 24 |
| Finished | Feb 07 03:46:36 PM PST 24 |
| Peak memory | 204824 kb |
| Host | smart-a31afefc-9677-4989-959c-7d5325e4f3b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3549686039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3549686039 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3485889022 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 3331021340 ps |
| CPU time | 13.04 seconds |
| Started | Feb 07 03:46:12 PM PST 24 |
| Finished | Feb 07 03:46:26 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-ada87f9c-5343-4a0e-ab1a-47228cfbfeef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485889022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3485889022 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.319941743 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 28668635574 ps |
| CPU time | 187.34 seconds |
| Started | Feb 07 03:46:08 PM PST 24 |
| Finished | Feb 07 03:49:16 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-10b83e74-cb12-48f1-b7a3-ec4457e38706 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=319941743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.319941743 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.1372331574 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 39300849 ps |
| CPU time | 4.63 seconds |
| Started | Feb 07 03:46:09 PM PST 24 |
| Finished | Feb 07 03:46:14 PM PST 24 |
| Peak memory | 204200 kb |
| Host | smart-3249220d-28ee-4628-a924-fea324ed51fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372331574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1372331574 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.721231820 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5783234452 ps |
| CPU time | 26.63 seconds |
| Started | Feb 07 03:46:11 PM PST 24 |
| Finished | Feb 07 03:46:38 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-439e2b0b-8968-4927-b3ef-e1423c84bfd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=721231820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.721231820 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.2366452138 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 46235919 ps |
| CPU time | 2.04 seconds |
| Started | Feb 07 03:46:08 PM PST 24 |
| Finished | Feb 07 03:46:11 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-17e726a1-425d-4a53-ba54-017bcd05a317 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2366452138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2366452138 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2974102865 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 24060983011 ps |
| CPU time | 35.05 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:46:46 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-00956be5-4bfd-4902-a19d-ec9453a330b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974102865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2974102865 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1101351179 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 8543616080 ps |
| CPU time | 25.65 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:46:37 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-1bce7dc8-1b23-4d4e-b7ec-64c74918f5be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1101351179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1101351179 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2021440455 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 58523653 ps |
| CPU time | 2.21 seconds |
| Started | Feb 07 03:46:09 PM PST 24 |
| Finished | Feb 07 03:46:12 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-b12ed9c6-31b5-457e-88ad-1607e78cde23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021440455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2021440455 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1324267487 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 8533272316 ps |
| CPU time | 307.72 seconds |
| Started | Feb 07 03:46:25 PM PST 24 |
| Finished | Feb 07 03:51:33 PM PST 24 |
| Peak memory | 209880 kb |
| Host | smart-4d702af1-57f2-4ed3-8bca-2d1d2dc251d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1324267487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1324267487 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2760304592 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4880377913 ps |
| CPU time | 164.57 seconds |
| Started | Feb 07 03:46:25 PM PST 24 |
| Finished | Feb 07 03:49:10 PM PST 24 |
| Peak memory | 211724 kb |
| Host | smart-1d26349e-cf38-4237-af4b-0591ddd20bf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2760304592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2760304592 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1987709359 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 2010033774 ps |
| CPU time | 315.34 seconds |
| Started | Feb 07 03:46:20 PM PST 24 |
| Finished | Feb 07 03:51:35 PM PST 24 |
| Peak memory | 211288 kb |
| Host | smart-d2a2950a-30c2-4b02-abb1-096b9890cdaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1987709359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.1987709359 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1829296219 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7678464741 ps |
| CPU time | 192.15 seconds |
| Started | Feb 07 03:46:21 PM PST 24 |
| Finished | Feb 07 03:49:33 PM PST 24 |
| Peak memory | 210232 kb |
| Host | smart-639d62d8-770f-4fef-9bae-a537ca738d3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1829296219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.1829296219 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2132627256 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 88955036 ps |
| CPU time | 10.28 seconds |
| Started | Feb 07 03:46:10 PM PST 24 |
| Finished | Feb 07 03:46:21 PM PST 24 |
| Peak memory | 204952 kb |
| Host | smart-ef62705b-c62c-4c8e-96e1-2548e4cb3b79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2132627256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2132627256 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.1287404187 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1891407808 ps |
| CPU time | 67.92 seconds |
| Started | Feb 07 03:46:23 PM PST 24 |
| Finished | Feb 07 03:47:32 PM PST 24 |
| Peak memory | 211576 kb |
| Host | smart-caf908ac-14b1-4551-b6a4-6f12bbb7b742 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1287404187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1287404187 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.3927548785 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 16798053700 ps |
| CPU time | 45.72 seconds |
| Started | Feb 07 03:46:27 PM PST 24 |
| Finished | Feb 07 03:47:13 PM PST 24 |
| Peak memory | 204052 kb |
| Host | smart-17972fbd-0bd2-42a4-bb30-c51965c2b1d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3927548785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.3927548785 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.781178124 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 57439834 ps |
| CPU time | 7.69 seconds |
| Started | Feb 07 03:46:23 PM PST 24 |
| Finished | Feb 07 03:46:31 PM PST 24 |
| Peak memory | 203332 kb |
| Host | smart-30dca3ef-9bfd-48eb-9d8d-2508b8ac2d5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=781178124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.781178124 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.3653246366 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 75754849 ps |
| CPU time | 3.15 seconds |
| Started | Feb 07 03:46:31 PM PST 24 |
| Finished | Feb 07 03:46:34 PM PST 24 |
| Peak memory | 203336 kb |
| Host | smart-bd877839-0601-4077-a775-0a359bed6560 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3653246366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3653246366 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.544699463 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 114697551 ps |
| CPU time | 18.03 seconds |
| Started | Feb 07 03:46:20 PM PST 24 |
| Finished | Feb 07 03:46:39 PM PST 24 |
| Peak memory | 204696 kb |
| Host | smart-5e7743d4-836a-4921-843c-0aeba2d477b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=544699463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.544699463 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.3210048859 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 67109352310 ps |
| CPU time | 219.65 seconds |
| Started | Feb 07 03:46:22 PM PST 24 |
| Finished | Feb 07 03:50:02 PM PST 24 |
| Peak memory | 211708 kb |
| Host | smart-64dda177-43f8-4f80-806a-6098b2bd5b43 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210048859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3210048859 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.974232183 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 24529958688 ps |
| CPU time | 214 seconds |
| Started | Feb 07 03:46:27 PM PST 24 |
| Finished | Feb 07 03:50:01 PM PST 24 |
| Peak memory | 211624 kb |
| Host | smart-03dfe781-3066-47d7-b6ed-fdba0828c94b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=974232183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.974232183 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1689826382 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 171519559 ps |
| CPU time | 21.39 seconds |
| Started | Feb 07 03:46:22 PM PST 24 |
| Finished | Feb 07 03:46:44 PM PST 24 |
| Peak memory | 211536 kb |
| Host | smart-c852c48b-ae41-4453-a44a-a6b6c0ecd149 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689826382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1689826382 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.1251783631 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 87144958 ps |
| CPU time | 5.65 seconds |
| Started | Feb 07 03:46:25 PM PST 24 |
| Finished | Feb 07 03:46:31 PM PST 24 |
| Peak memory | 203388 kb |
| Host | smart-3be41482-16d6-48ba-8318-ec774be62dd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1251783631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1251783631 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.2354149928 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 240937673 ps |
| CPU time | 3.33 seconds |
| Started | Feb 07 03:46:28 PM PST 24 |
| Finished | Feb 07 03:46:32 PM PST 24 |
| Peak memory | 203300 kb |
| Host | smart-58066d14-93f7-4329-9a26-a609af37ae28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2354149928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2354149928 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2561559571 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 8556908422 ps |
| CPU time | 27.88 seconds |
| Started | Feb 07 03:46:22 PM PST 24 |
| Finished | Feb 07 03:46:50 PM PST 24 |
| Peak memory | 203476 kb |
| Host | smart-45eb3073-25d8-4848-9a37-9fcac1870e9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561559571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2561559571 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2142079064 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 3796934563 ps |
| CPU time | 32.65 seconds |
| Started | Feb 07 03:46:23 PM PST 24 |
| Finished | Feb 07 03:46:56 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-f8924ada-9c69-4cc1-b9c2-9a44e51f4dfa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2142079064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2142079064 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3263102160 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 66239621 ps |
| CPU time | 2.44 seconds |
| Started | Feb 07 03:46:23 PM PST 24 |
| Finished | Feb 07 03:46:26 PM PST 24 |
| Peak memory | 203240 kb |
| Host | smart-ded0fffc-0dda-4d4a-b4d2-81ae5ea4a94e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263102160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3263102160 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.933750176 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 392719672 ps |
| CPU time | 53.97 seconds |
| Started | Feb 07 03:46:24 PM PST 24 |
| Finished | Feb 07 03:47:18 PM PST 24 |
| Peak memory | 206412 kb |
| Host | smart-6fb236c4-5f5f-4b92-8b39-dce42ffa4131 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=933750176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.933750176 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3372282440 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 3489085900 ps |
| CPU time | 183.37 seconds |
| Started | Feb 07 03:46:25 PM PST 24 |
| Finished | Feb 07 03:49:28 PM PST 24 |
| Peak memory | 206988 kb |
| Host | smart-ca84c4ee-99bf-4ead-b559-d72442e5e29a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3372282440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3372282440 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1148573865 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4111767843 ps |
| CPU time | 626.19 seconds |
| Started | Feb 07 03:46:23 PM PST 24 |
| Finished | Feb 07 03:56:50 PM PST 24 |
| Peak memory | 222680 kb |
| Host | smart-2b1d41fc-5b00-4b96-8904-22d8527bf8fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1148573865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1148573865 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2285289760 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 58469225 ps |
| CPU time | 17.27 seconds |
| Started | Feb 07 03:46:28 PM PST 24 |
| Finished | Feb 07 03:46:45 PM PST 24 |
| Peak memory | 205572 kb |
| Host | smart-e5f56eb1-0abd-4e2e-990d-1b024dd104e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2285289760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.2285289760 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.631007160 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 486603349 ps |
| CPU time | 16.49 seconds |
| Started | Feb 07 03:46:24 PM PST 24 |
| Finished | Feb 07 03:46:41 PM PST 24 |
| Peak memory | 204816 kb |
| Host | smart-0982b44a-0f96-4f64-845d-ad957154f193 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=631007160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.631007160 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.4071801173 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 43973927 ps |
| CPU time | 2.82 seconds |
| Started | Feb 07 03:46:37 PM PST 24 |
| Finished | Feb 07 03:46:42 PM PST 24 |
| Peak memory | 203260 kb |
| Host | smart-97076e4f-e0f8-4ff7-8d5b-d658c53c5579 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4071801173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.4071801173 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3873217666 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 49993934595 ps |
| CPU time | 458.06 seconds |
| Started | Feb 07 03:46:30 PM PST 24 |
| Finished | Feb 07 03:54:08 PM PST 24 |
| Peak memory | 207164 kb |
| Host | smart-030e4c55-875d-4bab-9ed6-f375d91434cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3873217666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3873217666 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.860218501 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 175726615 ps |
| CPU time | 14.73 seconds |
| Started | Feb 07 03:46:34 PM PST 24 |
| Finished | Feb 07 03:46:49 PM PST 24 |
| Peak memory | 203724 kb |
| Host | smart-c2cb7eb9-3915-4661-9a5a-616efa2c96be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=860218501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.860218501 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.4111371484 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 213678682 ps |
| CPU time | 6.52 seconds |
| Started | Feb 07 03:46:31 PM PST 24 |
| Finished | Feb 07 03:46:38 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-d00acf51-dced-471a-9038-2b346e828848 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4111371484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.4111371484 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.738007777 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 158089325 ps |
| CPU time | 10.22 seconds |
| Started | Feb 07 03:46:32 PM PST 24 |
| Finished | Feb 07 03:46:43 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-8029ac55-68ee-453c-ac60-9db0dc504d8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=738007777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.738007777 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.2816069629 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 29086387166 ps |
| CPU time | 171.65 seconds |
| Started | Feb 07 03:46:34 PM PST 24 |
| Finished | Feb 07 03:49:27 PM PST 24 |
| Peak memory | 211596 kb |
| Host | smart-a9187131-5a1c-4bde-8aec-0c16449b2f58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816069629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2816069629 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3356327094 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 67376221665 ps |
| CPU time | 214.25 seconds |
| Started | Feb 07 03:46:37 PM PST 24 |
| Finished | Feb 07 03:50:13 PM PST 24 |
| Peak memory | 211580 kb |
| Host | smart-87959b89-68e5-4072-8646-8a5cf7826162 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3356327094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3356327094 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.2761451918 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 175339683 ps |
| CPU time | 17.7 seconds |
| Started | Feb 07 03:46:31 PM PST 24 |
| Finished | Feb 07 03:46:49 PM PST 24 |
| Peak memory | 211552 kb |
| Host | smart-f68220bd-b77d-4564-8713-d22a54881b81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761451918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2761451918 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.2014615562 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1353210243 ps |
| CPU time | 21.94 seconds |
| Started | Feb 07 03:46:30 PM PST 24 |
| Finished | Feb 07 03:46:52 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-32f8968d-9e18-4eb0-a3f5-67d353bc2105 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2014615562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2014615562 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.1462558608 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 35450998 ps |
| CPU time | 2.41 seconds |
| Started | Feb 07 03:46:31 PM PST 24 |
| Finished | Feb 07 03:46:34 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-2b0418b1-f07c-4049-b50f-f6ca8972141b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1462558608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1462558608 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.1900172741 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 13456813205 ps |
| CPU time | 34.63 seconds |
| Started | Feb 07 03:46:31 PM PST 24 |
| Finished | Feb 07 03:47:06 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-4c572a2c-d2ea-493e-aee4-2abfb1439f22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900172741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1900172741 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3783482910 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2199741994 ps |
| CPU time | 21.16 seconds |
| Started | Feb 07 03:46:34 PM PST 24 |
| Finished | Feb 07 03:46:56 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-9889bce2-c533-4fee-8481-c2d79285db24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3783482910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3783482910 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.4233908362 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 39688739 ps |
| CPU time | 2.65 seconds |
| Started | Feb 07 03:46:30 PM PST 24 |
| Finished | Feb 07 03:46:34 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-fc9dd7e5-4af9-45b9-9899-b68a64a857bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233908362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.4233908362 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.4273842441 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 4307284158 ps |
| CPU time | 67.6 seconds |
| Started | Feb 07 03:46:32 PM PST 24 |
| Finished | Feb 07 03:47:40 PM PST 24 |
| Peak memory | 207136 kb |
| Host | smart-4095e433-542b-4b18-a789-2dc690cf14d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4273842441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.4273842441 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3240270906 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 17107051776 ps |
| CPU time | 99.99 seconds |
| Started | Feb 07 03:46:37 PM PST 24 |
| Finished | Feb 07 03:48:19 PM PST 24 |
| Peak memory | 206068 kb |
| Host | smart-efe04c45-285b-4416-9390-53b04d9e4355 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3240270906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3240270906 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2906811971 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 256886804 ps |
| CPU time | 68.51 seconds |
| Started | Feb 07 03:46:38 PM PST 24 |
| Finished | Feb 07 03:47:47 PM PST 24 |
| Peak memory | 208112 kb |
| Host | smart-52f9e998-d3be-4689-a7c8-a194cc745f8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2906811971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.2906811971 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.2652639158 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 897346130 ps |
| CPU time | 17.71 seconds |
| Started | Feb 07 03:46:30 PM PST 24 |
| Finished | Feb 07 03:46:48 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-d87dcb10-bd24-44e3-939c-a0972fb7f948 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2652639158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2652639158 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3930375404 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 406776176 ps |
| CPU time | 31.84 seconds |
| Started | Feb 07 03:46:41 PM PST 24 |
| Finished | Feb 07 03:47:14 PM PST 24 |
| Peak memory | 205904 kb |
| Host | smart-a29f7b69-c684-4b85-9553-0c433f349ffb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3930375404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3930375404 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1208878477 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 131754245198 ps |
| CPU time | 503.13 seconds |
| Started | Feb 07 03:46:39 PM PST 24 |
| Finished | Feb 07 03:55:03 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-3b787cb1-b0d0-46ad-aa2a-8f80cc24a384 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1208878477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.1208878477 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1386816810 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3597919471 ps |
| CPU time | 32.25 seconds |
| Started | Feb 07 03:46:36 PM PST 24 |
| Finished | Feb 07 03:47:11 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-6173da84-e589-4e9c-bf9d-9707599c9d82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1386816810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1386816810 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.2130510339 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 54015276 ps |
| CPU time | 4.48 seconds |
| Started | Feb 07 03:46:39 PM PST 24 |
| Finished | Feb 07 03:46:44 PM PST 24 |
| Peak memory | 203284 kb |
| Host | smart-a370702c-59f2-4136-bc66-417444c5788f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2130510339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2130510339 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.1552885347 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 927124101 ps |
| CPU time | 16.31 seconds |
| Started | Feb 07 03:46:37 PM PST 24 |
| Finished | Feb 07 03:46:55 PM PST 24 |
| Peak memory | 204528 kb |
| Host | smart-9512f24e-a20f-41d9-832e-92c4088e44d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1552885347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1552885347 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.3225917825 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 8149318072 ps |
| CPU time | 24.77 seconds |
| Started | Feb 07 03:46:38 PM PST 24 |
| Finished | Feb 07 03:47:04 PM PST 24 |
| Peak memory | 204124 kb |
| Host | smart-52d69aab-cddc-4410-9c71-58b89005cddd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225917825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3225917825 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.2865113996 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 23049775027 ps |
| CPU time | 211.26 seconds |
| Started | Feb 07 03:46:36 PM PST 24 |
| Finished | Feb 07 03:50:10 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-9f74393d-f67c-4c55-98dc-46e7e8e473c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2865113996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2865113996 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.528642673 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 27993083 ps |
| CPU time | 2.43 seconds |
| Started | Feb 07 03:46:37 PM PST 24 |
| Finished | Feb 07 03:46:41 PM PST 24 |
| Peak memory | 203360 kb |
| Host | smart-bcd18921-33dd-4cbe-9263-9c858f34c31d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528642673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.528642673 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.1119068533 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 463260398 ps |
| CPU time | 11.61 seconds |
| Started | Feb 07 03:46:38 PM PST 24 |
| Finished | Feb 07 03:46:51 PM PST 24 |
| Peak memory | 203864 kb |
| Host | smart-0ad32c0a-61f5-4a8f-970e-9ebda8c0226f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1119068533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1119068533 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.1056827078 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 263912224 ps |
| CPU time | 4.03 seconds |
| Started | Feb 07 03:46:37 PM PST 24 |
| Finished | Feb 07 03:46:43 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-31e35439-d0c5-48bd-bde1-69a7421fe523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1056827078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1056827078 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.958549036 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 16546714617 ps |
| CPU time | 35.72 seconds |
| Started | Feb 07 03:46:43 PM PST 24 |
| Finished | Feb 07 03:47:20 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-796f28ad-2e3d-408d-8608-e8205f25e1fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=958549036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.958549036 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1827296536 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 13592886555 ps |
| CPU time | 38.44 seconds |
| Started | Feb 07 03:46:38 PM PST 24 |
| Finished | Feb 07 03:47:17 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-eb69b5f3-cfab-4043-b3ab-254a9840880f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1827296536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1827296536 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.4067857593 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 55755835 ps |
| CPU time | 2.25 seconds |
| Started | Feb 07 03:46:39 PM PST 24 |
| Finished | Feb 07 03:46:42 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-2c1a3b3b-f6cb-4572-8100-282c21518ea9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067857593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.4067857593 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.2631690715 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 6134419892 ps |
| CPU time | 95.61 seconds |
| Started | Feb 07 03:46:36 PM PST 24 |
| Finished | Feb 07 03:48:15 PM PST 24 |
| Peak memory | 207356 kb |
| Host | smart-a9d5fbe8-27e3-4bf3-a2b8-dafc3963c9dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2631690715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2631690715 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1673039504 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 6814101299 ps |
| CPU time | 248.81 seconds |
| Started | Feb 07 03:46:38 PM PST 24 |
| Finished | Feb 07 03:50:48 PM PST 24 |
| Peak memory | 206864 kb |
| Host | smart-8bc74538-5798-432c-89d9-ac6f0a4587e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1673039504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1673039504 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2529985109 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 651990060 ps |
| CPU time | 244.69 seconds |
| Started | Feb 07 03:46:38 PM PST 24 |
| Finished | Feb 07 03:50:44 PM PST 24 |
| Peak memory | 208232 kb |
| Host | smart-b7d6e814-d8e4-4aea-a6d5-1f4512dc95a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2529985109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.2529985109 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3428029171 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2938904708 ps |
| CPU time | 287.15 seconds |
| Started | Feb 07 03:46:38 PM PST 24 |
| Finished | Feb 07 03:51:26 PM PST 24 |
| Peak memory | 219840 kb |
| Host | smart-e89c390a-1def-41c2-88a6-38e70ec271ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3428029171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.3428029171 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1740260613 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 66187782 ps |
| CPU time | 10.81 seconds |
| Started | Feb 07 03:46:39 PM PST 24 |
| Finished | Feb 07 03:46:50 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-a33cabf0-56b9-4b54-8ef9-f84ef174d260 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1740260613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1740260613 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.2897202087 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1069335945 ps |
| CPU time | 11.32 seconds |
| Started | Feb 07 03:46:43 PM PST 24 |
| Finished | Feb 07 03:46:55 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-5f0ae4da-c803-45ce-8939-3f505582b85b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2897202087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.2897202087 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.746818683 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 67362501754 ps |
| CPU time | 602.87 seconds |
| Started | Feb 07 03:46:45 PM PST 24 |
| Finished | Feb 07 03:56:48 PM PST 24 |
| Peak memory | 205864 kb |
| Host | smart-2290cea2-6220-4ba7-a082-097e363be3fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=746818683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slo w_rsp.746818683 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1770764467 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 243535793 ps |
| CPU time | 7.74 seconds |
| Started | Feb 07 03:46:59 PM PST 24 |
| Finished | Feb 07 03:47:09 PM PST 24 |
| Peak memory | 203264 kb |
| Host | smart-c89cac05-3b79-4d97-980b-118f28267940 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1770764467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1770764467 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.3918425388 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 526471683 ps |
| CPU time | 17.6 seconds |
| Started | Feb 07 03:46:43 PM PST 24 |
| Finished | Feb 07 03:47:01 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-de912c31-43f4-4bc3-a8f9-acea9d6ab249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3918425388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3918425388 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.346850738 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 755335995 ps |
| CPU time | 36.58 seconds |
| Started | Feb 07 03:46:46 PM PST 24 |
| Finished | Feb 07 03:47:23 PM PST 24 |
| Peak memory | 204576 kb |
| Host | smart-419f3ff5-2e7c-4757-ad65-0de05db34359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=346850738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.346850738 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2758609100 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 291441714429 ps |
| CPU time | 345.89 seconds |
| Started | Feb 07 03:46:45 PM PST 24 |
| Finished | Feb 07 03:52:31 PM PST 24 |
| Peak memory | 211648 kb |
| Host | smart-6516d3b6-9510-478e-afa6-b25932bcad7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758609100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2758609100 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1860195267 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 20682851257 ps |
| CPU time | 129.16 seconds |
| Started | Feb 07 03:46:44 PM PST 24 |
| Finished | Feb 07 03:48:53 PM PST 24 |
| Peak memory | 204692 kb |
| Host | smart-452b8be0-a99d-4416-af5c-6d89b17432c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1860195267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1860195267 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2430621170 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 183875165 ps |
| CPU time | 18.77 seconds |
| Started | Feb 07 03:46:45 PM PST 24 |
| Finished | Feb 07 03:47:04 PM PST 24 |
| Peak memory | 204472 kb |
| Host | smart-4db8ee81-e27a-46ae-a792-41bb7bb32793 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430621170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2430621170 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.199693710 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 829019927 ps |
| CPU time | 18.72 seconds |
| Started | Feb 07 03:46:43 PM PST 24 |
| Finished | Feb 07 03:47:02 PM PST 24 |
| Peak memory | 203864 kb |
| Host | smart-a83c40ce-f857-4276-872e-984726cc41ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=199693710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.199693710 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.1557992073 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 83291256 ps |
| CPU time | 2.63 seconds |
| Started | Feb 07 03:46:43 PM PST 24 |
| Finished | Feb 07 03:46:46 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-2e47a7d7-e2b0-4bd4-921d-848ae8c42197 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1557992073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1557992073 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.1469937835 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 8357619766 ps |
| CPU time | 25.55 seconds |
| Started | Feb 07 03:46:44 PM PST 24 |
| Finished | Feb 07 03:47:10 PM PST 24 |
| Peak memory | 203528 kb |
| Host | smart-733571fa-5943-428d-a145-5093b4ab61c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469937835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1469937835 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3460824688 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 5326626866 ps |
| CPU time | 31.71 seconds |
| Started | Feb 07 03:46:47 PM PST 24 |
| Finished | Feb 07 03:47:21 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-b220a6de-32b3-44b8-913b-e2feb760c99d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3460824688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3460824688 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2421820829 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 33583465 ps |
| CPU time | 2.23 seconds |
| Started | Feb 07 03:46:43 PM PST 24 |
| Finished | Feb 07 03:46:46 PM PST 24 |
| Peak memory | 203368 kb |
| Host | smart-81f82e8b-efc1-4321-8981-d6cf4f05b2da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421820829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2421820829 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.2501623187 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1260257051 ps |
| CPU time | 104.61 seconds |
| Started | Feb 07 03:46:59 PM PST 24 |
| Finished | Feb 07 03:48:46 PM PST 24 |
| Peak memory | 211640 kb |
| Host | smart-b09b617d-179b-4535-8205-e7feb0c99b0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2501623187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2501623187 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.2789190237 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 42487963 ps |
| CPU time | 5.25 seconds |
| Started | Feb 07 03:46:56 PM PST 24 |
| Finished | Feb 07 03:47:03 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-2b427bb4-7604-4d61-9a50-82b5be4da620 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2789190237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2789190237 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3142928382 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 120568255 ps |
| CPU time | 75.01 seconds |
| Started | Feb 07 03:46:55 PM PST 24 |
| Finished | Feb 07 03:48:12 PM PST 24 |
| Peak memory | 207980 kb |
| Host | smart-a01d4722-b905-4fe4-9009-34a75ce3303a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3142928382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.3142928382 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.543173884 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 7637845564 ps |
| CPU time | 371.16 seconds |
| Started | Feb 07 03:46:59 PM PST 24 |
| Finished | Feb 07 03:53:13 PM PST 24 |
| Peak memory | 219872 kb |
| Host | smart-d3ca26a3-948e-4cfc-9f24-afdd2b6f428b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=543173884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_res et_error.543173884 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3533099089 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 95961245 ps |
| CPU time | 7.9 seconds |
| Started | Feb 07 03:46:56 PM PST 24 |
| Finished | Feb 07 03:47:06 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-4087125d-9260-40e0-a528-389a604d9dbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3533099089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3533099089 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2666079871 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 551075970 ps |
| CPU time | 34.44 seconds |
| Started | Feb 07 03:47:00 PM PST 24 |
| Finished | Feb 07 03:47:36 PM PST 24 |
| Peak memory | 205344 kb |
| Host | smart-a43b5344-ea3d-4519-8944-9e2c8c5ccac8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2666079871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2666079871 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2404119444 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 44318615464 ps |
| CPU time | 251.44 seconds |
| Started | Feb 07 03:47:00 PM PST 24 |
| Finished | Feb 07 03:51:13 PM PST 24 |
| Peak memory | 206488 kb |
| Host | smart-87c73c81-9290-4a8d-9692-cf9056b2c07d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2404119444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.2404119444 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.1518720931 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 120298166 ps |
| CPU time | 13.38 seconds |
| Started | Feb 07 03:46:59 PM PST 24 |
| Finished | Feb 07 03:47:15 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-49f3e2da-6463-4da9-a5a7-74b9ba34fd94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1518720931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.1518720931 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.1787925905 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1138957439 ps |
| CPU time | 30.69 seconds |
| Started | Feb 07 03:46:57 PM PST 24 |
| Finished | Feb 07 03:47:29 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-3789f519-5903-4dcd-a059-69fbdf93cb20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1787925905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1787925905 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.931996413 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 59979265 ps |
| CPU time | 8.01 seconds |
| Started | Feb 07 03:46:59 PM PST 24 |
| Finished | Feb 07 03:47:09 PM PST 24 |
| Peak memory | 204492 kb |
| Host | smart-451d958e-a678-41e5-b763-f4a51e5c770a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=931996413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.931996413 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1016803203 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 41071633554 ps |
| CPU time | 173.46 seconds |
| Started | Feb 07 03:47:01 PM PST 24 |
| Finished | Feb 07 03:49:55 PM PST 24 |
| Peak memory | 211496 kb |
| Host | smart-612e68cc-6e22-4b9e-a7dc-77b562de913f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016803203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1016803203 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2961450908 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 49644349748 ps |
| CPU time | 222.6 seconds |
| Started | Feb 07 03:46:55 PM PST 24 |
| Finished | Feb 07 03:50:39 PM PST 24 |
| Peak memory | 205000 kb |
| Host | smart-b2013f6e-921c-4846-a78f-739d288a2cc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2961450908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2961450908 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.1784622096 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 248132159 ps |
| CPU time | 19.65 seconds |
| Started | Feb 07 03:46:56 PM PST 24 |
| Finished | Feb 07 03:47:17 PM PST 24 |
| Peak memory | 211612 kb |
| Host | smart-5ca9d6a8-99e4-4cf5-9c01-3f4f1536aa13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784622096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1784622096 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.3657391968 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 86462286 ps |
| CPU time | 7 seconds |
| Started | Feb 07 03:46:57 PM PST 24 |
| Finished | Feb 07 03:47:05 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-8c1ee429-7c78-46e5-ae46-d085c4401c57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3657391968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3657391968 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.180286915 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 36335208 ps |
| CPU time | 2.68 seconds |
| Started | Feb 07 03:47:00 PM PST 24 |
| Finished | Feb 07 03:47:04 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-64f729cc-adc7-4f81-b8a4-873c4d821ea2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=180286915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.180286915 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.839455957 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 6115336096 ps |
| CPU time | 25.56 seconds |
| Started | Feb 07 03:46:56 PM PST 24 |
| Finished | Feb 07 03:47:22 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-62a66e8e-687f-4483-8e8e-214177ce964c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=839455957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.839455957 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2943014058 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 5268419293 ps |
| CPU time | 37.32 seconds |
| Started | Feb 07 03:46:57 PM PST 24 |
| Finished | Feb 07 03:47:37 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-69cd548a-9403-45ae-a437-2b75f6142fab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2943014058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2943014058 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1116825781 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 29593989 ps |
| CPU time | 2.64 seconds |
| Started | Feb 07 03:47:02 PM PST 24 |
| Finished | Feb 07 03:47:05 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-8f596e5e-efb6-47cc-8b27-918e0e1f9fa1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116825781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1116825781 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.436911957 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 14888963515 ps |
| CPU time | 153.18 seconds |
| Started | Feb 07 03:46:59 PM PST 24 |
| Finished | Feb 07 03:49:35 PM PST 24 |
| Peak memory | 207160 kb |
| Host | smart-fd50d7f5-3d7e-4afd-96cf-e6f9162afd0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=436911957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.436911957 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2905815872 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 3131003898 ps |
| CPU time | 113.16 seconds |
| Started | Feb 07 03:47:01 PM PST 24 |
| Finished | Feb 07 03:48:55 PM PST 24 |
| Peak memory | 207732 kb |
| Host | smart-7e527653-01a4-4bdc-81b9-65143125ce20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2905815872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2905815872 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1207537259 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 430654945 ps |
| CPU time | 188.03 seconds |
| Started | Feb 07 03:47:00 PM PST 24 |
| Finished | Feb 07 03:50:10 PM PST 24 |
| Peak memory | 208108 kb |
| Host | smart-20c9e7ad-cc12-472d-9d79-ed686b8f2f31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1207537259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1207537259 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.2588722803 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 421447695 ps |
| CPU time | 126.04 seconds |
| Started | Feb 07 03:47:01 PM PST 24 |
| Finished | Feb 07 03:49:08 PM PST 24 |
| Peak memory | 209288 kb |
| Host | smart-dc2e05a2-4794-4142-a604-d4a48f29c7db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2588722803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.2588722803 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.2671229728 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 126353803 ps |
| CPU time | 19.13 seconds |
| Started | Feb 07 03:47:01 PM PST 24 |
| Finished | Feb 07 03:47:21 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-1bf844df-c629-485e-a24f-1f72e7a214c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2671229728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2671229728 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.4257118657 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 227490308 ps |
| CPU time | 23.68 seconds |
| Started | Feb 07 03:47:13 PM PST 24 |
| Finished | Feb 07 03:47:37 PM PST 24 |
| Peak memory | 211412 kb |
| Host | smart-d07a26ba-7841-4a66-bedf-d60d385066ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4257118657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.4257118657 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3562527444 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 60971186524 ps |
| CPU time | 339.37 seconds |
| Started | Feb 07 03:47:13 PM PST 24 |
| Finished | Feb 07 03:52:53 PM PST 24 |
| Peak memory | 211564 kb |
| Host | smart-c5f3e2aa-f534-411a-ac51-2ed319010244 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3562527444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.3562527444 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1785448979 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2029984121 ps |
| CPU time | 19.89 seconds |
| Started | Feb 07 03:47:13 PM PST 24 |
| Finished | Feb 07 03:47:34 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-e6bd0cad-a25a-4320-8d88-c3e8741b8a5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1785448979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1785448979 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.2414394836 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 63328493 ps |
| CPU time | 2.3 seconds |
| Started | Feb 07 03:47:09 PM PST 24 |
| Finished | Feb 07 03:47:12 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-76df565e-15e0-4129-8098-802ee038a47d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2414394836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2414394836 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.938170401 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1342581141 ps |
| CPU time | 25.59 seconds |
| Started | Feb 07 03:47:11 PM PST 24 |
| Finished | Feb 07 03:47:37 PM PST 24 |
| Peak memory | 204440 kb |
| Host | smart-fda1e9f7-7b74-4740-9b50-3f5c45d7f5c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=938170401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.938170401 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.535536120 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 51240395569 ps |
| CPU time | 134.44 seconds |
| Started | Feb 07 03:47:11 PM PST 24 |
| Finished | Feb 07 03:49:26 PM PST 24 |
| Peak memory | 211692 kb |
| Host | smart-160bd7af-9ef8-4160-9a65-f479dfccb108 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=535536120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.535536120 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2668984730 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 42349243810 ps |
| CPU time | 190.23 seconds |
| Started | Feb 07 03:47:08 PM PST 24 |
| Finished | Feb 07 03:50:19 PM PST 24 |
| Peak memory | 204616 kb |
| Host | smart-982bf61d-0001-40b6-900b-393a3c920fb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2668984730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2668984730 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.310117265 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 287580687 ps |
| CPU time | 31.24 seconds |
| Started | Feb 07 03:47:13 PM PST 24 |
| Finished | Feb 07 03:47:45 PM PST 24 |
| Peak memory | 204440 kb |
| Host | smart-3e163c93-141c-4ee1-816e-30f0c5619dff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310117265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.310117265 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.3649829863 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 199015309 ps |
| CPU time | 3.33 seconds |
| Started | Feb 07 03:47:13 PM PST 24 |
| Finished | Feb 07 03:47:17 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-ce277e40-8160-4245-8b24-98c06e0d3528 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3649829863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3649829863 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.3000308588 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 63553543 ps |
| CPU time | 2.29 seconds |
| Started | Feb 07 03:46:59 PM PST 24 |
| Finished | Feb 07 03:47:04 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-5a17d696-70d2-4654-a7e6-cae168f0d1c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3000308588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3000308588 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3908125731 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 5345687054 ps |
| CPU time | 30.62 seconds |
| Started | Feb 07 03:47:11 PM PST 24 |
| Finished | Feb 07 03:47:42 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-a2a1a9ea-97d2-4b73-8cc7-61c774bf50c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908125731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3908125731 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3712306454 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3148394950 ps |
| CPU time | 25.9 seconds |
| Started | Feb 07 03:47:14 PM PST 24 |
| Finished | Feb 07 03:47:40 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-e9c1a4e3-0da9-41f9-af4d-f346d73a86bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3712306454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3712306454 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3929813739 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 22802083 ps |
| CPU time | 2.23 seconds |
| Started | Feb 07 03:47:01 PM PST 24 |
| Finished | Feb 07 03:47:04 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-151fc75d-18bb-47a4-9589-b3249c413d7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929813739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3929813739 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2300842856 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 7778275031 ps |
| CPU time | 326.35 seconds |
| Started | Feb 07 03:47:10 PM PST 24 |
| Finished | Feb 07 03:52:37 PM PST 24 |
| Peak memory | 212068 kb |
| Host | smart-2b8610b5-5300-4f53-b890-d79226dc7bff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2300842856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2300842856 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.180221843 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 228092252 ps |
| CPU time | 31.45 seconds |
| Started | Feb 07 03:47:13 PM PST 24 |
| Finished | Feb 07 03:47:45 PM PST 24 |
| Peak memory | 205184 kb |
| Host | smart-e687ff31-57a6-46ff-aeaa-d7093fe5e89e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=180221843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.180221843 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3559502644 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5738254589 ps |
| CPU time | 400.45 seconds |
| Started | Feb 07 03:47:11 PM PST 24 |
| Finished | Feb 07 03:53:52 PM PST 24 |
| Peak memory | 208564 kb |
| Host | smart-51126b74-8bfb-4c29-8ac7-d47536524f42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3559502644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.3559502644 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3417876325 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 7849708790 ps |
| CPU time | 314.66 seconds |
| Started | Feb 07 03:47:15 PM PST 24 |
| Finished | Feb 07 03:52:30 PM PST 24 |
| Peak memory | 219860 kb |
| Host | smart-554ef376-32c2-4bc4-9e64-2505c908c94e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3417876325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.3417876325 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.3676236626 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 156668178 ps |
| CPU time | 10.4 seconds |
| Started | Feb 07 03:47:13 PM PST 24 |
| Finished | Feb 07 03:47:24 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-14440110-8c34-4ef4-9aa9-8c80acfcfae8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3676236626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3676236626 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.2649957273 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1855869924 ps |
| CPU time | 68.04 seconds |
| Started | Feb 07 03:47:11 PM PST 24 |
| Finished | Feb 07 03:48:20 PM PST 24 |
| Peak memory | 205272 kb |
| Host | smart-748dc46f-d277-4b8c-b990-7a48526d066c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2649957273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.2649957273 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.322335791 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 25125152866 ps |
| CPU time | 224.25 seconds |
| Started | Feb 07 03:47:11 PM PST 24 |
| Finished | Feb 07 03:50:56 PM PST 24 |
| Peak memory | 211704 kb |
| Host | smart-623977ad-12fa-45b5-b2e1-976727f2ff67 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=322335791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slo w_rsp.322335791 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1142419792 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1146485252 ps |
| CPU time | 11 seconds |
| Started | Feb 07 03:47:13 PM PST 24 |
| Finished | Feb 07 03:47:25 PM PST 24 |
| Peak memory | 203588 kb |
| Host | smart-f27aa54e-014b-4745-b117-b00e65f07419 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1142419792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1142419792 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.4023423876 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 818932992 ps |
| CPU time | 25.75 seconds |
| Started | Feb 07 03:47:16 PM PST 24 |
| Finished | Feb 07 03:47:43 PM PST 24 |
| Peak memory | 203272 kb |
| Host | smart-7846b4a0-5670-4d67-ab5f-001ba315da27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4023423876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4023423876 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.3506279323 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 229187171 ps |
| CPU time | 25.41 seconds |
| Started | Feb 07 03:47:15 PM PST 24 |
| Finished | Feb 07 03:47:40 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-9739d392-593b-4246-88d8-a6da528f331f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3506279323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3506279323 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3378131003 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5425973114 ps |
| CPU time | 28.7 seconds |
| Started | Feb 07 03:47:12 PM PST 24 |
| Finished | Feb 07 03:47:41 PM PST 24 |
| Peak memory | 204168 kb |
| Host | smart-b73400a6-4b2c-4b39-93c8-c988b81b91f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378131003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3378131003 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2538969117 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 39282258216 ps |
| CPU time | 175.71 seconds |
| Started | Feb 07 03:47:16 PM PST 24 |
| Finished | Feb 07 03:50:13 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-71c26599-1107-4ec7-b2f9-8f4f6180b9cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2538969117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2538969117 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3192143633 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 180103131 ps |
| CPU time | 21.26 seconds |
| Started | Feb 07 03:47:13 PM PST 24 |
| Finished | Feb 07 03:47:35 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-07b23c9d-3c79-473a-b729-355739beb221 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192143633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3192143633 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1092767992 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 68080895 ps |
| CPU time | 3.45 seconds |
| Started | Feb 07 03:47:11 PM PST 24 |
| Finished | Feb 07 03:47:16 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-0c9c8fb3-9870-4a7b-b4e9-5631dafe16a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1092767992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1092767992 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.1319296885 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 133931615 ps |
| CPU time | 3.2 seconds |
| Started | Feb 07 03:47:12 PM PST 24 |
| Finished | Feb 07 03:47:16 PM PST 24 |
| Peak memory | 203352 kb |
| Host | smart-7ef10ca6-1ca0-4bb9-9bbe-8f088bb9cd3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1319296885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1319296885 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2643912931 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 5424123330 ps |
| CPU time | 26.91 seconds |
| Started | Feb 07 03:47:15 PM PST 24 |
| Finished | Feb 07 03:47:43 PM PST 24 |
| Peak memory | 203512 kb |
| Host | smart-34ec690e-84d2-48b8-8118-b000e46499e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643912931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2643912931 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2344301434 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 23018978218 ps |
| CPU time | 36.11 seconds |
| Started | Feb 07 03:47:15 PM PST 24 |
| Finished | Feb 07 03:47:51 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-9b4c9a91-c48c-4606-9430-390c85b0e16d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2344301434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2344301434 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1766833082 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 149052200 ps |
| CPU time | 2.7 seconds |
| Started | Feb 07 03:47:12 PM PST 24 |
| Finished | Feb 07 03:47:16 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-dabab8d9-e25f-4ef1-ae76-9d09ffcb0975 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766833082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1766833082 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.1734634065 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 5584171170 ps |
| CPU time | 232.36 seconds |
| Started | Feb 07 03:47:14 PM PST 24 |
| Finished | Feb 07 03:51:07 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-82b2e723-8bac-4459-a5cc-cb9570229325 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1734634065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1734634065 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2836815782 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1758596934 ps |
| CPU time | 72.86 seconds |
| Started | Feb 07 03:47:12 PM PST 24 |
| Finished | Feb 07 03:48:25 PM PST 24 |
| Peak memory | 211592 kb |
| Host | smart-a202fed6-c325-419e-a6e9-efd8a444dc38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2836815782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2836815782 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2079202348 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 22147094 ps |
| CPU time | 17.14 seconds |
| Started | Feb 07 03:47:15 PM PST 24 |
| Finished | Feb 07 03:47:33 PM PST 24 |
| Peak memory | 206008 kb |
| Host | smart-1dc93110-4a2b-4a5b-af9c-16b0ec71b2c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2079202348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.2079202348 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3987642421 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1227577479 ps |
| CPU time | 195.76 seconds |
| Started | Feb 07 03:47:16 PM PST 24 |
| Finished | Feb 07 03:50:33 PM PST 24 |
| Peak memory | 211928 kb |
| Host | smart-36b2af16-7d4d-4e41-afee-fb70301bdfe8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3987642421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.3987642421 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3762054173 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 106675840 ps |
| CPU time | 15.94 seconds |
| Started | Feb 07 03:47:16 PM PST 24 |
| Finished | Feb 07 03:47:33 PM PST 24 |
| Peak memory | 204844 kb |
| Host | smart-c39654ea-c31e-4740-a7ab-38f097616a4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3762054173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3762054173 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.919202434 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2509156449 ps |
| CPU time | 41.67 seconds |
| Started | Feb 07 03:47:19 PM PST 24 |
| Finished | Feb 07 03:48:01 PM PST 24 |
| Peak memory | 206136 kb |
| Host | smart-8dab9aaf-5ba2-4699-a2bf-56c3dfabb0c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=919202434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.919202434 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2612612747 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 63579256324 ps |
| CPU time | 341.89 seconds |
| Started | Feb 07 03:47:23 PM PST 24 |
| Finished | Feb 07 03:53:06 PM PST 24 |
| Peak memory | 206620 kb |
| Host | smart-210979f4-53b6-44f8-9357-1e552dcfbf12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2612612747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2612612747 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3163272503 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 443679650 ps |
| CPU time | 14.01 seconds |
| Started | Feb 07 03:47:19 PM PST 24 |
| Finished | Feb 07 03:47:33 PM PST 24 |
| Peak memory | 203364 kb |
| Host | smart-40f72ced-9034-4fbb-8c30-6473c9b820e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3163272503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3163272503 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.1127938939 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1113692658 ps |
| CPU time | 21.87 seconds |
| Started | Feb 07 03:47:21 PM PST 24 |
| Finished | Feb 07 03:47:44 PM PST 24 |
| Peak memory | 203296 kb |
| Host | smart-7104ed13-6fdf-434b-8bae-00e71d726ea1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1127938939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1127938939 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.3783433676 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 242255332 ps |
| CPU time | 24.75 seconds |
| Started | Feb 07 03:47:22 PM PST 24 |
| Finished | Feb 07 03:47:47 PM PST 24 |
| Peak memory | 211544 kb |
| Host | smart-dc639a46-62ac-4fc4-bd82-5acad38847be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3783433676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3783433676 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2066950058 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 53191228886 ps |
| CPU time | 176.68 seconds |
| Started | Feb 07 03:47:21 PM PST 24 |
| Finished | Feb 07 03:50:18 PM PST 24 |
| Peak memory | 211672 kb |
| Host | smart-d3e25ae1-887c-4eb1-bf4f-9a790ae8f934 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066950058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2066950058 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2971802545 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 10119827334 ps |
| CPU time | 55.02 seconds |
| Started | Feb 07 03:47:18 PM PST 24 |
| Finished | Feb 07 03:48:14 PM PST 24 |
| Peak memory | 211736 kb |
| Host | smart-58ea0351-0c1f-4c14-96ed-ca1e08907341 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2971802545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2971802545 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2474092449 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 73409063 ps |
| CPU time | 8.02 seconds |
| Started | Feb 07 03:47:24 PM PST 24 |
| Finished | Feb 07 03:47:32 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-b4d51dd8-edad-44c6-8ceb-f256f65f9cdc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474092449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2474092449 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.874035613 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 298105227 ps |
| CPU time | 14.38 seconds |
| Started | Feb 07 03:47:19 PM PST 24 |
| Finished | Feb 07 03:47:34 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-d43bcedd-7a59-4c33-a714-bceb32ce7946 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=874035613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.874035613 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.2971462396 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 70617324 ps |
| CPU time | 2.5 seconds |
| Started | Feb 07 03:47:20 PM PST 24 |
| Finished | Feb 07 03:47:23 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-0c0922b1-3810-4995-8bcc-04038dcb54f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2971462396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2971462396 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2583014673 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 9442082227 ps |
| CPU time | 30.84 seconds |
| Started | Feb 07 03:47:21 PM PST 24 |
| Finished | Feb 07 03:47:52 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-84dedca2-35d5-4968-bbe7-3bc333bb55fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583014673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2583014673 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.4074234357 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 31850879576 ps |
| CPU time | 54.68 seconds |
| Started | Feb 07 03:47:19 PM PST 24 |
| Finished | Feb 07 03:48:14 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-d7610fed-5374-4883-87ff-433d747c7d2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4074234357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.4074234357 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1187224401 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 27063863 ps |
| CPU time | 2.31 seconds |
| Started | Feb 07 03:47:17 PM PST 24 |
| Finished | Feb 07 03:47:20 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-6582641d-4fc9-4c32-a144-accc608d7249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187224401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1187224401 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1788103038 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 740530060 ps |
| CPU time | 86.62 seconds |
| Started | Feb 07 03:47:25 PM PST 24 |
| Finished | Feb 07 03:48:52 PM PST 24 |
| Peak memory | 206892 kb |
| Host | smart-483dc6a9-f02c-4c84-9adf-446e7345e7b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1788103038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1788103038 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.796822339 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 380673873 ps |
| CPU time | 90.6 seconds |
| Started | Feb 07 03:47:31 PM PST 24 |
| Finished | Feb 07 03:49:02 PM PST 24 |
| Peak memory | 208636 kb |
| Host | smart-735084b7-e722-471f-a21b-2a72fa2168cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=796822339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand _reset.796822339 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.4243561357 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 292879677 ps |
| CPU time | 104.62 seconds |
| Started | Feb 07 03:47:26 PM PST 24 |
| Finished | Feb 07 03:49:11 PM PST 24 |
| Peak memory | 211564 kb |
| Host | smart-19250f10-8c69-417f-8bf4-5093c6b99bdd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4243561357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.4243561357 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2726073814 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 921269772 ps |
| CPU time | 26.16 seconds |
| Started | Feb 07 03:47:21 PM PST 24 |
| Finished | Feb 07 03:47:48 PM PST 24 |
| Peak memory | 205008 kb |
| Host | smart-b5d99bb2-7dce-44f4-bd24-c175b82ec832 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2726073814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2726073814 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1237838217 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 961960509 ps |
| CPU time | 31.71 seconds |
| Started | Feb 07 03:38:55 PM PST 24 |
| Finished | Feb 07 03:39:27 PM PST 24 |
| Peak memory | 205264 kb |
| Host | smart-b3a7f6e1-f602-4734-8c15-6032067eb3d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1237838217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1237838217 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.149132839 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 52752857739 ps |
| CPU time | 457.72 seconds |
| Started | Feb 07 03:38:55 PM PST 24 |
| Finished | Feb 07 03:46:33 PM PST 24 |
| Peak memory | 210568 kb |
| Host | smart-5e4e944a-f4f6-471d-a35a-445b40a6b180 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=149132839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow _rsp.149132839 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1683973709 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 5136115031 ps |
| CPU time | 26.25 seconds |
| Started | Feb 07 03:38:54 PM PST 24 |
| Finished | Feb 07 03:39:21 PM PST 24 |
| Peak memory | 203992 kb |
| Host | smart-03ce8b3c-7357-445e-a698-4ac39428d26a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1683973709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1683973709 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.2106296515 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 118153719 ps |
| CPU time | 14.62 seconds |
| Started | Feb 07 03:38:53 PM PST 24 |
| Finished | Feb 07 03:39:08 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-ff27da24-eae9-4b86-96cd-11ac535506ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2106296515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2106296515 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.364942468 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 826287550 ps |
| CPU time | 22.65 seconds |
| Started | Feb 07 03:38:47 PM PST 24 |
| Finished | Feb 07 03:39:10 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-4fe1fdec-be7a-41a3-bb43-c15014a0eefa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=364942468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.364942468 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2898040739 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 5826489926 ps |
| CPU time | 39.22 seconds |
| Started | Feb 07 03:38:47 PM PST 24 |
| Finished | Feb 07 03:39:27 PM PST 24 |
| Peak memory | 211692 kb |
| Host | smart-42573925-c970-4eb3-ad0a-6afa11ae5460 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898040739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2898040739 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1409219840 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 31192795188 ps |
| CPU time | 97.52 seconds |
| Started | Feb 07 03:38:55 PM PST 24 |
| Finished | Feb 07 03:40:33 PM PST 24 |
| Peak memory | 210652 kb |
| Host | smart-6fdb090e-7981-47ff-8b54-7350e0a0de5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1409219840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1409219840 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.367203012 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 86086070 ps |
| CPU time | 13.7 seconds |
| Started | Feb 07 03:38:52 PM PST 24 |
| Finished | Feb 07 03:39:06 PM PST 24 |
| Peak memory | 204100 kb |
| Host | smart-1e13779d-30a3-4a3b-aa8a-341946b3e444 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367203012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.367203012 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.2829700570 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 578126401 ps |
| CPU time | 10.67 seconds |
| Started | Feb 07 03:38:54 PM PST 24 |
| Finished | Feb 07 03:39:05 PM PST 24 |
| Peak memory | 203288 kb |
| Host | smart-6207cc82-abc1-4d21-8deb-210096bee60a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2829700570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2829700570 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.2852477180 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 57658498 ps |
| CPU time | 2.27 seconds |
| Started | Feb 07 03:38:48 PM PST 24 |
| Finished | Feb 07 03:38:50 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-c61eb048-5b1b-4340-bce9-1f022ae6e954 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2852477180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2852477180 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3009069134 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 6415155884 ps |
| CPU time | 39.05 seconds |
| Started | Feb 07 03:38:42 PM PST 24 |
| Finished | Feb 07 03:39:21 PM PST 24 |
| Peak memory | 203400 kb |
| Host | smart-a0fd2c81-8027-4e35-a72c-8c2c8fda66c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009069134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3009069134 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.728551997 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7502564782 ps |
| CPU time | 31.1 seconds |
| Started | Feb 07 03:38:45 PM PST 24 |
| Finished | Feb 07 03:39:17 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-3c981bf2-b71e-4365-a94e-3b49be42b86c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=728551997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.728551997 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2121398255 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 61351718 ps |
| CPU time | 2.61 seconds |
| Started | Feb 07 03:38:42 PM PST 24 |
| Finished | Feb 07 03:38:45 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-2da350f2-3d3b-4729-8b1a-3bc2f7e27777 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121398255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2121398255 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.361398206 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 271567439 ps |
| CPU time | 27.49 seconds |
| Started | Feb 07 03:39:03 PM PST 24 |
| Finished | Feb 07 03:39:31 PM PST 24 |
| Peak memory | 205600 kb |
| Host | smart-ab977c3b-7455-429e-bd60-2fe7ad252348 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=361398206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.361398206 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.3954724788 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1743104340 ps |
| CPU time | 102.45 seconds |
| Started | Feb 07 03:39:03 PM PST 24 |
| Finished | Feb 07 03:40:46 PM PST 24 |
| Peak memory | 207368 kb |
| Host | smart-e9c6b91a-62b5-4f08-ad0d-4a45b85f4c69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3954724788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3954724788 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2894677853 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 4232878166 ps |
| CPU time | 296.21 seconds |
| Started | Feb 07 03:39:03 PM PST 24 |
| Finished | Feb 07 03:44:00 PM PST 24 |
| Peak memory | 209340 kb |
| Host | smart-e01317b7-277e-4ab7-85f0-18a67cee794d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2894677853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.2894677853 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3933436906 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 628435572 ps |
| CPU time | 228.66 seconds |
| Started | Feb 07 03:39:09 PM PST 24 |
| Finished | Feb 07 03:42:58 PM PST 24 |
| Peak memory | 219692 kb |
| Host | smart-ee310096-506f-4847-b7d0-711a39e328c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3933436906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.3933436906 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.3414760167 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 70365930 ps |
| CPU time | 2.65 seconds |
| Started | Feb 07 03:38:56 PM PST 24 |
| Finished | Feb 07 03:38:59 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-944d0578-dedd-439c-a818-23266d9fb31b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3414760167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3414760167 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1431000833 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 119564954 ps |
| CPU time | 10.5 seconds |
| Started | Feb 07 03:39:17 PM PST 24 |
| Finished | Feb 07 03:39:27 PM PST 24 |
| Peak memory | 204052 kb |
| Host | smart-83773ff7-683b-4ab7-9c47-71236a816ee2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1431000833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1431000833 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1745636355 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 52550624 ps |
| CPU time | 2.02 seconds |
| Started | Feb 07 03:39:19 PM PST 24 |
| Finished | Feb 07 03:39:21 PM PST 24 |
| Peak memory | 203224 kb |
| Host | smart-890dcbf3-d68b-4831-83cb-7ed0f43aa616 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1745636355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1745636355 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.2399884293 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2162395389 ps |
| CPU time | 42.22 seconds |
| Started | Feb 07 03:39:21 PM PST 24 |
| Finished | Feb 07 03:40:03 PM PST 24 |
| Peak memory | 203564 kb |
| Host | smart-4a80c2b1-40f4-4819-a409-46bd7c311c8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2399884293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2399884293 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.1301623307 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 545581041 ps |
| CPU time | 6.76 seconds |
| Started | Feb 07 03:39:08 PM PST 24 |
| Finished | Feb 07 03:39:15 PM PST 24 |
| Peak memory | 204128 kb |
| Host | smart-a28041a9-3d40-4d6e-8d7c-5f734b9e6bd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1301623307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1301623307 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.4098494368 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 51985772139 ps |
| CPU time | 209.01 seconds |
| Started | Feb 07 03:39:15 PM PST 24 |
| Finished | Feb 07 03:42:45 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-1f94dde0-a648-4971-9c9f-3c8e0dccc207 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098494368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.4098494368 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.1054549648 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 51410489302 ps |
| CPU time | 248.13 seconds |
| Started | Feb 07 03:39:15 PM PST 24 |
| Finished | Feb 07 03:43:24 PM PST 24 |
| Peak memory | 211616 kb |
| Host | smart-e1133a34-d02c-4c2e-8a68-11c015519829 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1054549648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1054549648 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2781791255 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 338882504 ps |
| CPU time | 19.14 seconds |
| Started | Feb 07 03:39:15 PM PST 24 |
| Finished | Feb 07 03:39:35 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-da289c9e-6a99-44cd-9fad-6b65562363e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781791255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2781791255 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.2529824457 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 414181547 ps |
| CPU time | 18.03 seconds |
| Started | Feb 07 03:39:20 PM PST 24 |
| Finished | Feb 07 03:39:39 PM PST 24 |
| Peak memory | 203336 kb |
| Host | smart-403dc447-5e66-4fce-ad2c-2954c9f2a807 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2529824457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2529824457 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.2028424569 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 190555975 ps |
| CPU time | 3.73 seconds |
| Started | Feb 07 03:39:09 PM PST 24 |
| Finished | Feb 07 03:39:13 PM PST 24 |
| Peak memory | 203332 kb |
| Host | smart-f83cb883-9e79-479d-a280-343ccbde9e8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2028424569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2028424569 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1776593807 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8184674637 ps |
| CPU time | 28.33 seconds |
| Started | Feb 07 03:39:16 PM PST 24 |
| Finished | Feb 07 03:39:45 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-7f592a81-d42c-4f3c-bca1-d30c7fe09783 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776593807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1776593807 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1901070563 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3555660569 ps |
| CPU time | 29.34 seconds |
| Started | Feb 07 03:39:09 PM PST 24 |
| Finished | Feb 07 03:39:39 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-34972c4f-7ed9-491f-b382-edd67a9c834e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1901070563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1901070563 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2522598273 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 29191615 ps |
| CPU time | 2.19 seconds |
| Started | Feb 07 03:39:03 PM PST 24 |
| Finished | Feb 07 03:39:06 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-2cffbf6e-c18a-4f7a-ab60-dabe130c786e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522598273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2522598273 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.3716243575 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3159262205 ps |
| CPU time | 178.79 seconds |
| Started | Feb 07 03:39:20 PM PST 24 |
| Finished | Feb 07 03:42:19 PM PST 24 |
| Peak memory | 205800 kb |
| Host | smart-d7d6505a-4dca-447a-b111-9ed77d3e58c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3716243575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3716243575 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.3849158399 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1440935311 ps |
| CPU time | 83.96 seconds |
| Started | Feb 07 03:39:20 PM PST 24 |
| Finished | Feb 07 03:40:45 PM PST 24 |
| Peak memory | 207236 kb |
| Host | smart-e91a7c62-3803-4b0e-b949-a0e05d437d9c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3849158399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3849158399 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.4142582088 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3015757509 ps |
| CPU time | 206.61 seconds |
| Started | Feb 07 03:39:21 PM PST 24 |
| Finished | Feb 07 03:42:48 PM PST 24 |
| Peak memory | 208016 kb |
| Host | smart-a2c9bf25-b327-4c18-a952-0ca1f72d6522 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4142582088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.4142582088 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1668912438 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 317822879 ps |
| CPU time | 86.56 seconds |
| Started | Feb 07 03:39:20 PM PST 24 |
| Finished | Feb 07 03:40:47 PM PST 24 |
| Peak memory | 208460 kb |
| Host | smart-346123ba-f475-4e47-bb18-1b9e4effc937 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1668912438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.1668912438 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.921072211 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 476543232 ps |
| CPU time | 12.58 seconds |
| Started | Feb 07 03:39:20 PM PST 24 |
| Finished | Feb 07 03:39:33 PM PST 24 |
| Peak memory | 204640 kb |
| Host | smart-910429ff-feee-4aa9-b193-36106c2809ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=921072211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.921072211 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.543216727 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 1157595035 ps |
| CPU time | 39.03 seconds |
| Started | Feb 07 03:39:35 PM PST 24 |
| Finished | Feb 07 03:40:15 PM PST 24 |
| Peak memory | 211568 kb |
| Host | smart-d76aa3c8-3e33-4f8e-84fb-5d08e62ccb99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=543216727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.543216727 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1576954402 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 70918164876 ps |
| CPU time | 339.07 seconds |
| Started | Feb 07 03:39:34 PM PST 24 |
| Finished | Feb 07 03:45:14 PM PST 24 |
| Peak memory | 205648 kb |
| Host | smart-88d3266c-40ee-4007-8e09-d11734972ffc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1576954402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.1576954402 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.276208737 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 45410359 ps |
| CPU time | 2.12 seconds |
| Started | Feb 07 03:39:34 PM PST 24 |
| Finished | Feb 07 03:39:37 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-fd25f6ac-4626-421f-b70b-0ad5f9a2e70e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=276208737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.276208737 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.1667332789 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 173251948 ps |
| CPU time | 12.64 seconds |
| Started | Feb 07 03:39:36 PM PST 24 |
| Finished | Feb 07 03:39:50 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-cada7490-9e96-4d39-9d0c-19e8a841e2d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1667332789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1667332789 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.245096777 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 118609470 ps |
| CPU time | 4.63 seconds |
| Started | Feb 07 03:39:27 PM PST 24 |
| Finished | Feb 07 03:39:32 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-713a317a-ec55-4233-ac46-b26b7691346c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=245096777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.245096777 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.328501212 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2081240191 ps |
| CPU time | 13.47 seconds |
| Started | Feb 07 03:39:31 PM PST 24 |
| Finished | Feb 07 03:39:48 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-c577ddbc-babd-4173-81ba-e113de74d949 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=328501212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.328501212 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.285776915 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3506251105 ps |
| CPU time | 34.24 seconds |
| Started | Feb 07 03:39:32 PM PST 24 |
| Finished | Feb 07 03:40:09 PM PST 24 |
| Peak memory | 211608 kb |
| Host | smart-f72a8d6e-9e55-44c1-a55a-25fd5838850f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=285776915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.285776915 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.2466676753 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 371424176 ps |
| CPU time | 24.21 seconds |
| Started | Feb 07 03:39:32 PM PST 24 |
| Finished | Feb 07 03:39:59 PM PST 24 |
| Peak memory | 211472 kb |
| Host | smart-3c7424c5-2016-4096-b931-227c58aace2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466676753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.2466676753 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.3368493561 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3170319587 ps |
| CPU time | 23.04 seconds |
| Started | Feb 07 03:39:39 PM PST 24 |
| Finished | Feb 07 03:40:02 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-bee230ea-1ba7-4266-90a8-fb0b42c98547 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3368493561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3368493561 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.1107843430 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 179578495 ps |
| CPU time | 2.9 seconds |
| Started | Feb 07 03:39:31 PM PST 24 |
| Finished | Feb 07 03:39:37 PM PST 24 |
| Peak memory | 203344 kb |
| Host | smart-e7aef917-cb8e-4127-9472-4be848c9e766 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1107843430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1107843430 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3229055612 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 7620125025 ps |
| CPU time | 29.6 seconds |
| Started | Feb 07 03:39:32 PM PST 24 |
| Finished | Feb 07 03:40:04 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-1d224b33-8d1d-40ee-bfc4-3cdabf8f1819 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229055612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3229055612 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3736506443 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 16478369388 ps |
| CPU time | 33.35 seconds |
| Started | Feb 07 03:39:26 PM PST 24 |
| Finished | Feb 07 03:39:59 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-199d2203-1b28-40ce-9dc5-95ed9e950512 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3736506443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3736506443 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3592129427 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 27630912 ps |
| CPU time | 2.31 seconds |
| Started | Feb 07 03:39:32 PM PST 24 |
| Finished | Feb 07 03:39:37 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-fc16f882-2c32-4f96-beaa-5a5a1e0f83cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592129427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3592129427 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.565404643 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 17617490728 ps |
| CPU time | 299.99 seconds |
| Started | Feb 07 03:39:33 PM PST 24 |
| Finished | Feb 07 03:44:34 PM PST 24 |
| Peak memory | 209196 kb |
| Host | smart-b231055e-71e9-4de6-b3a9-6be0850dac39 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=565404643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.565404643 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1085684485 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 293478957 ps |
| CPU time | 27.1 seconds |
| Started | Feb 07 03:39:43 PM PST 24 |
| Finished | Feb 07 03:40:15 PM PST 24 |
| Peak memory | 203644 kb |
| Host | smart-9e983367-4c21-449c-a80e-489f34efc836 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1085684485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1085684485 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.427200108 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3523508588 ps |
| CPU time | 227.17 seconds |
| Started | Feb 07 03:39:35 PM PST 24 |
| Finished | Feb 07 03:43:25 PM PST 24 |
| Peak memory | 209460 kb |
| Host | smart-6536f205-6fbc-4e10-b972-9a1ec5f4a26a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=427200108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_ reset.427200108 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3473482122 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 174189439 ps |
| CPU time | 67.7 seconds |
| Started | Feb 07 03:39:42 PM PST 24 |
| Finished | Feb 07 03:40:51 PM PST 24 |
| Peak memory | 208312 kb |
| Host | smart-dfc589eb-2675-48b2-9205-cdcd2e177bc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3473482122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.3473482122 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.3968941072 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 135418558 ps |
| CPU time | 14.54 seconds |
| Started | Feb 07 03:39:34 PM PST 24 |
| Finished | Feb 07 03:39:49 PM PST 24 |
| Peak memory | 211628 kb |
| Host | smart-03519558-3b5a-48f0-bee0-642a3fd57d42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3968941072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3968941072 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3972398383 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 5032846419 ps |
| CPU time | 65.88 seconds |
| Started | Feb 07 03:39:53 PM PST 24 |
| Finished | Feb 07 03:40:59 PM PST 24 |
| Peak memory | 204640 kb |
| Host | smart-0e1a6912-e10b-4e62-86bc-763eb3fc86fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3972398383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3972398383 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.510263020 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 84716568182 ps |
| CPU time | 473.85 seconds |
| Started | Feb 07 03:39:49 PM PST 24 |
| Finished | Feb 07 03:47:45 PM PST 24 |
| Peak memory | 206672 kb |
| Host | smart-2b1204d2-9623-4877-b7d9-292de8eecb41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=510263020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow _rsp.510263020 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.963629557 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 168043783 ps |
| CPU time | 9.65 seconds |
| Started | Feb 07 03:39:51 PM PST 24 |
| Finished | Feb 07 03:40:01 PM PST 24 |
| Peak memory | 203680 kb |
| Host | smart-0e9c5318-c424-4d43-86b1-27181681dee0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=963629557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.963629557 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.1488964437 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1146504535 ps |
| CPU time | 14.57 seconds |
| Started | Feb 07 03:39:50 PM PST 24 |
| Finished | Feb 07 03:40:05 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-8f9dffb4-aac8-4904-8d09-48dd98801752 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1488964437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1488964437 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.1555567713 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 4004532696 ps |
| CPU time | 30.43 seconds |
| Started | Feb 07 03:39:46 PM PST 24 |
| Finished | Feb 07 03:40:18 PM PST 24 |
| Peak memory | 204648 kb |
| Host | smart-44118ab3-dd8d-4fb2-9a9e-dd76ad4d13e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555567713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1555567713 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2814983422 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 36895974038 ps |
| CPU time | 56.39 seconds |
| Started | Feb 07 03:39:49 PM PST 24 |
| Finished | Feb 07 03:40:47 PM PST 24 |
| Peak memory | 204472 kb |
| Host | smart-65300ede-5b02-4667-9e66-036bc9401105 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814983422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2814983422 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1976034669 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3328750793 ps |
| CPU time | 15.11 seconds |
| Started | Feb 07 03:39:49 PM PST 24 |
| Finished | Feb 07 03:40:06 PM PST 24 |
| Peak memory | 203368 kb |
| Host | smart-69416b71-62dd-4358-a6b6-9050875d851a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1976034669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1976034669 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3469452012 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 530708495 ps |
| CPU time | 12.43 seconds |
| Started | Feb 07 03:39:42 PM PST 24 |
| Finished | Feb 07 03:39:55 PM PST 24 |
| Peak memory | 211500 kb |
| Host | smart-9f773258-14b7-485e-aa01-3f2539d30bcf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469452012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3469452012 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.2522572508 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1211794819 ps |
| CPU time | 26.63 seconds |
| Started | Feb 07 03:39:48 PM PST 24 |
| Finished | Feb 07 03:40:17 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-a1244e66-5eb4-47e1-a97d-983678cc024c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2522572508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2522572508 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.1471322056 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 135296283 ps |
| CPU time | 2.46 seconds |
| Started | Feb 07 03:39:41 PM PST 24 |
| Finished | Feb 07 03:39:44 PM PST 24 |
| Peak memory | 203320 kb |
| Host | smart-dd626999-9f87-4285-ad85-f67ad0146d56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1471322056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1471322056 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.4252905139 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 11794325740 ps |
| CPU time | 29.53 seconds |
| Started | Feb 07 03:39:40 PM PST 24 |
| Finished | Feb 07 03:40:11 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-94c899df-5a51-45af-9d5f-1cc780f12bf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252905139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.4252905139 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3852855958 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2332297897 ps |
| CPU time | 23.31 seconds |
| Started | Feb 07 03:39:42 PM PST 24 |
| Finished | Feb 07 03:40:06 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-2cab3e45-44b5-4f1b-bb08-37ed8e428538 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3852855958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3852855958 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2327604851 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 32271695 ps |
| CPU time | 2.73 seconds |
| Started | Feb 07 03:39:41 PM PST 24 |
| Finished | Feb 07 03:39:45 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-8829b391-191b-4021-8841-b3fa63d3026c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327604851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2327604851 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.3446806837 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3303636753 ps |
| CPU time | 56.61 seconds |
| Started | Feb 07 03:39:49 PM PST 24 |
| Finished | Feb 07 03:40:48 PM PST 24 |
| Peak memory | 207348 kb |
| Host | smart-8b317e95-2e66-406a-be15-e884a73995b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3446806837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3446806837 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1998566405 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 133031663 ps |
| CPU time | 19.33 seconds |
| Started | Feb 07 03:39:54 PM PST 24 |
| Finished | Feb 07 03:40:14 PM PST 24 |
| Peak memory | 204428 kb |
| Host | smart-4afbf88a-38cf-49d4-b5d0-35c0af45c1dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1998566405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1998566405 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3232467197 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1158646797 ps |
| CPU time | 102.3 seconds |
| Started | Feb 07 03:39:48 PM PST 24 |
| Finished | Feb 07 03:41:33 PM PST 24 |
| Peak memory | 207032 kb |
| Host | smart-add337d7-da6e-4e12-a942-dc5e6db6910d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3232467197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.3232467197 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3603006810 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 252808861 ps |
| CPU time | 60.92 seconds |
| Started | Feb 07 03:39:54 PM PST 24 |
| Finished | Feb 07 03:40:56 PM PST 24 |
| Peak memory | 207988 kb |
| Host | smart-bd310056-347c-4478-b4eb-28402f2e8fee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3603006810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.3603006810 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3885839335 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 309942051 ps |
| CPU time | 16.34 seconds |
| Started | Feb 07 03:39:48 PM PST 24 |
| Finished | Feb 07 03:40:07 PM PST 24 |
| Peak memory | 211572 kb |
| Host | smart-af7f8777-d548-448d-84dc-2775406a2ec1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3885839335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3885839335 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.2421660605 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 496327247 ps |
| CPU time | 30.97 seconds |
| Started | Feb 07 03:40:07 PM PST 24 |
| Finished | Feb 07 03:40:39 PM PST 24 |
| Peak memory | 204496 kb |
| Host | smart-e34e545f-a2f2-45f9-91e8-71c982c50b13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2421660605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2421660605 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.1726810372 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 211041034934 ps |
| CPU time | 528.01 seconds |
| Started | Feb 07 03:40:09 PM PST 24 |
| Finished | Feb 07 03:48:58 PM PST 24 |
| Peak memory | 205848 kb |
| Host | smart-5835215d-cbba-4e9f-90c0-e3c107e5ce97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1726810372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.1726810372 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1241118877 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 429375887 ps |
| CPU time | 22.06 seconds |
| Started | Feb 07 03:40:12 PM PST 24 |
| Finished | Feb 07 03:40:35 PM PST 24 |
| Peak memory | 203584 kb |
| Host | smart-1fd1fdce-cde4-4ae6-af26-6710aa56b4b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1241118877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1241118877 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.1647240334 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 931417436 ps |
| CPU time | 29.45 seconds |
| Started | Feb 07 03:40:11 PM PST 24 |
| Finished | Feb 07 03:40:41 PM PST 24 |
| Peak memory | 203336 kb |
| Host | smart-ae0c4cae-50a0-4c42-bb69-a47b389a01f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1647240334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1647240334 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.2058492785 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 18134091 ps |
| CPU time | 2.51 seconds |
| Started | Feb 07 03:40:11 PM PST 24 |
| Finished | Feb 07 03:40:14 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-851576e8-1660-44f1-9ea6-af1a17fa6f7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2058492785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2058492785 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3575900787 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 18972755964 ps |
| CPU time | 59.36 seconds |
| Started | Feb 07 03:40:11 PM PST 24 |
| Finished | Feb 07 03:41:11 PM PST 24 |
| Peak memory | 211676 kb |
| Host | smart-66e0bcce-9ec1-44a3-942f-75e38eb8c259 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575900787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3575900787 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.323541231 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 2897455979 ps |
| CPU time | 15.06 seconds |
| Started | Feb 07 03:40:11 PM PST 24 |
| Finished | Feb 07 03:40:27 PM PST 24 |
| Peak memory | 203508 kb |
| Host | smart-810c157e-db0b-4b38-a0cb-d23b58bc3309 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=323541231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.323541231 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.1642760126 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 75509904 ps |
| CPU time | 8.91 seconds |
| Started | Feb 07 03:40:09 PM PST 24 |
| Finished | Feb 07 03:40:18 PM PST 24 |
| Peak memory | 204384 kb |
| Host | smart-7c2bd99f-4d1b-4a1b-95f9-858e2afeb77d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642760126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1642760126 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.4239791498 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 871060960 ps |
| CPU time | 19.51 seconds |
| Started | Feb 07 03:40:05 PM PST 24 |
| Finished | Feb 07 03:40:26 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-c9ec2d33-49cd-4509-9b9d-ec7bb1c158ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4239791498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.4239791498 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3880668579 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 254084206 ps |
| CPU time | 3.49 seconds |
| Started | Feb 07 03:39:56 PM PST 24 |
| Finished | Feb 07 03:40:00 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-410e3ab0-2d44-416f-a7fc-395e4487fb08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3880668579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3880668579 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1999127484 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 6993944076 ps |
| CPU time | 34.69 seconds |
| Started | Feb 07 03:39:55 PM PST 24 |
| Finished | Feb 07 03:40:30 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-fb3ce89f-6d88-40f8-9ff8-1553d8f219a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999127484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1999127484 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1242545572 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4148376660 ps |
| CPU time | 26.13 seconds |
| Started | Feb 07 03:39:54 PM PST 24 |
| Finished | Feb 07 03:40:21 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-ddcb1382-2101-49b1-b43c-70f2f41e87ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1242545572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1242545572 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2841097722 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 27502189 ps |
| CPU time | 2.54 seconds |
| Started | Feb 07 03:39:54 PM PST 24 |
| Finished | Feb 07 03:39:57 PM PST 24 |
| Peak memory | 203396 kb |
| Host | smart-e2f1e233-6741-4646-af48-10139abe72f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841097722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2841097722 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.378515917 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 615921655 ps |
| CPU time | 60 seconds |
| Started | Feb 07 03:40:10 PM PST 24 |
| Finished | Feb 07 03:41:11 PM PST 24 |
| Peak memory | 206716 kb |
| Host | smart-d7f6b996-863a-4c01-a45a-26194b863dbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=378515917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.378515917 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.270840368 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1078039143 ps |
| CPU time | 70.4 seconds |
| Started | Feb 07 03:40:09 PM PST 24 |
| Finished | Feb 07 03:41:20 PM PST 24 |
| Peak memory | 206856 kb |
| Host | smart-6614b9f1-7e5a-48ae-b8f3-491784e380fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=270840368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.270840368 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.1242555543 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 138226647 ps |
| CPU time | 60.59 seconds |
| Started | Feb 07 03:40:10 PM PST 24 |
| Finished | Feb 07 03:41:11 PM PST 24 |
| Peak memory | 207024 kb |
| Host | smart-f864a7e0-470b-451d-8664-5eeb6690b148 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1242555543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.1242555543 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2729834353 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 904515037 ps |
| CPU time | 165.87 seconds |
| Started | Feb 07 03:40:15 PM PST 24 |
| Finished | Feb 07 03:43:02 PM PST 24 |
| Peak memory | 211144 kb |
| Host | smart-11797a91-ee88-40de-ba79-f8f0e9b0b6f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2729834353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2729834353 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1088105931 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 157291078 ps |
| CPU time | 6.55 seconds |
| Started | Feb 07 03:40:12 PM PST 24 |
| Finished | Feb 07 03:40:19 PM PST 24 |
| Peak memory | 204812 kb |
| Host | smart-6d901eb3-432d-4784-acf2-ec50f5334e38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1088105931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1088105931 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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