Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 476 1 T1 1 T7 2 T10 9
all_values[1] 469 1 T7 1 T10 6 T11 9
all_values[2] 454 1 T6 2 T7 1 T10 6
all_values[3] 501 1 T6 3 T7 2 T10 12
all_values[4] 491 1 T5 1 T6 3 T10 7
all_values[5] 439 1 T10 9 T11 9 T15 12
all_values[6] 486 1 T1 1 T5 1 T7 1
all_values[7] 459 1 T1 1 T6 1 T7 3
all_values[8] 450 1 T1 1 T5 2 T6 2
all_values[9] 450 1 T5 1 T7 2 T10 7
all_values[10] 468 1 T5 1 T7 2 T10 4
all_values[11] 482 1 T10 7 T11 11 T15 9
all_values[12] 479 1 T6 2 T10 3 T11 6
all_values[13] 486 1 T7 1 T10 5 T11 11
all_values[14] 486 1 T10 4 T11 8 T15 12
all_values[15] 481 1 T1 2 T10 12 T11 5
all_values[16] 496 1 T6 1 T7 2 T10 12
all_values[17] 478 1 T6 1 T7 1 T10 9
all_values[18] 461 1 T6 1 T7 1 T10 8
all_values[19] 469 1 T5 1 T10 12 T11 2
all_values[20] 447 1 T1 1 T5 1 T6 1
all_values[21] 479 1 T1 3 T5 1 T6 1
all_values[22] 484 1 T1 1 T5 1 T6 1
all_values[23] 460 1 T1 1 T6 1 T10 7

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