Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1750	1			T5	2		T7	7		T10	22
all_values[1]	1800	1			T5	3		T7	3		T10	23
all_values[2]	1715	1			T5	1		T7	8		T10	24
all_values[3]	1728	1			T5	2		T7	4		T10	21
all_values[4]	1752	1			T5	3		T7	4		T10	27
all_values[5]	1680	1			T5	2		T7	6		T10	25
all_values[6]	1816	1			T5	2		T7	5		T10	28
all_values[7]	1734	1			T5	3		T7	3		T10	30
all_values[8]	1803	1			T5	4		T7	7		T10	29
all_values[9]	1697	1			T5	1		T7	5		T10	22
all_values[10]	1664	1			T5	1		T7	2		T10	28
all_values[11]	1713	1			T5	3		T7	4		T10	27
all_values[12]	1761	1			T5	1		T7	5		T10	23
all_values[13]	1740	1			T5	5		T7	4		T10	34
all_values[14]	1695	1			T5	6		T7	6		T10	16
all_values[15]	1788	1			T5	3		T7	8		T10	23
all_values[16]	1707	1			T5	1		T7	6		T10	30
all_values[17]	1751	1			T5	5		T7	7		T10	25
all_values[18]	1749	1			T5	3		T7	3		T10	23
all_values[19]	1768	1			T5	2		T7	6		T10	15
all_values[20]	1814	1			T5	3		T7	4		T10	29
all_values[21]	1707	1			T5	3		T7	4		T10	22
all_values[22]	1759	1			T5	1		T7	4		T10	23
all_values[23]	1737	1			T5	2		T7	12		T10	21
all_values[24]	1786	1			T5	2		T7	6		T10	32
all_values[25]	1736	1			T5	1		T7	7		T10	24
all_values[26]	1812	1			T5	4		T7	8		T10	18
all_values[27]	1790	1			T7	3		T10	26		T11	15
all_values[28]	1694	1			T5	3		T7	4		T10	21
all_values[29]	1750	1			T7	4		T10	25		T11	11
all_values[30]	1724	1			T5	2		T7	3		T10	20
all_values[31]	1798	1			T5	5		T7	5		T10	31
all_values[32]	1780	1			T5	5		T7	2		T10	28
all_values[33]	1811	1			T5	3		T7	6		T10	19
all_values[34]	1744	1			T5	1		T7	4		T10	23
all_values[35]	1731	1			T7	2		T10	30		T11	4
all_values[36]	1719	1			T5	1		T7	6		T10	24
all_values[37]	1741	1			T5	1		T7	10		T10	33
all_values[38]	1701	1			T5	3		T7	3		T10	28
all_values[39]	1738	1			T5	3		T7	8		T10	28
all_values[40]	1763	1			T7	4		T10	26		T11	8
all_values[41]	1742	1			T5	4		T7	10		T10	31
all_values[42]	1709	1			T5	1		T7	7		T10	24
all_values[43]	1817	1			T5	2		T7	6		T10	28
all_values[44]	1754	1			T5	4		T7	3		T10	27
all_values[45]	1717	1			T7	4		T10	26		T11	14
all_values[46]	1814	1			T5	1		T7	1		T10	38
all_values[47]	1713	1			T5	3		T7	9		T10	23
all_values[48]	1786	1			T7	7		T10	27		T11	14
all_values[49]	1724	1			T5	2		T7	3		T10	23
all_values[50]	1766	1			T5	2		T7	4		T10	21
all_values[51]	1726	1			T7	5		T10	22		T11	16
all_values[52]	1778	1			T7	1		T10	33		T11	11
all_values[53]	1764	1			T5	1		T7	4		T10	20
all_values[54]	1660	1			T5	4		T7	4		T10	29
all_values[55]	1703	1			T5	5		T7	3		T10	32
all_values[56]	1780	1			T7	5		T10	31		T11	10
all_values[57]	1724	1			T5	4		T7	3		T10	25
all_values[58]	1682	1			T5	4		T7	5		T10	25
all_values[59]	1772	1			T5	3		T7	6		T10	26
all_values[60]	1718	1			T5	3		T7	4		T10	26
all_values[61]	1766	1			T7	4		T10	27		T11	20
all_values[62]	1737	1			T7	6		T10	33		T11	8
all_values[63]	1747	1			T5	1		T7	8		T10	19