Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1812	1			T4	2		T7	17		T8	1
all_values[1]	1809	1			T4	2		T7	29		T15	32
all_values[2]	1796	1			T4	2		T7	30		T8	1
all_values[3]	1803	1			T4	3		T7	29		T8	1
all_values[4]	1790	1			T4	6		T7	37		T8	2
all_values[5]	1857	1			T4	3		T7	25		T8	2
all_values[6]	1817	1			T4	1		T7	22		T10	2
all_values[7]	1797	1			T4	1		T7	22		T8	1
all_values[8]	1811	1			T4	1		T7	29		T10	5
all_values[9]	1724	1			T4	5		T7	34		T10	1
all_values[10]	1802	1			T4	1		T7	34		T8	1
all_values[11]	1747	1			T4	3		T7	27		T10	3
all_values[12]	1733	1			T4	3		T7	24		T8	1
all_values[13]	1903	1			T4	3		T7	22		T8	1
all_values[14]	1835	1			T7	30		T10	2		T15	23
all_values[15]	1847	1			T4	2		T7	16		T8	1
all_values[16]	1760	1			T4	2		T7	23		T8	2
all_values[17]	1801	1			T4	2		T7	23		T10	3
all_values[18]	1784	1			T7	18		T10	3		T15	26
all_values[19]	1792	1			T4	2		T7	19		T15	28
all_values[20]	1700	1			T4	2		T7	21		T10	1
all_values[21]	1792	1			T4	5		T7	15		T8	2
all_values[22]	1738	1			T4	3		T7	23		T8	1
all_values[23]	1793	1			T4	1		T7	19		T10	2
all_values[24]	1850	1			T7	23		T10	3		T15	26
all_values[25]	1787	1			T4	4		T7	22		T10	3
all_values[26]	1765	1			T4	2		T7	28		T10	1
all_values[27]	1743	1			T4	3		T7	27		T10	3
all_values[28]	1795	1			T4	3		T7	34		T8	2
all_values[29]	1776	1			T4	3		T7	22		T8	1
all_values[30]	1769	1			T4	5		T7	17		T10	3
all_values[31]	1748	1			T4	1		T7	18		T10	3
all_values[32]	1822	1			T4	2		T7	22		T10	6
all_values[33]	1738	1			T4	1		T7	26		T10	4
all_values[34]	1829	1			T4	3		T7	31		T8	1
all_values[35]	1763	1			T7	28		T10	2		T15	25
all_values[36]	1885	1			T4	3		T7	30		T8	1
all_values[37]	1762	1			T4	2		T7	26		T8	3
all_values[38]	1858	1			T4	3		T7	34		T8	1
all_values[39]	1828	1			T4	1		T7	32		T10	2
all_values[40]	1792	1			T4	2		T7	22		T8	1
all_values[41]	1744	1			T4	5		T7	16		T8	1
all_values[42]	1866	1			T4	2		T7	23		T8	2
all_values[43]	1782	1			T4	4		T7	23		T8	3
all_values[44]	1776	1			T4	1		T7	19		T10	3
all_values[45]	1845	1			T4	4		T7	26		T8	1
all_values[46]	1789	1			T4	3		T7	26		T8	1
all_values[47]	1820	1			T7	26		T8	1		T10	9
all_values[48]	1786	1			T4	2		T7	20		T8	1
all_values[49]	1813	1			T7	27		T8	2		T15	24
all_values[50]	1841	1			T4	4		T7	21		T8	1
all_values[51]	1764	1			T4	3		T7	22		T8	1
all_values[52]	1759	1			T7	30		T10	1		T15	26
all_values[53]	1750	1			T4	5		T7	30		T8	1
all_values[54]	1752	1			T7	29		T8	1		T10	3
all_values[55]	1800	1			T4	5		T7	17		T8	1
all_values[56]	1787	1			T4	1		T7	20		T10	3
all_values[57]	1798	1			T4	3		T7	24		T8	1
all_values[58]	1755	1			T4	4		T7	19		T10	3
all_values[59]	1758	1			T4	2		T7	15		T8	1
all_values[60]	1821	1			T4	2		T7	29		T8	1
all_values[61]	1774	1			T4	1		T7	20		T10	1
all_values[62]	1848	1			T4	1		T7	17		T8	1
all_values[63]	1801	1			T4	2		T7	22		T8	3