| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.20 | 99.26 | 90.07 | 98.80 | 95.82 | 99.26 | 100.00 |
| T760 | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4224762144 | Feb 21 02:37:19 PM PST 24 | Feb 21 02:38:32 PM PST 24 | 174833604 ps | ||
| T761 | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3325912173 | Feb 21 02:37:41 PM PST 24 | Feb 21 02:37:43 PM PST 24 | 27766383 ps | ||
| T762 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2440013206 | Feb 21 02:35:52 PM PST 24 | Feb 21 02:39:14 PM PST 24 | 15887506641 ps | ||
| T31 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.3389102060 | Feb 21 02:39:12 PM PST 24 | Feb 21 02:42:35 PM PST 24 | 8834811698 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1657664757 | Feb 21 02:39:20 PM PST 24 | Feb 21 02:41:12 PM PST 24 | 59432373824 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.4005847859 | Feb 21 02:37:25 PM PST 24 | Feb 21 02:37:32 PM PST 24 | 38677788 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/14.xbar_random.792891827 | Feb 21 02:36:15 PM PST 24 | Feb 21 02:36:50 PM PST 24 | 2309160618 ps | ||
| T28 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2651359451 | Feb 21 02:39:33 PM PST 24 | Feb 21 02:43:21 PM PST 24 | 552003307 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.811563809 | Feb 21 02:37:22 PM PST 24 | Feb 21 02:37:55 PM PST 24 | 4842734289 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.861829401 | Feb 21 02:37:25 PM PST 24 | Feb 21 02:38:38 PM PST 24 | 13473044390 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3173494801 | Feb 21 02:35:36 PM PST 24 | Feb 21 02:35:38 PM PST 24 | 41177577 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.293654716 | Feb 21 02:39:13 PM PST 24 | Feb 21 02:39:43 PM PST 24 | 6259491189 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2977400501 | Feb 21 02:37:58 PM PST 24 | Feb 21 02:38:29 PM PST 24 | 6159171260 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3483687821 | Feb 21 02:38:43 PM PST 24 | Feb 21 02:44:19 PM PST 24 | 42591289484 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.571000420 | Feb 21 02:36:03 PM PST 24 | Feb 21 02:36:39 PM PST 24 | 15720780119 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.259662139 | Feb 21 02:36:09 PM PST 24 | Feb 21 02:36:54 PM PST 24 | 25024101230 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/35.xbar_smoke.1991911810 | Feb 21 02:38:15 PM PST 24 | Feb 21 02:38:18 PM PST 24 | 76465985 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3940962024 | Feb 21 02:36:03 PM PST 24 | Feb 21 02:36:27 PM PST 24 | 557167336 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2699749957 | Feb 21 02:37:10 PM PST 24 | Feb 21 02:38:11 PM PST 24 | 5927245745 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3839838593 | Feb 21 02:39:26 PM PST 24 | Feb 21 02:40:06 PM PST 24 | 957659148 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1544741218 | Feb 21 02:37:20 PM PST 24 | Feb 21 02:37:51 PM PST 24 | 9571200347 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/10.xbar_smoke.2387543094 | Feb 21 02:35:59 PM PST 24 | Feb 21 02:36:05 PM PST 24 | 30743758 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/41.xbar_smoke.2167216181 | Feb 21 02:38:42 PM PST 24 | Feb 21 02:38:45 PM PST 24 | 38626392 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1927862681 | Feb 21 02:37:17 PM PST 24 | Feb 21 02:47:28 PM PST 24 | 18896267809 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/35.xbar_same_source.764218917 | Feb 21 02:38:09 PM PST 24 | Feb 21 02:38:15 PM PST 24 | 206451835 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.484574645 | Feb 21 02:38:16 PM PST 24 | Feb 21 02:38:45 PM PST 24 | 9635468449 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/16.xbar_smoke.2566369246 | Feb 21 02:36:14 PM PST 24 | Feb 21 02:36:17 PM PST 24 | 52724433 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3281984301 | Feb 21 02:37:20 PM PST 24 | Feb 21 02:37:39 PM PST 24 | 239520515 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/17.xbar_smoke.851314902 | Feb 21 02:36:30 PM PST 24 | Feb 21 02:36:34 PM PST 24 | 371529511 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.4137472250 | Feb 21 02:36:03 PM PST 24 | Feb 21 02:36:29 PM PST 24 | 234504574 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1152162464 | Feb 21 02:36:56 PM PST 24 | Feb 21 02:41:33 PM PST 24 | 603606845 ps | ||
| T127 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2854518561 | Feb 21 02:36:00 PM PST 24 | Feb 21 02:42:52 PM PST 24 | 8180103768 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2505093221 | Feb 21 02:36:03 PM PST 24 | Feb 21 02:39:06 PM PST 24 | 4189932504 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3198902611 | Feb 21 02:35:39 PM PST 24 | Feb 21 02:35:57 PM PST 24 | 380302421 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/46.xbar_error_random.1894174263 | Feb 21 02:39:18 PM PST 24 | Feb 21 02:39:24 PM PST 24 | 69342105 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3026233432 | Feb 21 02:38:17 PM PST 24 | Feb 21 02:38:31 PM PST 24 | 1189366258 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.363356447 | Feb 21 02:37:55 PM PST 24 | Feb 21 02:37:58 PM PST 24 | 51067589 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.2066224897 | Feb 21 02:37:28 PM PST 24 | Feb 21 02:37:40 PM PST 24 | 319412144 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3642598714 | Feb 21 02:39:18 PM PST 24 | Feb 21 02:42:04 PM PST 24 | 35935193101 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1442521347 | Feb 21 02:37:20 PM PST 24 | Feb 21 02:37:24 PM PST 24 | 55202507 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/2.xbar_smoke.3082484470 | Feb 21 02:35:47 PM PST 24 | Feb 21 02:35:53 PM PST 24 | 204724412 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.459238582 | Feb 21 02:36:36 PM PST 24 | Feb 21 02:37:41 PM PST 24 | 2296816819 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/11.xbar_random.1077410290 | Feb 21 02:36:01 PM PST 24 | Feb 21 02:36:29 PM PST 24 | 634554368 ps | ||
| T111 | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.469783598 | Feb 21 02:36:39 PM PST 24 | Feb 21 02:41:20 PM PST 24 | 53623205642 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1850323179 | Feb 21 02:36:12 PM PST 24 | Feb 21 02:39:29 PM PST 24 | 2496415257 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2010538467 | Feb 21 02:35:44 PM PST 24 | Feb 21 02:36:05 PM PST 24 | 1257343071 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1265652890 | Feb 21 02:37:36 PM PST 24 | Feb 21 02:38:26 PM PST 24 | 9852514540 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3175796676 | Feb 21 02:37:42 PM PST 24 | Feb 21 02:39:09 PM PST 24 | 774404064 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3235549285 | Feb 21 02:39:12 PM PST 24 | Feb 21 02:41:25 PM PST 24 | 17723684894 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/29.xbar_smoke.2049529076 | Feb 21 02:37:27 PM PST 24 | Feb 21 02:37:31 PM PST 24 | 288901589 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.745295119 | Feb 21 02:35:55 PM PST 24 | Feb 21 02:36:31 PM PST 24 | 10477774693 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2532712943 | Feb 21 02:36:15 PM PST 24 | Feb 21 02:36:33 PM PST 24 | 402982823 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2564610015 | Feb 21 02:38:07 PM PST 24 | Feb 21 02:38:34 PM PST 24 | 1818120994 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3982545062 | Feb 21 02:36:01 PM PST 24 | Feb 21 02:36:18 PM PST 24 | 271050173 ps | ||
| T128 | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2891819910 | Feb 21 02:35:56 PM PST 24 | Feb 21 02:39:53 PM PST 24 | 37569787571 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2453005792 | Feb 21 02:36:03 PM PST 24 | Feb 21 02:36:10 PM PST 24 | 294447332 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2620117635 | Feb 21 02:39:12 PM PST 24 | Feb 21 02:39:20 PM PST 24 | 191566422 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2037754348 | Feb 21 02:38:26 PM PST 24 | Feb 21 02:41:52 PM PST 24 | 23833310254 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2922591979 | Feb 21 02:36:20 PM PST 24 | Feb 21 02:37:15 PM PST 24 | 11433584723 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1271354926 | Feb 21 02:38:13 PM PST 24 | Feb 21 02:38:15 PM PST 24 | 41788859 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3935120685 | Feb 21 02:37:54 PM PST 24 | Feb 21 02:38:37 PM PST 24 | 10335597877 ps | ||
| T154 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1068533361 | Feb 21 02:38:00 PM PST 24 | Feb 21 02:40:08 PM PST 24 | 414658342 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1296911100 | Feb 21 02:39:10 PM PST 24 | Feb 21 02:40:25 PM PST 24 | 2574636718 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.496861730 | Feb 21 02:36:00 PM PST 24 | Feb 21 02:38:51 PM PST 24 | 10910818650 ps | ||
| T20 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1400099698 | Feb 21 02:39:23 PM PST 24 | Feb 21 02:44:16 PM PST 24 | 6887821244 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/6.xbar_random.3574057787 | Feb 21 02:35:54 PM PST 24 | Feb 21 02:36:16 PM PST 24 | 625933497 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.627893175 | Feb 21 02:36:29 PM PST 24 | Feb 21 02:36:35 PM PST 24 | 169548213 ps | ||
| T129 | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.211554979 | Feb 21 02:36:32 PM PST 24 | Feb 21 02:37:03 PM PST 24 | 1134512529 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1836948374 | Feb 21 02:35:57 PM PST 24 | Feb 21 02:36:19 PM PST 24 | 236303002 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.903806275 | Feb 21 02:37:23 PM PST 24 | Feb 21 02:38:18 PM PST 24 | 646502089 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/13.xbar_random.113669177 | Feb 21 02:36:10 PM PST 24 | Feb 21 02:36:29 PM PST 24 | 938535216 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.946830860 | Feb 21 02:36:44 PM PST 24 | Feb 21 02:37:01 PM PST 24 | 380699321 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.62904147 | Feb 21 02:36:45 PM PST 24 | Feb 21 02:37:32 PM PST 24 | 9265414372 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3419930502 | Feb 21 02:35:52 PM PST 24 | Feb 21 02:38:11 PM PST 24 | 14069348402 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/26.xbar_error_random.502981215 | Feb 21 02:37:21 PM PST 24 | Feb 21 02:37:27 PM PST 24 | 138824970 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3086786836 | Feb 21 02:39:16 PM PST 24 | Feb 21 02:43:18 PM PST 24 | 532836087 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3379137543 | Feb 21 02:37:57 PM PST 24 | Feb 21 02:43:51 PM PST 24 | 2704761814 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.221287340 | Feb 21 02:37:13 PM PST 24 | Feb 21 02:38:11 PM PST 24 | 29519281924 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1043335991 | Feb 21 02:36:05 PM PST 24 | Feb 21 02:36:27 PM PST 24 | 716063490 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2280130198 | Feb 21 02:37:28 PM PST 24 | Feb 21 02:38:03 PM PST 24 | 9875532282 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2846753792 | Feb 21 02:35:58 PM PST 24 | Feb 21 02:38:45 PM PST 24 | 21079150315 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3539867520 | Feb 21 02:36:27 PM PST 24 | Feb 21 02:36:51 PM PST 24 | 1343068288 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.364167935 | Feb 21 02:38:30 PM PST 24 | Feb 21 02:38:56 PM PST 24 | 1080900280 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2354490549 | Feb 21 02:35:45 PM PST 24 | Feb 21 02:36:53 PM PST 24 | 3999644715 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2908401148 | Feb 21 02:39:13 PM PST 24 | Feb 21 02:39:54 PM PST 24 | 15187816804 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/34.xbar_random.3001756461 | Feb 21 02:38:04 PM PST 24 | Feb 21 02:38:13 PM PST 24 | 173281203 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2027318794 | Feb 21 02:39:12 PM PST 24 | Feb 21 02:40:50 PM PST 24 | 678645727 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1699306879 | Feb 21 02:38:27 PM PST 24 | Feb 21 02:40:06 PM PST 24 | 348927487 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2920667444 | Feb 21 02:39:23 PM PST 24 | Feb 21 02:39:27 PM PST 24 | 35494702 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2160285248 | Feb 21 02:38:16 PM PST 24 | Feb 21 02:48:14 PM PST 24 | 320372919216 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3494392671 | Feb 21 02:38:16 PM PST 24 | Feb 21 02:40:15 PM PST 24 | 1652457449 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1752372009 | Feb 21 02:36:52 PM PST 24 | Feb 21 02:37:20 PM PST 24 | 726512800 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.162167011 | Feb 21 02:35:38 PM PST 24 | Feb 21 02:36:17 PM PST 24 | 16920679517 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3238626142 | Feb 21 02:35:51 PM PST 24 | Feb 21 02:36:15 PM PST 24 | 536962413 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1626451033 | Feb 21 02:36:01 PM PST 24 | Feb 21 02:40:25 PM PST 24 | 138069300948 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2605052904 | Feb 21 02:39:38 PM PST 24 | Feb 21 02:40:28 PM PST 24 | 492908140 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3351993510 | Feb 21 02:39:25 PM PST 24 | Feb 21 02:43:08 PM PST 24 | 494739630 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3221354251 | Feb 21 02:39:26 PM PST 24 | Feb 21 02:39:44 PM PST 24 | 81158881 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3924591517 | Feb 21 02:35:57 PM PST 24 | Feb 21 02:36:22 PM PST 24 | 712262521 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/24.xbar_smoke.571384095 | Feb 21 02:37:12 PM PST 24 | Feb 21 02:37:16 PM PST 24 | 130577326 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2308871448 | Feb 21 02:38:25 PM PST 24 | Feb 21 02:42:28 PM PST 24 | 104129230676 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.609912637 | Feb 21 02:37:57 PM PST 24 | Feb 21 02:41:47 PM PST 24 | 43261226979 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/42.xbar_random.2929719259 | Feb 21 02:39:20 PM PST 24 | Feb 21 02:39:55 PM PST 24 | 1132648286 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.702187557 | Feb 21 02:35:58 PM PST 24 | Feb 21 02:36:39 PM PST 24 | 643278989 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.4185371334 | Feb 21 02:37:28 PM PST 24 | Feb 21 02:41:05 PM PST 24 | 3110663065 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3092124936 | Feb 21 02:36:10 PM PST 24 | Feb 21 02:36:41 PM PST 24 | 3577190190 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2609530588 | Feb 21 02:36:19 PM PST 24 | Feb 21 02:36:29 PM PST 24 | 142925732 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1449539534 | Feb 21 02:39:38 PM PST 24 | Feb 21 02:40:04 PM PST 24 | 310879021 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1497046938 | Feb 21 02:35:56 PM PST 24 | Feb 21 02:40:31 PM PST 24 | 16961883871 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/42.xbar_error_random.458563225 | Feb 21 02:39:00 PM PST 24 | Feb 21 02:39:27 PM PST 24 | 711975398 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3742584646 | Feb 21 02:39:01 PM PST 24 | Feb 21 02:39:04 PM PST 24 | 35766137 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2960074830 | Feb 21 02:38:14 PM PST 24 | Feb 21 02:42:43 PM PST 24 | 52305912204 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.427591491 | Feb 21 02:39:23 PM PST 24 | Feb 21 02:40:03 PM PST 24 | 24254223343 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/20.xbar_smoke.370851988 | Feb 21 02:36:54 PM PST 24 | Feb 21 02:37:00 PM PST 24 | 54310884 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1114171239 | Feb 21 02:37:45 PM PST 24 | Feb 21 02:40:30 PM PST 24 | 6370273140 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2388006847 | Feb 21 02:36:44 PM PST 24 | Feb 21 02:36:54 PM PST 24 | 116257013 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1207220615 | Feb 21 02:37:25 PM PST 24 | Feb 21 02:37:45 PM PST 24 | 333133403 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.4043313902 | Feb 21 02:37:57 PM PST 24 | Feb 21 02:38:22 PM PST 24 | 795928532 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/38.xbar_random.171552941 | Feb 21 02:38:26 PM PST 24 | Feb 21 02:38:42 PM PST 24 | 536017766 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/47.xbar_same_source.3467228943 | Feb 21 02:39:15 PM PST 24 | Feb 21 02:39:29 PM PST 24 | 721475027 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3120115841 | Feb 21 02:35:57 PM PST 24 | Feb 21 02:36:02 PM PST 24 | 93467366 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.802102880 | Feb 21 02:36:53 PM PST 24 | Feb 21 02:48:18 PM PST 24 | 82513402843 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.4215632066 | Feb 21 02:36:11 PM PST 24 | Feb 21 02:36:33 PM PST 24 | 362216068 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.607041924 | Feb 21 02:36:54 PM PST 24 | Feb 21 02:39:07 PM PST 24 | 1584804859 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.3491895269 | Feb 21 02:37:34 PM PST 24 | Feb 21 02:38:47 PM PST 24 | 2966966688 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1945978805 | Feb 21 02:36:55 PM PST 24 | Feb 21 02:37:09 PM PST 24 | 68352189 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1399136595 | Feb 21 02:37:22 PM PST 24 | Feb 21 02:37:35 PM PST 24 | 278392854 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2315476820 | Feb 21 02:38:43 PM PST 24 | Feb 21 02:42:00 PM PST 24 | 9556067205 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.2360858980 | Feb 21 02:36:34 PM PST 24 | Feb 21 02:38:10 PM PST 24 | 20719973332 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2523775221 | Feb 21 02:37:22 PM PST 24 | Feb 21 02:37:26 PM PST 24 | 30639120 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3628648824 | Feb 21 02:37:27 PM PST 24 | Feb 21 02:39:41 PM PST 24 | 26190349121 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3322910730 | Feb 21 02:39:19 PM PST 24 | Feb 21 02:40:42 PM PST 24 | 1964284439 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/25.xbar_same_source.2367239862 | Feb 21 02:37:16 PM PST 24 | Feb 21 02:37:21 PM PST 24 | 62106564 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.866669008 | Feb 21 02:36:00 PM PST 24 | Feb 21 02:36:56 PM PST 24 | 402304562 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1132114657 | Feb 21 02:38:02 PM PST 24 | Feb 21 02:38:06 PM PST 24 | 137650873 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2190418707 | Feb 21 02:36:56 PM PST 24 | Feb 21 02:37:44 PM PST 24 | 751427928 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/14.xbar_error_random.3289512617 | Feb 21 02:36:16 PM PST 24 | Feb 21 02:36:45 PM PST 24 | 197506449 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2645514688 | Feb 21 02:39:27 PM PST 24 | Feb 21 02:39:35 PM PST 24 | 79861036 ps | ||
| T29 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3625735031 | Feb 21 02:36:10 PM PST 24 | Feb 21 02:39:37 PM PST 24 | 2230671563 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/15.xbar_smoke.417854263 | Feb 21 02:36:31 PM PST 24 | Feb 21 02:36:35 PM PST 24 | 266576158 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.891068865 | Feb 21 02:38:29 PM PST 24 | Feb 21 02:48:31 PM PST 24 | 141762832665 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3876711093 | Feb 21 02:36:03 PM PST 24 | Feb 21 02:36:31 PM PST 24 | 218726373 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/23.xbar_error_random.394619388 | Feb 21 02:37:10 PM PST 24 | Feb 21 02:37:36 PM PST 24 | 775665234 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/22.xbar_random.3728023871 | Feb 21 02:37:20 PM PST 24 | Feb 21 02:37:57 PM PST 24 | 1068541070 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.781878757 | Feb 21 02:36:10 PM PST 24 | Feb 21 02:36:37 PM PST 24 | 5267341025 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3174430278 | Feb 21 02:36:04 PM PST 24 | Feb 21 02:36:40 PM PST 24 | 20963012112 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1291547322 | Feb 21 02:39:05 PM PST 24 | Feb 21 02:39:24 PM PST 24 | 443050348 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3362676241 | Feb 21 02:37:48 PM PST 24 | Feb 21 02:40:35 PM PST 24 | 788557938 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3115232553 | Feb 21 02:36:44 PM PST 24 | Feb 21 02:36:56 PM PST 24 | 71578502 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1447834887 | Feb 21 02:39:01 PM PST 24 | Feb 21 02:40:38 PM PST 24 | 6506569065 ps |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3003852276 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8854809489 ps |
| CPU time | 355.06 seconds |
| Started | Feb 21 02:36:17 PM PST 24 |
| Finished | Feb 21 02:42:15 PM PST 24 |
| Peak memory | 213280 kb |
| Host | smart-3a026c4f-dc09-41ad-a499-e88b226acaaf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3003852276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.3003852276 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.4099803494 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 183211680145 ps |
| CPU time | 670.02 seconds |
| Started | Feb 21 02:37:11 PM PST 24 |
| Finished | Feb 21 02:48:22 PM PST 24 |
| Peak memory | 206900 kb |
| Host | smart-a3ead167-42f2-45ed-b842-d3d5efad303f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4099803494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.4099803494 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2034340882 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 94104473769 ps |
| CPU time | 637.19 seconds |
| Started | Feb 21 02:39:25 PM PST 24 |
| Finished | Feb 21 02:50:03 PM PST 24 |
| Peak memory | 211216 kb |
| Host | smart-5acb400f-5dbd-4835-aba1-f924b6085ca2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2034340882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.2034340882 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2988976318 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 104946457797 ps |
| CPU time | 552.59 seconds |
| Started | Feb 21 02:35:56 PM PST 24 |
| Finished | Feb 21 02:45:11 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-000a8f5a-c39e-443d-a903-8bb09110a3a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2988976318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.2988976318 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.889499551 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 424124387 ps |
| CPU time | 57.13 seconds |
| Started | Feb 21 02:35:40 PM PST 24 |
| Finished | Feb 21 02:36:37 PM PST 24 |
| Peak memory | 206196 kb |
| Host | smart-0df5d619-4e58-4647-be3e-550443321058 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=889499551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.889499551 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.2949147482 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 17643190613 ps |
| CPU time | 173.5 seconds |
| Started | Feb 21 02:36:17 PM PST 24 |
| Finished | Feb 21 02:39:14 PM PST 24 |
| Peak memory | 211296 kb |
| Host | smart-459cedbf-d085-4131-b7e3-a1125918d29f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2949147482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2949147482 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.3837445903 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 23881918366 ps |
| CPU time | 229.41 seconds |
| Started | Feb 21 02:39:28 PM PST 24 |
| Finished | Feb 21 02:43:18 PM PST 24 |
| Peak memory | 209228 kb |
| Host | smart-07fcf98f-f916-45c6-9cee-91b7e00728fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3837445903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3837445903 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1193590793 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 16605601522 ps |
| CPU time | 108.99 seconds |
| Started | Feb 21 02:38:25 PM PST 24 |
| Finished | Feb 21 02:40:14 PM PST 24 |
| Peak memory | 211296 kb |
| Host | smart-a9273afc-8081-4586-9470-3c2ad2eb9c54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193590793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1193590793 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1140235057 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 14585090963 ps |
| CPU time | 305.95 seconds |
| Started | Feb 21 02:36:45 PM PST 24 |
| Finished | Feb 21 02:41:52 PM PST 24 |
| Peak memory | 210600 kb |
| Host | smart-d961861f-8e97-4294-8b35-5eae718135c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1140235057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.1140235057 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2646832626 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 14135481377 ps |
| CPU time | 543.41 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:46:29 PM PST 24 |
| Peak memory | 220948 kb |
| Host | smart-27bc597a-5d8d-4ac2-a474-c9e6410f9a88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2646832626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.2646832626 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1841398590 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1315189269 ps |
| CPU time | 281.38 seconds |
| Started | Feb 21 02:39:05 PM PST 24 |
| Finished | Feb 21 02:43:49 PM PST 24 |
| Peak memory | 219344 kb |
| Host | smart-e45e95ee-53d2-432c-af84-76d0cc2add5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1841398590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re set_error.1841398590 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.3059960978 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 11705283890 ps |
| CPU time | 268.76 seconds |
| Started | Feb 21 02:38:09 PM PST 24 |
| Finished | Feb 21 02:42:39 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-78c75e42-ba36-441b-b54a-70b09f9b605f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3059960978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3059960978 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.1400099698 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6887821244 ps |
| CPU time | 290.89 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:44:16 PM PST 24 |
| Peak memory | 219524 kb |
| Host | smart-0bd50fec-2583-4f2b-a51b-5cb53226f61c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1400099698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.1400099698 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.1548648281 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 11657894337 ps |
| CPU time | 292.72 seconds |
| Started | Feb 21 02:35:51 PM PST 24 |
| Finished | Feb 21 02:40:44 PM PST 24 |
| Peak memory | 210512 kb |
| Host | smart-c0fc059c-5adb-4c2c-b079-79cf7b9b1b33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1548648281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.1548648281 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3397549267 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 119045045870 ps |
| CPU time | 678.93 seconds |
| Started | Feb 21 02:36:52 PM PST 24 |
| Finished | Feb 21 02:48:12 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-317f9066-623b-41d2-bd7d-7df336541c8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3397549267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.3397549267 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3625735031 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2230671563 ps |
| CPU time | 207.14 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:39:37 PM PST 24 |
| Peak memory | 211276 kb |
| Host | smart-91cf379e-f0a8-4ae3-8402-4ceeebbba827 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3625735031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.3625735031 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.29898785 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1256265296 ps |
| CPU time | 190.96 seconds |
| Started | Feb 21 02:37:06 PM PST 24 |
| Finished | Feb 21 02:40:22 PM PST 24 |
| Peak memory | 211184 kb |
| Host | smart-eba8632a-aac6-4458-9ea1-21bfada694b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=29898785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rese t_error.29898785 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3949872268 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 78205213 ps |
| CPU time | 3.73 seconds |
| Started | Feb 21 02:35:40 PM PST 24 |
| Finished | Feb 21 02:35:45 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-b5d90752-b264-401d-9af1-0ec87bcce0e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3949872268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3949872268 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.4207383456 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 45650369795 ps |
| CPU time | 231.72 seconds |
| Started | Feb 21 02:35:39 PM PST 24 |
| Finished | Feb 21 02:39:32 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-b7416bd6-afa4-4594-bdb4-115f78b04e5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4207383456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.4207383456 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.10517833 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 920941320 ps |
| CPU time | 11.85 seconds |
| Started | Feb 21 02:35:48 PM PST 24 |
| Finished | Feb 21 02:36:02 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-8c6bde26-7499-4664-bf57-0037f1459179 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=10517833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.10517833 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.1367989189 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2185163958 ps |
| CPU time | 31.43 seconds |
| Started | Feb 21 02:35:40 PM PST 24 |
| Finished | Feb 21 02:36:12 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-abd7f46e-3e64-4ee7-b415-a8cbece0b469 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1367989189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1367989189 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.1305508757 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 205648441 ps |
| CPU time | 25.35 seconds |
| Started | Feb 21 02:35:38 PM PST 24 |
| Finished | Feb 21 02:36:03 PM PST 24 |
| Peak memory | 204356 kb |
| Host | smart-d85e961f-178e-47ff-b1cb-2cc6104e153f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1305508757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1305508757 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.4293839446 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 20912341352 ps |
| CPU time | 46.21 seconds |
| Started | Feb 21 02:35:40 PM PST 24 |
| Finished | Feb 21 02:36:26 PM PST 24 |
| Peak memory | 204272 kb |
| Host | smart-bca7ae3e-15ab-414f-aeac-9f1e70c98dce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293839446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.4293839446 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.4050710092 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 11830449426 ps |
| CPU time | 95.18 seconds |
| Started | Feb 21 02:35:36 PM PST 24 |
| Finished | Feb 21 02:37:12 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-170f6e48-50c3-44fc-a981-c1f0a85aefc5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4050710092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.4050710092 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.1836948374 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 236303002 ps |
| CPU time | 19.42 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:19 PM PST 24 |
| Peak memory | 204548 kb |
| Host | smart-67279e17-e4a8-4ae1-bb2e-58790abe05c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836948374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1836948374 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2010538467 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1257343071 ps |
| CPU time | 19.89 seconds |
| Started | Feb 21 02:35:44 PM PST 24 |
| Finished | Feb 21 02:36:05 PM PST 24 |
| Peak memory | 203500 kb |
| Host | smart-d3c691f4-c93f-431b-accb-4bff038b9d1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2010538467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2010538467 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.4279302792 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 569321428 ps |
| CPU time | 3.34 seconds |
| Started | Feb 21 02:35:39 PM PST 24 |
| Finished | Feb 21 02:35:42 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-d63b68bf-eb96-4392-b527-6ceed24c371e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4279302792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4279302792 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1569825805 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 4978127360 ps |
| CPU time | 30.77 seconds |
| Started | Feb 21 02:35:25 PM PST 24 |
| Finished | Feb 21 02:35:57 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-70428e85-dc23-47dc-b6d4-48384f64e23d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569825805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1569825805 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.128940316 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 3917704473 ps |
| CPU time | 31.4 seconds |
| Started | Feb 21 02:35:39 PM PST 24 |
| Finished | Feb 21 02:36:11 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-f725beba-3744-4672-8593-ff24d1acb62f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=128940316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.128940316 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3173494801 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 41177577 ps |
| CPU time | 2.11 seconds |
| Started | Feb 21 02:35:36 PM PST 24 |
| Finished | Feb 21 02:35:38 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-1f26ea2d-e355-46ba-86f1-94e46cbc80ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173494801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3173494801 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.1079293325 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 804451241 ps |
| CPU time | 106.27 seconds |
| Started | Feb 21 02:35:40 PM PST 24 |
| Finished | Feb 21 02:37:26 PM PST 24 |
| Peak memory | 211212 kb |
| Host | smart-c040c1a0-dae7-4c4b-8cf5-165e2648a7f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1079293325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1079293325 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.3198902611 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 380302421 ps |
| CPU time | 16.63 seconds |
| Started | Feb 21 02:35:39 PM PST 24 |
| Finished | Feb 21 02:35:57 PM PST 24 |
| Peak memory | 204176 kb |
| Host | smart-ee567f33-1c04-4aa8-85de-b989a4daea2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3198902611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3198902611 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.230693845 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1306693422 ps |
| CPU time | 205.1 seconds |
| Started | Feb 21 02:35:39 PM PST 24 |
| Finished | Feb 21 02:39:05 PM PST 24 |
| Peak memory | 210164 kb |
| Host | smart-70629b7c-b434-49a4-a6ff-71686fbfbae8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=230693845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_ reset.230693845 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3385237541 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 196587625 ps |
| CPU time | 36.58 seconds |
| Started | Feb 21 02:35:46 PM PST 24 |
| Finished | Feb 21 02:36:23 PM PST 24 |
| Peak memory | 207064 kb |
| Host | smart-4aaddb35-f35a-48bf-b8f3-4fc48e9f3103 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3385237541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.3385237541 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.761447135 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 396962356 ps |
| CPU time | 5.85 seconds |
| Started | Feb 21 02:35:46 PM PST 24 |
| Finished | Feb 21 02:35:53 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-1c4ae7a2-074c-4711-9cef-c8320bca4908 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=761447135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.761447135 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.3443781281 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 861580701 ps |
| CPU time | 44.94 seconds |
| Started | Feb 21 02:35:39 PM PST 24 |
| Finished | Feb 21 02:36:25 PM PST 24 |
| Peak memory | 205344 kb |
| Host | smart-7c01729a-c5d8-41f3-b58c-6d612d0e94a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3443781281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3443781281 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1993903330 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 195869494351 ps |
| CPU time | 634.38 seconds |
| Started | Feb 21 02:35:40 PM PST 24 |
| Finished | Feb 21 02:46:15 PM PST 24 |
| Peak memory | 211288 kb |
| Host | smart-0e418ff6-e66b-4f38-9196-715acf90c2ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1993903330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.1993903330 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.456973293 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 57905411 ps |
| CPU time | 9.88 seconds |
| Started | Feb 21 02:35:38 PM PST 24 |
| Finished | Feb 21 02:35:49 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-bf7cc02c-dbbe-4834-b51d-d59378effbb1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=456973293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.456973293 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.42805433 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 102336208 ps |
| CPU time | 13.43 seconds |
| Started | Feb 21 02:35:54 PM PST 24 |
| Finished | Feb 21 02:36:07 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-d8824766-dc7d-4554-87d1-14a1502a8b6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=42805433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.42805433 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.3034700108 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 515779903 ps |
| CPU time | 13.07 seconds |
| Started | Feb 21 02:35:38 PM PST 24 |
| Finished | Feb 21 02:35:51 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-4b9ae7c3-2140-45b2-ab2b-67f966cb7212 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3034700108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3034700108 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.925280744 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8013267477 ps |
| CPU time | 50.38 seconds |
| Started | Feb 21 02:35:37 PM PST 24 |
| Finished | Feb 21 02:36:28 PM PST 24 |
| Peak memory | 211300 kb |
| Host | smart-2a0f9281-462d-40b2-93f7-67b9d1739159 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=925280744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.925280744 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3419930502 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 14069348402 ps |
| CPU time | 138.05 seconds |
| Started | Feb 21 02:35:52 PM PST 24 |
| Finished | Feb 21 02:38:11 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-cfc7ba12-8481-4425-b3de-5cfc1d9a3308 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3419930502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3419930502 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2968536135 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 138510309 ps |
| CPU time | 27.41 seconds |
| Started | Feb 21 02:35:38 PM PST 24 |
| Finished | Feb 21 02:36:06 PM PST 24 |
| Peak memory | 204640 kb |
| Host | smart-a0fdf362-d44c-4102-b9a4-02f0f6031093 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968536135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2968536135 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2742452013 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1660052728 ps |
| CPU time | 32.47 seconds |
| Started | Feb 21 02:35:43 PM PST 24 |
| Finished | Feb 21 02:36:16 PM PST 24 |
| Peak memory | 203016 kb |
| Host | smart-ce547d10-dbbc-4cc5-9280-f036f178219c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2742452013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2742452013 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.2782416361 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 84370881 ps |
| CPU time | 2.42 seconds |
| Started | Feb 21 02:35:50 PM PST 24 |
| Finished | Feb 21 02:35:53 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-4dae1431-c0a5-49a5-bb1a-8855edbada9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2782416361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2782416361 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2612428120 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 11433474710 ps |
| CPU time | 37.33 seconds |
| Started | Feb 21 02:35:40 PM PST 24 |
| Finished | Feb 21 02:36:17 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-55e5f7cd-1096-45fb-9122-9439f3e545ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612428120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2612428120 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3459959136 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 3928587783 ps |
| CPU time | 33.8 seconds |
| Started | Feb 21 02:35:47 PM PST 24 |
| Finished | Feb 21 02:36:24 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-cb6c5192-ca25-4748-909a-43261a7f0e54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3459959136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3459959136 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2332390359 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 64720365 ps |
| CPU time | 3.02 seconds |
| Started | Feb 21 02:35:45 PM PST 24 |
| Finished | Feb 21 02:35:49 PM PST 24 |
| Peak memory | 203264 kb |
| Host | smart-ca2e1cd3-1ea6-4643-b32c-533ec12c5341 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332390359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2332390359 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2354490549 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3999644715 ps |
| CPU time | 67.07 seconds |
| Started | Feb 21 02:35:45 PM PST 24 |
| Finished | Feb 21 02:36:53 PM PST 24 |
| Peak memory | 205928 kb |
| Host | smart-a413022d-f9c5-42a1-b3a9-2dac5f23f778 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2354490549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2354490549 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.3549601560 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 139998854 ps |
| CPU time | 51.68 seconds |
| Started | Feb 21 02:35:41 PM PST 24 |
| Finished | Feb 21 02:36:33 PM PST 24 |
| Peak memory | 207544 kb |
| Host | smart-6e31861a-852c-4267-bdd5-8c7186167e40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3549601560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand _reset.3549601560 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3180224439 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1293654666 ps |
| CPU time | 30.48 seconds |
| Started | Feb 21 02:35:46 PM PST 24 |
| Finished | Feb 21 02:36:17 PM PST 24 |
| Peak memory | 204352 kb |
| Host | smart-9d71af71-8931-4271-8812-b8bf5792d8de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3180224439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3180224439 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.851396347 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1426565613 ps |
| CPU time | 28.68 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:34 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-a46122fb-08d7-4c11-ba20-6c23393dcf3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=851396347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.851396347 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.989235039 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 35080202361 ps |
| CPU time | 149.5 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:38:35 PM PST 24 |
| Peak memory | 205312 kb |
| Host | smart-f0485274-36e1-4d37-a3d2-1ee396298a13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=989235039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slo w_rsp.989235039 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.4175977524 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 452839523 ps |
| CPU time | 21.78 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:27 PM PST 24 |
| Peak memory | 202740 kb |
| Host | smart-e93538bb-035a-4ad6-8aea-004b25b6f0f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4175977524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.4175977524 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.3930943296 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1996641542 ps |
| CPU time | 30.22 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:34 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-28aa9ac6-bf58-4f43-bb75-3b6e96f347a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3930943296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3930943296 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.794829227 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 728326381 ps |
| CPU time | 27.6 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:31 PM PST 24 |
| Peak memory | 211164 kb |
| Host | smart-e4f2d2b0-f0d8-42ed-b580-7a571017abc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=794829227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.794829227 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.805100552 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 44526562923 ps |
| CPU time | 198.34 seconds |
| Started | Feb 21 02:36:02 PM PST 24 |
| Finished | Feb 21 02:39:24 PM PST 24 |
| Peak memory | 211332 kb |
| Host | smart-49c22fc5-02b8-4b4c-989e-591bba8568a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=805100552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.805100552 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2608787182 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 6995360004 ps |
| CPU time | 41.21 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:46 PM PST 24 |
| Peak memory | 211276 kb |
| Host | smart-e4de9eeb-8793-4cd2-9854-1cf475f39d2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2608787182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2608787182 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.3876711093 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 218726373 ps |
| CPU time | 26.33 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:31 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-6a220aba-4d2b-47ca-95be-5bf1b2146306 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876711093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3876711093 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.3108538375 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 266993337 ps |
| CPU time | 18.43 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:36:22 PM PST 24 |
| Peak memory | 202996 kb |
| Host | smart-fd990626-1344-4716-a506-aeb103da8e44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3108538375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3108538375 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.2387543094 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 30743758 ps |
| CPU time | 2.37 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:36:05 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-afe0c866-a4eb-4952-ba88-c5ac54de7650 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2387543094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2387543094 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3174430278 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 20963012112 ps |
| CPU time | 33.74 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:36:40 PM PST 24 |
| Peak memory | 203180 kb |
| Host | smart-90a8d402-3974-4a1f-9cda-d6b02711d34c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174430278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3174430278 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1934664435 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2978107837 ps |
| CPU time | 27.55 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:34 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-ae356f68-c25b-413e-b694-8880b48632e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1934664435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1934664435 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3719902739 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 26141945 ps |
| CPU time | 2.15 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:01 PM PST 24 |
| Peak memory | 203096 kb |
| Host | smart-326906b4-1752-4741-acd3-b0c6dd8b8d81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719902739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3719902739 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.496861730 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 10910818650 ps |
| CPU time | 167.76 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:38:51 PM PST 24 |
| Peak memory | 206892 kb |
| Host | smart-a418095d-e62e-4015-873a-e516de194f9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=496861730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.496861730 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2454320737 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 9023865000 ps |
| CPU time | 203.7 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:39:27 PM PST 24 |
| Peak memory | 209632 kb |
| Host | smart-ae6be567-5e6b-47e9-b2dd-11861f58a928 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2454320737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2454320737 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2505093221 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4189932504 ps |
| CPU time | 179.86 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:39:06 PM PST 24 |
| Peak memory | 207740 kb |
| Host | smart-9fcfcba9-9769-4c29-ba39-e07475ace84f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2505093221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.2505093221 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2694376046 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 271798207 ps |
| CPU time | 84.17 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:37:30 PM PST 24 |
| Peak memory | 208384 kb |
| Host | smart-24e3aca2-1bf0-49a9-95ec-7de81934f0bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2694376046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.2694376046 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.973740718 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1173344351 ps |
| CPU time | 17.09 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:36:21 PM PST 24 |
| Peak memory | 204352 kb |
| Host | smart-328a125d-1226-4e37-8042-a3ab25bb4240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=973740718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.973740718 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.2288036294 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 175421367 ps |
| CPU time | 16.26 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:36:20 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-d3bcaf7f-8ed6-4adb-ba4d-e0654a965dd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2288036294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2288036294 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2675360629 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 160451741745 ps |
| CPU time | 590.27 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:45:56 PM PST 24 |
| Peak memory | 206532 kb |
| Host | smart-9efbbec2-3c63-43b7-b784-3667cd89ecc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2675360629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.2675360629 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3275429055 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1002135605 ps |
| CPU time | 29.94 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:36:36 PM PST 24 |
| Peak memory | 203164 kb |
| Host | smart-89a3b063-0a53-4da2-b69f-47255be016d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3275429055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3275429055 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.112468545 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 627652748 ps |
| CPU time | 16.48 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:36:23 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-8b52e545-d738-43ea-828a-28b9c528b2a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=112468545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.112468545 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.1077410290 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 634554368 ps |
| CPU time | 24.77 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:36:29 PM PST 24 |
| Peak memory | 211240 kb |
| Host | smart-521cb8c4-48e7-4dcc-a602-9ba9c1187e2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1077410290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.1077410290 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1772778859 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 14255573826 ps |
| CPU time | 39.39 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:43 PM PST 24 |
| Peak memory | 203984 kb |
| Host | smart-e12de600-ced8-44de-8170-cb34a69988dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772778859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1772778859 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.178459270 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 5913103638 ps |
| CPU time | 27.24 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:30 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-e586866d-e256-469b-a0d3-c55654b89e21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=178459270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.178459270 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.4205256414 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 62940159 ps |
| CPU time | 6.77 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:10 PM PST 24 |
| Peak memory | 204120 kb |
| Host | smart-fc6ad68c-d7f5-4770-848f-efe110204e4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205256414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.4205256414 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.486425275 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 319945003 ps |
| CPU time | 5.96 seconds |
| Started | Feb 21 02:36:05 PM PST 24 |
| Finished | Feb 21 02:36:12 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-4329f59b-9770-4acf-b0ce-19a05513565c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=486425275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.486425275 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.2453005792 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 294447332 ps |
| CPU time | 4.14 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:10 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-490e6520-80df-46fa-a57f-acee9f0409c9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2453005792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2453005792 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.571000420 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 15720780119 ps |
| CPU time | 32.38 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:39 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-4afaf852-71be-4c3b-89f7-7c2f828943ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=571000420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.571000420 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1678757143 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 3291119701 ps |
| CPU time | 23.27 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:36:25 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-73cb8722-ee7f-4be9-a6a7-14f82f19d8d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1678757143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1678757143 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.651368797 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 56387991 ps |
| CPU time | 2.77 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:06 PM PST 24 |
| Peak memory | 202976 kb |
| Host | smart-24305370-a1cf-4f50-a9be-c9613c73b3ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651368797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.651368797 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.3069528952 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 874900482 ps |
| CPU time | 60.14 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:37:11 PM PST 24 |
| Peak memory | 206516 kb |
| Host | smart-d4bd7d0a-1cce-4084-a84e-3d4d3e12778e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3069528952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3069528952 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3299081846 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 154535744 ps |
| CPU time | 15.96 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:27 PM PST 24 |
| Peak memory | 203584 kb |
| Host | smart-e4c5461e-6be5-458a-89ca-008c0fd6064f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3299081846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3299081846 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.2408455485 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1651424580 ps |
| CPU time | 346.9 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:41:53 PM PST 24 |
| Peak memory | 209944 kb |
| Host | smart-c10e90f3-adcb-4534-ae0c-18f4b706d201 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2408455485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.2408455485 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.459011773 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 631375753 ps |
| CPU time | 198.42 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:39:29 PM PST 24 |
| Peak memory | 211236 kb |
| Host | smart-a5555b31-5f4a-43dc-9611-0d9ea7a972f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=459011773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_res et_error.459011773 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1043335991 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 716063490 ps |
| CPU time | 21.01 seconds |
| Started | Feb 21 02:36:05 PM PST 24 |
| Finished | Feb 21 02:36:27 PM PST 24 |
| Peak memory | 204468 kb |
| Host | smart-6b1e7710-70fd-4fc7-9113-976e10e34944 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1043335991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1043335991 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.1637853070 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 43930548 ps |
| CPU time | 3.74 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:36:08 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-47d1d950-b24e-4c9f-9363-8b214526f9ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1637853070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1637853070 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1201233706 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 57512481384 ps |
| CPU time | 472.94 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:43:53 PM PST 24 |
| Peak memory | 211352 kb |
| Host | smart-73d9913c-d2b6-44c8-988e-5339c52baed1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1201233706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.1201233706 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2662398305 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 84169492 ps |
| CPU time | 8.77 seconds |
| Started | Feb 21 02:35:53 PM PST 24 |
| Finished | Feb 21 02:36:02 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-35f72afc-944c-404c-b49f-7e1e12de7c50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662398305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2662398305 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.176844459 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1302218139 ps |
| CPU time | 34.14 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:36:40 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-8c8ef10f-5eb3-4a75-a543-f019e745ac91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=176844459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.176844459 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.3361964252 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 904528728 ps |
| CPU time | 27.41 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:37 PM PST 24 |
| Peak memory | 204292 kb |
| Host | smart-c3a93614-049e-43d2-9878-737160cfd826 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3361964252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3361964252 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.87077775 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 22856106799 ps |
| CPU time | 132.73 seconds |
| Started | Feb 21 02:36:11 PM PST 24 |
| Finished | Feb 21 02:38:24 PM PST 24 |
| Peak memory | 211296 kb |
| Host | smart-fc2aeefe-693e-418b-80fe-25f304294fcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=87077775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.87077775 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.1783461404 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1415698074 ps |
| CPU time | 11.85 seconds |
| Started | Feb 21 02:36:36 PM PST 24 |
| Finished | Feb 21 02:36:48 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-52402f41-93c8-448e-a249-35f7beb06421 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1783461404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1783461404 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.3183657303 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 113830262 ps |
| CPU time | 3.66 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:14 PM PST 24 |
| Peak memory | 203364 kb |
| Host | smart-4d5e4c70-7527-4afd-9d24-2ffc3de08ce8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183657303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3183657303 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.3594750243 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 22650191 ps |
| CPU time | 2.13 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:05 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-ee7b20bc-9d67-4f72-8c58-5850982d4428 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3594750243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3594750243 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.2610234801 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 43485380 ps |
| CPU time | 2.42 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:36:06 PM PST 24 |
| Peak memory | 203000 kb |
| Host | smart-0151254f-9410-451c-ad62-e1f392530670 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2610234801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2610234801 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2748372234 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 11147043692 ps |
| CPU time | 28.33 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:38 PM PST 24 |
| Peak memory | 203032 kb |
| Host | smart-2a267aea-3e05-4da7-acc1-b1cfba939eea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748372234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2748372234 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.458999663 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 4524896795 ps |
| CPU time | 31.42 seconds |
| Started | Feb 21 02:36:02 PM PST 24 |
| Finished | Feb 21 02:36:36 PM PST 24 |
| Peak memory | 203104 kb |
| Host | smart-b938d34d-c340-4d25-adee-2fa35b4f658c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=458999663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.458999663 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2135199497 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 33776624 ps |
| CPU time | 2.31 seconds |
| Started | Feb 21 02:36:09 PM PST 24 |
| Finished | Feb 21 02:36:12 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-632c7107-ec6b-4319-9e34-e5ef97a7166b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135199497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2135199497 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.533103905 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1913204462 ps |
| CPU time | 48.6 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:47 PM PST 24 |
| Peak memory | 205368 kb |
| Host | smart-81da3399-161b-4a81-8295-7beabf74aca8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=533103905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.533103905 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1377089018 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 5516908918 ps |
| CPU time | 110.64 seconds |
| Started | Feb 21 02:36:09 PM PST 24 |
| Finished | Feb 21 02:38:00 PM PST 24 |
| Peak memory | 204688 kb |
| Host | smart-a2120afd-b8f5-4a88-83aa-2073d0354e3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1377089018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1377089018 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.688987912 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 558953506 ps |
| CPU time | 174.21 seconds |
| Started | Feb 21 02:36:15 PM PST 24 |
| Finished | Feb 21 02:39:09 PM PST 24 |
| Peak memory | 208300 kb |
| Host | smart-e672f006-7ee8-4b13-a204-e00f953df648 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=688987912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand _reset.688987912 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3982545062 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 271050173 ps |
| CPU time | 13.21 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:36:18 PM PST 24 |
| Peak memory | 211160 kb |
| Host | smart-ca3740d5-9bc8-48a0-ac16-15841b9be2a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3982545062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3982545062 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.334942161 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1726060464 ps |
| CPU time | 65.11 seconds |
| Started | Feb 21 02:36:09 PM PST 24 |
| Finished | Feb 21 02:37:15 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-667fbfc0-2d9d-4890-bb9e-985cb6dab099 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=334942161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.334942161 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.4197508337 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 6991554857 ps |
| CPU time | 59.54 seconds |
| Started | Feb 21 02:36:11 PM PST 24 |
| Finished | Feb 21 02:37:11 PM PST 24 |
| Peak memory | 211292 kb |
| Host | smart-5b159bc1-94ac-4fd0-9879-0bfd69b462ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4197508337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.4197508337 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2532712943 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 402982823 ps |
| CPU time | 17.23 seconds |
| Started | Feb 21 02:36:15 PM PST 24 |
| Finished | Feb 21 02:36:33 PM PST 24 |
| Peak memory | 203172 kb |
| Host | smart-a6e77bb2-046c-4023-9dd8-6f5f27581360 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2532712943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2532712943 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.927827921 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 249604264 ps |
| CPU time | 20.74 seconds |
| Started | Feb 21 02:36:11 PM PST 24 |
| Finished | Feb 21 02:36:32 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-fce8b1d2-2189-474a-86c5-5a5449554be1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=927827921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.927827921 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.113669177 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 938535216 ps |
| CPU time | 19.01 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:29 PM PST 24 |
| Peak memory | 211248 kb |
| Host | smart-747c5cd3-eb35-433f-9f40-71d889bf5085 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=113669177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.113669177 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.2142883979 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 51406365712 ps |
| CPU time | 145.24 seconds |
| Started | Feb 21 02:36:02 PM PST 24 |
| Finished | Feb 21 02:38:31 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-95a0c410-b725-4bda-a51e-3bc1b8cd2ce8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142883979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2142883979 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.773758106 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 830998417 ps |
| CPU time | 22.3 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:33 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-efedc1c5-2634-4c67-9186-87c468ee414b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773758106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.773758106 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.378503127 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 126369764 ps |
| CPU time | 8.63 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:36:14 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-199bbc71-0771-4e56-82f9-d8ad0a3a0e0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=378503127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.378503127 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.4197632536 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 110591481 ps |
| CPU time | 3.58 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:13 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-fd7c1ccb-b581-41c2-9afc-879a4d609a9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4197632536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4197632536 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.447651028 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 19325135782 ps |
| CPU time | 33.66 seconds |
| Started | Feb 21 02:36:12 PM PST 24 |
| Finished | Feb 21 02:36:46 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-d1a856b6-ef9e-4549-9df7-7a77cfe3eda0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=447651028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.447651028 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.781878757 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 5267341025 ps |
| CPU time | 26.73 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:37 PM PST 24 |
| Peak memory | 203092 kb |
| Host | smart-b3f7d503-e9cb-4aff-9510-4f78b448a948 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=781878757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.781878757 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.884793510 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 25235013 ps |
| CPU time | 2.31 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:12 PM PST 24 |
| Peak memory | 203032 kb |
| Host | smart-f91cac36-8109-4608-a06c-f7c6d9f41a65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884793510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.884793510 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.3616511617 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1896466418 ps |
| CPU time | 146.3 seconds |
| Started | Feb 21 02:36:15 PM PST 24 |
| Finished | Feb 21 02:38:42 PM PST 24 |
| Peak memory | 209264 kb |
| Host | smart-b985f0cf-c6be-428d-a690-ea8e31f8af87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3616511617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3616511617 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.681400555 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 11157278169 ps |
| CPU time | 240.43 seconds |
| Started | Feb 21 02:36:11 PM PST 24 |
| Finished | Feb 21 02:40:12 PM PST 24 |
| Peak memory | 209128 kb |
| Host | smart-62dac509-3c16-4273-8d92-b68b9d079af2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=681400555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.681400555 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.12541527 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 7577350 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 02:36:13 PM PST 24 |
| Finished | Feb 21 02:36:14 PM PST 24 |
| Peak memory | 194856 kb |
| Host | smart-1a4810f8-51af-4dd9-891d-68201fcbb21f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=12541527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_ reset.12541527 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1864371931 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 7744844386 ps |
| CPU time | 402 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:42:52 PM PST 24 |
| Peak memory | 219456 kb |
| Host | smart-a2576c1a-5bfc-4421-9d6c-bf8b6a19167e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1864371931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.1864371931 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2889534532 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1023364051 ps |
| CPU time | 8.48 seconds |
| Started | Feb 21 02:36:15 PM PST 24 |
| Finished | Feb 21 02:36:25 PM PST 24 |
| Peak memory | 204400 kb |
| Host | smart-760e3fa9-e047-4f89-88fe-aa2849578fce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2889534532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2889534532 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2186789428 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 262545264 ps |
| CPU time | 32.56 seconds |
| Started | Feb 21 02:36:13 PM PST 24 |
| Finished | Feb 21 02:36:45 PM PST 24 |
| Peak memory | 204844 kb |
| Host | smart-bb5cbc24-87ac-42e3-b64a-650424f70555 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2186789428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2186789428 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1831478155 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 69485623411 ps |
| CPU time | 441.97 seconds |
| Started | Feb 21 02:36:09 PM PST 24 |
| Finished | Feb 21 02:43:31 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-856ae08e-a3b7-4a9d-8562-e3cf04e55a3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1831478155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.1831478155 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.627893175 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 169548213 ps |
| CPU time | 6.57 seconds |
| Started | Feb 21 02:36:29 PM PST 24 |
| Finished | Feb 21 02:36:35 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-faa59c4d-5c04-4be5-8be3-6c090f39bf78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=627893175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.627893175 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.3289512617 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 197506449 ps |
| CPU time | 26.82 seconds |
| Started | Feb 21 02:36:16 PM PST 24 |
| Finished | Feb 21 02:36:45 PM PST 24 |
| Peak memory | 203268 kb |
| Host | smart-1b8d1615-ec5c-45bd-8ff0-954cd8586723 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3289512617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3289512617 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.792891827 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 2309160618 ps |
| CPU time | 34.83 seconds |
| Started | Feb 21 02:36:15 PM PST 24 |
| Finished | Feb 21 02:36:50 PM PST 24 |
| Peak memory | 204200 kb |
| Host | smart-924e310a-cb2b-4a7f-b2ae-f2b468055c55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=792891827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.792891827 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.1387508260 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 102010911981 ps |
| CPU time | 258.55 seconds |
| Started | Feb 21 02:36:15 PM PST 24 |
| Finished | Feb 21 02:40:34 PM PST 24 |
| Peak memory | 211168 kb |
| Host | smart-b79b8977-13cf-47c1-94b9-0f83a6d83aec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387508260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1387508260 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1882614106 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 64040759013 ps |
| CPU time | 300.04 seconds |
| Started | Feb 21 02:36:11 PM PST 24 |
| Finished | Feb 21 02:41:11 PM PST 24 |
| Peak memory | 211300 kb |
| Host | smart-39c1c608-d7cc-4068-a800-82de7f1727a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1882614106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1882614106 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2803361612 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 244098278 ps |
| CPU time | 28.75 seconds |
| Started | Feb 21 02:36:12 PM PST 24 |
| Finished | Feb 21 02:36:41 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-471eea9e-0a9d-4d82-b94b-40931f023b2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803361612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2803361612 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.4015982579 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 5953552882 ps |
| CPU time | 26.93 seconds |
| Started | Feb 21 02:36:19 PM PST 24 |
| Finished | Feb 21 02:36:47 PM PST 24 |
| Peak memory | 204220 kb |
| Host | smart-304b9c13-a560-4040-9cfe-015c70b45b6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4015982579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4015982579 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.1176303808 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 414407128 ps |
| CPU time | 3.71 seconds |
| Started | Feb 21 02:36:17 PM PST 24 |
| Finished | Feb 21 02:36:24 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-d5bd1177-d81a-482f-a50c-ee9a1ace5f24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1176303808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1176303808 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.259662139 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 25024101230 ps |
| CPU time | 44.29 seconds |
| Started | Feb 21 02:36:09 PM PST 24 |
| Finished | Feb 21 02:36:54 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-8ac8dd6c-38d9-4c50-85d9-6d943b87f9f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=259662139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.259662139 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2334665039 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 7240968563 ps |
| CPU time | 33.91 seconds |
| Started | Feb 21 02:36:17 PM PST 24 |
| Finished | Feb 21 02:36:54 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-e41d89fb-4c9a-42f4-895b-813ef2eb1c99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2334665039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2334665039 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.1202431669 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 23239578 ps |
| CPU time | 2.06 seconds |
| Started | Feb 21 02:36:14 PM PST 24 |
| Finished | Feb 21 02:36:17 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-e9d36a89-3178-4b3c-ac1e-f7222c3a4387 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202431669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1202431669 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.2307369468 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 500133477 ps |
| CPU time | 23.18 seconds |
| Started | Feb 21 02:36:15 PM PST 24 |
| Finished | Feb 21 02:36:39 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-2c91630b-7274-4665-8fc5-dad76ec415be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2307369468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2307369468 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1850323179 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2496415257 ps |
| CPU time | 196.23 seconds |
| Started | Feb 21 02:36:12 PM PST 24 |
| Finished | Feb 21 02:39:29 PM PST 24 |
| Peak memory | 208976 kb |
| Host | smart-d6f34f16-7617-47a3-b4b8-b68dc3eebf9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1850323179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1850323179 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1808592100 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 45308312 ps |
| CPU time | 22.1 seconds |
| Started | Feb 21 02:36:31 PM PST 24 |
| Finished | Feb 21 02:36:54 PM PST 24 |
| Peak memory | 205588 kb |
| Host | smart-5e360efc-f676-4a7e-aef7-754012ebd4fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1808592100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.1808592100 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1790081183 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 207505880 ps |
| CPU time | 52.5 seconds |
| Started | Feb 21 02:36:30 PM PST 24 |
| Finished | Feb 21 02:37:22 PM PST 24 |
| Peak memory | 206164 kb |
| Host | smart-2461934d-c9ac-4e99-a044-261fc99dcb5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1790081183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.1790081183 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.4215632066 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 362216068 ps |
| CPU time | 22 seconds |
| Started | Feb 21 02:36:11 PM PST 24 |
| Finished | Feb 21 02:36:33 PM PST 24 |
| Peak memory | 204292 kb |
| Host | smart-f33b8f22-90a1-4593-92fe-c3133b345377 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4215632066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.4215632066 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3940094694 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1765051796 ps |
| CPU time | 65.51 seconds |
| Started | Feb 21 02:36:22 PM PST 24 |
| Finished | Feb 21 02:37:28 PM PST 24 |
| Peak memory | 211248 kb |
| Host | smart-f1260a9d-3cb7-48fb-8bf3-4babffa91a8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3940094694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3940094694 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.219179661 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 11022525177 ps |
| CPU time | 33.06 seconds |
| Started | Feb 21 02:36:32 PM PST 24 |
| Finished | Feb 21 02:37:06 PM PST 24 |
| Peak memory | 203568 kb |
| Host | smart-1f55f24d-a074-4898-a17b-1c60b7358d5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=219179661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slo w_rsp.219179661 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3477726782 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 719244308 ps |
| CPU time | 22.46 seconds |
| Started | Feb 21 02:36:21 PM PST 24 |
| Finished | Feb 21 02:36:44 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-598420b2-6fb4-4257-a701-97937befe236 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3477726782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3477726782 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.3969508249 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 156124288 ps |
| CPU time | 20.8 seconds |
| Started | Feb 21 02:36:16 PM PST 24 |
| Finished | Feb 21 02:36:38 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-e343cb3b-ecfa-41a3-8952-7f0515cb934a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3969508249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3969508249 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.2542614232 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2642484730 ps |
| CPU time | 18.88 seconds |
| Started | Feb 21 02:36:32 PM PST 24 |
| Finished | Feb 21 02:36:52 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-a686feb1-f75d-4dd6-986a-1735f798f680 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2542614232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2542614232 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.2922591979 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 11433584723 ps |
| CPU time | 54.17 seconds |
| Started | Feb 21 02:36:20 PM PST 24 |
| Finished | Feb 21 02:37:15 PM PST 24 |
| Peak memory | 204340 kb |
| Host | smart-da43a273-9b9a-467a-9711-00971daa8aa7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922591979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2922591979 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.971537608 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 11044654931 ps |
| CPU time | 21.25 seconds |
| Started | Feb 21 02:36:24 PM PST 24 |
| Finished | Feb 21 02:36:46 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-d95f2ee4-4a7b-4022-bf1b-cab76b812cdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=971537608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.971537608 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2609530588 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 142925732 ps |
| CPU time | 8.6 seconds |
| Started | Feb 21 02:36:19 PM PST 24 |
| Finished | Feb 21 02:36:29 PM PST 24 |
| Peak memory | 204112 kb |
| Host | smart-03bde96a-003a-46ec-ad4e-de15a6fbca09 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609530588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2609530588 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.1619299840 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 812845856 ps |
| CPU time | 4.41 seconds |
| Started | Feb 21 02:36:31 PM PST 24 |
| Finished | Feb 21 02:36:36 PM PST 24 |
| Peak memory | 203044 kb |
| Host | smart-c76ef8d1-3779-4bab-bd2d-9ff10a4639f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1619299840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1619299840 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.417854263 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 266576158 ps |
| CPU time | 3.95 seconds |
| Started | Feb 21 02:36:31 PM PST 24 |
| Finished | Feb 21 02:36:35 PM PST 24 |
| Peak memory | 203036 kb |
| Host | smart-342928de-4276-492b-ae79-0b9debfcbae5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=417854263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.417854263 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2312432940 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 9463078506 ps |
| CPU time | 33.85 seconds |
| Started | Feb 21 02:36:30 PM PST 24 |
| Finished | Feb 21 02:37:04 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-bc77e337-0533-4c65-8d76-bc30c6b9ce3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312432940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2312432940 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.86945753 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 3284669046 ps |
| CPU time | 27.11 seconds |
| Started | Feb 21 02:36:24 PM PST 24 |
| Finished | Feb 21 02:36:52 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-387f69b1-5bca-4b9b-952d-1482c39d84e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=86945753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.86945753 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.942931263 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 75744439 ps |
| CPU time | 2.36 seconds |
| Started | Feb 21 02:36:30 PM PST 24 |
| Finished | Feb 21 02:36:32 PM PST 24 |
| Peak memory | 203032 kb |
| Host | smart-2077ef5e-6037-4e00-b1a8-2fd28bae5594 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942931263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.942931263 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.755855168 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 36940215729 ps |
| CPU time | 239.17 seconds |
| Started | Feb 21 02:36:16 PM PST 24 |
| Finished | Feb 21 02:40:17 PM PST 24 |
| Peak memory | 210364 kb |
| Host | smart-2c41bfe6-55ca-4621-a624-4a08e4a1b660 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=755855168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.755855168 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.159041663 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2585840616 ps |
| CPU time | 95.36 seconds |
| Started | Feb 21 02:36:15 PM PST 24 |
| Finished | Feb 21 02:37:51 PM PST 24 |
| Peak memory | 205532 kb |
| Host | smart-cee7b30e-313e-4906-a287-cc8d0fa1b435 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=159041663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.159041663 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1708339659 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 470307864 ps |
| CPU time | 153.72 seconds |
| Started | Feb 21 02:36:18 PM PST 24 |
| Finished | Feb 21 02:38:54 PM PST 24 |
| Peak memory | 207684 kb |
| Host | smart-a6a7c74f-a8f9-4ef1-b02d-4c6868681fd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1708339659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.1708339659 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.759297600 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 547588767 ps |
| CPU time | 12.38 seconds |
| Started | Feb 21 02:36:31 PM PST 24 |
| Finished | Feb 21 02:36:44 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-4ff9042f-a975-441b-8bf6-07750440e663 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=759297600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.759297600 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.211554979 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1134512529 ps |
| CPU time | 31.12 seconds |
| Started | Feb 21 02:36:32 PM PST 24 |
| Finished | Feb 21 02:37:03 PM PST 24 |
| Peak memory | 205288 kb |
| Host | smart-26b738d1-cc93-455f-965e-514908db5830 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=211554979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.211554979 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.89889401 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 163886378581 ps |
| CPU time | 639.51 seconds |
| Started | Feb 21 02:36:43 PM PST 24 |
| Finished | Feb 21 02:47:26 PM PST 24 |
| Peak memory | 206652 kb |
| Host | smart-6fafafac-951f-4c50-a9f1-c8591a9520b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=89889401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow _rsp.89889401 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.946830860 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 380699321 ps |
| CPU time | 14.68 seconds |
| Started | Feb 21 02:36:44 PM PST 24 |
| Finished | Feb 21 02:37:01 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-d8e910b4-2d90-46a6-968b-dce63985aa0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=946830860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.946830860 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.3592889164 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 133602354 ps |
| CPU time | 17.47 seconds |
| Started | Feb 21 02:36:27 PM PST 24 |
| Finished | Feb 21 02:36:45 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-f4435141-6271-4c81-b3af-8dc34878f990 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3592889164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3592889164 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.1915402831 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 331494223 ps |
| CPU time | 17.74 seconds |
| Started | Feb 21 02:36:43 PM PST 24 |
| Finished | Feb 21 02:37:04 PM PST 24 |
| Peak memory | 211220 kb |
| Host | smart-761d6d47-88be-4154-8e90-264a3e5f3f6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1915402831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1915402831 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3343674109 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 20614353266 ps |
| CPU time | 82.13 seconds |
| Started | Feb 21 02:36:42 PM PST 24 |
| Finished | Feb 21 02:38:07 PM PST 24 |
| Peak memory | 204384 kb |
| Host | smart-b8a81f99-39e8-4248-92e9-f25b5307a8ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343674109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3343674109 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.362115648 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 25771808257 ps |
| CPU time | 146.56 seconds |
| Started | Feb 21 02:36:44 PM PST 24 |
| Finished | Feb 21 02:39:13 PM PST 24 |
| Peak memory | 204264 kb |
| Host | smart-06ec6dbd-416f-4208-8d81-f7356a2f1f47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=362115648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.362115648 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.2818938194 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 177176605 ps |
| CPU time | 19.68 seconds |
| Started | Feb 21 02:36:28 PM PST 24 |
| Finished | Feb 21 02:36:48 PM PST 24 |
| Peak memory | 211200 kb |
| Host | smart-96ac9281-905f-4e29-952e-dc82c723d8d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818938194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2818938194 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.2048925887 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2549461455 ps |
| CPU time | 38.19 seconds |
| Started | Feb 21 02:36:27 PM PST 24 |
| Finished | Feb 21 02:37:06 PM PST 24 |
| Peak memory | 203660 kb |
| Host | smart-ca1ce9e4-0f0e-4fb7-87c2-0003d5a03c68 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2048925887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2048925887 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.2566369246 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 52724433 ps |
| CPU time | 2.63 seconds |
| Started | Feb 21 02:36:14 PM PST 24 |
| Finished | Feb 21 02:36:17 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-80779284-a9a1-4dae-a7c6-2a2e51d53e59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2566369246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2566369246 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3603430210 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 4073723480 ps |
| CPU time | 24.16 seconds |
| Started | Feb 21 02:36:18 PM PST 24 |
| Finished | Feb 21 02:36:44 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-88a2ae23-5c8c-4905-9b36-30b9cdea6a4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603430210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3603430210 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2551146746 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 6560541078 ps |
| CPU time | 30.08 seconds |
| Started | Feb 21 02:36:42 PM PST 24 |
| Finished | Feb 21 02:37:15 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-9880aef5-5c48-4d15-b9b3-be98197dcd18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2551146746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2551146746 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2390328188 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 38841258 ps |
| CPU time | 2.2 seconds |
| Started | Feb 21 02:36:33 PM PST 24 |
| Finished | Feb 21 02:36:36 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-566c5172-a729-47be-bf7c-f52ac3963345 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390328188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2390328188 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.2158561475 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 11616906900 ps |
| CPU time | 369.13 seconds |
| Started | Feb 21 02:36:42 PM PST 24 |
| Finished | Feb 21 02:42:55 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-fba5410e-576e-4420-ae79-35dbac5cb6dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2158561475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2158561475 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2088675118 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1635998591 ps |
| CPU time | 90.46 seconds |
| Started | Feb 21 02:36:45 PM PST 24 |
| Finished | Feb 21 02:38:17 PM PST 24 |
| Peak memory | 211108 kb |
| Host | smart-f746319e-fc1a-4e5d-9b21-1c6f7637a176 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2088675118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2088675118 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.1124020979 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 11135680747 ps |
| CPU time | 212.3 seconds |
| Started | Feb 21 02:36:28 PM PST 24 |
| Finished | Feb 21 02:40:00 PM PST 24 |
| Peak memory | 209508 kb |
| Host | smart-0be14768-d6ac-44bc-97f3-f2c90137bf60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1124020979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran d_reset.1124020979 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.1452010621 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 171524694 ps |
| CPU time | 2.64 seconds |
| Started | Feb 21 02:36:43 PM PST 24 |
| Finished | Feb 21 02:36:49 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-e7129309-3913-45a7-9c65-3830df6c2509 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1452010621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1452010621 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.98919479 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 458899830 ps |
| CPU time | 14.63 seconds |
| Started | Feb 21 02:36:35 PM PST 24 |
| Finished | Feb 21 02:36:51 PM PST 24 |
| Peak memory | 204828 kb |
| Host | smart-7ddff14f-c14e-4888-8351-37ebe58d2742 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=98919479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.98919479 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2100158725 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 128219888873 ps |
| CPU time | 350.79 seconds |
| Started | Feb 21 02:36:44 PM PST 24 |
| Finished | Feb 21 02:42:37 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-bf89f028-850e-45bb-84a9-a4592bbf5090 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2100158725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.2100158725 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2388006847 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 116257013 ps |
| CPU time | 8.2 seconds |
| Started | Feb 21 02:36:44 PM PST 24 |
| Finished | Feb 21 02:36:54 PM PST 24 |
| Peak memory | 202964 kb |
| Host | smart-79726dc6-7bbf-46bd-a755-c49e80b2fdf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2388006847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2388006847 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.575805995 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 313183751 ps |
| CPU time | 9.86 seconds |
| Started | Feb 21 02:36:34 PM PST 24 |
| Finished | Feb 21 02:36:44 PM PST 24 |
| Peak memory | 202996 kb |
| Host | smart-bba215d6-fcb4-4214-bb4d-0b07757a3414 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=575805995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.575805995 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.3052101310 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 389510396 ps |
| CPU time | 26.47 seconds |
| Started | Feb 21 02:36:45 PM PST 24 |
| Finished | Feb 21 02:37:13 PM PST 24 |
| Peak memory | 211224 kb |
| Host | smart-372dc6dd-e923-4083-a5e8-4ac9399b3ec8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3052101310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3052101310 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.2360858980 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 20719973332 ps |
| CPU time | 95.04 seconds |
| Started | Feb 21 02:36:34 PM PST 24 |
| Finished | Feb 21 02:38:10 PM PST 24 |
| Peak memory | 204304 kb |
| Host | smart-b6721ee9-4dc8-4773-9018-e8ac8a6e7446 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360858980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2360858980 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.3701258185 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 42040656836 ps |
| CPU time | 192.64 seconds |
| Started | Feb 21 02:36:44 PM PST 24 |
| Finished | Feb 21 02:39:59 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-f505b7a4-7a6d-4efb-be6f-84aace5e332e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3701258185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3701258185 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.1900262858 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1089860253 ps |
| CPU time | 22.55 seconds |
| Started | Feb 21 02:36:44 PM PST 24 |
| Finished | Feb 21 02:37:09 PM PST 24 |
| Peak memory | 211268 kb |
| Host | smart-e0da774d-6597-476f-981d-0d7df42c7538 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900262858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1900262858 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.1878188019 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4000866110 ps |
| CPU time | 24.9 seconds |
| Started | Feb 21 02:36:37 PM PST 24 |
| Finished | Feb 21 02:37:02 PM PST 24 |
| Peak memory | 203524 kb |
| Host | smart-481c6364-ce7e-4e89-b0b0-6af1cf608031 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1878188019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1878188019 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.851314902 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 371529511 ps |
| CPU time | 3.67 seconds |
| Started | Feb 21 02:36:30 PM PST 24 |
| Finished | Feb 21 02:36:34 PM PST 24 |
| Peak memory | 203264 kb |
| Host | smart-3b2c1d6b-8c40-4ee2-838b-941d3898b17b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=851314902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.851314902 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.231416004 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 6325781083 ps |
| CPU time | 32.08 seconds |
| Started | Feb 21 02:36:45 PM PST 24 |
| Finished | Feb 21 02:37:19 PM PST 24 |
| Peak memory | 203104 kb |
| Host | smart-0efc5c6f-31c5-4d14-8861-3bcc9f0aecc4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=231416004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.231416004 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2186865666 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 7463346866 ps |
| CPU time | 30.59 seconds |
| Started | Feb 21 02:36:30 PM PST 24 |
| Finished | Feb 21 02:37:01 PM PST 24 |
| Peak memory | 203324 kb |
| Host | smart-599cc67c-78fc-4a6e-81fb-306751e18c85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2186865666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2186865666 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.260618794 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 31704477 ps |
| CPU time | 2.18 seconds |
| Started | Feb 21 02:36:44 PM PST 24 |
| Finished | Feb 21 02:36:49 PM PST 24 |
| Peak memory | 203032 kb |
| Host | smart-193bc009-7e99-4b90-9a81-651a31a88754 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260618794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.260618794 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.459238582 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2296816819 ps |
| CPU time | 64.05 seconds |
| Started | Feb 21 02:36:36 PM PST 24 |
| Finished | Feb 21 02:37:41 PM PST 24 |
| Peak memory | 206204 kb |
| Host | smart-897d77bc-cd03-441a-84a8-611c67dec009 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=459238582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.459238582 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1274561953 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4989848270 ps |
| CPU time | 88.07 seconds |
| Started | Feb 21 02:36:46 PM PST 24 |
| Finished | Feb 21 02:38:15 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-db5df75b-ffab-4c76-b4db-9671aafd4273 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1274561953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1274561953 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1553652178 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 6634598271 ps |
| CPU time | 292.43 seconds |
| Started | Feb 21 02:36:46 PM PST 24 |
| Finished | Feb 21 02:41:39 PM PST 24 |
| Peak memory | 207920 kb |
| Host | smart-15807bb8-0312-43b8-9c5d-c33858fcabb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1553652178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1553652178 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3115232553 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 71578502 ps |
| CPU time | 9.28 seconds |
| Started | Feb 21 02:36:44 PM PST 24 |
| Finished | Feb 21 02:36:56 PM PST 24 |
| Peak memory | 204240 kb |
| Host | smart-5153fb9f-b9b7-4a0a-9ac1-7c00e7275338 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3115232553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.3115232553 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.730995930 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 288512399 ps |
| CPU time | 11.23 seconds |
| Started | Feb 21 02:36:33 PM PST 24 |
| Finished | Feb 21 02:36:45 PM PST 24 |
| Peak memory | 204312 kb |
| Host | smart-c4067955-d90e-47ec-b65e-a9d76c13ead3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=730995930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.730995930 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.400073333 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 988712218 ps |
| CPU time | 48.47 seconds |
| Started | Feb 21 02:36:36 PM PST 24 |
| Finished | Feb 21 02:37:25 PM PST 24 |
| Peak memory | 204076 kb |
| Host | smart-4a77e587-8891-4f68-ad8b-5f0aea6bd668 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=400073333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.400073333 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3459244102 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 80924540835 ps |
| CPU time | 636.57 seconds |
| Started | Feb 21 02:36:40 PM PST 24 |
| Finished | Feb 21 02:47:17 PM PST 24 |
| Peak memory | 205432 kb |
| Host | smart-8f110579-6da3-4ad6-b0ef-0a8496e17821 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3459244102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.3459244102 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.1180904015 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 95894499 ps |
| CPU time | 13.25 seconds |
| Started | Feb 21 02:36:42 PM PST 24 |
| Finished | Feb 21 02:36:59 PM PST 24 |
| Peak memory | 203344 kb |
| Host | smart-4be5855f-acbc-4b71-abc3-402cc743ef1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1180904015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.1180904015 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.2600395974 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 368597679 ps |
| CPU time | 21.38 seconds |
| Started | Feb 21 02:36:43 PM PST 24 |
| Finished | Feb 21 02:37:08 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-bda6416b-69d8-440a-8081-308ffdfd2804 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2600395974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2600395974 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.1122044162 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1376648375 ps |
| CPU time | 30.32 seconds |
| Started | Feb 21 02:36:45 PM PST 24 |
| Finished | Feb 21 02:37:17 PM PST 24 |
| Peak memory | 211244 kb |
| Host | smart-37f9fb3a-b702-420a-b7ce-2b400f08473e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1122044162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1122044162 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.1501340106 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 28036201206 ps |
| CPU time | 146.99 seconds |
| Started | Feb 21 02:36:45 PM PST 24 |
| Finished | Feb 21 02:39:14 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-681145a1-f228-48c1-8c76-ef445668a77c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501340106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1501340106 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.62904147 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 9265414372 ps |
| CPU time | 45.08 seconds |
| Started | Feb 21 02:36:45 PM PST 24 |
| Finished | Feb 21 02:37:32 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-887aff16-123b-4f4f-b99b-d0c9246fba88 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=62904147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.62904147 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.3851645856 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 394072877 ps |
| CPU time | 24.99 seconds |
| Started | Feb 21 02:36:34 PM PST 24 |
| Finished | Feb 21 02:37:00 PM PST 24 |
| Peak memory | 211264 kb |
| Host | smart-ac3958bf-bf91-4df8-b56a-ed14418d4daf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851645856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3851645856 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1813003412 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 141288786 ps |
| CPU time | 13.28 seconds |
| Started | Feb 21 02:36:43 PM PST 24 |
| Finished | Feb 21 02:36:59 PM PST 24 |
| Peak memory | 203364 kb |
| Host | smart-326a79f3-4911-43be-bcde-a573dc59aaf8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1813003412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1813003412 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.544103943 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 30718991 ps |
| CPU time | 2.35 seconds |
| Started | Feb 21 02:36:43 PM PST 24 |
| Finished | Feb 21 02:36:49 PM PST 24 |
| Peak memory | 203264 kb |
| Host | smart-97d34f7a-1c13-4529-a989-7983e8919110 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=544103943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.544103943 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.313352263 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 12158876856 ps |
| CPU time | 44.22 seconds |
| Started | Feb 21 02:36:46 PM PST 24 |
| Finished | Feb 21 02:37:31 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-16b86f80-cd55-41be-a91e-e1e668894599 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=313352263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.313352263 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1228413815 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 8319739180 ps |
| CPU time | 28.68 seconds |
| Started | Feb 21 02:36:46 PM PST 24 |
| Finished | Feb 21 02:37:15 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-5da22abf-c35e-40b1-8dc9-6780f773eb6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1228413815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1228413815 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.573016648 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 35630730 ps |
| CPU time | 2.18 seconds |
| Started | Feb 21 02:36:44 PM PST 24 |
| Finished | Feb 21 02:36:49 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-ba388fd5-903d-4fda-9e9d-fb5ba3fb7952 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573016648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.573016648 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.3437353662 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1327340090 ps |
| CPU time | 36.95 seconds |
| Started | Feb 21 02:36:41 PM PST 24 |
| Finished | Feb 21 02:37:19 PM PST 24 |
| Peak memory | 205304 kb |
| Host | smart-c75506b7-ad9f-4acd-a216-2d883095037d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3437353662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3437353662 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3492702851 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3466243575 ps |
| CPU time | 74.82 seconds |
| Started | Feb 21 02:36:42 PM PST 24 |
| Finished | Feb 21 02:37:58 PM PST 24 |
| Peak memory | 204448 kb |
| Host | smart-a78f1ea0-e2b2-4ece-aece-6758ba2900b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3492702851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3492702851 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.4105631858 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 160625341 ps |
| CPU time | 90.55 seconds |
| Started | Feb 21 02:36:42 PM PST 24 |
| Finished | Feb 21 02:38:16 PM PST 24 |
| Peak memory | 207380 kb |
| Host | smart-091aed1d-7edc-4ecd-9d92-c4043929394e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4105631858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.4105631858 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2516153247 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3685055855 ps |
| CPU time | 115.33 seconds |
| Started | Feb 21 02:36:41 PM PST 24 |
| Finished | Feb 21 02:38:37 PM PST 24 |
| Peak memory | 209012 kb |
| Host | smart-416fdd4f-13ca-4e22-a8e9-3a71f80f9eca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2516153247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.2516153247 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.2202194323 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 763132694 ps |
| CPU time | 13.24 seconds |
| Started | Feb 21 02:36:43 PM PST 24 |
| Finished | Feb 21 02:37:00 PM PST 24 |
| Peak memory | 211224 kb |
| Host | smart-549977d4-2731-405e-91e3-cae972f0c146 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2202194323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2202194323 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2190418707 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 751427928 ps |
| CPU time | 46.62 seconds |
| Started | Feb 21 02:36:56 PM PST 24 |
| Finished | Feb 21 02:37:44 PM PST 24 |
| Peak memory | 205528 kb |
| Host | smart-cd32985e-9a1b-437e-bb7f-4ad47d2de82a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2190418707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2190418707 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.272962802 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2536411451 ps |
| CPU time | 18.74 seconds |
| Started | Feb 21 02:36:51 PM PST 24 |
| Finished | Feb 21 02:37:11 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-559851e5-bd9a-4ddd-b3a0-803413f68547 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=272962802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.272962802 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.3209682019 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2243113845 ps |
| CPU time | 33.99 seconds |
| Started | Feb 21 02:36:53 PM PST 24 |
| Finished | Feb 21 02:37:27 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-b8771c86-0911-4b63-a7b3-cc116b796b8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3209682019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3209682019 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.3540802272 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 311939225 ps |
| CPU time | 25.24 seconds |
| Started | Feb 21 02:36:41 PM PST 24 |
| Finished | Feb 21 02:37:07 PM PST 24 |
| Peak memory | 204560 kb |
| Host | smart-df7ff623-a2ad-4c81-8cd4-24e52190c530 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3540802272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3540802272 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.469783598 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 53623205642 ps |
| CPU time | 280.1 seconds |
| Started | Feb 21 02:36:39 PM PST 24 |
| Finished | Feb 21 02:41:20 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-d12b1ead-51ff-4521-aaa2-c95c029bc6dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=469783598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.469783598 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3824770535 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 188607707229 ps |
| CPU time | 347.51 seconds |
| Started | Feb 21 02:36:44 PM PST 24 |
| Finished | Feb 21 02:42:34 PM PST 24 |
| Peak memory | 204548 kb |
| Host | smart-82f94481-7b42-4797-9b7e-b3562bb24806 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3824770535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3824770535 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.3983627487 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 101842141 ps |
| CPU time | 11.8 seconds |
| Started | Feb 21 02:36:42 PM PST 24 |
| Finished | Feb 21 02:36:57 PM PST 24 |
| Peak memory | 204208 kb |
| Host | smart-d5a8042a-a6b4-49dc-abe7-38fbe911a300 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983627487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3983627487 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.2086610394 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 175807513 ps |
| CPU time | 8.24 seconds |
| Started | Feb 21 02:36:55 PM PST 24 |
| Finished | Feb 21 02:37:05 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-cc1ab883-d210-4cad-87b4-89bd107ceb4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2086610394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2086610394 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.3838946057 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 240933284 ps |
| CPU time | 3.16 seconds |
| Started | Feb 21 02:36:42 PM PST 24 |
| Finished | Feb 21 02:36:48 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-560bbf17-740e-4500-a352-915cce2dff14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3838946057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3838946057 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1209337652 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 7334385630 ps |
| CPU time | 36.72 seconds |
| Started | Feb 21 02:36:41 PM PST 24 |
| Finished | Feb 21 02:37:19 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-8ca7c294-277f-48ac-8f44-8de7f2595b36 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209337652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1209337652 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1468479151 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2752921568 ps |
| CPU time | 26.23 seconds |
| Started | Feb 21 02:36:40 PM PST 24 |
| Finished | Feb 21 02:37:07 PM PST 24 |
| Peak memory | 202976 kb |
| Host | smart-925a6bb8-cade-41e7-94e3-5e9c9b702f2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1468479151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1468479151 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2149019375 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 47019619 ps |
| CPU time | 2.1 seconds |
| Started | Feb 21 02:36:42 PM PST 24 |
| Finished | Feb 21 02:36:44 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-8487ad44-4d70-4a7d-822a-21b75af21939 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149019375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2149019375 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.607041924 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1584804859 ps |
| CPU time | 130.49 seconds |
| Started | Feb 21 02:36:54 PM PST 24 |
| Finished | Feb 21 02:39:07 PM PST 24 |
| Peak memory | 205460 kb |
| Host | smart-6e712daf-e72b-4449-a276-a71bc194bc7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=607041924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.607041924 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1661095093 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2300921661 ps |
| CPU time | 65.81 seconds |
| Started | Feb 21 02:36:55 PM PST 24 |
| Finished | Feb 21 02:38:03 PM PST 24 |
| Peak memory | 204524 kb |
| Host | smart-03e1cd11-c0a2-4170-b727-33dece3284ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1661095093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1661095093 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2915469331 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 92796478 ps |
| CPU time | 16.14 seconds |
| Started | Feb 21 02:37:06 PM PST 24 |
| Finished | Feb 21 02:37:27 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-a76c97a7-95f9-44c4-a1fe-c2c20cb830c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2915469331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.2915469331 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.607171530 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1584946732 ps |
| CPU time | 61.54 seconds |
| Started | Feb 21 02:36:56 PM PST 24 |
| Finished | Feb 21 02:37:59 PM PST 24 |
| Peak memory | 205772 kb |
| Host | smart-a18d91e5-25fa-47ec-9dd6-7e252ba9446d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=607171530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res et_error.607171530 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3477246851 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1122860532 ps |
| CPU time | 14.97 seconds |
| Started | Feb 21 02:36:53 PM PST 24 |
| Finished | Feb 21 02:37:10 PM PST 24 |
| Peak memory | 204312 kb |
| Host | smart-58da6d90-cc5b-4111-9d44-8ee236381883 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3477246851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3477246851 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2299799669 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1447516149 ps |
| CPU time | 43.45 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:36:48 PM PST 24 |
| Peak memory | 211204 kb |
| Host | smart-2cd6cf5c-f580-4a39-9d1b-7325ce1729c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2299799669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2299799669 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1690718119 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 128831310551 ps |
| CPU time | 739.01 seconds |
| Started | Feb 21 02:35:40 PM PST 24 |
| Finished | Feb 21 02:47:59 PM PST 24 |
| Peak memory | 206984 kb |
| Host | smart-1a9a5eb2-200b-4876-84eb-6eebdb745416 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1690718119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.1690718119 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2767290558 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 119426336 ps |
| CPU time | 21.55 seconds |
| Started | Feb 21 02:35:39 PM PST 24 |
| Finished | Feb 21 02:36:01 PM PST 24 |
| Peak memory | 203636 kb |
| Host | smart-19b78eaf-c1cc-423a-9fc5-df94bf6445fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2767290558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2767290558 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.632008515 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 58323666 ps |
| CPU time | 7.3 seconds |
| Started | Feb 21 02:35:38 PM PST 24 |
| Finished | Feb 21 02:35:46 PM PST 24 |
| Peak memory | 202920 kb |
| Host | smart-c4911906-ec6b-4e27-8b3b-25299a204559 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=632008515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.632008515 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.537122287 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 47467785 ps |
| CPU time | 3.13 seconds |
| Started | Feb 21 02:35:37 PM PST 24 |
| Finished | Feb 21 02:35:41 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-54e7c2f8-8cb4-468e-8898-5f328a124d0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=537122287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.537122287 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.2620420370 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 36908902554 ps |
| CPU time | 235.71 seconds |
| Started | Feb 21 02:35:45 PM PST 24 |
| Finished | Feb 21 02:39:41 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-5aeb8ec9-3181-4766-b6f0-d11bae821254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620420370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2620420370 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2696185976 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 15091360078 ps |
| CPU time | 79.16 seconds |
| Started | Feb 21 02:35:40 PM PST 24 |
| Finished | Feb 21 02:36:59 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-4bbf8a1a-8478-4fcf-9009-9c9d9b1568a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2696185976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2696185976 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2515872635 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 241346213 ps |
| CPU time | 23.98 seconds |
| Started | Feb 21 02:35:43 PM PST 24 |
| Finished | Feb 21 02:36:07 PM PST 24 |
| Peak memory | 203948 kb |
| Host | smart-678778cd-2ee6-4f82-bb94-c298880c6bdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515872635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2515872635 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.3589681251 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 218988590 ps |
| CPU time | 14.59 seconds |
| Started | Feb 21 02:35:46 PM PST 24 |
| Finished | Feb 21 02:36:01 PM PST 24 |
| Peak memory | 203616 kb |
| Host | smart-96033c57-4c7b-4474-88b3-16743168c264 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3589681251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3589681251 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.3082484470 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 204724412 ps |
| CPU time | 3.23 seconds |
| Started | Feb 21 02:35:47 PM PST 24 |
| Finished | Feb 21 02:35:53 PM PST 24 |
| Peak memory | 203016 kb |
| Host | smart-69cefc0a-644d-4c0c-ab0f-49734649857d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3082484470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3082484470 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.946499000 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 7283704924 ps |
| CPU time | 22.98 seconds |
| Started | Feb 21 02:35:38 PM PST 24 |
| Finished | Feb 21 02:36:01 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-8eae50c4-46ad-4ac3-8588-1ebf33333fca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=946499000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.946499000 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.162167011 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 16920679517 ps |
| CPU time | 39.04 seconds |
| Started | Feb 21 02:35:38 PM PST 24 |
| Finished | Feb 21 02:36:17 PM PST 24 |
| Peak memory | 203172 kb |
| Host | smart-23467931-2156-44a3-98af-e73bf1a26c74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=162167011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.162167011 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2276257396 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 27258964 ps |
| CPU time | 2.24 seconds |
| Started | Feb 21 02:35:37 PM PST 24 |
| Finished | Feb 21 02:35:40 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-7a2b01be-c03a-4171-940f-eddf287fc7fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276257396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2276257396 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.2440013206 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 15887506641 ps |
| CPU time | 201.65 seconds |
| Started | Feb 21 02:35:52 PM PST 24 |
| Finished | Feb 21 02:39:14 PM PST 24 |
| Peak memory | 209600 kb |
| Host | smart-eb836122-71b7-440a-b4ce-91290c68b805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2440013206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2440013206 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1871145499 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 523854693 ps |
| CPU time | 47.69 seconds |
| Started | Feb 21 02:35:39 PM PST 24 |
| Finished | Feb 21 02:36:28 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-9f72014f-484a-40c6-8b6c-98af190c3748 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1871145499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1871145499 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3180390873 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 270510520 ps |
| CPU time | 55.57 seconds |
| Started | Feb 21 02:35:52 PM PST 24 |
| Finished | Feb 21 02:36:48 PM PST 24 |
| Peak memory | 206832 kb |
| Host | smart-fc1cb844-6d94-4d2f-b396-59652e69dd3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3180390873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3180390873 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3400694112 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 92439191 ps |
| CPU time | 38.66 seconds |
| Started | Feb 21 02:35:51 PM PST 24 |
| Finished | Feb 21 02:36:31 PM PST 24 |
| Peak memory | 206744 kb |
| Host | smart-b1bf8302-257e-4788-93a3-d0d637e68803 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3400694112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.3400694112 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.469162886 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 975002269 ps |
| CPU time | 29.94 seconds |
| Started | Feb 21 02:35:46 PM PST 24 |
| Finished | Feb 21 02:36:20 PM PST 24 |
| Peak memory | 204168 kb |
| Host | smart-3682fc1d-3fbe-47a1-8b6f-21b3d8f9db16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=469162886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.469162886 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2563041597 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 312277071 ps |
| CPU time | 10.93 seconds |
| Started | Feb 21 02:36:51 PM PST 24 |
| Finished | Feb 21 02:37:03 PM PST 24 |
| Peak memory | 204084 kb |
| Host | smart-60d58877-a473-456d-ab04-f51260ee825b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2563041597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2563041597 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.802102880 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 82513402843 ps |
| CPU time | 684.83 seconds |
| Started | Feb 21 02:36:53 PM PST 24 |
| Finished | Feb 21 02:48:18 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-56143da1-a02b-4678-bf86-a73b46ea89de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=802102880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slo w_rsp.802102880 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1752372009 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 726512800 ps |
| CPU time | 27.32 seconds |
| Started | Feb 21 02:36:52 PM PST 24 |
| Finished | Feb 21 02:37:20 PM PST 24 |
| Peak memory | 202996 kb |
| Host | smart-f2fdcbf7-b85e-4afc-92ae-9464619f4f73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1752372009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1752372009 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.3897949822 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 448744100 ps |
| CPU time | 23.96 seconds |
| Started | Feb 21 02:36:52 PM PST 24 |
| Finished | Feb 21 02:37:17 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-6c98335a-6bb6-43cc-b9a7-f5f463f04a03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3897949822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3897949822 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.3325822648 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 6022436939 ps |
| CPU time | 34.82 seconds |
| Started | Feb 21 02:36:53 PM PST 24 |
| Finished | Feb 21 02:37:30 PM PST 24 |
| Peak memory | 204704 kb |
| Host | smart-cfe6735c-0d99-4e68-b363-7fde1241b4ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3325822648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3325822648 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1724539620 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 70050947488 ps |
| CPU time | 254.54 seconds |
| Started | Feb 21 02:36:52 PM PST 24 |
| Finished | Feb 21 02:41:08 PM PST 24 |
| Peak memory | 204300 kb |
| Host | smart-0b53eee7-2f9b-4b79-a123-9eecc0b8a914 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724539620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1724539620 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1269318175 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 77147792610 ps |
| CPU time | 193.27 seconds |
| Started | Feb 21 02:36:54 PM PST 24 |
| Finished | Feb 21 02:40:10 PM PST 24 |
| Peak memory | 204340 kb |
| Host | smart-3b43063c-b1cf-4188-8874-cc27a61a8e0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1269318175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1269318175 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3182941297 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 147305426 ps |
| CPU time | 22.8 seconds |
| Started | Feb 21 02:36:56 PM PST 24 |
| Finished | Feb 21 02:37:20 PM PST 24 |
| Peak memory | 211244 kb |
| Host | smart-0ae9bf6e-5d5a-4cba-bdc7-25b0192ee9b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182941297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3182941297 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.3996776766 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1203596595 ps |
| CPU time | 17.25 seconds |
| Started | Feb 21 02:36:52 PM PST 24 |
| Finished | Feb 21 02:37:10 PM PST 24 |
| Peak memory | 203600 kb |
| Host | smart-09bf2d02-1a2a-4f7e-9fae-d12df9418930 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3996776766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3996776766 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.370851988 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 54310884 ps |
| CPU time | 2.58 seconds |
| Started | Feb 21 02:36:54 PM PST 24 |
| Finished | Feb 21 02:37:00 PM PST 24 |
| Peak memory | 203032 kb |
| Host | smart-11e48a64-d251-4709-92da-53f2911dbaa7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=370851988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.370851988 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.533552708 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 10372702064 ps |
| CPU time | 33.39 seconds |
| Started | Feb 21 02:36:51 PM PST 24 |
| Finished | Feb 21 02:37:25 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-d579b35e-e3cf-471b-8f79-d88c61302b72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=533552708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.533552708 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2063302493 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 5155989037 ps |
| CPU time | 31.49 seconds |
| Started | Feb 21 02:36:54 PM PST 24 |
| Finished | Feb 21 02:37:29 PM PST 24 |
| Peak memory | 202756 kb |
| Host | smart-70f681fe-0eb5-4289-b778-25929210edd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2063302493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2063302493 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3687644652 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 152249047 ps |
| CPU time | 2.68 seconds |
| Started | Feb 21 02:36:53 PM PST 24 |
| Finished | Feb 21 02:36:59 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-0e868594-848b-438b-89e7-5a8c9fc5324b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687644652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3687644652 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.681512408 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 3534635539 ps |
| CPU time | 163.28 seconds |
| Started | Feb 21 02:36:53 PM PST 24 |
| Finished | Feb 21 02:39:36 PM PST 24 |
| Peak memory | 206696 kb |
| Host | smart-005fbe62-8846-4a9b-8ddb-f88e7fbfd270 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=681512408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.681512408 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1917169074 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1590045783 ps |
| CPU time | 65.04 seconds |
| Started | Feb 21 02:36:52 PM PST 24 |
| Finished | Feb 21 02:37:58 PM PST 24 |
| Peak memory | 211248 kb |
| Host | smart-076b8ed4-2275-4f38-aba7-a09df1919440 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1917169074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1917169074 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.1152162464 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 603606845 ps |
| CPU time | 275.01 seconds |
| Started | Feb 21 02:36:56 PM PST 24 |
| Finished | Feb 21 02:41:33 PM PST 24 |
| Peak memory | 208264 kb |
| Host | smart-cce22f08-9322-46e6-88ab-23a9c1109cb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1152162464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran d_reset.1152162464 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3843396764 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 249185840 ps |
| CPU time | 11.06 seconds |
| Started | Feb 21 02:36:52 PM PST 24 |
| Finished | Feb 21 02:37:04 PM PST 24 |
| Peak memory | 211212 kb |
| Host | smart-27317d75-6b72-4693-8471-a61cfe9e4090 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3843396764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3843396764 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.1176007466 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1381080614 ps |
| CPU time | 55.08 seconds |
| Started | Feb 21 02:36:55 PM PST 24 |
| Finished | Feb 21 02:37:52 PM PST 24 |
| Peak memory | 204944 kb |
| Host | smart-94bcda92-6396-4c8b-9506-8df93f92dd26 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1176007466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1176007466 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1820824169 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 153070384687 ps |
| CPU time | 563.79 seconds |
| Started | Feb 21 02:37:05 PM PST 24 |
| Finished | Feb 21 02:46:34 PM PST 24 |
| Peak memory | 205496 kb |
| Host | smart-fe90a16b-714a-444b-ad49-ec869dac7750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1820824169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.1820824169 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3020340574 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 84223175 ps |
| CPU time | 8.26 seconds |
| Started | Feb 21 02:36:53 PM PST 24 |
| Finished | Feb 21 02:37:05 PM PST 24 |
| Peak memory | 203200 kb |
| Host | smart-8da9d320-ee88-40fb-8ca7-c07a72317d3a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3020340574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3020340574 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.1459476017 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 640758589 ps |
| CPU time | 23.33 seconds |
| Started | Feb 21 02:36:52 PM PST 24 |
| Finished | Feb 21 02:37:16 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-83f37ab0-1eca-4fb9-b234-f0f30b6f80bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1459476017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1459476017 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.4119866219 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 808906835 ps |
| CPU time | 14.55 seconds |
| Started | Feb 21 02:36:54 PM PST 24 |
| Finished | Feb 21 02:37:12 PM PST 24 |
| Peak memory | 204204 kb |
| Host | smart-ee785619-3adb-4e0d-89f6-41dd2f3e176c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4119866219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.4119866219 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.1899935469 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 27126805875 ps |
| CPU time | 143.4 seconds |
| Started | Feb 21 02:36:55 PM PST 24 |
| Finished | Feb 21 02:39:20 PM PST 24 |
| Peak memory | 204404 kb |
| Host | smart-b2e7064b-9660-46ec-a6ad-bf67ee39289e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899935469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1899935469 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.360911171 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 32023670652 ps |
| CPU time | 153.8 seconds |
| Started | Feb 21 02:36:54 PM PST 24 |
| Finished | Feb 21 02:39:31 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-5006ebb0-1248-482f-83a7-dcab4ef6645b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=360911171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.360911171 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.206666276 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 174435788 ps |
| CPU time | 24.15 seconds |
| Started | Feb 21 02:36:52 PM PST 24 |
| Finished | Feb 21 02:37:17 PM PST 24 |
| Peak memory | 204136 kb |
| Host | smart-688cd069-b90e-4eda-8d0c-bc33067e3d80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206666276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.206666276 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.1616248509 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 450894861 ps |
| CPU time | 19.01 seconds |
| Started | Feb 21 02:36:56 PM PST 24 |
| Finished | Feb 21 02:37:17 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-5b1a9440-5297-417a-920e-15014f2a98c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1616248509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1616248509 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.711608354 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 40299565 ps |
| CPU time | 2.42 seconds |
| Started | Feb 21 02:36:59 PM PST 24 |
| Finished | Feb 21 02:37:02 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-64e5e838-e6d4-4e8f-ab16-d84bb9312c34 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=711608354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.711608354 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.953351031 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 18480548402 ps |
| CPU time | 27.94 seconds |
| Started | Feb 21 02:36:53 PM PST 24 |
| Finished | Feb 21 02:37:21 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-ca2fee3d-f22d-46f1-85fe-b889b3045d70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=953351031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.953351031 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1181206271 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 9445195990 ps |
| CPU time | 32.89 seconds |
| Started | Feb 21 02:36:55 PM PST 24 |
| Finished | Feb 21 02:37:30 PM PST 24 |
| Peak memory | 203356 kb |
| Host | smart-cbac5bc5-ca89-4242-858e-e6d6f061b6cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1181206271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1181206271 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.860658984 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 173562097 ps |
| CPU time | 2.74 seconds |
| Started | Feb 21 02:36:56 PM PST 24 |
| Finished | Feb 21 02:37:00 PM PST 24 |
| Peak memory | 202972 kb |
| Host | smart-a67757d0-ae6f-449b-aa2c-a67ab1d7655c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860658984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.860658984 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.3147220393 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3282519482 ps |
| CPU time | 139.39 seconds |
| Started | Feb 21 02:36:54 PM PST 24 |
| Finished | Feb 21 02:39:17 PM PST 24 |
| Peak memory | 207088 kb |
| Host | smart-5a85db48-9ef0-45ac-9316-342df8801aca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3147220393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3147220393 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.1521703127 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2762331103 ps |
| CPU time | 59.34 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:38:23 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-500b7d89-f989-4451-a459-d3061b2e44f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1521703127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1521703127 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.2977973479 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 549525001 ps |
| CPU time | 70.22 seconds |
| Started | Feb 21 02:37:12 PM PST 24 |
| Finished | Feb 21 02:38:23 PM PST 24 |
| Peak memory | 206336 kb |
| Host | smart-06d35bed-3cc2-4524-8638-846e9f3cfbb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2977973479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.2977973479 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2811188349 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 937669415 ps |
| CPU time | 117.03 seconds |
| Started | Feb 21 02:37:07 PM PST 24 |
| Finished | Feb 21 02:39:08 PM PST 24 |
| Peak memory | 208780 kb |
| Host | smart-205edb27-4844-41dd-9e47-579b232527b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2811188349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.2811188349 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.1945978805 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 68352189 ps |
| CPU time | 12.14 seconds |
| Started | Feb 21 02:36:55 PM PST 24 |
| Finished | Feb 21 02:37:09 PM PST 24 |
| Peak memory | 204476 kb |
| Host | smart-fdbc642f-6c89-4d34-9fbb-aecee48ca457 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1945978805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1945978805 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1231839728 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 964879334 ps |
| CPU time | 41.03 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:38:07 PM PST 24 |
| Peak memory | 204320 kb |
| Host | smart-bcd4fdb1-bf4c-4d2f-9ea9-e787e78015d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1231839728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1231839728 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2728477409 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 716634051 ps |
| CPU time | 22.66 seconds |
| Started | Feb 21 02:37:09 PM PST 24 |
| Finished | Feb 21 02:37:34 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-aeacb45a-ada5-47eb-bea4-755a2e5a3f56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2728477409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2728477409 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.2333014663 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3492990662 ps |
| CPU time | 33.54 seconds |
| Started | Feb 21 02:37:21 PM PST 24 |
| Finished | Feb 21 02:37:57 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-af89b5c8-e7f1-4576-bd67-6620deb60215 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2333014663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2333014663 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.3728023871 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 1068541070 ps |
| CPU time | 35.71 seconds |
| Started | Feb 21 02:37:20 PM PST 24 |
| Finished | Feb 21 02:37:57 PM PST 24 |
| Peak memory | 211256 kb |
| Host | smart-f7d10c76-463f-4e75-bd0a-b85b4651a87a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3728023871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3728023871 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3506452230 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 25811449082 ps |
| CPU time | 153.5 seconds |
| Started | Feb 21 02:37:07 PM PST 24 |
| Finished | Feb 21 02:39:44 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-b49e0422-214f-4b58-a8b5-326ae043b318 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506452230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3506452230 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.1536721274 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 47240865713 ps |
| CPU time | 128.95 seconds |
| Started | Feb 21 02:37:09 PM PST 24 |
| Finished | Feb 21 02:39:20 PM PST 24 |
| Peak memory | 211168 kb |
| Host | smart-0143ef46-bc60-4562-b7fa-96b981142dc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1536721274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1536721274 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.1061025411 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 144730362 ps |
| CPU time | 26.54 seconds |
| Started | Feb 21 02:37:11 PM PST 24 |
| Finished | Feb 21 02:37:38 PM PST 24 |
| Peak memory | 211132 kb |
| Host | smart-92da161f-e8ba-4665-abb5-bbede55b89d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061025411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1061025411 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.283483868 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1545076563 ps |
| CPU time | 35.18 seconds |
| Started | Feb 21 02:37:08 PM PST 24 |
| Finished | Feb 21 02:37:46 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-7fa85513-8d59-4c0f-986c-89e86058e4f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=283483868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.283483868 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.3455721531 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 502384698 ps |
| CPU time | 3.76 seconds |
| Started | Feb 21 02:37:12 PM PST 24 |
| Finished | Feb 21 02:37:16 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-30a4102c-967b-44f4-bc2b-b4b7bbfc7f58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3455721531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3455721531 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1762889330 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 8346486400 ps |
| CPU time | 39.39 seconds |
| Started | Feb 21 02:37:11 PM PST 24 |
| Finished | Feb 21 02:37:51 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-3eb3bdc3-cf96-4f74-b3bf-19ae20c8de17 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762889330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1762889330 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1544741218 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 9571200347 ps |
| CPU time | 28.28 seconds |
| Started | Feb 21 02:37:20 PM PST 24 |
| Finished | Feb 21 02:37:51 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-6c4be52f-512d-499e-aa73-6effcb9dfcc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1544741218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1544741218 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.1442521347 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 55202507 ps |
| CPU time | 2.23 seconds |
| Started | Feb 21 02:37:20 PM PST 24 |
| Finished | Feb 21 02:37:24 PM PST 24 |
| Peak memory | 202912 kb |
| Host | smart-254d6acd-4424-42da-b4d6-8f28cd895c8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442521347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.1442521347 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3726494474 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1326374245 ps |
| CPU time | 32.23 seconds |
| Started | Feb 21 02:37:13 PM PST 24 |
| Finished | Feb 21 02:37:46 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-4b9c12d4-8783-490d-bcae-dbca6e907af2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3726494474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3726494474 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3752748188 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 15146239657 ps |
| CPU time | 164.14 seconds |
| Started | Feb 21 02:37:07 PM PST 24 |
| Finished | Feb 21 02:39:55 PM PST 24 |
| Peak memory | 207568 kb |
| Host | smart-4304f3a2-5d85-4d9f-ad1a-07cf2b4c9088 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3752748188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3752748188 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.916535845 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3050707026 ps |
| CPU time | 200.09 seconds |
| Started | Feb 21 02:37:11 PM PST 24 |
| Finished | Feb 21 02:40:32 PM PST 24 |
| Peak memory | 208872 kb |
| Host | smart-fa667774-faed-436f-848a-301037473d7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=916535845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand _reset.916535845 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.4162603608 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1802176041 ps |
| CPU time | 242.52 seconds |
| Started | Feb 21 02:37:12 PM PST 24 |
| Finished | Feb 21 02:41:15 PM PST 24 |
| Peak memory | 211064 kb |
| Host | smart-4eee062c-6acd-4694-8fbb-1af215eef2bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4162603608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.4162603608 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.2479455147 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 58675826 ps |
| CPU time | 2.5 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:37:27 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-91ff6d66-aa2e-4726-9431-621a8f48c9ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2479455147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2479455147 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.4270907836 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 663066581 ps |
| CPU time | 42.61 seconds |
| Started | Feb 21 02:37:13 PM PST 24 |
| Finished | Feb 21 02:37:56 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-1379c24c-9dce-44df-93cc-5cba9c9aa95a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4270907836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.4270907836 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2678958028 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 128387735256 ps |
| CPU time | 666.19 seconds |
| Started | Feb 21 02:37:13 PM PST 24 |
| Finished | Feb 21 02:48:20 PM PST 24 |
| Peak memory | 211212 kb |
| Host | smart-5a2d7989-a3df-4aaa-be70-87d290396803 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2678958028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.2678958028 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2079565428 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 529218880 ps |
| CPU time | 16.03 seconds |
| Started | Feb 21 02:37:09 PM PST 24 |
| Finished | Feb 21 02:37:27 PM PST 24 |
| Peak memory | 203156 kb |
| Host | smart-17a83d88-9cbf-4375-9d2a-4f4e373a0fb5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2079565428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2079565428 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.394619388 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 775665234 ps |
| CPU time | 24.77 seconds |
| Started | Feb 21 02:37:10 PM PST 24 |
| Finished | Feb 21 02:37:36 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-db02ced3-620b-4e6b-afcb-b3cde9924d04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=394619388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.394619388 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.618723209 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1281729691 ps |
| CPU time | 20.86 seconds |
| Started | Feb 21 02:37:16 PM PST 24 |
| Finished | Feb 21 02:37:37 PM PST 24 |
| Peak memory | 204176 kb |
| Host | smart-a9ffcf25-d5c8-4568-afc8-9ef58c067f4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=618723209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.618723209 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.4044196446 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 198002091462 ps |
| CPU time | 269.64 seconds |
| Started | Feb 21 02:37:13 PM PST 24 |
| Finished | Feb 21 02:41:44 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-16ef4c13-3ff5-4bf9-87b2-d699635eb0b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044196446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.4044196446 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.558950887 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 56031096654 ps |
| CPU time | 199.1 seconds |
| Started | Feb 21 02:37:19 PM PST 24 |
| Finished | Feb 21 02:40:38 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-a99078e9-54f2-448d-82ed-2e4c03c853bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=558950887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.558950887 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.1251553129 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 219674756 ps |
| CPU time | 18.37 seconds |
| Started | Feb 21 02:37:18 PM PST 24 |
| Finished | Feb 21 02:37:37 PM PST 24 |
| Peak memory | 211200 kb |
| Host | smart-a37d9394-263d-41bb-8869-3b6af90bc038 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251553129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1251553129 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.668430265 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2064154528 ps |
| CPU time | 23.62 seconds |
| Started | Feb 21 02:37:20 PM PST 24 |
| Finished | Feb 21 02:37:46 PM PST 24 |
| Peak memory | 203672 kb |
| Host | smart-19fce3df-50f6-4f24-8afe-8dad6ddbf78c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=668430265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.668430265 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.788881256 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 305716194 ps |
| CPU time | 3.77 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:27 PM PST 24 |
| Peak memory | 203024 kb |
| Host | smart-25d2b76f-0111-455c-806d-3507090f42a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=788881256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.788881256 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.4080264441 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 10665346957 ps |
| CPU time | 28.86 seconds |
| Started | Feb 21 02:37:08 PM PST 24 |
| Finished | Feb 21 02:37:40 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-6a4eb1d5-6dc4-44ca-9e2f-e77799fb3616 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080264441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4080264441 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.221287340 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 29519281924 ps |
| CPU time | 58.22 seconds |
| Started | Feb 21 02:37:13 PM PST 24 |
| Finished | Feb 21 02:38:11 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-3d71e4c6-5481-4c7e-a83c-b40124817fc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=221287340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.221287340 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1622415484 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 43055212 ps |
| CPU time | 2.38 seconds |
| Started | Feb 21 02:37:10 PM PST 24 |
| Finished | Feb 21 02:37:14 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-ad99e5ac-a2f3-42e2-8771-3935548c701a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622415484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1622415484 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.2913587947 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 21696795104 ps |
| CPU time | 236.13 seconds |
| Started | Feb 21 02:37:20 PM PST 24 |
| Finished | Feb 21 02:41:17 PM PST 24 |
| Peak memory | 206756 kb |
| Host | smart-0cbe19ab-756f-4040-abb6-5cbeb4d1491d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2913587947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2913587947 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2445351934 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 80000043 ps |
| CPU time | 7.3 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:30 PM PST 24 |
| Peak memory | 203536 kb |
| Host | smart-63a1ee9a-affc-4380-a3cf-107f1726f642 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2445351934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2445351934 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.3875101019 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1778440350 ps |
| CPU time | 355.96 seconds |
| Started | Feb 21 02:37:11 PM PST 24 |
| Finished | Feb 21 02:43:08 PM PST 24 |
| Peak memory | 207964 kb |
| Host | smart-bbf0edfb-3218-4f4c-a6b1-066039c0a241 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3875101019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.3875101019 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1927862681 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 18896267809 ps |
| CPU time | 611.1 seconds |
| Started | Feb 21 02:37:17 PM PST 24 |
| Finished | Feb 21 02:47:28 PM PST 24 |
| Peak memory | 219844 kb |
| Host | smart-5879c40c-d176-4cdf-8fc2-d5e653eddaf6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1927862681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.1927862681 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1562812172 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1391264235 ps |
| CPU time | 14.82 seconds |
| Started | Feb 21 02:37:14 PM PST 24 |
| Finished | Feb 21 02:37:29 PM PST 24 |
| Peak memory | 204448 kb |
| Host | smart-ce34cb26-f614-40b9-868f-4e9fa023f67e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1562812172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1562812172 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.1558780149 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 157788252 ps |
| CPU time | 4.68 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:37:28 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-e0ce75bf-dab1-4dab-b71f-23631caa6066 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1558780149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.1558780149 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.48953610 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 27413192422 ps |
| CPU time | 154.46 seconds |
| Started | Feb 21 02:37:24 PM PST 24 |
| Finished | Feb 21 02:39:59 PM PST 24 |
| Peak memory | 211276 kb |
| Host | smart-b55046c8-43bd-494a-9738-dc3f521549d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=48953610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow _rsp.48953610 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.4005847859 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 38677788 ps |
| CPU time | 5.56 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:32 PM PST 24 |
| Peak memory | 203012 kb |
| Host | smart-26889fd1-4b1e-4d07-9732-3def54df2a35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4005847859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.4005847859 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.2221410681 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 152721267 ps |
| CPU time | 5.4 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:31 PM PST 24 |
| Peak memory | 203284 kb |
| Host | smart-6a39a871-dfbb-4a10-bf0d-65f82b46f2b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2221410681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2221410681 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.730297802 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 860114859 ps |
| CPU time | 29.66 seconds |
| Started | Feb 21 02:37:21 PM PST 24 |
| Finished | Feb 21 02:37:52 PM PST 24 |
| Peak memory | 204252 kb |
| Host | smart-d9d51e53-cb99-4f6d-9814-96bbe1ef5a7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=730297802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.730297802 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.877793443 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 39413829896 ps |
| CPU time | 117.05 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:39:20 PM PST 24 |
| Peak memory | 204300 kb |
| Host | smart-dadf4b64-bb76-4775-abfc-b465c86f3bd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=877793443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.877793443 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2385733235 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 150876098331 ps |
| CPU time | 332.38 seconds |
| Started | Feb 21 02:37:14 PM PST 24 |
| Finished | Feb 21 02:42:47 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-9aa63238-46b5-4678-98cc-9f8f8c5c0a24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2385733235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2385733235 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1207220615 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 333133403 ps |
| CPU time | 19.15 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:45 PM PST 24 |
| Peak memory | 211468 kb |
| Host | smart-8babad9f-ddcc-4225-bfdc-f1771663a914 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207220615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1207220615 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.3705770619 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 855678654 ps |
| CPU time | 20.71 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:46 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-795dc197-9ec1-4250-a48e-6ed8588363df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3705770619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3705770619 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.571384095 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 130577326 ps |
| CPU time | 4.09 seconds |
| Started | Feb 21 02:37:12 PM PST 24 |
| Finished | Feb 21 02:37:16 PM PST 24 |
| Peak memory | 202748 kb |
| Host | smart-4882569b-6648-429d-951c-ed9e2b6baac9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=571384095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.571384095 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2280994354 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 6127194792 ps |
| CPU time | 26.22 seconds |
| Started | Feb 21 02:37:19 PM PST 24 |
| Finished | Feb 21 02:37:46 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-f354ccb5-0c24-4052-8782-fb8348e1a7ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280994354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2280994354 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.811563809 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4842734289 ps |
| CPU time | 31.31 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:55 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-d7bb90de-cd1c-4a07-939c-d3518ba1e0ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=811563809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.811563809 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.213628605 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 54946624 ps |
| CPU time | 2.8 seconds |
| Started | Feb 21 02:37:11 PM PST 24 |
| Finished | Feb 21 02:37:15 PM PST 24 |
| Peak memory | 202940 kb |
| Host | smart-d01422c8-472e-4d18-a4a8-c0d78625122b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213628605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.213628605 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.1649621225 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6223086963 ps |
| CPU time | 184.09 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:40:27 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-fc323482-8331-4377-b2bd-71f238d67507 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1649621225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1649621225 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2699749957 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 5927245745 ps |
| CPU time | 59.43 seconds |
| Started | Feb 21 02:37:10 PM PST 24 |
| Finished | Feb 21 02:38:11 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-6da6cffb-9b09-47e4-8cc0-80bcc7816027 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2699749957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2699749957 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.4185371334 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3110663065 ps |
| CPU time | 215.93 seconds |
| Started | Feb 21 02:37:28 PM PST 24 |
| Finished | Feb 21 02:41:05 PM PST 24 |
| Peak memory | 209416 kb |
| Host | smart-72f2dead-0f40-4a56-a80b-061437e2b30a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4185371334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.4185371334 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3038445760 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 584859783 ps |
| CPU time | 125.21 seconds |
| Started | Feb 21 02:37:15 PM PST 24 |
| Finished | Feb 21 02:39:20 PM PST 24 |
| Peak memory | 209912 kb |
| Host | smart-83ac110a-71b1-4b01-9eb9-af8317177bde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3038445760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.3038445760 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.2517801577 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1168674055 ps |
| CPU time | 25.08 seconds |
| Started | Feb 21 02:37:16 PM PST 24 |
| Finished | Feb 21 02:37:41 PM PST 24 |
| Peak memory | 204648 kb |
| Host | smart-cd95bc3a-de94-4c12-9013-43611c672680 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2517801577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2517801577 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.195306171 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 174669172 ps |
| CPU time | 14.45 seconds |
| Started | Feb 21 02:37:13 PM PST 24 |
| Finished | Feb 21 02:37:29 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-0ef859f3-5614-4e1f-9e6f-05a1d2673d79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=195306171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.195306171 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.784721145 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 27613410256 ps |
| CPU time | 131.45 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:39:39 PM PST 24 |
| Peak memory | 205424 kb |
| Host | smart-cbf4500a-5327-4afa-877e-52ff555dc098 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=784721145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.784721145 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3281984301 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 239520515 ps |
| CPU time | 16.36 seconds |
| Started | Feb 21 02:37:20 PM PST 24 |
| Finished | Feb 21 02:37:39 PM PST 24 |
| Peak memory | 203336 kb |
| Host | smart-1a164151-651f-43c6-b92e-6101681fa25f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3281984301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3281984301 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.2772160592 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 468027944 ps |
| CPU time | 15.97 seconds |
| Started | Feb 21 02:37:11 PM PST 24 |
| Finished | Feb 21 02:37:28 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-2c74756e-3fea-4d60-afc7-40142c9ea755 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2772160592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2772160592 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.2610203163 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 144572520 ps |
| CPU time | 19.15 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:45 PM PST 24 |
| Peak memory | 204000 kb |
| Host | smart-01d903ea-15b4-4b9c-883c-9eabc93fe999 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2610203163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2610203163 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.861829401 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 13473044390 ps |
| CPU time | 71.67 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:38:38 PM PST 24 |
| Peak memory | 211120 kb |
| Host | smart-d529f050-d668-4381-8c2e-9850301ba678 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=861829401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.861829401 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1667923769 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 20507753140 ps |
| CPU time | 161.6 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:40:05 PM PST 24 |
| Peak memory | 211292 kb |
| Host | smart-06770ee1-74e3-44b0-aeaf-b1c545c4bc46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1667923769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1667923769 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.4252370811 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 32821566 ps |
| CPU time | 4.26 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:27 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-d1f44be4-0f99-4bad-b836-0144cbc009f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252370811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.4252370811 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.2367239862 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 62106564 ps |
| CPU time | 5.51 seconds |
| Started | Feb 21 02:37:16 PM PST 24 |
| Finished | Feb 21 02:37:21 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-9c0384e0-f6c5-451b-8d29-717bbd5d94bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2367239862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2367239862 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.3100161002 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 309786541 ps |
| CPU time | 3.63 seconds |
| Started | Feb 21 02:37:21 PM PST 24 |
| Finished | Feb 21 02:37:26 PM PST 24 |
| Peak memory | 203288 kb |
| Host | smart-e241c588-ac88-40dc-aa60-8e5940489766 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3100161002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3100161002 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.947303080 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 8114900069 ps |
| CPU time | 36.44 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:38:04 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-de498aac-217f-4dd6-9fe9-6b44f5315abf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=947303080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.947303080 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2548227095 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 6046673291 ps |
| CPU time | 24.2 seconds |
| Started | Feb 21 02:37:12 PM PST 24 |
| Finished | Feb 21 02:37:37 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-49fea7d2-32c2-4961-acba-19713bff2e79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2548227095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2548227095 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.4098950064 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 30446832 ps |
| CPU time | 2.12 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:28 PM PST 24 |
| Peak memory | 202996 kb |
| Host | smart-5ad4fc00-7ac8-4d48-a7a2-1776663a4cee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098950064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.4098950064 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.3715283173 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 1189790905 ps |
| CPU time | 158.09 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:40:01 PM PST 24 |
| Peak memory | 211240 kb |
| Host | smart-4f9dab1c-a078-4cff-b57c-a4c9ff0a3f5f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3715283173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3715283173 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1460919912 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3685297793 ps |
| CPU time | 45.38 seconds |
| Started | Feb 21 02:37:24 PM PST 24 |
| Finished | Feb 21 02:38:10 PM PST 24 |
| Peak memory | 211292 kb |
| Host | smart-a0d786ba-9464-4f40-bd9b-848808abb2e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1460919912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1460919912 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.4224762144 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 174833604 ps |
| CPU time | 72.8 seconds |
| Started | Feb 21 02:37:19 PM PST 24 |
| Finished | Feb 21 02:38:32 PM PST 24 |
| Peak memory | 206064 kb |
| Host | smart-9d836077-7134-4663-8f9b-984a823e7dc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4224762144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_ran d_reset.4224762144 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.928910949 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 284408390 ps |
| CPU time | 59.08 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:38:27 PM PST 24 |
| Peak memory | 206260 kb |
| Host | smart-8d652598-83be-46ad-9c5d-7a4664a6c28f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=928910949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res et_error.928910949 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.2066224897 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 319412144 ps |
| CPU time | 10.63 seconds |
| Started | Feb 21 02:37:28 PM PST 24 |
| Finished | Feb 21 02:37:40 PM PST 24 |
| Peak memory | 204312 kb |
| Host | smart-16580a75-448a-4511-a038-372418834e48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2066224897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2066224897 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.1859676926 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 426997957 ps |
| CPU time | 37.92 seconds |
| Started | Feb 21 02:37:21 PM PST 24 |
| Finished | Feb 21 02:38:01 PM PST 24 |
| Peak memory | 205752 kb |
| Host | smart-6ff249ec-c22b-4789-9f21-745e9f5fcea6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1859676926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.1859676926 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1434156522 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 107066937783 ps |
| CPU time | 741.74 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:49:45 PM PST 24 |
| Peak memory | 207024 kb |
| Host | smart-dcda1f17-07e6-429f-b3e3-234a4aabe60b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1434156522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.1434156522 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1399136595 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 278392854 ps |
| CPU time | 11.99 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:35 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-c4adefdc-104d-4cdc-ad0f-c8b5d00c4445 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1399136595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1399136595 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.502981215 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 138824970 ps |
| CPU time | 4.47 seconds |
| Started | Feb 21 02:37:21 PM PST 24 |
| Finished | Feb 21 02:37:27 PM PST 24 |
| Peak memory | 203024 kb |
| Host | smart-2f78e5cd-6245-4841-bf95-e8e6d94d9e0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=502981215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.502981215 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.2687276640 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 191697306 ps |
| CPU time | 31.49 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:55 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-7c3cce16-f227-41cb-a968-f100a1d66f4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2687276640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2687276640 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1680734204 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 37710266853 ps |
| CPU time | 163.83 seconds |
| Started | Feb 21 02:37:24 PM PST 24 |
| Finished | Feb 21 02:40:09 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-917bfc1b-ca70-49ac-a226-8f180b4c7ce5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680734204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1680734204 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.4020747842 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 31068940037 ps |
| CPU time | 166.15 seconds |
| Started | Feb 21 02:37:28 PM PST 24 |
| Finished | Feb 21 02:40:15 PM PST 24 |
| Peak memory | 211280 kb |
| Host | smart-eb2c402c-c5fa-4454-b2ea-1e59dd39ad77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4020747842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.4020747842 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3846223854 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 277207539 ps |
| CPU time | 20.18 seconds |
| Started | Feb 21 02:37:24 PM PST 24 |
| Finished | Feb 21 02:37:45 PM PST 24 |
| Peak memory | 204320 kb |
| Host | smart-3374782f-1663-4928-bd8f-3a3e40d55ecf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846223854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3846223854 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.3003781412 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 903264105 ps |
| CPU time | 10.29 seconds |
| Started | Feb 21 02:37:21 PM PST 24 |
| Finished | Feb 21 02:37:33 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-db42782d-fc15-4897-9594-908fbeb01dea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3003781412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3003781412 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.2009509282 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 42067671 ps |
| CPU time | 2.55 seconds |
| Started | Feb 21 02:37:20 PM PST 24 |
| Finished | Feb 21 02:37:24 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-cf9d0f14-18ce-4e8b-80b7-9692a1105108 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2009509282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2009509282 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1718926410 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 6284676930 ps |
| CPU time | 34.68 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:38:02 PM PST 24 |
| Peak memory | 202884 kb |
| Host | smart-3f7b693e-a6f6-401d-8b2e-2e871268f448 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718926410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1718926410 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3332359991 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 12263218685 ps |
| CPU time | 38.57 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:38:02 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-96183282-426b-4590-910b-34f7beb64b28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3332359991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3332359991 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.4107779498 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 41108224 ps |
| CPU time | 2.64 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:26 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-2e06bc03-92ae-4677-acb8-a87d9f7172ca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107779498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.4107779498 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.2748769904 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 546521150 ps |
| CPU time | 44.69 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:38:09 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-5282e81f-d206-49e0-ba8e-57dab8a59c94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2748769904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2748769904 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3628648824 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 26190349121 ps |
| CPU time | 134.12 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:39:41 PM PST 24 |
| Peak memory | 206644 kb |
| Host | smart-89b581e1-1e35-4b26-97d5-9b154dc313fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3628648824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3628648824 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1082269839 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 1294795499 ps |
| CPU time | 428.98 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:44:32 PM PST 24 |
| Peak memory | 210336 kb |
| Host | smart-b106797e-2154-40f0-a7c2-f3a5c66bfff9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1082269839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.1082269839 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.874167182 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1863606353 ps |
| CPU time | 381.18 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:43:47 PM PST 24 |
| Peak memory | 219448 kb |
| Host | smart-0b0cef67-f9ba-4741-b4fe-dccd3bca0445 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=874167182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.874167182 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2494782386 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 979002105 ps |
| CPU time | 7.78 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:37:35 PM PST 24 |
| Peak memory | 204408 kb |
| Host | smart-6dc0315c-2341-4116-bae3-30318b76e094 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2494782386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2494782386 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.2929629303 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1208253440 ps |
| CPU time | 45.31 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:38:10 PM PST 24 |
| Peak memory | 204416 kb |
| Host | smart-4ddaeaa9-e896-4d57-8c14-2ecfeccda7f5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2929629303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.2929629303 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2574339545 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 135024643616 ps |
| CPU time | 514.75 seconds |
| Started | Feb 21 02:37:24 PM PST 24 |
| Finished | Feb 21 02:46:00 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-1fcb5fde-ecf4-4514-876d-ac5bff85f60d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2574339545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.2574339545 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.4055351229 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1618218856 ps |
| CPU time | 29.22 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:55 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-984cff37-88a6-4609-b71e-1e38b50278c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4055351229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.4055351229 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.2200139616 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 448579400 ps |
| CPU time | 17.11 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:37:42 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-b7a2430a-6ff7-49d8-83a1-a7b27065b0db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2200139616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2200139616 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.2462398830 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 30326606 ps |
| CPU time | 3.89 seconds |
| Started | Feb 21 02:37:21 PM PST 24 |
| Finished | Feb 21 02:37:26 PM PST 24 |
| Peak memory | 203616 kb |
| Host | smart-06bf15a3-fd46-4354-aff3-271fc8c2e5b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2462398830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.2462398830 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1502334838 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 41262394678 ps |
| CPU time | 204.77 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:40:50 PM PST 24 |
| Peak memory | 204412 kb |
| Host | smart-19c8fc22-03db-494d-90a0-427bb601ff0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502334838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1502334838 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.2134650057 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 201815798002 ps |
| CPU time | 421.78 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:44:30 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-b184deff-3a8a-4305-a01c-d607895be48b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2134650057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2134650057 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.2143705727 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 66131145 ps |
| CPU time | 8.18 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:31 PM PST 24 |
| Peak memory | 211240 kb |
| Host | smart-e3daff13-7d0c-42e1-bd47-285c7a141969 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143705727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.2143705727 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.3987718950 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 969963598 ps |
| CPU time | 5.16 seconds |
| Started | Feb 21 02:37:28 PM PST 24 |
| Finished | Feb 21 02:37:34 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-2105f033-e2bb-4c0b-9fac-e71e16a426fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3987718950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3987718950 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.1400222523 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 40936503 ps |
| CPU time | 2.27 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:28 PM PST 24 |
| Peak memory | 202988 kb |
| Host | smart-cc70574e-42c3-4c0a-8483-68cebe3bf907 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1400222523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1400222523 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.35947890 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 6873399714 ps |
| CPU time | 30.44 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:56 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-fc668e12-cbb6-45e3-8862-9c5cd093b2fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=35947890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.35947890 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.1916598726 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 5234285817 ps |
| CPU time | 37.1 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:38:05 PM PST 24 |
| Peak memory | 203184 kb |
| Host | smart-9c411686-4484-47f2-af0d-4ea1b9a420dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1916598726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1916598726 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3176727259 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 40327565 ps |
| CPU time | 2.69 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:37:27 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-05cb381c-df65-4522-818c-c7bdaaca708d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176727259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3176727259 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.897938954 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 9173210551 ps |
| CPU time | 159.93 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:40:07 PM PST 24 |
| Peak memory | 211372 kb |
| Host | smart-035f99c4-ac5a-4cf7-9f77-4f65171db86a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=897938954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.897938954 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2133939620 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 28183916762 ps |
| CPU time | 250.57 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:41:36 PM PST 24 |
| Peak memory | 209236 kb |
| Host | smart-d694f33e-51d9-4df8-8d9e-a9e988967061 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2133939620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2133939620 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.683912002 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 268995000 ps |
| CPU time | 104.12 seconds |
| Started | Feb 21 02:37:28 PM PST 24 |
| Finished | Feb 21 02:39:13 PM PST 24 |
| Peak memory | 207884 kb |
| Host | smart-219fb82a-77cb-469d-b972-d2355fa0e29e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=683912002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand _reset.683912002 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.903806275 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 646502089 ps |
| CPU time | 53.21 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:38:18 PM PST 24 |
| Peak memory | 206208 kb |
| Host | smart-c997257b-ec0f-44ef-b0c2-4e5bf8b489e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=903806275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res et_error.903806275 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.1387893507 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 800779268 ps |
| CPU time | 14.66 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:37:39 PM PST 24 |
| Peak memory | 204432 kb |
| Host | smart-cea20c7f-86d6-4614-8f8d-8b8b2577f39d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1387893507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1387893507 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.2883823241 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 190477172 ps |
| CPU time | 8.75 seconds |
| Started | Feb 21 02:37:24 PM PST 24 |
| Finished | Feb 21 02:37:33 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-17a4f02c-7751-4165-8eb2-53dd4c62a12f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2883823241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2883823241 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.1074925419 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 34760702915 ps |
| CPU time | 196.86 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:40:41 PM PST 24 |
| Peak memory | 205852 kb |
| Host | smart-c772df2d-5f45-4b1c-b9a9-7a6b705df4bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1074925419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.1074925419 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.292589156 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 130879663 ps |
| CPU time | 2.39 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:37:30 PM PST 24 |
| Peak memory | 203032 kb |
| Host | smart-751804ec-6253-491c-a227-4b4c4b2bf791 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=292589156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.292589156 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.1708506259 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 297968914 ps |
| CPU time | 28 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:37:51 PM PST 24 |
| Peak memory | 202996 kb |
| Host | smart-6c2ba421-315b-4f98-abb5-2b8abc08c124 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1708506259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1708506259 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.3715316990 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 507698685 ps |
| CPU time | 16.87 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:40 PM PST 24 |
| Peak memory | 211228 kb |
| Host | smart-1b7a2fcc-4a49-43bf-96fc-88b085ece063 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3715316990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.3715316990 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1522841000 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 34152105745 ps |
| CPU time | 99.29 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:39:07 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-3bed87f5-e026-4f08-9701-55c4e44dcbd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522841000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1522841000 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.154031805 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 4711971614 ps |
| CPU time | 41.35 seconds |
| Started | Feb 21 02:37:24 PM PST 24 |
| Finished | Feb 21 02:38:06 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-afa5ce53-ebd5-4673-bd6d-95229933578e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=154031805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.154031805 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.936675524 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1228298039 ps |
| CPU time | 31.05 seconds |
| Started | Feb 21 02:37:28 PM PST 24 |
| Finished | Feb 21 02:38:00 PM PST 24 |
| Peak memory | 204120 kb |
| Host | smart-eceec33e-456d-4f96-a98e-3ffa0d58dd3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936675524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.936675524 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.3444580590 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 888695220 ps |
| CPU time | 4.19 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:30 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-28c3a1e3-efb4-4804-9c39-9e0f2a617e58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3444580590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3444580590 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.1467064744 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 31126962 ps |
| CPU time | 2.47 seconds |
| Started | Feb 21 02:37:23 PM PST 24 |
| Finished | Feb 21 02:37:26 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-d5a5159b-f3d4-41c3-830a-4ad06e389d4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1467064744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1467064744 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2280130198 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 9875532282 ps |
| CPU time | 34.51 seconds |
| Started | Feb 21 02:37:28 PM PST 24 |
| Finished | Feb 21 02:38:03 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-2ed98d1d-c473-4480-a832-e77962e7d37f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280130198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2280130198 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.4259556074 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 3614878035 ps |
| CPU time | 27.41 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:51 PM PST 24 |
| Peak memory | 203356 kb |
| Host | smart-84e2518c-406b-4e6e-95ab-eca7b18d0f94 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4259556074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4259556074 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3981358200 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 26471643 ps |
| CPU time | 2.25 seconds |
| Started | Feb 21 02:37:24 PM PST 24 |
| Finished | Feb 21 02:37:27 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-4c014f91-0000-4844-ba9f-01ffa7d4602e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981358200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3981358200 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.699605875 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 670621969 ps |
| CPU time | 66.5 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:38:34 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-d5b37f30-b427-472e-bf62-2e473524425c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=699605875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.699605875 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3718435225 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 961236206 ps |
| CPU time | 68.44 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:38:36 PM PST 24 |
| Peak memory | 205596 kb |
| Host | smart-41ee8119-c4c0-4730-9595-3d8e2b781240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3718435225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3718435225 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1088660852 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 830299720 ps |
| CPU time | 131.26 seconds |
| Started | Feb 21 02:37:24 PM PST 24 |
| Finished | Feb 21 02:39:36 PM PST 24 |
| Peak memory | 209596 kb |
| Host | smart-d3320592-2651-4037-bef1-7364659db90b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1088660852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.1088660852 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2642874645 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1153215580 ps |
| CPU time | 8.08 seconds |
| Started | Feb 21 02:37:25 PM PST 24 |
| Finished | Feb 21 02:37:34 PM PST 24 |
| Peak memory | 204468 kb |
| Host | smart-d55f552a-9718-4bbc-8aec-16a200697995 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2642874645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2642874645 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.652526362 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2860832504 ps |
| CPU time | 45.63 seconds |
| Started | Feb 21 02:37:32 PM PST 24 |
| Finished | Feb 21 02:38:19 PM PST 24 |
| Peak memory | 211268 kb |
| Host | smart-4a7a97a3-a981-45de-bd9a-8b7e851d5c86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=652526362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.652526362 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3299212264 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 24527844723 ps |
| CPU time | 127.84 seconds |
| Started | Feb 21 02:37:34 PM PST 24 |
| Finished | Feb 21 02:39:43 PM PST 24 |
| Peak memory | 205304 kb |
| Host | smart-72fcc5bc-06c9-4cc8-af1d-324cb31def8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3299212264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.3299212264 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.4046470136 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 152906450 ps |
| CPU time | 11.75 seconds |
| Started | Feb 21 02:37:32 PM PST 24 |
| Finished | Feb 21 02:37:45 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-5c173c5d-f2f5-4ace-a325-d04d7fece45e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4046470136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.4046470136 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.4046485539 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 595496290 ps |
| CPU time | 23.97 seconds |
| Started | Feb 21 02:37:33 PM PST 24 |
| Finished | Feb 21 02:37:58 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-1861a6a1-5989-4e55-8b39-25f72108dfad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4046485539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.4046485539 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.2831839997 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 439701266 ps |
| CPU time | 17.05 seconds |
| Started | Feb 21 02:37:40 PM PST 24 |
| Finished | Feb 21 02:37:58 PM PST 24 |
| Peak memory | 204200 kb |
| Host | smart-4b516ebc-fe3f-40e6-8839-7f514c360316 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2831839997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2831839997 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.1738137473 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 166788554927 ps |
| CPU time | 233.01 seconds |
| Started | Feb 21 02:37:35 PM PST 24 |
| Finished | Feb 21 02:41:29 PM PST 24 |
| Peak memory | 211552 kb |
| Host | smart-0b9f1426-3d92-4391-b63a-e81d4574db44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738137473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1738137473 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1265652890 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 9852514540 ps |
| CPU time | 49.38 seconds |
| Started | Feb 21 02:37:36 PM PST 24 |
| Finished | Feb 21 02:38:26 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-0b5e2534-ca29-43be-99c3-09f21c9e3fb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1265652890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1265652890 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.2120051924 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 198670302 ps |
| CPU time | 19.96 seconds |
| Started | Feb 21 02:37:38 PM PST 24 |
| Finished | Feb 21 02:37:59 PM PST 24 |
| Peak memory | 211468 kb |
| Host | smart-f15f3731-ca9d-483d-8d73-c68d4202c4d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120051924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2120051924 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.1403274968 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 409234960 ps |
| CPU time | 16.97 seconds |
| Started | Feb 21 02:37:33 PM PST 24 |
| Finished | Feb 21 02:37:51 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-9b1d48b2-5e7d-4632-b3ce-5661a2af58f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1403274968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1403274968 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.2049529076 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 288901589 ps |
| CPU time | 3.45 seconds |
| Started | Feb 21 02:37:27 PM PST 24 |
| Finished | Feb 21 02:37:31 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-e659a28e-0b08-45d6-8a3c-61b941abfbcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2049529076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2049529076 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2868512605 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 6640668756 ps |
| CPU time | 32.15 seconds |
| Started | Feb 21 02:37:24 PM PST 24 |
| Finished | Feb 21 02:37:57 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-122b0e63-5284-4f03-a9a2-54cdf4b8da1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868512605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2868512605 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2811019709 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3671810670 ps |
| CPU time | 30.84 seconds |
| Started | Feb 21 02:37:31 PM PST 24 |
| Finished | Feb 21 02:38:03 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-b898e63a-9102-4efe-9284-7c07f0f8dbc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2811019709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2811019709 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2523775221 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 30639120 ps |
| CPU time | 2.57 seconds |
| Started | Feb 21 02:37:22 PM PST 24 |
| Finished | Feb 21 02:37:26 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-ddc2a945-1d1c-40d9-8cc5-3ae51a77bcae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523775221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2523775221 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.3491895269 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2966966688 ps |
| CPU time | 72.87 seconds |
| Started | Feb 21 02:37:34 PM PST 24 |
| Finished | Feb 21 02:38:47 PM PST 24 |
| Peak memory | 211256 kb |
| Host | smart-db67553d-ffe7-47a9-9910-554edae51a48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3491895269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3491895269 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3907871001 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 6036997435 ps |
| CPU time | 163.27 seconds |
| Started | Feb 21 02:37:37 PM PST 24 |
| Finished | Feb 21 02:40:21 PM PST 24 |
| Peak memory | 207588 kb |
| Host | smart-9ccbcc81-1094-4aa5-bb0e-865ca1eb5962 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3907871001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3907871001 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2099170917 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 841850203 ps |
| CPU time | 226.66 seconds |
| Started | Feb 21 02:37:38 PM PST 24 |
| Finished | Feb 21 02:41:25 PM PST 24 |
| Peak memory | 208564 kb |
| Host | smart-4fba8039-7db6-49fd-b102-647f0a4d4e59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2099170917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.2099170917 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.700604860 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1246203749 ps |
| CPU time | 207.63 seconds |
| Started | Feb 21 02:37:35 PM PST 24 |
| Finished | Feb 21 02:41:04 PM PST 24 |
| Peak memory | 211244 kb |
| Host | smart-a4b9a144-50fc-4b49-9fdb-7baef34529c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=700604860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res et_error.700604860 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.1436017563 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2098604764 ps |
| CPU time | 27.47 seconds |
| Started | Feb 21 02:37:35 PM PST 24 |
| Finished | Feb 21 02:38:03 PM PST 24 |
| Peak memory | 211240 kb |
| Host | smart-c9a023dd-de83-4e2c-a3c1-fef8bad46cbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1436017563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1436017563 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2070694960 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 157969508 ps |
| CPU time | 7.5 seconds |
| Started | Feb 21 02:35:53 PM PST 24 |
| Finished | Feb 21 02:36:01 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-8746fb1f-c8f4-487c-9f0d-23ddfc922051 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2070694960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2070694960 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3768178748 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 106504676196 ps |
| CPU time | 355.73 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:41:53 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-e4c083d9-2f61-4488-8a35-fd2088d5bcb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3768178748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.3768178748 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3924591517 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 712262521 ps |
| CPU time | 21.92 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:22 PM PST 24 |
| Peak memory | 203308 kb |
| Host | smart-4d95bfe8-ac35-443a-a87c-b2ad43500cf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3924591517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3924591517 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.2272464185 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 330105984 ps |
| CPU time | 8.11 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:05 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-c9d340db-70cb-46ab-87eb-4614d460b2cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2272464185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2272464185 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.2580803997 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 986904804 ps |
| CPU time | 33.44 seconds |
| Started | Feb 21 02:35:53 PM PST 24 |
| Finished | Feb 21 02:36:27 PM PST 24 |
| Peak memory | 204088 kb |
| Host | smart-7d6207ca-f558-47bd-8f42-f2b0d219f750 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2580803997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2580803997 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2123218927 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 54136257975 ps |
| CPU time | 145.26 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:38:24 PM PST 24 |
| Peak memory | 211248 kb |
| Host | smart-9c046000-749b-4416-a669-35fecf6950f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123218927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2123218927 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1167471353 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 13971866578 ps |
| CPU time | 131.12 seconds |
| Started | Feb 21 02:36:02 PM PST 24 |
| Finished | Feb 21 02:38:17 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-420eef8a-a4cc-492b-9954-0aa3938e8a2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1167471353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1167471353 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2978337239 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 210453273 ps |
| CPU time | 29.09 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:36:33 PM PST 24 |
| Peak memory | 204600 kb |
| Host | smart-d15d3b30-14ad-451e-b8d9-854dfe139914 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978337239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2978337239 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.3539867520 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 1343068288 ps |
| CPU time | 23.8 seconds |
| Started | Feb 21 02:36:27 PM PST 24 |
| Finished | Feb 21 02:36:51 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-2f1eb577-f969-4133-8bd0-499bdcdc5af4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3539867520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3539867520 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.367923761 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 38958102 ps |
| CPU time | 2.83 seconds |
| Started | Feb 21 02:35:49 PM PST 24 |
| Finished | Feb 21 02:35:53 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-265f8ec0-2978-4d53-a8ce-eb5e25bebc70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=367923761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.367923761 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1446240035 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 20110096038 ps |
| CPU time | 34.7 seconds |
| Started | Feb 21 02:35:39 PM PST 24 |
| Finished | Feb 21 02:36:14 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-3648ac93-e34b-467e-a6a6-a24dda5841d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446240035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1446240035 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3621598334 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 17936923031 ps |
| CPU time | 47.18 seconds |
| Started | Feb 21 02:35:41 PM PST 24 |
| Finished | Feb 21 02:36:29 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-dc638293-5e25-4b26-996d-f0f19d66cc70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3621598334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3621598334 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.223756389 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 39066188 ps |
| CPU time | 2.71 seconds |
| Started | Feb 21 02:35:38 PM PST 24 |
| Finished | Feb 21 02:35:42 PM PST 24 |
| Peak memory | 202904 kb |
| Host | smart-faadeb9f-1b63-4f82-a3d9-572f0a0c708c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223756389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.223756389 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.798163000 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2732527287 ps |
| CPU time | 51.39 seconds |
| Started | Feb 21 02:35:53 PM PST 24 |
| Finished | Feb 21 02:36:45 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-b563cbcf-5823-4d62-b3f1-a89cfa8f3a47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=798163000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.798163000 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.679661553 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 22728943617 ps |
| CPU time | 142.66 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:38:21 PM PST 24 |
| Peak memory | 205912 kb |
| Host | smart-252cf5e1-5721-4fd9-a571-4ea25f71189d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=679661553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.679661553 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.469752462 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1886777268 ps |
| CPU time | 224.45 seconds |
| Started | Feb 21 02:35:51 PM PST 24 |
| Finished | Feb 21 02:39:36 PM PST 24 |
| Peak memory | 209828 kb |
| Host | smart-9867d0ca-b9fc-468a-a3b0-52ad7182a18a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=469752462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_ reset.469752462 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1818438689 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 6270129056 ps |
| CPU time | 277.73 seconds |
| Started | Feb 21 02:36:02 PM PST 24 |
| Finished | Feb 21 02:40:43 PM PST 24 |
| Peak memory | 210404 kb |
| Host | smart-a3032653-4666-4508-a3e2-669e8a416462 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1818438689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.1818438689 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.36319464 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 121349484 ps |
| CPU time | 13.1 seconds |
| Started | Feb 21 02:35:48 PM PST 24 |
| Finished | Feb 21 02:36:04 PM PST 24 |
| Peak memory | 204276 kb |
| Host | smart-931fe930-a9e1-4ca3-aebe-0c6df5b427a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=36319464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.36319464 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.3195757793 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3611433845 ps |
| CPU time | 72.34 seconds |
| Started | Feb 21 02:37:32 PM PST 24 |
| Finished | Feb 21 02:38:45 PM PST 24 |
| Peak memory | 206328 kb |
| Host | smart-067456ff-cd89-48fd-8a4a-34bb1a139698 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3195757793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3195757793 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3951350345 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 26913669147 ps |
| CPU time | 253.63 seconds |
| Started | Feb 21 02:37:35 PM PST 24 |
| Finished | Feb 21 02:41:49 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-63a49234-ae2a-4417-94ca-e5a88f9d4837 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3951350345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.3951350345 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3325912173 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 27766383 ps |
| CPU time | 2.1 seconds |
| Started | Feb 21 02:37:41 PM PST 24 |
| Finished | Feb 21 02:37:43 PM PST 24 |
| Peak memory | 203284 kb |
| Host | smart-28629d72-0924-43cf-8629-a330a3426200 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3325912173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3325912173 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.2991639676 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 321285468 ps |
| CPU time | 18.39 seconds |
| Started | Feb 21 02:37:38 PM PST 24 |
| Finished | Feb 21 02:37:57 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-cfa6b9e0-446b-429b-b38a-2dac4ce36023 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2991639676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2991639676 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.137884982 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 216151715 ps |
| CPU time | 14.54 seconds |
| Started | Feb 21 02:37:32 PM PST 24 |
| Finished | Feb 21 02:37:47 PM PST 24 |
| Peak memory | 204192 kb |
| Host | smart-6697cc26-0324-44e2-8cc5-7f369db198f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=137884982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.137884982 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2196367978 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 97413446459 ps |
| CPU time | 248.42 seconds |
| Started | Feb 21 02:37:36 PM PST 24 |
| Finished | Feb 21 02:41:45 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-72e7c818-4785-4a5b-8694-6e7728b62971 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196367978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2196367978 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3115474059 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 98406524459 ps |
| CPU time | 251.03 seconds |
| Started | Feb 21 02:37:33 PM PST 24 |
| Finished | Feb 21 02:41:45 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-9b4e367b-be94-4a14-9c9d-922fb6cc62f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3115474059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3115474059 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.2444040664 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 248133163 ps |
| CPU time | 19.17 seconds |
| Started | Feb 21 02:37:32 PM PST 24 |
| Finished | Feb 21 02:37:52 PM PST 24 |
| Peak memory | 204148 kb |
| Host | smart-930488db-6384-430b-8fec-59ce99f79d2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444040664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2444040664 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.2260188206 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 145104573 ps |
| CPU time | 3.15 seconds |
| Started | Feb 21 02:37:32 PM PST 24 |
| Finished | Feb 21 02:37:36 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-d1df3a59-d7e8-43de-97ec-ecb755d14a3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2260188206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2260188206 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.2128883340 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 137520502 ps |
| CPU time | 3.01 seconds |
| Started | Feb 21 02:37:35 PM PST 24 |
| Finished | Feb 21 02:37:38 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-5199ca43-dbe7-49fb-b563-6f90010f93a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2128883340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2128883340 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1346502810 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 11740464772 ps |
| CPU time | 31.24 seconds |
| Started | Feb 21 02:37:35 PM PST 24 |
| Finished | Feb 21 02:38:07 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-e3d90163-14c3-4990-8cae-eededd191579 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346502810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1346502810 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3695659321 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 2536988206 ps |
| CPU time | 23.32 seconds |
| Started | Feb 21 02:37:33 PM PST 24 |
| Finished | Feb 21 02:37:57 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-f1df5fa4-9356-4667-97af-e433e2e8e1d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3695659321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3695659321 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.1868643233 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 39789239 ps |
| CPU time | 2.47 seconds |
| Started | Feb 21 02:37:31 PM PST 24 |
| Finished | Feb 21 02:37:34 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-fd902ac9-5d2a-4bd7-86b3-08ac1a4c03c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868643233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.1868643233 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.698440291 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1878780329 ps |
| CPU time | 37.72 seconds |
| Started | Feb 21 02:37:43 PM PST 24 |
| Finished | Feb 21 02:38:23 PM PST 24 |
| Peak memory | 204992 kb |
| Host | smart-d004179a-1693-4c9d-9dae-80f16af56dfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=698440291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.698440291 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3175796676 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 774404064 ps |
| CPU time | 85.84 seconds |
| Started | Feb 21 02:37:42 PM PST 24 |
| Finished | Feb 21 02:39:09 PM PST 24 |
| Peak memory | 211272 kb |
| Host | smart-a83075e5-8479-451e-b7d1-a2593edbdc8b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3175796676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3175796676 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4293807639 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 460889625 ps |
| CPU time | 147.2 seconds |
| Started | Feb 21 02:37:40 PM PST 24 |
| Finished | Feb 21 02:40:08 PM PST 24 |
| Peak memory | 207820 kb |
| Host | smart-7ae3bae5-0cc9-45e6-b90d-04676e63bf7e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4293807639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.4293807639 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.3362676241 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 788557938 ps |
| CPU time | 165.07 seconds |
| Started | Feb 21 02:37:48 PM PST 24 |
| Finished | Feb 21 02:40:35 PM PST 24 |
| Peak memory | 210700 kb |
| Host | smart-36c5068c-2875-4132-a038-8251cc117890 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3362676241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.3362676241 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.4030185863 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 135903525 ps |
| CPU time | 4.01 seconds |
| Started | Feb 21 02:37:38 PM PST 24 |
| Finished | Feb 21 02:37:43 PM PST 24 |
| Peak memory | 204148 kb |
| Host | smart-354e9927-9a42-45a7-b972-cec21e2e9fbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4030185863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4030185863 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.2604270926 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 261971782 ps |
| CPU time | 19.4 seconds |
| Started | Feb 21 02:37:41 PM PST 24 |
| Finished | Feb 21 02:38:01 PM PST 24 |
| Peak memory | 203524 kb |
| Host | smart-e998850b-d56b-42b8-b7b9-acdc9e2f8feb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2604270926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2604270926 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1668095900 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 53847529296 ps |
| CPU time | 494.27 seconds |
| Started | Feb 21 02:37:47 PM PST 24 |
| Finished | Feb 21 02:46:03 PM PST 24 |
| Peak memory | 211300 kb |
| Host | smart-0ce82b26-ea9b-4b69-b7b2-1854268c1710 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1668095900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl ow_rsp.1668095900 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.3191225407 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 361034745 ps |
| CPU time | 12.5 seconds |
| Started | Feb 21 02:37:40 PM PST 24 |
| Finished | Feb 21 02:37:53 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-a6856bb7-fa90-401d-ab0f-a0ee71abb8fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3191225407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3191225407 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.1465663620 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1154730795 ps |
| CPU time | 30.5 seconds |
| Started | Feb 21 02:37:41 PM PST 24 |
| Finished | Feb 21 02:38:12 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-9493da8e-6edb-43de-b882-ab20c37167ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1465663620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1465663620 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.788829454 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 267941025 ps |
| CPU time | 10.51 seconds |
| Started | Feb 21 02:37:41 PM PST 24 |
| Finished | Feb 21 02:37:52 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-304b064c-c92a-469e-a514-7456bd7d33a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=788829454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.788829454 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.1596736359 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 51923810332 ps |
| CPU time | 98.97 seconds |
| Started | Feb 21 02:37:48 PM PST 24 |
| Finished | Feb 21 02:39:29 PM PST 24 |
| Peak memory | 204216 kb |
| Host | smart-3e3fbb67-76a6-40b7-aa72-a807cec2bf3d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596736359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1596736359 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2653289341 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 37804678800 ps |
| CPU time | 181.9 seconds |
| Started | Feb 21 02:37:41 PM PST 24 |
| Finished | Feb 21 02:40:43 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-e8d13670-d1be-41e3-a0c9-cbcec3a9dd4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2653289341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2653289341 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.4073493381 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 133107844 ps |
| CPU time | 3.67 seconds |
| Started | Feb 21 02:37:46 PM PST 24 |
| Finished | Feb 21 02:37:52 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-6a5a7fdc-6c40-49e7-99a8-1a681b32e42e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073493381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.4073493381 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.704462140 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 862630163 ps |
| CPU time | 18.44 seconds |
| Started | Feb 21 02:37:45 PM PST 24 |
| Finished | Feb 21 02:38:07 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-9d79aa03-edfd-4356-8eaf-4263bb80eeba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=704462140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.704462140 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.3397204496 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 558618014 ps |
| CPU time | 3.51 seconds |
| Started | Feb 21 02:37:44 PM PST 24 |
| Finished | Feb 21 02:37:50 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-73dddddb-c367-4d28-bb43-c98e793d4613 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3397204496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3397204496 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3418624373 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4598797008 ps |
| CPU time | 27.87 seconds |
| Started | Feb 21 02:37:42 PM PST 24 |
| Finished | Feb 21 02:38:11 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-0d971310-2f99-47d4-a056-76b17bf51bd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418624373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3418624373 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.1780341347 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3246645816 ps |
| CPU time | 28.48 seconds |
| Started | Feb 21 02:37:42 PM PST 24 |
| Finished | Feb 21 02:38:12 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-4f22da4a-40e1-4b89-a812-d15cb5f7f200 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1780341347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1780341347 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3234537159 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 43658112 ps |
| CPU time | 2.43 seconds |
| Started | Feb 21 02:37:40 PM PST 24 |
| Finished | Feb 21 02:37:42 PM PST 24 |
| Peak memory | 202992 kb |
| Host | smart-e3be262b-3671-49ac-b83c-e54d08eca250 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234537159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3234537159 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1114171239 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 6370273140 ps |
| CPU time | 162.88 seconds |
| Started | Feb 21 02:37:45 PM PST 24 |
| Finished | Feb 21 02:40:30 PM PST 24 |
| Peak memory | 208272 kb |
| Host | smart-a5246383-0377-4a5a-a002-76a6ce772238 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1114171239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1114171239 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2782935246 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1669802058 ps |
| CPU time | 64.54 seconds |
| Started | Feb 21 02:37:40 PM PST 24 |
| Finished | Feb 21 02:38:45 PM PST 24 |
| Peak memory | 205176 kb |
| Host | smart-d04d0a85-c1af-40d5-8e29-10236c02a66c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2782935246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2782935246 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1971809433 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 324553556 ps |
| CPU time | 150.35 seconds |
| Started | Feb 21 02:37:48 PM PST 24 |
| Finished | Feb 21 02:40:20 PM PST 24 |
| Peak memory | 208056 kb |
| Host | smart-54f9e543-1845-46cd-bf52-a3dd12a0f4de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1971809433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1971809433 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.4175133286 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 868021424 ps |
| CPU time | 168.14 seconds |
| Started | Feb 21 02:37:47 PM PST 24 |
| Finished | Feb 21 02:40:37 PM PST 24 |
| Peak memory | 210208 kb |
| Host | smart-41d5a632-32a2-49d3-a53e-d747ed496526 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4175133286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.4175133286 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1903107309 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1395250042 ps |
| CPU time | 34.26 seconds |
| Started | Feb 21 02:37:40 PM PST 24 |
| Finished | Feb 21 02:38:14 PM PST 24 |
| Peak memory | 204192 kb |
| Host | smart-b1eb6918-12d4-4a30-bdbc-10ded5e96509 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1903107309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1903107309 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.4043313902 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 795928532 ps |
| CPU time | 24.4 seconds |
| Started | Feb 21 02:37:57 PM PST 24 |
| Finished | Feb 21 02:38:22 PM PST 24 |
| Peak memory | 211216 kb |
| Host | smart-10fb3c75-429f-49f0-9ca5-20dd148a0bf2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4043313902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.4043313902 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1291814841 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 106160065107 ps |
| CPU time | 604.94 seconds |
| Started | Feb 21 02:38:08 PM PST 24 |
| Finished | Feb 21 02:48:13 PM PST 24 |
| Peak memory | 205556 kb |
| Host | smart-2d1ac735-ada2-4ca4-b496-cb0b089a2434 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1291814841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.1291814841 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.706351996 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2407751844 ps |
| CPU time | 26.46 seconds |
| Started | Feb 21 02:37:53 PM PST 24 |
| Finished | Feb 21 02:38:20 PM PST 24 |
| Peak memory | 203232 kb |
| Host | smart-fa25b478-3a5c-4f2a-b314-9c62b53fbd78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=706351996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.706351996 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.1202932193 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 144526996 ps |
| CPU time | 18.51 seconds |
| Started | Feb 21 02:37:55 PM PST 24 |
| Finished | Feb 21 02:38:13 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-9bc9bc39-00e3-4207-b50c-51b9b254e558 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1202932193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1202932193 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.2532413933 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 78147405 ps |
| CPU time | 3.09 seconds |
| Started | Feb 21 02:38:06 PM PST 24 |
| Finished | Feb 21 02:38:09 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-2eccc882-6c5d-4633-9ca6-1399844b56bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2532413933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2532413933 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.662874952 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 32804189941 ps |
| CPU time | 177.08 seconds |
| Started | Feb 21 02:37:57 PM PST 24 |
| Finished | Feb 21 02:40:54 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-89a2ff49-0569-48d8-ad80-857b63266270 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=662874952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.662874952 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2390950954 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 2852968940 ps |
| CPU time | 12.58 seconds |
| Started | Feb 21 02:37:57 PM PST 24 |
| Finished | Feb 21 02:38:10 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-2694927f-84cb-4074-8b6f-214c188b9420 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2390950954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2390950954 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.986066943 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 113338022 ps |
| CPU time | 13.36 seconds |
| Started | Feb 21 02:37:55 PM PST 24 |
| Finished | Feb 21 02:38:09 PM PST 24 |
| Peak memory | 204236 kb |
| Host | smart-3e241c0a-12af-495e-9d93-774ed63ccaf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986066943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.986066943 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.2340179204 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 352712269 ps |
| CPU time | 6.33 seconds |
| Started | Feb 21 02:37:56 PM PST 24 |
| Finished | Feb 21 02:38:02 PM PST 24 |
| Peak memory | 203316 kb |
| Host | smart-7525a905-c9ac-435d-b584-d138999cdab2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2340179204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2340179204 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.4293065071 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 30866170 ps |
| CPU time | 2.45 seconds |
| Started | Feb 21 02:37:56 PM PST 24 |
| Finished | Feb 21 02:37:59 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-b04eeac9-637a-498c-af2f-68adad90e3da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4293065071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.4293065071 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2946935932 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 6967531998 ps |
| CPU time | 41.12 seconds |
| Started | Feb 21 02:37:59 PM PST 24 |
| Finished | Feb 21 02:38:42 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-400b982f-0792-4598-832d-520eba9f9741 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946935932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2946935932 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2977400501 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 6159171260 ps |
| CPU time | 30.47 seconds |
| Started | Feb 21 02:37:58 PM PST 24 |
| Finished | Feb 21 02:38:29 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-660cecd4-b554-4d86-854c-e12c97e437ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2977400501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2977400501 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1132114657 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 137650873 ps |
| CPU time | 2.43 seconds |
| Started | Feb 21 02:38:02 PM PST 24 |
| Finished | Feb 21 02:38:06 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-5e0602b2-8f3f-48a8-bbe5-c98808aa4881 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132114657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1132114657 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.347255448 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 67374919 ps |
| CPU time | 2.46 seconds |
| Started | Feb 21 02:37:57 PM PST 24 |
| Finished | Feb 21 02:37:59 PM PST 24 |
| Peak memory | 203036 kb |
| Host | smart-8898da37-602a-4804-b11c-becc4a76037d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=347255448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.347255448 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1905489503 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4408757899 ps |
| CPU time | 222.53 seconds |
| Started | Feb 21 02:37:56 PM PST 24 |
| Finished | Feb 21 02:41:39 PM PST 24 |
| Peak memory | 219584 kb |
| Host | smart-e0031e2e-6f88-4c84-a3b8-0edf7d39ef10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1905489503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1905489503 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.1068533361 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 414658342 ps |
| CPU time | 126.61 seconds |
| Started | Feb 21 02:38:00 PM PST 24 |
| Finished | Feb 21 02:40:08 PM PST 24 |
| Peak memory | 207820 kb |
| Host | smart-627956e5-0860-4e73-8b81-72fc00c77fa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1068533361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.1068533361 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.3379137543 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2704761814 ps |
| CPU time | 353.57 seconds |
| Started | Feb 21 02:37:57 PM PST 24 |
| Finished | Feb 21 02:43:51 PM PST 24 |
| Peak memory | 225916 kb |
| Host | smart-bab0b5c4-56ec-446a-bdab-323772f6b09c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3379137543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.3379137543 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.841835333 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1007009915 ps |
| CPU time | 13.07 seconds |
| Started | Feb 21 02:37:59 PM PST 24 |
| Finished | Feb 21 02:38:12 PM PST 24 |
| Peak memory | 204492 kb |
| Host | smart-47771ad9-d1d2-4a1e-a77b-a016db0c677f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=841835333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.841835333 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.764628236 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 172958109 ps |
| CPU time | 15.73 seconds |
| Started | Feb 21 02:37:58 PM PST 24 |
| Finished | Feb 21 02:38:14 PM PST 24 |
| Peak memory | 203732 kb |
| Host | smart-d940f751-c28b-4258-a198-f193a1474ad1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=764628236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.764628236 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2468364594 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 18852234119 ps |
| CPU time | 162.96 seconds |
| Started | Feb 21 02:37:57 PM PST 24 |
| Finished | Feb 21 02:40:40 PM PST 24 |
| Peak memory | 211352 kb |
| Host | smart-e1441d69-a28d-4622-99fe-883a19319d22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2468364594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.2468364594 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.4155853888 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 108560910 ps |
| CPU time | 2.63 seconds |
| Started | Feb 21 02:38:02 PM PST 24 |
| Finished | Feb 21 02:38:06 PM PST 24 |
| Peak memory | 203008 kb |
| Host | smart-9b62e3ac-2cc0-4be8-a247-9cd72051c93c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4155853888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.4155853888 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.3075525918 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2967132486 ps |
| CPU time | 22.38 seconds |
| Started | Feb 21 02:38:06 PM PST 24 |
| Finished | Feb 21 02:38:28 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-942312de-c19f-4a58-afc4-3d5269454138 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3075525918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3075525918 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.1841370769 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 170227401 ps |
| CPU time | 10.42 seconds |
| Started | Feb 21 02:37:55 PM PST 24 |
| Finished | Feb 21 02:38:06 PM PST 24 |
| Peak memory | 211216 kb |
| Host | smart-15c6b935-510d-4e7c-9a1d-e42b41e16915 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1841370769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.1841370769 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.2482591084 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 47225243239 ps |
| CPU time | 185.36 seconds |
| Started | Feb 21 02:38:08 PM PST 24 |
| Finished | Feb 21 02:41:14 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-7f71f73a-1d95-43b9-92e0-72faa8226805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482591084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2482591084 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3821603631 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 34678268992 ps |
| CPU time | 237.35 seconds |
| Started | Feb 21 02:37:56 PM PST 24 |
| Finished | Feb 21 02:41:54 PM PST 24 |
| Peak memory | 204424 kb |
| Host | smart-f4905842-fdd1-4919-92ad-e994ffccaca5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3821603631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3821603631 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.3932694129 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 128975557 ps |
| CPU time | 15.72 seconds |
| Started | Feb 21 02:38:05 PM PST 24 |
| Finished | Feb 21 02:38:21 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-d980c48e-50d9-4b1c-9539-14b8e564cfa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932694129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3932694129 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.4266804822 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1278134251 ps |
| CPU time | 16.39 seconds |
| Started | Feb 21 02:38:04 PM PST 24 |
| Finished | Feb 21 02:38:21 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-7d9df15a-ede8-46af-8920-20b68c3ead9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4266804822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.4266804822 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.237665949 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 80987551 ps |
| CPU time | 2.45 seconds |
| Started | Feb 21 02:37:59 PM PST 24 |
| Finished | Feb 21 02:38:01 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-c7108c2f-5c9b-42df-8db9-bb959349e15c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=237665949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.237665949 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1502618062 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3961375282 ps |
| CPU time | 24.47 seconds |
| Started | Feb 21 02:37:57 PM PST 24 |
| Finished | Feb 21 02:38:21 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-fff74e16-7ecb-493e-9703-316153ace865 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502618062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1502618062 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3935120685 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 10335597877 ps |
| CPU time | 43.29 seconds |
| Started | Feb 21 02:37:54 PM PST 24 |
| Finished | Feb 21 02:38:37 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-05f18f2a-c7ef-4cd9-b05b-f3d93ad75ad6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3935120685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3935120685 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.363356447 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 51067589 ps |
| CPU time | 2.46 seconds |
| Started | Feb 21 02:37:55 PM PST 24 |
| Finished | Feb 21 02:37:58 PM PST 24 |
| Peak memory | 203024 kb |
| Host | smart-b91d8a93-86e9-4b35-8ba4-f9a65a6b74b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363356447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.363356447 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.4050322912 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 5414143196 ps |
| CPU time | 52.23 seconds |
| Started | Feb 21 02:38:02 PM PST 24 |
| Finished | Feb 21 02:38:56 PM PST 24 |
| Peak memory | 204296 kb |
| Host | smart-aeb067a9-bafc-4a26-8c13-e51882fd4f29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4050322912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4050322912 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.4031123653 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 38849885 ps |
| CPU time | 26.64 seconds |
| Started | Feb 21 02:38:08 PM PST 24 |
| Finished | Feb 21 02:38:35 PM PST 24 |
| Peak memory | 205960 kb |
| Host | smart-9335d202-775c-41cd-b92f-89d49ed7adbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4031123653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.4031123653 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2499245063 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2962115499 ps |
| CPU time | 426.42 seconds |
| Started | Feb 21 02:38:04 PM PST 24 |
| Finished | Feb 21 02:45:11 PM PST 24 |
| Peak memory | 219492 kb |
| Host | smart-15479735-ba8f-4d50-a755-19ac8124a49e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2499245063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.2499245063 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2240272769 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 206247142 ps |
| CPU time | 6.23 seconds |
| Started | Feb 21 02:37:55 PM PST 24 |
| Finished | Feb 21 02:38:02 PM PST 24 |
| Peak memory | 211108 kb |
| Host | smart-b89efa44-6eaf-4563-9ee8-8a646794569c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2240272769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2240272769 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.2224080984 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 8647569841 ps |
| CPU time | 59.32 seconds |
| Started | Feb 21 02:37:57 PM PST 24 |
| Finished | Feb 21 02:38:56 PM PST 24 |
| Peak memory | 205880 kb |
| Host | smart-ee6716f0-8df9-4f9c-bbe9-50f2354e7416 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2224080984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2224080984 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3653410081 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 84082967262 ps |
| CPU time | 699.7 seconds |
| Started | Feb 21 02:37:58 PM PST 24 |
| Finished | Feb 21 02:49:38 PM PST 24 |
| Peak memory | 207008 kb |
| Host | smart-1f5af975-0baf-4701-a34f-e1fcc5fa2bde |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3653410081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.3653410081 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2564610015 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1818120994 ps |
| CPU time | 27.03 seconds |
| Started | Feb 21 02:38:07 PM PST 24 |
| Finished | Feb 21 02:38:34 PM PST 24 |
| Peak memory | 203228 kb |
| Host | smart-44edb6ba-83a4-43d8-ad7f-83667334dc5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2564610015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2564610015 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.292215765 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1539816815 ps |
| CPU time | 27.42 seconds |
| Started | Feb 21 02:38:09 PM PST 24 |
| Finished | Feb 21 02:38:37 PM PST 24 |
| Peak memory | 203172 kb |
| Host | smart-b7c6a0ab-aad1-45d8-ac25-bafb10fd3221 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=292215765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.292215765 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.3001756461 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 173281203 ps |
| CPU time | 8.77 seconds |
| Started | Feb 21 02:38:04 PM PST 24 |
| Finished | Feb 21 02:38:13 PM PST 24 |
| Peak memory | 203772 kb |
| Host | smart-07340127-ce96-43a7-b3c8-c38e43645c90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3001756461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3001756461 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.609912637 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 43261226979 ps |
| CPU time | 229.54 seconds |
| Started | Feb 21 02:37:57 PM PST 24 |
| Finished | Feb 21 02:41:47 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-f06246eb-2307-4e74-8518-e56a3cb1f542 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=609912637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.609912637 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.126676017 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 24052383490 ps |
| CPU time | 188.66 seconds |
| Started | Feb 21 02:38:00 PM PST 24 |
| Finished | Feb 21 02:41:10 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-c633ff17-e264-4ad5-865b-7895509552b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=126676017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.126676017 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.1293352577 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 79725726 ps |
| CPU time | 4.18 seconds |
| Started | Feb 21 02:38:05 PM PST 24 |
| Finished | Feb 21 02:38:09 PM PST 24 |
| Peak memory | 203448 kb |
| Host | smart-a8ac43ed-9853-4f1f-9f4e-393ae0b3a0d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293352577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1293352577 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.467476605 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9033438979 ps |
| CPU time | 37.35 seconds |
| Started | Feb 21 02:37:56 PM PST 24 |
| Finished | Feb 21 02:38:34 PM PST 24 |
| Peak memory | 211288 kb |
| Host | smart-ed4abd4d-bc92-4a43-9468-d9d01a74acf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=467476605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.467476605 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.4033128825 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 36629447 ps |
| CPU time | 2.1 seconds |
| Started | Feb 21 02:38:04 PM PST 24 |
| Finished | Feb 21 02:38:07 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-4b41ce12-3c97-4906-8feb-56ea831d1b85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4033128825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.4033128825 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2470221132 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 6549348302 ps |
| CPU time | 36.67 seconds |
| Started | Feb 21 02:38:10 PM PST 24 |
| Finished | Feb 21 02:38:47 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-12ceb1ab-1c83-4e86-a856-9b696e3c3d82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470221132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2470221132 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.512052906 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2666707040 ps |
| CPU time | 25.25 seconds |
| Started | Feb 21 02:38:07 PM PST 24 |
| Finished | Feb 21 02:38:33 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-4fb243fd-e4ad-4a10-af7f-aca5315bb1da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=512052906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.512052906 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.2646978704 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 27651303 ps |
| CPU time | 2.42 seconds |
| Started | Feb 21 02:37:54 PM PST 24 |
| Finished | Feb 21 02:37:57 PM PST 24 |
| Peak memory | 202852 kb |
| Host | smart-5bad7749-7804-4009-9415-c7f441af8fdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646978704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2646978704 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.241286266 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4060526289 ps |
| CPU time | 92.79 seconds |
| Started | Feb 21 02:38:15 PM PST 24 |
| Finished | Feb 21 02:39:48 PM PST 24 |
| Peak memory | 206156 kb |
| Host | smart-6ab39780-171b-48e1-accc-5bba64faa42d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=241286266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.241286266 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3670308826 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2766024365 ps |
| CPU time | 86.81 seconds |
| Started | Feb 21 02:38:10 PM PST 24 |
| Finished | Feb 21 02:39:38 PM PST 24 |
| Peak memory | 204620 kb |
| Host | smart-145941ca-5202-44cc-8929-044598abf369 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3670308826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3670308826 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.2136234182 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 398372541 ps |
| CPU time | 140.72 seconds |
| Started | Feb 21 02:38:14 PM PST 24 |
| Finished | Feb 21 02:40:35 PM PST 24 |
| Peak memory | 207736 kb |
| Host | smart-beb4dd19-2eb6-45c9-b631-017f64309756 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2136234182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.2136234182 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.733263353 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 8030833573 ps |
| CPU time | 273.72 seconds |
| Started | Feb 21 02:38:17 PM PST 24 |
| Finished | Feb 21 02:42:51 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-007403d2-b246-4dab-a170-e262010ed093 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=733263353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_res et_error.733263353 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.1961684461 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 376795734 ps |
| CPU time | 8.27 seconds |
| Started | Feb 21 02:38:16 PM PST 24 |
| Finished | Feb 21 02:38:24 PM PST 24 |
| Peak memory | 204420 kb |
| Host | smart-87912642-330d-4781-9600-45c6d0fbc168 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1961684461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1961684461 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.833184688 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1353720304 ps |
| CPU time | 22.52 seconds |
| Started | Feb 21 02:38:18 PM PST 24 |
| Finished | Feb 21 02:38:41 PM PST 24 |
| Peak memory | 205492 kb |
| Host | smart-41e0fcf6-67d6-437b-8c75-b112c0a9243d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=833184688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.833184688 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2986152866 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 84795810770 ps |
| CPU time | 564.14 seconds |
| Started | Feb 21 02:38:07 PM PST 24 |
| Finished | Feb 21 02:47:32 PM PST 24 |
| Peak memory | 206988 kb |
| Host | smart-c262cae7-f273-477c-bfcc-c10de9a6b07a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2986152866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.2986152866 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2738456315 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 338819812 ps |
| CPU time | 14.25 seconds |
| Started | Feb 21 02:38:19 PM PST 24 |
| Finished | Feb 21 02:38:33 PM PST 24 |
| Peak memory | 202684 kb |
| Host | smart-2f207a35-0913-426c-bac8-f36d7e3bd1c1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2738456315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2738456315 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.347742310 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 200688235 ps |
| CPU time | 21.54 seconds |
| Started | Feb 21 02:38:13 PM PST 24 |
| Finished | Feb 21 02:38:35 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-0cfcd5b6-d079-405a-b7f9-c744ea455261 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=347742310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.347742310 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.2073713120 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 667301405 ps |
| CPU time | 8.51 seconds |
| Started | Feb 21 02:38:09 PM PST 24 |
| Finished | Feb 21 02:38:18 PM PST 24 |
| Peak memory | 204208 kb |
| Host | smart-629b0780-0b0a-4441-99a0-4ff8a6ed560b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2073713120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2073713120 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3920749899 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 32559722996 ps |
| CPU time | 119.51 seconds |
| Started | Feb 21 02:38:19 PM PST 24 |
| Finished | Feb 21 02:40:19 PM PST 24 |
| Peak memory | 210724 kb |
| Host | smart-5bf40b4e-a45b-47d2-87ed-31231faa3865 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920749899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3920749899 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2960074830 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 52305912204 ps |
| CPU time | 268.57 seconds |
| Started | Feb 21 02:38:14 PM PST 24 |
| Finished | Feb 21 02:42:43 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-691ee208-748c-42a2-9ac5-6a36f44c37cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2960074830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2960074830 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.3605036253 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 486657184 ps |
| CPU time | 13.26 seconds |
| Started | Feb 21 02:38:17 PM PST 24 |
| Finished | Feb 21 02:38:31 PM PST 24 |
| Peak memory | 204120 kb |
| Host | smart-3dac5f5d-c525-4f3d-98f4-50e7faba8891 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605036253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3605036253 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.764218917 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 206451835 ps |
| CPU time | 5.4 seconds |
| Started | Feb 21 02:38:09 PM PST 24 |
| Finished | Feb 21 02:38:15 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-e6ff31e5-b2f4-4a37-812b-d59f2f536c0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=764218917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.764218917 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.1991911810 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 76465985 ps |
| CPU time | 2.14 seconds |
| Started | Feb 21 02:38:15 PM PST 24 |
| Finished | Feb 21 02:38:18 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-62cae7e2-3de7-41b4-9169-cc2c4dd56977 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1991911810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1991911810 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.4053545943 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 12334535940 ps |
| CPU time | 36.66 seconds |
| Started | Feb 21 02:38:12 PM PST 24 |
| Finished | Feb 21 02:38:49 PM PST 24 |
| Peak memory | 203036 kb |
| Host | smart-f8784235-aabe-41f5-8306-9e835e9e4977 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053545943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.4053545943 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2334656637 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 4828394916 ps |
| CPU time | 33.65 seconds |
| Started | Feb 21 02:38:16 PM PST 24 |
| Finished | Feb 21 02:38:50 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-6759107d-ad31-48ec-b3db-0386dad2179c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2334656637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2334656637 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4061677056 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 76304743 ps |
| CPU time | 2.44 seconds |
| Started | Feb 21 02:38:08 PM PST 24 |
| Finished | Feb 21 02:38:11 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-53118cd6-e932-45be-a183-2af418479dab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061677056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.4061677056 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.2579870476 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 14510698810 ps |
| CPU time | 196.85 seconds |
| Started | Feb 21 02:38:09 PM PST 24 |
| Finished | Feb 21 02:41:26 PM PST 24 |
| Peak memory | 208428 kb |
| Host | smart-61688d6a-8ade-4d86-9c01-af246ab6fb7b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2579870476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2579870476 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.4197767273 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 5016461711 ps |
| CPU time | 117.39 seconds |
| Started | Feb 21 02:38:14 PM PST 24 |
| Finished | Feb 21 02:40:12 PM PST 24 |
| Peak memory | 207328 kb |
| Host | smart-2f260a48-4882-4bd7-ab79-221e08b78560 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4197767273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.4197767273 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1221700079 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 821434978 ps |
| CPU time | 265.89 seconds |
| Started | Feb 21 02:38:17 PM PST 24 |
| Finished | Feb 21 02:42:44 PM PST 24 |
| Peak memory | 208228 kb |
| Host | smart-285478c7-c6cd-44a5-8440-691f2c38a29a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1221700079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.1221700079 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1940490575 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 145779209 ps |
| CPU time | 36.92 seconds |
| Started | Feb 21 02:38:09 PM PST 24 |
| Finished | Feb 21 02:38:46 PM PST 24 |
| Peak memory | 203956 kb |
| Host | smart-7d8cd5b5-c9c6-49d4-b39a-0a1edae82039 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1940490575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.1940490575 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3678577948 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1245529659 ps |
| CPU time | 33.36 seconds |
| Started | Feb 21 02:38:09 PM PST 24 |
| Finished | Feb 21 02:38:42 PM PST 24 |
| Peak memory | 204752 kb |
| Host | smart-65f3fed7-8903-4cdb-853d-caad5540ead8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3678577948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3678577948 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.1203347580 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1298618484 ps |
| CPU time | 29.98 seconds |
| Started | Feb 21 02:38:25 PM PST 24 |
| Finished | Feb 21 02:38:55 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-4430537b-9b72-4ea1-98e9-bc87ec8883b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1203347580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1203347580 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2160285248 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 320372919216 ps |
| CPU time | 597.77 seconds |
| Started | Feb 21 02:38:16 PM PST 24 |
| Finished | Feb 21 02:48:14 PM PST 24 |
| Peak memory | 211376 kb |
| Host | smart-888ef8ba-bedc-47ee-ba6c-c02180a93a2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2160285248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.2160285248 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3026233432 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1189366258 ps |
| CPU time | 13.62 seconds |
| Started | Feb 21 02:38:17 PM PST 24 |
| Finished | Feb 21 02:38:31 PM PST 24 |
| Peak memory | 203156 kb |
| Host | smart-d3066a63-93dd-4b22-af2b-6d918ff394d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3026233432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3026233432 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.1217781068 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1794048364 ps |
| CPU time | 36.07 seconds |
| Started | Feb 21 02:38:16 PM PST 24 |
| Finished | Feb 21 02:38:52 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-f2777740-1c6a-4726-84c6-32b24887c5e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1217781068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1217781068 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.2771308696 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1072007903 ps |
| CPU time | 34.07 seconds |
| Started | Feb 21 02:38:18 PM PST 24 |
| Finished | Feb 21 02:38:53 PM PST 24 |
| Peak memory | 204208 kb |
| Host | smart-7ccc69dd-c98f-484e-b17a-98ec0cf0aa66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2771308696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2771308696 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2506424489 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 10120918916 ps |
| CPU time | 86.13 seconds |
| Started | Feb 21 02:38:17 PM PST 24 |
| Finished | Feb 21 02:39:43 PM PST 24 |
| Peak memory | 204868 kb |
| Host | smart-d2087de3-0860-4562-aa98-ebb2d4f4731e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2506424489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2506424489 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.3164082753 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 892745797 ps |
| CPU time | 23.7 seconds |
| Started | Feb 21 02:38:17 PM PST 24 |
| Finished | Feb 21 02:38:41 PM PST 24 |
| Peak memory | 204604 kb |
| Host | smart-8bd20ece-950a-4a46-83e1-3a287704559d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164082753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3164082753 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.2042231319 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2250954869 ps |
| CPU time | 8.74 seconds |
| Started | Feb 21 02:38:20 PM PST 24 |
| Finished | Feb 21 02:38:29 PM PST 24 |
| Peak memory | 203412 kb |
| Host | smart-aac85f3d-6219-4639-bb81-762df4df173f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2042231319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2042231319 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.4228215019 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 167856411 ps |
| CPU time | 3.62 seconds |
| Started | Feb 21 02:38:14 PM PST 24 |
| Finished | Feb 21 02:38:18 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-9be4908f-4c1f-4e8d-b5e7-87f06f7917e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4228215019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4228215019 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3493798054 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 26679612244 ps |
| CPU time | 37.8 seconds |
| Started | Feb 21 02:38:18 PM PST 24 |
| Finished | Feb 21 02:38:57 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-bf143713-9161-42d0-81f6-21de773ec083 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493798054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3493798054 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.484574645 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 9635468449 ps |
| CPU time | 28.71 seconds |
| Started | Feb 21 02:38:16 PM PST 24 |
| Finished | Feb 21 02:38:45 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-74fb7aa1-9160-4794-8ee6-e8032f33a7c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=484574645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.484574645 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1271354926 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 41788859 ps |
| CPU time | 1.79 seconds |
| Started | Feb 21 02:38:13 PM PST 24 |
| Finished | Feb 21 02:38:15 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-4ba58800-65a1-439e-8568-1d412e005df1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271354926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1271354926 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.3933751167 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2865465231 ps |
| CPU time | 220.38 seconds |
| Started | Feb 21 02:38:18 PM PST 24 |
| Finished | Feb 21 02:41:59 PM PST 24 |
| Peak memory | 210236 kb |
| Host | smart-b48828c2-c433-4188-a42e-9b86f855d747 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3933751167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3933751167 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3251530518 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1179448125 ps |
| CPU time | 133.27 seconds |
| Started | Feb 21 02:38:18 PM PST 24 |
| Finished | Feb 21 02:40:32 PM PST 24 |
| Peak memory | 206820 kb |
| Host | smart-aae80ef4-6367-4725-b5c8-481aae2717f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3251530518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3251530518 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2748389326 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 7337112999 ps |
| CPU time | 361.13 seconds |
| Started | Feb 21 02:38:18 PM PST 24 |
| Finished | Feb 21 02:44:20 PM PST 24 |
| Peak memory | 210356 kb |
| Host | smart-85139e36-c9d9-420e-9077-6e55e501c552 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2748389326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.2748389326 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3718654130 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 832323916 ps |
| CPU time | 121.54 seconds |
| Started | Feb 21 02:38:19 PM PST 24 |
| Finished | Feb 21 02:40:21 PM PST 24 |
| Peak memory | 209020 kb |
| Host | smart-34866ceb-8f3f-4f01-9b22-f6c6bfa5a6d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3718654130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.3718654130 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.4025116247 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 38796510 ps |
| CPU time | 6.67 seconds |
| Started | Feb 21 02:38:16 PM PST 24 |
| Finished | Feb 21 02:38:23 PM PST 24 |
| Peak memory | 211220 kb |
| Host | smart-e2c5f956-fb15-4618-ad07-1ff75b9cce9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4025116247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.4025116247 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.3142557837 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 328118150 ps |
| CPU time | 24.71 seconds |
| Started | Feb 21 02:38:18 PM PST 24 |
| Finished | Feb 21 02:38:44 PM PST 24 |
| Peak memory | 204164 kb |
| Host | smart-e8c93ce3-19d3-4426-a108-99226d098256 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3142557837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3142557837 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3022561830 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 19387187179 ps |
| CPU time | 37.3 seconds |
| Started | Feb 21 02:38:16 PM PST 24 |
| Finished | Feb 21 02:38:54 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-565e954d-9cad-4257-b04a-24239cda206c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3022561830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.3022561830 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2207592592 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 79889167 ps |
| CPU time | 11.05 seconds |
| Started | Feb 21 02:38:23 PM PST 24 |
| Finished | Feb 21 02:38:35 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-c1f57b4b-894e-4c86-aa3e-323e13405e18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2207592592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2207592592 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.2801529433 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 389805796 ps |
| CPU time | 12.89 seconds |
| Started | Feb 21 02:38:16 PM PST 24 |
| Finished | Feb 21 02:38:29 PM PST 24 |
| Peak memory | 202992 kb |
| Host | smart-50df482a-c0d9-4389-848c-fdd5f3d7e49b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2801529433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2801529433 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.449611147 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 53854171 ps |
| CPU time | 2.77 seconds |
| Started | Feb 21 02:38:18 PM PST 24 |
| Finished | Feb 21 02:38:21 PM PST 24 |
| Peak memory | 203000 kb |
| Host | smart-5c7dbdd3-5a16-495f-93ba-af7fcb2fbb32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=449611147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.449611147 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.104754320 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 69772172288 ps |
| CPU time | 149.86 seconds |
| Started | Feb 21 02:38:17 PM PST 24 |
| Finished | Feb 21 02:40:48 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-83d57c6e-cab1-47c2-a27f-c705ce72d26e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=104754320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.104754320 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.410113541 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 30611822930 ps |
| CPU time | 180.13 seconds |
| Started | Feb 21 02:38:20 PM PST 24 |
| Finished | Feb 21 02:41:20 PM PST 24 |
| Peak memory | 204252 kb |
| Host | smart-b12a3687-c761-47c5-aa88-1043060fbd9f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=410113541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.410113541 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3382726856 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 210098298 ps |
| CPU time | 18.6 seconds |
| Started | Feb 21 02:38:18 PM PST 24 |
| Finished | Feb 21 02:38:37 PM PST 24 |
| Peak memory | 204484 kb |
| Host | smart-a2b1db48-4eaf-4278-90c2-7e39305d0e23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382726856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3382726856 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.2924896845 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2803756239 ps |
| CPU time | 33.18 seconds |
| Started | Feb 21 02:38:18 PM PST 24 |
| Finished | Feb 21 02:38:52 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-2f038357-f3a2-4459-8663-3a6205517295 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2924896845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2924896845 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.1451344469 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 58820399 ps |
| CPU time | 2.08 seconds |
| Started | Feb 21 02:38:24 PM PST 24 |
| Finished | Feb 21 02:38:27 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-9303dbf3-f1cb-47af-8f24-3dde5a9e1485 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1451344469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1451344469 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3162129759 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 6041623673 ps |
| CPU time | 25.35 seconds |
| Started | Feb 21 02:38:24 PM PST 24 |
| Finished | Feb 21 02:38:49 PM PST 24 |
| Peak memory | 203092 kb |
| Host | smart-aa581982-f68c-4bee-a331-d77e3da5e461 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162129759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3162129759 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3765444610 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4710472386 ps |
| CPU time | 33.44 seconds |
| Started | Feb 21 02:38:24 PM PST 24 |
| Finished | Feb 21 02:38:58 PM PST 24 |
| Peak memory | 203016 kb |
| Host | smart-425f14dc-f0a6-446a-b6d2-5c9898c7958f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3765444610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3765444610 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2594206537 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 117798803 ps |
| CPU time | 2.24 seconds |
| Started | Feb 21 02:38:17 PM PST 24 |
| Finished | Feb 21 02:38:20 PM PST 24 |
| Peak memory | 202984 kb |
| Host | smart-3c41ec67-4dd6-45fa-b36c-9b987f2daa82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594206537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2594206537 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1697192023 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 206862713 ps |
| CPU time | 28.88 seconds |
| Started | Feb 21 02:38:16 PM PST 24 |
| Finished | Feb 21 02:38:46 PM PST 24 |
| Peak memory | 205136 kb |
| Host | smart-fbfe13d9-3d9e-468e-8695-cccb0238559e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1697192023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1697192023 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3494392671 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 1652457449 ps |
| CPU time | 117.87 seconds |
| Started | Feb 21 02:38:16 PM PST 24 |
| Finished | Feb 21 02:40:15 PM PST 24 |
| Peak memory | 211268 kb |
| Host | smart-14d08c19-4005-4d84-a15a-b501b752af47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3494392671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3494392671 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.1331379318 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 7081296173 ps |
| CPU time | 459.57 seconds |
| Started | Feb 21 02:38:17 PM PST 24 |
| Finished | Feb 21 02:45:57 PM PST 24 |
| Peak memory | 210904 kb |
| Host | smart-cb46db0d-8e57-4aee-96f9-ae1df2f79ee9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1331379318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.1331379318 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1835600142 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 6401130147 ps |
| CPU time | 121.58 seconds |
| Started | Feb 21 02:38:17 PM PST 24 |
| Finished | Feb 21 02:40:19 PM PST 24 |
| Peak memory | 208944 kb |
| Host | smart-bed7574c-0742-414a-8dca-a4adccd6bb62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1835600142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1835600142 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3738325354 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 215262029 ps |
| CPU time | 17.68 seconds |
| Started | Feb 21 02:38:23 PM PST 24 |
| Finished | Feb 21 02:38:41 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-64213341-8aa0-4d90-b41d-fab30df3f292 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3738325354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3738325354 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.364167935 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1080900280 ps |
| CPU time | 25.73 seconds |
| Started | Feb 21 02:38:30 PM PST 24 |
| Finished | Feb 21 02:38:56 PM PST 24 |
| Peak memory | 204868 kb |
| Host | smart-16809839-bf99-4241-861a-19b1286152e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=364167935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.364167935 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.891068865 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 141762832665 ps |
| CPU time | 601.07 seconds |
| Started | Feb 21 02:38:29 PM PST 24 |
| Finished | Feb 21 02:48:31 PM PST 24 |
| Peak memory | 211544 kb |
| Host | smart-831f0872-6703-47df-994e-973b3caf7321 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=891068865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slo w_rsp.891068865 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3495846908 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 203321089 ps |
| CPU time | 8.07 seconds |
| Started | Feb 21 02:38:27 PM PST 24 |
| Finished | Feb 21 02:38:36 PM PST 24 |
| Peak memory | 203092 kb |
| Host | smart-d76f7160-99df-419a-98d2-f93d63acc1da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3495846908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3495846908 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.612225859 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 156170370 ps |
| CPU time | 9.69 seconds |
| Started | Feb 21 02:38:33 PM PST 24 |
| Finished | Feb 21 02:38:45 PM PST 24 |
| Peak memory | 203288 kb |
| Host | smart-039ff9fc-f44b-4d63-903e-65acdfac8b9e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=612225859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.612225859 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.171552941 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 536017766 ps |
| CPU time | 15.57 seconds |
| Started | Feb 21 02:38:26 PM PST 24 |
| Finished | Feb 21 02:38:42 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-c71cb72d-ce7d-46fe-b46f-1ad05da42481 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=171552941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.171552941 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.4157702290 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 85403650749 ps |
| CPU time | 151.74 seconds |
| Started | Feb 21 02:38:28 PM PST 24 |
| Finished | Feb 21 02:41:00 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-83e5fae8-f5c7-4003-af81-d45dd84a14e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157702290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.4157702290 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2037754348 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 23833310254 ps |
| CPU time | 205.86 seconds |
| Started | Feb 21 02:38:26 PM PST 24 |
| Finished | Feb 21 02:41:52 PM PST 24 |
| Peak memory | 205176 kb |
| Host | smart-4463a42d-85fd-41ca-968e-7381c3eadc83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2037754348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2037754348 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.3404126961 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 126678418 ps |
| CPU time | 10.72 seconds |
| Started | Feb 21 02:38:27 PM PST 24 |
| Finished | Feb 21 02:38:38 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-5dc439fa-3af8-474a-a7d5-33f3f3146ad5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404126961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.3404126961 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.1309882284 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 128657591 ps |
| CPU time | 5.93 seconds |
| Started | Feb 21 02:38:27 PM PST 24 |
| Finished | Feb 21 02:38:33 PM PST 24 |
| Peak memory | 203428 kb |
| Host | smart-3b7e5686-bdc8-4b5e-9777-da6975220170 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1309882284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1309882284 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.2330832489 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 34179269 ps |
| CPU time | 1.84 seconds |
| Started | Feb 21 02:38:24 PM PST 24 |
| Finished | Feb 21 02:38:26 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-e3240d89-c3e0-4618-9121-8b5511361387 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2330832489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2330832489 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3684521965 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 6926077202 ps |
| CPU time | 34.14 seconds |
| Started | Feb 21 02:38:19 PM PST 24 |
| Finished | Feb 21 02:38:54 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-a3ea09f5-317e-4b58-be2d-094ea0415b50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684521965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3684521965 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.98380652 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 16236517008 ps |
| CPU time | 38.67 seconds |
| Started | Feb 21 02:38:29 PM PST 24 |
| Finished | Feb 21 02:39:08 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-4ee623c4-9c6c-457a-bd7c-1f1eb7d375fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=98380652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.98380652 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2006112384 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 29704693 ps |
| CPU time | 2.23 seconds |
| Started | Feb 21 02:38:21 PM PST 24 |
| Finished | Feb 21 02:38:23 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-8f9992ba-8be7-4536-959b-0eccbe63372a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006112384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2006112384 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.826724465 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 12165194413 ps |
| CPU time | 153.57 seconds |
| Started | Feb 21 02:38:33 PM PST 24 |
| Finished | Feb 21 02:41:09 PM PST 24 |
| Peak memory | 207172 kb |
| Host | smart-ab051a8a-e748-4ce6-83e0-987ed6a08e23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=826724465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.826724465 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3274878337 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 19673791899 ps |
| CPU time | 293.55 seconds |
| Started | Feb 21 02:38:27 PM PST 24 |
| Finished | Feb 21 02:43:21 PM PST 24 |
| Peak memory | 208932 kb |
| Host | smart-a01ea68f-2955-4f9a-8675-6376ca15f764 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3274878337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3274878337 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1699306879 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 348927487 ps |
| CPU time | 98.9 seconds |
| Started | Feb 21 02:38:27 PM PST 24 |
| Finished | Feb 21 02:40:06 PM PST 24 |
| Peak memory | 207524 kb |
| Host | smart-eb7e49eb-18d5-425b-9e09-2c3735460a0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1699306879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.1699306879 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.4134367840 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 111956310 ps |
| CPU time | 21.94 seconds |
| Started | Feb 21 02:38:30 PM PST 24 |
| Finished | Feb 21 02:38:52 PM PST 24 |
| Peak memory | 211240 kb |
| Host | smart-23c50a88-5ca4-427c-a084-32e45c5658f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4134367840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.4134367840 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.2367221180 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 626230930 ps |
| CPU time | 20.67 seconds |
| Started | Feb 21 02:38:28 PM PST 24 |
| Finished | Feb 21 02:38:49 PM PST 24 |
| Peak memory | 204368 kb |
| Host | smart-4fa7163d-303f-497e-9fab-c76172b5d2bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2367221180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2367221180 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.3199700953 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 4959234429 ps |
| CPU time | 72.43 seconds |
| Started | Feb 21 02:38:31 PM PST 24 |
| Finished | Feb 21 02:39:45 PM PST 24 |
| Peak memory | 206332 kb |
| Host | smart-7b681ec6-87f5-48c8-ab7f-6bd1102e0da7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3199700953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.3199700953 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3483687821 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 42591289484 ps |
| CPU time | 334.13 seconds |
| Started | Feb 21 02:38:43 PM PST 24 |
| Finished | Feb 21 02:44:19 PM PST 24 |
| Peak memory | 211220 kb |
| Host | smart-2020a0f7-39ac-4093-ac17-4272ae4772f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3483687821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.3483687821 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3798550736 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 674651356 ps |
| CPU time | 11.74 seconds |
| Started | Feb 21 02:38:43 PM PST 24 |
| Finished | Feb 21 02:38:56 PM PST 24 |
| Peak memory | 203164 kb |
| Host | smart-6f1fcf40-961d-434b-9967-5be891fd1146 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3798550736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3798550736 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.2704546075 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1514250440 ps |
| CPU time | 29.38 seconds |
| Started | Feb 21 02:38:41 PM PST 24 |
| Finished | Feb 21 02:39:10 PM PST 24 |
| Peak memory | 202956 kb |
| Host | smart-9f77edc5-420c-496d-9a00-41bf61254f70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2704546075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2704546075 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.3748622586 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 236703771 ps |
| CPU time | 2.98 seconds |
| Started | Feb 21 02:38:33 PM PST 24 |
| Finished | Feb 21 02:38:38 PM PST 24 |
| Peak memory | 203284 kb |
| Host | smart-b9628be8-f55a-4bcf-a811-d78858e67f7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3748622586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3748622586 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.2308871448 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 104129230676 ps |
| CPU time | 242.08 seconds |
| Started | Feb 21 02:38:25 PM PST 24 |
| Finished | Feb 21 02:42:28 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-33821098-d650-4e01-8ebc-83cf9dd1f086 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308871448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2308871448 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1131151973 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 73586536573 ps |
| CPU time | 237.04 seconds |
| Started | Feb 21 02:38:27 PM PST 24 |
| Finished | Feb 21 02:42:24 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-f60361d3-4d34-48dd-ae55-3f03d1f01d38 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1131151973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1131151973 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3959618606 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 297277177 ps |
| CPU time | 26.14 seconds |
| Started | Feb 21 02:38:25 PM PST 24 |
| Finished | Feb 21 02:38:52 PM PST 24 |
| Peak memory | 204192 kb |
| Host | smart-48c9dad6-0c16-4e61-854d-dadc6fcca335 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959618606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3959618606 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.2403585662 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 922563177 ps |
| CPU time | 15.99 seconds |
| Started | Feb 21 02:38:41 PM PST 24 |
| Finished | Feb 21 02:38:57 PM PST 24 |
| Peak memory | 203024 kb |
| Host | smart-ece273e7-a931-47a3-9949-a38e29da6e65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2403585662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2403585662 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.4128188000 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 272109892 ps |
| CPU time | 3.79 seconds |
| Started | Feb 21 02:38:28 PM PST 24 |
| Finished | Feb 21 02:38:32 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-952c4cd3-29d7-4fea-a39e-3692cb29adce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4128188000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.4128188000 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3404273752 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 8647659576 ps |
| CPU time | 33.78 seconds |
| Started | Feb 21 02:38:28 PM PST 24 |
| Finished | Feb 21 02:39:02 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-a85f6a20-4529-4051-92c6-ff8929600e18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404273752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3404273752 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.504894625 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 11441587654 ps |
| CPU time | 31.68 seconds |
| Started | Feb 21 02:38:29 PM PST 24 |
| Finished | Feb 21 02:39:01 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-b0f14d35-21d7-4b9d-a791-24d1d39a1123 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=504894625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.504894625 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1533960767 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 42592744 ps |
| CPU time | 2.14 seconds |
| Started | Feb 21 02:38:28 PM PST 24 |
| Finished | Feb 21 02:38:30 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-aa24cb2b-ba6e-43b3-8b88-866f0c17cb13 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533960767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1533960767 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.3764106332 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1455110910 ps |
| CPU time | 164.4 seconds |
| Started | Feb 21 02:38:43 PM PST 24 |
| Finished | Feb 21 02:41:28 PM PST 24 |
| Peak memory | 206632 kb |
| Host | smart-64425327-4408-4ee3-9059-76eac0238559 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3764106332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3764106332 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3696822586 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 13357228556 ps |
| CPU time | 201.01 seconds |
| Started | Feb 21 02:38:42 PM PST 24 |
| Finished | Feb 21 02:42:03 PM PST 24 |
| Peak memory | 206576 kb |
| Host | smart-3e3d036d-25d1-436c-a8aa-ad190590121b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3696822586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3696822586 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.4034684671 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2454188434 ps |
| CPU time | 218.71 seconds |
| Started | Feb 21 02:38:42 PM PST 24 |
| Finished | Feb 21 02:42:21 PM PST 24 |
| Peak memory | 208892 kb |
| Host | smart-292130e5-f2c7-48a0-bc71-209803b11041 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4034684671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.4034684671 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2935191448 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4120575363 ps |
| CPU time | 310.09 seconds |
| Started | Feb 21 02:38:41 PM PST 24 |
| Finished | Feb 21 02:43:51 PM PST 24 |
| Peak memory | 219452 kb |
| Host | smart-588bba91-200c-473b-ac1d-319a1e2cf9c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2935191448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.2935191448 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.3488519250 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 80343568 ps |
| CPU time | 12.69 seconds |
| Started | Feb 21 02:38:42 PM PST 24 |
| Finished | Feb 21 02:38:55 PM PST 24 |
| Peak memory | 211184 kb |
| Host | smart-f4d8a643-4575-4dbc-a210-6f940a6091bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3488519250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3488519250 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.169390218 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 283796756 ps |
| CPU time | 30.61 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:28 PM PST 24 |
| Peak memory | 205680 kb |
| Host | smart-d615ac3a-e8b6-4f3f-84cc-ee76ebda244a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=169390218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.169390218 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3345495003 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 940366765 ps |
| CPU time | 7.5 seconds |
| Started | Feb 21 02:35:53 PM PST 24 |
| Finished | Feb 21 02:36:01 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-ba3b84cc-9de3-443d-98ee-a73e541591ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3345495003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3345495003 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.3238626142 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 536962413 ps |
| CPU time | 22.93 seconds |
| Started | Feb 21 02:35:51 PM PST 24 |
| Finished | Feb 21 02:36:15 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-77931114-0bfc-4030-9e20-043183e86408 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3238626142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3238626142 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.1927857520 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3182904141 ps |
| CPU time | 17.73 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:18 PM PST 24 |
| Peak memory | 204152 kb |
| Host | smart-53ebce4e-fcae-4300-ba48-78ad8432a13d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1927857520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1927857520 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3827653864 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 21808873704 ps |
| CPU time | 90.36 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:37:33 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-ec76fec9-0cab-426f-8e32-38473614df40 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827653864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3827653864 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.356541020 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 8989994717 ps |
| CPU time | 74.66 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:37:19 PM PST 24 |
| Peak memory | 211276 kb |
| Host | smart-d1c4dfda-1acb-4334-b9db-34bf164ef017 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=356541020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.356541020 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2900504782 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 54279401 ps |
| CPU time | 7.31 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:05 PM PST 24 |
| Peak memory | 204412 kb |
| Host | smart-0f71a496-6ba4-43cd-a9b2-85a2ceb4be65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900504782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2900504782 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.1042216358 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 406153489 ps |
| CPU time | 23.27 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:24 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-269eda2b-6fef-413d-ae46-bb5b47e29781 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1042216358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1042216358 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2931825862 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 288496750 ps |
| CPU time | 3.87 seconds |
| Started | Feb 21 02:35:56 PM PST 24 |
| Finished | Feb 21 02:36:04 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-3dc40577-2a01-4d87-878f-8a214124a4ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2931825862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2931825862 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.3473933728 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 11109582869 ps |
| CPU time | 29.29 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:29 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-335b3124-f8a0-4865-b9c1-5dd35df4e857 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473933728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3473933728 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.254589773 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3777461197 ps |
| CPU time | 19.95 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:18 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-4e4e5637-9ff2-4ece-862a-a1a89b2dee12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=254589773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.254589773 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2960043810 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 23384428 ps |
| CPU time | 2.56 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:36:05 PM PST 24 |
| Peak memory | 203036 kb |
| Host | smart-fad299b0-77f7-4dbf-8d29-66e569c936b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960043810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2960043810 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.2333408431 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 6853398726 ps |
| CPU time | 212.02 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:39:36 PM PST 24 |
| Peak memory | 206744 kb |
| Host | smart-a1b9122c-5b63-4431-9364-d3d51fa790b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2333408431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2333408431 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1497046938 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 16961883871 ps |
| CPU time | 272.78 seconds |
| Started | Feb 21 02:35:56 PM PST 24 |
| Finished | Feb 21 02:40:31 PM PST 24 |
| Peak memory | 210264 kb |
| Host | smart-265ddf2a-4163-4f1a-9573-ece841bd7634 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1497046938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1497046938 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2854518561 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 8180103768 ps |
| CPU time | 408.63 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:42:52 PM PST 24 |
| Peak memory | 208612 kb |
| Host | smart-84030763-2fbe-45e1-99d5-24079c7280ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2854518561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.2854518561 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3579670599 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1644249519 ps |
| CPU time | 144.55 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:38:22 PM PST 24 |
| Peak memory | 209496 kb |
| Host | smart-1040cfdb-efcd-48b5-a76e-ad8d328a4dad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3579670599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.3579670599 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.1712182241 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 321309045 ps |
| CPU time | 23.06 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:27 PM PST 24 |
| Peak memory | 204608 kb |
| Host | smart-07bbf090-d6a4-4229-91a7-b0727390ca79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1712182241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1712182241 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.4063068200 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 291398004 ps |
| CPU time | 36.75 seconds |
| Started | Feb 21 02:38:44 PM PST 24 |
| Finished | Feb 21 02:39:22 PM PST 24 |
| Peak memory | 211280 kb |
| Host | smart-07bd6731-f0e2-41ac-89ed-4a2cd28ea367 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4063068200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4063068200 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.4086179812 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 8757076574 ps |
| CPU time | 78.51 seconds |
| Started | Feb 21 02:38:45 PM PST 24 |
| Finished | Feb 21 02:40:04 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-737627e1-a9da-41f2-bf41-9ba0d3ce07b2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4086179812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.4086179812 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1460815075 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 290147632 ps |
| CPU time | 12.36 seconds |
| Started | Feb 21 02:38:45 PM PST 24 |
| Finished | Feb 21 02:38:58 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-7373609c-4100-4524-a6ae-c3b5b28ae5c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1460815075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1460815075 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.1329117239 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 203596768 ps |
| CPU time | 24.95 seconds |
| Started | Feb 21 02:38:41 PM PST 24 |
| Finished | Feb 21 02:39:07 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-c76dc5a9-78a1-4390-a25c-78f9552d30e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1329117239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1329117239 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.2765964506 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1743876160 ps |
| CPU time | 38.72 seconds |
| Started | Feb 21 02:38:41 PM PST 24 |
| Finished | Feb 21 02:39:20 PM PST 24 |
| Peak memory | 204220 kb |
| Host | smart-800886c4-7606-4960-873c-a068c08e11e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2765964506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2765964506 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1078020136 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 102499095848 ps |
| CPU time | 167.05 seconds |
| Started | Feb 21 02:38:41 PM PST 24 |
| Finished | Feb 21 02:41:29 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-bba48688-6133-4c11-80f8-c4327c90a15d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078020136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1078020136 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.3930063266 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2379583141 ps |
| CPU time | 19.05 seconds |
| Started | Feb 21 02:38:40 PM PST 24 |
| Finished | Feb 21 02:39:00 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-ade48adc-cc94-4444-9fd0-29ca31b456d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3930063266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3930063266 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.3573957927 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 76550344 ps |
| CPU time | 15.76 seconds |
| Started | Feb 21 02:38:42 PM PST 24 |
| Finished | Feb 21 02:38:58 PM PST 24 |
| Peak memory | 211268 kb |
| Host | smart-518aec01-75ed-4cd1-851c-f99c634eb3b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573957927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.3573957927 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.2801084019 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 771557961 ps |
| CPU time | 12.55 seconds |
| Started | Feb 21 02:38:52 PM PST 24 |
| Finished | Feb 21 02:39:05 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-d3655b5c-ae40-4c59-a982-940464830fd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2801084019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2801084019 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.3403322174 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 59161383 ps |
| CPU time | 2.08 seconds |
| Started | Feb 21 02:38:42 PM PST 24 |
| Finished | Feb 21 02:38:44 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-02c3a5bb-1b2f-42b0-9200-4d3c228e0348 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3403322174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3403322174 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2508625422 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5908595038 ps |
| CPU time | 33.79 seconds |
| Started | Feb 21 02:38:40 PM PST 24 |
| Finished | Feb 21 02:39:15 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-103e0504-19f3-4fb7-9728-025a4e11d3c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508625422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2508625422 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2541643386 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12157535486 ps |
| CPU time | 32.43 seconds |
| Started | Feb 21 02:38:44 PM PST 24 |
| Finished | Feb 21 02:39:18 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-bfd2eb0b-4bf3-4b5b-aa38-dd2b7b7e19a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2541643386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2541643386 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3619142500 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 25927561 ps |
| CPU time | 2.09 seconds |
| Started | Feb 21 02:38:40 PM PST 24 |
| Finished | Feb 21 02:38:43 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-3cd9ec37-f9ff-4e02-ae43-9c2f649f9d32 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619142500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3619142500 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3142400129 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 7161736221 ps |
| CPU time | 192.04 seconds |
| Started | Feb 21 02:38:42 PM PST 24 |
| Finished | Feb 21 02:41:55 PM PST 24 |
| Peak memory | 209272 kb |
| Host | smart-2ef8a688-9b9c-4280-9016-c55cafe0ea4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3142400129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3142400129 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2315476820 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 9556067205 ps |
| CPU time | 197.02 seconds |
| Started | Feb 21 02:38:43 PM PST 24 |
| Finished | Feb 21 02:42:00 PM PST 24 |
| Peak memory | 205220 kb |
| Host | smart-c666f806-c377-442e-af01-72d737bdce19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2315476820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2315476820 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2671317168 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1976983089 ps |
| CPU time | 127.59 seconds |
| Started | Feb 21 02:38:43 PM PST 24 |
| Finished | Feb 21 02:40:51 PM PST 24 |
| Peak memory | 206316 kb |
| Host | smart-1e75f062-2542-4493-8b66-4d0ead6a96bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2671317168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.2671317168 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2835696796 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 8953543040 ps |
| CPU time | 186.27 seconds |
| Started | Feb 21 02:38:46 PM PST 24 |
| Finished | Feb 21 02:41:53 PM PST 24 |
| Peak memory | 211532 kb |
| Host | smart-aba06f32-94d0-4cdd-8286-5533c70b6fef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2835696796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.2835696796 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.1891200038 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 224226728 ps |
| CPU time | 14.44 seconds |
| Started | Feb 21 02:38:42 PM PST 24 |
| Finished | Feb 21 02:38:57 PM PST 24 |
| Peak memory | 204448 kb |
| Host | smart-0f9dc483-24ee-4972-b576-ff6554a24156 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1891200038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1891200038 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1108426333 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 8205461861 ps |
| CPU time | 70.7 seconds |
| Started | Feb 21 02:39:04 PM PST 24 |
| Finished | Feb 21 02:40:16 PM PST 24 |
| Peak memory | 211332 kb |
| Host | smart-992cc2a9-8f9d-4390-8d61-6eb14e3ae532 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1108426333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1108426333 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1117076088 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 336658651448 ps |
| CPU time | 728.59 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:51:25 PM PST 24 |
| Peak memory | 211368 kb |
| Host | smart-7de2de83-12a9-4b37-ab9e-499a576843dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1117076088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1117076088 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.270246160 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 166413033 ps |
| CPU time | 16.81 seconds |
| Started | Feb 21 02:39:03 PM PST 24 |
| Finished | Feb 21 02:39:20 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-96ce3b89-2338-4734-b92e-424934cd400b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=270246160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.270246160 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.2054632166 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 67209512 ps |
| CPU time | 9.15 seconds |
| Started | Feb 21 02:38:55 PM PST 24 |
| Finished | Feb 21 02:39:06 PM PST 24 |
| Peak memory | 203044 kb |
| Host | smart-1791a058-22dd-47d7-b3d4-21f763108abc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2054632166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2054632166 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.1934034873 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2695015728 ps |
| CPU time | 30.32 seconds |
| Started | Feb 21 02:39:01 PM PST 24 |
| Finished | Feb 21 02:39:32 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-c99f4882-7913-4031-816a-9617321a22a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1934034873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1934034873 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.1271928971 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 71780505126 ps |
| CPU time | 147.86 seconds |
| Started | Feb 21 02:39:06 PM PST 24 |
| Finished | Feb 21 02:41:36 PM PST 24 |
| Peak memory | 204252 kb |
| Host | smart-668c8939-a040-4608-86c7-7144a15df02d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271928971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1271928971 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2935720843 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 46757246165 ps |
| CPU time | 222.1 seconds |
| Started | Feb 21 02:38:52 PM PST 24 |
| Finished | Feb 21 02:42:35 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-ebe6343c-9480-4290-9e8c-b2ed6751b3cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2935720843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2935720843 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.104817337 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 49893401 ps |
| CPU time | 5.2 seconds |
| Started | Feb 21 02:39:01 PM PST 24 |
| Finished | Feb 21 02:39:07 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-39a23128-ce91-4bf1-b638-d941a5bd02ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104817337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.104817337 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.1915394920 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 106581229 ps |
| CPU time | 9.67 seconds |
| Started | Feb 21 02:38:59 PM PST 24 |
| Finished | Feb 21 02:39:11 PM PST 24 |
| Peak memory | 203460 kb |
| Host | smart-bfeaae39-35c9-4934-b5e7-82300b0f5dac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1915394920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1915394920 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.2167216181 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 38626392 ps |
| CPU time | 2.76 seconds |
| Started | Feb 21 02:38:42 PM PST 24 |
| Finished | Feb 21 02:38:45 PM PST 24 |
| Peak memory | 203004 kb |
| Host | smart-a127a4d1-b0ef-4a05-a2ea-0a7c10d39ecb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2167216181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2167216181 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3101495210 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 16454683793 ps |
| CPU time | 34.28 seconds |
| Started | Feb 21 02:38:56 PM PST 24 |
| Finished | Feb 21 02:39:31 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-57a710d0-4a50-4431-aa5d-ebad48304839 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101495210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3101495210 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.4067052111 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4752386374 ps |
| CPU time | 29.33 seconds |
| Started | Feb 21 02:39:17 PM PST 24 |
| Finished | Feb 21 02:39:46 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-23bd21b5-2319-47f1-841b-9b8562577734 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4067052111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4067052111 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2003200027 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 50192980 ps |
| CPU time | 2.46 seconds |
| Started | Feb 21 02:38:43 PM PST 24 |
| Finished | Feb 21 02:38:47 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-0a85acdd-0dde-4970-85a1-0a39600b99b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003200027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2003200027 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.1370080971 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 8250262361 ps |
| CPU time | 112.32 seconds |
| Started | Feb 21 02:38:57 PM PST 24 |
| Finished | Feb 21 02:40:51 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-5b4eb99a-cc5d-4ca7-8365-7e195a064aa5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1370080971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1370080971 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2114258597 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1566407481 ps |
| CPU time | 95.8 seconds |
| Started | Feb 21 02:39:02 PM PST 24 |
| Finished | Feb 21 02:40:38 PM PST 24 |
| Peak memory | 204960 kb |
| Host | smart-d37e07ec-c80a-45f0-ae9a-311ea4b75b75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2114258597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2114258597 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3593795248 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4314628189 ps |
| CPU time | 437.95 seconds |
| Started | Feb 21 02:38:55 PM PST 24 |
| Finished | Feb 21 02:46:14 PM PST 24 |
| Peak memory | 210424 kb |
| Host | smart-3a0f4c0d-7b95-40fb-80d3-23c2fe9a557b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3593795248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.3593795248 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.251445604 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 86446098 ps |
| CPU time | 8.73 seconds |
| Started | Feb 21 02:39:14 PM PST 24 |
| Finished | Feb 21 02:39:25 PM PST 24 |
| Peak memory | 204004 kb |
| Host | smart-e93d682d-cdf4-4327-8759-e3e153a5258b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=251445604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res et_error.251445604 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.2620117635 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 191566422 ps |
| CPU time | 6.99 seconds |
| Started | Feb 21 02:39:12 PM PST 24 |
| Finished | Feb 21 02:39:20 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-4111bf33-19cd-43cc-8431-fc0b14cbe7bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2620117635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2620117635 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2267290981 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5110514341 ps |
| CPU time | 44.52 seconds |
| Started | Feb 21 02:38:54 PM PST 24 |
| Finished | Feb 21 02:39:40 PM PST 24 |
| Peak memory | 205884 kb |
| Host | smart-0d2746e3-103b-4bcb-8f35-03e29b590a1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2267290981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2267290981 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2456579255 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 99063271418 ps |
| CPU time | 652.12 seconds |
| Started | Feb 21 02:39:01 PM PST 24 |
| Finished | Feb 21 02:49:54 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-bfe4f01d-75fc-4ab2-892d-68218c106fd9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2456579255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.2456579255 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.3456666254 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 555527614 ps |
| CPU time | 13.24 seconds |
| Started | Feb 21 02:39:02 PM PST 24 |
| Finished | Feb 21 02:39:15 PM PST 24 |
| Peak memory | 203176 kb |
| Host | smart-396d317f-fd0f-42cb-9db3-56589ed0be12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3456666254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.3456666254 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.458563225 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 711975398 ps |
| CPU time | 26.18 seconds |
| Started | Feb 21 02:39:00 PM PST 24 |
| Finished | Feb 21 02:39:27 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-45298d97-80f3-4bcc-a532-97c6d6e3c205 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=458563225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.458563225 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.2929719259 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1132648286 ps |
| CPU time | 31.48 seconds |
| Started | Feb 21 02:39:20 PM PST 24 |
| Finished | Feb 21 02:39:55 PM PST 24 |
| Peak memory | 211220 kb |
| Host | smart-f146652c-cf8c-4660-a04d-b5628db7ac83 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2929719259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2929719259 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.549719980 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 10304807297 ps |
| CPU time | 62.39 seconds |
| Started | Feb 21 02:39:02 PM PST 24 |
| Finished | Feb 21 02:40:05 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-7f97c4a0-6983-4ce8-8cc3-83f73d1816b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=549719980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.549719980 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.243042042 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 33445385027 ps |
| CPU time | 232.16 seconds |
| Started | Feb 21 02:38:54 PM PST 24 |
| Finished | Feb 21 02:42:48 PM PST 24 |
| Peak memory | 211300 kb |
| Host | smart-a0cdf907-66c9-434a-b2af-3455b6baf8cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=243042042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.243042042 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.1340062085 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 103052355 ps |
| CPU time | 12.44 seconds |
| Started | Feb 21 02:39:04 PM PST 24 |
| Finished | Feb 21 02:39:17 PM PST 24 |
| Peak memory | 204120 kb |
| Host | smart-57594c6b-5d9c-4947-a548-137d7c5791eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340062085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1340062085 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.590072811 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 308661205 ps |
| CPU time | 8.1 seconds |
| Started | Feb 21 02:38:57 PM PST 24 |
| Finished | Feb 21 02:39:07 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-90eb787a-56f2-4af7-b8cb-38e850eb2c3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=590072811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.590072811 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.2364670996 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 122270544 ps |
| CPU time | 3.42 seconds |
| Started | Feb 21 02:39:05 PM PST 24 |
| Finished | Feb 21 02:39:08 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-8e74fa2f-fe24-40a9-9ff6-7a1548a6e8dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2364670996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2364670996 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1163742628 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3869872265 ps |
| CPU time | 24.76 seconds |
| Started | Feb 21 02:39:03 PM PST 24 |
| Finished | Feb 21 02:39:28 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-ff9e814b-22f0-4f82-b2df-51044db570ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163742628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1163742628 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3739700280 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3246227181 ps |
| CPU time | 26.34 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:39:43 PM PST 24 |
| Peak memory | 203036 kb |
| Host | smart-650aba7d-80f2-4321-90e4-9cf8f56fe1da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3739700280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3739700280 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.4282788049 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 36447374 ps |
| CPU time | 2.41 seconds |
| Started | Feb 21 02:38:52 PM PST 24 |
| Finished | Feb 21 02:38:55 PM PST 24 |
| Peak memory | 202976 kb |
| Host | smart-c11d1813-21e2-4eb4-964e-5b95684e3305 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282788049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.4282788049 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1447834887 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 6506569065 ps |
| CPU time | 96.33 seconds |
| Started | Feb 21 02:39:01 PM PST 24 |
| Finished | Feb 21 02:40:38 PM PST 24 |
| Peak memory | 207508 kb |
| Host | smart-6701ae5e-cf72-4a7f-93ff-e920a88a9b3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1447834887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1447834887 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2893416017 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3750647728 ps |
| CPU time | 130.62 seconds |
| Started | Feb 21 02:38:56 PM PST 24 |
| Finished | Feb 21 02:41:08 PM PST 24 |
| Peak memory | 207132 kb |
| Host | smart-8c1f5a3b-52e3-4a00-843b-e0e913d52e42 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2893416017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2893416017 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.960297480 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 3362911851 ps |
| CPU time | 319.62 seconds |
| Started | Feb 21 02:39:02 PM PST 24 |
| Finished | Feb 21 02:44:22 PM PST 24 |
| Peak memory | 208712 kb |
| Host | smart-312e6ede-08cb-47a4-97db-d08cde2cd1cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960297480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand _reset.960297480 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3417497192 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 88843655 ps |
| CPU time | 7.49 seconds |
| Started | Feb 21 02:38:59 PM PST 24 |
| Finished | Feb 21 02:39:09 PM PST 24 |
| Peak memory | 211472 kb |
| Host | smart-1f070c87-882c-4020-8e14-f28fe13fc929 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3417497192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3417497192 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.2304299235 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 304186942 ps |
| CPU time | 19.42 seconds |
| Started | Feb 21 02:39:11 PM PST 24 |
| Finished | Feb 21 02:39:32 PM PST 24 |
| Peak memory | 211228 kb |
| Host | smart-1836fe12-7e33-41dd-b8bf-e8ff8f425e30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2304299235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.2304299235 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3642598714 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 35935193101 ps |
| CPU time | 165.4 seconds |
| Started | Feb 21 02:39:18 PM PST 24 |
| Finished | Feb 21 02:42:04 PM PST 24 |
| Peak memory | 211372 kb |
| Host | smart-cafcb7a9-3268-4104-86c6-65806c2bd07d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3642598714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3642598714 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.661672865 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 882128267 ps |
| CPU time | 18.93 seconds |
| Started | Feb 21 02:39:10 PM PST 24 |
| Finished | Feb 21 02:39:30 PM PST 24 |
| Peak memory | 203256 kb |
| Host | smart-25912441-88a3-407d-9c43-a7920c5deff5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=661672865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.661672865 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.3485548145 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 340463313 ps |
| CPU time | 20.17 seconds |
| Started | Feb 21 02:39:17 PM PST 24 |
| Finished | Feb 21 02:39:38 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-1c4c30bf-ead9-4068-ad7e-28ffc6ec1aeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3485548145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3485548145 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.2290845302 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 679234386 ps |
| CPU time | 33.5 seconds |
| Started | Feb 21 02:39:20 PM PST 24 |
| Finished | Feb 21 02:39:57 PM PST 24 |
| Peak memory | 204084 kb |
| Host | smart-b109e3a2-3122-4ab9-a4c9-aaff90e1459c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2290845302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2290845302 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1225728578 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 8507894762 ps |
| CPU time | 30.79 seconds |
| Started | Feb 21 02:39:24 PM PST 24 |
| Finished | Feb 21 02:39:56 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-4e409e6b-537d-4d68-9b89-c3891e912705 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225728578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1225728578 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3235549285 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 17723684894 ps |
| CPU time | 131.68 seconds |
| Started | Feb 21 02:39:12 PM PST 24 |
| Finished | Feb 21 02:41:25 PM PST 24 |
| Peak memory | 204528 kb |
| Host | smart-d56a4049-1104-48b6-8b8e-b001ec5e41a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3235549285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3235549285 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1619388910 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 395751554 ps |
| CPU time | 22.39 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:39:39 PM PST 24 |
| Peak memory | 204112 kb |
| Host | smart-33eebcbc-a821-4277-9d53-1545a9f39b70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619388910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1619388910 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.2834938467 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3140093769 ps |
| CPU time | 32.27 seconds |
| Started | Feb 21 02:39:20 PM PST 24 |
| Finished | Feb 21 02:39:56 PM PST 24 |
| Peak memory | 203096 kb |
| Host | smart-80654df6-665f-417d-97cb-79265051885e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2834938467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2834938467 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.2430650261 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 168144455 ps |
| CPU time | 3.79 seconds |
| Started | Feb 21 02:38:51 PM PST 24 |
| Finished | Feb 21 02:38:56 PM PST 24 |
| Peak memory | 203056 kb |
| Host | smart-0ac6bc66-28ee-4597-989e-9f7fa2240cf4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2430650261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2430650261 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2626449630 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 6985223605 ps |
| CPU time | 32.28 seconds |
| Started | Feb 21 02:39:14 PM PST 24 |
| Finished | Feb 21 02:39:47 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-35d67d97-28ce-42a7-9420-d9bb40ef38a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626449630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2626449630 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3661793476 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 23187193054 ps |
| CPU time | 42.91 seconds |
| Started | Feb 21 02:39:18 PM PST 24 |
| Finished | Feb 21 02:40:01 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-83be5275-5cc1-4c2a-8053-db72b5f90ad5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3661793476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3661793476 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3742584646 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 35766137 ps |
| CPU time | 2.28 seconds |
| Started | Feb 21 02:39:01 PM PST 24 |
| Finished | Feb 21 02:39:04 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-ffc71b92-1436-4626-a8fb-5bd33cd0b476 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742584646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3742584646 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.4238910112 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 13618469465 ps |
| CPU time | 167.15 seconds |
| Started | Feb 21 02:39:14 PM PST 24 |
| Finished | Feb 21 02:42:02 PM PST 24 |
| Peak memory | 207272 kb |
| Host | smart-ec97a240-ce8b-4060-a93e-301b8295502e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4238910112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.4238910112 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2964390595 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4907880495 ps |
| CPU time | 193.59 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:42:38 PM PST 24 |
| Peak memory | 208104 kb |
| Host | smart-4a719297-ce79-4416-9134-74b0485872f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2964390595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2964390595 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.1493032230 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3269584749 ps |
| CPU time | 168.79 seconds |
| Started | Feb 21 02:39:19 PM PST 24 |
| Finished | Feb 21 02:42:10 PM PST 24 |
| Peak memory | 208152 kb |
| Host | smart-926ed582-4c84-474c-92bc-9f46d37363b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1493032230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.1493032230 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.855555450 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 7162945561 ps |
| CPU time | 183.64 seconds |
| Started | Feb 21 02:39:11 PM PST 24 |
| Finished | Feb 21 02:42:16 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-835b74b4-bb46-42cb-8849-d4754fc9fa9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=855555450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_res et_error.855555450 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1291547322 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 443050348 ps |
| CPU time | 17.2 seconds |
| Started | Feb 21 02:39:05 PM PST 24 |
| Finished | Feb 21 02:39:24 PM PST 24 |
| Peak memory | 204312 kb |
| Host | smart-fd9d700c-5a73-4ab2-a950-7aa69c3a4974 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1291547322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1291547322 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.4271686076 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1493417275 ps |
| CPU time | 63.03 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:40:19 PM PST 24 |
| Peak memory | 205132 kb |
| Host | smart-4763d2e7-876c-4e27-9c74-48f6fa7582f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4271686076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.4271686076 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.724824051 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 43708270475 ps |
| CPU time | 302.87 seconds |
| Started | Feb 21 02:39:10 PM PST 24 |
| Finished | Feb 21 02:44:13 PM PST 24 |
| Peak memory | 211292 kb |
| Host | smart-1d4cff2c-f9b4-4528-a784-15f6b668bf7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=724824051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo w_rsp.724824051 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3228190657 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3191824726 ps |
| CPU time | 29.42 seconds |
| Started | Feb 21 02:39:14 PM PST 24 |
| Finished | Feb 21 02:39:45 PM PST 24 |
| Peak memory | 202864 kb |
| Host | smart-924326e3-7f7a-46dc-b702-5153d6909c8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3228190657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3228190657 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.917730519 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2309109983 ps |
| CPU time | 35.66 seconds |
| Started | Feb 21 02:39:14 PM PST 24 |
| Finished | Feb 21 02:39:51 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-87d6089c-8e18-4d17-9fda-652870b969ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=917730519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.917730519 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.1543716923 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1512678791 ps |
| CPU time | 37.57 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:39:54 PM PST 24 |
| Peak memory | 204424 kb |
| Host | smart-25f8ae32-5965-4009-82b3-217224ee3d98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1543716923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1543716923 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.2461972445 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 44978186497 ps |
| CPU time | 256.84 seconds |
| Started | Feb 21 02:39:16 PM PST 24 |
| Finished | Feb 21 02:43:33 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-bca612ec-3b5c-4842-8bc4-bad6f2fe6e9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461972445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2461972445 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3464521546 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 17596086554 ps |
| CPU time | 160.49 seconds |
| Started | Feb 21 02:39:04 PM PST 24 |
| Finished | Feb 21 02:41:45 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-0679ddaa-960b-4033-b757-5233f0f7221f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3464521546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3464521546 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.749794448 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 112590826 ps |
| CPU time | 12.66 seconds |
| Started | Feb 21 02:39:11 PM PST 24 |
| Finished | Feb 21 02:39:25 PM PST 24 |
| Peak memory | 204104 kb |
| Host | smart-f76a998d-a3ee-44bc-947f-da37ca5592e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749794448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.749794448 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.3833095226 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4242917244 ps |
| CPU time | 23.61 seconds |
| Started | Feb 21 02:39:14 PM PST 24 |
| Finished | Feb 21 02:39:40 PM PST 24 |
| Peak memory | 203568 kb |
| Host | smart-e75b01cb-acce-471d-9589-061edbec3494 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3833095226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3833095226 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.3375051313 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 143129725 ps |
| CPU time | 3.65 seconds |
| Started | Feb 21 02:39:18 PM PST 24 |
| Finished | Feb 21 02:39:22 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-12e3ad1f-62a7-434b-98a5-2436d5e93679 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3375051313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3375051313 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.2908401148 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 15187816804 ps |
| CPU time | 39.51 seconds |
| Started | Feb 21 02:39:13 PM PST 24 |
| Finished | Feb 21 02:39:54 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-06f689bb-b2f3-4a05-80a8-adbc12df7315 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908401148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2908401148 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.1706512575 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4557253953 ps |
| CPU time | 38.19 seconds |
| Started | Feb 21 02:39:11 PM PST 24 |
| Finished | Feb 21 02:39:49 PM PST 24 |
| Peak memory | 202976 kb |
| Host | smart-13b349f8-5c41-4f5f-9b61-414bb5bd482f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1706512575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1706512575 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2066979164 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 24977085 ps |
| CPU time | 2.34 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:39:27 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-ad90ec49-f05e-4816-a169-05d75301798d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066979164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2066979164 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.169649002 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1296672195 ps |
| CPU time | 145.72 seconds |
| Started | Feb 21 02:39:20 PM PST 24 |
| Finished | Feb 21 02:41:49 PM PST 24 |
| Peak memory | 207984 kb |
| Host | smart-76fc4864-e555-45f4-b60a-85bb22675284 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=169649002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.169649002 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1296911100 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2574636718 ps |
| CPU time | 75.51 seconds |
| Started | Feb 21 02:39:10 PM PST 24 |
| Finished | Feb 21 02:40:25 PM PST 24 |
| Peak memory | 206064 kb |
| Host | smart-b944b8e2-9d7b-4b8d-abeb-5c3b4815af6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1296911100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1296911100 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.2579884693 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 218373829 ps |
| CPU time | 123.92 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:41:20 PM PST 24 |
| Peak memory | 208076 kb |
| Host | smart-03036159-e3cb-4c1e-a4fc-eaaaf535ff6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2579884693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.2579884693 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.547971374 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1646127419 ps |
| CPU time | 229.66 seconds |
| Started | Feb 21 02:39:14 PM PST 24 |
| Finished | Feb 21 02:43:04 PM PST 24 |
| Peak memory | 208948 kb |
| Host | smart-fc17e246-05ab-4c06-b45f-a1d6d154ac3c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=547971374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_res et_error.547971374 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.1634400457 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 31561592 ps |
| CPU time | 4.52 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:39:21 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-068a2046-5190-49c7-b884-c127437cdeab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1634400457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1634400457 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3773090064 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1168509165 ps |
| CPU time | 45.29 seconds |
| Started | Feb 21 02:39:16 PM PST 24 |
| Finished | Feb 21 02:40:02 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-6ea2d1b8-d0d6-42e9-8e36-4239ad04b523 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3773090064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3773090064 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1360409239 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 94896851055 ps |
| CPU time | 362.16 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:45:19 PM PST 24 |
| Peak memory | 211332 kb |
| Host | smart-52ebb5b6-01bb-4bfa-80e2-d5dcb89cde72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1360409239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.1360409239 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1663789977 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1331030746 ps |
| CPU time | 13.19 seconds |
| Started | Feb 21 02:39:16 PM PST 24 |
| Finished | Feb 21 02:39:30 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-ffe339bf-c64b-4930-bc0e-45c328d18cb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1663789977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1663789977 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.1590033011 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 204675484 ps |
| CPU time | 13.75 seconds |
| Started | Feb 21 02:39:14 PM PST 24 |
| Finished | Feb 21 02:39:30 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-45cda682-2203-4f84-afa9-bc31234cbe59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1590033011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1590033011 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.793804433 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 219672935 ps |
| CPU time | 25.4 seconds |
| Started | Feb 21 02:39:11 PM PST 24 |
| Finished | Feb 21 02:39:38 PM PST 24 |
| Peak memory | 211224 kb |
| Host | smart-55ecdec4-3d10-4cfb-8186-3604a90c91f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=793804433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.793804433 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.1174163624 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 33505827556 ps |
| CPU time | 160.59 seconds |
| Started | Feb 21 02:39:14 PM PST 24 |
| Finished | Feb 21 02:41:57 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-d596e2e8-0e81-4ab8-982f-6e0aa72b1575 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174163624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1174163624 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2743525842 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 13697611102 ps |
| CPU time | 108.03 seconds |
| Started | Feb 21 02:39:17 PM PST 24 |
| Finished | Feb 21 02:41:06 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-1af49b27-a6e9-4867-a8ad-66b962883805 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2743525842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2743525842 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.2570153853 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 156424701 ps |
| CPU time | 19.52 seconds |
| Started | Feb 21 02:39:10 PM PST 24 |
| Finished | Feb 21 02:39:30 PM PST 24 |
| Peak memory | 204112 kb |
| Host | smart-f566f935-6a49-4095-838f-f46caf9339e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570153853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2570153853 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.354727462 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2145903395 ps |
| CPU time | 29.98 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:39:46 PM PST 24 |
| Peak memory | 202968 kb |
| Host | smart-0d7bbef4-f199-4f1d-8150-4e318a7ab02b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=354727462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.354727462 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.2976644997 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 132058035 ps |
| CPU time | 3.35 seconds |
| Started | Feb 21 02:39:19 PM PST 24 |
| Finished | Feb 21 02:39:23 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-0630634f-23ed-4652-bdd8-7bcd48e2acc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2976644997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2976644997 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2702633317 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 11642731392 ps |
| CPU time | 34.58 seconds |
| Started | Feb 21 02:39:24 PM PST 24 |
| Finished | Feb 21 02:39:59 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-a6a7f0a5-b5fb-4f15-8592-e47b8e42fd19 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702633317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2702633317 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.2559019372 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 10026207921 ps |
| CPU time | 31.18 seconds |
| Started | Feb 21 02:39:24 PM PST 24 |
| Finished | Feb 21 02:39:57 PM PST 24 |
| Peak memory | 203092 kb |
| Host | smart-5a604c00-c018-423b-9496-ed5c98c2ecf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2559019372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2559019372 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2920667444 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 35494702 ps |
| CPU time | 1.98 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:39:27 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-e4cdc644-72de-45f4-9c45-a570a0107649 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920667444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2920667444 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.3389102060 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8834811698 ps |
| CPU time | 202.42 seconds |
| Started | Feb 21 02:39:12 PM PST 24 |
| Finished | Feb 21 02:42:35 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-aee53110-021c-4155-8af8-7e0099a6c20b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3389102060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3389102060 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3322910730 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 1964284439 ps |
| CPU time | 80.01 seconds |
| Started | Feb 21 02:39:19 PM PST 24 |
| Finished | Feb 21 02:40:42 PM PST 24 |
| Peak memory | 203372 kb |
| Host | smart-6843dba7-120f-48ad-bcd6-fabcb9e4dcbd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3322910730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3322910730 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3086786836 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 532836087 ps |
| CPU time | 240.41 seconds |
| Started | Feb 21 02:39:16 PM PST 24 |
| Finished | Feb 21 02:43:18 PM PST 24 |
| Peak memory | 208384 kb |
| Host | smart-5f3db9fd-1d6f-4610-852f-7217e018ca35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3086786836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.3086786836 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.76979079 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1618475197 ps |
| CPU time | 247.91 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:43:33 PM PST 24 |
| Peak memory | 219428 kb |
| Host | smart-d830a913-d782-4604-98f1-7780aaa86087 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=76979079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rese t_error.76979079 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3955659821 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 370816290 ps |
| CPU time | 14.99 seconds |
| Started | Feb 21 02:39:18 PM PST 24 |
| Finished | Feb 21 02:39:33 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-c0bdaeff-e17a-49d3-8acb-0c3bd6b1a56d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3955659821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3955659821 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3348810298 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 634803053 ps |
| CPU time | 21.7 seconds |
| Started | Feb 21 02:39:19 PM PST 24 |
| Finished | Feb 21 02:39:43 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-40cf9231-94e8-4496-948b-b0dc4a2c5578 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3348810298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3348810298 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2172124050 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 74005621332 ps |
| CPU time | 155.27 seconds |
| Started | Feb 21 02:39:12 PM PST 24 |
| Finished | Feb 21 02:41:48 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-231400df-be3c-4814-9c83-589b223fe091 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2172124050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.2172124050 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2724114232 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 112343154 ps |
| CPU time | 13.64 seconds |
| Started | Feb 21 02:39:13 PM PST 24 |
| Finished | Feb 21 02:39:28 PM PST 24 |
| Peak memory | 203284 kb |
| Host | smart-2430e3f0-586c-4d2f-865f-a257aea371e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2724114232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2724114232 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.1894174263 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 69342105 ps |
| CPU time | 6.02 seconds |
| Started | Feb 21 02:39:18 PM PST 24 |
| Finished | Feb 21 02:39:24 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-4afbf31a-c53f-46c0-aa17-3e472929aaf6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1894174263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1894174263 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.2143766206 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 754664322 ps |
| CPU time | 14.6 seconds |
| Started | Feb 21 02:39:11 PM PST 24 |
| Finished | Feb 21 02:39:27 PM PST 24 |
| Peak memory | 204096 kb |
| Host | smart-dd54b034-ad88-4fed-acce-097cbe47c377 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2143766206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2143766206 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1298101504 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 9525338733 ps |
| CPU time | 63.78 seconds |
| Started | Feb 21 02:39:11 PM PST 24 |
| Finished | Feb 21 02:40:16 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-2de1d069-d642-4d13-8ef8-a6fe5b3efff6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298101504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1298101504 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1169333425 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 20749328615 ps |
| CPU time | 139.55 seconds |
| Started | Feb 21 02:39:13 PM PST 24 |
| Finished | Feb 21 02:41:33 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-46533da1-f9ca-48df-9175-41ff200d358a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1169333425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1169333425 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.3119505515 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 515364534 ps |
| CPU time | 23.5 seconds |
| Started | Feb 21 02:39:11 PM PST 24 |
| Finished | Feb 21 02:39:34 PM PST 24 |
| Peak memory | 204076 kb |
| Host | smart-392b4666-f630-4a92-bb31-2721762146f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119505515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3119505515 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.1102941568 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1024145214 ps |
| CPU time | 24.48 seconds |
| Started | Feb 21 02:39:09 PM PST 24 |
| Finished | Feb 21 02:39:34 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-b38f30ef-8190-44d3-8f8a-1c1c47d7764e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1102941568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1102941568 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.2859769062 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 36088088 ps |
| CPU time | 2.71 seconds |
| Started | Feb 21 02:39:18 PM PST 24 |
| Finished | Feb 21 02:39:21 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-57323cb9-3840-43ee-8a22-e7b7e2e15567 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2859769062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2859769062 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1903471399 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 5357065520 ps |
| CPU time | 28.01 seconds |
| Started | Feb 21 02:39:12 PM PST 24 |
| Finished | Feb 21 02:39:41 PM PST 24 |
| Peak memory | 203044 kb |
| Host | smart-4dde9817-8531-4f39-a58d-f54f6ee74fc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903471399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1903471399 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.293654716 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 6259491189 ps |
| CPU time | 28.37 seconds |
| Started | Feb 21 02:39:13 PM PST 24 |
| Finished | Feb 21 02:39:43 PM PST 24 |
| Peak memory | 203020 kb |
| Host | smart-1e841e28-6869-4ac0-a75b-c8e81fd6b0a5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=293654716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.293654716 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.200501048 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 50682160 ps |
| CPU time | 2.39 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:39:28 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-d00f2e7c-5461-49fd-be57-c38f161c64da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200501048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.200501048 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2571388536 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4058810052 ps |
| CPU time | 116.67 seconds |
| Started | Feb 21 02:39:25 PM PST 24 |
| Finished | Feb 21 02:41:23 PM PST 24 |
| Peak memory | 206564 kb |
| Host | smart-89decde1-1ca5-4b2c-8bf6-33ec220f656c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2571388536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2571388536 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1363308708 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1160994121 ps |
| CPU time | 113.49 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:41:18 PM PST 24 |
| Peak memory | 205748 kb |
| Host | smart-dd735116-0c06-49ff-b835-4af62a17382e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1363308708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1363308708 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1753087548 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 6584444870 ps |
| CPU time | 351.2 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:45:15 PM PST 24 |
| Peak memory | 207980 kb |
| Host | smart-528df298-c3f6-46b4-9eb9-60cfe9568e4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1753087548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.1753087548 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.758989675 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1426328118 ps |
| CPU time | 144.27 seconds |
| Started | Feb 21 02:39:16 PM PST 24 |
| Finished | Feb 21 02:41:41 PM PST 24 |
| Peak memory | 208644 kb |
| Host | smart-6cd729a0-2dbc-4e0a-a64c-a1d062ee8495 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=758989675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_res et_error.758989675 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.628671322 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 64011278 ps |
| CPU time | 7.18 seconds |
| Started | Feb 21 02:39:12 PM PST 24 |
| Finished | Feb 21 02:39:20 PM PST 24 |
| Peak memory | 204320 kb |
| Host | smart-59c33b41-6462-462f-9c66-aa8eb32b1960 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=628671322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.628671322 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.44003314 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 425713068 ps |
| CPU time | 28.08 seconds |
| Started | Feb 21 02:39:25 PM PST 24 |
| Finished | Feb 21 02:39:54 PM PST 24 |
| Peak memory | 204352 kb |
| Host | smart-8a7aaf84-647d-4cb6-b55a-34e774e6ef7c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=44003314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.44003314 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2085380315 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 261857963 ps |
| CPU time | 2.59 seconds |
| Started | Feb 21 02:39:25 PM PST 24 |
| Finished | Feb 21 02:39:29 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-0b285f07-6c8a-4d8c-affd-eabfb06b5de6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2085380315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2085380315 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.3919383836 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 40971143 ps |
| CPU time | 5.29 seconds |
| Started | Feb 21 02:39:25 PM PST 24 |
| Finished | Feb 21 02:39:32 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-a6a04205-c1f3-4211-a428-3698cb227706 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3919383836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3919383836 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.2933315631 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3286913380 ps |
| CPU time | 22.77 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:39:39 PM PST 24 |
| Peak memory | 204136 kb |
| Host | smart-206b8b08-3ef2-4a27-ac90-6ebb3fe7371c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2933315631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2933315631 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1657664757 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 59432373824 ps |
| CPU time | 108.92 seconds |
| Started | Feb 21 02:39:20 PM PST 24 |
| Finished | Feb 21 02:41:12 PM PST 24 |
| Peak memory | 204268 kb |
| Host | smart-ce6af259-aded-44d2-aca2-e1187d62e0e3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657664757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1657664757 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2623457193 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 72435554762 ps |
| CPU time | 209.28 seconds |
| Started | Feb 21 02:39:19 PM PST 24 |
| Finished | Feb 21 02:42:52 PM PST 24 |
| Peak memory | 211120 kb |
| Host | smart-13f6617c-a320-45f5-9ba9-5f9c91181a16 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2623457193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2623457193 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.3451446988 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 161612312 ps |
| CPU time | 14.17 seconds |
| Started | Feb 21 02:39:19 PM PST 24 |
| Finished | Feb 21 02:39:37 PM PST 24 |
| Peak memory | 204132 kb |
| Host | smart-33ed752c-2697-4340-bff4-7d70f3c2243f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451446988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.3451446988 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.3467228943 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 721475027 ps |
| CPU time | 13.06 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:39:29 PM PST 24 |
| Peak memory | 203696 kb |
| Host | smart-03e881dd-199b-429b-bc1d-bf0e98ef931f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3467228943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3467228943 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.1351693951 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 34884428 ps |
| CPU time | 2.56 seconds |
| Started | Feb 21 02:39:11 PM PST 24 |
| Finished | Feb 21 02:39:15 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-1f029a45-0b30-4d2b-933e-500fe51aaecd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1351693951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1351693951 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.427591491 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 24254223343 ps |
| CPU time | 38.94 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:40:03 PM PST 24 |
| Peak memory | 203104 kb |
| Host | smart-8a4b116b-cad5-400c-b9e6-d3e9357fe03d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=427591491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.427591491 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.2784598431 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 5203465940 ps |
| CPU time | 30.4 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:39:47 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-fe3a6cd3-b1de-481b-b860-a77d230f9023 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2784598431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2784598431 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.2368192394 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 64112388 ps |
| CPU time | 2.51 seconds |
| Started | Feb 21 02:39:18 PM PST 24 |
| Finished | Feb 21 02:39:21 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-4e907d8a-1ab0-4d2c-a7b4-654378981348 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368192394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.2368192394 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.2027318794 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 678645727 ps |
| CPU time | 97.6 seconds |
| Started | Feb 21 02:39:12 PM PST 24 |
| Finished | Feb 21 02:40:50 PM PST 24 |
| Peak memory | 207128 kb |
| Host | smart-27802684-1d89-441b-836c-d9c5225f321c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2027318794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2027318794 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3597343787 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2238613753 ps |
| CPU time | 131.09 seconds |
| Started | Feb 21 02:39:27 PM PST 24 |
| Finished | Feb 21 02:41:40 PM PST 24 |
| Peak memory | 205236 kb |
| Host | smart-8d623cee-9454-49ee-b1cc-1b0c164866ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3597343787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3597343787 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1879910102 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1569719130 ps |
| CPU time | 221.96 seconds |
| Started | Feb 21 02:39:28 PM PST 24 |
| Finished | Feb 21 02:43:11 PM PST 24 |
| Peak memory | 207692 kb |
| Host | smart-6a4f5c40-27ba-45c6-b614-8050608d84fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1879910102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.1879910102 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3221354251 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 81158881 ps |
| CPU time | 16.96 seconds |
| Started | Feb 21 02:39:26 PM PST 24 |
| Finished | Feb 21 02:39:44 PM PST 24 |
| Peak memory | 204308 kb |
| Host | smart-13e3aadd-4220-4ed1-9b8e-5163242ac3e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3221354251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.3221354251 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.574127532 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 1234854035 ps |
| CPU time | 12.05 seconds |
| Started | Feb 21 02:39:15 PM PST 24 |
| Finished | Feb 21 02:39:28 PM PST 24 |
| Peak memory | 204276 kb |
| Host | smart-f4d0da45-9263-4a7c-83fa-0232d29c8b2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=574127532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.574127532 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1585576389 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2491916365 ps |
| CPU time | 47.43 seconds |
| Started | Feb 21 02:39:27 PM PST 24 |
| Finished | Feb 21 02:40:16 PM PST 24 |
| Peak memory | 205072 kb |
| Host | smart-a4533775-58b9-432e-8af3-17ab100b1550 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1585576389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1585576389 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3329347808 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 168043505648 ps |
| CPU time | 578.79 seconds |
| Started | Feb 21 02:39:26 PM PST 24 |
| Finished | Feb 21 02:49:06 PM PST 24 |
| Peak memory | 206772 kb |
| Host | smart-78276ebf-df9e-4e54-9364-78a26b884afd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3329347808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.3329347808 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2275000998 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 532709803 ps |
| CPU time | 20.66 seconds |
| Started | Feb 21 02:39:22 PM PST 24 |
| Finished | Feb 21 02:39:45 PM PST 24 |
| Peak memory | 203376 kb |
| Host | smart-26360f06-1bb9-41ea-b068-f396b9b8736d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2275000998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2275000998 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.3549669666 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1986632290 ps |
| CPU time | 34.55 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:39:59 PM PST 24 |
| Peak memory | 203004 kb |
| Host | smart-7bd64b69-958b-47d8-a61e-827ae2f1188e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3549669666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3549669666 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.1594432860 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 130758884 ps |
| CPU time | 13.88 seconds |
| Started | Feb 21 02:39:24 PM PST 24 |
| Finished | Feb 21 02:39:39 PM PST 24 |
| Peak memory | 204124 kb |
| Host | smart-3bb21dab-410b-4201-8173-ea11b74e7548 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1594432860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.1594432860 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.2814166990 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 167407166761 ps |
| CPU time | 325.56 seconds |
| Started | Feb 21 02:39:29 PM PST 24 |
| Finished | Feb 21 02:44:56 PM PST 24 |
| Peak memory | 211300 kb |
| Host | smart-7af6f5ab-7906-4513-8e52-aab167321c9b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814166990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2814166990 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.1866540376 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 33722664531 ps |
| CPU time | 169.15 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:42:14 PM PST 24 |
| Peak memory | 211220 kb |
| Host | smart-5dd4e252-518c-4d9e-a0e5-e829826b0a76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1866540376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1866540376 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2645514688 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 79861036 ps |
| CPU time | 6.29 seconds |
| Started | Feb 21 02:39:27 PM PST 24 |
| Finished | Feb 21 02:39:35 PM PST 24 |
| Peak memory | 204144 kb |
| Host | smart-02208a53-5414-4b70-8cc9-6f859eb441c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645514688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2645514688 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.1644657284 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 290819573 ps |
| CPU time | 20.25 seconds |
| Started | Feb 21 02:39:24 PM PST 24 |
| Finished | Feb 21 02:39:46 PM PST 24 |
| Peak memory | 203416 kb |
| Host | smart-76fa3667-306f-47ff-92fc-06505be40067 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1644657284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1644657284 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.3966023715 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 56926417 ps |
| CPU time | 2.26 seconds |
| Started | Feb 21 02:39:22 PM PST 24 |
| Finished | Feb 21 02:39:26 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-279c2302-06a7-499c-b3de-32c84aa030d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3966023715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3966023715 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.414334758 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 8235684515 ps |
| CPU time | 30.52 seconds |
| Started | Feb 21 02:39:28 PM PST 24 |
| Finished | Feb 21 02:39:59 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-c99870f2-a66f-4bfc-b0f2-94f942faf650 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=414334758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.414334758 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.249383255 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 5302073230 ps |
| CPU time | 28 seconds |
| Started | Feb 21 02:39:21 PM PST 24 |
| Finished | Feb 21 02:39:52 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-e21854ad-15d5-41f8-b8ff-adc61ddd73dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=249383255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.249383255 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1113287449 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 27752696 ps |
| CPU time | 2.57 seconds |
| Started | Feb 21 02:39:24 PM PST 24 |
| Finished | Feb 21 02:39:28 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-9d74bdd4-6b68-4d48-b27b-ee2ae4d69a20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113287449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1113287449 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1902620799 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 8445512604 ps |
| CPU time | 132.77 seconds |
| Started | Feb 21 02:39:28 PM PST 24 |
| Finished | Feb 21 02:41:41 PM PST 24 |
| Peak memory | 206172 kb |
| Host | smart-9fedbcb5-854c-4a1b-b3e8-88fa173c8c5a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1902620799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1902620799 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3351993510 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 494739630 ps |
| CPU time | 221.53 seconds |
| Started | Feb 21 02:39:25 PM PST 24 |
| Finished | Feb 21 02:43:08 PM PST 24 |
| Peak memory | 209320 kb |
| Host | smart-131592f8-8ee5-4889-9e53-f3dcd5d550f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3351993510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.3351993510 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.3839838593 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 957659148 ps |
| CPU time | 37.48 seconds |
| Started | Feb 21 02:39:26 PM PST 24 |
| Finished | Feb 21 02:40:06 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-701ef7cd-a3cc-4294-a0d9-0a1851d98d31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3839838593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3839838593 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1414365088 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 356058773 ps |
| CPU time | 15.61 seconds |
| Started | Feb 21 02:39:44 PM PST 24 |
| Finished | Feb 21 02:40:01 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-cfdd40ad-e2af-402d-9c34-789889e21927 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1414365088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1414365088 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.2324258732 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 115077287432 ps |
| CPU time | 451.29 seconds |
| Started | Feb 21 02:39:36 PM PST 24 |
| Finished | Feb 21 02:47:09 PM PST 24 |
| Peak memory | 211280 kb |
| Host | smart-82aaf618-46fc-4932-99dd-fd6a48874f6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2324258732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.2324258732 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.924213162 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1074179154 ps |
| CPU time | 18.72 seconds |
| Started | Feb 21 02:39:35 PM PST 24 |
| Finished | Feb 21 02:39:54 PM PST 24 |
| Peak memory | 203284 kb |
| Host | smart-ca367826-02eb-4ecb-b862-992a2ac30235 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=924213162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.924213162 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.905856188 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1020263507 ps |
| CPU time | 12.55 seconds |
| Started | Feb 21 02:39:40 PM PST 24 |
| Finished | Feb 21 02:39:53 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-cc2007d7-adab-46b6-959d-3f129913e230 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=905856188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.905856188 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.1141687677 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 617212069 ps |
| CPU time | 14.95 seconds |
| Started | Feb 21 02:39:34 PM PST 24 |
| Finished | Feb 21 02:39:50 PM PST 24 |
| Peak memory | 211240 kb |
| Host | smart-a4752a58-d850-4d03-8c6d-59de7c322d1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1141687677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1141687677 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.902903367 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 35043873387 ps |
| CPU time | 229.07 seconds |
| Started | Feb 21 02:39:44 PM PST 24 |
| Finished | Feb 21 02:43:35 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-8487bd97-70d5-47a5-b1eb-6d7438a168ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=902903367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.902903367 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.796163999 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 43679256546 ps |
| CPU time | 244.82 seconds |
| Started | Feb 21 02:39:34 PM PST 24 |
| Finished | Feb 21 02:43:40 PM PST 24 |
| Peak memory | 211264 kb |
| Host | smart-73fcfd75-a2c3-4ae9-9b1c-8342f6839230 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=796163999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.796163999 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1449539534 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 310879021 ps |
| CPU time | 26.18 seconds |
| Started | Feb 21 02:39:38 PM PST 24 |
| Finished | Feb 21 02:40:04 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-ef646431-4e4c-42d2-bf19-fa2b4a661557 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449539534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1449539534 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.2423092366 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1208526267 ps |
| CPU time | 12.46 seconds |
| Started | Feb 21 02:39:34 PM PST 24 |
| Finished | Feb 21 02:39:47 PM PST 24 |
| Peak memory | 203024 kb |
| Host | smart-a4757f7b-d93f-43b4-9d71-82aeaef97acd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2423092366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2423092366 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.4253632453 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 815027395 ps |
| CPU time | 4.59 seconds |
| Started | Feb 21 02:39:26 PM PST 24 |
| Finished | Feb 21 02:39:32 PM PST 24 |
| Peak memory | 203088 kb |
| Host | smart-3e92b06a-b181-4fc3-baa0-6cddebdb13aa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4253632453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.4253632453 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4207105816 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 5183801115 ps |
| CPU time | 32.02 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:39:56 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-0f81c767-3bdb-4d57-8a47-c15dece72f41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207105816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.4207105816 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2808966124 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3867851812 ps |
| CPU time | 23.89 seconds |
| Started | Feb 21 02:39:28 PM PST 24 |
| Finished | Feb 21 02:39:53 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-db93f5b9-006e-403b-bc7b-1fe56b049bdb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2808966124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2808966124 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2741481657 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 73709076 ps |
| CPU time | 2.34 seconds |
| Started | Feb 21 02:39:23 PM PST 24 |
| Finished | Feb 21 02:39:28 PM PST 24 |
| Peak memory | 203016 kb |
| Host | smart-d523daca-ef94-4411-9445-205cddabeeee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741481657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2741481657 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.3845062763 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3239692300 ps |
| CPU time | 76.83 seconds |
| Started | Feb 21 02:39:37 PM PST 24 |
| Finished | Feb 21 02:40:54 PM PST 24 |
| Peak memory | 207400 kb |
| Host | smart-2daedf27-16b6-4b4b-aa27-3544d31b604a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3845062763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3845062763 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2605052904 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 492908140 ps |
| CPU time | 49.85 seconds |
| Started | Feb 21 02:39:38 PM PST 24 |
| Finished | Feb 21 02:40:28 PM PST 24 |
| Peak memory | 203864 kb |
| Host | smart-a6a57980-e9b5-40fc-b4b7-7a369d847d33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2605052904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2605052904 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.2651359451 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 552003307 ps |
| CPU time | 226.38 seconds |
| Started | Feb 21 02:39:33 PM PST 24 |
| Finished | Feb 21 02:43:21 PM PST 24 |
| Peak memory | 209368 kb |
| Host | smart-b32b7404-808d-4d81-a678-e01cf96f42c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2651359451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.2651359451 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2084392934 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3716488560 ps |
| CPU time | 226.3 seconds |
| Started | Feb 21 02:39:33 PM PST 24 |
| Finished | Feb 21 02:43:20 PM PST 24 |
| Peak memory | 210492 kb |
| Host | smart-e206b69e-89b7-41a3-a5bb-399e5c171464 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2084392934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.2084392934 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.2092298043 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 157474959 ps |
| CPU time | 6.78 seconds |
| Started | Feb 21 02:39:34 PM PST 24 |
| Finished | Feb 21 02:39:42 PM PST 24 |
| Peak memory | 204348 kb |
| Host | smart-b974bb45-a233-4b4e-b98f-7a1d8c094956 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2092298043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2092298043 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1865867807 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1487274747 ps |
| CPU time | 57.74 seconds |
| Started | Feb 21 02:35:52 PM PST 24 |
| Finished | Feb 21 02:36:50 PM PST 24 |
| Peak memory | 205332 kb |
| Host | smart-d4ec7882-8bd7-4f2c-b22f-045cf0a00fa8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1865867807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1865867807 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2891819910 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 37569787571 ps |
| CPU time | 234.68 seconds |
| Started | Feb 21 02:35:56 PM PST 24 |
| Finished | Feb 21 02:39:53 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-34fe3fc3-c9ba-4fa3-8ba1-bc6181f984cd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2891819910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.2891819910 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.446359124 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 833421223 ps |
| CPU time | 24.83 seconds |
| Started | Feb 21 02:35:53 PM PST 24 |
| Finished | Feb 21 02:36:18 PM PST 24 |
| Peak memory | 203096 kb |
| Host | smart-6caeb917-04c3-48c7-9181-69c39143ed4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=446359124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.446359124 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.2479389909 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 75822019 ps |
| CPU time | 7.37 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:04 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-6f85427e-bdc4-46ff-95eb-252f7caa9a93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2479389909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2479389909 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.3152255000 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 215294040 ps |
| CPU time | 10.92 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:07 PM PST 24 |
| Peak memory | 204432 kb |
| Host | smart-1e91487f-1847-4e8a-b9c1-4073e92ea8be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3152255000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3152255000 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.539865427 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 33628512945 ps |
| CPU time | 113.99 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:37:58 PM PST 24 |
| Peak memory | 211272 kb |
| Host | smart-76f60beb-c574-4d17-8f5e-d9d2b74dee8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=539865427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.539865427 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2846753792 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 21079150315 ps |
| CPU time | 163.77 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:38:45 PM PST 24 |
| Peak memory | 211248 kb |
| Host | smart-29a51ec5-3e3e-469e-85e5-66833e5804ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2846753792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2846753792 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3448382551 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 412679029 ps |
| CPU time | 16.83 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:17 PM PST 24 |
| Peak memory | 204340 kb |
| Host | smart-67dedb3a-a2c9-4ddb-a8c0-2f045eaadec9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448382551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3448382551 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.2414777597 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1957015615 ps |
| CPU time | 20.48 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:16 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-f1973ef0-89ab-439f-858e-6f8132b8ef30 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2414777597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2414777597 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.2214468767 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 144637997 ps |
| CPU time | 3.78 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:00 PM PST 24 |
| Peak memory | 202896 kb |
| Host | smart-76c8c95b-18b6-4852-b4ea-8bbf8009b211 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2214468767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2214468767 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.745295119 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 10477774693 ps |
| CPU time | 33.4 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:31 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-850cf65f-33ce-454c-8951-f6942cd161fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=745295119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.745295119 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1870944710 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 7136239251 ps |
| CPU time | 28.86 seconds |
| Started | Feb 21 02:35:51 PM PST 24 |
| Finished | Feb 21 02:36:21 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-723ca3c1-780a-4f13-bd55-3d2f83da802b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1870944710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1870944710 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.566402423 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 25981680 ps |
| CPU time | 2.28 seconds |
| Started | Feb 21 02:35:53 PM PST 24 |
| Finished | Feb 21 02:35:56 PM PST 24 |
| Peak memory | 202964 kb |
| Host | smart-a307b0c7-2e3a-4456-9ea0-d464e3f74ddc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566402423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.566402423 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.1325798399 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 1358719646 ps |
| CPU time | 53.58 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:49 PM PST 24 |
| Peak memory | 204992 kb |
| Host | smart-557ba2ae-233a-4026-b988-72613bbed528 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1325798399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1325798399 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2215528738 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 16321292290 ps |
| CPU time | 268.22 seconds |
| Started | Feb 21 02:35:52 PM PST 24 |
| Finished | Feb 21 02:40:21 PM PST 24 |
| Peak memory | 206596 kb |
| Host | smart-189f98ba-24ec-4b2c-ab4c-2d916b05f26a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2215528738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2215528738 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1793309029 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 568280398 ps |
| CPU time | 172.16 seconds |
| Started | Feb 21 02:35:54 PM PST 24 |
| Finished | Feb 21 02:38:46 PM PST 24 |
| Peak memory | 208404 kb |
| Host | smart-81ffd8ba-66b7-4c25-a2ff-229a42d099ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1793309029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.1793309029 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.1590447579 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1540518912 ps |
| CPU time | 231.5 seconds |
| Started | Feb 21 02:35:56 PM PST 24 |
| Finished | Feb 21 02:39:51 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-64cdff62-1bd8-49ba-85af-48b0cc7d569b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1590447579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.1590447579 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.316152192 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 5481610995 ps |
| CPU time | 32.31 seconds |
| Started | Feb 21 02:35:52 PM PST 24 |
| Finished | Feb 21 02:36:25 PM PST 24 |
| Peak memory | 204816 kb |
| Host | smart-96434228-dafb-4384-a162-8113ceb0dea8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=316152192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.316152192 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.702187557 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 643278989 ps |
| CPU time | 37.34 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:36:39 PM PST 24 |
| Peak memory | 205188 kb |
| Host | smart-0246c6dc-4554-402b-bcba-8652667ee118 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=702187557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.702187557 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3479322397 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 97181892904 ps |
| CPU time | 737.21 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:48:14 PM PST 24 |
| Peak memory | 211296 kb |
| Host | smart-dff8f289-efcc-4288-b2c5-f05b2fdd32b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3479322397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo w_rsp.3479322397 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3974690825 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 620659354 ps |
| CPU time | 12.57 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:36:14 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-46386167-4087-49b3-869c-b9fe7abc185b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3974690825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3974690825 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.1822653909 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 236206151 ps |
| CPU time | 19.49 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:20 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-cee4b5fb-71ed-4f0f-b59f-e0e8e15c93a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1822653909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1822653909 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.3574057787 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 625933497 ps |
| CPU time | 21.09 seconds |
| Started | Feb 21 02:35:54 PM PST 24 |
| Finished | Feb 21 02:36:16 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-b10a27ef-6c47-4292-b945-1a9d29104308 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3574057787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3574057787 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.1626451033 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 138069300948 ps |
| CPU time | 260.73 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:40:25 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-9cd85e71-2db9-418e-9d68-9ed43e0c2f75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626451033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1626451033 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.283142565 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 41897502804 ps |
| CPU time | 276.01 seconds |
| Started | Feb 21 02:35:51 PM PST 24 |
| Finished | Feb 21 02:40:27 PM PST 24 |
| Peak memory | 211248 kb |
| Host | smart-b41c8b33-72aa-494c-b9f8-720415127175 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=283142565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.283142565 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3309204175 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 53033280 ps |
| CPU time | 4.41 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:03 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-89c8e085-84f8-48a6-8ec5-a65a27fe93c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309204175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3309204175 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.3656602460 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 36562426 ps |
| CPU time | 2.11 seconds |
| Started | Feb 21 02:35:48 PM PST 24 |
| Finished | Feb 21 02:35:53 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-8f53576f-98bb-4797-95e3-af04e0f0059c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3656602460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3656602460 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.2265392058 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 45471483 ps |
| CPU time | 2.61 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:36:05 PM PST 24 |
| Peak memory | 203020 kb |
| Host | smart-7f62fdb4-f1b4-40ec-b48b-5ddf1e6367f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2265392058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2265392058 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.4043174889 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 5449893603 ps |
| CPU time | 34.37 seconds |
| Started | Feb 21 02:35:55 PM PST 24 |
| Finished | Feb 21 02:36:30 PM PST 24 |
| Peak memory | 202976 kb |
| Host | smart-434f0004-6033-425a-ac6c-d7228657667c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043174889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4043174889 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.1476906403 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 9062390808 ps |
| CPU time | 33.6 seconds |
| Started | Feb 21 02:35:56 PM PST 24 |
| Finished | Feb 21 02:36:32 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-75585123-acd5-4392-80a3-41a3e693dd66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1476906403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1476906403 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3034660854 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 44095090 ps |
| CPU time | 2.74 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:36:05 PM PST 24 |
| Peak memory | 203036 kb |
| Host | smart-ae0ae991-373b-4199-93c8-69f5232d802f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034660854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3034660854 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2615626429 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 5313777684 ps |
| CPU time | 215.34 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:39:37 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-84f9f05f-88e3-4be0-8597-231c92072bb8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2615626429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2615626429 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.866669008 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 402304562 ps |
| CPU time | 52.58 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:56 PM PST 24 |
| Peak memory | 204784 kb |
| Host | smart-f5221062-cf78-4d34-854c-604706fb580b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=866669008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.866669008 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1248652030 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2751034862 ps |
| CPU time | 436.92 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:43:21 PM PST 24 |
| Peak memory | 209288 kb |
| Host | smart-32955315-d883-439f-a6f2-5769d811ec2f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1248652030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.1248652030 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3652990923 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 824972785 ps |
| CPU time | 107.54 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:37:49 PM PST 24 |
| Peak memory | 206120 kb |
| Host | smart-fb793e53-7c51-4e95-87b2-9f2dc85bc18a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3652990923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.3652990923 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.405481788 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 605031146 ps |
| CPU time | 20.53 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:21 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-9394f2d9-3bc6-4a84-893a-650d4c1f4bcc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=405481788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.405481788 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1737703219 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 406308553 ps |
| CPU time | 15.03 seconds |
| Started | Feb 21 02:36:11 PM PST 24 |
| Finished | Feb 21 02:36:26 PM PST 24 |
| Peak memory | 204916 kb |
| Host | smart-fc55a72c-c381-4a2c-88ad-813870fb85f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1737703219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1737703219 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.549521669 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 69907805107 ps |
| CPU time | 290.91 seconds |
| Started | Feb 21 02:36:02 PM PST 24 |
| Finished | Feb 21 02:40:57 PM PST 24 |
| Peak memory | 211272 kb |
| Host | smart-82d6ff90-2f8d-4e6b-8b0b-0e9290893b25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=549521669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow _rsp.549521669 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2809676519 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 158856756 ps |
| CPU time | 5.4 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:11 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-a79386cb-3dcf-47d2-a606-98f278c9e655 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2809676519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2809676519 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2414337409 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 149231573 ps |
| CPU time | 6.43 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:12 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-498520ac-4462-4f1d-9b8c-368e081b96d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2414337409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2414337409 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.1602668185 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 757577298 ps |
| CPU time | 16.18 seconds |
| Started | Feb 21 02:36:05 PM PST 24 |
| Finished | Feb 21 02:36:23 PM PST 24 |
| Peak memory | 211232 kb |
| Host | smart-dcb5e225-099a-40fe-9860-1c15695b31dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1602668185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1602668185 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1004429713 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 28439397543 ps |
| CPU time | 169.87 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:39:01 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-52754f25-89af-4d84-8421-3dc1cfc55b11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004429713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1004429713 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.762222108 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 13534534279 ps |
| CPU time | 111.27 seconds |
| Started | Feb 21 02:36:05 PM PST 24 |
| Finished | Feb 21 02:37:58 PM PST 24 |
| Peak memory | 204296 kb |
| Host | smart-c95cb3eb-4363-4f2b-b492-ffad3997e53a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=762222108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.762222108 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.4137472250 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 234504574 ps |
| CPU time | 23.07 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:29 PM PST 24 |
| Peak memory | 203176 kb |
| Host | smart-4038e1cc-b6ee-4aab-bf48-9c2403f87fed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137472250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.4137472250 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.2172638245 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 102181862 ps |
| CPU time | 7.76 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:36:14 PM PST 24 |
| Peak memory | 203568 kb |
| Host | smart-afbf2ae8-7bca-4cce-9bb2-3d51c544cda1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2172638245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2172638245 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.3157476523 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 81089325 ps |
| CPU time | 2.06 seconds |
| Started | Feb 21 02:36:05 PM PST 24 |
| Finished | Feb 21 02:36:09 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-59a96867-3282-423e-9f8b-87144bceb9d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3157476523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3157476523 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3140303584 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 28347239741 ps |
| CPU time | 46.71 seconds |
| Started | Feb 21 02:36:02 PM PST 24 |
| Finished | Feb 21 02:36:52 PM PST 24 |
| Peak memory | 203104 kb |
| Host | smart-b81ef789-80a9-4d9c-ae02-7aa426573ec5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140303584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3140303584 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.3092124936 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 3577190190 ps |
| CPU time | 30.66 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:41 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-36b93bf2-c0b9-4d04-aa75-7b4897d85eab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3092124936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3092124936 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2237538225 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 71829132 ps |
| CPU time | 2.32 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:36:08 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-a12d560f-5341-49a3-a5a7-9f55abde35a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237538225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2237538225 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.3406286850 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 6361679533 ps |
| CPU time | 125.88 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:38:16 PM PST 24 |
| Peak memory | 208196 kb |
| Host | smart-69fc5a26-abc0-4e36-9740-002c6b256462 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3406286850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3406286850 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1911801597 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1770927070 ps |
| CPU time | 62.31 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:37:13 PM PST 24 |
| Peak memory | 205208 kb |
| Host | smart-9ebf8de2-de14-4cb1-88e1-4fe8205d01e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1911801597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1911801597 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.931764599 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 558659574 ps |
| CPU time | 242.87 seconds |
| Started | Feb 21 02:36:15 PM PST 24 |
| Finished | Feb 21 02:40:18 PM PST 24 |
| Peak memory | 209600 kb |
| Host | smart-f69cd602-91ff-4ce6-b966-89e36dfd7cb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=931764599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_ reset.931764599 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3127030216 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 107798129 ps |
| CPU time | 28.7 seconds |
| Started | Feb 21 02:36:18 PM PST 24 |
| Finished | Feb 21 02:36:49 PM PST 24 |
| Peak memory | 205520 kb |
| Host | smart-0a5db213-f6d7-44bd-a1cd-33610f72ed31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3127030216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.3127030216 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.909341731 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 408614924 ps |
| CPU time | 15.92 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:36:22 PM PST 24 |
| Peak memory | 210816 kb |
| Host | smart-257bc9ba-a783-40f6-8751-e7b227742e21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=909341731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.909341731 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.513263942 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8052998549 ps |
| CPU time | 49.45 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:50 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-73d67fbf-a2a0-45bd-8dbc-41660419357f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=513263942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.513263942 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.3050375439 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 183804340047 ps |
| CPU time | 375.25 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:42:18 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-ac04bcb1-a6e4-4cf1-9a16-64a28f9df962 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3050375439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.3050375439 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.848779060 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 611545864 ps |
| CPU time | 22.37 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:28 PM PST 24 |
| Peak memory | 202720 kb |
| Host | smart-b049f2bb-ee96-4745-a0cc-da744a30c2a4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=848779060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.848779060 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.335584262 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1530763786 ps |
| CPU time | 26.1 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:30 PM PST 24 |
| Peak memory | 202952 kb |
| Host | smart-e5614fae-55ec-4b48-a97f-d52184a31314 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=335584262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.335584262 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.4243592711 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 796581034 ps |
| CPU time | 22.87 seconds |
| Started | Feb 21 02:36:21 PM PST 24 |
| Finished | Feb 21 02:36:44 PM PST 24 |
| Peak memory | 204300 kb |
| Host | smart-6aa25829-ddf1-4ebe-a143-2406325444e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4243592711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.4243592711 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2512850946 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 43468617539 ps |
| CPU time | 55.43 seconds |
| Started | Feb 21 02:36:05 PM PST 24 |
| Finished | Feb 21 02:37:02 PM PST 24 |
| Peak memory | 204232 kb |
| Host | smart-f3788cc5-83ce-4141-981f-9861ce5a98d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512850946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2512850946 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.529325233 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 82728853594 ps |
| CPU time | 264.21 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:40:27 PM PST 24 |
| Peak memory | 204460 kb |
| Host | smart-8925682b-f59b-4369-9fb7-e0fbc305ded7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=529325233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.529325233 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.1971230943 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 160225781 ps |
| CPU time | 21.86 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:36:25 PM PST 24 |
| Peak memory | 204192 kb |
| Host | smart-8c672d05-35da-4beb-863a-fc5b8f50ad8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971230943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1971230943 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.820587869 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 26934790 ps |
| CPU time | 2.43 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:36:05 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-3e330f29-7cd0-407d-aae3-b924a8837d50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=820587869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.820587869 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.4279131443 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 87404404 ps |
| CPU time | 2.29 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:36:08 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-6cbd6993-d764-4635-a8ce-0b5370144229 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4279131443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.4279131443 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.584097077 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 8708237099 ps |
| CPU time | 32.19 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:38 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-a3f874df-8c60-405c-89b7-31da78dc9256 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=584097077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.584097077 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.232596742 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4482726725 ps |
| CPU time | 26.71 seconds |
| Started | Feb 21 02:36:26 PM PST 24 |
| Finished | Feb 21 02:36:53 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-438a6507-241c-43e2-a927-e268b82e5542 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=232596742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.232596742 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1385972725 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 33746460 ps |
| CPU time | 2.49 seconds |
| Started | Feb 21 02:36:10 PM PST 24 |
| Finished | Feb 21 02:36:13 PM PST 24 |
| Peak memory | 203036 kb |
| Host | smart-9a2f7c1d-be56-4a41-895b-28e84ae10a50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385972725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1385972725 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.887989034 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 545266296 ps |
| CPU time | 74.64 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:37:17 PM PST 24 |
| Peak memory | 205828 kb |
| Host | smart-d5cf76c0-abdd-4968-8a47-d560db9b2d25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=887989034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.887989034 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.252107860 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 578534796 ps |
| CPU time | 30.31 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:36:32 PM PST 24 |
| Peak memory | 204368 kb |
| Host | smart-73e976de-6743-4ab4-9aa3-4ceea3577dc1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=252107860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.252107860 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2982641389 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2527358040 ps |
| CPU time | 185.4 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:39:05 PM PST 24 |
| Peak memory | 208524 kb |
| Host | smart-ec98e6f7-7212-4a30-b8a3-aa7fe5dcf4fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2982641389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.2982641389 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2400838729 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 5308396210 ps |
| CPU time | 44.91 seconds |
| Started | Feb 21 02:35:59 PM PST 24 |
| Finished | Feb 21 02:36:47 PM PST 24 |
| Peak memory | 205632 kb |
| Host | smart-ea448851-8eac-4a4a-927b-a33ef4b0d8d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2400838729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2400838729 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3940962024 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 557167336 ps |
| CPU time | 20.83 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:27 PM PST 24 |
| Peak memory | 211232 kb |
| Host | smart-ebf84dd5-225b-4f17-b29b-915d76ca1102 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3940962024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3940962024 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.447928867 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 931397868 ps |
| CPU time | 18.31 seconds |
| Started | Feb 21 02:35:53 PM PST 24 |
| Finished | Feb 21 02:36:11 PM PST 24 |
| Peak memory | 204176 kb |
| Host | smart-25c5704f-0d83-4a91-8126-cfb8684e1cb6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=447928867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.447928867 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.4046133414 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 42716921372 ps |
| CPU time | 326.96 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:41:29 PM PST 24 |
| Peak memory | 211276 kb |
| Host | smart-4eff7581-aebc-440f-8c76-c6174886e96f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4046133414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.4046133414 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2856048500 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 395054458 ps |
| CPU time | 12.58 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:36:14 PM PST 24 |
| Peak memory | 203288 kb |
| Host | smart-c0b43b5f-ce72-4a0a-aed3-30689c3616c3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2856048500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2856048500 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.1633402083 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 626797097 ps |
| CPU time | 25.94 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:29 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-36984d40-4317-4945-a403-32b8b5d264b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1633402083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1633402083 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.2654995201 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1363969054 ps |
| CPU time | 26.4 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:36:28 PM PST 24 |
| Peak memory | 204100 kb |
| Host | smart-99ccc5b3-5424-4eba-a22f-880dd4e0e580 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2654995201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2654995201 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.3558377368 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4156151293 ps |
| CPU time | 16.09 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:22 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-92f79352-4744-4d91-9a2b-5a49a3569c37 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558377368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3558377368 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1594587260 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 29985297562 ps |
| CPU time | 172.74 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:38:58 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-a1991c08-e94f-4560-92df-9c01a594a63a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1594587260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1594587260 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2079895162 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 223139761 ps |
| CPU time | 9.53 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:15 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-d3c2a0bc-1ef6-4cb5-ba9b-ce819c19f08b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079895162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2079895162 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.3837364528 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 431055598 ps |
| CPU time | 12.78 seconds |
| Started | Feb 21 02:36:03 PM PST 24 |
| Finished | Feb 21 02:36:18 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-25722e1b-85b8-4675-81df-596a32c2f6c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3837364528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3837364528 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.3120115841 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 93467366 ps |
| CPU time | 2.34 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:02 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-774cbdf9-4d8e-401c-a14f-a73afeb16222 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3120115841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3120115841 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1091428418 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 6049675928 ps |
| CPU time | 35.45 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:39 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-dac4a943-a1dd-459d-9f8a-17144760eb3e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091428418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1091428418 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2447619147 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 6178941407 ps |
| CPU time | 26.7 seconds |
| Started | Feb 21 02:35:58 PM PST 24 |
| Finished | Feb 21 02:36:28 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-6895e36e-7bf7-413d-b701-0e99e5da5768 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2447619147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2447619147 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.196584295 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 96032980 ps |
| CPU time | 2.46 seconds |
| Started | Feb 21 02:36:01 PM PST 24 |
| Finished | Feb 21 02:36:06 PM PST 24 |
| Peak memory | 202988 kb |
| Host | smart-925b65f1-a693-4626-9d3f-b7cdd1931bba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196584295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.196584295 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.3867597415 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 305738548 ps |
| CPU time | 6.88 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:36:10 PM PST 24 |
| Peak memory | 204808 kb |
| Host | smart-8e279dff-77d0-4bbf-9269-f1b9f9207553 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3867597415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3867597415 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2119672749 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 7712986882 ps |
| CPU time | 147.71 seconds |
| Started | Feb 21 02:36:00 PM PST 24 |
| Finished | Feb 21 02:38:30 PM PST 24 |
| Peak memory | 207312 kb |
| Host | smart-87fe5fdd-0bc7-4ae5-a6f1-c0d14a6777d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2119672749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2119672749 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2012967377 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 184443993 ps |
| CPU time | 41.48 seconds |
| Started | Feb 21 02:36:04 PM PST 24 |
| Finished | Feb 21 02:36:48 PM PST 24 |
| Peak memory | 206600 kb |
| Host | smart-ee853674-c2e3-4f5d-a0bd-c9aa2f6da202 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2012967377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.2012967377 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.438685471 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2003457418 ps |
| CPU time | 226.35 seconds |
| Started | Feb 21 02:35:56 PM PST 24 |
| Finished | Feb 21 02:39:45 PM PST 24 |
| Peak memory | 211156 kb |
| Host | smart-43715176-ff56-4cad-8611-32f3b7fe62d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=438685471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese t_error.438685471 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1740473253 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 185375485 ps |
| CPU time | 2.05 seconds |
| Started | Feb 21 02:35:57 PM PST 24 |
| Finished | Feb 21 02:36:02 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-8fe81615-384f-4024-8e7e-5b8f2693be58 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1740473253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1740473253 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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