Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1749	1			T11	2		T22	3		T16	20
all_values[1]	1733	1			T11	1		T22	4		T16	15
all_values[2]	1711	1			T11	2		T22	6		T16	19
all_values[3]	1689	1			T11	1		T22	7		T16	19
all_values[4]	1754	1			T11	1		T22	5		T16	33
all_values[5]	1731	1			T11	3		T22	4		T16	17
all_values[6]	1643	1			T11	2		T22	4		T16	21
all_values[7]	1752	1			T11	1		T22	4		T16	14
all_values[8]	1768	1			T11	3		T22	7		T16	35
all_values[9]	1678	1			T11	6		T22	3		T16	30
all_values[10]	1640	1			T11	2		T22	1		T16	19
all_values[11]	1739	1			T11	2		T22	5		T16	22
all_values[12]	1630	1			T11	1		T22	2		T16	21
all_values[13]	1707	1			T11	2		T22	6		T16	26
all_values[14]	1771	1			T11	1		T22	6		T16	19
all_values[15]	1700	1			T11	5		T22	1		T16	18
all_values[16]	1710	1			T11	2		T22	3		T16	30
all_values[17]	1740	1			T11	1		T22	5		T16	24
all_values[18]	1679	1			T11	3		T22	4		T16	27
all_values[19]	1668	1			T11	1		T22	4		T16	22
all_values[20]	1702	1			T11	1		T22	1		T16	25
all_values[21]	1709	1			T11	1		T22	3		T16	25
all_values[22]	1702	1			T11	2		T22	2		T16	31
all_values[23]	1709	1			T11	1		T22	6		T16	21
all_values[24]	1717	1			T11	3		T22	1		T16	25
all_values[25]	1730	1			T11	2		T22	6		T16	25
all_values[26]	1669	1			T11	1		T22	4		T16	22
all_values[27]	1699	1			T11	1		T22	8		T16	21
all_values[28]	1693	1			T22	3		T16	18		T17	1
all_values[29]	1748	1			T11	1		T22	3		T16	25
all_values[30]	1725	1			T11	4		T22	5		T16	21
all_values[31]	1625	1			T11	2		T22	5		T16	18
all_values[32]	1744	1			T11	1		T22	7		T16	17
all_values[33]	1724	1			T11	1		T22	2		T16	18
all_values[34]	1688	1			T11	3		T22	5		T16	21
all_values[35]	1746	1			T11	3		T22	7		T16	18
all_values[36]	1775	1			T11	3		T22	4		T16	21
all_values[37]	1704	1			T11	1		T22	3		T16	22
all_values[38]	1798	1			T11	1		T22	10		T16	25
all_values[39]	1730	1			T11	1		T22	3		T16	18
all_values[40]	1731	1			T11	2		T22	3		T16	18
all_values[41]	1704	1			T11	4		T22	4		T16	20
all_values[42]	1707	1			T11	3		T22	4		T16	20
all_values[43]	1742	1			T11	1		T22	3		T16	28
all_values[44]	1747	1			T11	2		T22	3		T16	25
all_values[45]	1778	1			T22	1		T16	35		T17	3
all_values[46]	1637	1			T11	2		T22	2		T16	16
all_values[47]	1760	1			T22	6		T16	11		T19	2
all_values[48]	1759	1			T11	4		T22	6		T16	30
all_values[49]	1761	1			T11	1		T22	7		T16	20
all_values[50]	1703	1			T11	2		T22	4		T16	24
all_values[51]	1656	1			T11	1		T22	6		T16	20
all_values[52]	1700	1			T11	3		T22	3		T16	20
all_values[53]	1714	1			T11	1		T22	1		T16	23
all_values[54]	1672	1			T11	3		T22	6		T16	16
all_values[55]	1734	1			T22	4		T16	21		T19	3
all_values[56]	1800	1			T11	3		T22	6		T16	21
all_values[57]	1734	1			T11	2		T22	1		T16	21
all_values[58]	1738	1			T11	2		T22	6		T16	18
all_values[59]	1674	1			T11	7		T22	3		T16	26
all_values[60]	1691	1			T11	1		T22	6		T16	13
all_values[61]	1714	1			T11	1		T22	1		T16	24
all_values[62]	1720	1			T11	3		T22	3		T16	21
all_values[63]	1686	1			T11	1		T22	9		T16	22