Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.20	99.26	90.07	98.80		95.82	99.26	100.00

Total test records in report: 900

T763	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3512264238	Feb 25 02:29:36 PM PST 24	Feb 25 02:30:18 PM PST 24	31042397509 ps
T764	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1790616598	Feb 25 02:25:58 PM PST 24	Feb 25 02:26:36 PM PST 24	12305874643 ps
T765	/workspace/coverage/xbar_build_mode/39.xbar_smoke.1177937263	Feb 25 02:30:00 PM PST 24	Feb 25 02:30:03 PM PST 24	101077816 ps
T766	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3640330045	Feb 25 02:29:36 PM PST 24	Feb 25 02:30:04 PM PST 24	4168311411 ps
T767	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1126811859	Feb 25 02:26:48 PM PST 24	Feb 25 02:26:58 PM PST 24	108308294 ps
T768	/workspace/coverage/xbar_build_mode/20.xbar_random.3014439265	Feb 25 02:27:45 PM PST 24	Feb 25 02:28:31 PM PST 24	1194048305 ps
T769	/workspace/coverage/xbar_build_mode/10.xbar_smoke.452333517	Feb 25 02:26:42 PM PST 24	Feb 25 02:26:44 PM PST 24	42642319 ps
T770	/workspace/coverage/xbar_build_mode/2.xbar_error_random.2733727288	Feb 25 02:26:26 PM PST 24	Feb 25 02:26:48 PM PST 24	222072145 ps
T771	/workspace/coverage/xbar_build_mode/13.xbar_same_source.471215543	Feb 25 02:27:08 PM PST 24	Feb 25 02:27:25 PM PST 24	300024570 ps
T772	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.49509517	Feb 25 02:27:30 PM PST 24	Feb 25 02:36:06 PM PST 24	82410912411 ps
T773	/workspace/coverage/xbar_build_mode/26.xbar_error_random.3745826296	Feb 25 02:28:48 PM PST 24	Feb 25 02:28:53 PM PST 24	84930910 ps
T774	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2248666118	Feb 25 02:27:43 PM PST 24	Feb 25 02:28:40 PM PST 24	3765018845 ps
T775	/workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.400373537	Feb 25 02:29:43 PM PST 24	Feb 25 02:29:45 PM PST 24	58756954 ps
T776	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1090437029	Feb 25 02:27:35 PM PST 24	Feb 25 02:28:04 PM PST 24	4188077055 ps
T777	/workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2767248030	Feb 25 02:31:03 PM PST 24	Feb 25 02:34:09 PM PST 24	31635135598 ps
T778	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1956554983	Feb 25 02:27:43 PM PST 24	Feb 25 02:30:19 PM PST 24	9793184253 ps
T779	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2540143845	Feb 25 02:26:36 PM PST 24	Feb 25 02:27:34 PM PST 24	8338385291 ps
T780	/workspace/coverage/xbar_build_mode/34.xbar_smoke.2626958634	Feb 25 02:29:37 PM PST 24	Feb 25 02:29:42 PM PST 24	299298493 ps
T781	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.839168459	Feb 25 02:28:26 PM PST 24	Feb 25 02:28:35 PM PST 24	186393970 ps
T782	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3531612615	Feb 25 02:28:24 PM PST 24	Feb 25 02:32:13 PM PST 24	1176202724 ps
T783	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.795003418	Feb 25 02:27:12 PM PST 24	Feb 25 02:28:47 PM PST 24	12091915289 ps
T784	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.155111722	Feb 25 02:31:09 PM PST 24	Feb 25 02:42:51 PM PST 24	75727616645 ps
T785	/workspace/coverage/xbar_build_mode/23.xbar_error_random.3158037945	Feb 25 02:28:14 PM PST 24	Feb 25 02:28:38 PM PST 24	2132405607 ps
T786	/workspace/coverage/xbar_build_mode/7.xbar_error_random.931274347	Feb 25 02:26:38 PM PST 24	Feb 25 02:26:41 PM PST 24	44465236 ps
T787	/workspace/coverage/xbar_build_mode/49.xbar_error_random.2167193051	Feb 25 02:31:08 PM PST 24	Feb 25 02:31:32 PM PST 24	283873147 ps
T788	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.204778145	Feb 25 02:27:43 PM PST 24	Feb 25 02:29:32 PM PST 24	57422911880 ps
T789	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1392333224	Feb 25 02:26:40 PM PST 24	Feb 25 02:26:51 PM PST 24	500131972 ps
T790	/workspace/coverage/xbar_build_mode/12.xbar_smoke.128200609	Feb 25 02:26:55 PM PST 24	Feb 25 02:27:01 PM PST 24	516399582 ps
T791	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2529265909	Feb 25 02:27:15 PM PST 24	Feb 25 02:38:03 PM PST 24	155368496014 ps
T792	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4268628864	Feb 25 02:26:40 PM PST 24	Feb 25 02:28:58 PM PST 24	9679970577 ps
T793	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.4170284889	Feb 25 02:26:36 PM PST 24	Feb 25 02:29:30 PM PST 24	7021513824 ps
T794	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2922157536	Feb 25 02:26:39 PM PST 24	Feb 25 02:28:10 PM PST 24	17484465621 ps
T795	/workspace/coverage/xbar_build_mode/20.xbar_same_source.2212571622	Feb 25 02:27:43 PM PST 24	Feb 25 02:27:45 PM PST 24	39526710 ps
T796	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1667240142	Feb 25 02:27:59 PM PST 24	Feb 25 02:35:12 PM PST 24	72718755352 ps
T797	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.121420495	Feb 25 02:25:57 PM PST 24	Feb 25 02:25:59 PM PST 24	109035622 ps
T798	/workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1129675859	Feb 25 02:26:40 PM PST 24	Feb 25 02:26:46 PM PST 24	26050734 ps
T799	/workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3255689045	Feb 25 02:30:29 PM PST 24	Feb 25 02:30:52 PM PST 24	3077294903 ps
T800	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1814547320	Feb 25 02:30:30 PM PST 24	Feb 25 02:30:53 PM PST 24	289801977 ps
T197	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.177283788	Feb 25 02:28:36 PM PST 24	Feb 25 02:35:09 PM PST 24	1989054860 ps
T801	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2682828166	Feb 25 02:26:44 PM PST 24	Feb 25 02:26:47 PM PST 24	79737400 ps
T802	/workspace/coverage/xbar_build_mode/21.xbar_error_random.3596624521	Feb 25 02:28:05 PM PST 24	Feb 25 02:28:27 PM PST 24	330774058 ps
T65	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3002560495	Feb 25 02:29:44 PM PST 24	Feb 25 02:30:18 PM PST 24	24947207073 ps
T803	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1628144374	Feb 25 02:26:37 PM PST 24	Feb 25 02:33:12 PM PST 24	9042924779 ps
T804	/workspace/coverage/xbar_build_mode/47.xbar_same_source.3918469330	Feb 25 02:31:01 PM PST 24	Feb 25 02:31:15 PM PST 24	535119224 ps
T198	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.1840229347	Feb 25 02:27:42 PM PST 24	Feb 25 02:30:24 PM PST 24	2412692857 ps
T805	/workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2653748494	Feb 25 02:31:11 PM PST 24	Feb 25 02:31:14 PM PST 24	75258268 ps
T806	/workspace/coverage/xbar_build_mode/32.xbar_smoke.3644255125	Feb 25 02:29:15 PM PST 24	Feb 25 02:29:19 PM PST 24	27466605 ps
T807	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3388355454	Feb 25 02:26:26 PM PST 24	Feb 25 02:29:58 PM PST 24	10522662109 ps
T808	/workspace/coverage/xbar_build_mode/48.xbar_error_random.3320579739	Feb 25 02:31:04 PM PST 24	Feb 25 02:31:38 PM PST 24	852901910 ps
T809	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3103460824	Feb 25 02:27:41 PM PST 24	Feb 25 02:29:19 PM PST 24	25529799777 ps
T66	/workspace/coverage/xbar_build_mode/1.xbar_smoke.2785668765	Feb 25 02:25:57 PM PST 24	Feb 25 02:26:00 PM PST 24	290042969 ps
T810	/workspace/coverage/xbar_build_mode/17.xbar_same_source.2849447293	Feb 25 02:27:32 PM PST 24	Feb 25 02:28:02 PM PST 24	1639037459 ps
T811	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3680382648	Feb 25 02:26:40 PM PST 24	Feb 25 02:27:12 PM PST 24	14081028535 ps
T812	/workspace/coverage/xbar_build_mode/36.xbar_error_random.2662325068	Feb 25 02:29:41 PM PST 24	Feb 25 02:30:20 PM PST 24	892606744 ps
T813	/workspace/coverage/xbar_build_mode/37.xbar_smoke.3340011119	Feb 25 02:29:42 PM PST 24	Feb 25 02:29:44 PM PST 24	46008876 ps
T814	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1950165216	Feb 25 02:26:38 PM PST 24	Feb 25 02:26:49 PM PST 24	115091928 ps
T815	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2934579259	Feb 25 02:27:21 PM PST 24	Feb 25 02:28:23 PM PST 24	7181777585 ps
T67	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1866324199	Feb 25 02:26:40 PM PST 24	Feb 25 02:26:42 PM PST 24	72492505 ps
T816	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3444784643	Feb 25 02:29:40 PM PST 24	Feb 25 02:30:49 PM PST 24	2495003860 ps
T817	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1229989620	Feb 25 02:26:29 PM PST 24	Feb 25 02:27:00 PM PST 24	1802917973 ps
T818	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.148185635	Feb 25 02:29:44 PM PST 24	Feb 25 02:30:15 PM PST 24	4419622385 ps
T819	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1944489072	Feb 25 02:26:38 PM PST 24	Feb 25 02:27:33 PM PST 24	21334774011 ps
T820	/workspace/coverage/xbar_build_mode/5.xbar_random.3415263241	Feb 25 02:26:32 PM PST 24	Feb 25 02:26:41 PM PST 24	87861760 ps
T821	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.719335820	Feb 25 02:28:00 PM PST 24	Feb 25 02:28:21 PM PST 24	104612051 ps
T822	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2192849020	Feb 25 02:27:20 PM PST 24	Feb 25 02:27:56 PM PST 24	3797752306 ps
T823	/workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.647448570	Feb 25 02:28:25 PM PST 24	Feb 25 02:28:34 PM PST 24	330520159 ps
T824	/workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3304771762	Feb 25 02:25:59 PM PST 24	Feb 25 02:26:30 PM PST 24	5483019037 ps
T825	/workspace/coverage/xbar_build_mode/1.xbar_error_random.1658041009	Feb 25 02:26:05 PM PST 24	Feb 25 02:26:09 PM PST 24	60257232 ps
T826	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.261738621	Feb 25 02:29:48 PM PST 24	Feb 25 02:29:52 PM PST 24	17921536 ps
T827	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.568720164	Feb 25 02:31:01 PM PST 24	Feb 25 02:34:43 PM PST 24	37429082979 ps
T828	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1601798732	Feb 25 02:30:50 PM PST 24	Feb 25 02:34:14 PM PST 24	85520684495 ps
T34	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2962792697	Feb 25 02:30:16 PM PST 24	Feb 25 02:32:36 PM PST 24	408083698 ps
T829	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.946297890	Feb 25 02:31:14 PM PST 24	Feb 25 02:33:16 PM PST 24	6380324162 ps
T28	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2810711150	Feb 25 02:28:52 PM PST 24	Feb 25 02:30:14 PM PST 24	263448883 ps
T830	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.4223103014	Feb 25 02:30:29 PM PST 24	Feb 25 02:32:02 PM PST 24	529815075 ps
T831	/workspace/coverage/xbar_build_mode/25.xbar_random.3665720068	Feb 25 02:28:24 PM PST 24	Feb 25 02:28:29 PM PST 24	387816991 ps
T832	/workspace/coverage/xbar_build_mode/15.xbar_random.3172351538	Feb 25 02:27:15 PM PST 24	Feb 25 02:28:00 PM PST 24	7436273842 ps
T833	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.744972772	Feb 25 02:30:16 PM PST 24	Feb 25 02:30:18 PM PST 24	110559398 ps
T834	/workspace/coverage/xbar_build_mode/6.xbar_smoke.1032923223	Feb 25 02:26:30 PM PST 24	Feb 25 02:26:33 PM PST 24	33473966 ps
T835	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.372226300	Feb 25 02:27:08 PM PST 24	Feb 25 02:27:38 PM PST 24	6756457050 ps
T836	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.330126336	Feb 25 02:30:27 PM PST 24	Feb 25 02:31:12 PM PST 24	2487913416 ps
T837	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.9345986	Feb 25 02:31:17 PM PST 24	Feb 25 02:34:08 PM PST 24	1556815931 ps
T838	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3255357461	Feb 25 02:27:31 PM PST 24	Feb 25 02:27:34 PM PST 24	65858573 ps
T839	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2119190523	Feb 25 02:26:28 PM PST 24	Feb 25 02:27:01 PM PST 24	10360612614 ps
T840	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.3843720486	Feb 25 02:26:39 PM PST 24	Feb 25 02:28:49 PM PST 24	2489321717 ps
T841	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.3592879920	Feb 25 02:28:39 PM PST 24	Feb 25 02:29:26 PM PST 24	7518436143 ps
T842	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.3435362072	Feb 25 02:28:40 PM PST 24	Feb 25 02:29:36 PM PST 24	650448345 ps
T843	/workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2973040112	Feb 25 02:30:01 PM PST 24	Feb 25 02:30:20 PM PST 24	158609587 ps
T844	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2342706781	Feb 25 02:28:10 PM PST 24	Feb 25 02:28:38 PM PST 24	4219080464 ps
T845	/workspace/coverage/xbar_build_mode/37.xbar_same_source.503079906	Feb 25 02:29:45 PM PST 24	Feb 25 02:30:05 PM PST 24	592661264 ps
T846	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3242813006	Feb 25 02:26:27 PM PST 24	Feb 25 02:32:02 PM PST 24	74104540625 ps
T847	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2884353986	Feb 25 02:26:05 PM PST 24	Feb 25 02:26:27 PM PST 24	397839832 ps
T848	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.227434600	Feb 25 02:28:25 PM PST 24	Feb 25 02:29:02 PM PST 24	956243370 ps
T849	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1235680983	Feb 25 02:29:02 PM PST 24	Feb 25 02:29:20 PM PST 24	1150717080 ps
T850	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1221086656	Feb 25 02:29:03 PM PST 24	Feb 25 02:29:05 PM PST 24	114797150 ps
T851	/workspace/coverage/xbar_build_mode/45.xbar_same_source.2855060477	Feb 25 02:30:41 PM PST 24	Feb 25 02:30:46 PM PST 24	102934882 ps
T852	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.883576142	Feb 25 02:29:22 PM PST 24	Feb 25 02:29:33 PM PST 24	75275608 ps
T853	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3421409002	Feb 25 02:27:23 PM PST 24	Feb 25 02:28:35 PM PST 24	3885533706 ps
T854	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1220764962	Feb 25 02:28:04 PM PST 24	Feb 25 02:28:29 PM PST 24	4665880979 ps
T855	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.4239815583	Feb 25 02:26:48 PM PST 24	Feb 25 02:27:06 PM PST 24	13295070150 ps
T856	/workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3850579170	Feb 25 02:30:29 PM PST 24	Feb 25 02:30:59 PM PST 24	4973293729 ps
T857	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3163102986	Feb 25 02:30:09 PM PST 24	Feb 25 02:31:58 PM PST 24	2916159978 ps
T142	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2529311608	Feb 25 02:28:05 PM PST 24	Feb 25 02:37:01 PM PST 24	158843226396 ps
T200	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3221149208	Feb 25 02:28:25 PM PST 24	Feb 25 02:29:06 PM PST 24	525748117 ps
T858	/workspace/coverage/xbar_build_mode/12.xbar_error_random.296377013	Feb 25 02:26:51 PM PST 24	Feb 25 02:27:19 PM PST 24	1978703908 ps
T859	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.911165500	Feb 25 02:28:41 PM PST 24	Feb 25 02:28:59 PM PST 24	779009206 ps
T860	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1810741814	Feb 25 02:30:51 PM PST 24	Feb 25 02:32:34 PM PST 24	357670814 ps
T225	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1303705996	Feb 25 02:26:42 PM PST 24	Feb 25 02:32:14 PM PST 24	82603191280 ps
T861	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.367080912	Feb 25 02:29:42 PM PST 24	Feb 25 02:29:44 PM PST 24	44561078 ps
T862	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.774434091	Feb 25 02:27:58 PM PST 24	Feb 25 02:28:18 PM PST 24	4521238655 ps
T156	/workspace/coverage/xbar_build_mode/24.xbar_stress_all.2773964690	Feb 25 02:28:27 PM PST 24	Feb 25 02:29:49 PM PST 24	3196361482 ps
T863	/workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.2274563483	Feb 25 02:29:02 PM PST 24	Feb 25 02:29:37 PM PST 24	16990442775 ps
T864	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.884750467	Feb 25 02:26:09 PM PST 24	Feb 25 02:29:24 PM PST 24	4983196289 ps
T865	/workspace/coverage/xbar_build_mode/13.xbar_error_random.166518766	Feb 25 02:27:08 PM PST 24	Feb 25 02:27:11 PM PST 24	26498199 ps
T866	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.561227894	Feb 25 02:26:31 PM PST 24	Feb 25 02:29:39 PM PST 24	8546597410 ps
T867	/workspace/coverage/xbar_build_mode/2.xbar_stress_all.813718853	Feb 25 02:26:27 PM PST 24	Feb 25 02:26:54 PM PST 24	325113055 ps
T868	/workspace/coverage/xbar_build_mode/12.xbar_same_source.2582885824	Feb 25 02:26:50 PM PST 24	Feb 25 02:27:00 PM PST 24	281272578 ps
T869	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.1769763975	Feb 25 02:26:38 PM PST 24	Feb 25 02:27:02 PM PST 24	133043457 ps
T870	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3881428008	Feb 25 02:27:59 PM PST 24	Feb 25 02:28:32 PM PST 24	6127370117 ps
T871	/workspace/coverage/xbar_build_mode/3.xbar_random.1943816910	Feb 25 02:26:27 PM PST 24	Feb 25 02:27:03 PM PST 24	1745833180 ps
T872	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1772514232	Feb 25 02:30:27 PM PST 24	Feb 25 02:31:13 PM PST 24	1819408411 ps
T873	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3820252678	Feb 25 02:26:03 PM PST 24	Feb 25 02:26:48 PM PST 24	17977917494 ps
T874	/workspace/coverage/xbar_build_mode/29.xbar_error_random.1268048752	Feb 25 02:29:04 PM PST 24	Feb 25 02:29:16 PM PST 24	170381372 ps
T875	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3429325405	Feb 25 02:30:41 PM PST 24	Feb 25 02:30:56 PM PST 24	286119747 ps
T876	/workspace/coverage/xbar_build_mode/24.xbar_same_source.3727266985	Feb 25 02:28:12 PM PST 24	Feb 25 02:28:24 PM PST 24	664324294 ps
T877	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2829425796	Feb 25 02:29:01 PM PST 24	Feb 25 02:29:04 PM PST 24	34102188 ps
T878	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.4246099796	Feb 25 02:26:37 PM PST 24	Feb 25 02:28:17 PM PST 24	4754764691 ps
T879	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2030798348	Feb 25 02:29:36 PM PST 24	Feb 25 02:29:40 PM PST 24	26106184 ps
T880	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3196000197	Feb 25 02:26:42 PM PST 24	Feb 25 02:29:25 PM PST 24	17250506803 ps
T881	/workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.498210035	Feb 25 02:25:54 PM PST 24	Feb 25 02:29:40 PM PST 24	131233026008 ps
T882	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2761744304	Feb 25 02:29:58 PM PST 24	Feb 25 02:30:10 PM PST 24	1016937162 ps
T883	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3063836115	Feb 25 02:30:50 PM PST 24	Feb 25 02:31:03 PM PST 24	1619061187 ps
T884	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3338382535	Feb 25 02:29:17 PM PST 24	Feb 25 02:30:11 PM PST 24	368216424 ps
T885	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2809898757	Feb 25 02:29:50 PM PST 24	Feb 25 02:30:20 PM PST 24	3072801638 ps
T886	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.4098800275	Feb 25 02:29:33 PM PST 24	Feb 25 02:30:02 PM PST 24	3791226558 ps
T887	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3284161141	Feb 25 02:29:34 PM PST 24	Feb 25 02:37:19 PM PST 24	153814719535 ps
T888	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.182555507	Feb 25 02:26:42 PM PST 24	Feb 25 02:30:05 PM PST 24	5202012849 ps
T889	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1202037385	Feb 25 02:26:09 PM PST 24	Feb 25 02:26:23 PM PST 24	531153667 ps
T890	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1995252840	Feb 25 02:28:04 PM PST 24	Feb 25 02:28:49 PM PST 24	426715081 ps
T891	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.513147270	Feb 25 02:29:56 PM PST 24	Feb 25 02:31:53 PM PST 24	14674827755 ps
T892	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1868319300	Feb 25 02:26:41 PM PST 24	Feb 25 02:27:14 PM PST 24	2053270968 ps
T893	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3441683726	Feb 25 02:26:37 PM PST 24	Feb 25 02:27:04 PM PST 24	194491308 ps
T894	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3315055568	Feb 25 02:26:40 PM PST 24	Feb 25 02:30:35 PM PST 24	3731486278 ps
T895	/workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3385280479	Feb 25 02:30:27 PM PST 24	Feb 25 02:31:05 PM PST 24	9829156189 ps
T896	/workspace/coverage/xbar_build_mode/21.xbar_random.674693350	Feb 25 02:27:57 PM PST 24	Feb 25 02:28:33 PM PST 24	812960323 ps
T897	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1684301350	Feb 25 02:26:29 PM PST 24	Feb 25 02:28:21 PM PST 24	24006146726 ps
T898	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.4019656583	Feb 25 02:28:26 PM PST 24	Feb 25 02:28:28 PM PST 24	56827883 ps
T899	/workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3512578249	Feb 25 02:26:31 PM PST 24	Feb 25 02:30:35 PM PST 24	72943339377 ps
T900	/workspace/coverage/xbar_build_mode/44.xbar_random.2051990961	Feb 25 02:30:36 PM PST 24	Feb 25 02:31:07 PM PST 24	2545435699 ps
T255	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2908561417	Feb 25 02:26:55 PM PST 24	Feb 25 02:27:18 PM PST 24	4368750199 ps

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.4226225864
Short name	T4
Test name
Test status
Simulation time	806863411 ps
CPU time	46.96 seconds
Started	Feb 25 02:29:00 PM PST 24
Finished	Feb 25 02:29:47 PM PST 24
Peak memory	205404 kb
Host	smart-79bc1121-d9ff-42cb-9fce-7323cba7ae57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4226225864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.4226225864
Directory	/workspace/28.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2876163931
Short name	T163
Test name
Test status
Simulation time	71183590526 ps
CPU time	569.38 seconds
Started	Feb 25 02:29:37 PM PST 24
Finished	Feb 25 02:39:07 PM PST 24
Peak memory	206780 kb
Host	smart-e5bdf0e2-f40e-47a1-b103-557af13ee3ed
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2876163931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.2876163931
Directory	/workspace/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3719304429
Short name	T12
Test name
Test status
Simulation time	119004585246 ps
CPU time	429.83 seconds
Started	Feb 25 02:26:46 PM PST 24
Finished	Feb 25 02:33:56 PM PST 24
Peak memory	211296 kb
Host	smart-e178011d-e441-4851-b9fe-650aba8c3cfb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3719304429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3719304429
Directory	/workspace/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.362994
Short name	T97
Test name
Test status
Simulation time	63268171460 ps
CPU time	572.73 seconds
Started	Feb 25 02:26:35 PM PST 24
Finished	Feb 25 02:36:08 PM PST 24
Peak memory	211276 kb
Host	smart-721a62e7-56c5-47e2-b1c2-7b31f69a03c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=362994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.362994
Directory	/workspace/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2053617697
Short name	T37
Test name
Test status
Simulation time	30693068065 ps
CPU time	231.83 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:30:34 PM PST 24
Peak memory	211308 kb
Host	smart-1d06304b-e5d0-4d8c-bfac-07842e2a05e1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2053617697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.2053617697
Directory	/workspace/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1696129299
Short name	T22
Test name
Test status
Simulation time	150101620 ps
CPU time	42.87 seconds
Started	Feb 25 02:27:18 PM PST 24
Finished	Feb 25 02:28:01 PM PST 24
Peak memory	211244 kb
Host	smart-2c2a8dfd-e5c0-4703-9c27-3c358739ae94
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1696129299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.1696129299
Directory	/workspace/13.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.290276255
Short name	T39
Test name
Test status
Simulation time	173130292614 ps
CPU time	327.29 seconds
Started	Feb 25 02:28:41 PM PST 24
Finished	Feb 25 02:34:09 PM PST 24
Peak memory	204380 kb
Host	smart-7d7ca92a-516b-4705-83c7-34c1d950cb6e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=290276255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.290276255
Directory	/workspace/26.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3159908090
Short name	T2
Test name
Test status
Simulation time	10688536225 ps
CPU time	28.56 seconds
Started	Feb 25 02:28:10 PM PST 24
Finished	Feb 25 02:28:39 PM PST 24
Peak memory	203108 kb
Host	smart-9a9020f0-d411-4f64-83ee-721a00fe2f78
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159908090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3159908090
Directory	/workspace/24.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1687553398
Short name	T77
Test name
Test status
Simulation time	22266057961 ps
CPU time	478.21 seconds
Started	Feb 25 02:31:16 PM PST 24
Finished	Feb 25 02:39:15 PM PST 24
Peak memory	219540 kb
Host	smart-0fce40f3-0ebb-43cc-8f7c-ba420b5c614f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1687553398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran d_reset.1687553398
Directory	/workspace/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2396120017
Short name	T25
Test name
Test status
Simulation time	11875560368 ps
CPU time	587.15 seconds
Started	Feb 25 02:29:37 PM PST 24
Finished	Feb 25 02:39:24 PM PST 24
Peak memory	219504 kb
Host	smart-b6f5a8a2-2520-4cbd-ba9e-b084d0a04981
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2396120017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.2396120017
Directory	/workspace/35.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all.1376789697
Short name	T125
Test name
Test status
Simulation time	6874115977 ps
CPU time	329.86 seconds
Started	Feb 25 02:26:49 PM PST 24
Finished	Feb 25 02:32:19 PM PST 24
Peak memory	212360 kb
Host	smart-31e13806-7fb4-4331-b9ab-aa1b8c28bd5e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1376789697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1376789697
Directory	/workspace/11.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1461941896
Short name	T16
Test name
Test status
Simulation time	513066566 ps
CPU time	191.36 seconds
Started	Feb 25 02:31:01 PM PST 24
Finished	Feb 25 02:34:13 PM PST 24
Peak memory	208368 kb
Host	smart-f191b0cc-cd20-4358-b3dc-19f8bb779219
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1461941896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran d_reset.1461941896
Directory	/workspace/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all.2113488535
Short name	T131
Test name
Test status
Simulation time	42678439912 ps
CPU time	363.33 seconds
Started	Feb 25 02:28:41 PM PST 24
Finished	Feb 25 02:34:44 PM PST 24
Peak memory	210212 kb
Host	smart-60074ac1-f41d-402e-8e8e-66f91913b57a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2113488535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2113488535
Directory	/workspace/27.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.831956301
Short name	T115
Test name
Test status
Simulation time	734547537 ps
CPU time	221.34 seconds
Started	Feb 25 02:28:40 PM PST 24
Finished	Feb 25 02:32:21 PM PST 24
Peak memory	211180 kb
Host	smart-3dba8d8d-7396-4c30-a459-c7963cde6366
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=831956301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_res et_error.831956301
Directory	/workspace/26.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.4005999259
Short name	T26
Test name
Test status
Simulation time	6258608785 ps
CPU time	517.79 seconds
Started	Feb 25 02:28:25 PM PST 24
Finished	Feb 25 02:37:03 PM PST 24
Peak memory	219504 kb
Host	smart-e3ee573a-88b2-41ce-8ffd-d89f3928b405
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4005999259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.4005999259
Directory	/workspace/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random.560995520
Short name	T40
Test name
Test status
Simulation time	618063336 ps
CPU time	17.6 seconds
Started	Feb 25 02:29:35 PM PST 24
Finished	Feb 25 02:29:53 PM PST 24
Peak memory	204140 kb
Host	smart-9196d7bf-ac2d-408c-9931-3fc32532c826
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=560995520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.560995520
Directory	/workspace/34.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.924702230
Short name	T33
Test name
Test status
Simulation time	5013079750 ps
CPU time	225.94 seconds
Started	Feb 25 02:27:19 PM PST 24
Finished	Feb 25 02:31:05 PM PST 24
Peak memory	210080 kb
Host	smart-c2ee1491-38b5-483c-ae46-33692497ca6d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=924702230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_res et_error.924702230
Directory	/workspace/14.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1293594436
Short name	T399
Test name
Test status
Simulation time	527871576 ps
CPU time	195.15 seconds
Started	Feb 25 02:27:08 PM PST 24
Finished	Feb 25 02:30:23 PM PST 24
Peak memory	207848 kb
Host	smart-477b606c-6435-40d8-9b06-537ed91714e2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1293594436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_ran d_reset.1293594436
Directory	/workspace/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2266095502
Short name	T35
Test name
Test status
Simulation time	627245051 ps
CPU time	162.5 seconds
Started	Feb 25 02:27:21 PM PST 24
Finished	Feb 25 02:30:03 PM PST 24
Peak memory	210100 kb
Host	smart-94c2d298-fb57-4b03-836f-bfc0236e3b6a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2266095502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.2266095502
Directory	/workspace/15.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2102768162
Short name	T129
Test name
Test status
Simulation time	408611323706 ps
CPU time	992.9 seconds
Started	Feb 25 02:26:55 PM PST 24
Finished	Feb 25 02:43:29 PM PST 24
Peak memory	207092 kb
Host	smart-8c3b021f-b501-4448-a13d-5f347cdf3f0a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2102768162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.2102768162
Directory	/workspace/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device.235644787
Short name	T139
Test name
Test status
Simulation time	4643222024 ps
CPU time	57.59 seconds
Started	Feb 25 02:27:11 PM PST 24
Finished	Feb 25 02:28:09 PM PST 24
Peak memory	205860 kb
Host	smart-cf2e8bc3-8fdb-4617-bc3e-8d50e2fe3cdf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=235644787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.235644787
Directory	/workspace/14.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all.404352623
Short name	T100
Test name
Test status
Simulation time	12959119587 ps
CPU time	164.76 seconds
Started	Feb 25 02:27:21 PM PST 24
Finished	Feb 25 02:30:06 PM PST 24
Peak memory	208896 kb
Host	smart-e14211dc-9f21-40f0-a173-467e7f131d1f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=404352623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.404352623
Directory	/workspace/15.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device.2732906405
Short name	T245
Test name
Test status
Simulation time	268824142 ps
CPU time	13.42 seconds
Started	Feb 25 02:25:58 PM PST 24
Finished	Feb 25 02:26:11 PM PST 24
Peak memory	203976 kb
Host	smart-e86ffc3d-4429-4aa1-953e-00607c772299
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2732906405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.2732906405
Directory	/workspace/0.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.884842593
Short name	T110
Test name
Test status
Simulation time	45809686547 ps
CPU time	384.42 seconds
Started	Feb 25 02:26:04 PM PST 24
Finished	Feb 25 02:32:29 PM PST 24
Peak memory	211304 kb
Host	smart-3085d52d-8b5d-4199-9ba9-6b134da4a322
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=884842593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow _rsp.884842593
Directory	/workspace/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3436295328
Short name	T365
Test name
Test status
Simulation time	12765617 ps
CPU time	1.78 seconds
Started	Feb 25 02:26:03 PM PST 24
Finished	Feb 25 02:26:05 PM PST 24
Peak memory	203048 kb
Host	smart-645287d1-d67c-4a0a-9916-da1fbfd99590
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3436295328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3436295328
Directory	/workspace/0.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_error_random.3626650293
Short name	T685
Test name
Test status
Simulation time	606994296 ps
CPU time	21.87 seconds
Started	Feb 25 02:26:01 PM PST 24
Finished	Feb 25 02:26:23 PM PST 24
Peak memory	203036 kb
Host	smart-902c5fe8-5667-4050-93fa-19d77806608e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3626650293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3626650293
Directory	/workspace/0.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random.308251498
Short name	T74
Test name
Test status
Simulation time	3348405575 ps
CPU time	20.26 seconds
Started	Feb 25 02:25:58 PM PST 24
Finished	Feb 25 02:26:18 PM PST 24
Peak memory	203916 kb
Host	smart-0ac0bb16-1c5b-4277-8708-ebc120992292
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=308251498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.308251498
Directory	/workspace/0.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.498210035
Short name	T881
Test name
Test status
Simulation time	131233026008 ps
CPU time	225.78 seconds
Started	Feb 25 02:25:54 PM PST 24
Finished	Feb 25 02:29:40 PM PST 24
Peak memory	211308 kb
Host	smart-d4e7db5c-99cb-4279-98a1-63fa096b5275
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=498210035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.498210035
Directory	/workspace/0.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.412350889
Short name	T234
Test name
Test status
Simulation time	5323951307 ps
CPU time	40.49 seconds
Started	Feb 25 02:25:59 PM PST 24
Finished	Feb 25 02:26:39 PM PST 24
Peak memory	211256 kb
Host	smart-9b39d6aa-116f-4241-88c8-0723143ae035
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=412350889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.412350889
Directory	/workspace/0.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3240878180
Short name	T205
Test name
Test status
Simulation time	136897477 ps
CPU time	22.17 seconds
Started	Feb 25 02:25:58 PM PST 24
Finished	Feb 25 02:26:20 PM PST 24
Peak memory	204096 kb
Host	smart-d51f3d57-e84c-4282-b9b1-c1277cc27ce7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240878180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3240878180
Directory	/workspace/0.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_same_source.2246149371
Short name	T418
Test name
Test status
Simulation time	918303231 ps
CPU time	24.91 seconds
Started	Feb 25 02:26:00 PM PST 24
Finished	Feb 25 02:26:25 PM PST 24
Peak memory	203460 kb
Host	smart-361740b4-cd47-4d0e-a6fc-e1f0d58a7907
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2246149371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2246149371
Directory	/workspace/0.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke.1936163871
Short name	T340
Test name
Test status
Simulation time	44690522 ps
CPU time	2.34 seconds
Started	Feb 25 02:26:02 PM PST 24
Finished	Feb 25 02:26:05 PM PST 24
Peak memory	203040 kb
Host	smart-dc640590-a0f2-4ddf-a568-16d0964af14e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1936163871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1936163871
Directory	/workspace/0.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3304771762
Short name	T824
Test name
Test status
Simulation time	5483019037 ps
CPU time	30.38 seconds
Started	Feb 25 02:25:59 PM PST 24
Finished	Feb 25 02:26:30 PM PST 24
Peak memory	203120 kb
Host	smart-879558ed-9f8d-4216-ae3f-807fe7a428c3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304771762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3304771762
Directory	/workspace/0.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1790616598
Short name	T764
Test name
Test status
Simulation time	12305874643 ps
CPU time	37.75 seconds
Started	Feb 25 02:25:58 PM PST 24
Finished	Feb 25 02:26:36 PM PST 24
Peak memory	203092 kb
Host	smart-0e8dc812-83c2-4387-8ca9-eaa879c71f2d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1790616598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1790616598
Directory	/workspace/0.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.121420495
Short name	T797
Test name
Test status
Simulation time	109035622 ps
CPU time	2.11 seconds
Started	Feb 25 02:25:57 PM PST 24
Finished	Feb 25 02:25:59 PM PST 24
Peak memory	203036 kb
Host	smart-56ffcd3c-1df4-4d0a-b2e9-7762bdf3dccb
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121420495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.121420495
Directory	/workspace/0.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all.2688771572
Short name	T387
Test name
Test status
Simulation time	4418235203 ps
CPU time	175.38 seconds
Started	Feb 25 02:26:03 PM PST 24
Finished	Feb 25 02:28:58 PM PST 24
Peak memory	209664 kb
Host	smart-befb53a0-12ef-4a89-a9e5-2b04c86df8f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2688771572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2688771572
Directory	/workspace/0.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2117652923
Short name	T752
Test name
Test status
Simulation time	6554119968 ps
CPU time	166.63 seconds
Started	Feb 25 02:26:02 PM PST 24
Finished	Feb 25 02:28:49 PM PST 24
Peak memory	205280 kb
Host	smart-8c6aa861-2dfc-4fe1-bbd0-589ad7aa0858
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2117652923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2117652923
Directory	/workspace/0.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3386059247
Short name	T610
Test name
Test status
Simulation time	15327467429 ps
CPU time	863.98 seconds
Started	Feb 25 02:26:01 PM PST 24
Finished	Feb 25 02:40:25 PM PST 24
Peak memory	209676 kb
Host	smart-b2306a39-2405-4ca5-8f45-863c87ac187e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3386059247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.3386059247
Directory	/workspace/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2314194930
Short name	T614
Test name
Test status
Simulation time	10085948549 ps
CPU time	285.17 seconds
Started	Feb 25 02:26:02 PM PST 24
Finished	Feb 25 02:30:47 PM PST 24
Peak memory	211000 kb
Host	smart-d5518efa-ab3b-406d-adc5-1e95c47c3ef7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2314194930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.2314194930
Directory	/workspace/0.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3779336573
Short name	T510
Test name
Test status
Simulation time	64486557 ps
CPU time	2.66 seconds
Started	Feb 25 02:26:01 PM PST 24
Finished	Feb 25 02:26:04 PM PST 24
Peak memory	203032 kb
Host	smart-9ee442aa-57fe-43f6-a879-a5b9881f0ff7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3779336573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3779336573
Directory	/workspace/0.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2569383276
Short name	T181
Test name
Test status
Simulation time	74286121 ps
CPU time	10.76 seconds
Started	Feb 25 02:26:09 PM PST 24
Finished	Feb 25 02:26:20 PM PST 24
Peak memory	204576 kb
Host	smart-6182057a-bf3c-4a18-a364-2bb4fad3e87f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2569383276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2569383276
Directory	/workspace/1.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.3955706876
Short name	T536
Test name
Test status
Simulation time	9429779481 ps
CPU time	67.82 seconds
Started	Feb 25 02:26:03 PM PST 24
Finished	Feb 25 02:27:11 PM PST 24
Peak memory	211296 kb
Host	smart-a9a30351-c70d-4956-901b-b17b520feda9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3955706876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.3955706876
Directory	/workspace/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1202037385
Short name	T889
Test name
Test status
Simulation time	531153667 ps
CPU time	14.59 seconds
Started	Feb 25 02:26:09 PM PST 24
Finished	Feb 25 02:26:23 PM PST 24
Peak memory	203056 kb
Host	smart-a9f960c6-d091-4f6c-afa1-3405c36f953e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1202037385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1202037385
Directory	/workspace/1.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_error_random.1658041009
Short name	T825
Test name
Test status
Simulation time	60257232 ps
CPU time	4.58 seconds
Started	Feb 25 02:26:05 PM PST 24
Finished	Feb 25 02:26:09 PM PST 24
Peak memory	203064 kb
Host	smart-b911ef8d-1587-4868-a5e2-c3bbd307f3bb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1658041009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1658041009
Directory	/workspace/1.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random.2990412263
Short name	T697
Test name
Test status
Simulation time	966445806 ps
CPU time	25.49 seconds
Started	Feb 25 02:26:09 PM PST 24
Finished	Feb 25 02:26:34 PM PST 24
Peak memory	204160 kb
Host	smart-f714051d-0fd9-4eb3-929b-d1b9d1747798
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2990412263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2990412263
Directory	/workspace/1.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.1695718860
Short name	T650
Test name
Test status
Simulation time	39153935417 ps
CPU time	231.02 seconds
Started	Feb 25 02:26:04 PM PST 24
Finished	Feb 25 02:29:55 PM PST 24
Peak memory	204396 kb
Host	smart-8d868aad-8158-427a-83db-cd7c9ffeac4e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695718860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1695718860
Directory	/workspace/1.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3926372171
Short name	T135
Test name
Test status
Simulation time	9718524437 ps
CPU time	72.47 seconds
Started	Feb 25 02:26:05 PM PST 24
Finished	Feb 25 02:27:18 PM PST 24
Peak memory	204532 kb
Host	smart-d86dfc16-dfaf-4b51-9ad0-661f14b815bc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3926372171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3926372171
Directory	/workspace/1.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.2884353986
Short name	T847
Test name
Test status
Simulation time	397839832 ps
CPU time	21.54 seconds
Started	Feb 25 02:26:05 PM PST 24
Finished	Feb 25 02:26:27 PM PST 24
Peak memory	204052 kb
Host	smart-08cc1e60-f308-46b3-94a9-75548a5b987a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884353986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2884353986
Directory	/workspace/1.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_same_source.3112636491
Short name	T389
Test name
Test status
Simulation time	153847011 ps
CPU time	14.72 seconds
Started	Feb 25 02:26:07 PM PST 24
Finished	Feb 25 02:26:21 PM PST 24
Peak memory	203356 kb
Host	smart-a81a640a-29a4-4652-accd-b2797c8a94d9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3112636491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3112636491
Directory	/workspace/1.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke.2785668765
Short name	T66
Test name
Test status
Simulation time	290042969 ps
CPU time	3.55 seconds
Started	Feb 25 02:25:57 PM PST 24
Finished	Feb 25 02:26:00 PM PST 24
Peak memory	203024 kb
Host	smart-958e415a-4b17-4350-8599-84fcf2ff9545
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2785668765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2785668765
Directory	/workspace/1.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3820252678
Short name	T873
Test name
Test status
Simulation time	17977917494 ps
CPU time	44.93 seconds
Started	Feb 25 02:26:03 PM PST 24
Finished	Feb 25 02:26:48 PM PST 24
Peak memory	203108 kb
Host	smart-97e34647-50a3-4fe1-acb0-701279f46b78
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820252678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3820252678
Directory	/workspace/1.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3219477821
Short name	T47
Test name
Test status
Simulation time	2957958110 ps
CPU time	27.65 seconds
Started	Feb 25 02:26:05 PM PST 24
Finished	Feb 25 02:26:33 PM PST 24
Peak memory	203036 kb
Host	smart-654b7d32-0e74-4674-bfec-02698c3bd671
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3219477821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3219477821
Directory	/workspace/1.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1357210421
Short name	T636
Test name
Test status
Simulation time	44827450 ps
CPU time	2.42 seconds
Started	Feb 25 02:25:57 PM PST 24
Finished	Feb 25 02:25:59 PM PST 24
Peak memory	202956 kb
Host	smart-0f259c66-621a-4fb2-ac6c-049eba804eb6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357210421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1357210421
Directory	/workspace/1.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all.680966564
Short name	T397
Test name
Test status
Simulation time	2542009058 ps
CPU time	60.26 seconds
Started	Feb 25 02:26:05 PM PST 24
Finished	Feb 25 02:27:06 PM PST 24
Peak memory	205720 kb
Host	smart-35ba338a-b41d-4a54-98b3-39a345b401d0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=680966564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.680966564
Directory	/workspace/1.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.884750467
Short name	T864
Test name
Test status
Simulation time	4983196289 ps
CPU time	194.94 seconds
Started	Feb 25 02:26:09 PM PST 24
Finished	Feb 25 02:29:24 PM PST 24
Peak memory	209144 kb
Host	smart-462b433e-4025-4de8-96da-c974fd63d6c6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=884750467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.884750467
Directory	/workspace/1.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.137289904
Short name	T461
Test name
Test status
Simulation time	123325005 ps
CPU time	46.93 seconds
Started	Feb 25 02:26:08 PM PST 24
Finished	Feb 25 02:26:55 PM PST 24
Peak memory	205884 kb
Host	smart-6244c794-2139-436f-948e-cf348ee2333a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=137289904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_ reset.137289904
Directory	/workspace/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2054652917
Short name	T591
Test name
Test status
Simulation time	234394251 ps
CPU time	46.55 seconds
Started	Feb 25 02:26:05 PM PST 24
Finished	Feb 25 02:26:51 PM PST 24
Peak memory	206868 kb
Host	smart-f8e360d8-1032-4f54-917b-afc4a3efa26e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2054652917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.2054652917
Directory	/workspace/1.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.1521970723
Short name	T507
Test name
Test status
Simulation time	485597592 ps
CPU time	23.93 seconds
Started	Feb 25 02:26:03 PM PST 24
Finished	Feb 25 02:26:27 PM PST 24
Peak memory	204480 kb
Host	smart-415aa52f-bb90-41f0-be36-d9ba2c4574b8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1521970723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1521970723
Directory	/workspace/1.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device.1631867640
Short name	T58
Test name
Test status
Simulation time	462547991 ps
CPU time	34.92 seconds
Started	Feb 25 02:26:41 PM PST 24
Finished	Feb 25 02:27:16 PM PST 24
Peak memory	211200 kb
Host	smart-1d2fa3f4-a711-4623-a49b-c65a120d3e83
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1631867640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1631867640
Directory	/workspace/10.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.2112009496
Short name	T439
Test name
Test status
Simulation time	116657961828 ps
CPU time	518.7 seconds
Started	Feb 25 02:26:45 PM PST 24
Finished	Feb 25 02:35:24 PM PST 24
Peak memory	206632 kb
Host	smart-4ce28d03-68fb-450f-b7d4-c73e48f90d38
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2112009496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.2112009496
Directory	/workspace/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2129838043
Short name	T757
Test name
Test status
Simulation time	174317581 ps
CPU time	13.95 seconds
Started	Feb 25 02:26:44 PM PST 24
Finished	Feb 25 02:26:58 PM PST 24
Peak memory	203072 kb
Host	smart-22354766-7db4-4187-a225-aaa8d348962e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2129838043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2129838043
Directory	/workspace/10.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_error_random.2337698975
Short name	T742
Test name
Test status
Simulation time	887484010 ps
CPU time	24.7 seconds
Started	Feb 25 02:26:44 PM PST 24
Finished	Feb 25 02:27:09 PM PST 24
Peak memory	203068 kb
Host	smart-666df0dd-981c-4602-bff6-9b682736e838
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2337698975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2337698975
Directory	/workspace/10.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random.2670156425
Short name	T367
Test name
Test status
Simulation time	184433866 ps
CPU time	14.4 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:26:57 PM PST 24
Peak memory	204088 kb
Host	smart-a575196b-547f-4e12-92c2-9e530288a751
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2670156425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2670156425
Directory	/workspace/10.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.1355120317
Short name	T224
Test name
Test status
Simulation time	41323723862 ps
CPU time	175.66 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:29:38 PM PST 24
Peak memory	204240 kb
Host	smart-09480656-dff7-4b18-92eb-aff4a6247199
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355120317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1355120317
Directory	/workspace/10.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2150478191
Short name	T164
Test name
Test status
Simulation time	21729353578 ps
CPU time	91.38 seconds
Started	Feb 25 02:26:43 PM PST 24
Finished	Feb 25 02:28:15 PM PST 24
Peak memory	211316 kb
Host	smart-b3d2133e-12a0-4529-972b-76540aa97b0a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2150478191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2150478191
Directory	/workspace/10.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.651088510
Short name	T259
Test name
Test status
Simulation time	409493608 ps
CPU time	24.9 seconds
Started	Feb 25 02:26:39 PM PST 24
Finished	Feb 25 02:27:04 PM PST 24
Peak memory	204516 kb
Host	smart-ce925b7f-586f-4f27-849e-e2b0d1c00640
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651088510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.651088510
Directory	/workspace/10.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_same_source.3979139914
Short name	T413
Test name
Test status
Simulation time	2217735518 ps
CPU time	19.86 seconds
Started	Feb 25 02:26:41 PM PST 24
Finished	Feb 25 02:27:01 PM PST 24
Peak memory	203116 kb
Host	smart-973a024c-718e-4765-84c0-eecc7f09e3a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3979139914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3979139914
Directory	/workspace/10.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke.452333517
Short name	T769
Test name
Test status
Simulation time	42642319 ps
CPU time	2.55 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:26:44 PM PST 24
Peak memory	203024 kb
Host	smart-2d0c96b1-f52a-4689-80e0-18418be5f515
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=452333517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.452333517
Directory	/workspace/10.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.267730893
Short name	T299
Test name
Test status
Simulation time	5445112179 ps
CPU time	31.34 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:27:13 PM PST 24
Peak memory	203108 kb
Host	smart-4233f778-4f4d-4db4-812d-7769b8532b91
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=267730893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.267730893
Directory	/workspace/10.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3795198894
Short name	T218
Test name
Test status
Simulation time	11816379901 ps
CPU time	43.96 seconds
Started	Feb 25 02:26:38 PM PST 24
Finished	Feb 25 02:27:22 PM PST 24
Peak memory	203108 kb
Host	smart-40c1e525-823c-45a7-bae0-ba02792ebb52
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3795198894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3795198894
Directory	/workspace/10.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2612729672
Short name	T514
Test name
Test status
Simulation time	34349845 ps
CPU time	2.22 seconds
Started	Feb 25 02:26:41 PM PST 24
Finished	Feb 25 02:26:44 PM PST 24
Peak memory	203060 kb
Host	smart-03bafd3a-d765-48f6-ae21-f8aea62dfd66
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612729672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2612729672
Directory	/workspace/10.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all.3015555308
Short name	T563
Test name
Test status
Simulation time	479067437 ps
CPU time	41.41 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:27:23 PM PST 24
Peak memory	205236 kb
Host	smart-34226ad3-fbbc-4b5a-93f3-883381814a3f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3015555308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3015555308
Directory	/workspace/10.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3058893174
Short name	T256
Test name
Test status
Simulation time	1548655771 ps
CPU time	124.3 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:28:47 PM PST 24
Peak memory	204472 kb
Host	smart-8b60e882-fe06-452f-bc58-ae580694d172
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3058893174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3058893174
Directory	/workspace/10.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3063773821
Short name	T412
Test name
Test status
Simulation time	207781346 ps
CPU time	66.17 seconds
Started	Feb 25 02:26:45 PM PST 24
Finished	Feb 25 02:27:51 PM PST 24
Peak memory	206344 kb
Host	smart-50b9fa2e-6aa4-410b-8a7f-2208579b17d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3063773821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.3063773821
Directory	/workspace/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1127203718
Short name	T693
Test name
Test status
Simulation time	123063478 ps
CPU time	28.76 seconds
Started	Feb 25 02:26:46 PM PST 24
Finished	Feb 25 02:27:15 PM PST 24
Peak memory	205400 kb
Host	smart-94bfcf8d-ac40-47b1-909f-d17dd3ee6715
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1127203718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re set_error.1127203718
Directory	/workspace/10.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.4167476855
Short name	T638
Test name
Test status
Simulation time	750822436 ps
CPU time	23.9 seconds
Started	Feb 25 02:26:44 PM PST 24
Finished	Feb 25 02:27:08 PM PST 24
Peak memory	211220 kb
Host	smart-801409a0-72ef-4835-b349-bbb0bc7f9fde
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4167476855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.4167476855
Directory	/workspace/10.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_access_same_device.215361790
Short name	T659
Test name
Test status
Simulation time	1580314675 ps
CPU time	33.73 seconds
Started	Feb 25 02:26:47 PM PST 24
Finished	Feb 25 02:27:21 PM PST 24
Peak memory	204852 kb
Host	smart-81deb3e9-1de7-47b4-9c39-39b41b7b6119
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=215361790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.215361790
Directory	/workspace/11.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2970234623
Short name	T628
Test name
Test status
Simulation time	1151961947 ps
CPU time	11.16 seconds
Started	Feb 25 02:26:45 PM PST 24
Finished	Feb 25 02:26:57 PM PST 24
Peak memory	203284 kb
Host	smart-7fcdfc5b-3867-405e-b9af-d4f8658e4ca6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2970234623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2970234623
Directory	/workspace/11.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_error_random.3084516734
Short name	T282
Test name
Test status
Simulation time	4114824511 ps
CPU time	30.55 seconds
Started	Feb 25 02:26:49 PM PST 24
Finished	Feb 25 02:27:20 PM PST 24
Peak memory	203216 kb
Host	smart-d7b6639e-ac5d-44be-8f3c-8bdf78ab4998
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3084516734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3084516734
Directory	/workspace/11.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random.3538382557
Short name	T543
Test name
Test status
Simulation time	112553001 ps
CPU time	13.78 seconds
Started	Feb 25 02:26:46 PM PST 24
Finished	Feb 25 02:27:00 PM PST 24
Peak memory	204156 kb
Host	smart-2b3d26ed-c9a9-4f34-9c19-8a22929ff139
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3538382557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3538382557
Directory	/workspace/11.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3463530440
Short name	T60
Test name
Test status
Simulation time	29845525773 ps
CPU time	120.79 seconds
Started	Feb 25 02:26:43 PM PST 24
Finished	Feb 25 02:28:44 PM PST 24
Peak memory	211320 kb
Host	smart-bc2e4de6-7e30-4a32-b9e5-6c45f441027e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463530440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3463530440
Directory	/workspace/11.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3196000197
Short name	T880
Test name
Test status
Simulation time	17250506803 ps
CPU time	163.41 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:29:25 PM PST 24
Peak memory	204664 kb
Host	smart-4e3f950b-0b86-42c4-92ab-4f9231f78c78
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3196000197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3196000197
Directory	/workspace/11.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.1126811859
Short name	T767
Test name
Test status
Simulation time	108308294 ps
CPU time	10.61 seconds
Started	Feb 25 02:26:48 PM PST 24
Finished	Feb 25 02:26:58 PM PST 24
Peak memory	204100 kb
Host	smart-230552f7-b673-41b9-b45e-bd722518da61
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126811859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1126811859
Directory	/workspace/11.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_same_source.439405691
Short name	T506
Test name
Test status
Simulation time	183910772 ps
CPU time	8.54 seconds
Started	Feb 25 02:26:43 PM PST 24
Finished	Feb 25 02:26:52 PM PST 24
Peak memory	203032 kb
Host	smart-ec0a6376-682e-4ab5-8d53-3331c1df3944
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=439405691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.439405691
Directory	/workspace/11.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke.1183908846
Short name	T305
Test name
Test status
Simulation time	298474652 ps
CPU time	3.73 seconds
Started	Feb 25 02:26:47 PM PST 24
Finished	Feb 25 02:26:51 PM PST 24
Peak memory	203060 kb
Host	smart-69886b4d-08ee-4e63-b45b-6fa62267819e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1183908846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1183908846
Directory	/workspace/11.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.4163707845
Short name	T568
Test name
Test status
Simulation time	6068243655 ps
CPU time	26.49 seconds
Started	Feb 25 02:26:43 PM PST 24
Finished	Feb 25 02:27:09 PM PST 24
Peak memory	203092 kb
Host	smart-ec1533a8-cb3b-4c7e-895b-842eeec39540
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163707845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4163707845
Directory	/workspace/11.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1110630382
Short name	T336
Test name
Test status
Simulation time	9144353319 ps
CPU time	27.06 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:27:08 PM PST 24
Peak memory	203104 kb
Host	smart-3f2d7f4a-213d-450d-b41d-3e5717f18578
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1110630382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1110630382
Directory	/workspace/11.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.4176086323
Short name	T499
Test name
Test status
Simulation time	89123259 ps
CPU time	2.13 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:26:44 PM PST 24
Peak memory	203044 kb
Host	smart-e2bc7b5a-517c-4d4c-83e1-e64259542cc4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176086323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.4176086323
Directory	/workspace/11.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.3815741691
Short name	T643
Test name
Test status
Simulation time	7086494252 ps
CPU time	233.04 seconds
Started	Feb 25 02:26:48 PM PST 24
Finished	Feb 25 02:30:41 PM PST 24
Peak memory	208220 kb
Host	smart-2172e8b6-acac-4480-91ff-85dc3a2a4ad2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3815741691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3815741691
Directory	/workspace/11.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.794710493
Short name	T657
Test name
Test status
Simulation time	5657162374 ps
CPU time	450.96 seconds
Started	Feb 25 02:26:49 PM PST 24
Finished	Feb 25 02:34:21 PM PST 24
Peak memory	208340 kb
Host	smart-9c3ac708-c963-4952-ad5c-97608af5557f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=794710493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand _reset.794710493
Directory	/workspace/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3093759519
Short name	T564
Test name
Test status
Simulation time	124608111 ps
CPU time	43.03 seconds
Started	Feb 25 02:26:51 PM PST 24
Finished	Feb 25 02:27:34 PM PST 24
Peak memory	206076 kb
Host	smart-ba9ad1f0-6816-4b24-a3c8-c21651809d86
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3093759519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.3093759519
Directory	/workspace/11.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1609689053
Short name	T241
Test name
Test status
Simulation time	669924912 ps
CPU time	8.47 seconds
Started	Feb 25 02:26:49 PM PST 24
Finished	Feb 25 02:26:58 PM PST 24
Peak memory	204316 kb
Host	smart-fac25105-42ee-4b8b-8387-818329c96191
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1609689053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1609689053
Directory	/workspace/11.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_access_same_device.3968554017
Short name	T190
Test name
Test status
Simulation time	605882935 ps
CPU time	52.24 seconds
Started	Feb 25 02:26:54 PM PST 24
Finished	Feb 25 02:27:48 PM PST 24
Peak memory	211236 kb
Host	smart-93bf82cf-8aca-4fc6-aa74-7596ee768c97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3968554017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3968554017
Directory	/workspace/12.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1814113410
Short name	T309
Test name
Test status
Simulation time	967925465 ps
CPU time	15.92 seconds
Started	Feb 25 02:26:45 PM PST 24
Finished	Feb 25 02:27:02 PM PST 24
Peak memory	203168 kb
Host	smart-b99c0b6c-6bf2-45ab-a073-0fb7fe6c34ab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1814113410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1814113410
Directory	/workspace/12.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_error_random.296377013
Short name	T858
Test name
Test status
Simulation time	1978703908 ps
CPU time	27.53 seconds
Started	Feb 25 02:26:51 PM PST 24
Finished	Feb 25 02:27:19 PM PST 24
Peak memory	203120 kb
Host	smart-aa12c31d-787d-422c-9f7c-f6c71e6a0088
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=296377013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.296377013
Directory	/workspace/12.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random.1384910533
Short name	T118
Test name
Test status
Simulation time	4781136146 ps
CPU time	32.04 seconds
Started	Feb 25 02:26:49 PM PST 24
Finished	Feb 25 02:27:21 PM PST 24
Peak memory	204392 kb
Host	smart-1ddcf7d8-8d45-4f84-89d3-c2b7c2ae9366
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1384910533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1384910533
Directory	/workspace/12.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.4239815583
Short name	T855
Test name
Test status
Simulation time	13295070150 ps
CPU time	17.71 seconds
Started	Feb 25 02:26:48 PM PST 24
Finished	Feb 25 02:27:06 PM PST 24
Peak memory	203124 kb
Host	smart-f2568e10-35f8-4605-9c34-cb2f94dbca2d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239815583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.4239815583
Directory	/workspace/12.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.898392999
Short name	T328
Test name
Test status
Simulation time	4201520588 ps
CPU time	33.66 seconds
Started	Feb 25 02:26:49 PM PST 24
Finished	Feb 25 02:27:23 PM PST 24
Peak memory	203136 kb
Host	smart-56bf64e0-346d-464c-ac83-b251f2e9c2ff
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=898392999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.898392999
Directory	/workspace/12.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.2021815016
Short name	T194
Test name
Test status
Simulation time	267209128 ps
CPU time	22.39 seconds
Started	Feb 25 02:26:49 PM PST 24
Finished	Feb 25 02:27:12 PM PST 24
Peak memory	204364 kb
Host	smart-eba89dad-295b-4625-bcbb-11a9f252d99c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021815016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2021815016
Directory	/workspace/12.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_same_source.2582885824
Short name	T868
Test name
Test status
Simulation time	281272578 ps
CPU time	9.93 seconds
Started	Feb 25 02:26:50 PM PST 24
Finished	Feb 25 02:27:00 PM PST 24
Peak memory	203496 kb
Host	smart-be507ce0-6241-469f-be44-8df118f601a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2582885824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2582885824
Directory	/workspace/12.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke.128200609
Short name	T790
Test name
Test status
Simulation time	516399582 ps
CPU time	4.92 seconds
Started	Feb 25 02:26:55 PM PST 24
Finished	Feb 25 02:27:01 PM PST 24
Peak memory	203040 kb
Host	smart-2384ebb6-99a9-4aba-a389-0f3d6adbaaee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=128200609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.128200609
Directory	/workspace/12.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.276030201
Short name	T357
Test name
Test status
Simulation time	37169143765 ps
CPU time	42.9 seconds
Started	Feb 25 02:26:46 PM PST 24
Finished	Feb 25 02:27:29 PM PST 24
Peak memory	203104 kb
Host	smart-9df8015c-c1e6-4826-a209-feefce7b047b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=276030201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.276030201
Directory	/workspace/12.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.2908561417
Short name	T255
Test name
Test status
Simulation time	4368750199 ps
CPU time	22 seconds
Started	Feb 25 02:26:55 PM PST 24
Finished	Feb 25 02:27:18 PM PST 24
Peak memory	203112 kb
Host	smart-473087c6-5ad0-41b9-84f1-f5c4a7c50370
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2908561417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2908561417
Directory	/workspace/12.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2094914907
Short name	T457
Test name
Test status
Simulation time	65445139 ps
CPU time	2.51 seconds
Started	Feb 25 02:26:48 PM PST 24
Finished	Feb 25 02:26:51 PM PST 24
Peak memory	203052 kb
Host	smart-d82d5340-fecb-4d54-a566-22ae6f3cc312
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094914907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2094914907
Directory	/workspace/12.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all.3184124246
Short name	T732
Test name
Test status
Simulation time	7551001085 ps
CPU time	119.72 seconds
Started	Feb 25 02:26:46 PM PST 24
Finished	Feb 25 02:28:46 PM PST 24
Peak memory	209040 kb
Host	smart-7081f301-b3cf-4447-a3c1-dee7a3ca6e23
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3184124246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3184124246
Directory	/workspace/12.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.234858165
Short name	T316
Test name
Test status
Simulation time	8328802598 ps
CPU time	179.52 seconds
Started	Feb 25 02:26:48 PM PST 24
Finished	Feb 25 02:29:48 PM PST 24
Peak memory	209292 kb
Host	smart-7f4dd5e5-0d4a-4141-aea0-612d8a2ea7ce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=234858165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.234858165
Directory	/workspace/12.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.3158530839
Short name	T242
Test name
Test status
Simulation time	13269810720 ps
CPU time	407.96 seconds
Started	Feb 25 02:26:50 PM PST 24
Finished	Feb 25 02:33:38 PM PST 24
Peak memory	211876 kb
Host	smart-bb859bf4-16c4-48ce-98fb-78f79eb63272
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3158530839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran d_reset.3158530839
Directory	/workspace/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.371274036
Short name	T674
Test name
Test status
Simulation time	7787009 ps
CPU time	0.8 seconds
Started	Feb 25 02:26:46 PM PST 24
Finished	Feb 25 02:26:47 PM PST 24
Peak memory	194832 kb
Host	smart-9e72882d-7873-488e-b38e-4f868bf0447f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=371274036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_res et_error.371274036
Directory	/workspace/12.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3832675971
Short name	T306
Test name
Test status
Simulation time	240803209 ps
CPU time	11.62 seconds
Started	Feb 25 02:26:50 PM PST 24
Finished	Feb 25 02:27:02 PM PST 24
Peak memory	204464 kb
Host	smart-7a2d2ea0-40cd-4d94-bfad-a48239376e12
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3832675971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3832675971
Directory	/workspace/12.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2742296293
Short name	T334
Test name
Test status
Simulation time	1433497691 ps
CPU time	37.71 seconds
Started	Feb 25 02:27:02 PM PST 24
Finished	Feb 25 02:27:40 PM PST 24
Peak memory	204660 kb
Host	smart-968f13e4-1093-498e-9e69-a15a36994791
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2742296293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2742296293
Directory	/workspace/13.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2331085004
Short name	T64
Test name
Test status
Simulation time	178516002888 ps
CPU time	509.99 seconds
Started	Feb 25 02:27:00 PM PST 24
Finished	Feb 25 02:35:31 PM PST 24
Peak memory	211248 kb
Host	smart-ff0e1875-a847-4371-8897-59025181dde9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2331085004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.2331085004
Directory	/workspace/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.525458903
Short name	T482
Test name
Test status
Simulation time	305076871 ps
CPU time	19.13 seconds
Started	Feb 25 02:27:19 PM PST 24
Finished	Feb 25 02:27:39 PM PST 24
Peak memory	203508 kb
Host	smart-885f7fe6-b7e0-4864-bb9d-57df7fd9e6a2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=525458903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.525458903
Directory	/workspace/13.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_error_random.166518766
Short name	T865
Test name
Test status
Simulation time	26498199 ps
CPU time	2.19 seconds
Started	Feb 25 02:27:08 PM PST 24
Finished	Feb 25 02:27:11 PM PST 24
Peak memory	203048 kb
Host	smart-b3f923ee-ee1e-496c-affa-4d872b0d9626
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=166518766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.166518766
Directory	/workspace/13.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random.3163848040
Short name	T579
Test name
Test status
Simulation time	92012701 ps
CPU time	10.32 seconds
Started	Feb 25 02:27:01 PM PST 24
Finished	Feb 25 02:27:11 PM PST 24
Peak memory	211208 kb
Host	smart-f24781f5-81d9-434b-a1cb-ad3ccf65f843
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3163848040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3163848040
Directory	/workspace/13.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.233595758
Short name	T191
Test name
Test status
Simulation time	90513468758 ps
CPU time	137.15 seconds
Started	Feb 25 02:27:03 PM PST 24
Finished	Feb 25 02:29:21 PM PST 24
Peak memory	204292 kb
Host	smart-3b7a9261-d686-475d-8d38-e2c89fe419e0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=233595758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.233595758
Directory	/workspace/13.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3114057490
Short name	T486
Test name
Test status
Simulation time	1907160276 ps
CPU time	14.45 seconds
Started	Feb 25 02:27:13 PM PST 24
Finished	Feb 25 02:27:28 PM PST 24
Peak memory	203060 kb
Host	smart-ed36403a-ad24-4c35-aad7-48ffacf23f73
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3114057490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3114057490
Directory	/workspace/13.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.4162260541
Short name	T285
Test name
Test status
Simulation time	249011396 ps
CPU time	12.3 seconds
Started	Feb 25 02:27:00 PM PST 24
Finished	Feb 25 02:27:12 PM PST 24
Peak memory	211212 kb
Host	smart-52c2a54f-9598-4b56-9687-bb275d70fa4e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162260541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.4162260541
Directory	/workspace/13.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_same_source.471215543
Short name	T771
Test name
Test status
Simulation time	300024570 ps
CPU time	16.97 seconds
Started	Feb 25 02:27:08 PM PST 24
Finished	Feb 25 02:27:25 PM PST 24
Peak memory	203048 kb
Host	smart-36b5849a-ec2f-42da-9c43-bf700c0c6e0e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=471215543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.471215543
Directory	/workspace/13.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke.2862450902
Short name	T230
Test name
Test status
Simulation time	37260444 ps
CPU time	2.51 seconds
Started	Feb 25 02:27:00 PM PST 24
Finished	Feb 25 02:27:02 PM PST 24
Peak memory	203084 kb
Host	smart-b6719723-357f-4301-b83b-7e8c0d2164fe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2862450902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2862450902
Directory	/workspace/13.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.3068340077
Short name	T253
Test name
Test status
Simulation time	23714243108 ps
CPU time	39.57 seconds
Started	Feb 25 02:26:59 PM PST 24
Finished	Feb 25 02:27:39 PM PST 24
Peak memory	203124 kb
Host	smart-50388f75-156e-49ff-a6af-817588f49674
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068340077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3068340077
Directory	/workspace/13.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.4073061788
Short name	T338
Test name
Test status
Simulation time	4766831057 ps
CPU time	25.99 seconds
Started	Feb 25 02:27:01 PM PST 24
Finished	Feb 25 02:27:28 PM PST 24
Peak memory	203108 kb
Host	smart-444c370d-5c2b-46e7-b1ef-f86d57fc192f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4073061788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4073061788
Directory	/workspace/13.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.1829319573
Short name	T70
Test name
Test status
Simulation time	133417364 ps
CPU time	2.48 seconds
Started	Feb 25 02:27:00 PM PST 24
Finished	Feb 25 02:27:03 PM PST 24
Peak memory	202960 kb
Host	smart-4467eaa4-887a-4d0f-94e9-bed390cfa5e9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829319573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.1829319573
Directory	/workspace/13.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all.3657784407
Short name	T120
Test name
Test status
Simulation time	1831477235 ps
CPU time	62.7 seconds
Started	Feb 25 02:27:16 PM PST 24
Finished	Feb 25 02:28:19 PM PST 24
Peak memory	211212 kb
Host	smart-8e028eb9-f6a1-4f3a-b32e-110e56de0e8b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3657784407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3657784407
Directory	/workspace/13.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2871457582
Short name	T364
Test name
Test status
Simulation time	4163968468 ps
CPU time	158.08 seconds
Started	Feb 25 02:27:12 PM PST 24
Finished	Feb 25 02:29:51 PM PST 24
Peak memory	211276 kb
Host	smart-21182e66-fa4e-46c0-9a5f-81cd532b75db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2871457582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2871457582
Directory	/workspace/13.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.4036526992
Short name	T286
Test name
Test status
Simulation time	52972121 ps
CPU time	8.57 seconds
Started	Feb 25 02:27:08 PM PST 24
Finished	Feb 25 02:27:17 PM PST 24
Peak memory	204356 kb
Host	smart-cde83085-3f02-41e6-9e2b-6b72b15f8713
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4036526992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.4036526992
Directory	/workspace/13.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3375660888
Short name	T59
Test name
Test status
Simulation time	146009378030 ps
CPU time	674.23 seconds
Started	Feb 25 02:27:13 PM PST 24
Finished	Feb 25 02:38:28 PM PST 24
Peak memory	206820 kb
Host	smart-a800e34a-88d1-4e91-96b0-42263fb09a44
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3375660888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.3375660888
Directory	/workspace/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2797675376
Short name	T716
Test name
Test status
Simulation time	600213177 ps
CPU time	18.44 seconds
Started	Feb 25 02:27:20 PM PST 24
Finished	Feb 25 02:27:39 PM PST 24
Peak memory	203072 kb
Host	smart-02f1dafb-1e25-43ac-86f3-ffb8fa9b8cf9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2797675376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2797675376
Directory	/workspace/14.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_error_random.362108312
Short name	T711
Test name
Test status
Simulation time	1114418775 ps
CPU time	21.17 seconds
Started	Feb 25 02:27:11 PM PST 24
Finished	Feb 25 02:27:32 PM PST 24
Peak memory	202984 kb
Host	smart-1ebc635f-8aa2-44e2-8517-fc7a7b4c5ef8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=362108312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.362108312
Directory	/workspace/14.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random.571745059
Short name	T573
Test name
Test status
Simulation time	819311025 ps
CPU time	20.76 seconds
Started	Feb 25 02:27:12 PM PST 24
Finished	Feb 25 02:27:33 PM PST 24
Peak memory	211232 kb
Host	smart-48d993bc-03db-4737-a931-83cb9a1d416a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=571745059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.571745059
Directory	/workspace/14.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.585662249
Short name	T392
Test name
Test status
Simulation time	67382599879 ps
CPU time	274.71 seconds
Started	Feb 25 02:27:13 PM PST 24
Finished	Feb 25 02:31:48 PM PST 24
Peak memory	204736 kb
Host	smart-c2032cc2-c15d-4ff8-817e-b674f5221173
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=585662249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.585662249
Directory	/workspace/14.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3097340426
Short name	T404
Test name
Test status
Simulation time	33712179550 ps
CPU time	228.57 seconds
Started	Feb 25 02:27:14 PM PST 24
Finished	Feb 25 02:31:03 PM PST 24
Peak memory	205376 kb
Host	smart-02afed55-0a35-4381-b092-c2ca4cdf8c6a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3097340426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3097340426
Directory	/workspace/14.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2771338678
Short name	T504
Test name
Test status
Simulation time	128287262 ps
CPU time	17.78 seconds
Started	Feb 25 02:27:13 PM PST 24
Finished	Feb 25 02:27:31 PM PST 24
Peak memory	204344 kb
Host	smart-6b3139a7-45de-40c6-9a91-f6542028539e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771338678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2771338678
Directory	/workspace/14.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_same_source.1182969505
Short name	T751
Test name
Test status
Simulation time	2014448100 ps
CPU time	22.87 seconds
Started	Feb 25 02:27:19 PM PST 24
Finished	Feb 25 02:27:42 PM PST 24
Peak memory	203052 kb
Host	smart-fcdcc82e-76f1-4110-aa10-e395d1e74a5e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1182969505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1182969505
Directory	/workspace/14.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke.4212927786
Short name	T63
Test name
Test status
Simulation time	31150116 ps
CPU time	2.35 seconds
Started	Feb 25 02:27:14 PM PST 24
Finished	Feb 25 02:27:16 PM PST 24
Peak memory	203064 kb
Host	smart-70fd79dc-256c-4c02-bac5-027d852c5d69
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4212927786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.4212927786
Directory	/workspace/14.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2725938993
Short name	T23
Test name
Test status
Simulation time	5876783517 ps
CPU time	27.86 seconds
Started	Feb 25 02:27:12 PM PST 24
Finished	Feb 25 02:27:40 PM PST 24
Peak memory	203108 kb
Host	smart-ff4455e4-9cde-4360-8f0e-5dc1907ed0c1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725938993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2725938993
Directory	/workspace/14.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.372226300
Short name	T835
Test name
Test status
Simulation time	6756457050 ps
CPU time	29.27 seconds
Started	Feb 25 02:27:08 PM PST 24
Finished	Feb 25 02:27:38 PM PST 24
Peak memory	203032 kb
Host	smart-305ff52b-dc58-43a6-8a33-398b6d0cbba1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=372226300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.372226300
Directory	/workspace/14.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.3773264053
Short name	T552
Test name
Test status
Simulation time	37099822 ps
CPU time	2.68 seconds
Started	Feb 25 02:27:09 PM PST 24
Finished	Feb 25 02:27:12 PM PST 24
Peak memory	203072 kb
Host	smart-c94b2404-d2af-44a9-918c-9eb91a77c492
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773264053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.3773264053
Directory	/workspace/14.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all.330512830
Short name	T78
Test name
Test status
Simulation time	7290134653 ps
CPU time	82.35 seconds
Started	Feb 25 02:27:13 PM PST 24
Finished	Feb 25 02:28:36 PM PST 24
Peak memory	211304 kb
Host	smart-14926624-3d59-48d8-9439-8b8422c5e1e8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=330512830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.330512830
Directory	/workspace/14.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.4145315816
Short name	T310
Test name
Test status
Simulation time	2050566918 ps
CPU time	174.01 seconds
Started	Feb 25 02:27:17 PM PST 24
Finished	Feb 25 02:30:11 PM PST 24
Peak memory	211236 kb
Host	smart-408e7599-b9f3-4a3e-9b99-2da74d92da06
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4145315816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.4145315816
Directory	/workspace/14.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1382609522
Short name	T80
Test name
Test status
Simulation time	557287683 ps
CPU time	96 seconds
Started	Feb 25 02:27:19 PM PST 24
Finished	Feb 25 02:28:55 PM PST 24
Peak memory	206152 kb
Host	smart-8ce41c51-a787-406f-8fe3-7bf3c5e1287b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1382609522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.1382609522
Directory	/workspace/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2111164459
Short name	T723
Test name
Test status
Simulation time	397394639 ps
CPU time	9.6 seconds
Started	Feb 25 02:27:13 PM PST 24
Finished	Feb 25 02:27:23 PM PST 24
Peak memory	204436 kb
Host	smart-d19bc154-c712-467b-afa5-ad527b858844
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2111164459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2111164459
Directory	/workspace/14.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device.2192849020
Short name	T822
Test name
Test status
Simulation time	3797752306 ps
CPU time	35.18 seconds
Started	Feb 25 02:27:20 PM PST 24
Finished	Feb 25 02:27:56 PM PST 24
Peak memory	204892 kb
Host	smart-cb68a29b-17e8-4843-b677-39a4dbbd52a0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2192849020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2192849020
Directory	/workspace/15.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2529265909
Short name	T791
Test name
Test status
Simulation time	155368496014 ps
CPU time	648.24 seconds
Started	Feb 25 02:27:15 PM PST 24
Finished	Feb 25 02:38:03 PM PST 24
Peak memory	211348 kb
Host	smart-3a07d04b-79e9-4ad8-9276-a7e5ed545d42
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2529265909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.2529265909
Directory	/workspace/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.480448421
Short name	T592
Test name
Test status
Simulation time	106808266 ps
CPU time	11.03 seconds
Started	Feb 25 02:27:22 PM PST 24
Finished	Feb 25 02:27:33 PM PST 24
Peak memory	203120 kb
Host	smart-9fbfa3f7-8878-4f91-994f-53dcb46137a3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=480448421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.480448421
Directory	/workspace/15.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_error_random.3291136263
Short name	T725
Test name
Test status
Simulation time	308671090 ps
CPU time	11.79 seconds
Started	Feb 25 02:27:22 PM PST 24
Finished	Feb 25 02:27:34 PM PST 24
Peak memory	203064 kb
Host	smart-eec8f351-14b3-4ba2-a8cd-9170f3fa8dcb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3291136263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3291136263
Directory	/workspace/15.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random.3172351538
Short name	T832
Test name
Test status
Simulation time	7436273842 ps
CPU time	44.95 seconds
Started	Feb 25 02:27:15 PM PST 24
Finished	Feb 25 02:28:00 PM PST 24
Peak memory	205040 kb
Host	smart-ad60ddf0-6bd2-4a1a-9b71-c45dcfb03e1d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3172351538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3172351538
Directory	/workspace/15.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.666962138
Short name	T467
Test name
Test status
Simulation time	32689073259 ps
CPU time	138.68 seconds
Started	Feb 25 02:27:15 PM PST 24
Finished	Feb 25 02:29:34 PM PST 24
Peak memory	204212 kb
Host	smart-072da8f0-c19a-45e2-94fb-9a24f96ca5f3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=666962138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.666962138
Directory	/workspace/15.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.795003418
Short name	T783
Test name
Test status
Simulation time	12091915289 ps
CPU time	94.07 seconds
Started	Feb 25 02:27:12 PM PST 24
Finished	Feb 25 02:28:47 PM PST 24
Peak memory	204244 kb
Host	smart-fbca9df7-49d5-4604-ac5f-729a008e03b9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=795003418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.795003418
Directory	/workspace/15.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.367953594
Short name	T540
Test name
Test status
Simulation time	509243102 ps
CPU time	23.5 seconds
Started	Feb 25 02:27:14 PM PST 24
Finished	Feb 25 02:27:38 PM PST 24
Peak memory	211204 kb
Host	smart-956ed76d-3e67-4626-b76f-ba1ef371d3e7
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367953594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.367953594
Directory	/workspace/15.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_same_source.3201212921
Short name	T708
Test name
Test status
Simulation time	2578163695 ps
CPU time	29.46 seconds
Started	Feb 25 02:27:18 PM PST 24
Finished	Feb 25 02:27:48 PM PST 24
Peak memory	203368 kb
Host	smart-83a2b33f-c8fa-4738-a955-3ee6b55cd734
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3201212921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3201212921
Directory	/workspace/15.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke.3328234991
Short name	T345
Test name
Test status
Simulation time	159615730 ps
CPU time	3.68 seconds
Started	Feb 25 02:27:14 PM PST 24
Finished	Feb 25 02:27:17 PM PST 24
Peak memory	203008 kb
Host	smart-fe65cac4-13d1-4c8f-8c9b-32ec43ab7888
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3328234991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3328234991
Directory	/workspace/15.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2794139348
Short name	T320
Test name
Test status
Simulation time	7247964608 ps
CPU time	30.8 seconds
Started	Feb 25 02:27:13 PM PST 24
Finished	Feb 25 02:27:45 PM PST 24
Peak memory	203112 kb
Host	smart-26efe1fb-a4f6-4646-a1a8-35f0ea92d421
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794139348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2794139348
Directory	/workspace/15.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3218107318
Short name	T386
Test name
Test status
Simulation time	2935615301 ps
CPU time	24.62 seconds
Started	Feb 25 02:27:17 PM PST 24
Finished	Feb 25 02:27:42 PM PST 24
Peak memory	203100 kb
Host	smart-99198a0b-844a-4bd5-816a-00bdc68171e8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3218107318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3218107318
Directory	/workspace/15.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.568535003
Short name	T666
Test name
Test status
Simulation time	29486797 ps
CPU time	2.4 seconds
Started	Feb 25 02:27:13 PM PST 24
Finished	Feb 25 02:27:16 PM PST 24
Peak memory	203052 kb
Host	smart-244067c5-4537-4e1e-bf42-f169b708c454
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568535003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.568535003
Directory	/workspace/15.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3421409002
Short name	T853
Test name
Test status
Simulation time	3885533706 ps
CPU time	71.38 seconds
Started	Feb 25 02:27:23 PM PST 24
Finished	Feb 25 02:28:35 PM PST 24
Peak memory	205432 kb
Host	smart-b7d6edb2-a49a-488d-950c-ab5e12585f21
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3421409002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3421409002
Directory	/workspace/15.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.4004406779
Short name	T155
Test name
Test status
Simulation time	8006985232 ps
CPU time	373.12 seconds
Started	Feb 25 02:27:22 PM PST 24
Finished	Feb 25 02:33:35 PM PST 24
Peak memory	209160 kb
Host	smart-17cb8324-13e2-4588-89bb-2daa595d736f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4004406779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.4004406779
Directory	/workspace/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.3947446174
Short name	T616
Test name
Test status
Simulation time	284372796 ps
CPU time	20.75 seconds
Started	Feb 25 02:27:20 PM PST 24
Finished	Feb 25 02:27:41 PM PST 24
Peak memory	204248 kb
Host	smart-da67278d-57a4-4df3-a01d-c88834495eb8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3947446174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3947446174
Directory	/workspace/15.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device.415350482
Short name	T528
Test name
Test status
Simulation time	1073602293 ps
CPU time	37.8 seconds
Started	Feb 25 02:27:21 PM PST 24
Finished	Feb 25 02:27:59 PM PST 24
Peak memory	205344 kb
Host	smart-0d363269-2043-49ee-b23d-c8531e66016a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=415350482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.415350482
Directory	/workspace/16.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2934579259
Short name	T815
Test name
Test status
Simulation time	7181777585 ps
CPU time	61.9 seconds
Started	Feb 25 02:27:21 PM PST 24
Finished	Feb 25 02:28:23 PM PST 24
Peak memory	204108 kb
Host	smart-ce1ae354-7f17-43a5-9d27-342d7cc47e7b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2934579259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.2934579259
Directory	/workspace/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1929535451
Short name	T748
Test name
Test status
Simulation time	817432422 ps
CPU time	15.38 seconds
Started	Feb 25 02:27:21 PM PST 24
Finished	Feb 25 02:27:36 PM PST 24
Peak memory	203076 kb
Host	smart-4e8f437a-7b61-42ea-820a-785400ee9604
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1929535451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1929535451
Directory	/workspace/16.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_error_random.1099821732
Short name	T692
Test name
Test status
Simulation time	345444559 ps
CPU time	9.13 seconds
Started	Feb 25 02:27:22 PM PST 24
Finished	Feb 25 02:27:32 PM PST 24
Peak memory	203056 kb
Host	smart-8ce9fe04-87ec-474a-8c07-19ecba28035b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1099821732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1099821732
Directory	/workspace/16.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random.2103524780
Short name	T337
Test name
Test status
Simulation time	108877274 ps
CPU time	4.89 seconds
Started	Feb 25 02:27:22 PM PST 24
Finished	Feb 25 02:27:27 PM PST 24
Peak memory	203876 kb
Host	smart-06a89b06-376a-4c80-a251-93f0cb7dbf7d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2103524780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2103524780
Directory	/workspace/16.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.368976139
Short name	T656
Test name
Test status
Simulation time	131160081761 ps
CPU time	224.38 seconds
Started	Feb 25 02:27:22 PM PST 24
Finished	Feb 25 02:31:07 PM PST 24
Peak memory	211284 kb
Host	smart-5d21960c-f9de-465c-afe6-eb344e57d9fb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=368976139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.368976139
Directory	/workspace/16.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1708221182
Short name	T744
Test name
Test status
Simulation time	8080243463 ps
CPU time	78.2 seconds
Started	Feb 25 02:27:22 PM PST 24
Finished	Feb 25 02:28:41 PM PST 24
Peak memory	211296 kb
Host	smart-17b9d3d6-8fc5-4344-83d0-3a61081c3d85
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1708221182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1708221182
Directory	/workspace/16.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.4050846868
Short name	T219
Test name
Test status
Simulation time	130557947 ps
CPU time	16.27 seconds
Started	Feb 25 02:27:20 PM PST 24
Finished	Feb 25 02:27:36 PM PST 24
Peak memory	204092 kb
Host	smart-e5ee0656-c639-42ce-aa1e-48c70dce6cda
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050846868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4050846868
Directory	/workspace/16.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_same_source.743675958
Short name	T145
Test name
Test status
Simulation time	2293845420 ps
CPU time	33.26 seconds
Started	Feb 25 02:27:23 PM PST 24
Finished	Feb 25 02:27:56 PM PST 24
Peak memory	203488 kb
Host	smart-b3701908-87ac-4abd-b34d-a0ffbd77b23a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=743675958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.743675958
Directory	/workspace/16.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke.1172647995
Short name	T368
Test name
Test status
Simulation time	308992472 ps
CPU time	3.95 seconds
Started	Feb 25 02:27:24 PM PST 24
Finished	Feb 25 02:27:28 PM PST 24
Peak memory	203064 kb
Host	smart-475905bc-50a3-486f-a994-3ca8d72b8b66
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1172647995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1172647995
Directory	/workspace/16.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3163066842
Short name	T746
Test name
Test status
Simulation time	18258951672 ps
CPU time	36.75 seconds
Started	Feb 25 02:27:21 PM PST 24
Finished	Feb 25 02:27:57 PM PST 24
Peak memory	203092 kb
Host	smart-198e6889-07b0-4c64-a619-e6c7fa3cad5a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163066842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3163066842
Directory	/workspace/16.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3444440449
Short name	T262
Test name
Test status
Simulation time	15268298116 ps
CPU time	28.78 seconds
Started	Feb 25 02:27:24 PM PST 24
Finished	Feb 25 02:27:52 PM PST 24
Peak memory	203084 kb
Host	smart-ccc44256-db31-473a-81d4-ccac7e83ac4e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3444440449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3444440449
Directory	/workspace/16.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2259866281
Short name	T737
Test name
Test status
Simulation time	63118165 ps
CPU time	2.91 seconds
Started	Feb 25 02:27:21 PM PST 24
Finished	Feb 25 02:27:24 PM PST 24
Peak memory	203068 kb
Host	smart-753ab8ed-c8b2-4e6e-9256-096d4dec4d88
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259866281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2259866281
Directory	/workspace/16.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all.57329788
Short name	T586
Test name
Test status
Simulation time	1791424806 ps
CPU time	37.69 seconds
Started	Feb 25 02:27:24 PM PST 24
Finished	Feb 25 02:28:01 PM PST 24
Peak memory	205304 kb
Host	smart-864538a0-62fb-409f-89c2-297127fa7c80
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=57329788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.57329788
Directory	/workspace/16.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.3460690091
Short name	T423
Test name
Test status
Simulation time	2475186774 ps
CPU time	62.1 seconds
Started	Feb 25 02:27:22 PM PST 24
Finished	Feb 25 02:28:24 PM PST 24
Peak memory	205340 kb
Host	smart-1b2871fd-5d44-4c65-953e-95daa54cdf16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3460690091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3460690091
Directory	/workspace/16.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.213413020
Short name	T595
Test name
Test status
Simulation time	5276913505 ps
CPU time	287.56 seconds
Started	Feb 25 02:27:25 PM PST 24
Finished	Feb 25 02:32:13 PM PST 24
Peak memory	209728 kb
Host	smart-eb79e156-fd53-4aa8-9445-a9cae6f682ff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=213413020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand _reset.213413020
Directory	/workspace/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.1445839424
Short name	T756
Test name
Test status
Simulation time	543661261 ps
CPU time	120.65 seconds
Started	Feb 25 02:27:25 PM PST 24
Finished	Feb 25 02:29:26 PM PST 24
Peak memory	209236 kb
Host	smart-0183ae3f-bd6d-4049-8914-85b1a928a957
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1445839424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.1445839424
Directory	/workspace/16.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.783002210
Short name	T498
Test name
Test status
Simulation time	872255731 ps
CPU time	18.76 seconds
Started	Feb 25 02:27:26 PM PST 24
Finished	Feb 25 02:27:45 PM PST 24
Peak memory	204480 kb
Host	smart-d1818b75-9eea-4797-95a7-03bf9517a3e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=783002210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.783002210
Directory	/workspace/16.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device.5338324
Short name	T436
Test name
Test status
Simulation time	17441035 ps
CPU time	3.38 seconds
Started	Feb 25 02:27:31 PM PST 24
Finished	Feb 25 02:27:34 PM PST 24
Peak memory	203084 kb
Host	smart-2eb9daf5-7a7d-4b10-8134-80ac4e41f349
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=5338324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.5338324
Directory	/workspace/17.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.49509517
Short name	T772
Test name
Test status
Simulation time	82410912411 ps
CPU time	515.01 seconds
Started	Feb 25 02:27:30 PM PST 24
Finished	Feb 25 02:36:06 PM PST 24
Peak memory	211316 kb
Host	smart-1a79bc97-83ef-420c-9519-d38bf4e61624
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=49509517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow _rsp.49509517
Directory	/workspace/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3075550376
Short name	T488
Test name
Test status
Simulation time	247564717 ps
CPU time	13.17 seconds
Started	Feb 25 02:27:33 PM PST 24
Finished	Feb 25 02:27:46 PM PST 24
Peak memory	203056 kb
Host	smart-758a12e6-9f4b-4941-82f4-5a38735c42f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3075550376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3075550376
Directory	/workspace/17.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_error_random.1589001906
Short name	T559
Test name
Test status
Simulation time	115994135 ps
CPU time	13.72 seconds
Started	Feb 25 02:27:33 PM PST 24
Finished	Feb 25 02:27:47 PM PST 24
Peak memory	203060 kb
Host	smart-05e8e4cf-ea36-4399-bbba-36fd600530fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1589001906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1589001906
Directory	/workspace/17.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random.246184204
Short name	T251
Test name
Test status
Simulation time	1669524901 ps
CPU time	29.97 seconds
Started	Feb 25 02:27:31 PM PST 24
Finished	Feb 25 02:28:01 PM PST 24
Peak memory	211236 kb
Host	smart-2d97872b-ad7c-447c-ae9b-11847ab6a809
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=246184204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.246184204
Directory	/workspace/17.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.1975390370
Short name	T113
Test name
Test status
Simulation time	24596906033 ps
CPU time	118.99 seconds
Started	Feb 25 02:27:30 PM PST 24
Finished	Feb 25 02:29:29 PM PST 24
Peak memory	211308 kb
Host	smart-215c7874-7b4f-48da-b337-342dbdf6dd4c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975390370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1975390370
Directory	/workspace/17.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.371642581
Short name	T524
Test name
Test status
Simulation time	34632276585 ps
CPU time	241.09 seconds
Started	Feb 25 02:27:35 PM PST 24
Finished	Feb 25 02:31:36 PM PST 24
Peak memory	211280 kb
Host	smart-b237ca3c-2cec-48ae-811f-cfbf37850c21
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=371642581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.371642581
Directory	/workspace/17.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.2043802376
Short name	T363
Test name
Test status
Simulation time	37509364 ps
CPU time	6.28 seconds
Started	Feb 25 02:27:34 PM PST 24
Finished	Feb 25 02:27:40 PM PST 24
Peak memory	204120 kb
Host	smart-d49a8951-9203-41fd-8360-7107d4ab2592
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043802376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2043802376
Directory	/workspace/17.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_same_source.2849447293
Short name	T810
Test name
Test status
Simulation time	1639037459 ps
CPU time	30.02 seconds
Started	Feb 25 02:27:32 PM PST 24
Finished	Feb 25 02:28:02 PM PST 24
Peak memory	203504 kb
Host	smart-17f551e7-4579-46d0-83fb-b5cb1da81fc2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2849447293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2849447293
Directory	/workspace/17.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke.228469656
Short name	T390
Test name
Test status
Simulation time	285700844 ps
CPU time	3.43 seconds
Started	Feb 25 02:27:22 PM PST 24
Finished	Feb 25 02:27:25 PM PST 24
Peak memory	202956 kb
Host	smart-315c7047-4b44-46d8-bc67-44843799f4ea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=228469656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.228469656
Directory	/workspace/17.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2783774763
Short name	T184
Test name
Test status
Simulation time	5541887028 ps
CPU time	27.54 seconds
Started	Feb 25 02:27:21 PM PST 24
Finished	Feb 25 02:27:49 PM PST 24
Peak memory	203112 kb
Host	smart-401e8f78-3c07-4c7d-a3e3-d5a2175eab27
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783774763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2783774763
Directory	/workspace/17.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.2708524001
Short name	T427
Test name
Test status
Simulation time	4179472815 ps
CPU time	28.62 seconds
Started	Feb 25 02:27:32 PM PST 24
Finished	Feb 25 02:28:01 PM PST 24
Peak memory	203084 kb
Host	smart-c7b34b08-4be5-4682-b6cd-5d0f6627487b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2708524001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2708524001
Directory	/workspace/17.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2888564910
Short name	T731
Test name
Test status
Simulation time	52427860 ps
CPU time	2.5 seconds
Started	Feb 25 02:27:26 PM PST 24
Finished	Feb 25 02:27:28 PM PST 24
Peak memory	203072 kb
Host	smart-cbd519fd-a272-45d3-acfd-c77d795dfba8
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888564910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2888564910
Directory	/workspace/17.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all.1155996894
Short name	T220
Test name
Test status
Simulation time	1950590933 ps
CPU time	45.49 seconds
Started	Feb 25 02:27:32 PM PST 24
Finished	Feb 25 02:28:17 PM PST 24
Peak memory	205308 kb
Host	smart-99434e36-574e-4dd4-81bb-2adc1f6b96f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1155996894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1155996894
Directory	/workspace/17.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.2621045584
Short name	T329
Test name
Test status
Simulation time	1047362354 ps
CPU time	69.13 seconds
Started	Feb 25 02:27:35 PM PST 24
Finished	Feb 25 02:28:44 PM PST 24
Peak memory	206952 kb
Host	smart-326f1461-94da-4659-8a5e-21ea05aad44c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2621045584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2621045584
Directory	/workspace/17.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3791810186
Short name	T572
Test name
Test status
Simulation time	1583493426 ps
CPU time	350.44 seconds
Started	Feb 25 02:27:32 PM PST 24
Finished	Feb 25 02:33:22 PM PST 24
Peak memory	207760 kb
Host	smart-f4d390c3-7312-48ce-b5fa-b07b51d2a8c1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3791810186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.3791810186
Directory	/workspace/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.546671652
Short name	T521
Test name
Test status
Simulation time	8379218504 ps
CPU time	217.94 seconds
Started	Feb 25 02:27:35 PM PST 24
Finished	Feb 25 02:31:13 PM PST 24
Peak memory	211352 kb
Host	smart-5fb5a898-12a7-48df-9a7f-cdb9a7ee014e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=546671652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res et_error.546671652
Directory	/workspace/17.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.421599574
Short name	T344
Test name
Test status
Simulation time	212923787 ps
CPU time	13.8 seconds
Started	Feb 25 02:27:31 PM PST 24
Finished	Feb 25 02:27:45 PM PST 24
Peak memory	211188 kb
Host	smart-0b1379d5-2674-411d-b5a4-e318fa77855a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=421599574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.421599574
Directory	/workspace/17.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device.2486812727
Short name	T123
Test name
Test status
Simulation time	4766065597 ps
CPU time	46.31 seconds
Started	Feb 25 02:27:34 PM PST 24
Finished	Feb 25 02:28:21 PM PST 24
Peak memory	204892 kb
Host	smart-0f5ca391-4889-41cd-8546-10d73dd357f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2486812727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2486812727
Directory	/workspace/18.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3368124171
Short name	T683
Test name
Test status
Simulation time	8893997442 ps
CPU time	62.43 seconds
Started	Feb 25 02:27:33 PM PST 24
Finished	Feb 25 02:28:35 PM PST 24
Peak memory	204156 kb
Host	smart-c7e136e4-e308-423d-92f6-71db95c4ee4b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3368124171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_sl ow_rsp.3368124171
Directory	/workspace/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3509796940
Short name	T729
Test name
Test status
Simulation time	873781115 ps
CPU time	21.67 seconds
Started	Feb 25 02:27:36 PM PST 24
Finished	Feb 25 02:27:58 PM PST 24
Peak memory	203112 kb
Host	smart-67369189-1132-431a-b5c1-99f5b44f81cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3509796940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3509796940
Directory	/workspace/18.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_error_random.3649253346
Short name	T146
Test name
Test status
Simulation time	2954498844 ps
CPU time	35.58 seconds
Started	Feb 25 02:27:32 PM PST 24
Finished	Feb 25 02:28:08 PM PST 24
Peak memory	203120 kb
Host	smart-4d902ea7-1815-41d8-bca3-cd461d33a6f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3649253346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3649253346
Directory	/workspace/18.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random.1702874823
Short name	T476
Test name
Test status
Simulation time	429692992 ps
CPU time	13.7 seconds
Started	Feb 25 02:27:31 PM PST 24
Finished	Feb 25 02:27:45 PM PST 24
Peak memory	211144 kb
Host	smart-e482277d-515e-4c30-ac0f-0028b2b48426
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1702874823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1702874823
Directory	/workspace/18.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.3917908967
Short name	T298
Test name
Test status
Simulation time	14852733952 ps
CPU time	61.93 seconds
Started	Feb 25 02:27:34 PM PST 24
Finished	Feb 25 02:28:36 PM PST 24
Peak memory	211168 kb
Host	smart-ab11f72b-4b29-4a61-8a26-806f5e72398c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917908967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3917908967
Directory	/workspace/18.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.4269169973
Short name	T161
Test name
Test status
Simulation time	11266824631 ps
CPU time	19.87 seconds
Started	Feb 25 02:27:32 PM PST 24
Finished	Feb 25 02:27:52 PM PST 24
Peak memory	203044 kb
Host	smart-8177f942-f554-4a5e-b718-2b2be18bf352
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4269169973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.4269169973
Directory	/workspace/18.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.447092304
Short name	T180
Test name
Test status
Simulation time	13225089 ps
CPU time	2.19 seconds
Started	Feb 25 02:27:30 PM PST 24
Finished	Feb 25 02:27:32 PM PST 24
Peak memory	203088 kb
Host	smart-2ab0da2b-89db-431d-a15d-208e03f8d8d5
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447092304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.447092304
Directory	/workspace/18.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_same_source.2302680153
Short name	T414
Test name
Test status
Simulation time	1343749766 ps
CPU time	19.95 seconds
Started	Feb 25 02:27:30 PM PST 24
Finished	Feb 25 02:27:50 PM PST 24
Peak memory	203060 kb
Host	smart-5bc51272-02af-4e87-862e-b9e338a15428
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2302680153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2302680153
Directory	/workspace/18.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke.353030194
Short name	T429
Test name
Test status
Simulation time	112488119 ps
CPU time	2.16 seconds
Started	Feb 25 02:27:30 PM PST 24
Finished	Feb 25 02:27:33 PM PST 24
Peak memory	203052 kb
Host	smart-bd3b3c06-130b-4d0b-8c57-bf8abfd0404e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=353030194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.353030194
Directory	/workspace/18.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1023751772
Short name	T331
Test name
Test status
Simulation time	5605258365 ps
CPU time	26.96 seconds
Started	Feb 25 02:27:34 PM PST 24
Finished	Feb 25 02:28:01 PM PST 24
Peak memory	202996 kb
Host	smart-abe7fc87-828b-407a-a184-cd99bfed570b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023751772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1023751772
Directory	/workspace/18.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1090437029
Short name	T776
Test name
Test status
Simulation time	4188077055 ps
CPU time	28.82 seconds
Started	Feb 25 02:27:35 PM PST 24
Finished	Feb 25 02:28:04 PM PST 24
Peak memory	203156 kb
Host	smart-8a465c46-954c-41f8-b1a3-36afd565a628
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1090437029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1090437029
Directory	/workspace/18.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.3255357461
Short name	T838
Test name
Test status
Simulation time	65858573 ps
CPU time	2.22 seconds
Started	Feb 25 02:27:31 PM PST 24
Finished	Feb 25 02:27:34 PM PST 24
Peak memory	202984 kb
Host	smart-71a476bf-2bee-4161-a48c-2c67538c6ccf
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255357461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3255357461
Directory	/workspace/18.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all.3752322690
Short name	T68
Test name
Test status
Simulation time	857658060 ps
CPU time	80.63 seconds
Started	Feb 25 02:27:49 PM PST 24
Finished	Feb 25 02:29:10 PM PST 24
Peak memory	206136 kb
Host	smart-ec677ab5-f4f8-4a8c-bc97-0184434f5ae5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3752322690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3752322690
Directory	/workspace/18.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.3571486529
Short name	T406
Test name
Test status
Simulation time	15663269547 ps
CPU time	325.57 seconds
Started	Feb 25 02:27:44 PM PST 24
Finished	Feb 25 02:33:10 PM PST 24
Peak memory	210044 kb
Host	smart-071d0c26-cfd9-423a-871a-b728cc341e0d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3571486529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3571486529
Directory	/workspace/18.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1956554983
Short name	T778
Test name
Test status
Simulation time	9793184253 ps
CPU time	156.27 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:30:19 PM PST 24
Peak memory	208520 kb
Host	smart-992f1dad-a1af-4c20-8de0-74f46e14636b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1956554983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran d_reset.1956554983
Directory	/workspace/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3984148649
Short name	T529
Test name
Test status
Simulation time	341279381 ps
CPU time	106.39 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:29:30 PM PST 24
Peak memory	209156 kb
Host	smart-777c6093-0d33-44c8-9a4e-436b3a25433b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3984148649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.3984148649
Directory	/workspace/18.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.3330052657
Short name	T372
Test name
Test status
Simulation time	322706285 ps
CPU time	8.78 seconds
Started	Feb 25 02:27:32 PM PST 24
Finished	Feb 25 02:27:40 PM PST 24
Peak memory	204504 kb
Host	smart-c54440c6-0736-4e94-8295-59eac32195c4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3330052657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3330052657
Directory	/workspace/18.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device.92036164
Short name	T79
Test name
Test status
Simulation time	103247837 ps
CPU time	4.13 seconds
Started	Feb 25 02:27:46 PM PST 24
Finished	Feb 25 02:27:50 PM PST 24
Peak memory	203128 kb
Host	smart-5d2aa617-a065-4a06-9128-ad76958ddba9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=92036164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.92036164
Directory	/workspace/19.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1174395006
Short name	T391
Test name
Test status
Simulation time	128424337678 ps
CPU time	743.79 seconds
Started	Feb 25 02:27:44 PM PST 24
Finished	Feb 25 02:40:08 PM PST 24
Peak memory	211312 kb
Host	smart-e36e5ded-1c29-44e5-94cb-fd9163bae836
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1174395006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.1174395006
Directory	/workspace/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.576769412
Short name	T359
Test name
Test status
Simulation time	699668175 ps
CPU time	24.93 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:28:08 PM PST 24
Peak memory	203056 kb
Host	smart-ff4cbd56-46b3-492e-bb1e-b6e6f606b731
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=576769412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.576769412
Directory	/workspace/19.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_error_random.1363712701
Short name	T407
Test name
Test status
Simulation time	1492819939 ps
CPU time	26.49 seconds
Started	Feb 25 02:27:41 PM PST 24
Finished	Feb 25 02:28:08 PM PST 24
Peak memory	203004 kb
Host	smart-bd63b385-5980-4027-a749-470107a37990
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1363712701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1363712701
Directory	/workspace/19.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random.2311854884
Short name	T684
Test name
Test status
Simulation time	530361867 ps
CPU time	13.79 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:27:57 PM PST 24
Peak memory	204156 kb
Host	smart-7eff3009-209c-408e-9b7b-d9023478fe70
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2311854884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.2311854884
Directory	/workspace/19.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.204778145
Short name	T788
Test name
Test status
Simulation time	57422911880 ps
CPU time	108.22 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:29:32 PM PST 24
Peak memory	204216 kb
Host	smart-7512af5f-3002-4c8a-a121-e68adafb4639
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=204778145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.204778145
Directory	/workspace/19.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1555239969
Short name	T669
Test name
Test status
Simulation time	9421191502 ps
CPU time	81.19 seconds
Started	Feb 25 02:27:42 PM PST 24
Finished	Feb 25 02:29:04 PM PST 24
Peak memory	211288 kb
Host	smart-437da07d-8050-4e3c-8fcc-e4013061f440
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1555239969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1555239969
Directory	/workspace/19.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.400499727
Short name	T293
Test name
Test status
Simulation time	414893770 ps
CPU time	25.36 seconds
Started	Feb 25 02:27:46 PM PST 24
Finished	Feb 25 02:28:12 PM PST 24
Peak memory	211252 kb
Host	smart-4dd21660-65ae-44e9-be71-6a39cc604d59
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400499727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.400499727
Directory	/workspace/19.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_same_source.374882554
Short name	T346
Test name
Test status
Simulation time	310507785 ps
CPU time	17.25 seconds
Started	Feb 25 02:27:48 PM PST 24
Finished	Feb 25 02:28:06 PM PST 24
Peak memory	203052 kb
Host	smart-022e2e2c-e108-4e2f-a2bb-f5fe98958fe9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=374882554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.374882554
Directory	/workspace/19.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke.3314206044
Short name	T222
Test name
Test status
Simulation time	144913739 ps
CPU time	3.91 seconds
Started	Feb 25 02:27:50 PM PST 24
Finished	Feb 25 02:27:54 PM PST 24
Peak memory	202732 kb
Host	smart-622a10dc-a6ca-43c5-943e-d8b8ae6294ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3314206044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3314206044
Directory	/workspace/19.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.43248642
Short name	T408
Test name
Test status
Simulation time	25822304006 ps
CPU time	34.35 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:28:18 PM PST 24
Peak memory	203048 kb
Host	smart-e008737d-e4c9-49a3-bbe1-d89c122708cc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=43248642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.43248642
Directory	/workspace/19.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.629314163
Short name	T678
Test name
Test status
Simulation time	19034703601 ps
CPU time	40.89 seconds
Started	Feb 25 02:27:50 PM PST 24
Finished	Feb 25 02:28:31 PM PST 24
Peak memory	202756 kb
Host	smart-277558dc-fef7-4208-90a6-283e6c4c985e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=629314163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.629314163
Directory	/workspace/19.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1783263328
Short name	T438
Test name
Test status
Simulation time	108160613 ps
CPU time	2.56 seconds
Started	Feb 25 02:27:42 PM PST 24
Finished	Feb 25 02:27:45 PM PST 24
Peak memory	203056 kb
Host	smart-4dd920f2-0f6e-4cd5-89b5-f45983ac56c9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783263328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1783263328
Directory	/workspace/19.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all.1840229347
Short name	T198
Test name
Test status
Simulation time	2412692857 ps
CPU time	161.62 seconds
Started	Feb 25 02:27:42 PM PST 24
Finished	Feb 25 02:30:24 PM PST 24
Peak memory	205604 kb
Host	smart-e4c09371-049d-4ce2-a2c8-1c1fc403ac95
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1840229347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1840229347
Directory	/workspace/19.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.2712187536
Short name	T677
Test name
Test status
Simulation time	1869808874 ps
CPU time	80.96 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:29:04 PM PST 24
Peak memory	206196 kb
Host	smart-7adccf61-6246-4a4c-a8f3-a99994e5ca9a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2712187536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2712187536
Directory	/workspace/19.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2039701629
Short name	T617
Test name
Test status
Simulation time	7127091299 ps
CPU time	392.46 seconds
Started	Feb 25 02:27:44 PM PST 24
Finished	Feb 25 02:34:17 PM PST 24
Peak memory	211296 kb
Host	smart-0a7a92e4-881a-4873-8519-4f05ce46d0ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2039701629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.2039701629
Directory	/workspace/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.437704000
Short name	T332
Test name
Test status
Simulation time	6940790469 ps
CPU time	362.48 seconds
Started	Feb 25 02:27:42 PM PST 24
Finished	Feb 25 02:33:44 PM PST 24
Peak memory	211308 kb
Host	smart-0d3342d9-2475-489c-8002-13cd75adda09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=437704000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res et_error.437704000
Directory	/workspace/19.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2098229361
Short name	T585
Test name
Test status
Simulation time	132672165 ps
CPU time	4.89 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:27:48 PM PST 24
Peak memory	211188 kb
Host	smart-f00e4ea3-86bb-4487-9c37-262c8541b717
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2098229361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2098229361
Directory	/workspace/19.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device.1120441036
Short name	T523
Test name
Test status
Simulation time	34896543 ps
CPU time	7.67 seconds
Started	Feb 25 02:26:27 PM PST 24
Finished	Feb 25 02:26:35 PM PST 24
Peak memory	203076 kb
Host	smart-638dea95-e7ab-4db6-b40d-1867c1a5358b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1120441036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1120441036
Directory	/workspace/2.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2397160720
Short name	T81
Test name
Test status
Simulation time	125661328622 ps
CPU time	380.13 seconds
Started	Feb 25 02:26:25 PM PST 24
Finished	Feb 25 02:32:46 PM PST 24
Peak memory	206288 kb
Host	smart-e37796de-296a-4b55-84ab-1c12856f8088
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2397160720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.2397160720
Directory	/workspace/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3464284511
Short name	T330
Test name
Test status
Simulation time	457813627 ps
CPU time	17.51 seconds
Started	Feb 25 02:26:25 PM PST 24
Finished	Feb 25 02:26:43 PM PST 24
Peak memory	203052 kb
Host	smart-323d59c6-cdad-4290-b993-7b2bb0ee8518
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3464284511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3464284511
Directory	/workspace/2.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_error_random.2733727288
Short name	T770
Test name
Test status
Simulation time	222072145 ps
CPU time	21.42 seconds
Started	Feb 25 02:26:26 PM PST 24
Finished	Feb 25 02:26:48 PM PST 24
Peak memory	203072 kb
Host	smart-6f58e4e9-8f9a-49f0-a7aa-537c5ee950db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2733727288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2733727288
Directory	/workspace/2.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random.2747575611
Short name	T410
Test name
Test status
Simulation time	78623525 ps
CPU time	3.28 seconds
Started	Feb 25 02:26:26 PM PST 24
Finished	Feb 25 02:26:30 PM PST 24
Peak memory	203428 kb
Host	smart-6f5e6170-416d-4dfa-a0dd-d946aa5a7335
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2747575611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2747575611
Directory	/workspace/2.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1684301350
Short name	T897
Test name
Test status
Simulation time	24006146726 ps
CPU time	111.91 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:28:21 PM PST 24
Peak memory	204384 kb
Host	smart-a2986681-a5f6-4fa6-bb65-30f268e358a3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684301350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1684301350
Directory	/workspace/2.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.4073204585
Short name	T739
Test name
Test status
Simulation time	71980400637 ps
CPU time	167.15 seconds
Started	Feb 25 02:26:25 PM PST 24
Finished	Feb 25 02:29:12 PM PST 24
Peak memory	211304 kb
Host	smart-685b1d2f-eaa5-4ede-a9be-3135eb342a7e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4073204585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4073204585
Directory	/workspace/2.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.3041929196
Short name	T55
Test name
Test status
Simulation time	198471928 ps
CPU time	27.84 seconds
Started	Feb 25 02:26:24 PM PST 24
Finished	Feb 25 02:26:53 PM PST 24
Peak memory	204420 kb
Host	smart-d7e2e932-68ce-4883-b50b-31af8fd04dfa
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041929196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3041929196
Directory	/workspace/2.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_same_source.2200130627
Short name	T160
Test name
Test status
Simulation time	310327582 ps
CPU time	10.83 seconds
Started	Feb 25 02:26:25 PM PST 24
Finished	Feb 25 02:26:36 PM PST 24
Peak memory	203044 kb
Host	smart-6bcb778c-760f-4879-bd3e-1a9b6df9cd49
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2200130627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2200130627
Directory	/workspace/2.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke.3741492374
Short name	T240
Test name
Test status
Simulation time	158520666 ps
CPU time	3.87 seconds
Started	Feb 25 02:26:09 PM PST 24
Finished	Feb 25 02:26:14 PM PST 24
Peak memory	202860 kb
Host	smart-00f55130-4a04-4c7e-aa8c-45b78521344e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3741492374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3741492374
Directory	/workspace/2.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.1554140362
Short name	T73
Test name
Test status
Simulation time	4520061816 ps
CPU time	29.29 seconds
Started	Feb 25 02:26:23 PM PST 24
Finished	Feb 25 02:26:52 PM PST 24
Peak memory	203112 kb
Host	smart-f45578e4-0bfa-4e1d-88fe-7d1a24c4ed2e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554140362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1554140362
Directory	/workspace/2.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.525520537
Short name	T607
Test name
Test status
Simulation time	9802225741 ps
CPU time	33.36 seconds
Started	Feb 25 02:26:24 PM PST 24
Finished	Feb 25 02:26:58 PM PST 24
Peak memory	203040 kb
Host	smart-5a60cf5d-21fe-46eb-a4aa-b48a6abad890
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=525520537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.525520537
Directory	/workspace/2.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.263471774
Short name	T326
Test name
Test status
Simulation time	40560253 ps
CPU time	2.59 seconds
Started	Feb 25 02:26:24 PM PST 24
Finished	Feb 25 02:26:27 PM PST 24
Peak memory	203048 kb
Host	smart-998c4209-f693-46cc-9bf0-3ed0132f300e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263471774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.263471774
Directory	/workspace/2.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all.813718853
Short name	T867
Test name
Test status
Simulation time	325113055 ps
CPU time	26.51 seconds
Started	Feb 25 02:26:27 PM PST 24
Finished	Feb 25 02:26:54 PM PST 24
Peak memory	204712 kb
Host	smart-6703d895-80a8-40ac-af32-55d425ecbe52
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=813718853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.813718853
Directory	/workspace/2.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3388355454
Short name	T807
Test name
Test status
Simulation time	10522662109 ps
CPU time	211.78 seconds
Started	Feb 25 02:26:26 PM PST 24
Finished	Feb 25 02:29:58 PM PST 24
Peak memory	206608 kb
Host	smart-76e50634-5384-4169-8352-9892f4c695f4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3388355454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3388355454
Directory	/workspace/2.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3419992998
Short name	T517
Test name
Test status
Simulation time	3211906514 ps
CPU time	254.71 seconds
Started	Feb 25 02:26:30 PM PST 24
Finished	Feb 25 02:30:45 PM PST 24
Peak memory	211292 kb
Host	smart-be6b1c72-e430-46a5-8984-78f0a10cbc39
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3419992998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.3419992998
Directory	/workspace/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1669201479
Short name	T29
Test name
Test status
Simulation time	1309737598 ps
CPU time	359.54 seconds
Started	Feb 25 02:26:25 PM PST 24
Finished	Feb 25 02:32:25 PM PST 24
Peak memory	223216 kb
Host	smart-a514f5ed-63d9-4710-bd7c-de695d2f85af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1669201479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_res et_error.1669201479
Directory	/workspace/2.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.2782315976
Short name	T383
Test name
Test status
Simulation time	24310875 ps
CPU time	2.86 seconds
Started	Feb 25 02:26:27 PM PST 24
Finished	Feb 25 02:26:30 PM PST 24
Peak memory	203128 kb
Host	smart-4eff2084-c310-43b2-8d5b-637551af5830
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2782315976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2782315976
Directory	/workspace/2.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device.2248666118
Short name	T774
Test name
Test status
Simulation time	3765018845 ps
CPU time	55.99 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:28:40 PM PST 24
Peak memory	203812 kb
Host	smart-b791d6cc-a490-4828-9b9e-8edbee25a636
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2248666118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2248666118
Directory	/workspace/20.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2689617653
Short name	T103
Test name
Test status
Simulation time	126408129083 ps
CPU time	584.47 seconds
Started	Feb 25 02:27:45 PM PST 24
Finished	Feb 25 02:37:30 PM PST 24
Peak memory	211408 kb
Host	smart-74a91a64-30b9-4708-ab59-0e221557fd22
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2689617653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.2689617653
Directory	/workspace/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1220764962
Short name	T854
Test name
Test status
Simulation time	4665880979 ps
CPU time	24.39 seconds
Started	Feb 25 02:28:04 PM PST 24
Finished	Feb 25 02:28:29 PM PST 24
Peak memory	211284 kb
Host	smart-a0924b4d-a0f7-409c-a4bb-9a7f66a7d625
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1220764962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1220764962
Directory	/workspace/20.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_error_random.3906662925
Short name	T258
Test name
Test status
Simulation time	204183291 ps
CPU time	18.68 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:28:02 PM PST 24
Peak memory	203080 kb
Host	smart-2ae8be6a-8677-4467-8a82-752854b85cdc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3906662925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3906662925
Directory	/workspace/20.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random.3014439265
Short name	T768
Test name
Test status
Simulation time	1194048305 ps
CPU time	45.65 seconds
Started	Feb 25 02:27:45 PM PST 24
Finished	Feb 25 02:28:31 PM PST 24
Peak memory	211216 kb
Host	smart-e38448b1-15ad-49f4-9755-df229f762773
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3014439265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3014439265
Directory	/workspace/20.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1848372172
Short name	T437
Test name
Test status
Simulation time	17814537416 ps
CPU time	76.26 seconds
Started	Feb 25 02:27:45 PM PST 24
Finished	Feb 25 02:29:02 PM PST 24
Peak memory	204240 kb
Host	smart-f4832eff-4072-4109-b1bd-732cf9ab914c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848372172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1848372172
Directory	/workspace/20.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.3103460824
Short name	T809
Test name
Test status
Simulation time	25529799777 ps
CPU time	97.79 seconds
Started	Feb 25 02:27:41 PM PST 24
Finished	Feb 25 02:29:19 PM PST 24
Peak memory	211304 kb
Host	smart-f4c14b4a-0563-4abc-99b0-3def784faa0e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3103460824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3103460824
Directory	/workspace/20.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.1436507906
Short name	T594
Test name
Test status
Simulation time	50075379 ps
CPU time	2.63 seconds
Started	Feb 25 02:27:42 PM PST 24
Finished	Feb 25 02:27:45 PM PST 24
Peak memory	203368 kb
Host	smart-5d5a5dc5-8ac6-4f09-9977-c1f9a3cedcbe
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436507906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1436507906
Directory	/workspace/20.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_same_source.2212571622
Short name	T795
Test name
Test status
Simulation time	39526710 ps
CPU time	2.01 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:27:45 PM PST 24
Peak memory	203052 kb
Host	smart-58e455f1-b1bb-4d08-9682-79ea856161b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2212571622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2212571622
Directory	/workspace/20.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke.926516158
Short name	T348
Test name
Test status
Simulation time	185012270 ps
CPU time	4.41 seconds
Started	Feb 25 02:27:46 PM PST 24
Finished	Feb 25 02:27:51 PM PST 24
Peak memory	203028 kb
Host	smart-6c5f4ae8-c93f-49ef-9f2e-407218ff7fa5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=926516158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.926516158
Directory	/workspace/20.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.3502776132
Short name	T422
Test name
Test status
Simulation time	13395497921 ps
CPU time	34.34 seconds
Started	Feb 25 02:27:42 PM PST 24
Finished	Feb 25 02:28:17 PM PST 24
Peak memory	203120 kb
Host	smart-ca1486fb-92b5-4bb9-b361-6e3bdc322d17
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502776132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3502776132
Directory	/workspace/20.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1286424284
Short name	T9
Test name
Test status
Simulation time	7329269792 ps
CPU time	38.11 seconds
Started	Feb 25 02:27:43 PM PST 24
Finished	Feb 25 02:28:22 PM PST 24
Peak memory	203128 kb
Host	smart-a174a91c-a891-4968-a5f4-b0bd1ac21f68
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1286424284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1286424284
Directory	/workspace/20.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1535201558
Short name	T322
Test name
Test status
Simulation time	123826956 ps
CPU time	2.46 seconds
Started	Feb 25 02:27:46 PM PST 24
Finished	Feb 25 02:27:49 PM PST 24
Peak memory	203056 kb
Host	smart-50d532ce-8afa-4c31-b4fa-137acc94f6b9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535201558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1535201558
Directory	/workspace/20.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all.1416759489
Short name	T560
Test name
Test status
Simulation time	478346663 ps
CPU time	41.58 seconds
Started	Feb 25 02:28:00 PM PST 24
Finished	Feb 25 02:28:43 PM PST 24
Peak memory	211228 kb
Host	smart-003f878d-b045-4a1f-9e24-375b523b7202
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1416759489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1416759489
Directory	/workspace/20.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.3621637576
Short name	T284
Test name
Test status
Simulation time	5036193400 ps
CPU time	176.11 seconds
Started	Feb 25 02:27:54 PM PST 24
Finished	Feb 25 02:30:50 PM PST 24
Peak memory	205016 kb
Host	smart-02b47a55-2b31-4a35-80d3-6ac1cbfd8ad0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3621637576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3621637576
Directory	/workspace/20.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.729048343
Short name	T121
Test name
Test status
Simulation time	170684373 ps
CPU time	95.18 seconds
Started	Feb 25 02:28:05 PM PST 24
Finished	Feb 25 02:29:41 PM PST 24
Peak memory	206640 kb
Host	smart-8a3dd736-582b-4839-88e8-74f182721082
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=729048343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand _reset.729048343
Directory	/workspace/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.658599905
Short name	T269
Test name
Test status
Simulation time	444360580 ps
CPU time	116.65 seconds
Started	Feb 25 02:28:04 PM PST 24
Finished	Feb 25 02:30:01 PM PST 24
Peak memory	209044 kb
Host	smart-ddedf1fd-d1b5-4aaa-9c07-c3b82864f452
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=658599905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_res et_error.658599905
Directory	/workspace/20.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.214124690
Short name	T496
Test name
Test status
Simulation time	1014270859 ps
CPU time	12.49 seconds
Started	Feb 25 02:27:57 PM PST 24
Finished	Feb 25 02:28:10 PM PST 24
Peak memory	211284 kb
Host	smart-9bbdbfb1-a119-401b-a00c-1c7d84c611f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=214124690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.214124690
Directory	/workspace/20.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device.4249929999
Short name	T400
Test name
Test status
Simulation time	656808117 ps
CPU time	36.28 seconds
Started	Feb 25 02:28:04 PM PST 24
Finished	Feb 25 02:28:41 PM PST 24
Peak memory	211224 kb
Host	smart-9fc20bc9-cbb3-410d-9a6e-a6ff4ea0bdad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4249929999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.4249929999
Directory	/workspace/21.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1667240142
Short name	T796
Test name
Test status
Simulation time	72718755352 ps
CPU time	433.33 seconds
Started	Feb 25 02:27:59 PM PST 24
Finished	Feb 25 02:35:12 PM PST 24
Peak memory	211316 kb
Host	smart-37d11e27-1df8-42c4-a6d6-8a9f7a7001a1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1667240142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl ow_rsp.1667240142
Directory	/workspace/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1319605027
Short name	T493
Test name
Test status
Simulation time	37535124 ps
CPU time	5.31 seconds
Started	Feb 25 02:27:57 PM PST 24
Finished	Feb 25 02:28:02 PM PST 24
Peak memory	203112 kb
Host	smart-8c8503d7-140b-4522-b948-9e99e186c3c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1319605027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1319605027
Directory	/workspace/21.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_error_random.3596624521
Short name	T802
Test name
Test status
Simulation time	330774058 ps
CPU time	21.86 seconds
Started	Feb 25 02:28:05 PM PST 24
Finished	Feb 25 02:28:27 PM PST 24
Peak memory	203248 kb
Host	smart-f93d0661-1692-4da2-8626-d036fb6f609e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3596624521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3596624521
Directory	/workspace/21.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random.674693350
Short name	T896
Test name
Test status
Simulation time	812960323 ps
CPU time	35.49 seconds
Started	Feb 25 02:27:57 PM PST 24
Finished	Feb 25 02:28:33 PM PST 24
Peak memory	204076 kb
Host	smart-ac997519-21bc-4676-bf2d-5dc75ee98f91
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=674693350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.674693350
Directory	/workspace/21.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3247447012
Short name	T38
Test name
Test status
Simulation time	10652410379 ps
CPU time	66.8 seconds
Started	Feb 25 02:27:54 PM PST 24
Finished	Feb 25 02:29:01 PM PST 24
Peak memory	211324 kb
Host	smart-cbf4e196-23f3-40c4-b23f-a84f09d57bb6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247447012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3247447012
Directory	/workspace/21.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3226911886
Short name	T741
Test name
Test status
Simulation time	2807652628 ps
CPU time	26.39 seconds
Started	Feb 25 02:27:52 PM PST 24
Finished	Feb 25 02:28:19 PM PST 24
Peak memory	204160 kb
Host	smart-614100ac-52ed-4969-be74-09fb0e1f670a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3226911886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3226911886
Directory	/workspace/21.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.2526751605
Short name	T21
Test name
Test status
Simulation time	197801476 ps
CPU time	23.06 seconds
Started	Feb 25 02:27:56 PM PST 24
Finished	Feb 25 02:28:20 PM PST 24
Peak memory	211252 kb
Host	smart-475e76ca-cbe9-4dad-a162-3dfdaf0d5b1c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526751605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.2526751605
Directory	/workspace/21.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_same_source.925151392
Short name	T11
Test name
Test status
Simulation time	150039087 ps
CPU time	13.99 seconds
Started	Feb 25 02:28:04 PM PST 24
Finished	Feb 25 02:28:19 PM PST 24
Peak memory	202988 kb
Host	smart-747597d8-f117-4bd3-a16e-87752e2f2ccf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=925151392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.925151392
Directory	/workspace/21.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke.1359642810
Short name	T485
Test name
Test status
Simulation time	165727822 ps
CPU time	4.27 seconds
Started	Feb 25 02:27:53 PM PST 24
Finished	Feb 25 02:27:58 PM PST 24
Peak memory	203020 kb
Host	smart-2d153b76-bee1-4736-a05a-eb31f73fedd9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1359642810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1359642810
Directory	/workspace/21.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.1876498118
Short name	T435
Test name
Test status
Simulation time	27945129492 ps
CPU time	45.93 seconds
Started	Feb 25 02:28:01 PM PST 24
Finished	Feb 25 02:28:48 PM PST 24
Peak memory	203116 kb
Host	smart-d48a0512-5c90-4a87-b57d-ebf2beb355c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876498118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1876498118
Directory	/workspace/21.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2321384038
Short name	T462
Test name
Test status
Simulation time	8881048643 ps
CPU time	29.64 seconds
Started	Feb 25 02:28:04 PM PST 24
Finished	Feb 25 02:28:34 PM PST 24
Peak memory	203120 kb
Host	smart-729a98fa-5330-413c-85de-1c44d39fadbc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2321384038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2321384038
Directory	/workspace/21.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3951316686
Short name	T561
Test name
Test status
Simulation time	28298419 ps
CPU time	2.1 seconds
Started	Feb 25 02:27:59 PM PST 24
Finished	Feb 25 02:28:01 PM PST 24
Peak memory	203064 kb
Host	smart-28a0ae49-40e1-494b-901e-e9b005b215ec
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951316686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3951316686
Directory	/workspace/21.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all.3287886312
Short name	T525
Test name
Test status
Simulation time	13680354924 ps
CPU time	199.73 seconds
Started	Feb 25 02:28:06 PM PST 24
Finished	Feb 25 02:31:26 PM PST 24
Peak memory	211300 kb
Host	smart-b26717a5-77e7-4dd7-b19b-a8dbac7b2284
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3287886312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3287886312
Directory	/workspace/21.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3885533699
Short name	T665
Test name
Test status
Simulation time	11767414694 ps
CPU time	180.52 seconds
Started	Feb 25 02:27:57 PM PST 24
Finished	Feb 25 02:30:58 PM PST 24
Peak memory	209024 kb
Host	smart-bb1bf524-33ba-4bca-8fd0-272880354eb3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3885533699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3885533699
Directory	/workspace/21.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.719335820
Short name	T821
Test name
Test status
Simulation time	104612051 ps
CPU time	19.32 seconds
Started	Feb 25 02:28:00 PM PST 24
Finished	Feb 25 02:28:21 PM PST 24
Peak memory	205272 kb
Host	smart-38c444c8-3ed7-496d-90d6-e265d00f3c18
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=719335820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand _reset.719335820
Directory	/workspace/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.4217906340
Short name	T433
Test name
Test status
Simulation time	160381864 ps
CPU time	13.36 seconds
Started	Feb 25 02:27:55 PM PST 24
Finished	Feb 25 02:28:08 PM PST 24
Peak memory	204044 kb
Host	smart-d0c60c11-9c21-4b70-beee-d16e71e20a09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4217906340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.4217906340
Directory	/workspace/21.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2319265239
Short name	T327
Test name
Test status
Simulation time	11115014 ps
CPU time	1.92 seconds
Started	Feb 25 02:28:04 PM PST 24
Finished	Feb 25 02:28:06 PM PST 24
Peak memory	203040 kb
Host	smart-a7052798-10a6-4772-8b3c-6f79832b5c6b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2319265239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2319265239
Directory	/workspace/21.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1995252840
Short name	T890
Test name
Test status
Simulation time	426715081 ps
CPU time	44.76 seconds
Started	Feb 25 02:28:04 PM PST 24
Finished	Feb 25 02:28:49 PM PST 24
Peak memory	205408 kb
Host	smart-6a6ff68b-628b-4188-b34c-010a7093f5e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1995252840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1995252840
Directory	/workspace/22.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.2529311608
Short name	T142
Test name
Test status
Simulation time	158843226396 ps
CPU time	535.95 seconds
Started	Feb 25 02:28:05 PM PST 24
Finished	Feb 25 02:37:01 PM PST 24
Peak memory	211320 kb
Host	smart-2c86a3a2-d403-4658-9b29-0a38301ec7f0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2529311608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.2529311608
Directory	/workspace/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.851571125
Short name	T761
Test name
Test status
Simulation time	150549752 ps
CPU time	19.27 seconds
Started	Feb 25 02:28:06 PM PST 24
Finished	Feb 25 02:28:26 PM PST 24
Peak memory	203056 kb
Host	smart-2f67d702-ea4a-4151-9a35-a872d631a0da
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=851571125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.851571125
Directory	/workspace/22.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_error_random.2518415455
Short name	T207
Test name
Test status
Simulation time	472987918 ps
CPU time	16.02 seconds
Started	Feb 25 02:28:07 PM PST 24
Finished	Feb 25 02:28:23 PM PST 24
Peak memory	203044 kb
Host	smart-041af18a-ab9a-42b8-b143-6e6e2333f354
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2518415455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2518415455
Directory	/workspace/22.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random.1074284589
Short name	T613
Test name
Test status
Simulation time	3085662175 ps
CPU time	28.52 seconds
Started	Feb 25 02:27:56 PM PST 24
Finished	Feb 25 02:28:25 PM PST 24
Peak memory	204088 kb
Host	smart-68b0f20d-c718-4155-9c3b-db804a388c47
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1074284589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1074284589
Directory	/workspace/22.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.3171758231
Short name	T232
Test name
Test status
Simulation time	76389966601 ps
CPU time	269.86 seconds
Started	Feb 25 02:28:05 PM PST 24
Finished	Feb 25 02:32:35 PM PST 24
Peak memory	211304 kb
Host	smart-175091ab-4fcd-4993-a631-ea334b69a4ac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171758231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3171758231
Directory	/workspace/22.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.3898624642
Short name	T494
Test name
Test status
Simulation time	23196815258 ps
CPU time	211.91 seconds
Started	Feb 25 02:28:08 PM PST 24
Finished	Feb 25 02:31:40 PM PST 24
Peak memory	211288 kb
Host	smart-f08eccc2-0ae1-45c8-8965-a33af42bcf5e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3898624642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3898624642
Directory	/workspace/22.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.4012412022
Short name	T147
Test name
Test status
Simulation time	545795961 ps
CPU time	20.53 seconds
Started	Feb 25 02:28:01 PM PST 24
Finished	Feb 25 02:28:22 PM PST 24
Peak memory	211232 kb
Host	smart-1231885b-9520-4e10-96f9-f647dfe34fca
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012412022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.4012412022
Directory	/workspace/22.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_same_source.2433013007
Short name	T279
Test name
Test status
Simulation time	851295960 ps
CPU time	21.14 seconds
Started	Feb 25 02:28:10 PM PST 24
Finished	Feb 25 02:28:31 PM PST 24
Peak memory	203472 kb
Host	smart-1ff409e2-930a-4e49-903c-ff841b67304f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2433013007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2433013007
Directory	/workspace/22.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke.3406938250
Short name	T444
Test name
Test status
Simulation time	88917238 ps
CPU time	2.48 seconds
Started	Feb 25 02:28:05 PM PST 24
Finished	Feb 25 02:28:08 PM PST 24
Peak memory	203084 kb
Host	smart-08dca3aa-08db-4ea5-a527-4db53110fe34
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3406938250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3406938250
Directory	/workspace/22.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.3881428008
Short name	T870
Test name
Test status
Simulation time	6127370117 ps
CPU time	32.52 seconds
Started	Feb 25 02:27:59 PM PST 24
Finished	Feb 25 02:28:32 PM PST 24
Peak memory	203120 kb
Host	smart-39be5336-25d8-434f-8436-8807b9401b9b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881428008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.3881428008
Directory	/workspace/22.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.774434091
Short name	T862
Test name
Test status
Simulation time	4521238655 ps
CPU time	19.98 seconds
Started	Feb 25 02:27:58 PM PST 24
Finished	Feb 25 02:28:18 PM PST 24
Peak memory	203048 kb
Host	smart-df5f4ef6-124d-4e1f-bb1d-2a51c21254eb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=774434091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.774434091
Directory	/workspace/22.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.4217648847
Short name	T654
Test name
Test status
Simulation time	29634484 ps
CPU time	2.62 seconds
Started	Feb 25 02:27:58 PM PST 24
Finished	Feb 25 02:28:01 PM PST 24
Peak memory	203056 kb
Host	smart-901253ab-59f9-4080-935d-560db0f04675
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217648847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.4217648847
Directory	/workspace/22.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all.4099535327
Short name	T86
Test name
Test status
Simulation time	7467025444 ps
CPU time	70.45 seconds
Started	Feb 25 02:28:07 PM PST 24
Finished	Feb 25 02:29:17 PM PST 24
Peak memory	205792 kb
Host	smart-054faea2-7a16-4fb2-95f8-6d21b79dd8c6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4099535327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.4099535327
Directory	/workspace/22.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.56089500
Short name	T604
Test name
Test status
Simulation time	15090666850 ps
CPU time	154.46 seconds
Started	Feb 25 02:27:59 PM PST 24
Finished	Feb 25 02:30:34 PM PST 24
Peak memory	208184 kb
Host	smart-29ed2c74-302e-4c14-b1a9-067cb9da3eb3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=56089500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.56089500
Directory	/workspace/22.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3062920233
Short name	T175
Test name
Test status
Simulation time	39740739 ps
CPU time	12.98 seconds
Started	Feb 25 02:28:10 PM PST 24
Finished	Feb 25 02:28:23 PM PST 24
Peak memory	205608 kb
Host	smart-91c63391-b736-4804-ba59-f07e57292a5c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3062920233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.3062920233
Directory	/workspace/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.3969168201
Short name	T296
Test name
Test status
Simulation time	6811102 ps
CPU time	2.65 seconds
Started	Feb 25 02:28:08 PM PST 24
Finished	Feb 25 02:28:11 PM PST 24
Peak memory	203044 kb
Host	smart-68816c35-a005-460e-a416-a244cfb6964d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3969168201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.3969168201
Directory	/workspace/22.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.2058344456
Short name	T584
Test name
Test status
Simulation time	5367019457 ps
CPU time	34.47 seconds
Started	Feb 25 02:28:04 PM PST 24
Finished	Feb 25 02:28:38 PM PST 24
Peak memory	204596 kb
Host	smart-596310ed-703a-4414-81fb-d67ab812afd3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2058344456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2058344456
Directory	/workspace/22.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device.3999611890
Short name	T126
Test name
Test status
Simulation time	5877036147 ps
CPU time	34.72 seconds
Started	Feb 25 02:28:05 PM PST 24
Finished	Feb 25 02:28:40 PM PST 24
Peak memory	211288 kb
Host	smart-74f1d193-cf34-4847-aec1-492a4b7143f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3999611890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3999611890
Directory	/workspace/23.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.1302413798
Short name	T633
Test name
Test status
Simulation time	12211926715 ps
CPU time	93.62 seconds
Started	Feb 25 02:28:10 PM PST 24
Finished	Feb 25 02:29:44 PM PST 24
Peak memory	211284 kb
Host	smart-09ff3f82-30ab-4659-b21a-693c03e11a3b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1302413798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.1302413798
Directory	/workspace/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.31822172
Short name	T686
Test name
Test status
Simulation time	555612626 ps
CPU time	10.82 seconds
Started	Feb 25 02:28:15 PM PST 24
Finished	Feb 25 02:28:28 PM PST 24
Peak memory	203052 kb
Host	smart-84e5e4c7-a3aa-48ec-b812-d0f5888ac10c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=31822172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.31822172
Directory	/workspace/23.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_error_random.3158037945
Short name	T785
Test name
Test status
Simulation time	2132405607 ps
CPU time	21.79 seconds
Started	Feb 25 02:28:14 PM PST 24
Finished	Feb 25 02:28:38 PM PST 24
Peak memory	203044 kb
Host	smart-f447c087-a4d0-46e4-b10a-867220b35473
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3158037945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3158037945
Directory	/workspace/23.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random.1886800108
Short name	T624
Test name
Test status
Simulation time	5182272243 ps
CPU time	43.73 seconds
Started	Feb 25 02:27:59 PM PST 24
Finished	Feb 25 02:28:43 PM PST 24
Peak memory	204736 kb
Host	smart-f7bcee0b-edce-4234-b3d0-6ca4042a3575
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1886800108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1886800108
Directory	/workspace/23.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.3925632625
Short name	T474
Test name
Test status
Simulation time	86734051056 ps
CPU time	175.06 seconds
Started	Feb 25 02:28:03 PM PST 24
Finished	Feb 25 02:30:59 PM PST 24
Peak memory	204384 kb
Host	smart-0273d758-22d7-4631-8918-625d4188aa9c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925632625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3925632625
Directory	/workspace/23.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.841774830
Short name	T434
Test name
Test status
Simulation time	42121105271 ps
CPU time	191.41 seconds
Started	Feb 25 02:28:04 PM PST 24
Finished	Feb 25 02:31:16 PM PST 24
Peak memory	211292 kb
Host	smart-69935eca-a552-45fd-a5b6-b73dd4bab78c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=841774830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.841774830
Directory	/workspace/23.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.2701883497
Short name	T713
Test name
Test status
Simulation time	31183478 ps
CPU time	2.43 seconds
Started	Feb 25 02:28:08 PM PST 24
Finished	Feb 25 02:28:10 PM PST 24
Peak memory	203084 kb
Host	smart-051040fc-ce97-41e4-ade7-4100fecf2368
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701883497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2701883497
Directory	/workspace/23.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_same_source.4091385438
Short name	T165
Test name
Test status
Simulation time	1160444466 ps
CPU time	28.41 seconds
Started	Feb 25 02:28:07 PM PST 24
Finished	Feb 25 02:28:35 PM PST 24
Peak memory	202620 kb
Host	smart-de2dcc06-c60f-47a0-9a2b-03f0669fc4e0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4091385438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.4091385438
Directory	/workspace/23.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke.2032019091
Short name	T626
Test name
Test status
Simulation time	73048901 ps
CPU time	2.31 seconds
Started	Feb 25 02:28:06 PM PST 24
Finished	Feb 25 02:28:09 PM PST 24
Peak memory	203068 kb
Host	smart-3942cded-4c77-458e-a2d3-4b1e27427fda
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2032019091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2032019091
Directory	/workspace/23.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2194388161
Short name	T304
Test name
Test status
Simulation time	15291877089 ps
CPU time	32.71 seconds
Started	Feb 25 02:28:04 PM PST 24
Finished	Feb 25 02:28:37 PM PST 24
Peak memory	203112 kb
Host	smart-c91fe22f-2574-40ee-8001-0513154e060b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194388161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2194388161
Directory	/workspace/23.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.2342706781
Short name	T844
Test name
Test status
Simulation time	4219080464 ps
CPU time	27.86 seconds
Started	Feb 25 02:28:10 PM PST 24
Finished	Feb 25 02:28:38 PM PST 24
Peak memory	203104 kb
Host	smart-5aa29b32-42b0-45e1-817e-6cd53267be03
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2342706781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2342706781
Directory	/workspace/23.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.482490799
Short name	T72
Test name
Test status
Simulation time	29498874 ps
CPU time	2.41 seconds
Started	Feb 25 02:28:03 PM PST 24
Finished	Feb 25 02:28:06 PM PST 24
Peak memory	203032 kb
Host	smart-e42ff2b5-f93c-496c-85d4-884d87fd65db
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482490799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.482490799
Directory	/workspace/23.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all.2319429632
Short name	T734
Test name
Test status
Simulation time	3364928717 ps
CPU time	57.5 seconds
Started	Feb 25 02:28:17 PM PST 24
Finished	Feb 25 02:29:15 PM PST 24
Peak memory	205568 kb
Host	smart-3f6ac902-7b0d-4b05-b30f-78b8ed541128
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2319429632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2319429632
Directory	/workspace/23.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.317289771
Short name	T246
Test name
Test status
Simulation time	376631361 ps
CPU time	39.4 seconds
Started	Feb 25 02:28:09 PM PST 24
Finished	Feb 25 02:28:49 PM PST 24
Peak memory	206096 kb
Host	smart-a7a286de-643a-4edf-a7ae-51ade0e44dc8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=317289771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.317289771
Directory	/workspace/23.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.1489302675
Short name	T449
Test name
Test status
Simulation time	298741160 ps
CPU time	49.08 seconds
Started	Feb 25 02:28:11 PM PST 24
Finished	Feb 25 02:29:00 PM PST 24
Peak memory	206188 kb
Host	smart-88e8feb4-cc58-466e-b305-7d215d5eeb31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1489302675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.1489302675
Directory	/workspace/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2020522790
Short name	T32
Test name
Test status
Simulation time	454743265 ps
CPU time	128.97 seconds
Started	Feb 25 02:28:12 PM PST 24
Finished	Feb 25 02:30:21 PM PST 24
Peak memory	209916 kb
Host	smart-e966772f-fff6-4715-bad0-10dedac35056
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2020522790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.2020522790
Directory	/workspace/23.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.1447362521
Short name	T676
Test name
Test status
Simulation time	71223039 ps
CPU time	4.6 seconds
Started	Feb 25 02:28:17 PM PST 24
Finished	Feb 25 02:28:22 PM PST 24
Peak memory	211240 kb
Host	smart-d031a7f1-2477-4076-bd2c-14e2193dc50b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1447362521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1447362521
Directory	/workspace/23.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2508074372
Short name	T621
Test name
Test status
Simulation time	1286562881 ps
CPU time	18.99 seconds
Started	Feb 25 02:28:11 PM PST 24
Finished	Feb 25 02:28:31 PM PST 24
Peak memory	211232 kb
Host	smart-59f083d9-206d-4950-84e9-0479975be8bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2508074372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2508074372
Directory	/workspace/24.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.2590557472
Short name	T98
Test name
Test status
Simulation time	17116218297 ps
CPU time	121.47 seconds
Started	Feb 25 02:28:10 PM PST 24
Finished	Feb 25 02:30:12 PM PST 24
Peak memory	211320 kb
Host	smart-7da3644f-c41e-4a74-9384-50525ca5ed7f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2590557472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_sl ow_rsp.2590557472
Directory	/workspace/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.647448570
Short name	T823
Test name
Test status
Simulation time	330520159 ps
CPU time	9.03 seconds
Started	Feb 25 02:28:25 PM PST 24
Finished	Feb 25 02:28:34 PM PST 24
Peak memory	203072 kb
Host	smart-327fe05f-649c-454c-80b9-130dddc40a60
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647448570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.647448570
Directory	/workspace/24.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_error_random.3375994707
Short name	T290
Test name
Test status
Simulation time	2950594346 ps
CPU time	27.86 seconds
Started	Feb 25 02:28:15 PM PST 24
Finished	Feb 25 02:28:45 PM PST 24
Peak memory	203116 kb
Host	smart-e0c47c32-53cf-434e-bfef-d0f8c18e4012
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3375994707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3375994707
Directory	/workspace/24.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random.452864431
Short name	T740
Test name
Test status
Simulation time	419701655 ps
CPU time	8.21 seconds
Started	Feb 25 02:28:11 PM PST 24
Finished	Feb 25 02:28:20 PM PST 24
Peak memory	204072 kb
Host	smart-16dd46b7-9571-4a55-bb80-d232c554d005
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=452864431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.452864431
Directory	/workspace/24.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.4076389159
Short name	T492
Test name
Test status
Simulation time	34611215708 ps
CPU time	199.47 seconds
Started	Feb 25 02:28:12 PM PST 24
Finished	Feb 25 02:31:32 PM PST 24
Peak memory	211332 kb
Host	smart-3e312385-575b-4a64-8ecc-bc2fd272f3ac
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076389159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4076389159
Directory	/workspace/24.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2142102265
Short name	T366
Test name
Test status
Simulation time	82139015124 ps
CPU time	234.52 seconds
Started	Feb 25 02:28:13 PM PST 24
Finished	Feb 25 02:32:10 PM PST 24
Peak memory	211288 kb
Host	smart-daac1d23-e33c-40f0-9d8e-78e7db4a13a7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2142102265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2142102265
Directory	/workspace/24.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1023182743
Short name	T426
Test name
Test status
Simulation time	195406487 ps
CPU time	8.76 seconds
Started	Feb 25 02:28:11 PM PST 24
Finished	Feb 25 02:28:21 PM PST 24
Peak memory	211248 kb
Host	smart-83de4d8f-e8b8-439e-a5fa-1cd99a415e8e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023182743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1023182743
Directory	/workspace/24.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_same_source.3727266985
Short name	T876
Test name
Test status
Simulation time	664324294 ps
CPU time	11.85 seconds
Started	Feb 25 02:28:12 PM PST 24
Finished	Feb 25 02:28:24 PM PST 24
Peak memory	203420 kb
Host	smart-156866a5-1bde-4100-9eb1-313cb205f542
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3727266985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3727266985
Directory	/workspace/24.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke.970740789
Short name	T111
Test name
Test status
Simulation time	178795304 ps
CPU time	3.15 seconds
Started	Feb 25 02:28:10 PM PST 24
Finished	Feb 25 02:28:13 PM PST 24
Peak memory	203032 kb
Host	smart-2b7ca33b-7290-4534-8e4e-308b21353cdd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=970740789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.970740789
Directory	/workspace/24.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1658240050
Short name	T598
Test name
Test status
Simulation time	20438890491 ps
CPU time	35.72 seconds
Started	Feb 25 02:28:11 PM PST 24
Finished	Feb 25 02:28:47 PM PST 24
Peak memory	203100 kb
Host	smart-0edaec24-1040-419c-b8a0-5422a34dfe80
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1658240050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1658240050
Directory	/workspace/24.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3466994133
Short name	T405
Test name
Test status
Simulation time	28894268 ps
CPU time	2.27 seconds
Started	Feb 25 02:28:13 PM PST 24
Finished	Feb 25 02:28:17 PM PST 24
Peak memory	203056 kb
Host	smart-cebb0787-dabe-4702-8f1f-c8e7bbfe658e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466994133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3466994133
Directory	/workspace/24.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all.2773964690
Short name	T156
Test name
Test status
Simulation time	3196361482 ps
CPU time	82.03 seconds
Started	Feb 25 02:28:27 PM PST 24
Finished	Feb 25 02:29:49 PM PST 24
Peak memory	206404 kb
Host	smart-70f2fb5e-1118-4c84-a99e-cd3113da2e42
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2773964690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2773964690
Directory	/workspace/24.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.622230991
Short name	T151
Test name
Test status
Simulation time	2105354462 ps
CPU time	138.62 seconds
Started	Feb 25 02:28:35 PM PST 24
Finished	Feb 25 02:30:54 PM PST 24
Peak memory	206104 kb
Host	smart-fca4eefe-240e-4c8b-8a78-8a4c36fe3952
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=622230991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.622230991
Directory	/workspace/24.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3531612615
Short name	T782
Test name
Test status
Simulation time	1176202724 ps
CPU time	228.63 seconds
Started	Feb 25 02:28:24 PM PST 24
Finished	Feb 25 02:32:13 PM PST 24
Peak memory	219444 kb
Host	smart-cebf2324-8d28-4fdb-88b2-ce1036647226
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3531612615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.3531612615
Directory	/workspace/24.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.820658911
Short name	T377
Test name
Test status
Simulation time	146520647 ps
CPU time	20.52 seconds
Started	Feb 25 02:28:25 PM PST 24
Finished	Feb 25 02:28:45 PM PST 24
Peak memory	204624 kb
Host	smart-b5343e83-3852-41e4-a66c-3c5afa753a9b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=820658911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.820658911
Directory	/workspace/24.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3221149208
Short name	T200
Test name
Test status
Simulation time	525748117 ps
CPU time	41.3 seconds
Started	Feb 25 02:28:25 PM PST 24
Finished	Feb 25 02:29:06 PM PST 24
Peak memory	204280 kb
Host	smart-72bcae12-6a89-4d67-9fa4-90f60a127b3c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3221149208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3221149208
Directory	/workspace/25.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2361672746
Short name	T565
Test name
Test status
Simulation time	98560068873 ps
CPU time	445.14 seconds
Started	Feb 25 02:28:25 PM PST 24
Finished	Feb 25 02:35:50 PM PST 24
Peak memory	206372 kb
Host	smart-9a0b57d2-d389-4a20-9d24-b9b45f4c5e9d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2361672746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl ow_rsp.2361672746
Directory	/workspace/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.839168459
Short name	T781
Test name
Test status
Simulation time	186393970 ps
CPU time	8.6 seconds
Started	Feb 25 02:28:26 PM PST 24
Finished	Feb 25 02:28:35 PM PST 24
Peak memory	203280 kb
Host	smart-8aa77be3-8778-4844-b003-485a2bd9081f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=839168459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.839168459
Directory	/workspace/25.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_error_random.3616203258
Short name	T615
Test name
Test status
Simulation time	749224319 ps
CPU time	23.32 seconds
Started	Feb 25 02:28:24 PM PST 24
Finished	Feb 25 02:28:47 PM PST 24
Peak memory	202988 kb
Host	smart-345110c7-8c0f-481e-a92f-fe293c645ff3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3616203258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3616203258
Directory	/workspace/25.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random.3665720068
Short name	T831
Test name
Test status
Simulation time	387816991 ps
CPU time	5.21 seconds
Started	Feb 25 02:28:24 PM PST 24
Finished	Feb 25 02:28:29 PM PST 24
Peak memory	203744 kb
Host	smart-2db78b55-b7c8-4a1b-94be-48267aaa9a06
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3665720068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3665720068
Directory	/workspace/25.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.1211468083
Short name	T133
Test name
Test status
Simulation time	40448811605 ps
CPU time	246.24 seconds
Started	Feb 25 02:28:26 PM PST 24
Finished	Feb 25 02:32:32 PM PST 24
Peak memory	211316 kb
Host	smart-cbcd99a5-34f5-4e8a-a4ce-a609dba4fd04
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211468083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1211468083
Directory	/workspace/25.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1354566348
Short name	T119
Test name
Test status
Simulation time	6151127572 ps
CPU time	23.12 seconds
Started	Feb 25 02:28:29 PM PST 24
Finished	Feb 25 02:28:52 PM PST 24
Peak memory	203908 kb
Host	smart-8051773d-514e-4189-9a1d-8edccb7cbff4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1354566348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1354566348
Directory	/workspace/25.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.1001231826
Short name	T574
Test name
Test status
Simulation time	118262069 ps
CPU time	13.3 seconds
Started	Feb 25 02:28:24 PM PST 24
Finished	Feb 25 02:28:37 PM PST 24
Peak memory	203680 kb
Host	smart-8c651152-9419-4d9b-b5f7-1ffc9b9cf909
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001231826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1001231826
Directory	/workspace/25.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_same_source.3340318547
Short name	T759
Test name
Test status
Simulation time	244781964 ps
CPU time	5.18 seconds
Started	Feb 25 02:28:24 PM PST 24
Finished	Feb 25 02:28:29 PM PST 24
Peak memory	203320 kb
Host	smart-e8dfb3ba-0437-45b1-b928-ee394e1c70a1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3340318547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3340318547
Directory	/workspace/25.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke.4046145471
Short name	T509
Test name
Test status
Simulation time	184702180 ps
CPU time	3.28 seconds
Started	Feb 25 02:28:24 PM PST 24
Finished	Feb 25 02:28:28 PM PST 24
Peak memory	203076 kb
Host	smart-f1516f0c-7829-4044-85ee-1d5be81bf081
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4046145471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4046145471
Directory	/workspace/25.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2939946519
Short name	T420
Test name
Test status
Simulation time	7261452451 ps
CPU time	22.62 seconds
Started	Feb 25 02:28:25 PM PST 24
Finished	Feb 25 02:28:47 PM PST 24
Peak memory	203124 kb
Host	smart-12ef98e2-6949-48b1-853b-01e6b266101a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939946519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2939946519
Directory	/workspace/25.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2422022214
Short name	T690
Test name
Test status
Simulation time	4411446403 ps
CPU time	33.65 seconds
Started	Feb 25 02:28:36 PM PST 24
Finished	Feb 25 02:29:10 PM PST 24
Peak memory	203104 kb
Host	smart-8756815b-e5d3-409d-903f-8a7d717b571c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2422022214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2422022214
Directory	/workspace/25.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2698277864
Short name	T714
Test name
Test status
Simulation time	103266408 ps
CPU time	2.56 seconds
Started	Feb 25 02:28:25 PM PST 24
Finished	Feb 25 02:28:27 PM PST 24
Peak memory	203068 kb
Host	smart-188b1fed-3a45-4db3-b1c5-c2b9cc0e1152
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698277864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2698277864
Directory	/workspace/25.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all.227434600
Short name	T848
Test name
Test status
Simulation time	956243370 ps
CPU time	36.15 seconds
Started	Feb 25 02:28:25 PM PST 24
Finished	Feb 25 02:29:02 PM PST 24
Peak memory	204528 kb
Host	smart-471f9b30-b2cb-4706-89eb-d3796ff2eb83
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=227434600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.227434600
Directory	/workspace/25.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.261894175
Short name	T388
Test name
Test status
Simulation time	1492442202 ps
CPU time	166.47 seconds
Started	Feb 25 02:28:25 PM PST 24
Finished	Feb 25 02:31:12 PM PST 24
Peak memory	206264 kb
Host	smart-de2d0908-6849-4c02-aa73-54ba3a42f403
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=261894175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.261894175
Directory	/workspace/25.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.177283788
Short name	T197
Test name
Test status
Simulation time	1989054860 ps
CPU time	393.11 seconds
Started	Feb 25 02:28:36 PM PST 24
Finished	Feb 25 02:35:09 PM PST 24
Peak memory	209216 kb
Host	smart-61c7d705-6bf6-42c5-81c4-660b9f07dfec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=177283788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand _reset.177283788
Directory	/workspace/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.831274302
Short name	T750
Test name
Test status
Simulation time	1958560112 ps
CPU time	255.96 seconds
Started	Feb 25 02:28:26 PM PST 24
Finished	Feb 25 02:32:42 PM PST 24
Peak memory	211168 kb
Host	smart-255e8ec0-3ac4-4553-ad32-ec3e57321971
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=831274302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_res et_error.831274302
Directory	/workspace/25.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.4229606274
Short name	T571
Test name
Test status
Simulation time	1981683551 ps
CPU time	29.78 seconds
Started	Feb 25 02:28:26 PM PST 24
Finished	Feb 25 02:28:56 PM PST 24
Peak memory	211252 kb
Host	smart-0ed1188b-b34f-494e-9076-29574f072521
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4229606274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.4229606274
Directory	/workspace/25.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3001294696
Short name	T501
Test name
Test status
Simulation time	2766897046 ps
CPU time	24.07 seconds
Started	Feb 25 02:28:44 PM PST 24
Finished	Feb 25 02:29:08 PM PST 24
Peak memory	211292 kb
Host	smart-df4eef85-4302-45dd-ba53-75fd1ae756db
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3001294696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3001294696
Directory	/workspace/26.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.862396747
Short name	T3
Test name
Test status
Simulation time	86473553616 ps
CPU time	276.45 seconds
Started	Feb 25 02:28:44 PM PST 24
Finished	Feb 25 02:33:20 PM PST 24
Peak memory	205896 kb
Host	smart-9704adc3-d14a-4ba8-8a4d-8afc9a3941db
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=862396747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slo w_rsp.862396747
Directory	/workspace/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3218129930
Short name	T675
Test name
Test status
Simulation time	218957037 ps
CPU time	8.06 seconds
Started	Feb 25 02:28:43 PM PST 24
Finished	Feb 25 02:28:51 PM PST 24
Peak memory	203056 kb
Host	smart-9a1f7043-c2da-421e-9d02-8c6a67cef232
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3218129930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3218129930
Directory	/workspace/26.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_error_random.3745826296
Short name	T773
Test name
Test status
Simulation time	84930910 ps
CPU time	5.03 seconds
Started	Feb 25 02:28:48 PM PST 24
Finished	Feb 25 02:28:53 PM PST 24
Peak memory	203056 kb
Host	smart-f0281143-d15f-4696-88e4-aa35a1cf0bdd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745826296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3745826296
Directory	/workspace/26.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random.787536072
Short name	T101
Test name
Test status
Simulation time	3801514978 ps
CPU time	23.03 seconds
Started	Feb 25 02:28:28 PM PST 24
Finished	Feb 25 02:28:51 PM PST 24
Peak memory	204180 kb
Host	smart-e6ec01bd-ca2b-4ab0-9e22-f87f5c4eb5cf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=787536072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.787536072
Directory	/workspace/26.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1250927878
Short name	T673
Test name
Test status
Simulation time	83516360152 ps
CPU time	190.18 seconds
Started	Feb 25 02:28:43 PM PST 24
Finished	Feb 25 02:31:53 PM PST 24
Peak memory	211304 kb
Host	smart-00f93ff2-b081-438b-9fbe-83d9df476de4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1250927878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1250927878
Directory	/workspace/26.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2791931941
Short name	T343
Test name
Test status
Simulation time	126050316 ps
CPU time	15.64 seconds
Started	Feb 25 02:28:23 PM PST 24
Finished	Feb 25 02:28:39 PM PST 24
Peak memory	211216 kb
Host	smart-2570742b-d095-496e-89d1-4fce6b871bfe
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791931941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2791931941
Directory	/workspace/26.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_same_source.1769637101
Short name	T618
Test name
Test status
Simulation time	59752400 ps
CPU time	3.24 seconds
Started	Feb 25 02:28:40 PM PST 24
Finished	Feb 25 02:28:44 PM PST 24
Peak memory	202988 kb
Host	smart-81b174d1-187a-46e8-85a1-42b481b44bb2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1769637101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1769637101
Directory	/workspace/26.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke.2047600539
Short name	T352
Test name
Test status
Simulation time	373183380 ps
CPU time	3.21 seconds
Started	Feb 25 02:28:25 PM PST 24
Finished	Feb 25 02:28:29 PM PST 24
Peak memory	203040 kb
Host	smart-46fb8bbe-1e26-410f-b4c1-e25c2b3de52c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2047600539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2047600539
Directory	/workspace/26.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3550688108
Short name	T350
Test name
Test status
Simulation time	7092057323 ps
CPU time	31.51 seconds
Started	Feb 25 02:28:28 PM PST 24
Finished	Feb 25 02:28:59 PM PST 24
Peak memory	203068 kb
Host	smart-3a00ba75-5b9a-490b-913c-96f6263e0751
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550688108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3550688108
Directory	/workspace/26.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3276205441
Short name	T620
Test name
Test status
Simulation time	3128191609 ps
CPU time	20.25 seconds
Started	Feb 25 02:28:36 PM PST 24
Finished	Feb 25 02:28:56 PM PST 24
Peak memory	203104 kb
Host	smart-4cbcab92-e30c-4542-a05b-19859c8f0277
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3276205441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3276205441
Directory	/workspace/26.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.4019656583
Short name	T898
Test name
Test status
Simulation time	56827883 ps
CPU time	2.17 seconds
Started	Feb 25 02:28:26 PM PST 24
Finished	Feb 25 02:28:28 PM PST 24
Peak memory	203052 kb
Host	smart-76c3e870-8207-4225-ae02-2f337995d503
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019656583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.4019656583
Directory	/workspace/26.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all.3435362072
Short name	T842
Test name
Test status
Simulation time	650448345 ps
CPU time	56.09 seconds
Started	Feb 25 02:28:40 PM PST 24
Finished	Feb 25 02:29:36 PM PST 24
Peak memory	205356 kb
Host	smart-7cc16ca0-1239-451f-a19a-9032ec4adaf5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3435362072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3435362072
Directory	/workspace/26.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.2354112593
Short name	T264
Test name
Test status
Simulation time	8344527116 ps
CPU time	160.65 seconds
Started	Feb 25 02:28:48 PM PST 24
Finished	Feb 25 02:31:29 PM PST 24
Peak memory	207804 kb
Host	smart-6204516c-689f-403f-9bfe-5b702d45a853
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2354112593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2354112593
Directory	/workspace/26.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.1847526557
Short name	T567
Test name
Test status
Simulation time	254177104 ps
CPU time	71.33 seconds
Started	Feb 25 02:28:44 PM PST 24
Finished	Feb 25 02:29:55 PM PST 24
Peak memory	206280 kb
Host	smart-ab206044-6431-4c6a-84a2-f2ea11a6ea5a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1847526557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran d_reset.1847526557
Directory	/workspace/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.4143415851
Short name	T409
Test name
Test status
Simulation time	1507063559 ps
CPU time	23.97 seconds
Started	Feb 25 02:28:38 PM PST 24
Finished	Feb 25 02:29:02 PM PST 24
Peak memory	204636 kb
Host	smart-248b6401-cb40-4383-9fef-94177b975193
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4143415851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4143415851
Directory	/workspace/26.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device.3592879920
Short name	T841
Test name
Test status
Simulation time	7518436143 ps
CPU time	47.12 seconds
Started	Feb 25 02:28:39 PM PST 24
Finished	Feb 25 02:29:26 PM PST 24
Peak memory	205960 kb
Host	smart-cee901cf-aad7-45b2-9cbe-ec3352f19e59
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3592879920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3592879920
Directory	/workspace/27.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.4157020921
Short name	T141
Test name
Test status
Simulation time	22675466407 ps
CPU time	189.81 seconds
Started	Feb 25 02:28:41 PM PST 24
Finished	Feb 25 02:31:51 PM PST 24
Peak memory	211208 kb
Host	smart-0d9b62ba-7aaf-472c-b325-a386e3952c89
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4157020921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.4157020921
Directory	/workspace/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1332222419
Short name	T619
Test name
Test status
Simulation time	327656267 ps
CPU time	10.85 seconds
Started	Feb 25 02:28:41 PM PST 24
Finished	Feb 25 02:28:52 PM PST 24
Peak memory	203072 kb
Host	smart-5db712f2-0dcd-47a9-a9bc-1ec4ca0e2d0e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1332222419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1332222419
Directory	/workspace/27.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_error_random.4117067391
Short name	T324
Test name
Test status
Simulation time	466009099 ps
CPU time	20.9 seconds
Started	Feb 25 02:28:40 PM PST 24
Finished	Feb 25 02:29:01 PM PST 24
Peak memory	203112 kb
Host	smart-645c7f16-f102-4127-9367-18624a76e0c8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4117067391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.4117067391
Directory	/workspace/27.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random.962132958
Short name	T10
Test name
Test status
Simulation time	93802920 ps
CPU time	2.56 seconds
Started	Feb 25 02:28:40 PM PST 24
Finished	Feb 25 02:28:42 PM PST 24
Peak memory	203032 kb
Host	smart-12aee255-41d5-434b-9e2f-610fa0d7c5ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=962132958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.962132958
Directory	/workspace/27.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1109850177
Short name	T743
Test name
Test status
Simulation time	86464092238 ps
CPU time	220.24 seconds
Started	Feb 25 02:28:39 PM PST 24
Finished	Feb 25 02:32:20 PM PST 24
Peak memory	204760 kb
Host	smart-abc7a572-bb8a-48f5-901e-cc27b8db59c9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109850177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1109850177
Directory	/workspace/27.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.30526120
Short name	T473
Test name
Test status
Simulation time	55556985100 ps
CPU time	146.01 seconds
Started	Feb 25 02:28:42 PM PST 24
Finished	Feb 25 02:31:08 PM PST 24
Peak memory	211316 kb
Host	smart-34e0ef66-74d6-4bf9-8e9b-eff5e3fe0d76
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=30526120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.30526120
Directory	/workspace/27.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.911165500
Short name	T859
Test name
Test status
Simulation time	779009206 ps
CPU time	18.17 seconds
Started	Feb 25 02:28:41 PM PST 24
Finished	Feb 25 02:28:59 PM PST 24
Peak memory	204080 kb
Host	smart-bdb960c2-144c-4cec-8f32-277ca8731c2d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911165500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.911165500
Directory	/workspace/27.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_same_source.3708254438
Short name	T760
Test name
Test status
Simulation time	347654804 ps
CPU time	6.03 seconds
Started	Feb 25 02:28:39 PM PST 24
Finished	Feb 25 02:28:46 PM PST 24
Peak memory	203048 kb
Host	smart-3dd791d1-da4b-4794-8f52-7c677bb52109
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3708254438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3708254438
Directory	/workspace/27.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke.779708720
Short name	T144
Test name
Test status
Simulation time	113484181 ps
CPU time	3.21 seconds
Started	Feb 25 02:28:42 PM PST 24
Finished	Feb 25 02:28:45 PM PST 24
Peak memory	203044 kb
Host	smart-ab9994a4-feeb-40a1-b5e0-5875f0f01c19
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=779708720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.779708720
Directory	/workspace/27.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.4274340376
Short name	T5
Test name
Test status
Simulation time	7445273750 ps
CPU time	32.5 seconds
Started	Feb 25 02:28:40 PM PST 24
Finished	Feb 25 02:29:12 PM PST 24
Peak memory	203116 kb
Host	smart-d92a5623-509a-4741-b135-43759b219472
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274340376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4274340376
Directory	/workspace/27.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3364983385
Short name	T696
Test name
Test status
Simulation time	3282170281 ps
CPU time	28.06 seconds
Started	Feb 25 02:28:48 PM PST 24
Finished	Feb 25 02:29:16 PM PST 24
Peak memory	203104 kb
Host	smart-2e3ef552-50ec-4c04-9caf-8bd39398f155
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3364983385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3364983385
Directory	/workspace/27.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.813993021
Short name	T287
Test name
Test status
Simulation time	60139036 ps
CPU time	2.7 seconds
Started	Feb 25 02:28:39 PM PST 24
Finished	Feb 25 02:28:42 PM PST 24
Peak memory	203032 kb
Host	smart-efb31210-1d81-4364-9913-93c1a224fd6e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813993021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.813993021
Directory	/workspace/27.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.139476020
Short name	T351
Test name
Test status
Simulation time	12199211220 ps
CPU time	173.91 seconds
Started	Feb 25 02:28:44 PM PST 24
Finished	Feb 25 02:31:38 PM PST 24
Peak memory	208068 kb
Host	smart-fc30d5e9-89c1-434b-b24e-c4281fbc8f97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=139476020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.139476020
Directory	/workspace/27.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2708349488
Short name	T341
Test name
Test status
Simulation time	442257055 ps
CPU time	156.21 seconds
Started	Feb 25 02:28:43 PM PST 24
Finished	Feb 25 02:31:19 PM PST 24
Peak memory	208076 kb
Host	smart-c4fef7ac-0fbf-4110-a856-8590b524d54f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2708349488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.2708349488
Directory	/workspace/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.2382513002
Short name	T8
Test name
Test status
Simulation time	27608425 ps
CPU time	12.2 seconds
Started	Feb 25 02:28:49 PM PST 24
Finished	Feb 25 02:29:01 PM PST 24
Peak memory	203732 kb
Host	smart-ba8adee4-5abf-4f04-b401-354cdab8ddc6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2382513002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re set_error.2382513002
Directory	/workspace/27.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.4194679916
Short name	T668
Test name
Test status
Simulation time	3180932815 ps
CPU time	27.8 seconds
Started	Feb 25 02:28:38 PM PST 24
Finished	Feb 25 02:29:06 PM PST 24
Peak memory	204344 kb
Host	smart-a5c727e5-d855-4f30-adf6-6ce3957eb635
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4194679916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.4194679916
Directory	/workspace/27.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device.1394107231
Short name	T453
Test name
Test status
Simulation time	51301211 ps
CPU time	3.35 seconds
Started	Feb 25 02:28:51 PM PST 24
Finished	Feb 25 02:28:54 PM PST 24
Peak memory	203056 kb
Host	smart-fdcbace6-4839-4ea9-8bb0-f5a44af75a11
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1394107231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1394107231
Directory	/workspace/28.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4162828689
Short name	T701
Test name
Test status
Simulation time	89449580008 ps
CPU time	697.96 seconds
Started	Feb 25 02:28:52 PM PST 24
Finished	Feb 25 02:40:30 PM PST 24
Peak memory	211296 kb
Host	smart-e808469f-e12c-46f8-898f-7fec7a18b21c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4162828689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl ow_rsp.4162828689
Directory	/workspace/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2300060188
Short name	T353
Test name
Test status
Simulation time	573862971 ps
CPU time	5.89 seconds
Started	Feb 25 02:28:47 PM PST 24
Finished	Feb 25 02:28:53 PM PST 24
Peak memory	203136 kb
Host	smart-bfeb7e13-31db-45d7-a6bf-8e934accf23b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2300060188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2300060188
Directory	/workspace/28.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_error_random.3439657267
Short name	T323
Test name
Test status
Simulation time	159338427 ps
CPU time	8.11 seconds
Started	Feb 25 02:28:48 PM PST 24
Finished	Feb 25 02:28:57 PM PST 24
Peak memory	203056 kb
Host	smart-a416db8f-e6e3-49a1-8bc8-c10e0b75ae22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3439657267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3439657267
Directory	/workspace/28.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random.4143221086
Short name	T606
Test name
Test status
Simulation time	1513399769 ps
CPU time	29.8 seconds
Started	Feb 25 02:28:45 PM PST 24
Finished	Feb 25 02:29:15 PM PST 24
Peak memory	204160 kb
Host	smart-b05d6086-3716-4840-b722-ba6fc869c8b2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4143221086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.4143221086
Directory	/workspace/28.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.1151525541
Short name	T53
Test name
Test status
Simulation time	45250573756 ps
CPU time	217.83 seconds
Started	Feb 25 02:29:00 PM PST 24
Finished	Feb 25 02:32:38 PM PST 24
Peak memory	211312 kb
Host	smart-c5760e7a-3367-4eb3-b67c-51106c182779
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151525541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1151525541
Directory	/workspace/28.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.524623830
Short name	T527
Test name
Test status
Simulation time	30063580684 ps
CPU time	134.09 seconds
Started	Feb 25 02:28:45 PM PST 24
Finished	Feb 25 02:30:59 PM PST 24
Peak memory	211304 kb
Host	smart-a81be074-ee0c-42f8-abfc-96f8bf673a58
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=524623830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.524623830
Directory	/workspace/28.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.2014371927
Short name	T179
Test name
Test status
Simulation time	195410144 ps
CPU time	24.76 seconds
Started	Feb 25 02:28:46 PM PST 24
Finished	Feb 25 02:29:11 PM PST 24
Peak memory	211252 kb
Host	smart-21ae5e01-1b30-4492-bafd-b46a4b299a0e
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014371927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2014371927
Directory	/workspace/28.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_same_source.4135837728
Short name	T566
Test name
Test status
Simulation time	1982925555 ps
CPU time	26.98 seconds
Started	Feb 25 02:29:00 PM PST 24
Finished	Feb 25 02:29:27 PM PST 24
Peak memory	203072 kb
Host	smart-753d3ec0-cdd9-46e4-aa25-db98fc0a47e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4135837728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.4135837728
Directory	/workspace/28.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke.919803360
Short name	T233
Test name
Test status
Simulation time	163965989 ps
CPU time	3.61 seconds
Started	Feb 25 02:28:59 PM PST 24
Finished	Feb 25 02:29:03 PM PST 24
Peak memory	203048 kb
Host	smart-15dbd620-0fd3-4ccc-9f27-5e8f8730b010
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=919803360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.919803360
Directory	/workspace/28.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1515156683
Short name	T239
Test name
Test status
Simulation time	11526805882 ps
CPU time	27.76 seconds
Started	Feb 25 02:28:43 PM PST 24
Finished	Feb 25 02:29:11 PM PST 24
Peak memory	203124 kb
Host	smart-4202b04e-f0f5-45a4-82a7-4bad3b21782f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515156683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1515156683
Directory	/workspace/28.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.2719301702
Short name	T557
Test name
Test status
Simulation time	7026357633 ps
CPU time	33.82 seconds
Started	Feb 25 02:28:51 PM PST 24
Finished	Feb 25 02:29:25 PM PST 24
Peak memory	203120 kb
Host	smart-ac5632c5-a9de-4882-8e2d-0a9165a11d80
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2719301702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2719301702
Directory	/workspace/28.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2139583427
Short name	T753
Test name
Test status
Simulation time	33643161 ps
CPU time	2.4 seconds
Started	Feb 25 02:28:52 PM PST 24
Finished	Feb 25 02:28:54 PM PST 24
Peak memory	203056 kb
Host	smart-b8a4844c-3d12-40bb-90c3-c741265d40f3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139583427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2139583427
Directory	/workspace/28.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all.3005032585
Short name	T580
Test name
Test status
Simulation time	37524781617 ps
CPU time	294.71 seconds
Started	Feb 25 02:28:46 PM PST 24
Finished	Feb 25 02:33:41 PM PST 24
Peak memory	206860 kb
Host	smart-d30b37a8-bc30-45f7-b64e-a4e25ca250fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3005032585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3005032585
Directory	/workspace/28.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2810711150
Short name	T28
Test name
Test status
Simulation time	263448883 ps
CPU time	82.13 seconds
Started	Feb 25 02:28:52 PM PST 24
Finished	Feb 25 02:30:14 PM PST 24
Peak memory	207424 kb
Host	smart-d4928c8d-f447-4def-a0b3-18eaffdc5c2a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2810711150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran d_reset.2810711150
Directory	/workspace/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.3870626391
Short name	T542
Test name
Test status
Simulation time	14150301559 ps
CPU time	335.95 seconds
Started	Feb 25 02:28:44 PM PST 24
Finished	Feb 25 02:34:20 PM PST 24
Peak memory	221132 kb
Host	smart-644629f8-591d-4b5a-9edd-22f9ddd5c91c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3870626391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.3870626391
Directory	/workspace/28.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2827002586
Short name	T736
Test name
Test status
Simulation time	27475291 ps
CPU time	1.94 seconds
Started	Feb 25 02:28:47 PM PST 24
Finished	Feb 25 02:28:49 PM PST 24
Peak memory	203024 kb
Host	smart-128e5cef-2caf-4c21-afea-b5986cf2793a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2827002586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2827002586
Directory	/workspace/28.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device.633347070
Short name	T446
Test name
Test status
Simulation time	1298516149 ps
CPU time	29.71 seconds
Started	Feb 25 02:28:53 PM PST 24
Finished	Feb 25 02:29:23 PM PST 24
Peak memory	205232 kb
Host	smart-f8cec015-d398-478f-8f84-599a701232cd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=633347070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.633347070
Directory	/workspace/29.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.943307386
Short name	T570
Test name
Test status
Simulation time	56613784846 ps
CPU time	228.82 seconds
Started	Feb 25 02:29:00 PM PST 24
Finished	Feb 25 02:32:49 PM PST 24
Peak memory	211312 kb
Host	smart-f9b7e09b-de56-42e8-9316-1907fa24d57a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=943307386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slo w_rsp.943307386
Directory	/workspace/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1203649941
Short name	T380
Test name
Test status
Simulation time	1923232955 ps
CPU time	30.63 seconds
Started	Feb 25 02:28:51 PM PST 24
Finished	Feb 25 02:29:22 PM PST 24
Peak memory	203056 kb
Host	smart-8638d438-93c8-4be4-9f57-310f03b0009f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1203649941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1203649941
Directory	/workspace/29.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_error_random.1268048752
Short name	T874
Test name
Test status
Simulation time	170381372 ps
CPU time	12.33 seconds
Started	Feb 25 02:29:04 PM PST 24
Finished	Feb 25 02:29:16 PM PST 24
Peak memory	203056 kb
Host	smart-228b2a75-d223-4187-8922-3c31cd99d3af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1268048752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1268048752
Directory	/workspace/29.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random.2723392959
Short name	T360
Test name
Test status
Simulation time	591963474 ps
CPU time	19.65 seconds
Started	Feb 25 02:29:04 PM PST 24
Finished	Feb 25 02:29:24 PM PST 24
Peak memory	204084 kb
Host	smart-fd120141-c14d-441a-a3b3-1d507932683d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2723392959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2723392959
Directory	/workspace/29.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.208614569
Short name	T315
Test name
Test status
Simulation time	294703208625 ps
CPU time	328.46 seconds
Started	Feb 25 02:28:51 PM PST 24
Finished	Feb 25 02:34:20 PM PST 24
Peak memory	211308 kb
Host	smart-6ce0a621-beb7-49b1-b6fe-f13f29631a11
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=208614569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.208614569
Directory	/workspace/29.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3071941294
Short name	T56
Test name
Test status
Simulation time	27532829994 ps
CPU time	120.68 seconds
Started	Feb 25 02:28:57 PM PST 24
Finished	Feb 25 02:30:57 PM PST 24
Peak memory	204264 kb
Host	smart-44771390-c98c-49b2-b559-45cb16827602
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3071941294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3071941294
Directory	/workspace/29.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.4093934212
Short name	T478
Test name
Test status
Simulation time	111052813 ps
CPU time	12.87 seconds
Started	Feb 25 02:28:53 PM PST 24
Finished	Feb 25 02:29:06 PM PST 24
Peak memory	204176 kb
Host	smart-9e51d3bd-3371-4e0b-84f3-76b9cd869f8d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093934212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.4093934212
Directory	/workspace/29.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_same_source.3169911526
Short name	T689
Test name
Test status
Simulation time	348425057 ps
CPU time	19.26 seconds
Started	Feb 25 02:29:03 PM PST 24
Finished	Feb 25 02:29:23 PM PST 24
Peak memory	203528 kb
Host	smart-7ff07df2-e770-4e37-ac3a-581c134a1bce
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3169911526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3169911526
Directory	/workspace/29.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke.3801998387
Short name	T644
Test name
Test status
Simulation time	442334804 ps
CPU time	3.69 seconds
Started	Feb 25 02:28:49 PM PST 24
Finished	Feb 25 02:28:53 PM PST 24
Peak memory	203076 kb
Host	smart-98c72a4d-5aae-4b43-9894-e857172dd5ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3801998387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3801998387
Directory	/workspace/29.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1803316112
Short name	T48
Test name
Test status
Simulation time	8603230052 ps
CPU time	28.94 seconds
Started	Feb 25 02:28:58 PM PST 24
Finished	Feb 25 02:29:27 PM PST 24
Peak memory	203108 kb
Host	smart-0aba969c-adb4-4834-a84f-7ab3aa9f95b3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803316112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1803316112
Directory	/workspace/29.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.2496913536
Short name	T312
Test name
Test status
Simulation time	3626900167 ps
CPU time	32.92 seconds
Started	Feb 25 02:28:51 PM PST 24
Finished	Feb 25 02:29:24 PM PST 24
Peak memory	203120 kb
Host	smart-df8299a6-918d-4560-a5ba-6e5b7d6ddc70
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2496913536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2496913536
Directory	/workspace/29.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.695538818
Short name	T57
Test name
Test status
Simulation time	27793529 ps
CPU time	2.18 seconds
Started	Feb 25 02:28:45 PM PST 24
Finished	Feb 25 02:28:47 PM PST 24
Peak memory	203016 kb
Host	smart-5fcbcbe3-3528-4144-8a51-3dc0107c3912
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695538818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.695538818
Directory	/workspace/29.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all.3305517034
Short name	T87
Test name
Test status
Simulation time	16534139113 ps
CPU time	156.82 seconds
Started	Feb 25 02:29:05 PM PST 24
Finished	Feb 25 02:31:42 PM PST 24
Peak memory	206872 kb
Host	smart-885180b9-f7bb-4bbc-9b0f-a7a367c9ab3c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3305517034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3305517034
Directory	/workspace/29.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3503063480
Short name	T272
Test name
Test status
Simulation time	2743965909 ps
CPU time	61.47 seconds
Started	Feb 25 02:29:04 PM PST 24
Finished	Feb 25 02:30:05 PM PST 24
Peak memory	204944 kb
Host	smart-aebbacca-2763-4652-9f4f-31d7ffc25a05
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3503063480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3503063480
Directory	/workspace/29.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.825776719
Short name	T195
Test name
Test status
Simulation time	520165742 ps
CPU time	222.82 seconds
Started	Feb 25 02:28:52 PM PST 24
Finished	Feb 25 02:32:35 PM PST 24
Peak memory	208216 kb
Host	smart-708fe118-a0ff-4e53-84b4-4a85c786122b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=825776719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand _reset.825776719
Directory	/workspace/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3523817120
Short name	T319
Test name
Test status
Simulation time	360614609 ps
CPU time	114.54 seconds
Started	Feb 25 02:29:04 PM PST 24
Finished	Feb 25 02:30:59 PM PST 24
Peak memory	209428 kb
Host	smart-3990457e-7dfc-48e3-96fb-3e582421d0c0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3523817120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re set_error.3523817120
Directory	/workspace/29.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.3332697849
Short name	T381
Test name
Test status
Simulation time	252768382 ps
CPU time	18.44 seconds
Started	Feb 25 02:28:52 PM PST 24
Finished	Feb 25 02:29:10 PM PST 24
Peak memory	204280 kb
Host	smart-a7d3c746-45ed-4fbc-8f13-a60e6334fb08
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3332697849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3332697849
Directory	/workspace/29.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device.2239853086
Short name	T92
Test name
Test status
Simulation time	225805316 ps
CPU time	18.79 seconds
Started	Feb 25 02:26:26 PM PST 24
Finished	Feb 25 02:26:46 PM PST 24
Peak memory	211192 kb
Host	smart-edae9298-3079-4f09-b9a3-e2265631c3fd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2239853086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2239853086
Directory	/workspace/3.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3242813006
Short name	T846
Test name
Test status
Simulation time	74104540625 ps
CPU time	333.56 seconds
Started	Feb 25 02:26:27 PM PST 24
Finished	Feb 25 02:32:02 PM PST 24
Peak memory	205456 kb
Host	smart-0859e330-3646-41b0-8b45-27f75881619b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3242813006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.3242813006
Directory	/workspace/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3106513693
Short name	T276
Test name
Test status
Simulation time	198321547 ps
CPU time	3.92 seconds
Started	Feb 25 02:26:31 PM PST 24
Finished	Feb 25 02:26:35 PM PST 24
Peak memory	203168 kb
Host	smart-376728c4-3a97-4724-943d-30d3531b6d10
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3106513693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3106513693
Directory	/workspace/3.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_error_random.1288550532
Short name	T530
Test name
Test status
Simulation time	714563156 ps
CPU time	16.51 seconds
Started	Feb 25 02:26:30 PM PST 24
Finished	Feb 25 02:26:47 PM PST 24
Peak memory	203072 kb
Host	smart-a5354148-ebeb-4fd8-86e2-a9475c2bb1d8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1288550532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1288550532
Directory	/workspace/3.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random.1943816910
Short name	T871
Test name
Test status
Simulation time	1745833180 ps
CPU time	35.15 seconds
Started	Feb 25 02:26:27 PM PST 24
Finished	Feb 25 02:27:03 PM PST 24
Peak memory	204384 kb
Host	smart-c8598eb2-0d08-406a-8415-db3f3b98ec1f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1943816910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1943816910
Directory	/workspace/3.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2029583168
Short name	T61
Test name
Test status
Simulation time	25457370940 ps
CPU time	152.05 seconds
Started	Feb 25 02:26:28 PM PST 24
Finished	Feb 25 02:29:01 PM PST 24
Peak memory	211320 kb
Host	smart-ee964bdb-d4f3-44e6-bb89-8ac50d8c1f54
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029583168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2029583168
Directory	/workspace/3.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3512578249
Short name	T899
Test name
Test status
Simulation time	72943339377 ps
CPU time	244.36 seconds
Started	Feb 25 02:26:31 PM PST 24
Finished	Feb 25 02:30:35 PM PST 24
Peak memory	211312 kb
Host	smart-87a037fd-0264-499d-93c7-6aeb7527085c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3512578249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3512578249
Directory	/workspace/3.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.2659381499
Short name	T292
Test name
Test status
Simulation time	123950168 ps
CPU time	20.85 seconds
Started	Feb 25 02:26:30 PM PST 24
Finished	Feb 25 02:26:51 PM PST 24
Peak memory	211248 kb
Host	smart-7056a05d-0824-4925-81e9-45b2207c4e20
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659381499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2659381499
Directory	/workspace/3.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_same_source.2404879063
Short name	T481
Test name
Test status
Simulation time	4825244109 ps
CPU time	37.95 seconds
Started	Feb 25 02:26:28 PM PST 24
Finished	Feb 25 02:27:06 PM PST 24
Peak memory	203776 kb
Host	smart-32c32f5a-0002-47f8-b676-7835c1a974a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2404879063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2404879063
Directory	/workspace/3.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke.2243732486
Short name	T62
Test name
Test status
Simulation time	35419639 ps
CPU time	2.27 seconds
Started	Feb 25 02:26:24 PM PST 24
Finished	Feb 25 02:26:27 PM PST 24
Peak memory	203028 kb
Host	smart-863fea74-a7a8-4fc1-910b-0fcca3e6b9af
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2243732486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2243732486
Directory	/workspace/3.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.3459470501
Short name	T244
Test name
Test status
Simulation time	6125749939 ps
CPU time	31.16 seconds
Started	Feb 25 02:26:28 PM PST 24
Finished	Feb 25 02:27:00 PM PST 24
Peak memory	203128 kb
Host	smart-bcb20595-784d-4c1e-b848-ed5a71b5158e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459470501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3459470501
Directory	/workspace/3.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1712328735
Short name	T758
Test name
Test status
Simulation time	4215357097 ps
CPU time	23.46 seconds
Started	Feb 25 02:26:27 PM PST 24
Finished	Feb 25 02:26:50 PM PST 24
Peak memory	203092 kb
Host	smart-ee7c7c15-2611-4e2e-95a8-82806aafcff8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1712328735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1712328735
Directory	/workspace/3.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2325269247
Short name	T637
Test name
Test status
Simulation time	42539418 ps
CPU time	2.61 seconds
Started	Feb 25 02:26:28 PM PST 24
Finished	Feb 25 02:26:31 PM PST 24
Peak memory	203048 kb
Host	smart-dce7e9a3-8f3f-4841-9293-dbecbe83fb86
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325269247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2325269247
Directory	/workspace/3.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all.2300469134
Short name	T629
Test name
Test status
Simulation time	10728467343 ps
CPU time	144.08 seconds
Started	Feb 25 02:26:30 PM PST 24
Finished	Feb 25 02:28:55 PM PST 24
Peak memory	205808 kb
Host	smart-05da4253-7eda-47cd-b043-b0f2ceb92fa1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2300469134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2300469134
Directory	/workspace/3.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.4170284889
Short name	T793
Test name
Test status
Simulation time	7021513824 ps
CPU time	172.83 seconds
Started	Feb 25 02:26:36 PM PST 24
Finished	Feb 25 02:29:30 PM PST 24
Peak memory	208488 kb
Host	smart-6b3fa2e1-1816-4e7f-82ef-da454709691c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4170284889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4170284889
Directory	/workspace/3.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.544922506
Short name	T140
Test name
Test status
Simulation time	1201477298 ps
CPU time	134.27 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:28:43 PM PST 24
Peak memory	207528 kb
Host	smart-63df25e3-ec87-48e1-a1b1-3bf89514ab5a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=544922506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_ reset.544922506
Directory	/workspace/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3963932351
Short name	T695
Test name
Test status
Simulation time	331942151 ps
CPU time	71.44 seconds
Started	Feb 25 02:26:32 PM PST 24
Finished	Feb 25 02:27:44 PM PST 24
Peak memory	207876 kb
Host	smart-359cdfb7-98e4-4924-abc6-c2b21e2ff28f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3963932351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res et_error.3963932351
Directory	/workspace/3.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.1769763975
Short name	T869
Test name
Test status
Simulation time	133043457 ps
CPU time	24.55 seconds
Started	Feb 25 02:26:38 PM PST 24
Finished	Feb 25 02:27:02 PM PST 24
Peak memory	204760 kb
Host	smart-793a76ea-9aa9-4a27-b80c-c4af4fa120a9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1769763975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1769763975
Directory	/workspace/3.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1235680983
Short name	T849
Test name
Test status
Simulation time	1150717080 ps
CPU time	18.69 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:29:20 PM PST 24
Peak memory	204072 kb
Host	smart-37e2cc5f-db51-45d3-ae9e-21ab5a508d26
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1235680983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1235680983
Directory	/workspace/30.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3318215786
Short name	T667
Test name
Test status
Simulation time	52992736822 ps
CPU time	246.5 seconds
Started	Feb 25 02:29:04 PM PST 24
Finished	Feb 25 02:33:10 PM PST 24
Peak memory	211308 kb
Host	smart-9c1275eb-0189-4cae-b085-21c986f1bacc
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3318215786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl ow_rsp.3318215786
Directory	/workspace/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2025355218
Short name	T238
Test name
Test status
Simulation time	281097378 ps
CPU time	11.52 seconds
Started	Feb 25 02:29:00 PM PST 24
Finished	Feb 25 02:29:11 PM PST 24
Peak memory	203076 kb
Host	smart-71816014-fd95-4153-b4b7-807409215a57
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2025355218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2025355218
Directory	/workspace/30.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_error_random.86854795
Short name	T374
Test name
Test status
Simulation time	116988331 ps
CPU time	17.97 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:29:20 PM PST 24
Peak memory	202956 kb
Host	smart-92510ab6-27f4-4790-9d69-5ac9788bb042
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=86854795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.86854795
Directory	/workspace/30.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random.399965979
Short name	T76
Test name
Test status
Simulation time	1945419668 ps
CPU time	14.78 seconds
Started	Feb 25 02:29:06 PM PST 24
Finished	Feb 25 02:29:21 PM PST 24
Peak memory	204172 kb
Host	smart-d37204c4-5486-4e91-929c-f45ba22b6442
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=399965979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.399965979
Directory	/workspace/30.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.1238088266
Short name	T166
Test name
Test status
Simulation time	77026006707 ps
CPU time	167.69 seconds
Started	Feb 25 02:29:00 PM PST 24
Finished	Feb 25 02:31:48 PM PST 24
Peak memory	204492 kb
Host	smart-c5d59316-7fcc-44b1-903c-7726c2ec5b5f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238088266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1238088266
Directory	/workspace/30.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1860174114
Short name	T159
Test name
Test status
Simulation time	13501496457 ps
CPU time	130.6 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:31:13 PM PST 24
Peak memory	204444 kb
Host	smart-293b0f90-c6c8-4ae4-b800-27c5b8b615f2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1860174114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1860174114
Directory	/workspace/30.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.828478171
Short name	T430
Test name
Test status
Simulation time	319582395 ps
CPU time	17.59 seconds
Started	Feb 25 02:29:01 PM PST 24
Finished	Feb 25 02:29:19 PM PST 24
Peak memory	204184 kb
Host	smart-b8a373f2-2c3b-40f1-b5fc-b7b3e9d7624a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828478171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.828478171
Directory	/workspace/30.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_same_source.2639611834
Short name	T709
Test name
Test status
Simulation time	1610362996 ps
CPU time	14.39 seconds
Started	Feb 25 02:29:03 PM PST 24
Finished	Feb 25 02:29:17 PM PST 24
Peak memory	203376 kb
Host	smart-fe3e8758-f214-4f6e-9cac-721ea4983f53
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639611834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2639611834
Directory	/workspace/30.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke.1823579623
Short name	T235
Test name
Test status
Simulation time	139106634 ps
CPU time	3.41 seconds
Started	Feb 25 02:28:59 PM PST 24
Finished	Feb 25 02:29:03 PM PST 24
Peak memory	203084 kb
Host	smart-6d9e46ff-d014-4e0c-bc44-07d204b0a502
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1823579623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1823579623
Directory	/workspace/30.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1630070206
Short name	T519
Test name
Test status
Simulation time	8815707131 ps
CPU time	28.41 seconds
Started	Feb 25 02:29:04 PM PST 24
Finished	Feb 25 02:29:33 PM PST 24
Peak memory	203124 kb
Host	smart-b741e3b0-7695-4261-99fe-6ad48fdd4e4e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630070206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1630070206
Directory	/workspace/30.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3212332471
Short name	T91
Test name
Test status
Simulation time	3607701164 ps
CPU time	29.1 seconds
Started	Feb 25 02:29:04 PM PST 24
Finished	Feb 25 02:29:33 PM PST 24
Peak memory	203120 kb
Host	smart-acc65fa7-0247-4cc0-a6c1-62c227c116d3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3212332471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3212332471
Directory	/workspace/30.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3113180763
Short name	T698
Test name
Test status
Simulation time	46045525 ps
CPU time	2.37 seconds
Started	Feb 25 02:29:04 PM PST 24
Finished	Feb 25 02:29:07 PM PST 24
Peak memory	203072 kb
Host	smart-e51a2d08-1477-436a-8c44-d9f72404ab05
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113180763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3113180763
Directory	/workspace/30.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all.105144656
Short name	T171
Test name
Test status
Simulation time	2463767743 ps
CPU time	21.55 seconds
Started	Feb 25 02:29:06 PM PST 24
Finished	Feb 25 02:29:28 PM PST 24
Peak memory	205336 kb
Host	smart-739eebee-943f-4569-8237-66b3019c1e73
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=105144656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.105144656
Directory	/workspace/30.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3766487006
Short name	T280
Test name
Test status
Simulation time	3969710117 ps
CPU time	152.76 seconds
Started	Feb 25 02:29:03 PM PST 24
Finished	Feb 25 02:31:36 PM PST 24
Peak memory	205888 kb
Host	smart-e20fe616-c904-4e0e-96f4-510325fe6f3d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3766487006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3766487006
Directory	/workspace/30.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1289422513
Short name	T178
Test name
Test status
Simulation time	509044107 ps
CPU time	212.27 seconds
Started	Feb 25 02:29:04 PM PST 24
Finished	Feb 25 02:32:36 PM PST 24
Peak memory	208164 kb
Host	smart-81b5b0a1-505e-435f-8181-982995a06208
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1289422513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.1289422513
Directory	/workspace/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1695260525
Short name	T122
Test name
Test status
Simulation time	305942480 ps
CPU time	90.28 seconds
Started	Feb 25 02:29:01 PM PST 24
Finished	Feb 25 02:30:32 PM PST 24
Peak memory	208820 kb
Host	smart-51725b20-9c09-4628-960c-e911c5f01a24
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1695260525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re set_error.1695260525
Directory	/workspace/30.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.823446896
Short name	T728
Test name
Test status
Simulation time	42822422 ps
CPU time	6.02 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:29:08 PM PST 24
Peak memory	211204 kb
Host	smart-dcc73c16-17b5-40d8-8be8-a5243b14f7a8
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=823446896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.823446896
Directory	/workspace/30.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device.521700242
Short name	T712
Test name
Test status
Simulation time	366388647 ps
CPU time	44.9 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:29:47 PM PST 24
Peak memory	204788 kb
Host	smart-54130900-b1ab-4dc7-b213-f1617d953e9a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=521700242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.521700242
Directory	/workspace/31.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.848611443
Short name	T102
Test name
Test status
Simulation time	60768901974 ps
CPU time	438.78 seconds
Started	Feb 25 02:29:01 PM PST 24
Finished	Feb 25 02:36:20 PM PST 24
Peak memory	211288 kb
Host	smart-53b834d2-cd57-43a2-ae78-6dcb9232994a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=848611443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo w_rsp.848611443
Directory	/workspace/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.4240147680
Short name	T295
Test name
Test status
Simulation time	346488656 ps
CPU time	13.62 seconds
Started	Feb 25 02:29:09 PM PST 24
Finished	Feb 25 02:29:23 PM PST 24
Peak memory	203068 kb
Host	smart-7f7517ad-d0c8-4233-8e0f-5f927d210917
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4240147680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.4240147680
Directory	/workspace/31.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_error_random.4081347773
Short name	T335
Test name
Test status
Simulation time	174774117 ps
CPU time	6.73 seconds
Started	Feb 25 02:28:57 PM PST 24
Finished	Feb 25 02:29:03 PM PST 24
Peak memory	203064 kb
Host	smart-29ec984d-1017-4ff4-93aa-ed33a17345c7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4081347773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.4081347773
Directory	/workspace/31.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random.760824436
Short name	T174
Test name
Test status
Simulation time	1023028953 ps
CPU time	41.6 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:29:43 PM PST 24
Peak memory	204500 kb
Host	smart-7f530aa6-f02b-4fbc-8cd7-b427443d48a6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=760824436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.760824436
Directory	/workspace/31.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.2274563483
Short name	T863
Test name
Test status
Simulation time	16990442775 ps
CPU time	34.48 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:29:37 PM PST 24
Peak memory	204076 kb
Host	smart-c6ad2690-73e2-4254-a409-73be9f42923f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274563483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2274563483
Directory	/workspace/31.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.886519978
Short name	T321
Test name
Test status
Simulation time	21770278376 ps
CPU time	84.29 seconds
Started	Feb 25 02:29:08 PM PST 24
Finished	Feb 25 02:30:33 PM PST 24
Peak memory	211288 kb
Host	smart-14f23c86-caae-479b-a8a6-aa5039d704d3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=886519978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.886519978
Directory	/workspace/31.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.513280547
Short name	T622
Test name
Test status
Simulation time	31104724 ps
CPU time	5.29 seconds
Started	Feb 25 02:29:00 PM PST 24
Finished	Feb 25 02:29:06 PM PST 24
Peak memory	203068 kb
Host	smart-f964738d-9812-4378-aa44-905507d9776c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513280547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.513280547
Directory	/workspace/31.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_same_source.1610001448
Short name	T44
Test name
Test status
Simulation time	707835299 ps
CPU time	19 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:29:21 PM PST 24
Peak memory	202976 kb
Host	smart-15eeb141-db67-4b81-afd0-7a7f70abecff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1610001448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1610001448
Directory	/workspace/31.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke.610112226
Short name	T627
Test name
Test status
Simulation time	91379402 ps
CPU time	2.75 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:29:05 PM PST 24
Peak memory	203028 kb
Host	smart-ccfe0ae3-fbdd-4727-abda-d3675160f2f2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=610112226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.610112226
Directory	/workspace/31.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3395980450
Short name	T602
Test name
Test status
Simulation time	15137212690 ps
CPU time	33.59 seconds
Started	Feb 25 02:29:01 PM PST 24
Finished	Feb 25 02:29:34 PM PST 24
Peak memory	203056 kb
Host	smart-0a4f183f-f2c6-45e9-9d32-a8a380a7c9ab
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395980450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3395980450
Directory	/workspace/31.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.395984094
Short name	T158
Test name
Test status
Simulation time	13244841019 ps
CPU time	34.12 seconds
Started	Feb 25 02:29:01 PM PST 24
Finished	Feb 25 02:29:35 PM PST 24
Peak memory	202992 kb
Host	smart-7c2a1e57-550c-4371-ba08-cbde18d388f2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=395984094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.395984094
Directory	/workspace/31.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2829425796
Short name	T877
Test name
Test status
Simulation time	34102188 ps
CPU time	2.76 seconds
Started	Feb 25 02:29:01 PM PST 24
Finished	Feb 25 02:29:04 PM PST 24
Peak memory	203048 kb
Host	smart-f594d8ac-cb58-428c-b22f-2d125845cfac
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829425796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2829425796
Directory	/workspace/31.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all.2660294908
Short name	T88
Test name
Test status
Simulation time	4015194781 ps
CPU time	97.91 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:30:40 PM PST 24
Peak memory	208228 kb
Host	smart-b54398f5-779b-438e-a9ae-c884fea83792
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2660294908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2660294908
Directory	/workspace/31.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.578285016
Short name	T738
Test name
Test status
Simulation time	11395676384 ps
CPU time	205.43 seconds
Started	Feb 25 02:29:01 PM PST 24
Finished	Feb 25 02:32:27 PM PST 24
Peak memory	206640 kb
Host	smart-27e0227f-b5f5-44f1-bb0c-9ed80bb29418
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=578285016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.578285016
Directory	/workspace/31.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1319896007
Short name	T583
Test name
Test status
Simulation time	98572275 ps
CPU time	31.64 seconds
Started	Feb 25 02:29:02 PM PST 24
Finished	Feb 25 02:29:34 PM PST 24
Peak memory	206092 kb
Host	smart-5c681afa-366b-4c38-99b3-cbaca3f25980
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1319896007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.1319896007
Directory	/workspace/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1262487478
Short name	T398
Test name
Test status
Simulation time	7905368683 ps
CPU time	302.4 seconds
Started	Feb 25 02:29:13 PM PST 24
Finished	Feb 25 02:34:15 PM PST 24
Peak memory	219496 kb
Host	smart-938eef2a-7033-4df3-b931-1bf590699abd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1262487478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.1262487478
Directory	/workspace/31.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1221086656
Short name	T850
Test name
Test status
Simulation time	114797150 ps
CPU time	2.7 seconds
Started	Feb 25 02:29:03 PM PST 24
Finished	Feb 25 02:29:05 PM PST 24
Peak memory	203052 kb
Host	smart-cfd08e2f-f857-4653-91a9-4892bfa44a09
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1221086656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1221086656
Directory	/workspace/31.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device.4282707174
Short name	T362
Test name
Test status
Simulation time	1588162710 ps
CPU time	24.82 seconds
Started	Feb 25 02:29:17 PM PST 24
Finished	Feb 25 02:29:42 PM PST 24
Peak memory	211180 kb
Host	smart-272b8dfd-3893-4e91-bb33-cbc8a9366d97
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4282707174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.4282707174
Directory	/workspace/32.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1439776039
Short name	T589
Test name
Test status
Simulation time	99141224963 ps
CPU time	466.09 seconds
Started	Feb 25 02:29:14 PM PST 24
Finished	Feb 25 02:37:01 PM PST 24
Peak memory	211304 kb
Host	smart-75c85a57-02cb-42a3-bd22-8b41c4bcbaae
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1439776039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.1439776039
Directory	/workspace/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3190207828
Short name	T448
Test name
Test status
Simulation time	428470467 ps
CPU time	14.13 seconds
Started	Feb 25 02:29:14 PM PST 24
Finished	Feb 25 02:29:29 PM PST 24
Peak memory	203040 kb
Host	smart-9f8be026-1e7c-4a16-ba8b-08fc9f9db4e7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3190207828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3190207828
Directory	/workspace/32.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_error_random.1895108447
Short name	T117
Test name
Test status
Simulation time	820201695 ps
CPU time	24.93 seconds
Started	Feb 25 02:29:12 PM PST 24
Finished	Feb 25 02:29:37 PM PST 24
Peak memory	203056 kb
Host	smart-589a048b-35b3-4f00-9970-df01c30291cf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1895108447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1895108447
Directory	/workspace/32.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random.1009012400
Short name	T236
Test name
Test status
Simulation time	1195376897 ps
CPU time	23.81 seconds
Started	Feb 25 02:29:15 PM PST 24
Finished	Feb 25 02:29:40 PM PST 24
Peak memory	211232 kb
Host	smart-49991e05-94fb-4cf1-b2c0-cf30dffc9b5a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1009012400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.1009012400
Directory	/workspace/32.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.451399338
Short name	T522
Test name
Test status
Simulation time	21765147715 ps
CPU time	106.33 seconds
Started	Feb 25 02:29:15 PM PST 24
Finished	Feb 25 02:31:02 PM PST 24
Peak memory	211316 kb
Host	smart-a86cf541-c976-4772-9e13-f9a541598c70
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=451399338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.451399338
Directory	/workspace/32.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1062619635
Short name	T49
Test name
Test status
Simulation time	13698526312 ps
CPU time	62.17 seconds
Started	Feb 25 02:29:16 PM PST 24
Finished	Feb 25 02:30:19 PM PST 24
Peak memory	211300 kb
Host	smart-928e8621-360d-46da-a826-86afdb931e9e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1062619635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1062619635
Directory	/workspace/32.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.1420890456
Short name	T297
Test name
Test status
Simulation time	457566409 ps
CPU time	24.44 seconds
Started	Feb 25 02:29:16 PM PST 24
Finished	Feb 25 02:29:40 PM PST 24
Peak memory	211252 kb
Host	smart-d4892d8a-87a9-4a6d-88df-3627a580d58a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420890456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.1420890456
Directory	/workspace/32.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_same_source.2114877004
Short name	T114
Test name
Test status
Simulation time	4260762896 ps
CPU time	31.79 seconds
Started	Feb 25 02:29:18 PM PST 24
Finished	Feb 25 02:29:50 PM PST 24
Peak memory	203108 kb
Host	smart-9e3501fe-4d79-4b8f-b71a-60bb3a8d796a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2114877004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2114877004
Directory	/workspace/32.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke.3644255125
Short name	T806
Test name
Test status
Simulation time	27466605 ps
CPU time	2.81 seconds
Started	Feb 25 02:29:15 PM PST 24
Finished	Feb 25 02:29:19 PM PST 24
Peak memory	203064 kb
Host	smart-f640142f-3618-4db9-9b54-39a3775e8164
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3644255125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3644255125
Directory	/workspace/32.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.702696731
Short name	T199
Test name
Test status
Simulation time	13413841788 ps
CPU time	34.35 seconds
Started	Feb 25 02:29:15 PM PST 24
Finished	Feb 25 02:29:50 PM PST 24
Peak memory	203124 kb
Host	smart-75bb9100-98e2-4a5e-b412-0d5a1a6a090f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=702696731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.702696731
Directory	/workspace/32.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.168169439
Short name	T632
Test name
Test status
Simulation time	6138858675 ps
CPU time	33.55 seconds
Started	Feb 25 02:29:09 PM PST 24
Finished	Feb 25 02:29:43 PM PST 24
Peak memory	203120 kb
Host	smart-1b4acfa4-d020-4737-9643-4825d3548112
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=168169439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.168169439
Directory	/workspace/32.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.3202008360
Short name	T719
Test name
Test status
Simulation time	35294830 ps
CPU time	2.13 seconds
Started	Feb 25 02:29:14 PM PST 24
Finished	Feb 25 02:29:17 PM PST 24
Peak memory	203060 kb
Host	smart-b7181509-977f-4e59-bb3c-5e859a8fca35
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202008360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.3202008360
Directory	/workspace/32.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all.2651463684
Short name	T587
Test name
Test status
Simulation time	7571001332 ps
CPU time	282.18 seconds
Started	Feb 25 02:29:17 PM PST 24
Finished	Feb 25 02:33:59 PM PST 24
Peak memory	206860 kb
Host	smart-5e03b396-8210-436d-8d1e-29ff590ca48f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2651463684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2651463684
Directory	/workspace/32.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1697025356
Short name	T535
Test name
Test status
Simulation time	512393177 ps
CPU time	35.6 seconds
Started	Feb 25 02:29:18 PM PST 24
Finished	Feb 25 02:29:54 PM PST 24
Peak memory	204248 kb
Host	smart-c6d9b8c3-0d9a-48ae-b094-4a299dc3f2f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1697025356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1697025356
Directory	/workspace/32.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3338382535
Short name	T884
Test name
Test status
Simulation time	368216424 ps
CPU time	53.99 seconds
Started	Feb 25 02:29:17 PM PST 24
Finished	Feb 25 02:30:11 PM PST 24
Peak memory	207216 kb
Host	smart-6948324e-5bbd-4eea-8d47-f82e9e8f38a6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3338382535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.3338382535
Directory	/workspace/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1538844010
Short name	T268
Test name
Test status
Simulation time	111977377 ps
CPU time	26.33 seconds
Started	Feb 25 02:29:11 PM PST 24
Finished	Feb 25 02:29:37 PM PST 24
Peak memory	205500 kb
Host	smart-213ae58d-9808-4e55-ae7b-ac4fa212fb85
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1538844010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.1538844010
Directory	/workspace/32.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.3994163246
Short name	T445
Test name
Test status
Simulation time	784065532 ps
CPU time	16.99 seconds
Started	Feb 25 02:29:15 PM PST 24
Finished	Feb 25 02:29:32 PM PST 24
Peak memory	204696 kb
Host	smart-cb481158-7d40-45f9-b75d-2177b39d3f0b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3994163246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3994163246
Directory	/workspace/32.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_access_same_device.883576142
Short name	T852
Test name
Test status
Simulation time	75275608 ps
CPU time	10.1 seconds
Started	Feb 25 02:29:22 PM PST 24
Finished	Feb 25 02:29:33 PM PST 24
Peak memory	204860 kb
Host	smart-0388f6e4-834f-4b6e-b401-20c212533e77
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=883576142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.883576142
Directory	/workspace/33.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1854424074
Short name	T577
Test name
Test status
Simulation time	95315913 ps
CPU time	14.68 seconds
Started	Feb 25 02:29:34 PM PST 24
Finished	Feb 25 02:29:49 PM PST 24
Peak memory	203052 kb
Host	smart-714e3801-ebb0-4a6e-b331-6c98630e7b8b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1854424074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1854424074
Directory	/workspace/33.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_error_random.3906237860
Short name	T596
Test name
Test status
Simulation time	225607739 ps
CPU time	18.93 seconds
Started	Feb 25 02:29:35 PM PST 24
Finished	Feb 25 02:29:55 PM PST 24
Peak memory	202988 kb
Host	smart-6bac80d6-54c6-449e-bdbc-23c81321ee1c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3906237860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3906237860
Directory	/workspace/33.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random.2786676818
Short name	T402
Test name
Test status
Simulation time	1432903057 ps
CPU time	40.75 seconds
Started	Feb 25 02:29:34 PM PST 24
Finished	Feb 25 02:30:16 PM PST 24
Peak memory	211188 kb
Host	smart-ee4d20f9-6814-4cc9-be63-d42bc3431df4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2786676818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2786676818
Directory	/workspace/33.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.622552040
Short name	T451
Test name
Test status
Simulation time	15086074756 ps
CPU time	44.03 seconds
Started	Feb 25 02:29:33 PM PST 24
Finished	Feb 25 02:30:18 PM PST 24
Peak memory	211280 kb
Host	smart-1da6b033-6c53-4fb8-b6b3-0e8069e61ecd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=622552040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.622552040
Directory	/workspace/33.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.2437141408
Short name	T289
Test name
Test status
Simulation time	5394301543 ps
CPU time	44.53 seconds
Started	Feb 25 02:29:24 PM PST 24
Finished	Feb 25 02:30:09 PM PST 24
Peak memory	211316 kb
Host	smart-651c6f28-b144-4292-b3ab-3ee424221423
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2437141408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2437141408
Directory	/workspace/33.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.2053340422
Short name	T652
Test name
Test status
Simulation time	39256725 ps
CPU time	4.82 seconds
Started	Feb 25 02:29:36 PM PST 24
Finished	Feb 25 02:29:41 PM PST 24
Peak memory	203088 kb
Host	smart-5d99c91c-65fc-4e64-9aa8-10b7226ec922
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053340422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.2053340422
Directory	/workspace/33.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_same_source.581636636
Short name	T271
Test name
Test status
Simulation time	121481126 ps
CPU time	10.56 seconds
Started	Feb 25 02:29:35 PM PST 24
Finished	Feb 25 02:29:46 PM PST 24
Peak memory	203060 kb
Host	smart-412b050e-6677-46ce-9a54-bfcb86844c1e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=581636636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.581636636
Directory	/workspace/33.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke.4016463348
Short name	T210
Test name
Test status
Simulation time	26568276 ps
CPU time	2.21 seconds
Started	Feb 25 02:29:16 PM PST 24
Finished	Feb 25 02:29:19 PM PST 24
Peak memory	202972 kb
Host	smart-77c2683c-3b67-463a-af08-8c1968d63fda
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4016463348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.4016463348
Directory	/workspace/33.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2379642008
Short name	T185
Test name
Test status
Simulation time	7833266528 ps
CPU time	34.38 seconds
Started	Feb 25 02:29:35 PM PST 24
Finished	Feb 25 02:30:10 PM PST 24
Peak memory	203060 kb
Host	smart-c2a44ae7-575a-4b1e-9582-a4fd67b28349
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379642008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2379642008
Directory	/workspace/33.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.4098800275
Short name	T886
Test name
Test status
Simulation time	3791226558 ps
CPU time	29.36 seconds
Started	Feb 25 02:29:33 PM PST 24
Finished	Feb 25 02:30:02 PM PST 24
Peak memory	203128 kb
Host	smart-8a0833d4-0ea1-440a-af2e-7df6a54c81f8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4098800275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.4098800275
Directory	/workspace/33.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1493091035
Short name	T261
Test name
Test status
Simulation time	32270561 ps
CPU time	2.52 seconds
Started	Feb 25 02:29:23 PM PST 24
Finished	Feb 25 02:29:26 PM PST 24
Peak memory	203056 kb
Host	smart-f3eabc96-9cfd-48b2-9c3d-75bd0214f750
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493091035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1493091035
Directory	/workspace/33.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all.2192558921
Short name	T54
Test name
Test status
Simulation time	1987592553 ps
CPU time	43.65 seconds
Started	Feb 25 02:29:40 PM PST 24
Finished	Feb 25 02:30:24 PM PST 24
Peak memory	204344 kb
Host	smart-c6d30cb4-49bb-4678-a681-0ffa44467251
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2192558921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2192558921
Directory	/workspace/33.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1147199192
Short name	T382
Test name
Test status
Simulation time	1145821348 ps
CPU time	78.62 seconds
Started	Feb 25 02:29:33 PM PST 24
Finished	Feb 25 02:30:52 PM PST 24
Peak memory	205912 kb
Host	smart-81a45ca4-5bbc-4da5-a93e-10c4e6554519
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1147199192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1147199192
Directory	/workspace/33.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2248011266
Short name	T611
Test name
Test status
Simulation time	1048203385 ps
CPU time	299.19 seconds
Started	Feb 25 02:29:37 PM PST 24
Finished	Feb 25 02:34:37 PM PST 24
Peak memory	210556 kb
Host	smart-b12ba77f-54dd-4962-87a6-5608b99e93f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2248011266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.2248011266
Directory	/workspace/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.3728510108
Short name	T699
Test name
Test status
Simulation time	195955636 ps
CPU time	21.78 seconds
Started	Feb 25 02:29:34 PM PST 24
Finished	Feb 25 02:29:57 PM PST 24
Peak memory	205240 kb
Host	smart-953cbd74-0b10-49ad-a3ec-a17886547333
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3728510108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.3728510108
Directory	/workspace/33.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.3215231337
Short name	T545
Test name
Test status
Simulation time	554602658 ps
CPU time	26.89 seconds
Started	Feb 25 02:29:25 PM PST 24
Finished	Feb 25 02:29:52 PM PST 24
Peak memory	211232 kb
Host	smart-6bac6ec7-a37b-40f0-8b04-8ecc91e2d1c9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3215231337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3215231337
Directory	/workspace/33.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device.3180727109
Short name	T647
Test name
Test status
Simulation time	562019036 ps
CPU time	21.62 seconds
Started	Feb 25 02:29:23 PM PST 24
Finished	Feb 25 02:29:46 PM PST 24
Peak memory	204148 kb
Host	smart-c88332f2-5649-4155-b98a-ad9818c34bcb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3180727109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3180727109
Directory	/workspace/34.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.1397911719
Short name	T562
Test name
Test status
Simulation time	35670904298 ps
CPU time	222.24 seconds
Started	Feb 25 02:29:35 PM PST 24
Finished	Feb 25 02:33:18 PM PST 24
Peak memory	211312 kb
Host	smart-70b0884f-583b-4263-a09c-668bdf6bfc28
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1397911719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.1397911719
Directory	/workspace/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2793718132
Short name	T484
Test name
Test status
Simulation time	74489705 ps
CPU time	4.15 seconds
Started	Feb 25 02:29:38 PM PST 24
Finished	Feb 25 02:29:42 PM PST 24
Peak memory	203088 kb
Host	smart-8ce37c67-1eb3-4d37-ace8-93ad7fdad476
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2793718132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2793718132
Directory	/workspace/34.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_error_random.2462097821
Short name	T393
Test name
Test status
Simulation time	91697426 ps
CPU time	4.3 seconds
Started	Feb 25 02:29:36 PM PST 24
Finished	Feb 25 02:29:41 PM PST 24
Peak memory	203068 kb
Host	smart-4a3a76f1-941b-448a-b950-f1d046129c16
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2462097821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2462097821
Directory	/workspace/34.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.149113295
Short name	T153
Test name
Test status
Simulation time	57224729489 ps
CPU time	204.29 seconds
Started	Feb 25 02:29:37 PM PST 24
Finished	Feb 25 02:33:02 PM PST 24
Peak memory	211248 kb
Host	smart-e336f31e-b5e4-4c60-9aa1-2bce81e31cf6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=149113295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.149113295
Directory	/workspace/34.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.3552411438
Short name	T472
Test name
Test status
Simulation time	25219239691 ps
CPU time	72.9 seconds
Started	Feb 25 02:29:23 PM PST 24
Finished	Feb 25 02:30:37 PM PST 24
Peak memory	211284 kb
Host	smart-5c236380-68b8-4924-828b-0fd8a9f91bbf
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3552411438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3552411438
Directory	/workspace/34.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.2663724832
Short name	T187
Test name
Test status
Simulation time	126127087 ps
CPU time	15.09 seconds
Started	Feb 25 02:29:35 PM PST 24
Finished	Feb 25 02:29:51 PM PST 24
Peak memory	211284 kb
Host	smart-3bedd206-6ed8-4ce6-97a3-480ce098e500
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663724832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.2663724832
Directory	/workspace/34.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_same_source.4013691806
Short name	T252
Test name
Test status
Simulation time	357313983 ps
CPU time	10.5 seconds
Started	Feb 25 02:29:34 PM PST 24
Finished	Feb 25 02:29:46 PM PST 24
Peak memory	203380 kb
Host	smart-42a60104-4c77-4f17-839c-a66c1b6f1cab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4013691806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4013691806
Directory	/workspace/34.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke.2626958634
Short name	T780
Test name
Test status
Simulation time	299298493 ps
CPU time	3.92 seconds
Started	Feb 25 02:29:37 PM PST 24
Finished	Feb 25 02:29:42 PM PST 24
Peak memory	203052 kb
Host	smart-6c3bd40f-eacb-42dd-b3f6-c97230ecfee9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2626958634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2626958634
Directory	/workspace/34.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1109665089
Short name	T46
Test name
Test status
Simulation time	5545248982 ps
CPU time	22.21 seconds
Started	Feb 25 02:29:35 PM PST 24
Finished	Feb 25 02:29:58 PM PST 24
Peak memory	202996 kb
Host	smart-998f3c9c-0c16-4a36-b3bf-2cfe6dc5de23
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109665089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1109665089
Directory	/workspace/34.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.3753072002
Short name	T229
Test name
Test status
Simulation time	4866324806 ps
CPU time	22.86 seconds
Started	Feb 25 02:29:23 PM PST 24
Finished	Feb 25 02:29:47 PM PST 24
Peak memory	203116 kb
Host	smart-24093b0f-b1fa-48b8-9dcc-afb58599da2e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3753072002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3753072002
Directory	/workspace/34.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.949569662
Short name	T645
Test name
Test status
Simulation time	37988235 ps
CPU time	2.48 seconds
Started	Feb 25 02:29:36 PM PST 24
Finished	Feb 25 02:29:38 PM PST 24
Peak memory	202988 kb
Host	smart-6f283818-c15b-47e8-9a9f-ac484513f64d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949569662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.949569662
Directory	/workspace/34.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all.750624733
Short name	T148
Test name
Test status
Simulation time	7000439800 ps
CPU time	146.63 seconds
Started	Feb 25 02:29:34 PM PST 24
Finished	Feb 25 02:32:02 PM PST 24
Peak memory	207288 kb
Host	smart-9a5af644-032c-4d71-95a5-671be623e8f6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=750624733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.750624733
Directory	/workspace/34.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.952691432
Short name	T358
Test name
Test status
Simulation time	184540869 ps
CPU time	26.76 seconds
Started	Feb 25 02:29:34 PM PST 24
Finished	Feb 25 02:30:02 PM PST 24
Peak memory	204400 kb
Host	smart-7fe310e5-d813-437d-9c48-5685dafc16ea
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=952691432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.952691432
Directory	/workspace/34.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.4082515695
Short name	T136
Test name
Test status
Simulation time	8903711776 ps
CPU time	349.32 seconds
Started	Feb 25 02:29:38 PM PST 24
Finished	Feb 25 02:35:27 PM PST 24
Peak memory	209136 kb
Host	smart-6f4feef8-daac-43f9-96e0-840941b30fff
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4082515695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.4082515695
Directory	/workspace/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.1289599189
Short name	T442
Test name
Test status
Simulation time	233484703 ps
CPU time	52.16 seconds
Started	Feb 25 02:29:40 PM PST 24
Finished	Feb 25 02:30:32 PM PST 24
Peak memory	207364 kb
Host	smart-885e1a16-d525-414c-a07d-b091b4cfb503
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1289599189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.1289599189
Directory	/workspace/34.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.2949090149
Short name	T608
Test name
Test status
Simulation time	1593220475 ps
CPU time	18.84 seconds
Started	Feb 25 02:29:34 PM PST 24
Finished	Feb 25 02:29:55 PM PST 24
Peak memory	204336 kb
Host	smart-95336740-2e68-4bd4-91af-105a326614ec
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2949090149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2949090149
Directory	/workspace/34.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device.3950291112
Short name	T460
Test name
Test status
Simulation time	447958753 ps
CPU time	33.95 seconds
Started	Feb 25 02:29:34 PM PST 24
Finished	Feb 25 02:30:09 PM PST 24
Peak memory	203740 kb
Host	smart-e9f70e95-e6ed-4d46-b7ab-194bafbcbf3f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3950291112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3950291112
Directory	/workspace/35.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3284161141
Short name	T887
Test name
Test status
Simulation time	153814719535 ps
CPU time	464.96 seconds
Started	Feb 25 02:29:34 PM PST 24
Finished	Feb 25 02:37:19 PM PST 24
Peak memory	206348 kb
Host	smart-caa90753-4a11-4754-b064-121b683a9bde
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3284161141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.3284161141
Directory	/workspace/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.178872788
Short name	T270
Test name
Test status
Simulation time	15693571 ps
CPU time	1.6 seconds
Started	Feb 25 02:29:36 PM PST 24
Finished	Feb 25 02:29:38 PM PST 24
Peak memory	203052 kb
Host	smart-32a02a8f-c348-4233-b60f-79fa4dff9ea2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=178872788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.178872788
Directory	/workspace/35.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_error_random.271901803
Short name	T396
Test name
Test status
Simulation time	62287880 ps
CPU time	6.86 seconds
Started	Feb 25 02:29:42 PM PST 24
Finished	Feb 25 02:29:49 PM PST 24
Peak memory	203048 kb
Host	smart-0664cadf-da30-433e-9158-d8a6b286ad48
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=271901803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.271901803
Directory	/workspace/35.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random.2605891896
Short name	T526
Test name
Test status
Simulation time	893828367 ps
CPU time	25.82 seconds
Started	Feb 25 02:29:42 PM PST 24
Finished	Feb 25 02:30:08 PM PST 24
Peak memory	211228 kb
Host	smart-c73cb493-7237-4c51-966e-3ffc2a27b04c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2605891896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2605891896
Directory	/workspace/35.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3640330045
Short name	T766
Test name
Test status
Simulation time	4168311411 ps
CPU time	27.72 seconds
Started	Feb 25 02:29:36 PM PST 24
Finished	Feb 25 02:30:04 PM PST 24
Peak memory	203128 kb
Host	smart-3115d99c-bed6-4fbc-9549-befaf72ee960
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640330045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3640330045
Directory	/workspace/35.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1401953825
Short name	T170
Test name
Test status
Simulation time	32138768645 ps
CPU time	183.78 seconds
Started	Feb 25 02:29:39 PM PST 24
Finished	Feb 25 02:32:44 PM PST 24
Peak memory	204248 kb
Host	smart-013ac6d3-90eb-4049-a4d1-aa3c3770230d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1401953825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1401953825
Directory	/workspace/35.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.1435790184
Short name	T531
Test name
Test status
Simulation time	798990277 ps
CPU time	27.58 seconds
Started	Feb 25 02:29:40 PM PST 24
Finished	Feb 25 02:30:08 PM PST 24
Peak memory	211088 kb
Host	smart-500803fa-58e6-4332-a37f-5be1a334d06c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435790184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1435790184
Directory	/workspace/35.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_same_source.590445559
Short name	T313
Test name
Test status
Simulation time	208328449 ps
CPU time	3.01 seconds
Started	Feb 25 02:29:42 PM PST 24
Finished	Feb 25 02:29:45 PM PST 24
Peak memory	203048 kb
Host	smart-da99226e-1aac-495a-b909-cb42fabf35c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=590445559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.590445559
Directory	/workspace/35.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke.3681777960
Short name	T428
Test name
Test status
Simulation time	209848720 ps
CPU time	3.33 seconds
Started	Feb 25 02:29:35 PM PST 24
Finished	Feb 25 02:29:39 PM PST 24
Peak memory	203072 kb
Host	smart-47778755-2921-45e2-baac-46a2ffd875a3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3681777960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3681777960
Directory	/workspace/35.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.228253170
Short name	T50
Test name
Test status
Simulation time	7855342697 ps
CPU time	32.81 seconds
Started	Feb 25 02:29:42 PM PST 24
Finished	Feb 25 02:30:15 PM PST 24
Peak memory	203108 kb
Host	smart-a30a3d2b-02e8-4847-91c2-1a002a0b75b5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=228253170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.228253170
Directory	/workspace/35.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.1543220578
Short name	T600
Test name
Test status
Simulation time	19717119426 ps
CPU time	44.69 seconds
Started	Feb 25 02:29:37 PM PST 24
Finished	Feb 25 02:30:21 PM PST 24
Peak memory	203108 kb
Host	smart-9ebc0040-9f47-4a5a-8e4b-7c68510bf6c7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1543220578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1543220578
Directory	/workspace/35.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.2546591377
Short name	T597
Test name
Test status
Simulation time	27010937 ps
CPU time	2.32 seconds
Started	Feb 25 02:29:32 PM PST 24
Finished	Feb 25 02:29:35 PM PST 24
Peak memory	203068 kb
Host	smart-ca584bbf-7f08-4641-99c6-b50dca6cd044
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546591377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.2546591377
Directory	/workspace/35.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all.3777067886
Short name	T83
Test name
Test status
Simulation time	13351423507 ps
CPU time	140.79 seconds
Started	Feb 25 02:29:40 PM PST 24
Finished	Feb 25 02:32:01 PM PST 24
Peak memory	207312 kb
Host	smart-68b5ca56-45ee-43a5-8f67-0ae24d0abbf1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3777067886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3777067886
Directory	/workspace/35.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3489497515
Short name	T212
Test name
Test status
Simulation time	4342526582 ps
CPU time	51.56 seconds
Started	Feb 25 02:29:38 PM PST 24
Finished	Feb 25 02:30:29 PM PST 24
Peak memory	204144 kb
Host	smart-df09e372-c63b-4222-8d31-361ba9b8d868
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3489497515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3489497515
Directory	/workspace/35.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.3645390413
Short name	T206
Test name
Test status
Simulation time	185062953 ps
CPU time	120.35 seconds
Started	Feb 25 02:29:40 PM PST 24
Finished	Feb 25 02:31:40 PM PST 24
Peak memory	208220 kb
Host	smart-8537cb9a-2c8e-4a37-afb5-0a3388065b38
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3645390413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran d_reset.3645390413
Directory	/workspace/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1192548235
Short name	T248
Test name
Test status
Simulation time	22932397 ps
CPU time	1.89 seconds
Started	Feb 25 02:29:40 PM PST 24
Finished	Feb 25 02:29:42 PM PST 24
Peak memory	203028 kb
Host	smart-604f8a9b-0f72-4bef-b2c3-28e5bc810557
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1192548235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1192548235
Directory	/workspace/35.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device.730844797
Short name	T441
Test name
Test status
Simulation time	71232793 ps
CPU time	7.77 seconds
Started	Feb 25 02:29:39 PM PST 24
Finished	Feb 25 02:29:48 PM PST 24
Peak memory	203076 kb
Host	smart-5aca15da-329f-4bd9-8d4e-694c941b5c5f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=730844797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.730844797
Directory	/workspace/36.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3596906255
Short name	T265
Test name
Test status
Simulation time	131601441412 ps
CPU time	447.1 seconds
Started	Feb 25 02:29:45 PM PST 24
Finished	Feb 25 02:37:13 PM PST 24
Peak memory	211248 kb
Host	smart-5f90f8af-cd17-4c6d-8507-391ac68978ce
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3596906255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.3596906255
Directory	/workspace/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.400373537
Short name	T775
Test name
Test status
Simulation time	58756954 ps
CPU time	2.62 seconds
Started	Feb 25 02:29:43 PM PST 24
Finished	Feb 25 02:29:45 PM PST 24
Peak memory	203052 kb
Host	smart-ee6125d7-3d33-4e9a-ac8c-968a405deb1f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=400373537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.400373537
Directory	/workspace/36.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_error_random.2662325068
Short name	T812
Test name
Test status
Simulation time	892606744 ps
CPU time	38.4 seconds
Started	Feb 25 02:29:41 PM PST 24
Finished	Feb 25 02:30:20 PM PST 24
Peak memory	203140 kb
Host	smart-2c5efb1d-d256-4d15-aa59-1e6e12b664e2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2662325068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2662325068
Directory	/workspace/36.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random.960234582
Short name	T394
Test name
Test status
Simulation time	660662766 ps
CPU time	25.48 seconds
Started	Feb 25 02:29:38 PM PST 24
Finished	Feb 25 02:30:04 PM PST 24
Peak memory	204136 kb
Host	smart-d1df8266-8008-4ebe-91d7-aa82622c0cc1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960234582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.960234582
Directory	/workspace/36.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.719131778
Short name	T317
Test name
Test status
Simulation time	8240065574 ps
CPU time	36.82 seconds
Started	Feb 25 02:29:46 PM PST 24
Finished	Feb 25 02:30:23 PM PST 24
Peak memory	211292 kb
Host	smart-8d3d0094-29b0-4f8c-bdb0-d32ba0fe20c5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=719131778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.719131778
Directory	/workspace/36.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1915085701
Short name	T556
Test name
Test status
Simulation time	52521729791 ps
CPU time	173.52 seconds
Started	Feb 25 02:29:39 PM PST 24
Finished	Feb 25 02:32:33 PM PST 24
Peak memory	204248 kb
Host	smart-ce381262-497b-4f99-bc35-b105729a1e15
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1915085701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1915085701
Directory	/workspace/36.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2030798348
Short name	T879
Test name
Test status
Simulation time	26106184 ps
CPU time	3.85 seconds
Started	Feb 25 02:29:36 PM PST 24
Finished	Feb 25 02:29:40 PM PST 24
Peak memory	203076 kb
Host	smart-8a5d7279-aa4e-49e4-a1c2-450d97db420b
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030798348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2030798348
Directory	/workspace/36.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_same_source.3826758211
Short name	T544
Test name
Test status
Simulation time	4119873565 ps
CPU time	33.2 seconds
Started	Feb 25 02:29:42 PM PST 24
Finished	Feb 25 02:30:15 PM PST 24
Peak memory	203108 kb
Host	smart-6a2942a0-92c4-412d-8516-52ceae08fa6a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3826758211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3826758211
Directory	/workspace/36.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke.381486094
Short name	T96
Test name
Test status
Simulation time	42042818 ps
CPU time	2.34 seconds
Started	Feb 25 02:29:41 PM PST 24
Finished	Feb 25 02:29:44 PM PST 24
Peak memory	203008 kb
Host	smart-078b9dab-55f4-47b5-ab1c-d3f2b90b37bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=381486094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.381486094
Directory	/workspace/36.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3512264238
Short name	T763
Test name
Test status
Simulation time	31042397509 ps
CPU time	41.06 seconds
Started	Feb 25 02:29:36 PM PST 24
Finished	Feb 25 02:30:18 PM PST 24
Peak memory	203156 kb
Host	smart-465a9947-d183-489a-88e6-9739279f2882
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512264238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3512264238
Directory	/workspace/36.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.148185635
Short name	T818
Test name
Test status
Simulation time	4419622385 ps
CPU time	31.22 seconds
Started	Feb 25 02:29:44 PM PST 24
Finished	Feb 25 02:30:15 PM PST 24
Peak memory	203120 kb
Host	smart-aae51f63-02c3-4665-afab-1c6087025b26
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=148185635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.148185635
Directory	/workspace/36.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1852571999
Short name	T339
Test name
Test status
Simulation time	32980750 ps
CPU time	2.15 seconds
Started	Feb 25 02:29:35 PM PST 24
Finished	Feb 25 02:29:38 PM PST 24
Peak memory	203060 kb
Host	smart-8c4d7e4d-a3ae-475f-8057-f764554b2b3d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852571999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1852571999
Directory	/workspace/36.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all.1323154281
Short name	T172
Test name
Test status
Simulation time	9374382605 ps
CPU time	89.74 seconds
Started	Feb 25 02:29:40 PM PST 24
Finished	Feb 25 02:31:10 PM PST 24
Peak memory	206268 kb
Host	smart-a3932499-4f5d-4316-895c-1b99df126458
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1323154281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1323154281
Directory	/workspace/36.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3444784643
Short name	T816
Test name
Test status
Simulation time	2495003860 ps
CPU time	68.11 seconds
Started	Feb 25 02:29:40 PM PST 24
Finished	Feb 25 02:30:49 PM PST 24
Peak memory	205068 kb
Host	smart-406f9c12-f0a6-43db-b2b0-397e6985e5b1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3444784643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3444784643
Directory	/workspace/36.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.887667619
Short name	T724
Test name
Test status
Simulation time	1429263849 ps
CPU time	315.89 seconds
Started	Feb 25 02:29:44 PM PST 24
Finished	Feb 25 02:35:00 PM PST 24
Peak memory	211236 kb
Host	smart-923e49c2-99e6-4f0a-8943-c6e322fd6fba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=887667619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand _reset.887667619
Directory	/workspace/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.2504081874
Short name	T378
Test name
Test status
Simulation time	511944993 ps
CPU time	156.41 seconds
Started	Feb 25 02:29:41 PM PST 24
Finished	Feb 25 02:32:17 PM PST 24
Peak memory	209900 kb
Host	smart-ae5b38fa-d903-47be-b447-6d33b322c496
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2504081874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re set_error.2504081874
Directory	/workspace/36.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.367080912
Short name	T861
Test name
Test status
Simulation time	44561078 ps
CPU time	2.25 seconds
Started	Feb 25 02:29:42 PM PST 24
Finished	Feb 25 02:29:44 PM PST 24
Peak memory	203048 kb
Host	smart-abb8c84f-3183-4194-9dcc-a08b931ea610
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=367080912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.367080912
Directory	/workspace/36.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device.479053656
Short name	T487
Test name
Test status
Simulation time	183997739 ps
CPU time	16.97 seconds
Started	Feb 25 02:29:45 PM PST 24
Finished	Feb 25 02:30:03 PM PST 24
Peak memory	211140 kb
Host	smart-de962672-a732-48ba-9f54-52f8213ae6b5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=479053656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.479053656
Directory	/workspace/37.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1996973481
Short name	T502
Test name
Test status
Simulation time	49760414647 ps
CPU time	380.54 seconds
Started	Feb 25 02:29:41 PM PST 24
Finished	Feb 25 02:36:02 PM PST 24
Peak memory	211292 kb
Host	smart-1c27513c-2185-41e2-83ed-de19af7ba7a8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1996973481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.1996973481
Directory	/workspace/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1873289155
Short name	T376
Test name
Test status
Simulation time	314806323 ps
CPU time	9.43 seconds
Started	Feb 25 02:29:51 PM PST 24
Finished	Feb 25 02:30:01 PM PST 24
Peak memory	203068 kb
Host	smart-cb3ab0c9-4b74-4fe9-a9e3-a31f357e8887
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1873289155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1873289155
Directory	/workspace/37.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_error_random.1746706203
Short name	T475
Test name
Test status
Simulation time	1127348207 ps
CPU time	25.99 seconds
Started	Feb 25 02:29:49 PM PST 24
Finished	Feb 25 02:30:17 PM PST 24
Peak memory	203072 kb
Host	smart-7cf4ed1e-e7de-4e6f-ab60-3ef82687c4c7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1746706203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1746706203
Directory	/workspace/37.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random.3339122802
Short name	T694
Test name
Test status
Simulation time	1548051674 ps
CPU time	22.41 seconds
Started	Feb 25 02:29:42 PM PST 24
Finished	Feb 25 02:30:05 PM PST 24
Peak memory	204204 kb
Host	smart-67727a0c-abc3-47c4-b293-c82a95e9565d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3339122802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3339122802
Directory	/workspace/37.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.402484126
Short name	T157
Test name
Test status
Simulation time	53110147193 ps
CPU time	224.24 seconds
Started	Feb 25 02:29:39 PM PST 24
Finished	Feb 25 02:33:24 PM PST 24
Peak memory	204316 kb
Host	smart-5f919892-93a4-4082-a1a3-58d163a67d54
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=402484126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.402484126
Directory	/workspace/37.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.1148480384
Short name	T512
Test name
Test status
Simulation time	50531808004 ps
CPU time	215.55 seconds
Started	Feb 25 02:29:45 PM PST 24
Finished	Feb 25 02:33:21 PM PST 24
Peak memory	211316 kb
Host	smart-38edabdb-8eac-4241-9cc6-3446c4594ad5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1148480384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1148480384
Directory	/workspace/37.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1877646335
Short name	T691
Test name
Test status
Simulation time	41126890 ps
CPU time	2.11 seconds
Started	Feb 25 02:29:47 PM PST 24
Finished	Feb 25 02:29:50 PM PST 24
Peak memory	203084 kb
Host	smart-b3d3d430-470f-4845-a95e-06e13b33c84c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877646335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1877646335
Directory	/workspace/37.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_same_source.503079906
Short name	T845
Test name
Test status
Simulation time	592661264 ps
CPU time	19.6 seconds
Started	Feb 25 02:29:45 PM PST 24
Finished	Feb 25 02:30:05 PM PST 24
Peak memory	203068 kb
Host	smart-5f6e3837-72e1-4b60-93ea-956f37d0bb20
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=503079906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.503079906
Directory	/workspace/37.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke.3340011119
Short name	T813
Test name
Test status
Simulation time	46008876 ps
CPU time	2.14 seconds
Started	Feb 25 02:29:42 PM PST 24
Finished	Feb 25 02:29:44 PM PST 24
Peak memory	203000 kb
Host	smart-17a86def-a9ca-4407-acec-b7969309c022
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3340011119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3340011119
Directory	/workspace/37.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3002560495
Short name	T65
Test name
Test status
Simulation time	24947207073 ps
CPU time	33.89 seconds
Started	Feb 25 02:29:44 PM PST 24
Finished	Feb 25 02:30:18 PM PST 24
Peak memory	203108 kb
Host	smart-34cb2e38-e27c-465a-94d5-18129bce620f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002560495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3002560495
Directory	/workspace/37.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.396446322
Short name	T726
Test name
Test status
Simulation time	9038128845 ps
CPU time	32.78 seconds
Started	Feb 25 02:29:42 PM PST 24
Finished	Feb 25 02:30:15 PM PST 24
Peak memory	203028 kb
Host	smart-1ebc4b41-2032-426e-bfd1-8201a98df8c6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=396446322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.396446322
Directory	/workspace/37.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.3651225555
Short name	T90
Test name
Test status
Simulation time	97262967 ps
CPU time	2.29 seconds
Started	Feb 25 02:29:46 PM PST 24
Finished	Feb 25 02:29:48 PM PST 24
Peak memory	203072 kb
Host	smart-da5dfbe7-e2f7-46d2-b556-bd6ebc114d39
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651225555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.3651225555
Directory	/workspace/37.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all.2613425946
Short name	T551
Test name
Test status
Simulation time	984567883 ps
CPU time	124.31 seconds
Started	Feb 25 02:29:49 PM PST 24
Finished	Feb 25 02:31:55 PM PST 24
Peak memory	209440 kb
Host	smart-64a58edb-488a-41dd-87fc-4d7cc3aedb62
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2613425946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2613425946
Directory	/workspace/37.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1082291639
Short name	T722
Test name
Test status
Simulation time	2985455854 ps
CPU time	191.73 seconds
Started	Feb 25 02:29:49 PM PST 24
Finished	Feb 25 02:33:01 PM PST 24
Peak memory	208532 kb
Host	smart-e36f7814-dcfe-4c00-be1c-d3a4cb5ea3ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1082291639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1082291639
Directory	/workspace/37.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2991502599
Short name	T300
Test name
Test status
Simulation time	85882623 ps
CPU time	52.3 seconds
Started	Feb 25 02:29:53 PM PST 24
Finished	Feb 25 02:30:46 PM PST 24
Peak memory	205900 kb
Host	smart-157ad72f-86b5-423d-b87e-a57ba9da1b7f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2991502599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran d_reset.2991502599
Directory	/workspace/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2968763321
Short name	T20
Test name
Test status
Simulation time	203476995 ps
CPU time	44.44 seconds
Started	Feb 25 02:29:49 PM PST 24
Finished	Feb 25 02:30:35 PM PST 24
Peak memory	206016 kb
Host	smart-90f6f2b4-7e55-4797-872b-1ce61b941a91
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2968763321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.2968763321
Directory	/workspace/37.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.3878326473
Short name	T704
Test name
Test status
Simulation time	1190692502 ps
CPU time	16.14 seconds
Started	Feb 25 02:29:52 PM PST 24
Finished	Feb 25 02:30:10 PM PST 24
Peak memory	204300 kb
Host	smart-8afb7ff4-6908-4e60-8051-9f5f233db8d4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3878326473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3878326473
Directory	/workspace/37.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device.3695094228
Short name	T24
Test name
Test status
Simulation time	1724214188 ps
CPU time	73.89 seconds
Started	Feb 25 02:29:56 PM PST 24
Finished	Feb 25 02:31:10 PM PST 24
Peak memory	206120 kb
Host	smart-b1e81868-fd38-47cd-961d-9856f785e911
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3695094228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3695094228
Directory	/workspace/38.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.2809898757
Short name	T885
Test name
Test status
Simulation time	3072801638 ps
CPU time	28.95 seconds
Started	Feb 25 02:29:50 PM PST 24
Finished	Feb 25 02:30:20 PM PST 24
Peak memory	203204 kb
Host	smart-a35479bd-a245-4647-8538-e35f223c38f3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2809898757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.2809898757
Directory	/workspace/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.261738621
Short name	T826
Test name
Test status
Simulation time	17921536 ps
CPU time	1.95 seconds
Started	Feb 25 02:29:48 PM PST 24
Finished	Feb 25 02:29:52 PM PST 24
Peak memory	203048 kb
Host	smart-249d21f5-20a7-4d9d-a481-4f33cc7e7353
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=261738621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.261738621
Directory	/workspace/38.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_error_random.1532030744
Short name	T471
Test name
Test status
Simulation time	1302266554 ps
CPU time	11.87 seconds
Started	Feb 25 02:29:53 PM PST 24
Finished	Feb 25 02:30:06 PM PST 24
Peak memory	202772 kb
Host	smart-44e27a92-1068-4378-bc1a-27056876582f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1532030744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1532030744
Directory	/workspace/38.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random.2911919173
Short name	T152
Test name
Test status
Simulation time	508789492 ps
CPU time	12.67 seconds
Started	Feb 25 02:29:51 PM PST 24
Finished	Feb 25 02:30:05 PM PST 24
Peak memory	204056 kb
Host	smart-1d1e0353-240a-4094-a121-38a7adcda82d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2911919173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2911919173
Directory	/workspace/38.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3892053816
Short name	T419
Test name
Test status
Simulation time	29814308830 ps
CPU time	92.38 seconds
Started	Feb 25 02:29:52 PM PST 24
Finished	Feb 25 02:31:25 PM PST 24
Peak memory	211300 kb
Host	smart-6a625006-1936-42c2-b5de-5e64d48376d5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892053816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3892053816
Directory	/workspace/38.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1292716297
Short name	T546
Test name
Test status
Simulation time	35902008640 ps
CPU time	173.35 seconds
Started	Feb 25 02:29:50 PM PST 24
Finished	Feb 25 02:32:45 PM PST 24
Peak memory	211304 kb
Host	smart-b3104289-b165-4926-8afc-1468462a7ef8
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1292716297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1292716297
Directory	/workspace/38.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.2882851844
Short name	T539
Test name
Test status
Simulation time	39863589 ps
CPU time	6.77 seconds
Started	Feb 25 02:29:56 PM PST 24
Finished	Feb 25 02:30:03 PM PST 24
Peak memory	204140 kb
Host	smart-8fa558c2-b46e-42d4-8092-e6a8a4db6867
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882851844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2882851844
Directory	/workspace/38.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_same_source.427787960
Short name	T19
Test name
Test status
Simulation time	472540649 ps
CPU time	17.02 seconds
Started	Feb 25 02:29:48 PM PST 24
Finished	Feb 25 02:30:07 PM PST 24
Peak memory	203068 kb
Host	smart-1dcb38eb-eefe-44e0-a955-21c9b5c44696
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=427787960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.427787960
Directory	/workspace/38.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke.3221960677
Short name	T361
Test name
Test status
Simulation time	144512424 ps
CPU time	3.48 seconds
Started	Feb 25 02:29:56 PM PST 24
Finished	Feb 25 02:30:00 PM PST 24
Peak memory	203060 kb
Host	smart-2362757f-bfdf-479f-8128-cf370081eb5f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3221960677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3221960677
Directory	/workspace/38.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.2764407588
Short name	T653
Test name
Test status
Simulation time	19882603404 ps
CPU time	40.36 seconds
Started	Feb 25 02:29:49 PM PST 24
Finished	Feb 25 02:30:32 PM PST 24
Peak memory	203056 kb
Host	smart-c3e1fba1-83cb-446a-aa59-a2968b0683cb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764407588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2764407588
Directory	/workspace/38.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2509371230
Short name	T747
Test name
Test status
Simulation time	5648994060 ps
CPU time	34.35 seconds
Started	Feb 25 02:29:48 PM PST 24
Finished	Feb 25 02:30:24 PM PST 24
Peak memory	203128 kb
Host	smart-1261ff2c-d59c-4ae3-a91c-873cab5885eb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2509371230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2509371230
Directory	/workspace/38.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.3517089820
Short name	T342
Test name
Test status
Simulation time	42207506 ps
CPU time	2.47 seconds
Started	Feb 25 02:29:50 PM PST 24
Finished	Feb 25 02:29:54 PM PST 24
Peak memory	203056 kb
Host	smart-2d0ea55a-95fe-4018-af19-fd4e55eba2be
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517089820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.3517089820
Directory	/workspace/38.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all.210800802
Short name	T480
Test name
Test status
Simulation time	1343464027 ps
CPU time	106.31 seconds
Started	Feb 25 02:29:48 PM PST 24
Finished	Feb 25 02:31:35 PM PST 24
Peak memory	207028 kb
Host	smart-6c80f43c-a158-4bd4-8e94-a1118c349a74
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=210800802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.210800802
Directory	/workspace/38.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.513147270
Short name	T891
Test name
Test status
Simulation time	14674827755 ps
CPU time	116.74 seconds
Started	Feb 25 02:29:56 PM PST 24
Finished	Feb 25 02:31:53 PM PST 24
Peak memory	207296 kb
Host	smart-14d6c04b-9f55-4879-8159-ccff25e311f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=513147270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.513147270
Directory	/workspace/38.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2664883624
Short name	T124
Test name
Test status
Simulation time	16753020496 ps
CPU time	777.31 seconds
Started	Feb 25 02:29:50 PM PST 24
Finished	Feb 25 02:42:49 PM PST 24
Peak memory	209204 kb
Host	smart-fc813a1c-d28e-4129-bc04-02972b78acac
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2664883624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran d_reset.2664883624
Directory	/workspace/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1222110491
Short name	T612
Test name
Test status
Simulation time	106472803 ps
CPU time	29.6 seconds
Started	Feb 25 02:29:47 PM PST 24
Finished	Feb 25 02:30:18 PM PST 24
Peak memory	206052 kb
Host	smart-a38accc5-04bb-4a9c-8c88-32ac36fdd360
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1222110491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re set_error.1222110491
Directory	/workspace/38.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.3336595052
Short name	T14
Test name
Test status
Simulation time	270742826 ps
CPU time	6.5 seconds
Started	Feb 25 02:29:49 PM PST 24
Finished	Feb 25 02:29:56 PM PST 24
Peak memory	204348 kb
Host	smart-baaca1f8-8e03-40e5-8683-7d35b83286cf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3336595052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3336595052
Directory	/workspace/38.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device.4145124536
Short name	T658
Test name
Test status
Simulation time	1473357998 ps
CPU time	50.51 seconds
Started	Feb 25 02:29:58 PM PST 24
Finished	Feb 25 02:30:49 PM PST 24
Peak memory	204700 kb
Host	smart-76117cd9-88c5-40b1-a5da-529b4571d52e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4145124536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.4145124536
Directory	/workspace/39.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1182638513
Short name	T130
Test name
Test status
Simulation time	61003330043 ps
CPU time	539.57 seconds
Started	Feb 25 02:29:58 PM PST 24
Finished	Feb 25 02:38:58 PM PST 24
Peak memory	211300 kb
Host	smart-02ea2039-0e21-47e3-beb6-4e1c4689332f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1182638513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.1182638513
Directory	/workspace/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2761744304
Short name	T882
Test name
Test status
Simulation time	1016937162 ps
CPU time	12.44 seconds
Started	Feb 25 02:29:58 PM PST 24
Finished	Feb 25 02:30:10 PM PST 24
Peak memory	203068 kb
Host	smart-a94300c6-593e-4b36-bae5-8798b17fbd36
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2761744304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2761744304
Directory	/workspace/39.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_error_random.3127092727
Short name	T630
Test name
Test status
Simulation time	98745188 ps
CPU time	12.17 seconds
Started	Feb 25 02:29:59 PM PST 24
Finished	Feb 25 02:30:11 PM PST 24
Peak memory	203048 kb
Host	smart-2a7142a8-6f3e-4acb-aca0-e064d3d35fc6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3127092727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3127092727
Directory	/workspace/39.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random.2046148716
Short name	T31
Test name
Test status
Simulation time	880405923 ps
CPU time	30.25 seconds
Started	Feb 25 02:29:59 PM PST 24
Finished	Feb 25 02:30:29 PM PST 24
Peak memory	204328 kb
Host	smart-49519e8b-ea07-4ffb-99d4-9f1c336fc8d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2046148716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2046148716
Directory	/workspace/39.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.4066872931
Short name	T105
Test name
Test status
Simulation time	132278319153 ps
CPU time	276.29 seconds
Started	Feb 25 02:29:59 PM PST 24
Finished	Feb 25 02:34:35 PM PST 24
Peak memory	211288 kb
Host	smart-69397c00-605c-4a90-8fbe-883cbea6e032
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066872931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.4066872931
Directory	/workspace/39.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2405909888
Short name	T469
Test name
Test status
Simulation time	19388324818 ps
CPU time	83.7 seconds
Started	Feb 25 02:29:59 PM PST 24
Finished	Feb 25 02:31:23 PM PST 24
Peak memory	211288 kb
Host	smart-b1e7d38c-cac9-49f1-b438-350ba20b3d11
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2405909888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2405909888
Directory	/workspace/39.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2973040112
Short name	T843
Test name
Test status
Simulation time	158609587 ps
CPU time	18.56 seconds
Started	Feb 25 02:30:01 PM PST 24
Finished	Feb 25 02:30:20 PM PST 24
Peak memory	204368 kb
Host	smart-395a7345-51fb-4ee9-8de3-356fc4cd3536
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973040112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2973040112
Directory	/workspace/39.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_same_source.398100447
Short name	T639
Test name
Test status
Simulation time	1237393832 ps
CPU time	11.61 seconds
Started	Feb 25 02:29:59 PM PST 24
Finished	Feb 25 02:30:11 PM PST 24
Peak memory	203052 kb
Host	smart-336bcf6f-3eb9-44af-aa97-356fb9f0eafe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=398100447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.398100447
Directory	/workspace/39.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke.1177937263
Short name	T765
Test name
Test status
Simulation time	101077816 ps
CPU time	3.15 seconds
Started	Feb 25 02:30:00 PM PST 24
Finished	Feb 25 02:30:03 PM PST 24
Peak memory	203048 kb
Host	smart-1f9da8b2-6e1f-4b67-b9a7-c37efbadee94
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1177937263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1177937263
Directory	/workspace/39.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.2550940080
Short name	T277
Test name
Test status
Simulation time	19519252847 ps
CPU time	45.25 seconds
Started	Feb 25 02:29:57 PM PST 24
Finished	Feb 25 02:30:42 PM PST 24
Peak memory	203112 kb
Host	smart-034cd7f2-8f3e-43d4-85e4-82c7bdfed772
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550940080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2550940080
Directory	/workspace/39.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.251257516
Short name	T275
Test name
Test status
Simulation time	4734604095 ps
CPU time	28.55 seconds
Started	Feb 25 02:29:57 PM PST 24
Finished	Feb 25 02:30:26 PM PST 24
Peak memory	203112 kb
Host	smart-eebf1789-7962-470c-b615-5ec7260f201b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=251257516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.251257516
Directory	/workspace/39.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.87204153
Short name	T283
Test name
Test status
Simulation time	113286619 ps
CPU time	2.57 seconds
Started	Feb 25 02:30:01 PM PST 24
Finished	Feb 25 02:30:03 PM PST 24
Peak memory	203028 kb
Host	smart-236a8f74-297e-40b5-816b-a8888d5431ed
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87204153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.87204153
Directory	/workspace/39.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all.929803225
Short name	T196
Test name
Test status
Simulation time	908127243 ps
CPU time	121.6 seconds
Started	Feb 25 02:30:00 PM PST 24
Finished	Feb 25 02:32:01 PM PST 24
Peak memory	205376 kb
Host	smart-4a8013c3-0f98-424a-9d0d-ab2600dfd055
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=929803225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.929803225
Directory	/workspace/39.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3163102986
Short name	T857
Test name
Test status
Simulation time	2916159978 ps
CPU time	109.54 seconds
Started	Feb 25 02:30:09 PM PST 24
Finished	Feb 25 02:31:58 PM PST 24
Peak memory	205620 kb
Host	smart-51725f45-27aa-45a6-8750-c79cc31f1c1f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3163102986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3163102986
Directory	/workspace/39.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.2858446218
Short name	T202
Test name
Test status
Simulation time	580240929 ps
CPU time	125.23 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:32:35 PM PST 24
Peak memory	208068 kb
Host	smart-79897fe1-9498-40d3-9949-12c4f6a3165e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2858446218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran d_reset.2858446218
Directory	/workspace/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2962792697
Short name	T34
Test name
Test status
Simulation time	408083698 ps
CPU time	140.49 seconds
Started	Feb 25 02:30:16 PM PST 24
Finished	Feb 25 02:32:36 PM PST 24
Peak memory	208824 kb
Host	smart-2aba110c-475e-45c7-816e-36bfa8decbbd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2962792697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_re set_error.2962792697
Directory	/workspace/39.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.2703378814
Short name	T450
Test name
Test status
Simulation time	409411460 ps
CPU time	7.07 seconds
Started	Feb 25 02:29:59 PM PST 24
Finished	Feb 25 02:30:06 PM PST 24
Peak memory	204164 kb
Host	smart-c31a25ca-d2a3-4f86-885c-e0d50490edfd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2703378814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2703378814
Directory	/workspace/39.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device.663437672
Short name	T558
Test name
Test status
Simulation time	524127884 ps
CPU time	31.37 seconds
Started	Feb 25 02:26:33 PM PST 24
Finished	Feb 25 02:27:04 PM PST 24
Peak memory	211228 kb
Host	smart-c6f92f67-62bd-4ed6-b1d6-24068ad9127c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=663437672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.663437672
Directory	/workspace/4.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2540143845
Short name	T779
Test name
Test status
Simulation time	8338385291 ps
CPU time	58 seconds
Started	Feb 25 02:26:36 PM PST 24
Finished	Feb 25 02:27:34 PM PST 24
Peak memory	203152 kb
Host	smart-e5b9f40d-1b45-4162-9b4f-e24934540498
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2540143845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo w_rsp.2540143845
Directory	/workspace/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.1229989620
Short name	T817
Test name
Test status
Simulation time	1802917973 ps
CPU time	30.8 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:27:00 PM PST 24
Peak memory	203076 kb
Host	smart-096f78a0-7fa3-4b7d-af32-139e60567869
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1229989620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1229989620
Directory	/workspace/4.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_error_random.1804830702
Short name	T500
Test name
Test status
Simulation time	782509556 ps
CPU time	7.04 seconds
Started	Feb 25 02:26:28 PM PST 24
Finished	Feb 25 02:26:36 PM PST 24
Peak memory	203052 kb
Host	smart-693ae1c5-8a89-490b-a8af-5f891572f833
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1804830702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1804830702
Directory	/workspace/4.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random.319678350
Short name	T717
Test name
Test status
Simulation time	241673180 ps
CPU time	10.48 seconds
Started	Feb 25 02:26:30 PM PST 24
Finished	Feb 25 02:26:40 PM PST 24
Peak memory	204100 kb
Host	smart-b45f58e5-7fa2-4cee-82f1-bf2838feca05
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=319678350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.319678350
Directory	/workspace/4.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.3959745543
Short name	T215
Test name
Test status
Simulation time	15937745633 ps
CPU time	49.73 seconds
Started	Feb 25 02:26:36 PM PST 24
Finished	Feb 25 02:27:27 PM PST 24
Peak memory	204144 kb
Host	smart-1160a89d-f0b9-4e6f-a1bf-d7036a3717de
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959745543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3959745543
Directory	/workspace/4.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2034810077
Short name	T281
Test name
Test status
Simulation time	4568860547 ps
CPU time	24.04 seconds
Started	Feb 25 02:26:32 PM PST 24
Finished	Feb 25 02:26:56 PM PST 24
Peak memory	203896 kb
Host	smart-27379676-c322-4ce1-8c4b-58f0b5338341
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2034810077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2034810077
Directory	/workspace/4.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1672139648
Short name	T477
Test name
Test status
Simulation time	257910675 ps
CPU time	13.14 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:26:43 PM PST 24
Peak memory	204048 kb
Host	smart-8e3ee80f-f0a1-4e2e-b6a1-ddb6ead62f6c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672139648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1672139648
Directory	/workspace/4.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_same_source.2420824300
Short name	T721
Test name
Test status
Simulation time	49435385 ps
CPU time	3.36 seconds
Started	Feb 25 02:26:28 PM PST 24
Finished	Feb 25 02:26:31 PM PST 24
Peak memory	202936 kb
Host	smart-0bd3082b-ed34-43a4-8ccf-788ce9df1bc3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2420824300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2420824300
Directory	/workspace/4.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke.1058382546
Short name	T51
Test name
Test status
Simulation time	32803580 ps
CPU time	2.34 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:26:32 PM PST 24
Peak memory	203004 kb
Host	smart-c9195721-41f9-4273-a3f5-440456c6a734
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1058382546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1058382546
Directory	/workspace/4.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2119190523
Short name	T839
Test name
Test status
Simulation time	10360612614 ps
CPU time	32.02 seconds
Started	Feb 25 02:26:28 PM PST 24
Finished	Feb 25 02:27:01 PM PST 24
Peak memory	203068 kb
Host	smart-97cd7c39-a48b-4837-95dc-94a6234ee901
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119190523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2119190523
Directory	/workspace/4.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.1519699171
Short name	T401
Test name
Test status
Simulation time	12331806270 ps
CPU time	33.34 seconds
Started	Feb 25 02:26:32 PM PST 24
Finished	Feb 25 02:27:05 PM PST 24
Peak memory	203036 kb
Host	smart-d1405698-9c60-4e07-a72f-a5df533308b3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1519699171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1519699171
Directory	/workspace/4.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3628679592
Short name	T314
Test name
Test status
Simulation time	69507139 ps
CPU time	2.32 seconds
Started	Feb 25 02:26:28 PM PST 24
Finished	Feb 25 02:26:31 PM PST 24
Peak memory	202848 kb
Host	smart-95b07193-80e3-4e4f-bdbc-a39b53936c26
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628679592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3628679592
Directory	/workspace/4.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all.561227894
Short name	T866
Test name
Test status
Simulation time	8546597410 ps
CPU time	187.81 seconds
Started	Feb 25 02:26:31 PM PST 24
Finished	Feb 25 02:29:39 PM PST 24
Peak memory	206920 kb
Host	smart-da07ea5c-a75f-4f7c-ab85-c5935df830ee
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=561227894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.561227894
Directory	/workspace/4.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2719053195
Short name	T623
Test name
Test status
Simulation time	3404470716 ps
CPU time	80.12 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:27:49 PM PST 24
Peak memory	204528 kb
Host	smart-430edb7c-c48e-441b-9226-36fba1423aa3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2719053195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2719053195
Directory	/workspace/4.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.2333626730
Short name	T36
Test name
Test status
Simulation time	2292232903 ps
CPU time	292.88 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:31:22 PM PST 24
Peak memory	209060 kb
Host	smart-308f5879-5997-4884-887f-db7bc325c38d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2333626730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.2333626730
Directory	/workspace/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.4123110295
Short name	T30
Test name
Test status
Simulation time	807871326 ps
CPU time	196.04 seconds
Started	Feb 25 02:26:35 PM PST 24
Finished	Feb 25 02:29:51 PM PST 24
Peak memory	211080 kb
Host	smart-5d0de01e-3b11-43e4-9eee-4571af27dc53
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4123110295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.4123110295
Directory	/workspace/4.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.491451779
Short name	T173
Test name
Test status
Simulation time	815294642 ps
CPU time	35.59 seconds
Started	Feb 25 02:26:30 PM PST 24
Finished	Feb 25 02:27:05 PM PST 24
Peak memory	204596 kb
Host	smart-4c25f41a-7bf2-4e46-978a-e5f1876b747b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=491451779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.491451779
Directory	/workspace/4.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device.70124420
Short name	T424
Test name
Test status
Simulation time	389637895 ps
CPU time	36.12 seconds
Started	Feb 25 02:30:18 PM PST 24
Finished	Feb 25 02:30:55 PM PST 24
Peak memory	211192 kb
Host	smart-4f68e076-7e35-4f19-8e77-c40cf3a773e4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=70124420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.70124420
Directory	/workspace/40.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3933220906
Short name	T127
Test name
Test status
Simulation time	76552006685 ps
CPU time	370.11 seconds
Started	Feb 25 02:30:15 PM PST 24
Finished	Feb 25 02:36:25 PM PST 24
Peak memory	211316 kb
Host	smart-b96d2237-7308-4755-b224-219d3273d4a6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3933220906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.3933220906
Directory	/workspace/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2005837283
Short name	T13
Test name
Test status
Simulation time	376377266 ps
CPU time	10.96 seconds
Started	Feb 25 02:30:16 PM PST 24
Finished	Feb 25 02:30:27 PM PST 24
Peak memory	203076 kb
Host	smart-c55ab8d0-46bf-4062-b51e-5f358cb95f2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2005837283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2005837283
Directory	/workspace/40.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_error_random.3550146234
Short name	T646
Test name
Test status
Simulation time	3725491485 ps
CPU time	34.56 seconds
Started	Feb 25 02:30:15 PM PST 24
Finished	Feb 25 02:30:49 PM PST 24
Peak memory	203036 kb
Host	smart-e9f24880-d620-4cc0-b56c-f4baafe94c22
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3550146234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3550146234
Directory	/workspace/40.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random.2293171601
Short name	T458
Test name
Test status
Simulation time	545210649 ps
CPU time	23.11 seconds
Started	Feb 25 02:30:14 PM PST 24
Finished	Feb 25 02:30:38 PM PST 24
Peak memory	204320 kb
Host	smart-b417cdef-0614-4a89-9a84-27c51fe34b79
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2293171601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.2293171601
Directory	/workspace/40.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.3510112469
Short name	T94
Test name
Test status
Simulation time	118644331187 ps
CPU time	222.78 seconds
Started	Feb 25 02:30:19 PM PST 24
Finished	Feb 25 02:34:02 PM PST 24
Peak memory	211320 kb
Host	smart-3d007be0-2d5f-49fc-8087-b4143b079df7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510112469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3510112469
Directory	/workspace/40.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2700643062
Short name	T755
Test name
Test status
Simulation time	26454211835 ps
CPU time	179.59 seconds
Started	Feb 25 02:30:17 PM PST 24
Finished	Feb 25 02:33:17 PM PST 24
Peak memory	204548 kb
Host	smart-a78b34e4-0a55-4c49-8b98-d46994bd0a23
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2700643062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2700643062
Directory	/workspace/40.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2775655397
Short name	T718
Test name
Test status
Simulation time	132758147 ps
CPU time	6.16 seconds
Started	Feb 25 02:30:26 PM PST 24
Finished	Feb 25 02:30:32 PM PST 24
Peak memory	204188 kb
Host	smart-c8254b4f-f99a-4372-842f-3d11ca82b343
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775655397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2775655397
Directory	/workspace/40.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_same_source.2878038612
Short name	T183
Test name
Test status
Simulation time	1147508702 ps
CPU time	29.74 seconds
Started	Feb 25 02:30:10 PM PST 24
Finished	Feb 25 02:30:40 PM PST 24
Peak memory	202936 kb
Host	smart-53ce128e-0c9d-4f45-99a6-467fde998a31
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2878038612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2878038612
Directory	/workspace/40.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke.1399093092
Short name	T162
Test name
Test status
Simulation time	161733092 ps
CPU time	4.08 seconds
Started	Feb 25 02:30:13 PM PST 24
Finished	Feb 25 02:30:17 PM PST 24
Peak memory	203008 kb
Host	smart-d92611ec-f5bd-4218-9251-9af42989db00
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1399093092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1399093092
Directory	/workspace/40.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.2770217854
Short name	T325
Test name
Test status
Simulation time	4483902538 ps
CPU time	26.48 seconds
Started	Feb 25 02:30:16 PM PST 24
Finished	Feb 25 02:30:42 PM PST 24
Peak memory	203120 kb
Host	smart-076a1d44-d0f3-46c0-ae99-d8307bdcf57f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770217854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2770217854
Directory	/workspace/40.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1411667021
Short name	T355
Test name
Test status
Simulation time	6593888557 ps
CPU time	27.51 seconds
Started	Feb 25 02:30:17 PM PST 24
Finished	Feb 25 02:30:45 PM PST 24
Peak memory	203028 kb
Host	smart-1dbc3a49-c8fd-491f-914c-b944343553f1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1411667021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1411667021
Directory	/workspace/40.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2431125006
Short name	T7
Test name
Test status
Simulation time	28318823 ps
CPU time	2.36 seconds
Started	Feb 25 02:30:19 PM PST 24
Finished	Feb 25 02:30:21 PM PST 24
Peak memory	203072 kb
Host	smart-14697f53-1b22-43a1-a549-ddcfb8a1abe3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431125006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2431125006
Directory	/workspace/40.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all.3371288818
Short name	T169
Test name
Test status
Simulation time	18749005312 ps
CPU time	364.53 seconds
Started	Feb 25 02:30:10 PM PST 24
Finished	Feb 25 02:36:15 PM PST 24
Peak memory	211280 kb
Host	smart-0f450cfd-e379-4182-b19e-cc93ed678e34
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3371288818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3371288818
Directory	/workspace/40.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1020090836
Short name	T575
Test name
Test status
Simulation time	3845041660 ps
CPU time	67.24 seconds
Started	Feb 25 02:30:26 PM PST 24
Finished	Feb 25 02:31:33 PM PST 24
Peak memory	204140 kb
Host	smart-1d0f41b2-feef-4ed6-9563-4b2f4154e785
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1020090836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1020090836
Directory	/workspace/40.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2439887238
Short name	T82
Test name
Test status
Simulation time	13602751229 ps
CPU time	209.1 seconds
Started	Feb 25 02:30:24 PM PST 24
Finished	Feb 25 02:33:53 PM PST 24
Peak memory	208424 kb
Host	smart-c90fed0a-56bc-40c5-b5bb-ccae3e40f761
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2439887238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.2439887238
Directory	/workspace/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.775930962
Short name	T491
Test name
Test status
Simulation time	137256403 ps
CPU time	63.99 seconds
Started	Feb 25 02:30:24 PM PST 24
Finished	Feb 25 02:31:29 PM PST 24
Peak memory	206584 kb
Host	smart-63cdc799-97e5-4ee7-82aa-b71806589fa9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=775930962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res et_error.775930962
Directory	/workspace/40.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.2692346902
Short name	T243
Test name
Test status
Simulation time	994693993 ps
CPU time	32.29 seconds
Started	Feb 25 02:30:24 PM PST 24
Finished	Feb 25 02:30:57 PM PST 24
Peak memory	204436 kb
Host	smart-fb38454a-ab20-4054-b65c-9c549a5ab222
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2692346902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2692346902
Directory	/workspace/40.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device.1772514232
Short name	T872
Test name
Test status
Simulation time	1819408411 ps
CPU time	45.78 seconds
Started	Feb 25 02:30:27 PM PST 24
Finished	Feb 25 02:31:13 PM PST 24
Peak memory	205416 kb
Host	smart-a2d77305-b6c7-4d20-b861-13e1491d84ca
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1772514232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1772514232
Directory	/workspace/41.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.3265053937
Short name	T223
Test name
Test status
Simulation time	54180452651 ps
CPU time	407.93 seconds
Started	Feb 25 02:30:25 PM PST 24
Finished	Feb 25 02:37:13 PM PST 24
Peak memory	205504 kb
Host	smart-b1fc1f9f-3f86-42bd-b6b3-6a84aec32ac7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3265053937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.3265053937
Directory	/workspace/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3956939793
Short name	T6
Test name
Test status
Simulation time	262420702 ps
CPU time	17.22 seconds
Started	Feb 25 02:30:26 PM PST 24
Finished	Feb 25 02:30:43 PM PST 24
Peak memory	203312 kb
Host	smart-14a5aa3e-e9d7-4bb5-8713-b7795aea7e71
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3956939793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3956939793
Directory	/workspace/41.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_error_random.4114447594
Short name	T660
Test name
Test status
Simulation time	119580948 ps
CPU time	5.82 seconds
Started	Feb 25 02:30:15 PM PST 24
Finished	Feb 25 02:30:21 PM PST 24
Peak memory	203044 kb
Host	smart-827bd013-666a-4718-b8d3-d334434e3ced
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4114447594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.4114447594
Directory	/workspace/41.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random.1949554809
Short name	T631
Test name
Test status
Simulation time	128552372 ps
CPU time	14.33 seconds
Started	Feb 25 02:30:16 PM PST 24
Finished	Feb 25 02:30:30 PM PST 24
Peak memory	204072 kb
Host	smart-cd3e2dac-e1dc-4621-b8b8-2a77804e95cc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1949554809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1949554809
Directory	/workspace/41.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3894646629
Short name	T227
Test name
Test status
Simulation time	36105962571 ps
CPU time	211.91 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:34:02 PM PST 24
Peak memory	204876 kb
Host	smart-6fbb83bb-5dd5-4668-8150-8c0308572fea
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894646629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3894646629
Directory	/workspace/41.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1333786393
Short name	T176
Test name
Test status
Simulation time	125940543839 ps
CPU time	285.43 seconds
Started	Feb 25 02:30:20 PM PST 24
Finished	Feb 25 02:35:06 PM PST 24
Peak memory	204288 kb
Host	smart-3aa9bc27-e8dc-4c35-bc83-49eb502bba51
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1333786393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1333786393
Directory	/workspace/41.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.2393983390
Short name	T192
Test name
Test status
Simulation time	253764887 ps
CPU time	24.71 seconds
Started	Feb 25 02:30:21 PM PST 24
Finished	Feb 25 02:30:46 PM PST 24
Peak memory	204160 kb
Host	smart-18069f15-fcc1-4303-abfc-a36d7cf8448c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393983390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2393983390
Directory	/workspace/41.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_same_source.526616282
Short name	T537
Test name
Test status
Simulation time	2877873131 ps
CPU time	24.36 seconds
Started	Feb 25 02:30:27 PM PST 24
Finished	Feb 25 02:30:52 PM PST 24
Peak memory	203480 kb
Host	smart-5a000e02-a62b-480e-87cd-6dcabff74c0f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=526616282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.526616282
Directory	/workspace/41.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke.4280525832
Short name	T84
Test name
Test status
Simulation time	316710172 ps
CPU time	3.51 seconds
Started	Feb 25 02:30:14 PM PST 24
Finished	Feb 25 02:30:17 PM PST 24
Peak memory	203000 kb
Host	smart-91135085-e209-4f2f-8d3b-2c8d88bdc139
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4280525832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.4280525832
Directory	/workspace/41.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2635481938
Short name	T490
Test name
Test status
Simulation time	5363133366 ps
CPU time	30.26 seconds
Started	Feb 25 02:30:17 PM PST 24
Finished	Feb 25 02:30:47 PM PST 24
Peak memory	203108 kb
Host	smart-d860bbf0-e43a-4853-b160-a295044cccb4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635481938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2635481938
Directory	/workspace/41.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3385280479
Short name	T895
Test name
Test status
Simulation time	9829156189 ps
CPU time	38.79 seconds
Started	Feb 25 02:30:27 PM PST 24
Finished	Feb 25 02:31:05 PM PST 24
Peak memory	203404 kb
Host	smart-2663e9da-62a3-45df-beec-bb0e4895fee9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3385280479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3385280479
Directory	/workspace/41.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1256777204
Short name	T71
Test name
Test status
Simulation time	22934536 ps
CPU time	1.84 seconds
Started	Feb 25 02:30:24 PM PST 24
Finished	Feb 25 02:30:26 PM PST 24
Peak memory	203056 kb
Host	smart-28f01da8-58ef-4e80-ad76-8c6c422c8ce6
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256777204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1256777204
Directory	/workspace/41.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all.3568183207
Short name	T193
Test name
Test status
Simulation time	962075868 ps
CPU time	140.78 seconds
Started	Feb 25 02:30:17 PM PST 24
Finished	Feb 25 02:32:38 PM PST 24
Peak memory	208832 kb
Host	smart-f79c5ae7-3dae-4357-9fd6-8987eb26e728
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3568183207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3568183207
Directory	/workspace/41.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3309416859
Short name	T569
Test name
Test status
Simulation time	720022019 ps
CPU time	66.71 seconds
Started	Feb 25 02:30:16 PM PST 24
Finished	Feb 25 02:31:23 PM PST 24
Peak memory	205260 kb
Host	smart-098b8fe8-723c-4cca-a416-27f5a49163b6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3309416859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3309416859
Directory	/workspace/41.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1739271408
Short name	T395
Test name
Test status
Simulation time	464868453 ps
CPU time	212.73 seconds
Started	Feb 25 02:30:17 PM PST 24
Finished	Feb 25 02:33:50 PM PST 24
Peak memory	208704 kb
Host	smart-8f7d5175-4e8e-447e-b470-59d71f388bcf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1739271408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.1739271408
Directory	/workspace/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1313317786
Short name	T93
Test name
Test status
Simulation time	963210896 ps
CPU time	178.38 seconds
Started	Feb 25 02:30:25 PM PST 24
Finished	Feb 25 02:33:23 PM PST 24
Peak memory	219440 kb
Host	smart-4fa3c369-972c-409d-aced-a9fa4e7b7119
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1313317786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re set_error.1313317786
Directory	/workspace/41.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.744972772
Short name	T833
Test name
Test status
Simulation time	110559398 ps
CPU time	2.04 seconds
Started	Feb 25 02:30:16 PM PST 24
Finished	Feb 25 02:30:18 PM PST 24
Peak memory	203060 kb
Host	smart-c4811f28-78a7-408a-a38d-db5da2ec11f3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=744972772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.744972772
Directory	/workspace/41.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device.3099715898
Short name	T168
Test name
Test status
Simulation time	188902104 ps
CPU time	8.97 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:30:38 PM PST 24
Peak memory	203756 kb
Host	smart-05baa06d-388e-4b03-8850-e6407a4f6012
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3099715898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3099715898
Directory	/workspace/42.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.4258970975
Short name	T109
Test name
Test status
Simulation time	168457982522 ps
CPU time	468.51 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:38:18 PM PST 24
Peak memory	211324 kb
Host	smart-1b68f62a-3635-4472-88d3-8604328830c1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4258970975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.4258970975
Directory	/workspace/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.987024509
Short name	T497
Test name
Test status
Simulation time	183205543 ps
CPU time	6 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:30:37 PM PST 24
Peak memory	203048 kb
Host	smart-a6ac9913-f592-475c-8638-476421fe2907
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=987024509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.987024509
Directory	/workspace/42.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_error_random.1611048466
Short name	T208
Test name
Test status
Simulation time	868816825 ps
CPU time	11.35 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:30:40 PM PST 24
Peak memory	203080 kb
Host	smart-426710ff-4de4-4fc1-a7c4-48aae5be2e30
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1611048466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1611048466
Directory	/workspace/42.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random.2729506232
Short name	T635
Test name
Test status
Simulation time	72010654 ps
CPU time	6.37 seconds
Started	Feb 25 02:30:28 PM PST 24
Finished	Feb 25 02:30:35 PM PST 24
Peak memory	203060 kb
Host	smart-8b4c6ec1-7d43-46db-a3a9-94cf08f2c6e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2729506232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2729506232
Directory	/workspace/42.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.35548435
Short name	T301
Test name
Test status
Simulation time	11483191290 ps
CPU time	41.62 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:31:12 PM PST 24
Peak memory	204232 kb
Host	smart-cc458c20-9793-41ca-95a4-423c3a462ed5
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=35548435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.35548435
Directory	/workspace/42.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.3922957514
Short name	T651
Test name
Test status
Simulation time	9461795051 ps
CPU time	83.76 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:31:55 PM PST 24
Peak memory	204396 kb
Host	smart-0401b288-9976-4934-a96c-54107e69e393
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3922957514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3922957514
Directory	/workspace/42.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.302644242
Short name	T745
Test name
Test status
Simulation time	156185810 ps
CPU time	18.42 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:30:47 PM PST 24
Peak memory	204196 kb
Host	smart-5c943ded-25b2-4b7d-aaf0-563491c5dda3
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302644242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.302644242
Directory	/workspace/42.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_same_source.2798925489
Short name	T375
Test name
Test status
Simulation time	300778838 ps
CPU time	8.15 seconds
Started	Feb 25 02:30:27 PM PST 24
Finished	Feb 25 02:30:36 PM PST 24
Peak memory	203280 kb
Host	smart-3460e190-dacc-45be-b37f-cfdaaac090ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2798925489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2798925489
Directory	/workspace/42.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke.2795438041
Short name	T379
Test name
Test status
Simulation time	202562748 ps
CPU time	3.52 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:30:32 PM PST 24
Peak memory	203084 kb
Host	smart-dacc0431-2695-4d25-9492-886f9bfd4015
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2795438041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2795438041
Directory	/workspace/42.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3455922417
Short name	T588
Test name
Test status
Simulation time	5587815727 ps
CPU time	27.65 seconds
Started	Feb 25 02:30:17 PM PST 24
Finished	Feb 25 02:30:45 PM PST 24
Peak memory	203104 kb
Host	smart-546ce773-a1e4-4c9d-a3bb-55b465aacfbb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455922417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3455922417
Directory	/workspace/42.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3623216198
Short name	T149
Test name
Test status
Simulation time	5225959350 ps
CPU time	27.03 seconds
Started	Feb 25 02:30:28 PM PST 24
Finished	Feb 25 02:30:55 PM PST 24
Peak memory	203104 kb
Host	smart-cde2b9cc-736e-4579-b47a-c00158dbc474
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3623216198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3623216198
Directory	/workspace/42.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2997732291
Short name	T41
Test name
Test status
Simulation time	85737953 ps
CPU time	2.19 seconds
Started	Feb 25 02:30:19 PM PST 24
Finished	Feb 25 02:30:22 PM PST 24
Peak memory	203052 kb
Host	smart-e4498045-9994-489b-9afa-532b3b9aa77d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997732291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2997732291
Directory	/workspace/42.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all.3619953169
Short name	T85
Test name
Test status
Simulation time	1516941872 ps
CPU time	43.51 seconds
Started	Feb 25 02:30:28 PM PST 24
Finished	Feb 25 02:31:12 PM PST 24
Peak memory	205232 kb
Host	smart-4576eda6-c63b-48b4-93d5-9d5c3acdc8c3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3619953169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3619953169
Directory	/workspace/42.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3440734771
Short name	T661
Test name
Test status
Simulation time	2761782167 ps
CPU time	46.98 seconds
Started	Feb 25 02:30:28 PM PST 24
Finished	Feb 25 02:31:15 PM PST 24
Peak memory	204132 kb
Host	smart-2db08d22-82ed-41d6-af92-358ec84f0700
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3440734771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3440734771
Directory	/workspace/42.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1041219830
Short name	T167
Test name
Test status
Simulation time	321199036 ps
CPU time	84.82 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:31:55 PM PST 24
Peak memory	207584 kb
Host	smart-e2792424-a83f-4cf6-b298-eb27c44b3640
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1041219830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.1041219830
Directory	/workspace/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.161972217
Short name	T267
Test name
Test status
Simulation time	823399821 ps
CPU time	224.66 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:34:14 PM PST 24
Peak memory	210784 kb
Host	smart-cbe7b759-240e-48f4-b595-089f464c4a58
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=161972217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_res et_error.161972217
Directory	/workspace/42.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.3747438718
Short name	T682
Test name
Test status
Simulation time	254270652 ps
CPU time	10.02 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:30:40 PM PST 24
Peak memory	204348 kb
Host	smart-b8e1b637-bbad-44ad-95c3-fa5992b7ae29
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3747438718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3747438718
Directory	/workspace/42.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device.330126336
Short name	T836
Test name
Test status
Simulation time	2487913416 ps
CPU time	44.65 seconds
Started	Feb 25 02:30:27 PM PST 24
Finished	Feb 25 02:31:12 PM PST 24
Peak memory	205556 kb
Host	smart-2fe6ab12-2649-43a7-b1be-712af5f5720c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=330126336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.330126336
Directory	/workspace/43.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3181370673
Short name	T128
Test name
Test status
Simulation time	122712457245 ps
CPU time	666.61 seconds
Started	Feb 25 02:30:28 PM PST 24
Finished	Feb 25 02:41:35 PM PST 24
Peak memory	207156 kb
Host	smart-24fdd7fa-34a2-4775-aad1-d88d180ab10a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3181370673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3181370673
Directory	/workspace/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.2257761035
Short name	T754
Test name
Test status
Simulation time	98453462 ps
CPU time	6.92 seconds
Started	Feb 25 02:30:28 PM PST 24
Finished	Feb 25 02:30:35 PM PST 24
Peak memory	203248 kb
Host	smart-e18ac936-a406-4e10-a81f-1ef87e4aba94
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2257761035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.2257761035
Directory	/workspace/43.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_error_random.4200271796
Short name	T468
Test name
Test status
Simulation time	407669662 ps
CPU time	6.66 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:30:35 PM PST 24
Peak memory	203008 kb
Host	smart-3969f259-02e8-4499-9391-a2bf3fa56b06
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4200271796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.4200271796
Directory	/workspace/43.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random.1286087745
Short name	T214
Test name
Test status
Simulation time	181185861 ps
CPU time	20.66 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:30:51 PM PST 24
Peak memory	211240 kb
Host	smart-9c44401a-222c-40ee-860c-c6ea1df53f8c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1286087745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1286087745
Directory	/workspace/43.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.158415383
Short name	T138
Test name
Test status
Simulation time	40844808223 ps
CPU time	174.93 seconds
Started	Feb 25 02:30:26 PM PST 24
Finished	Feb 25 02:33:21 PM PST 24
Peak memory	211292 kb
Host	smart-4ed6a487-dbc5-4b5e-b550-7e3056923591
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=158415383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.158415383
Directory	/workspace/43.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3255689045
Short name	T799
Test name
Test status
Simulation time	3077294903 ps
CPU time	23.1 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:30:52 PM PST 24
Peak memory	203656 kb
Host	smart-8c3512bf-230d-481a-a72b-8403e7463be2
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3255689045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3255689045
Directory	/workspace/43.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1958835200
Short name	T294
Test name
Test status
Simulation time	55331536 ps
CPU time	3.46 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:30:33 PM PST 24
Peak memory	203440 kb
Host	smart-227f6a5a-e24a-4e99-abb3-fe53704a546f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958835200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1958835200
Directory	/workspace/43.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_same_source.1040002461
Short name	T599
Test name
Test status
Simulation time	558852192 ps
CPU time	15.86 seconds
Started	Feb 25 02:30:27 PM PST 24
Finished	Feb 25 02:30:44 PM PST 24
Peak memory	203004 kb
Host	smart-db07297d-f970-47d6-82bd-d507ef0b1fd5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1040002461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1040002461
Directory	/workspace/43.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke.3961162412
Short name	T226
Test name
Test status
Simulation time	116037239 ps
CPU time	3.37 seconds
Started	Feb 25 02:30:28 PM PST 24
Finished	Feb 25 02:30:32 PM PST 24
Peak memory	203076 kb
Host	smart-95e90623-bcd1-4f0d-a015-986975c96126
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3961162412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3961162412
Directory	/workspace/43.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.686770217
Short name	T520
Test name
Test status
Simulation time	7633489945 ps
CPU time	34.53 seconds
Started	Feb 25 02:30:27 PM PST 24
Finished	Feb 25 02:31:02 PM PST 24
Peak memory	203124 kb
Host	smart-dfbc6057-2ad0-4ab0-bad9-4c87bd20e906
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=686770217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.686770217
Directory	/workspace/43.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.3850579170
Short name	T856
Test name
Test status
Simulation time	4973293729 ps
CPU time	30.45 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:30:59 PM PST 24
Peak memory	203104 kb
Host	smart-e7c019b0-f626-40c6-92c0-3e4ba4db4f1e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3850579170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3850579170
Directory	/workspace/43.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.3764873636
Short name	T443
Test name
Test status
Simulation time	46107403 ps
CPU time	2.39 seconds
Started	Feb 25 02:30:28 PM PST 24
Finished	Feb 25 02:30:31 PM PST 24
Peak memory	203060 kb
Host	smart-f12cf87f-e4ea-4145-a373-ee72bd88f161
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764873636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.3764873636
Directory	/workspace/43.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all.1655565634
Short name	T186
Test name
Test status
Simulation time	403448343 ps
CPU time	64.68 seconds
Started	Feb 25 02:30:27 PM PST 24
Finished	Feb 25 02:31:32 PM PST 24
Peak memory	207420 kb
Host	smart-d1c7cd90-e3c2-45d4-9adf-a1d38d2d9d4f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1655565634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1655565634
Directory	/workspace/43.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.1814547320
Short name	T800
Test name
Test status
Simulation time	289801977 ps
CPU time	22.27 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:30:53 PM PST 24
Peak memory	204128 kb
Host	smart-c1f76310-0afe-43eb-954f-f7533304ed92
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1814547320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1814547320
Directory	/workspace/43.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.4223103014
Short name	T830
Test name
Test status
Simulation time	529815075 ps
CPU time	93.19 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:32:02 PM PST 24
Peak memory	207680 kb
Host	smart-98c36dec-f8ea-48b4-ba62-6df6e0712a54
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4223103014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.4223103014
Directory	/workspace/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3429035551
Short name	T373
Test name
Test status
Simulation time	1835984228 ps
CPU time	384.25 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:36:54 PM PST 24
Peak memory	210552 kb
Host	smart-8ea75660-00bd-4825-abb6-c251c5d8c767
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3429035551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.3429035551
Directory	/workspace/43.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1276169155
Short name	T203
Test name
Test status
Simulation time	852724567 ps
CPU time	20.46 seconds
Started	Feb 25 02:30:28 PM PST 24
Finished	Feb 25 02:30:49 PM PST 24
Peak memory	204184 kb
Host	smart-5277fa26-8a59-4867-8d2c-0e7d2349213b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1276169155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1276169155
Directory	/workspace/43.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device.2868551650
Short name	T45
Test name
Test status
Simulation time	2599148091 ps
CPU time	35.11 seconds
Started	Feb 25 02:30:38 PM PST 24
Finished	Feb 25 02:31:14 PM PST 24
Peak memory	205356 kb
Host	smart-083db343-3cc3-4e6b-a081-00d74e9a22ad
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2868551650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.2868551650
Directory	/workspace/44.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.354918175
Short name	T356
Test name
Test status
Simulation time	43617438548 ps
CPU time	266.17 seconds
Started	Feb 25 02:30:42 PM PST 24
Finished	Feb 25 02:35:08 PM PST 24
Peak memory	211304 kb
Host	smart-8110a163-e36e-4e7d-9a9c-2f51610de15d
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=354918175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slo w_rsp.354918175
Directory	/workspace/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.521747842
Short name	T311
Test name
Test status
Simulation time	301790134 ps
CPU time	4.18 seconds
Started	Feb 25 02:30:39 PM PST 24
Finished	Feb 25 02:30:43 PM PST 24
Peak memory	203052 kb
Host	smart-12ea8bb1-2a61-4a63-b60f-a76590434afd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=521747842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.521747842
Directory	/workspace/44.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_error_random.3434925984
Short name	T735
Test name
Test status
Simulation time	353601791 ps
CPU time	22.38 seconds
Started	Feb 25 02:30:40 PM PST 24
Finished	Feb 25 02:31:03 PM PST 24
Peak memory	203140 kb
Host	smart-bb83f5ff-3878-4068-8118-f5ffd40d36e2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3434925984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3434925984
Directory	/workspace/44.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random.2051990961
Short name	T900
Test name
Test status
Simulation time	2545435699 ps
CPU time	30.77 seconds
Started	Feb 25 02:30:36 PM PST 24
Finished	Feb 25 02:31:07 PM PST 24
Peak memory	204232 kb
Host	smart-b911f6b4-5825-406d-a7cb-968d25c6c763
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2051990961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2051990961
Directory	/workspace/44.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.1951420324
Short name	T578
Test name
Test status
Simulation time	80893046221 ps
CPU time	185.53 seconds
Started	Feb 25 02:30:39 PM PST 24
Finished	Feb 25 02:33:45 PM PST 24
Peak memory	204704 kb
Host	smart-38082277-37ad-42f3-95e5-57b48b89852f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951420324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1951420324
Directory	/workspace/44.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1953013367
Short name	T177
Test name
Test status
Simulation time	20019963473 ps
CPU time	171.41 seconds
Started	Feb 25 02:30:43 PM PST 24
Finished	Feb 25 02:33:35 PM PST 24
Peak memory	204228 kb
Host	smart-371425fa-25a6-480a-a2c5-32125095f4c4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1953013367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1953013367
Directory	/workspace/44.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.2257806549
Short name	T549
Test name
Test status
Simulation time	52359448 ps
CPU time	8.75 seconds
Started	Feb 25 02:30:40 PM PST 24
Finished	Feb 25 02:30:50 PM PST 24
Peak memory	204188 kb
Host	smart-039ea7ff-d4aa-45a8-9f3c-fd3a4fb2d1b2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257806549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.2257806549
Directory	/workspace/44.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_same_source.4070780893
Short name	T470
Test name
Test status
Simulation time	3631090301 ps
CPU time	22.78 seconds
Started	Feb 25 02:30:38 PM PST 24
Finished	Feb 25 02:31:02 PM PST 24
Peak memory	203128 kb
Host	smart-0020240c-d7a5-4dd9-9b6e-822b7fa14acb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4070780893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.4070780893
Directory	/workspace/44.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke.2002768568
Short name	T590
Test name
Test status
Simulation time	24033047 ps
CPU time	2.32 seconds
Started	Feb 25 02:30:29 PM PST 24
Finished	Feb 25 02:30:31 PM PST 24
Peak memory	203080 kb
Host	smart-69d90a35-03d1-4c6b-af76-cccfbe70aa42
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2002768568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2002768568
Directory	/workspace/44.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.596553949
Short name	T440
Test name
Test status
Simulation time	7463360056 ps
CPU time	35.14 seconds
Started	Feb 25 02:30:38 PM PST 24
Finished	Feb 25 02:31:14 PM PST 24
Peak memory	202996 kb
Host	smart-6ef727ea-f519-452f-b78a-a82459461b7f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=596553949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.596553949
Directory	/workspace/44.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.243978008
Short name	T707
Test name
Test status
Simulation time	15084054952 ps
CPU time	35.14 seconds
Started	Feb 25 02:30:37 PM PST 24
Finished	Feb 25 02:31:12 PM PST 24
Peak memory	203028 kb
Host	smart-c7b4c501-834e-416e-a8da-20548d40fcc1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=243978008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.243978008
Directory	/workspace/44.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.716415805
Short name	T603
Test name
Test status
Simulation time	94131196 ps
CPU time	2.61 seconds
Started	Feb 25 02:30:30 PM PST 24
Finished	Feb 25 02:30:33 PM PST 24
Peak memory	203032 kb
Host	smart-2c43ea37-9403-4815-b1ae-98b7c5d22492
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716415805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.716415805
Directory	/workspace/44.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all.3899980497
Short name	T452
Test name
Test status
Simulation time	605861821 ps
CPU time	29.63 seconds
Started	Feb 25 02:30:41 PM PST 24
Finished	Feb 25 02:31:11 PM PST 24
Peak memory	205568 kb
Host	smart-3d347716-d24c-40ed-acc8-b9d2bee74872
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3899980497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3899980497
Directory	/workspace/44.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2418304385
Short name	T416
Test name
Test status
Simulation time	263709904 ps
CPU time	7.35 seconds
Started	Feb 25 02:30:41 PM PST 24
Finished	Feb 25 02:30:49 PM PST 24
Peak memory	202980 kb
Host	smart-9f988ab6-0938-4418-8801-d873834c7c2e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2418304385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2418304385
Directory	/workspace/44.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1159285178
Short name	T137
Test name
Test status
Simulation time	3582322095 ps
CPU time	269.04 seconds
Started	Feb 25 02:30:39 PM PST 24
Finished	Feb 25 02:35:08 PM PST 24
Peak memory	208212 kb
Host	smart-00c33b49-aaee-4132-bc36-06c73821db0f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1159285178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.1159285178
Directory	/workspace/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2796636858
Short name	T679
Test name
Test status
Simulation time	614372399 ps
CPU time	169.59 seconds
Started	Feb 25 02:30:42 PM PST 24
Finished	Feb 25 02:33:31 PM PST 24
Peak memory	210948 kb
Host	smart-ba3e6c54-f90c-4f77-820c-62f783c813ab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2796636858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re set_error.2796636858
Directory	/workspace/44.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2454905978
Short name	T634
Test name
Test status
Simulation time	815919665 ps
CPU time	22.81 seconds
Started	Feb 25 02:30:38 PM PST 24
Finished	Feb 25 02:31:01 PM PST 24
Peak memory	204572 kb
Host	smart-d523c7ec-f219-4dad-bce2-e2dbb5503a93
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2454905978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2454905978
Directory	/workspace/44.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device.3429325405
Short name	T875
Test name
Test status
Simulation time	286119747 ps
CPU time	14.86 seconds
Started	Feb 25 02:30:41 PM PST 24
Finished	Feb 25 02:30:56 PM PST 24
Peak memory	211220 kb
Host	smart-16c7cb64-ddba-43f2-895b-fa6a98eab5a7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3429325405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3429325405
Directory	/workspace/45.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1632604882
Short name	T749
Test name
Test status
Simulation time	46497773150 ps
CPU time	217.76 seconds
Started	Feb 25 02:30:39 PM PST 24
Finished	Feb 25 02:34:17 PM PST 24
Peak memory	205816 kb
Host	smart-ebfb75db-9544-4b65-a7f1-53a6b8f9c2af
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1632604882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.1632604882
Directory	/workspace/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3063836115
Short name	T883
Test name
Test status
Simulation time	1619061187 ps
CPU time	12.48 seconds
Started	Feb 25 02:30:50 PM PST 24
Finished	Feb 25 02:31:03 PM PST 24
Peak memory	203064 kb
Host	smart-8c0d573b-aa86-4d2b-b791-2dfdfb0040e5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3063836115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3063836115
Directory	/workspace/45.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_error_random.1349023748
Short name	T641
Test name
Test status
Simulation time	91200283 ps
CPU time	7.06 seconds
Started	Feb 25 02:30:40 PM PST 24
Finished	Feb 25 02:30:48 PM PST 24
Peak memory	202988 kb
Host	smart-b20c8274-3872-4650-b137-a9b1de57e5bc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1349023748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1349023748
Directory	/workspace/45.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random.2880417459
Short name	T706
Test name
Test status
Simulation time	216162099 ps
CPU time	9.4 seconds
Started	Feb 25 02:30:40 PM PST 24
Finished	Feb 25 02:30:49 PM PST 24
Peak memory	211216 kb
Host	smart-91a5be85-0ec5-497b-9432-88997250a681
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2880417459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2880417459
Directory	/workspace/45.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.4243693520
Short name	T518
Test name
Test status
Simulation time	21275337925 ps
CPU time	126.78 seconds
Started	Feb 25 02:30:38 PM PST 24
Finished	Feb 25 02:32:45 PM PST 24
Peak memory	211304 kb
Host	smart-04a41ee4-2441-4a0b-b200-fb5b77fd88b6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243693520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.4243693520
Directory	/workspace/45.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3794503586
Short name	T415
Test name
Test status
Simulation time	31621850728 ps
CPU time	200.37 seconds
Started	Feb 25 02:30:37 PM PST 24
Finished	Feb 25 02:33:58 PM PST 24
Peak memory	204684 kb
Host	smart-0a5b5f8c-5e32-4a63-a63e-e6f91090b151
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3794503586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3794503586
Directory	/workspace/45.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3699162273
Short name	T318
Test name
Test status
Simulation time	169615574 ps
CPU time	13.13 seconds
Started	Feb 25 02:30:37 PM PST 24
Finished	Feb 25 02:30:51 PM PST 24
Peak memory	204104 kb
Host	smart-e0d28930-ac0e-4de1-adbe-9537f15b8312
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699162273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3699162273
Directory	/workspace/45.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_same_source.2855060477
Short name	T851
Test name
Test status
Simulation time	102934882 ps
CPU time	5.15 seconds
Started	Feb 25 02:30:41 PM PST 24
Finished	Feb 25 02:30:46 PM PST 24
Peak memory	203060 kb
Host	smart-e11a6a9e-c4c1-45a3-9144-014a8e7fbc7b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2855060477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2855060477
Directory	/workspace/45.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke.42126547
Short name	T249
Test name
Test status
Simulation time	128690774 ps
CPU time	4 seconds
Started	Feb 25 02:30:38 PM PST 24
Finished	Feb 25 02:30:43 PM PST 24
Peak memory	202952 kb
Host	smart-e55d5308-fb43-4cd4-9731-145c82f48c91
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=42126547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.42126547
Directory	/workspace/45.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.101698641
Short name	T672
Test name
Test status
Simulation time	12668051416 ps
CPU time	34.13 seconds
Started	Feb 25 02:30:39 PM PST 24
Finished	Feb 25 02:31:14 PM PST 24
Peak memory	202996 kb
Host	smart-4d00a929-4858-41e5-8f2c-89a6ffd7b1ba
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=101698641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.101698641
Directory	/workspace/45.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3125394733
Short name	T550
Test name
Test status
Simulation time	5803500166 ps
CPU time	31.67 seconds
Started	Feb 25 02:30:41 PM PST 24
Finished	Feb 25 02:31:13 PM PST 24
Peak memory	203120 kb
Host	smart-af9148eb-9f0c-4da2-9a17-4c9abaf1fcd1
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3125394733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3125394733
Directory	/workspace/45.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.162687643
Short name	T69
Test name
Test status
Simulation time	23509638 ps
CPU time	2.07 seconds
Started	Feb 25 02:30:41 PM PST 24
Finished	Feb 25 02:30:43 PM PST 24
Peak memory	203044 kb
Host	smart-c4bf82df-cc46-46f4-add5-4ee399487758
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162687643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.162687643
Directory	/workspace/45.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all.3339430645
Short name	T516
Test name
Test status
Simulation time	2426865225 ps
CPU time	118.53 seconds
Started	Feb 25 02:30:54 PM PST 24
Finished	Feb 25 02:32:52 PM PST 24
Peak memory	206308 kb
Host	smart-a445f032-9a07-4cec-8ba8-2767f317b140
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3339430645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3339430645
Directory	/workspace/45.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3576127457
Short name	T640
Test name
Test status
Simulation time	5086254763 ps
CPU time	56.8 seconds
Started	Feb 25 02:30:51 PM PST 24
Finished	Feb 25 02:31:48 PM PST 24
Peak memory	205772 kb
Host	smart-5aab620c-81fb-4ebf-8e34-99e50e4fc136
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3576127457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3576127457
Directory	/workspace/45.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1382950218
Short name	T204
Test name
Test status
Simulation time	3057193777 ps
CPU time	590.1 seconds
Started	Feb 25 02:30:51 PM PST 24
Finished	Feb 25 02:40:42 PM PST 24
Peak memory	219500 kb
Host	smart-64aa474f-a70b-4227-bc01-c08c03942562
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1382950218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.1382950218
Directory	/workspace/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2697740594
Short name	T533
Test name
Test status
Simulation time	779915209 ps
CPU time	173.95 seconds
Started	Feb 25 02:30:54 PM PST 24
Finished	Feb 25 02:33:48 PM PST 24
Peak memory	209788 kb
Host	smart-fee3a4b2-56b5-4afa-8ee9-e6a256e4c513
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2697740594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.2697740594
Directory	/workspace/45.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3002390506
Short name	T411
Test name
Test status
Simulation time	67486790 ps
CPU time	10.78 seconds
Started	Feb 25 02:30:37 PM PST 24
Finished	Feb 25 02:30:48 PM PST 24
Peak memory	204128 kb
Host	smart-e4390165-8b48-4225-959d-d4961fa70019
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3002390506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3002390506
Directory	/workspace/45.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device.2428031457
Short name	T370
Test name
Test status
Simulation time	403858229 ps
CPU time	37.17 seconds
Started	Feb 25 02:30:51 PM PST 24
Finished	Feb 25 02:31:29 PM PST 24
Peak memory	211204 kb
Host	smart-9b712440-d010-4233-a5c8-10b96fdd631d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2428031457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.2428031457
Directory	/workspace/46.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2688334779
Short name	T733
Test name
Test status
Simulation time	35708256215 ps
CPU time	238.26 seconds
Started	Feb 25 02:30:53 PM PST 24
Finished	Feb 25 02:34:51 PM PST 24
Peak memory	211304 kb
Host	smart-1d4805cf-03e9-41b5-b9d4-018d082a029f
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2688334779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.2688334779
Directory	/workspace/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2283122179
Short name	T254
Test name
Test status
Simulation time	2732370805 ps
CPU time	16 seconds
Started	Feb 25 02:30:51 PM PST 24
Finished	Feb 25 02:31:07 PM PST 24
Peak memory	203176 kb
Host	smart-b67b4326-f194-4158-9f7f-7f839bef58f5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2283122179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2283122179
Directory	/workspace/46.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_error_random.1045454765
Short name	T503
Test name
Test status
Simulation time	865040663 ps
CPU time	28.35 seconds
Started	Feb 25 02:30:50 PM PST 24
Finished	Feb 25 02:31:19 PM PST 24
Peak memory	203040 kb
Host	smart-2cf51f17-6cfa-47f8-b170-d108c5229a6f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1045454765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1045454765
Directory	/workspace/46.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random.2341372682
Short name	T459
Test name
Test status
Simulation time	338083683 ps
CPU time	12.66 seconds
Started	Feb 25 02:30:54 PM PST 24
Finished	Feb 25 02:31:07 PM PST 24
Peak memory	204168 kb
Host	smart-37181073-b2d5-4028-acc1-532269348454
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2341372682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2341372682
Directory	/workspace/46.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.1601798732
Short name	T828
Test name
Test status
Simulation time	85520684495 ps
CPU time	203.74 seconds
Started	Feb 25 02:30:50 PM PST 24
Finished	Feb 25 02:34:14 PM PST 24
Peak memory	204340 kb
Host	smart-5a4959ea-8839-4f39-b3ea-664e8be278e3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601798732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1601798732
Directory	/workspace/46.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.2419036370
Short name	T538
Test name
Test status
Simulation time	7190281782 ps
CPU time	44.02 seconds
Started	Feb 25 02:30:56 PM PST 24
Finished	Feb 25 02:31:40 PM PST 24
Peak memory	204292 kb
Host	smart-e4ec0d11-b210-4195-8f6a-bfa90684b2f6
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2419036370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2419036370
Directory	/workspace/46.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2985202400
Short name	T513
Test name
Test status
Simulation time	105932502 ps
CPU time	15.52 seconds
Started	Feb 25 02:30:53 PM PST 24
Finished	Feb 25 02:31:09 PM PST 24
Peak memory	204160 kb
Host	smart-9489a543-74af-4b99-9c56-9f8d9b37f87a
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985202400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2985202400
Directory	/workspace/46.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_same_source.3335906498
Short name	T17
Test name
Test status
Simulation time	85329365 ps
CPU time	5.29 seconds
Started	Feb 25 02:30:50 PM PST 24
Finished	Feb 25 02:30:55 PM PST 24
Peak memory	203044 kb
Host	smart-34e04064-14cb-442a-b3d3-d76427da17fc
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3335906498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3335906498
Directory	/workspace/46.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke.3730221645
Short name	T479
Test name
Test status
Simulation time	162318777 ps
CPU time	3.47 seconds
Started	Feb 25 02:30:51 PM PST 24
Finished	Feb 25 02:30:55 PM PST 24
Peak memory	203072 kb
Host	smart-72fc3d6f-3544-48c6-8d64-e2736011d21a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3730221645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3730221645
Directory	/workspace/46.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1248820677
Short name	T228
Test name
Test status
Simulation time	5997730754 ps
CPU time	25.13 seconds
Started	Feb 25 02:30:51 PM PST 24
Finished	Feb 25 02:31:17 PM PST 24
Peak memory	203116 kb
Host	smart-df9a0e03-6fbf-4cea-a24e-74a78a45f756
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248820677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1248820677
Directory	/workspace/46.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2781669934
Short name	T291
Test name
Test status
Simulation time	18019840523 ps
CPU time	39.14 seconds
Started	Feb 25 02:30:52 PM PST 24
Finished	Feb 25 02:31:31 PM PST 24
Peak memory	203108 kb
Host	smart-86f412e6-41ce-4dfb-8613-2ba43469a215
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2781669934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2781669934
Directory	/workspace/46.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3169273414
Short name	T384
Test name
Test status
Simulation time	29250042 ps
CPU time	2.43 seconds
Started	Feb 25 02:30:54 PM PST 24
Finished	Feb 25 02:30:57 PM PST 24
Peak memory	203056 kb
Host	smart-3c080a6d-3e1c-4d1f-ab97-66c0582908cf
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169273414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3169273414
Directory	/workspace/46.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all.3303999261
Short name	T605
Test name
Test status
Simulation time	1925213482 ps
CPU time	237.26 seconds
Started	Feb 25 02:30:51 PM PST 24
Finished	Feb 25 02:34:49 PM PST 24
Peak memory	211156 kb
Host	smart-409d825c-7404-4739-a3fc-dd03a3bbb1ae
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3303999261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3303999261
Directory	/workspace/46.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2080454362
Short name	T702
Test name
Test status
Simulation time	5115262345 ps
CPU time	114.73 seconds
Started	Feb 25 02:30:52 PM PST 24
Finished	Feb 25 02:32:47 PM PST 24
Peak memory	206464 kb
Host	smart-c82cad74-fdc7-4bdc-8fb7-88325d0f05d2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2080454362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2080454362
Directory	/workspace/46.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3853436800
Short name	T154
Test name
Test status
Simulation time	1169255403 ps
CPU time	208.49 seconds
Started	Feb 25 02:30:52 PM PST 24
Finished	Feb 25 02:34:21 PM PST 24
Peak memory	208244 kb
Host	smart-e21c1389-ff23-491b-9adc-659464b30789
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3853436800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_ran d_reset.3853436800
Directory	/workspace/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1810741814
Short name	T860
Test name
Test status
Simulation time	357670814 ps
CPU time	103.54 seconds
Started	Feb 25 02:30:51 PM PST 24
Finished	Feb 25 02:32:34 PM PST 24
Peak memory	208840 kb
Host	smart-15adcfdb-94b6-4179-ab32-e9fdc3bed772
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1810741814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.1810741814
Directory	/workspace/46.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1102550784
Short name	T250
Test name
Test status
Simulation time	57426771 ps
CPU time	2.65 seconds
Started	Feb 25 02:30:50 PM PST 24
Finished	Feb 25 02:30:53 PM PST 24
Peak memory	211172 kb
Host	smart-9c964137-16e8-42c3-b56c-c1f186133039
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1102550784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1102550784
Directory	/workspace/46.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device.323583451
Short name	T52
Test name
Test status
Simulation time	60035749 ps
CPU time	7.48 seconds
Started	Feb 25 02:31:01 PM PST 24
Finished	Feb 25 02:31:10 PM PST 24
Peak memory	203372 kb
Host	smart-40ee2c54-0134-4460-87d3-560d71d99d1b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=323583451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.323583451
Directory	/workspace/47.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2984399814
Short name	T99
Test name
Test status
Simulation time	38142703591 ps
CPU time	299.68 seconds
Started	Feb 25 02:31:01 PM PST 24
Finished	Feb 25 02:36:02 PM PST 24
Peak memory	206116 kb
Host	smart-0b20cf46-83e1-46fe-afe6-4d1bc9e90ec0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2984399814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.2984399814
Directory	/workspace/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.2268248255
Short name	T303
Test name
Test status
Simulation time	114036392 ps
CPU time	11.57 seconds
Started	Feb 25 02:31:04 PM PST 24
Finished	Feb 25 02:31:16 PM PST 24
Peak memory	203036 kb
Host	smart-b2e609ce-2409-4677-b0f0-be10edc833c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2268248255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2268248255
Directory	/workspace/47.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_error_random.3263531825
Short name	T705
Test name
Test status
Simulation time	827489297 ps
CPU time	26.08 seconds
Started	Feb 25 02:31:02 PM PST 24
Finished	Feb 25 02:31:29 PM PST 24
Peak memory	203052 kb
Host	smart-7e184e67-12ab-4475-82da-ca73463c32be
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3263531825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3263531825
Directory	/workspace/47.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random.377934133
Short name	T15
Test name
Test status
Simulation time	140731282 ps
CPU time	9.39 seconds
Started	Feb 25 02:31:03 PM PST 24
Finished	Feb 25 02:31:13 PM PST 24
Peak memory	204140 kb
Host	smart-6db8e71a-c8ee-46bb-9e84-fe5e1355835c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=377934133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.377934133
Directory	/workspace/47.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1405423770
Short name	T489
Test name
Test status
Simulation time	9635247279 ps
CPU time	40.49 seconds
Started	Feb 25 02:31:02 PM PST 24
Finished	Feb 25 02:31:43 PM PST 24
Peak memory	211352 kb
Host	smart-16de074a-faea-48ff-991e-81769f49332b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405423770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1405423770
Directory	/workspace/47.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3467456195
Short name	T106
Test name
Test status
Simulation time	58889017507 ps
CPU time	200.35 seconds
Started	Feb 25 02:31:03 PM PST 24
Finished	Feb 25 02:34:24 PM PST 24
Peak memory	204668 kb
Host	smart-3d383b2a-f6e4-4100-a7ec-090fcba99fbd
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3467456195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3467456195
Directory	/workspace/47.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.2974894851
Short name	T680
Test name
Test status
Simulation time	37904637 ps
CPU time	3.45 seconds
Started	Feb 25 02:31:02 PM PST 24
Finished	Feb 25 02:31:06 PM PST 24
Peak memory	203080 kb
Host	smart-b9b7b746-33f4-4ed0-a7b0-43f881ccea85
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974894851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2974894851
Directory	/workspace/47.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_same_source.3918469330
Short name	T804
Test name
Test status
Simulation time	535119224 ps
CPU time	13.42 seconds
Started	Feb 25 02:31:01 PM PST 24
Finished	Feb 25 02:31:15 PM PST 24
Peak memory	203048 kb
Host	smart-920a1731-cc13-4145-9024-8ceacddc8540
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3918469330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3918469330
Directory	/workspace/47.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke.3376198423
Short name	T347
Test name
Test status
Simulation time	293171147 ps
CPU time	3.41 seconds
Started	Feb 25 02:30:50 PM PST 24
Finished	Feb 25 02:30:54 PM PST 24
Peak memory	203088 kb
Host	smart-db30ac32-9c93-41e4-a3bc-98ab0f67c74a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3376198423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3376198423
Directory	/workspace/47.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1423417150
Short name	T465
Test name
Test status
Simulation time	10726481929 ps
CPU time	32.42 seconds
Started	Feb 25 02:30:54 PM PST 24
Finished	Feb 25 02:31:27 PM PST 24
Peak memory	203108 kb
Host	smart-a05d7b41-c56d-4079-832d-d54e75520b51
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423417150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1423417150
Directory	/workspace/47.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3463585047
Short name	T421
Test name
Test status
Simulation time	18077225953 ps
CPU time	34.5 seconds
Started	Feb 25 02:30:50 PM PST 24
Finished	Feb 25 02:31:24 PM PST 24
Peak memory	203092 kb
Host	smart-85e5e46e-ac81-4a2c-bdd6-68c8b94fccb4
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3463585047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3463585047
Directory	/workspace/47.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1257363702
Short name	T664
Test name
Test status
Simulation time	37524179 ps
CPU time	2.38 seconds
Started	Feb 25 02:30:52 PM PST 24
Finished	Feb 25 02:30:54 PM PST 24
Peak memory	203056 kb
Host	smart-a3e3086b-0a7a-4398-89e9-45d6608dcd2c
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257363702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1257363702
Directory	/workspace/47.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all.353472615
Short name	T508
Test name
Test status
Simulation time	9384330288 ps
CPU time	194.99 seconds
Started	Feb 25 02:31:02 PM PST 24
Finished	Feb 25 02:34:18 PM PST 24
Peak memory	211292 kb
Host	smart-7274dbd8-1cb0-45a5-854d-046aaa6bb4c2
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=353472615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.353472615
Directory	/workspace/47.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.793236520
Short name	T515
Test name
Test status
Simulation time	2652614805 ps
CPU time	44.02 seconds
Started	Feb 25 02:31:02 PM PST 24
Finished	Feb 25 02:31:47 PM PST 24
Peak memory	204152 kb
Host	smart-e567258b-2584-4b15-baae-48cf62a30c4e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=793236520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.793236520
Directory	/workspace/47.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3341169470
Short name	T466
Test name
Test status
Simulation time	4508390831 ps
CPU time	246.33 seconds
Started	Feb 25 02:31:00 PM PST 24
Finished	Feb 25 02:35:07 PM PST 24
Peak memory	211116 kb
Host	smart-e39bb8be-4ce3-46d3-98e2-f4257ea47407
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3341169470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.3341169470
Directory	/workspace/47.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2100641733
Short name	T534
Test name
Test status
Simulation time	278911767 ps
CPU time	14.83 seconds
Started	Feb 25 02:31:03 PM PST 24
Finished	Feb 25 02:31:18 PM PST 24
Peak memory	204264 kb
Host	smart-a807acac-0aa6-4f62-af98-3128c2ecfc85
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2100641733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2100641733
Directory	/workspace/47.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device.4122880023
Short name	T201
Test name
Test status
Simulation time	436260636 ps
CPU time	10.15 seconds
Started	Feb 25 02:31:03 PM PST 24
Finished	Feb 25 02:31:14 PM PST 24
Peak memory	204564 kb
Host	smart-07cdeac6-75b7-495b-a4ef-77130aceabcd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4122880023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.4122880023
Directory	/workspace/48.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.1921271294
Short name	T432
Test name
Test status
Simulation time	106050143123 ps
CPU time	335.29 seconds
Started	Feb 25 02:31:05 PM PST 24
Finished	Feb 25 02:36:40 PM PST 24
Peak memory	205432 kb
Host	smart-3d28d19e-7b0a-4a6d-972a-0e97236d2c61
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1921271294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.1921271294
Directory	/workspace/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3109404707
Short name	T671
Test name
Test status
Simulation time	172033720 ps
CPU time	16.74 seconds
Started	Feb 25 02:31:14 PM PST 24
Finished	Feb 25 02:31:31 PM PST 24
Peak memory	203056 kb
Host	smart-fbce3d36-b3e6-4b2b-81b5-332d9a59bd44
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3109404707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3109404707
Directory	/workspace/48.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_error_random.3320579739
Short name	T808
Test name
Test status
Simulation time	852901910 ps
CPU time	33.01 seconds
Started	Feb 25 02:31:04 PM PST 24
Finished	Feb 25 02:31:38 PM PST 24
Peak memory	203088 kb
Host	smart-96e9b8f0-4ef9-47b3-8251-d254c59a4e79
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3320579739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3320579739
Directory	/workspace/48.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random.2249186323
Short name	T541
Test name
Test status
Simulation time	1588215260 ps
CPU time	19.6 seconds
Started	Feb 25 02:31:02 PM PST 24
Finished	Feb 25 02:31:23 PM PST 24
Peak memory	204016 kb
Host	smart-6a210018-44e0-41c0-a276-185362107b76
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2249186323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2249186323
Directory	/workspace/48.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.568720164
Short name	T827
Test name
Test status
Simulation time	37429082979 ps
CPU time	221.75 seconds
Started	Feb 25 02:31:01 PM PST 24
Finished	Feb 25 02:34:43 PM PST 24
Peak memory	204264 kb
Host	smart-3cc48cd2-d5e5-4eaa-84e4-302d0a22894a
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=568720164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.568720164
Directory	/workspace/48.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2767248030
Short name	T777
Test name
Test status
Simulation time	31635135598 ps
CPU time	185.15 seconds
Started	Feb 25 02:31:03 PM PST 24
Finished	Feb 25 02:34:09 PM PST 24
Peak memory	211308 kb
Host	smart-9b26fef0-acf0-4082-9dc1-6075c3fb92e3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2767248030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2767248030
Directory	/workspace/48.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.2724440351
Short name	T403
Test name
Test status
Simulation time	137405240 ps
CPU time	6.97 seconds
Started	Feb 25 02:31:05 PM PST 24
Finished	Feb 25 02:31:12 PM PST 24
Peak memory	204180 kb
Host	smart-5b90fafe-a5fc-4832-a94e-b69015307e1f
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724440351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.2724440351
Directory	/workspace/48.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_same_source.2472850165
Short name	T464
Test name
Test status
Simulation time	1864257518 ps
CPU time	14.37 seconds
Started	Feb 25 02:31:01 PM PST 24
Finished	Feb 25 02:31:16 PM PST 24
Peak memory	203576 kb
Host	smart-e1e1105c-e884-41f2-a712-de154299a3a4
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2472850165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2472850165
Directory	/workspace/48.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke.1931004543
Short name	T555
Test name
Test status
Simulation time	25221958 ps
CPU time	2.4 seconds
Started	Feb 25 02:31:03 PM PST 24
Finished	Feb 25 02:31:05 PM PST 24
Peak memory	203064 kb
Host	smart-837a3778-d585-41bc-8144-435eea52ea04
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1931004543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1931004543
Directory	/workspace/48.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1737007016
Short name	T687
Test name
Test status
Simulation time	11604255788 ps
CPU time	32.25 seconds
Started	Feb 25 02:31:02 PM PST 24
Finished	Feb 25 02:31:35 PM PST 24
Peak memory	203120 kb
Host	smart-26c96404-c185-4a37-97a1-be31f1ce6c8e
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737007016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1737007016
Directory	/workspace/48.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3486073579
Short name	T273
Test name
Test status
Simulation time	10127661672 ps
CPU time	32.89 seconds
Started	Feb 25 02:31:05 PM PST 24
Finished	Feb 25 02:31:38 PM PST 24
Peak memory	203120 kb
Host	smart-dc409669-114e-4c9e-adeb-3b54a575d575
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3486073579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3486073579
Directory	/workspace/48.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1522126933
Short name	T288
Test name
Test status
Simulation time	50428750 ps
CPU time	2.35 seconds
Started	Feb 25 02:31:05 PM PST 24
Finished	Feb 25 02:31:08 PM PST 24
Peak memory	203060 kb
Host	smart-d9452e96-5822-45d5-a6e5-84e1f1c70224
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522126933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1522126933
Directory	/workspace/48.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all.3904394826
Short name	T188
Test name
Test status
Simulation time	1429871346 ps
CPU time	144.05 seconds
Started	Feb 25 02:31:08 PM PST 24
Finished	Feb 25 02:33:32 PM PST 24
Peak memory	206936 kb
Host	smart-0d15cde9-7ae1-44c3-8dcd-477cc8d752aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3904394826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3904394826
Directory	/workspace/48.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.566037677
Short name	T593
Test name
Test status
Simulation time	320808697 ps
CPU time	42.57 seconds
Started	Feb 25 02:31:11 PM PST 24
Finished	Feb 25 02:31:54 PM PST 24
Peak memory	205304 kb
Host	smart-c3c6802e-4d5f-482f-81f0-30396bf85574
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=566037677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.566037677
Directory	/workspace/48.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2394760279
Short name	T132
Test name
Test status
Simulation time	4768174864 ps
CPU time	261.64 seconds
Started	Feb 25 02:31:10 PM PST 24
Finished	Feb 25 02:35:31 PM PST 24
Peak memory	208292 kb
Host	smart-14441e31-5313-4837-a6bd-c8c3271cc3ab
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2394760279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.2394760279
Directory	/workspace/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.677782173
Short name	T266
Test name
Test status
Simulation time	2440043151 ps
CPU time	220.53 seconds
Started	Feb 25 02:31:11 PM PST 24
Finished	Feb 25 02:34:52 PM PST 24
Peak memory	219520 kb
Host	smart-0b947449-5bd1-44f7-9c89-bb35ad362459
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=677782173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_res et_error.677782173
Directory	/workspace/48.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.2265340994
Short name	T307
Test name
Test status
Simulation time	117219186 ps
CPU time	13.91 seconds
Started	Feb 25 02:31:11 PM PST 24
Finished	Feb 25 02:31:25 PM PST 24
Peak memory	204692 kb
Host	smart-d8c40e7b-94c2-48b6-bffb-c678a67f4448
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2265340994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2265340994
Directory	/workspace/48.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2376175365
Short name	T143
Test name
Test status
Simulation time	55581175 ps
CPU time	7.35 seconds
Started	Feb 25 02:31:18 PM PST 24
Finished	Feb 25 02:31:25 PM PST 24
Peak memory	203476 kb
Host	smart-bd51ce0d-1a17-4989-b12c-a61a70617238
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2376175365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2376175365
Directory	/workspace/49.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.155111722
Short name	T784
Test name
Test status
Simulation time	75727616645 ps
CPU time	701.42 seconds
Started	Feb 25 02:31:09 PM PST 24
Finished	Feb 25 02:42:51 PM PST 24
Peak memory	211300 kb
Host	smart-daa0f899-081e-4dc5-9e4a-3248011474d3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=155111722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slo w_rsp.155111722
Directory	/workspace/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3288863334
Short name	T700
Test name
Test status
Simulation time	999947971 ps
CPU time	26.87 seconds
Started	Feb 25 02:31:16 PM PST 24
Finished	Feb 25 02:31:43 PM PST 24
Peak memory	203040 kb
Host	smart-95c18913-c308-4278-a55a-e3132c8bfda3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3288863334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3288863334
Directory	/workspace/49.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_error_random.2167193051
Short name	T787
Test name
Test status
Simulation time	283873147 ps
CPU time	24.17 seconds
Started	Feb 25 02:31:08 PM PST 24
Finished	Feb 25 02:31:32 PM PST 24
Peak memory	203048 kb
Host	smart-0bcdb61d-10d4-4c9d-9fff-449dd6307769
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2167193051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2167193051
Directory	/workspace/49.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random.1999389786
Short name	T655
Test name
Test status
Simulation time	700998708 ps
CPU time	28.23 seconds
Started	Feb 25 02:31:11 PM PST 24
Finished	Feb 25 02:31:40 PM PST 24
Peak memory	211228 kb
Host	smart-fc70a82f-1b60-40ca-b48c-9ed34b9f70e6
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1999389786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1999389786
Directory	/workspace/49.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.384097611
Short name	T505
Test name
Test status
Simulation time	37303620721 ps
CPU time	106.53 seconds
Started	Feb 25 02:31:08 PM PST 24
Finished	Feb 25 02:32:54 PM PST 24
Peak memory	204228 kb
Host	smart-e9754fc5-7602-4156-9012-8a50ed83f8d7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=384097611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.384097611
Directory	/workspace/49.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.473894043
Short name	T609
Test name
Test status
Simulation time	94754046126 ps
CPU time	278.16 seconds
Started	Feb 25 02:31:08 PM PST 24
Finished	Feb 25 02:35:46 PM PST 24
Peak memory	204236 kb
Host	smart-0ec5a847-89af-454a-b62f-5470fb2417eb
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=473894043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.473894043
Directory	/workspace/49.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.876235683
Short name	T455
Test name
Test status
Simulation time	117828342 ps
CPU time	11.55 seconds
Started	Feb 25 02:31:09 PM PST 24
Finished	Feb 25 02:31:21 PM PST 24
Peak memory	204116 kb
Host	smart-77b6da98-45d1-4065-a704-3bb2ebdc84e2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876235683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.876235683
Directory	/workspace/49.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_same_source.2227044396
Short name	T75
Test name
Test status
Simulation time	575857702 ps
CPU time	12.96 seconds
Started	Feb 25 02:31:09 PM PST 24
Finished	Feb 25 02:31:23 PM PST 24
Peak memory	203048 kb
Host	smart-179d1b1a-44c7-4ad7-b665-50e58d76e08c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2227044396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2227044396
Directory	/workspace/49.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke.2363845551
Short name	T274
Test name
Test status
Simulation time	107094021 ps
CPU time	3.37 seconds
Started	Feb 25 02:31:14 PM PST 24
Finished	Feb 25 02:31:17 PM PST 24
Peak memory	203064 kb
Host	smart-e83e4e0e-b8cb-40d9-9ea8-ab027cbdd59a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2363845551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2363845551
Directory	/workspace/49.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3916690964
Short name	T688
Test name
Test status
Simulation time	7532050008 ps
CPU time	28.97 seconds
Started	Feb 25 02:31:09 PM PST 24
Finished	Feb 25 02:31:38 PM PST 24
Peak memory	203036 kb
Host	smart-932702d2-bf4d-4bf7-afaf-a6adb1608b01
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916690964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3916690964
Directory	/workspace/49.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.667852850
Short name	T1
Test name
Test status
Simulation time	1928635197 ps
CPU time	18.78 seconds
Started	Feb 25 02:31:16 PM PST 24
Finished	Feb 25 02:31:35 PM PST 24
Peak memory	202972 kb
Host	smart-42a6af3c-0589-4f19-a345-7a2980bf2882
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=667852850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.667852850
Directory	/workspace/49.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.2653748494
Short name	T805
Test name
Test status
Simulation time	75258268 ps
CPU time	2.43 seconds
Started	Feb 25 02:31:11 PM PST 24
Finished	Feb 25 02:31:14 PM PST 24
Peak memory	203056 kb
Host	smart-6a9e19be-7845-4852-82d6-58de533f38f9
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653748494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.2653748494
Directory	/workspace/49.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all.1722147559
Short name	T95
Test name
Test status
Simulation time	2933008399 ps
CPU time	100.62 seconds
Started	Feb 25 02:31:17 PM PST 24
Finished	Feb 25 02:32:58 PM PST 24
Peak memory	206072 kb
Host	smart-03464338-1557-469c-898c-7dab51d36cd1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1722147559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1722147559
Directory	/workspace/49.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.946297890
Short name	T829
Test name
Test status
Simulation time	6380324162 ps
CPU time	121.26 seconds
Started	Feb 25 02:31:14 PM PST 24
Finished	Feb 25 02:33:16 PM PST 24
Peak memory	207504 kb
Host	smart-297ff020-c2fb-403c-bc05-e8d22da3a215
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=946297890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.946297890
Directory	/workspace/49.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.9345986
Short name	T837
Test name
Test status
Simulation time	1556815931 ps
CPU time	171.02 seconds
Started	Feb 25 02:31:17 PM PST 24
Finished	Feb 25 02:34:08 PM PST 24
Peak memory	208276 kb
Host	smart-6f70af62-fce7-49ed-8fac-133a729ba62b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=9345986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset _error.9345986
Directory	/workspace/49.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1447317611
Short name	T182
Test name
Test status
Simulation time	4719891269 ps
CPU time	35.09 seconds
Started	Feb 25 02:31:10 PM PST 24
Finished	Feb 25 02:31:45 PM PST 24
Peak memory	204944 kb
Host	smart-7205c49f-81cb-418b-a07b-2228b8a263d5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1447317611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1447317611
Directory	/workspace/49.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device.1034420857
Short name	T217
Test name
Test status
Simulation time	93354471 ps
CPU time	8.48 seconds
Started	Feb 25 02:26:37 PM PST 24
Finished	Feb 25 02:26:46 PM PST 24
Peak memory	211176 kb
Host	smart-27e511d1-8933-46c8-a25f-f0c873e1b622
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1034420857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1034420857
Directory	/workspace/5.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3797914650
Short name	T385
Test name
Test status
Simulation time	52755064464 ps
CPU time	359.22 seconds
Started	Feb 25 02:26:28 PM PST 24
Finished	Feb 25 02:32:28 PM PST 24
Peak memory	211312 kb
Host	smart-1f5a39aa-ebba-4eed-ac61-7251e2e92703
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3797914650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.3797914650
Directory	/workspace/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1359245854
Short name	T715
Test name
Test status
Simulation time	186645000 ps
CPU time	21.22 seconds
Started	Feb 25 02:26:33 PM PST 24
Finished	Feb 25 02:26:55 PM PST 24
Peak memory	203052 kb
Host	smart-3b0fffa8-c38e-42e7-9f0f-437d5dad2b52
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1359245854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1359245854
Directory	/workspace/5.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_error_random.2640769960
Short name	T221
Test name
Test status
Simulation time	237467701 ps
CPU time	23.63 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:26:53 PM PST 24
Peak memory	203024 kb
Host	smart-03dcdc7a-ddbd-4a65-be8b-c44e013972c5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2640769960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2640769960
Directory	/workspace/5.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random.3415263241
Short name	T820
Test name
Test status
Simulation time	87861760 ps
CPU time	9.34 seconds
Started	Feb 25 02:26:32 PM PST 24
Finished	Feb 25 02:26:41 PM PST 24
Peak memory	211276 kb
Host	smart-5c2f237a-42fa-4bdd-a534-9028cd54f0aa
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3415263241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.3415263241
Directory	/workspace/5.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.2839314550
Short name	T625
Test name
Test status
Simulation time	109145074524 ps
CPU time	158.14 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:29:08 PM PST 24
Peak memory	204436 kb
Host	smart-c0bb0bb7-ef73-40ce-a5ed-ca32d80d97b9
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839314550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2839314550
Directory	/workspace/5.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2052621819
Short name	T581
Test name
Test status
Simulation time	80585308076 ps
CPU time	264.54 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:30:54 PM PST 24
Peak memory	211300 kb
Host	smart-3c7383ba-9723-4cfc-b67b-213bfa224ff7
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2052621819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2052621819
Directory	/workspace/5.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3440916995
Short name	T116
Test name
Test status
Simulation time	312009337 ps
CPU time	22.91 seconds
Started	Feb 25 02:26:28 PM PST 24
Finished	Feb 25 02:26:51 PM PST 24
Peak memory	204404 kb
Host	smart-6921968c-b022-4a9a-b988-895e18fa4670
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440916995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3440916995
Directory	/workspace/5.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_same_source.2370566674
Short name	T710
Test name
Test status
Simulation time	1059748232 ps
CPU time	15.05 seconds
Started	Feb 25 02:26:32 PM PST 24
Finished	Feb 25 02:26:47 PM PST 24
Peak memory	203428 kb
Host	smart-ce509bcd-16a0-4116-910d-e98e77bf7069
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2370566674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2370566674
Directory	/workspace/5.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke.510524120
Short name	T231
Test name
Test status
Simulation time	28665457 ps
CPU time	2.64 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:26:32 PM PST 24
Peak memory	203052 kb
Host	smart-f8c7d26d-d78a-4cc9-9b91-8a5e283c1947
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=510524120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.510524120
Directory	/workspace/5.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1908112185
Short name	T112
Test name
Test status
Simulation time	11690488767 ps
CPU time	37.25 seconds
Started	Feb 25 02:26:35 PM PST 24
Finished	Feb 25 02:27:13 PM PST 24
Peak memory	203088 kb
Host	smart-977df1ea-a145-46f7-acd1-4e2a1c654b16
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908112185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1908112185
Directory	/workspace/5.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1117622323
Short name	T211
Test name
Test status
Simulation time	3459954796 ps
CPU time	23.84 seconds
Started	Feb 25 02:26:33 PM PST 24
Finished	Feb 25 02:26:57 PM PST 24
Peak memory	203120 kb
Host	smart-69b83e93-e79f-4c29-b0e2-2734512792aa
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1117622323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1117622323
Directory	/workspace/5.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1129378060
Short name	T42
Test name
Test status
Simulation time	42726080 ps
CPU time	2.18 seconds
Started	Feb 25 02:26:31 PM PST 24
Finished	Feb 25 02:26:33 PM PST 24
Peak memory	203044 kb
Host	smart-013d1a8d-9e11-4b5d-90fe-ff667bdc7973
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129378060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1129378060
Directory	/workspace/5.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all.3596746911
Short name	T553
Test name
Test status
Simulation time	10988315778 ps
CPU time	92.22 seconds
Started	Feb 25 02:26:33 PM PST 24
Finished	Feb 25 02:28:06 PM PST 24
Peak memory	207656 kb
Host	smart-2a1991af-8851-4fc1-90aa-46dbdbe812e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3596746911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3596746911
Directory	/workspace/5.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.190667243
Short name	T454
Test name
Test status
Simulation time	7077204803 ps
CPU time	205.76 seconds
Started	Feb 25 02:26:31 PM PST 24
Finished	Feb 25 02:29:56 PM PST 24
Peak memory	209740 kb
Host	smart-8715e8b9-2367-410d-a477-be2b13c2b965
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=190667243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.190667243
Directory	/workspace/5.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.3663034266
Short name	T278
Test name
Test status
Simulation time	237918327 ps
CPU time	146.92 seconds
Started	Feb 25 02:26:37 PM PST 24
Finished	Feb 25 02:29:04 PM PST 24
Peak memory	208244 kb
Host	smart-598bc20b-cc8f-46e6-a043-8d4acffa7c1d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3663034266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.3663034266
Directory	/workspace/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.3313856040
Short name	T730
Test name
Test status
Simulation time	2628485505 ps
CPU time	249.83 seconds
Started	Feb 25 02:26:34 PM PST 24
Finished	Feb 25 02:30:44 PM PST 24
Peak memory	219508 kb
Host	smart-30d936bb-f155-4d42-bd44-50ed1c33aa6c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3313856040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_res et_error.3313856040
Directory	/workspace/5.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2305809476
Short name	T582
Test name
Test status
Simulation time	152080238 ps
CPU time	22.25 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:26:51 PM PST 24
Peak memory	204868 kb
Host	smart-ef5d20c4-e439-44a5-a03b-c5b50b2a45d5
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2305809476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2305809476
Directory	/workspace/5.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device.4130653950
Short name	T670
Test name
Test status
Simulation time	90133972 ps
CPU time	7.21 seconds
Started	Feb 25 02:26:31 PM PST 24
Finished	Feb 25 02:26:38 PM PST 24
Peak memory	204084 kb
Host	smart-350b2e66-fb14-4219-9226-875ec8ca2069
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4130653950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.4130653950
Directory	/workspace/6.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.797498370
Short name	T89
Test name
Test status
Simulation time	13955227834 ps
CPU time	66.33 seconds
Started	Feb 25 02:26:30 PM PST 24
Finished	Feb 25 02:27:37 PM PST 24
Peak memory	204304 kb
Host	smart-34f6d867-97d1-403e-8a81-8073545828ea
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=797498370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow _rsp.797498370
Directory	/workspace/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.663872283
Short name	T349
Test name
Test status
Simulation time	597262804 ps
CPU time	25.38 seconds
Started	Feb 25 02:26:33 PM PST 24
Finished	Feb 25 02:26:58 PM PST 24
Peak memory	203364 kb
Host	smart-e9409c3c-d4ae-40d4-9e5f-a066f7721afd
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=663872283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.663872283
Directory	/workspace/6.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_error_random.1193970572
Short name	T237
Test name
Test status
Simulation time	1777306629 ps
CPU time	39.69 seconds
Started	Feb 25 02:26:34 PM PST 24
Finished	Feb 25 02:27:14 PM PST 24
Peak memory	203068 kb
Host	smart-2147a540-c850-4931-8c0f-4ee42d6d6bb9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1193970572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1193970572
Directory	/workspace/6.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random.2748597295
Short name	T576
Test name
Test status
Simulation time	205457778 ps
CPU time	28.9 seconds
Started	Feb 25 02:26:32 PM PST 24
Finished	Feb 25 02:27:01 PM PST 24
Peak memory	204300 kb
Host	smart-e190e502-05ac-4e6b-a6e2-12c0e4cf5f14
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2748597295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2748597295
Directory	/workspace/6.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.52373170
Short name	T601
Test name
Test status
Simulation time	72354518645 ps
CPU time	104.21 seconds
Started	Feb 25 02:26:34 PM PST 24
Finished	Feb 25 02:28:19 PM PST 24
Peak memory	204444 kb
Host	smart-120416df-b6f9-4d06-9042-c13f7d7e0613
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=52373170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.52373170
Directory	/workspace/6.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.698901437
Short name	T134
Test name
Test status
Simulation time	22241869310 ps
CPU time	131.23 seconds
Started	Feb 25 02:26:31 PM PST 24
Finished	Feb 25 02:28:42 PM PST 24
Peak memory	204236 kb
Host	smart-ecf898be-d6f5-4eb7-a4b9-dd948cecf9b0
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=698901437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.698901437
Directory	/workspace/6.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.3005572252
Short name	T333
Test name
Test status
Simulation time	189474943 ps
CPU time	6.47 seconds
Started	Feb 25 02:26:30 PM PST 24
Finished	Feb 25 02:26:37 PM PST 24
Peak memory	204120 kb
Host	smart-f2d91531-3c90-467f-9579-266d0c0f11fd
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005572252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3005572252
Directory	/workspace/6.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_same_source.2784335171
Short name	T417
Test name
Test status
Simulation time	3626903880 ps
CPU time	37.16 seconds
Started	Feb 25 02:26:29 PM PST 24
Finished	Feb 25 02:27:07 PM PST 24
Peak memory	203140 kb
Host	smart-41c6781a-2f7a-498d-93af-6cf7cdb13231
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2784335171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2784335171
Directory	/workspace/6.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke.1032923223
Short name	T834
Test name
Test status
Simulation time	33473966 ps
CPU time	2.4 seconds
Started	Feb 25 02:26:30 PM PST 24
Finished	Feb 25 02:26:33 PM PST 24
Peak memory	202972 kb
Host	smart-c7ef0b2b-abc1-4945-a4f7-05c2a6194d14
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1032923223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1032923223
Directory	/workspace/6.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.106050431
Short name	T642
Test name
Test status
Simulation time	10862609086 ps
CPU time	33.23 seconds
Started	Feb 25 02:26:34 PM PST 24
Finished	Feb 25 02:27:08 PM PST 24
Peak memory	203112 kb
Host	smart-dc00a105-a9f3-4363-a4fc-c8b777ce15c3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=106050431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.106050431
Directory	/workspace/6.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.627659805
Short name	T263
Test name
Test status
Simulation time	4870514231 ps
CPU time	20.53 seconds
Started	Feb 25 02:26:34 PM PST 24
Finished	Feb 25 02:26:55 PM PST 24
Peak memory	203108 kb
Host	smart-fdcccf07-a1b0-421b-aa28-2c0a6c4b7366
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=627659805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.627659805
Directory	/workspace/6.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3556251936
Short name	T354
Test name
Test status
Simulation time	31438406 ps
CPU time	2.38 seconds
Started	Feb 25 02:26:37 PM PST 24
Finished	Feb 25 02:26:39 PM PST 24
Peak memory	203024 kb
Host	smart-bc1f7c16-e0f6-4908-b468-774158801374
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556251936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3556251936
Directory	/workspace/6.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all.3160571961
Short name	T703
Test name
Test status
Simulation time	2755516881 ps
CPU time	108.34 seconds
Started	Feb 25 02:26:34 PM PST 24
Finished	Feb 25 02:28:22 PM PST 24
Peak memory	211280 kb
Host	smart-8f35098b-4d7f-4828-b9d4-74e67706e54d
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3160571961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3160571961
Directory	/workspace/6.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.350352325
Short name	T371
Test name
Test status
Simulation time	1181455189 ps
CPU time	97.25 seconds
Started	Feb 25 02:26:31 PM PST 24
Finished	Feb 25 02:28:09 PM PST 24
Peak memory	206448 kb
Host	smart-73531dd1-e87d-44fb-94f0-ba32d039fce9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=350352325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.350352325
Directory	/workspace/6.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3731300535
Short name	T431
Test name
Test status
Simulation time	322103772 ps
CPU time	104.78 seconds
Started	Feb 25 02:26:34 PM PST 24
Finished	Feb 25 02:28:19 PM PST 24
Peak memory	207652 kb
Host	smart-c22c6bf2-03d2-49ba-a3c5-f2231e72cbf7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3731300535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.3731300535
Directory	/workspace/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.421612233
Short name	T532
Test name
Test status
Simulation time	361569636 ps
CPU time	73.55 seconds
Started	Feb 25 02:26:37 PM PST 24
Finished	Feb 25 02:27:51 PM PST 24
Peak memory	208084 kb
Host	smart-a074f761-510a-40d2-9ab0-e20c218880d0
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=421612233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rese t_error.421612233
Directory	/workspace/6.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.2852189107
Short name	T663
Test name
Test status
Simulation time	96387286 ps
CPU time	11.52 seconds
Started	Feb 25 02:26:32 PM PST 24
Finished	Feb 25 02:26:44 PM PST 24
Peak memory	211232 kb
Host	smart-4ba3bdc7-5af3-4283-b5f0-bfa637346abe
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2852189107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2852189107
Directory	/workspace/6.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1566951995
Short name	T554
Test name
Test status
Simulation time	405489608 ps
CPU time	15.85 seconds
Started	Feb 25 02:26:33 PM PST 24
Finished	Feb 25 02:26:49 PM PST 24
Peak memory	203036 kb
Host	smart-9be6bdf4-d4c7-4b36-b1f8-276e80b39332
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1566951995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1566951995
Directory	/workspace/7.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.888478391
Short name	T727
Test name
Test status
Simulation time	379214571 ps
CPU time	6.17 seconds
Started	Feb 25 02:26:33 PM PST 24
Finished	Feb 25 02:26:39 PM PST 24
Peak memory	203128 kb
Host	smart-89ad8c58-6e6d-48cc-9c08-e079947ac7f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=888478391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.888478391
Directory	/workspace/7.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_error_random.931274347
Short name	T786
Test name
Test status
Simulation time	44465236 ps
CPU time	2.95 seconds
Started	Feb 25 02:26:38 PM PST 24
Finished	Feb 25 02:26:41 PM PST 24
Peak memory	203028 kb
Host	smart-c7fcd92d-72b1-456f-b845-338e82e5e407
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=931274347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.931274347
Directory	/workspace/7.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random.2564917551
Short name	T648
Test name
Test status
Simulation time	455324000 ps
CPU time	22.55 seconds
Started	Feb 25 02:26:32 PM PST 24
Finished	Feb 25 02:26:54 PM PST 24
Peak memory	211268 kb
Host	smart-b36a1914-45f6-4097-a5b4-76e7cbc9fadf
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2564917551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2564917551
Directory	/workspace/7.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.443610222
Short name	T447
Test name
Test status
Simulation time	16565840225 ps
CPU time	72.88 seconds
Started	Feb 25 02:26:33 PM PST 24
Finished	Feb 25 02:27:46 PM PST 24
Peak memory	204200 kb
Host	smart-65fddb0f-aa49-4ced-a896-c29282b03f78
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=443610222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.443610222
Directory	/workspace/7.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.3479654802
Short name	T662
Test name
Test status
Simulation time	23842781467 ps
CPU time	105.21 seconds
Started	Feb 25 02:26:36 PM PST 24
Finished	Feb 25 02:28:21 PM PST 24
Peak memory	211304 kb
Host	smart-cca985b5-3181-4d04-bff6-7493a58fb7de
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3479654802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3479654802
Directory	/workspace/7.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.1950165216
Short name	T814
Test name
Test status
Simulation time	115091928 ps
CPU time	11.25 seconds
Started	Feb 25 02:26:38 PM PST 24
Finished	Feb 25 02:26:49 PM PST 24
Peak memory	204168 kb
Host	smart-bf73a52a-d9b8-4af1-9e7c-523735e63c17
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950165216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1950165216
Directory	/workspace/7.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_same_source.1224862069
Short name	T547
Test name
Test status
Simulation time	1588249162 ps
CPU time	6.89 seconds
Started	Feb 25 02:26:36 PM PST 24
Finished	Feb 25 02:26:43 PM PST 24
Peak memory	203124 kb
Host	smart-b1c8ea00-0c22-41f2-a056-54478fd0ba32
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1224862069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1224862069
Directory	/workspace/7.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke.2641172067
Short name	T425
Test name
Test status
Simulation time	128417981 ps
CPU time	3.46 seconds
Started	Feb 25 02:26:32 PM PST 24
Finished	Feb 25 02:26:36 PM PST 24
Peak memory	203032 kb
Host	smart-eb647565-cc35-4432-bdd6-96ec10c6ba61
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2641172067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2641172067
Directory	/workspace/7.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2380351059
Short name	T463
Test name
Test status
Simulation time	14429169074 ps
CPU time	34.53 seconds
Started	Feb 25 02:26:32 PM PST 24
Finished	Feb 25 02:27:06 PM PST 24
Peak memory	203112 kb
Host	smart-f1075083-d3c8-40b4-a78c-89cbdef53108
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380351059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2380351059
Directory	/workspace/7.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1004904314
Short name	T302
Test name
Test status
Simulation time	2837450245 ps
CPU time	24.75 seconds
Started	Feb 25 02:26:36 PM PST 24
Finished	Feb 25 02:27:02 PM PST 24
Peak memory	203100 kb
Host	smart-6355c37a-4db1-4f3c-8dc0-619c6eb25f4c
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1004904314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1004904314
Directory	/workspace/7.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2121787654
Short name	T456
Test name
Test status
Simulation time	31762626 ps
CPU time	2.19 seconds
Started	Feb 25 02:26:37 PM PST 24
Finished	Feb 25 02:26:39 PM PST 24
Peak memory	203036 kb
Host	smart-2201ffda-b246-4280-a0f5-62090addf67d
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121787654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2121787654
Directory	/workspace/7.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all.2941618377
Short name	T104
Test name
Test status
Simulation time	4200835256 ps
CPU time	148.93 seconds
Started	Feb 25 02:26:37 PM PST 24
Finished	Feb 25 02:29:07 PM PST 24
Peak memory	207996 kb
Host	smart-f38553e7-d656-4230-ba04-709f9b8692e3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2941618377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2941618377
Directory	/workspace/7.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.4246099796
Short name	T878
Test name
Test status
Simulation time	4754764691 ps
CPU time	99.51 seconds
Started	Feb 25 02:26:37 PM PST 24
Finished	Feb 25 02:28:17 PM PST 24
Peak memory	205716 kb
Host	smart-6824750e-41e7-4e9c-82d0-d2ab0374f389
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4246099796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.4246099796
Directory	/workspace/7.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3315055568
Short name	T894
Test name
Test status
Simulation time	3731486278 ps
CPU time	235.1 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:30:35 PM PST 24
Peak memory	209208 kb
Host	smart-41d39972-2312-4583-bf8e-4935d977f6d3
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3315055568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.3315055568
Directory	/workspace/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1628144374
Short name	T803
Test name
Test status
Simulation time	9042924779 ps
CPU time	394.69 seconds
Started	Feb 25 02:26:37 PM PST 24
Finished	Feb 25 02:33:12 PM PST 24
Peak memory	219560 kb
Host	smart-a6c2b4b7-c73c-4ab8-a196-2693b810980b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1628144374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res et_error.1628144374
Directory	/workspace/7.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2436104138
Short name	T548
Test name
Test status
Simulation time	78490224 ps
CPU time	3.62 seconds
Started	Feb 25 02:26:36 PM PST 24
Finished	Feb 25 02:26:39 PM PST 24
Peak memory	203052 kb
Host	smart-5f40f90d-e94f-42e4-bb59-82de5ea7229a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2436104138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2436104138
Directory	/workspace/7.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_access_same_device.2572299214
Short name	T216
Test name
Test status
Simulation time	1270080772 ps
CPU time	35.43 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:27:16 PM PST 24
Peak memory	205696 kb
Host	smart-76f29b80-f048-4083-8cfc-d040e395ca0a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2572299214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.2572299214
Directory	/workspace/8.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1608078338
Short name	T209
Test name
Test status
Simulation time	1180784865 ps
CPU time	26.72 seconds
Started	Feb 25 02:26:39 PM PST 24
Finished	Feb 25 02:27:06 PM PST 24
Peak memory	203060 kb
Host	smart-aeac3243-4eb7-4aad-a246-b9a92dc14d8a
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1608078338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1608078338
Directory	/workspace/8.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_error_random.3430548927
Short name	T308
Test name
Test status
Simulation time	276631145 ps
CPU time	7.44 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:26:50 PM PST 24
Peak memory	202984 kb
Host	smart-b1a61d0c-656a-4b01-8282-61b33aa5a934
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3430548927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3430548927
Directory	/workspace/8.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random.2627712450
Short name	T18
Test name
Test status
Simulation time	360414747 ps
CPU time	18.07 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:27:00 PM PST 24
Peak memory	211244 kb
Host	smart-8da4344c-de8e-452e-9710-4643dc302c42
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2627712450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2627712450
Directory	/workspace/8.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2922157536
Short name	T794
Test name
Test status
Simulation time	17484465621 ps
CPU time	90.12 seconds
Started	Feb 25 02:26:39 PM PST 24
Finished	Feb 25 02:28:10 PM PST 24
Peak memory	204224 kb
Host	smart-78cb94cc-c297-4c72-be16-9c640fb6fe36
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922157536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2922157536
Directory	/workspace/8.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.1479277979
Short name	T108
Test name
Test status
Simulation time	11229889295 ps
CPU time	92.84 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:28:13 PM PST 24
Peak memory	204360 kb
Host	smart-e7f4d40d-1fbc-47fe-bda3-5344a273ef31
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1479277979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1479277979
Directory	/workspace/8.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.637026751
Short name	T150
Test name
Test status
Simulation time	109550083 ps
CPU time	13.93 seconds
Started	Feb 25 02:26:36 PM PST 24
Finished	Feb 25 02:26:50 PM PST 24
Peak memory	211248 kb
Host	smart-777f72e3-ea63-4442-adf9-abfdcbe51ea4
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637026751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.637026751
Directory	/workspace/8.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_same_source.605277467
Short name	T649
Test name
Test status
Simulation time	1084970129 ps
CPU time	24.45 seconds
Started	Feb 25 02:26:39 PM PST 24
Finished	Feb 25 02:27:04 PM PST 24
Peak memory	203064 kb
Host	smart-9969f999-309b-4ec2-9e00-1aa8d635753b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=605277467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.605277467
Directory	/workspace/8.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke.2182687384
Short name	T495
Test name
Test status
Simulation time	147339044 ps
CPU time	3.37 seconds
Started	Feb 25 02:26:44 PM PST 24
Finished	Feb 25 02:26:48 PM PST 24
Peak memory	202916 kb
Host	smart-3d57822e-d91e-47d8-b9e7-9ce62d45b04f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2182687384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2182687384
Directory	/workspace/8.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1489361706
Short name	T43
Test name
Test status
Simulation time	5776335913 ps
CPU time	34.84 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:27:17 PM PST 24
Peak memory	203116 kb
Host	smart-c4dca552-77b4-4b54-afda-40bf672bd295
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489361706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1489361706
Directory	/workspace/8.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1944489072
Short name	T819
Test name
Test status
Simulation time	21334774011 ps
CPU time	54.16 seconds
Started	Feb 25 02:26:38 PM PST 24
Finished	Feb 25 02:27:33 PM PST 24
Peak memory	203116 kb
Host	smart-3fd5b6d0-5e72-42d5-8bbd-b10be2224865
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1944489072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1944489072
Directory	/workspace/8.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.1866324199
Short name	T67
Test name
Test status
Simulation time	72492505 ps
CPU time	2.45 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:26:42 PM PST 24
Peak memory	203036 kb
Host	smart-447d937e-4ff9-49d4-86f4-8532ccfef4b2
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866324199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1866324199
Directory	/workspace/8.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all.3843720486
Short name	T840
Test name
Test status
Simulation time	2489321717 ps
CPU time	129.81 seconds
Started	Feb 25 02:26:39 PM PST 24
Finished	Feb 25 02:28:49 PM PST 24
Peak memory	207384 kb
Host	smart-b7e2952a-5ed2-4656-821f-ec3ffc525f2f
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3843720486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3843720486
Directory	/workspace/8.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4268628864
Short name	T792
Test name
Test status
Simulation time	9679970577 ps
CPU time	136.81 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:28:58 PM PST 24
Peak memory	207292 kb
Host	smart-fef8c3fa-1684-4abe-9b1f-2ee4c34d2958
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4268628864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4268628864
Directory	/workspace/8.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.1627543265
Short name	T681
Test name
Test status
Simulation time	9023261088 ps
CPU time	420.93 seconds
Started	Feb 25 02:26:43 PM PST 24
Finished	Feb 25 02:33:44 PM PST 24
Peak memory	209184 kb
Host	smart-b748a4dd-4eb8-4ce5-b173-83aef1806485
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1627543265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.1627543265
Directory	/workspace/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2110889677
Short name	T511
Test name
Test status
Simulation time	6252816404 ps
CPU time	272.26 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:31:13 PM PST 24
Peak memory	211316 kb
Host	smart-a5e23dac-c19c-443c-8715-84a80dfb592b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2110889677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.2110889677
Directory	/workspace/8.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3441683726
Short name	T893
Test name
Test status
Simulation time	194491308 ps
CPU time	25.97 seconds
Started	Feb 25 02:26:37 PM PST 24
Finished	Feb 25 02:27:04 PM PST 24
Peak memory	204796 kb
Host	smart-e5e6289d-05b2-4556-a2bc-e9a83a418d02
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3441683726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3441683726
Directory	/workspace/8.xbar_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device.1868319300
Short name	T892
Test name
Test status
Simulation time	2053270968 ps
CPU time	32.27 seconds
Started	Feb 25 02:26:41 PM PST 24
Finished	Feb 25 02:27:14 PM PST 24
Peak memory	205368 kb
Host	smart-71c8c2f2-0411-4422-9fb1-cfcd01579a9c
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1868319300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1868319300
Directory	/workspace/9.xbar_access_same_device/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3113669913
Short name	T107
Test name
Test status
Simulation time	92821720769 ps
CPU time	220.75 seconds
Started	Feb 25 02:26:51 PM PST 24
Finished	Feb 25 02:30:32 PM PST 24
Peak memory	211296 kb
Host	smart-6690cd31-1a5b-46c8-9056-95b295b73a76
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3113669913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.3113669913
Directory	/workspace/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1392333224
Short name	T789
Test name
Test status
Simulation time	500131972 ps
CPU time	10.49 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:26:51 PM PST 24
Peak memory	203052 kb
Host	smart-bc4815a2-6a91-4615-a62b-69d1f74222f1
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1392333224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1392333224
Directory	/workspace/9.xbar_error_and_unmapped_addr/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_error_random.3505540603
Short name	T260
Test name
Test status
Simulation time	195109472 ps
CPU time	24.91 seconds
Started	Feb 25 02:26:44 PM PST 24
Finished	Feb 25 02:27:09 PM PST 24
Peak memory	203196 kb
Host	smart-681fda9e-fa95-4e6a-8107-ef5bb8785718
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3505540603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3505540603
Directory	/workspace/9.xbar_error_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random.3462308849
Short name	T189
Test name
Test status
Simulation time	552643881 ps
CPU time	19.67 seconds
Started	Feb 25 02:26:41 PM PST 24
Finished	Feb 25 02:27:01 PM PST 24
Peak memory	204320 kb
Host	smart-147a4de7-03a5-40f6-9cfa-aebb17d642ba
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3462308849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3462308849
Directory	/workspace/9.xbar_random/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1080503612
Short name	T257
Test name
Test status
Simulation time	39543847284 ps
CPU time	188.54 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:29:49 PM PST 24
Peak memory	204232 kb
Host	smart-0b39691d-e5b4-4383-8118-84d65e8d7037
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080503612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1080503612
Directory	/workspace/9.xbar_random_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.1303705996
Short name	T225
Test name
Test status
Simulation time	82603191280 ps
CPU time	331.22 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:32:14 PM PST 24
Peak memory	204552 kb
Host	smart-dfef45b8-9385-473e-b968-c46aa99639b3
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1303705996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1303705996
Directory	/workspace/9.xbar_random_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2682828166
Short name	T801
Test name
Test status
Simulation time	79737400 ps
CPU time	3.52 seconds
Started	Feb 25 02:26:44 PM PST 24
Finished	Feb 25 02:26:47 PM PST 24
Peak memory	203052 kb
Host	smart-04188271-fbef-4b0e-b01d-92888b88dc66
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682828166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2682828166
Directory	/workspace/9.xbar_random_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_same_source.3561411986
Short name	T369
Test name
Test status
Simulation time	414065619 ps
CPU time	13.49 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:26:54 PM PST 24
Peak memory	203056 kb
Host	smart-e9d1940c-212c-4e7b-99c9-f6235e257b8b
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3561411986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3561411986
Directory	/workspace/9.xbar_same_source/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke.820966943
Short name	T483
Test name
Test status
Simulation time	55385192 ps
CPU time	2.49 seconds
Started	Feb 25 02:26:38 PM PST 24
Finished	Feb 25 02:26:40 PM PST 24
Peak memory	203040 kb
Host	smart-70382220-97cc-41d4-a499-da420f5be1f9
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=820966943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.820966943
Directory	/workspace/9.xbar_smoke/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3680382648
Short name	T811
Test name
Test status
Simulation time	14081028535 ps
CPU time	31.35 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:27:12 PM PST 24
Peak memory	203116 kb
Host	smart-a522684c-2b49-4a37-9f49-5845940d608b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680382648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3680382648
Directory	/workspace/9.xbar_smoke_large_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.2930339747
Short name	T213
Test name
Test status
Simulation time	16554526399 ps
CPU time	39.97 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:27:20 PM PST 24
Peak memory	202980 kb
Host	smart-724b7986-90fd-4fb4-89e4-d2c7706e161b
User	root
Command	/workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2930339747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2930339747
Directory	/workspace/9.xbar_smoke_slow_rsp/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3244531630
Short name	T720
Test name
Test status
Simulation time	74949445 ps
CPU time	2.65 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:26:43 PM PST 24
Peak memory	202976 kb
Host	smart-6af3664d-b613-4086-8b94-5d662a0e5218
User	root
Command	/workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244531630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3244531630
Directory	/workspace/9.xbar_smoke_zero_delays/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all.229632626
Short name	T247
Test name
Test status
Simulation time	960462843 ps
CPU time	109.09 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:28:30 PM PST 24
Peak memory	206728 kb
Host	smart-6880ada6-c74f-4964-a0e1-ba5e8141122e
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=229632626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.229632626
Directory	/workspace/9.xbar_stress_all/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.2998192710
Short name	T762
Test name
Test status
Simulation time	523368669 ps
CPU time	27.44 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:27:09 PM PST 24
Peak memory	204296 kb
Host	smart-844036bb-81dc-4019-a432-0d4b1d40f3f7
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2998192710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2998192710
Directory	/workspace/9.xbar_stress_all_with_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3081693330
Short name	T27
Test name
Test status
Simulation time	3101832333 ps
CPU time	313.14 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:31:56 PM PST 24
Peak memory	209004 kb
Host	smart-e9538c53-6c0d-4650-8b38-6e2d19f91950
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3081693330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.3081693330
Directory	/workspace/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.182555507
Short name	T888
Test name
Test status
Simulation time	5202012849 ps
CPU time	203.04 seconds
Started	Feb 25 02:26:42 PM PST 24
Finished	Feb 25 02:30:05 PM PST 24
Peak memory	210400 kb
Host	smart-370aaa42-40d1-417d-b033-6a06edda4bdb
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=182555507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese t_error.182555507
Directory	/workspace/9.xbar_stress_all_with_reset_error/latest

Test location	/workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1129675859
Short name	T798
Test name
Test status
Simulation time	26050734 ps
CPU time	4.66 seconds
Started	Feb 25 02:26:40 PM PST 24
Finished	Feb 25 02:26:46 PM PST 24
Peak memory	211216 kb
Host	smart-495d0a06-a141-45a6-8cea-1ee7af84ea03
User	root
Command	/workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1129675859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1129675859
Directory	/workspace/9.xbar_unmapped_addr/latest