Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1676	1			T3	3		T7	12		T9	1
all_values[1]	1707	1			T3	2		T7	13		T66	13
all_values[2]	1633	1			T3	5		T7	11		T9	1
all_values[3]	1650	1			T3	4		T7	14		T9	2
all_values[4]	1673	1			T3	4		T7	11		T66	14
all_values[5]	1721	1			T3	6		T7	10		T9	2
all_values[6]	1764	1			T3	3		T7	14		T9	6
all_values[7]	1708	1			T3	4		T7	13		T9	1
all_values[8]	1713	1			T3	1		T7	10		T9	3
all_values[9]	1690	1			T3	1		T7	20		T9	2
all_values[10]	1718	1			T3	3		T7	10		T9	2
all_values[11]	1664	1			T3	2		T7	9		T66	13
all_values[12]	1696	1			T3	2		T7	10		T66	20
all_values[13]	1601	1			T3	5		T7	10		T9	2
all_values[14]	1716	1			T3	3		T7	16		T9	1
all_values[15]	1726	1			T7	8		T9	2		T66	12
all_values[16]	1697	1			T3	5		T7	11		T9	5
all_values[17]	1726	1			T3	4		T7	10		T9	1
all_values[18]	1653	1			T3	4		T7	6		T9	1
all_values[19]	1680	1			T3	5		T7	11		T9	2
all_values[20]	1686	1			T3	6		T7	12		T9	2
all_values[21]	1689	1			T3	3		T7	9		T9	2
all_values[22]	1711	1			T3	5		T7	15		T9	3
all_values[23]	1721	1			T3	2		T7	7		T9	2
all_values[24]	1720	1			T7	12		T9	2		T66	20
all_values[25]	1683	1			T3	3		T7	8		T9	3
all_values[26]	1733	1			T3	6		T7	15		T66	20
all_values[27]	1702	1			T3	5		T7	15		T9	2
all_values[28]	1715	1			T3	5		T7	12		T66	20
all_values[29]	1617	1			T3	6		T7	18		T9	1
all_values[30]	1743	1			T3	3		T7	14		T66	14
all_values[31]	1679	1			T3	2		T7	8		T66	21
all_values[32]	1686	1			T3	5		T7	18		T9	2
all_values[33]	1758	1			T3	4		T7	17		T9	3
all_values[34]	1736	1			T3	6		T7	13		T66	12
all_values[35]	1732	1			T3	4		T7	9		T66	9
all_values[36]	1756	1			T3	3		T7	9		T9	2
all_values[37]	1659	1			T3	3		T7	11		T9	1
all_values[38]	1672	1			T3	4		T7	12		T9	1
all_values[39]	1729	1			T3	1		T7	7		T9	1
all_values[40]	1685	1			T3	5		T7	16		T9	1
all_values[41]	1680	1			T3	5		T7	12		T66	20
all_values[42]	1686	1			T3	7		T7	7		T9	1
all_values[43]	1728	1			T3	3		T7	12		T9	3
all_values[44]	1680	1			T3	5		T7	17		T66	11
all_values[45]	1731	1			T3	1		T7	12		T9	1
all_values[46]	1729	1			T3	5		T7	13		T9	1
all_values[47]	1703	1			T3	4		T7	11		T66	16
all_values[48]	1773	1			T3	7		T7	6		T66	11
all_values[49]	1683	1			T3	4		T7	11		T66	14
all_values[50]	1733	1			T3	4		T7	10		T9	1
all_values[51]	1673	1			T3	3		T7	16		T9	4
all_values[52]	1679	1			T3	4		T7	14		T9	2
all_values[53]	1685	1			T7	12		T9	1		T66	18
all_values[54]	1765	1			T3	5		T7	11		T66	17
all_values[55]	1710	1			T3	1		T7	11		T9	1
all_values[56]	1735	1			T3	3		T7	15		T9	3
all_values[57]	1669	1			T3	2		T7	6		T9	1
all_values[58]	1712	1			T3	3		T7	10		T9	1
all_values[59]	1693	1			T3	4		T7	17		T9	2
all_values[60]	1698	1			T3	1		T7	8		T9	1
all_values[61]	1669	1			T3	4		T7	8		T66	13
all_values[62]	1702	1			T3	2		T7	22		T66	11
all_values[63]	1695	1			T3	4		T7	10		T9	2