Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 479 1 T2 1 T8 1 T15 7
all_values[1] 524 1 T2 1 T4 1 T8 1
all_values[2] 482 1 T2 1 T8 3 T12 1
all_values[3] 487 1 T8 3 T15 4 T17 1
all_values[4] 496 1 T2 2 T4 1 T8 1
all_values[5] 497 1 T15 10 T68 1 T17 7
all_values[6] 482 1 T2 1 T12 1 T15 5
all_values[7] 481 1 T15 5 T17 3 T22 1
all_values[8] 480 1 T12 1 T15 9 T68 2
all_values[9] 485 1 T4 1 T8 1 T15 6
all_values[10] 480 1 T4 1 T8 3 T12 1
all_values[11] 506 1 T2 1 T8 2 T15 7
all_values[12] 469 1 T4 1 T8 2 T12 1
all_values[13] 476 1 T2 1 T4 2 T12 1
all_values[14] 448 1 T2 4 T4 1 T8 1
all_values[15] 469 1 T2 1 T4 1 T12 1
all_values[16] 530 1 T2 4 T4 2 T8 2
all_values[17] 521 1 T2 1 T4 2 T12 1
all_values[18] 472 1 T2 2 T4 1 T12 1
all_values[19] 475 1 T2 1 T4 1 T8 1
all_values[20] 485 1 T2 3 T8 6 T12 2
all_values[21] 492 1 T8 1 T15 6 T17 7
all_values[22] 496 1 T2 3 T4 1 T8 1
all_values[23] 480 1 T2 2 T12 1 T15 9

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