Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1694	1			T2	15		T8	5		T14	2
all_values[1]	1577	1			T2	9		T8	8		T12	2
all_values[2]	1681	1			T2	8		T8	5		T14	2
all_values[3]	1739	1			T2	11		T8	4		T12	2
all_values[4]	1707	1			T2	6		T8	6		T14	1
all_values[5]	1683	1			T2	6		T8	4		T14	3
all_values[6]	1671	1			T2	8		T8	7		T14	4
all_values[7]	1754	1			T2	7		T8	5		T12	1
all_values[8]	1649	1			T2	10		T8	4		T12	1
all_values[9]	1670	1			T2	7		T8	8		T12	1
all_values[10]	1675	1			T2	12		T8	1		T12	3
all_values[11]	1683	1			T2	6		T8	3		T12	2
all_values[12]	1704	1			T2	7		T8	8		T12	1
all_values[13]	1726	1			T2	6		T8	3		T14	1
all_values[14]	1706	1			T2	7		T8	3		T12	3
all_values[15]	1690	1			T2	10		T8	7		T14	1
all_values[16]	1704	1			T2	7		T8	4		T12	2
all_values[17]	1643	1			T2	4		T8	4		T12	1
all_values[18]	1728	1			T2	7		T8	9		T12	3
all_values[19]	1726	1			T2	9		T8	3		T14	1
all_values[20]	1689	1			T2	5		T8	2		T14	1
all_values[21]	1766	1			T2	12		T8	3		T12	1
all_values[22]	1696	1			T8	7		T14	3		T15	22
all_values[23]	1720	1			T2	2		T8	8		T15	16
all_values[24]	1747	1			T2	8		T8	2		T12	1
all_values[25]	1693	1			T2	8		T8	11		T12	1
all_values[26]	1729	1			T2	10		T8	8		T12	1
all_values[27]	1707	1			T2	8		T8	5		T12	2
all_values[28]	1761	1			T2	4		T8	3		T15	12
all_values[29]	1670	1			T2	10		T8	9		T14	4
all_values[30]	1713	1			T2	9		T8	4		T12	4
all_values[31]	1710	1			T2	3		T8	6		T14	1
all_values[32]	1772	1			T2	8		T8	7		T12	3
all_values[33]	1772	1			T2	8		T8	5		T12	1
all_values[34]	1758	1			T2	6		T8	6		T14	1
all_values[35]	1708	1			T2	5		T8	6		T12	2
all_values[36]	1707	1			T2	5		T8	7		T12	1
all_values[37]	1687	1			T2	6		T8	4		T12	1
all_values[38]	1666	1			T2	8		T8	3		T12	1
all_values[39]	1706	1			T2	10		T8	6		T12	1
all_values[40]	1721	1			T2	12		T8	5		T12	2
all_values[41]	1720	1			T2	6		T8	6		T12	1
all_values[42]	1635	1			T2	4		T8	10		T12	1
all_values[43]	1727	1			T2	11		T8	5		T14	4
all_values[44]	1750	1			T2	5		T8	5		T12	2
all_values[45]	1758	1			T2	5		T8	6		T12	3
all_values[46]	1759	1			T2	3		T8	3		T12	1
all_values[47]	1693	1			T2	7		T8	5		T12	2
all_values[48]	1730	1			T2	6		T8	10		T14	2
all_values[49]	1729	1			T2	7		T8	6		T12	2
all_values[50]	1781	1			T2	12		T8	8		T12	4
all_values[51]	1665	1			T2	11		T8	2		T12	1
all_values[52]	1700	1			T2	8		T8	4		T14	2
all_values[53]	1722	1			T2	3		T8	3		T12	3
all_values[54]	1670	1			T2	11		T8	4		T12	3
all_values[55]	1745	1			T2	7		T8	4		T14	2
all_values[56]	1758	1			T2	11		T8	4		T12	1
all_values[57]	1732	1			T2	7		T8	5		T12	4
all_values[58]	1759	1			T2	10		T8	9		T12	1
all_values[59]	1647	1			T2	6		T8	2		T12	2
all_values[60]	1635	1			T2	6		T8	8		T12	1
all_values[61]	1693	1			T2	12		T8	4		T14	2
all_values[62]	1629	1			T2	1		T8	6		T14	1
all_values[63]	1744	1			T2	9		T8	9		T12	2