Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 521 1 T1 2 T3 9 T4 1
all_values[1] 453 1 T1 4 T3 2 T8 2
all_values[2] 462 1 T1 4 T3 6 T8 1
all_values[3] 457 1 T1 1 T3 7 T8 1
all_values[4] 455 1 T1 1 T3 7 T8 1
all_values[5] 492 1 T1 3 T3 8 T10 1
all_values[6] 494 1 T3 7 T8 2 T10 1
all_values[7] 477 1 T1 2 T3 14 T8 1
all_values[8] 454 1 T1 2 T3 4 T10 1
all_values[9] 434 1 T1 1 T3 7 T8 2
all_values[10] 458 1 T1 2 T3 12 T8 4
all_values[11] 453 1 T1 4 T3 8 T4 1
all_values[12] 445 1 T1 1 T3 6 T10 2
all_values[13] 453 1 T3 11 T4 1 T8 2
all_values[14] 515 1 T1 1 T3 4 T4 1
all_values[15] 495 1 T1 2 T3 4 T10 1
all_values[16] 485 1 T1 1 T3 10 T4 1
all_values[17] 444 1 T1 1 T3 5 T15 6
all_values[18] 424 1 T3 4 T4 1 T8 1
all_values[19] 491 1 T1 4 T3 6 T8 2
all_values[20] 451 1 T3 9 T8 3 T10 1
all_values[21] 467 1 T3 5 T4 2 T8 1
all_values[22] 443 1 T1 1 T3 10 T8 1
all_values[23] 436 1 T3 7 T12 1 T14 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%