Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1696	1			T1	5		T3	35		T13	3
all_values[1]	1774	1			T1	3		T3	22		T12	3
all_values[2]	1704	1			T1	6		T3	32		T12	1
all_values[3]	1782	1			T1	8		T3	41		T12	1
all_values[4]	1783	1			T1	6		T3	31		T12	2
all_values[5]	1770	1			T1	8		T3	26		T13	12
all_values[6]	1819	1			T1	7		T3	43		T12	2
all_values[7]	1675	1			T1	4		T3	27		T12	1
all_values[8]	1696	1			T1	4		T3	30		T13	6
all_values[9]	1723	1			T1	5		T3	31		T13	1
all_values[10]	1844	1			T1	6		T3	34		T12	1
all_values[11]	1811	1			T1	2		T3	31		T13	8
all_values[12]	1734	1			T1	3		T3	34		T12	2
all_values[13]	1783	1			T1	2		T3	35		T12	2
all_values[14]	1710	1			T1	3		T3	37		T12	1
all_values[15]	1694	1			T1	8		T3	39		T13	7
all_values[16]	1745	1			T1	6		T3	39		T13	2
all_values[17]	1838	1			T1	7		T3	29		T13	6
all_values[18]	1696	1			T1	5		T3	38		T13	5
all_values[19]	1685	1			T1	6		T3	43		T12	1
all_values[20]	1786	1			T1	11		T3	32		T12	2
all_values[21]	1755	1			T1	1		T3	40		T12	4
all_values[22]	1813	1			T1	9		T3	33		T13	4
all_values[23]	1763	1			T1	7		T3	34		T13	5
all_values[24]	1741	1			T1	6		T3	33		T12	1
all_values[25]	1705	1			T1	5		T3	29		T13	4
all_values[26]	1785	1			T1	5		T3	36		T12	1
all_values[27]	1672	1			T1	5		T3	33		T12	1
all_values[28]	1801	1			T1	4		T3	26		T13	4
all_values[29]	1759	1			T1	11		T3	31		T12	1
all_values[30]	1841	1			T1	7		T3	35		T12	1
all_values[31]	1782	1			T1	8		T3	31		T12	1
all_values[32]	1769	1			T1	6		T3	35		T13	5
all_values[33]	1758	1			T1	11		T3	40		T12	2
all_values[34]	1773	1			T1	6		T3	42		T13	3
all_values[35]	1772	1			T1	6		T3	49		T12	1
all_values[36]	1761	1			T1	2		T3	26		T12	1
all_values[37]	1760	1			T1	9		T3	36		T13	7
all_values[38]	1780	1			T1	6		T3	44		T13	5
all_values[39]	1738	1			T1	5		T3	34		T13	5
all_values[40]	1785	1			T1	7		T3	28		T12	1
all_values[41]	1722	1			T1	5		T3	37		T12	1
all_values[42]	1742	1			T1	6		T3	29		T12	1
all_values[43]	1697	1			T1	6		T3	34		T13	7
all_values[44]	1712	1			T1	8		T3	25		T13	7
all_values[45]	1668	1			T1	1		T3	42		T13	3
all_values[46]	1813	1			T1	4		T3	41		T12	2
all_values[47]	1745	1			T1	5		T3	42		T13	4
all_values[48]	1740	1			T1	7		T3	28		T12	1
all_values[49]	1782	1			T1	9		T3	43		T12	1
all_values[50]	1819	1			T1	8		T3	28		T12	1
all_values[51]	1791	1			T1	4		T3	29		T12	2
all_values[52]	1718	1			T1	9		T3	35		T12	1
all_values[53]	1779	1			T1	7		T3	35		T13	6
all_values[54]	1766	1			T1	6		T3	38		T12	2
all_values[55]	1788	1			T1	3		T3	38		T12	3
all_values[56]	1719	1			T1	3		T3	34		T12	1
all_values[57]	1809	1			T1	5		T3	32		T13	4
all_values[58]	1778	1			T1	5		T3	31		T13	2
all_values[59]	1787	1			T1	8		T3	40		T12	3
all_values[60]	1748	1			T1	4		T3	37		T13	4
all_values[61]	1722	1			T1	4		T3	32		T12	2
all_values[62]	1721	1			T1	5		T3	31		T13	6
all_values[63]	1762	1			T1	3		T3	37		T12	1