Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1692	1			T6	3		T7	14		T14	15
all_values[1]	1764	1			T6	4		T7	13		T11	1
all_values[2]	1684	1			T6	1		T7	11		T11	1
all_values[3]	1727	1			T6	7		T7	11		T14	24
all_values[4]	1711	1			T6	5		T7	17		T11	1
all_values[5]	1626	1			T6	1		T7	7		T14	22
all_values[6]	1711	1			T6	2		T7	9		T14	23
all_values[7]	1701	1			T6	3		T7	11		T11	1
all_values[8]	1689	1			T7	7		T11	3		T14	22
all_values[9]	1671	1			T6	2		T7	13		T11	1
all_values[10]	1723	1			T6	5		T7	12		T11	1
all_values[11]	1713	1			T6	5		T7	13		T11	1
all_values[12]	1673	1			T6	3		T7	17		T14	24
all_values[13]	1622	1			T6	4		T7	14		T11	2
all_values[14]	1700	1			T6	4		T7	14		T11	2
all_values[15]	1684	1			T6	3		T7	5		T14	27
all_values[16]	1739	1			T6	2		T7	12		T11	2
all_values[17]	1746	1			T6	1		T7	13		T14	19
all_values[18]	1691	1			T6	3		T7	12		T11	1
all_values[19]	1690	1			T6	3		T7	20		T14	31
all_values[20]	1733	1			T6	2		T7	12		T11	2
all_values[21]	1627	1			T6	5		T7	11		T14	32
all_values[22]	1690	1			T6	1		T7	11		T14	18
all_values[23]	1666	1			T6	3		T7	17		T11	1
all_values[24]	1618	1			T6	7		T7	10		T14	23
all_values[25]	1661	1			T6	5		T7	19		T14	25
all_values[26]	1673	1			T6	2		T7	14		T11	1
all_values[27]	1728	1			T7	24		T14	16		T17	13
all_values[28]	1744	1			T6	1		T7	14		T11	1
all_values[29]	1660	1			T6	1		T7	10		T14	22
all_values[30]	1723	1			T7	16		T11	1		T14	14
all_values[31]	1672	1			T6	3		T7	11		T11	1
all_values[32]	1694	1			T6	4		T7	13		T14	31
all_values[33]	1656	1			T6	1		T7	16		T11	1
all_values[34]	1640	1			T6	2		T7	20		T14	20
all_values[35]	1675	1			T6	2		T7	15		T11	2
all_values[36]	1666	1			T6	7		T7	10		T14	15
all_values[37]	1682	1			T7	12		T11	2		T14	22
all_values[38]	1696	1			T6	5		T7	17		T14	16
all_values[39]	1692	1			T6	2		T7	17		T11	1
all_values[40]	1739	1			T6	2		T7	10		T14	18
all_values[41]	1692	1			T6	2		T7	7		T14	21
all_values[42]	1696	1			T6	1		T7	15		T11	1
all_values[43]	1679	1			T6	4		T7	13		T11	1
all_values[44]	1669	1			T6	1		T7	18		T11	1
all_values[45]	1744	1			T6	3		T7	12		T11	1
all_values[46]	1663	1			T6	7		T7	12		T14	22
all_values[47]	1733	1			T6	3		T7	12		T11	1
all_values[48]	1706	1			T6	5		T7	15		T11	1
all_values[49]	1667	1			T6	3		T7	10		T11	1
all_values[50]	1756	1			T6	5		T7	18		T11	1
all_values[51]	1680	1			T6	2		T7	10		T11	1
all_values[52]	1663	1			T6	4		T7	10		T14	13
all_values[53]	1672	1			T6	2		T7	14		T11	2
all_values[54]	1681	1			T7	8		T11	4		T14	22
all_values[55]	1819	1			T6	6		T7	11		T11	4
all_values[56]	1712	1			T6	1		T7	16		T11	1
all_values[57]	1696	1			T6	1		T7	12		T14	24
all_values[58]	1704	1			T6	2		T7	18		T14	27
all_values[59]	1729	1			T6	1		T7	9		T11	4
all_values[60]	1727	1			T6	1		T7	7		T11	1
all_values[61]	1601	1			T6	1		T7	12		T14	19
all_values[62]	1748	1			T6	4		T7	20		T11	2
all_values[63]	1698	1			T6	3		T7	8		T11	2