| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.21 | 99.26 | 90.10 | 98.80 | 95.82 | 99.26 | 100.00 |
| T762 | /workspace/coverage/xbar_build_mode/29.xbar_smoke.2728175706 | Mar 07 01:38:54 PM PST 24 | Mar 07 01:38:59 PM PST 24 | 60533359 ps | ||
| T763 | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.1479975110 | Mar 07 01:39:46 PM PST 24 | Mar 07 01:41:02 PM PST 24 | 3171005201 ps | ||
| T107 | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.100005363 | Mar 07 01:37:50 PM PST 24 | Mar 07 01:41:10 PM PST 24 | 9259980159 ps | ||
| T764 | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2235688930 | Mar 07 01:37:11 PM PST 24 | Mar 07 01:39:03 PM PST 24 | 696032875 ps | ||
| T765 | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3843892833 | Mar 07 01:38:57 PM PST 24 | Mar 07 01:39:24 PM PST 24 | 184233123 ps | ||
| T766 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1775028038 | Mar 07 01:40:24 PM PST 24 | Mar 07 01:40:55 PM PST 24 | 7541242550 ps | ||
| T767 | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.320614622 | Mar 07 01:39:46 PM PST 24 | Mar 07 01:40:00 PM PST 24 | 329599012 ps | ||
| T768 | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2277653001 | Mar 07 01:40:10 PM PST 24 | Mar 07 01:42:18 PM PST 24 | 2234654577 ps | ||
| T769 | /workspace/coverage/xbar_build_mode/6.xbar_error_random.935934113 | Mar 07 01:37:32 PM PST 24 | Mar 07 01:37:54 PM PST 24 | 184680445 ps | ||
| T770 | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2172635726 | Mar 07 01:39:04 PM PST 24 | Mar 07 01:47:20 PM PST 24 | 10120756650 ps | ||
| T771 | /workspace/coverage/xbar_build_mode/25.xbar_smoke.1958110925 | Mar 07 01:38:32 PM PST 24 | Mar 07 01:38:36 PM PST 24 | 166536906 ps | ||
| T772 | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.25977546 | Mar 07 01:39:20 PM PST 24 | Mar 07 01:40:54 PM PST 24 | 3075157431 ps | ||
| T773 | /workspace/coverage/xbar_build_mode/5.xbar_random.2015185647 | Mar 07 01:37:32 PM PST 24 | Mar 07 01:37:41 PM PST 24 | 72151254 ps | ||
| T774 | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.956041324 | Mar 07 01:37:40 PM PST 24 | Mar 07 01:38:11 PM PST 24 | 10158628679 ps | ||
| T775 | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2642708849 | Mar 07 01:39:30 PM PST 24 | Mar 07 01:40:02 PM PST 24 | 9561068004 ps | ||
| T776 | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1719357771 | Mar 07 01:37:27 PM PST 24 | Mar 07 01:37:36 PM PST 24 | 99164312 ps | ||
| T777 | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3922701681 | Mar 07 01:37:25 PM PST 24 | Mar 07 01:37:40 PM PST 24 | 195426274 ps | ||
| T778 | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2860817382 | Mar 07 01:37:40 PM PST 24 | Mar 07 01:37:50 PM PST 24 | 235794112 ps | ||
| T779 | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2698545491 | Mar 07 01:38:15 PM PST 24 | Mar 07 01:38:22 PM PST 24 | 73554028 ps | ||
| T780 | /workspace/coverage/xbar_build_mode/6.xbar_same_source.1941072651 | Mar 07 01:37:27 PM PST 24 | Mar 07 01:38:03 PM PST 24 | 1920965409 ps | ||
| T781 | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.80684040 | Mar 07 01:39:03 PM PST 24 | Mar 07 01:39:33 PM PST 24 | 5977034844 ps | ||
| T782 | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.25209388 | Mar 07 01:39:33 PM PST 24 | Mar 07 01:39:47 PM PST 24 | 134154685 ps | ||
| T783 | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3880856695 | Mar 07 01:38:21 PM PST 24 | Mar 07 01:38:45 PM PST 24 | 73802039 ps | ||
| T784 | /workspace/coverage/xbar_build_mode/7.xbar_same_source.1016441080 | Mar 07 01:37:36 PM PST 24 | Mar 07 01:37:46 PM PST 24 | 578096783 ps | ||
| T785 | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2912577474 | Mar 07 01:37:11 PM PST 24 | Mar 07 01:41:08 PM PST 24 | 2120849484 ps | ||
| T28 | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.384037596 | Mar 07 01:38:59 PM PST 24 | Mar 07 01:40:20 PM PST 24 | 190701987 ps | ||
| T786 | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3154592161 | Mar 07 01:37:11 PM PST 24 | Mar 07 01:37:21 PM PST 24 | 65342675 ps | ||
| T787 | /workspace/coverage/xbar_build_mode/0.xbar_random.4226932243 | Mar 07 01:36:57 PM PST 24 | Mar 07 01:37:07 PM PST 24 | 95045440 ps | ||
| T788 | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2970250563 | Mar 07 01:39:30 PM PST 24 | Mar 07 01:39:55 PM PST 24 | 609302076 ps | ||
| T789 | /workspace/coverage/xbar_build_mode/19.xbar_same_source.3123600451 | Mar 07 01:38:17 PM PST 24 | Mar 07 01:38:23 PM PST 24 | 206194253 ps | ||
| T790 | /workspace/coverage/xbar_build_mode/40.xbar_error_random.3598186163 | Mar 07 01:39:46 PM PST 24 | Mar 07 01:40:04 PM PST 24 | 138858689 ps | ||
| T791 | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3167824328 | Mar 07 01:37:54 PM PST 24 | Mar 07 01:40:03 PM PST 24 | 3676776488 ps | ||
| T792 | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.1260885509 | Mar 07 01:37:47 PM PST 24 | Mar 07 01:41:22 PM PST 24 | 36388118839 ps | ||
| T793 | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3699899933 | Mar 07 01:38:54 PM PST 24 | Mar 07 01:40:45 PM PST 24 | 12332693495 ps | ||
| T794 | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1833786740 | Mar 07 01:39:59 PM PST 24 | Mar 07 01:41:04 PM PST 24 | 2896791811 ps | ||
| T795 | /workspace/coverage/xbar_build_mode/16.xbar_error_random.1956550091 | Mar 07 01:38:02 PM PST 24 | Mar 07 01:38:33 PM PST 24 | 2965927870 ps | ||
| T796 | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3336234967 | Mar 07 01:39:42 PM PST 24 | Mar 07 01:39:53 PM PST 24 | 243887216 ps | ||
| T797 | /workspace/coverage/xbar_build_mode/43.xbar_smoke.888855937 | Mar 07 01:39:52 PM PST 24 | Mar 07 01:39:55 PM PST 24 | 35057824 ps | ||
| T798 | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.750247411 | Mar 07 01:39:32 PM PST 24 | Mar 07 01:39:59 PM PST 24 | 560124730 ps | ||
| T799 | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.4270135226 | Mar 07 01:38:07 PM PST 24 | Mar 07 01:38:20 PM PST 24 | 291672570 ps | ||
| T800 | /workspace/coverage/xbar_build_mode/3.xbar_error_random.1531570357 | Mar 07 01:37:28 PM PST 24 | Mar 07 01:37:45 PM PST 24 | 293830590 ps | ||
| T801 | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3571931802 | Mar 07 01:38:58 PM PST 24 | Mar 07 01:39:18 PM PST 24 | 259040153 ps | ||
| T802 | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3685774417 | Mar 07 01:37:38 PM PST 24 | Mar 07 01:38:03 PM PST 24 | 284553844 ps | ||
| T803 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.414812611 | Mar 07 01:40:34 PM PST 24 | Mar 07 01:44:49 PM PST 24 | 2298216687 ps | ||
| T804 | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3821399031 | Mar 07 01:37:58 PM PST 24 | Mar 07 01:38:38 PM PST 24 | 2715981051 ps | ||
| T805 | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1242425675 | Mar 07 01:37:38 PM PST 24 | Mar 07 01:37:51 PM PST 24 | 703065926 ps | ||
| T806 | /workspace/coverage/xbar_build_mode/37.xbar_error_random.3998571807 | Mar 07 01:39:31 PM PST 24 | Mar 07 01:39:50 PM PST 24 | 277449353 ps | ||
| T108 | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2396055498 | Mar 07 01:38:01 PM PST 24 | Mar 07 01:41:47 PM PST 24 | 32569237747 ps | ||
| T807 | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3999229293 | Mar 07 01:38:44 PM PST 24 | Mar 07 01:39:01 PM PST 24 | 186056627 ps | ||
| T808 | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2751021890 | Mar 07 01:39:44 PM PST 24 | Mar 07 01:43:04 PM PST 24 | 22003200441 ps | ||
| T210 | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2331691873 | Mar 07 01:37:40 PM PST 24 | Mar 07 01:37:53 PM PST 24 | 109638840 ps | ||
| T281 | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.599326261 | Mar 07 01:40:12 PM PST 24 | Mar 07 01:43:14 PM PST 24 | 2113106885 ps | ||
| T809 | /workspace/coverage/xbar_build_mode/48.xbar_random.4230301534 | Mar 07 01:40:21 PM PST 24 | Mar 07 01:40:43 PM PST 24 | 683891522 ps | ||
| T810 | /workspace/coverage/xbar_build_mode/28.xbar_error_random.3751334045 | Mar 07 01:38:54 PM PST 24 | Mar 07 01:39:21 PM PST 24 | 778069239 ps | ||
| T811 | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.908524958 | Mar 07 01:37:28 PM PST 24 | Mar 07 01:40:49 PM PST 24 | 27990614804 ps | ||
| T812 | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.4102512167 | Mar 07 01:38:33 PM PST 24 | Mar 07 01:40:02 PM PST 24 | 18983383330 ps | ||
| T813 | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2639333504 | Mar 07 01:37:33 PM PST 24 | Mar 07 01:37:55 PM PST 24 | 196471653 ps | ||
| T814 | /workspace/coverage/xbar_build_mode/17.xbar_random.2008712007 | Mar 07 01:38:03 PM PST 24 | Mar 07 01:38:30 PM PST 24 | 612585479 ps | ||
| T815 | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2384179925 | Mar 07 01:37:48 PM PST 24 | Mar 07 01:42:22 PM PST 24 | 35744272914 ps | ||
| T816 | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2877300596 | Mar 07 01:37:52 PM PST 24 | Mar 07 01:38:11 PM PST 24 | 3788445125 ps | ||
| T817 | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1018644722 | Mar 07 01:38:08 PM PST 24 | Mar 07 01:44:40 PM PST 24 | 127268103676 ps | ||
| T818 | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.727700069 | Mar 07 01:39:18 PM PST 24 | Mar 07 01:39:23 PM PST 24 | 28953679 ps | ||
| T819 | /workspace/coverage/xbar_build_mode/20.xbar_random.3651437751 | Mar 07 01:38:21 PM PST 24 | Mar 07 01:38:34 PM PST 24 | 625058844 ps | ||
| T820 | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.962047256 | Mar 07 01:37:49 PM PST 24 | Mar 07 01:39:32 PM PST 24 | 19317553666 ps | ||
| T821 | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2444829186 | Mar 07 01:37:36 PM PST 24 | Mar 07 01:37:39 PM PST 24 | 29330884 ps | ||
| T822 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3302066708 | Mar 07 01:38:03 PM PST 24 | Mar 07 01:38:43 PM PST 24 | 6964913599 ps | ||
| T823 | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2082047203 | Mar 07 01:38:19 PM PST 24 | Mar 07 01:38:25 PM PST 24 | 142584787 ps | ||
| T824 | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.935504195 | Mar 07 01:37:39 PM PST 24 | Mar 07 01:37:57 PM PST 24 | 140961664 ps | ||
| T825 | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3287051993 | Mar 07 01:38:19 PM PST 24 | Mar 07 01:40:38 PM PST 24 | 47211425666 ps | ||
| T826 | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3800876606 | Mar 07 01:40:21 PM PST 24 | Mar 07 01:40:24 PM PST 24 | 49865004 ps | ||
| T827 | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.3243196059 | Mar 07 01:38:44 PM PST 24 | Mar 07 01:39:10 PM PST 24 | 3431349401 ps | ||
| T828 | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.4123463360 | Mar 07 01:38:01 PM PST 24 | Mar 07 01:39:11 PM PST 24 | 3658451425 ps | ||
| T212 | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3679600978 | Mar 07 01:38:31 PM PST 24 | Mar 07 01:40:15 PM PST 24 | 1327438947 ps | ||
| T185 | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1082454331 | Mar 07 01:39:51 PM PST 24 | Mar 07 01:42:01 PM PST 24 | 18252017083 ps | ||
| T829 | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2526622932 | Mar 07 01:38:30 PM PST 24 | Mar 07 01:39:10 PM PST 24 | 1073621633 ps | ||
| T830 | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2759394155 | Mar 07 01:40:13 PM PST 24 | Mar 07 01:40:44 PM PST 24 | 4917749607 ps | ||
| T211 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.626121287 | Mar 07 01:39:43 PM PST 24 | Mar 07 01:43:27 PM PST 24 | 1724742279 ps | ||
| T831 | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3640325355 | Mar 07 01:38:04 PM PST 24 | Mar 07 01:38:30 PM PST 24 | 311712159 ps | ||
| T832 | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1117114680 | Mar 07 01:39:17 PM PST 24 | Mar 07 01:39:50 PM PST 24 | 7035088453 ps | ||
| T833 | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1112086568 | Mar 07 01:38:58 PM PST 24 | Mar 07 01:39:08 PM PST 24 | 61064514 ps | ||
| T834 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.960197528 | Mar 07 01:38:57 PM PST 24 | Mar 07 01:39:25 PM PST 24 | 4744031549 ps | ||
| T202 | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2680847105 | Mar 07 01:38:00 PM PST 24 | Mar 07 01:38:50 PM PST 24 | 279430021 ps | ||
| T835 | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2491619352 | Mar 07 01:39:45 PM PST 24 | Mar 07 01:39:59 PM PST 24 | 470059123 ps | ||
| T836 | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1744303460 | Mar 07 01:39:32 PM PST 24 | Mar 07 01:39:43 PM PST 24 | 66572950 ps | ||
| T837 | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1016434320 | Mar 07 01:39:29 PM PST 24 | Mar 07 01:39:37 PM PST 24 | 67301905 ps | ||
| T838 | /workspace/coverage/xbar_build_mode/27.xbar_error_random.3046711339 | Mar 07 01:38:42 PM PST 24 | Mar 07 01:39:12 PM PST 24 | 3845417415 ps | ||
| T839 | /workspace/coverage/xbar_build_mode/3.xbar_smoke.1692710866 | Mar 07 01:37:28 PM PST 24 | Mar 07 01:37:31 PM PST 24 | 198078163 ps | ||
| T840 | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2872138824 | Mar 07 01:40:22 PM PST 24 | Mar 07 01:40:32 PM PST 24 | 10568650 ps | ||
| T841 | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3364712893 | Mar 07 01:39:52 PM PST 24 | Mar 07 01:43:20 PM PST 24 | 4362118339 ps | ||
| T842 | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.50402161 | Mar 07 01:38:21 PM PST 24 | Mar 07 01:39:04 PM PST 24 | 5208984568 ps | ||
| T843 | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.4222937369 | Mar 07 01:39:05 PM PST 24 | Mar 07 01:39:44 PM PST 24 | 15314092726 ps | ||
| T844 | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1994364817 | Mar 07 01:37:47 PM PST 24 | Mar 07 01:41:13 PM PST 24 | 44358456612 ps | ||
| T845 | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2625361730 | Mar 07 01:37:38 PM PST 24 | Mar 07 01:46:11 PM PST 24 | 56416510917 ps | ||
| T846 | /workspace/coverage/xbar_build_mode/26.xbar_error_random.2876091828 | Mar 07 01:38:43 PM PST 24 | Mar 07 01:39:09 PM PST 24 | 783373893 ps | ||
| T847 | /workspace/coverage/xbar_build_mode/30.xbar_random.1908817267 | Mar 07 01:39:00 PM PST 24 | Mar 07 01:39:22 PM PST 24 | 263697166 ps | ||
| T848 | /workspace/coverage/xbar_build_mode/34.xbar_error_random.3879539447 | Mar 07 01:39:17 PM PST 24 | Mar 07 01:39:26 PM PST 24 | 345079905 ps | ||
| T849 | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1922696146 | Mar 07 01:39:53 PM PST 24 | Mar 07 01:42:50 PM PST 24 | 90328850236 ps | ||
| T850 | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1741114324 | Mar 07 01:38:00 PM PST 24 | Mar 07 01:41:07 PM PST 24 | 41591847912 ps | ||
| T186 | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.598030134 | Mar 07 01:38:11 PM PST 24 | Mar 07 01:41:16 PM PST 24 | 7858010374 ps | ||
| T851 | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.1542935188 | Mar 07 01:38:32 PM PST 24 | Mar 07 01:42:41 PM PST 24 | 41443885074 ps | ||
| T852 | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1310135854 | Mar 07 01:39:55 PM PST 24 | Mar 07 01:39:58 PM PST 24 | 28376043 ps | ||
| T853 | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1940398959 | Mar 07 01:39:41 PM PST 24 | Mar 07 01:42:42 PM PST 24 | 66312461834 ps | ||
| T854 | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2512684257 | Mar 07 01:40:11 PM PST 24 | Mar 07 01:46:14 PM PST 24 | 119665110497 ps | ||
| T855 | /workspace/coverage/xbar_build_mode/26.xbar_smoke.58580069 | Mar 07 01:38:43 PM PST 24 | Mar 07 01:38:46 PM PST 24 | 206128853 ps | ||
| T856 | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3158723083 | Mar 07 01:37:11 PM PST 24 | Mar 07 01:39:11 PM PST 24 | 1925510052 ps | ||
| T857 | /workspace/coverage/xbar_build_mode/47.xbar_same_source.3025890706 | Mar 07 01:40:15 PM PST 24 | Mar 07 01:40:36 PM PST 24 | 583586813 ps | ||
| T858 | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3786361941 | Mar 07 01:38:42 PM PST 24 | Mar 07 01:43:00 PM PST 24 | 28326789078 ps | ||
| T859 | /workspace/coverage/xbar_build_mode/13.xbar_random.4089044883 | Mar 07 01:37:47 PM PST 24 | Mar 07 01:37:49 PM PST 24 | 18524190 ps | ||
| T860 | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.350759341 | Mar 07 01:38:19 PM PST 24 | Mar 07 01:38:58 PM PST 24 | 13618891728 ps | ||
| T861 | /workspace/coverage/xbar_build_mode/39.xbar_smoke.2315488754 | Mar 07 01:39:34 PM PST 24 | Mar 07 01:39:36 PM PST 24 | 25258626 ps | ||
| T862 | /workspace/coverage/xbar_build_mode/10.xbar_error_random.184472614 | Mar 07 01:37:38 PM PST 24 | Mar 07 01:37:47 PM PST 24 | 241252139 ps | ||
| T863 | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3164640569 | Mar 07 01:39:41 PM PST 24 | Mar 07 01:42:01 PM PST 24 | 10863383912 ps | ||
| T864 | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.75730991 | Mar 07 01:37:59 PM PST 24 | Mar 07 01:38:02 PM PST 24 | 44390940 ps | ||
| T865 | /workspace/coverage/xbar_build_mode/38.xbar_smoke.2684565363 | Mar 07 01:39:33 PM PST 24 | Mar 07 01:39:37 PM PST 24 | 375403651 ps | ||
| T866 | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2864664829 | Mar 07 01:38:20 PM PST 24 | Mar 07 01:38:23 PM PST 24 | 169015063 ps | ||
| T109 | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.4128545418 | Mar 07 01:37:26 PM PST 24 | Mar 07 01:38:41 PM PST 24 | 23058156882 ps | ||
| T867 | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2517038160 | Mar 07 01:38:32 PM PST 24 | Mar 07 01:38:47 PM PST 24 | 141746373 ps | ||
| T868 | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.2393602669 | Mar 07 01:38:29 PM PST 24 | Mar 07 01:38:35 PM PST 24 | 85405118 ps | ||
| T869 | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3496095460 | Mar 07 01:40:20 PM PST 24 | Mar 07 01:40:36 PM PST 24 | 402559302 ps | ||
| T870 | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1587985863 | Mar 07 01:37:26 PM PST 24 | Mar 07 01:44:14 PM PST 24 | 6110258636 ps | ||
| T871 | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2933971117 | Mar 07 01:40:34 PM PST 24 | Mar 07 01:44:56 PM PST 24 | 2848825615 ps | ||
| T872 | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3609505924 | Mar 07 01:38:44 PM PST 24 | Mar 07 01:43:38 PM PST 24 | 29378266077 ps | ||
| T873 | /workspace/coverage/xbar_build_mode/45.xbar_smoke.617985456 | Mar 07 01:40:03 PM PST 24 | Mar 07 01:40:06 PM PST 24 | 96930996 ps | ||
| T874 | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1013129340 | Mar 07 01:40:04 PM PST 24 | Mar 07 01:41:21 PM PST 24 | 5787962987 ps | ||
| T875 | /workspace/coverage/xbar_build_mode/43.xbar_error_random.3163090852 | Mar 07 01:39:52 PM PST 24 | Mar 07 01:39:59 PM PST 24 | 196526631 ps | ||
| T876 | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3724753654 | Mar 07 01:38:57 PM PST 24 | Mar 07 01:39:01 PM PST 24 | 79799217 ps | ||
| T877 | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1941568044 | Mar 07 01:38:22 PM PST 24 | Mar 07 01:41:00 PM PST 24 | 11217503505 ps | ||
| T878 | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3461254735 | Mar 07 01:37:32 PM PST 24 | Mar 07 01:38:01 PM PST 24 | 9501607081 ps | ||
| T879 | /workspace/coverage/xbar_build_mode/29.xbar_error_random.1634050686 | Mar 07 01:38:57 PM PST 24 | Mar 07 01:39:13 PM PST 24 | 171751135 ps | ||
| T880 | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3743358164 | Mar 07 01:39:59 PM PST 24 | Mar 07 01:45:04 PM PST 24 | 83604917610 ps | ||
| T881 | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2451787483 | Mar 07 01:40:10 PM PST 24 | Mar 07 01:43:45 PM PST 24 | 45119313984 ps | ||
| T882 | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.72080556 | Mar 07 01:37:37 PM PST 24 | Mar 07 01:38:05 PM PST 24 | 6472697233 ps | ||
| T883 | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.4034721133 | Mar 07 01:37:36 PM PST 24 | Mar 07 01:37:38 PM PST 24 | 36950771 ps | ||
| T884 | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.4215037197 | Mar 07 01:38:20 PM PST 24 | Mar 07 01:38:47 PM PST 24 | 4036266392 ps | ||
| T885 | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3214102193 | Mar 07 01:39:42 PM PST 24 | Mar 07 01:39:57 PM PST 24 | 710056396 ps | ||
| T886 | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1913177540 | Mar 07 01:39:28 PM PST 24 | Mar 07 01:42:27 PM PST 24 | 36575010520 ps | ||
| T887 | /workspace/coverage/xbar_build_mode/44.xbar_error_random.3981539776 | Mar 07 01:40:01 PM PST 24 | Mar 07 01:40:23 PM PST 24 | 225604363 ps | ||
| T888 | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1179368135 | Mar 07 01:37:49 PM PST 24 | Mar 07 01:41:33 PM PST 24 | 11032550562 ps | ||
| T889 | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.392940021 | Mar 07 01:38:08 PM PST 24 | Mar 07 01:47:16 PM PST 24 | 88325972563 ps | ||
| T890 | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2249844486 | Mar 07 01:37:36 PM PST 24 | Mar 07 01:40:24 PM PST 24 | 86918974777 ps | ||
| T891 | /workspace/coverage/xbar_build_mode/33.xbar_smoke.1510519876 | Mar 07 01:39:20 PM PST 24 | Mar 07 01:39:22 PM PST 24 | 28028526 ps | ||
| T892 | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2617674257 | Mar 07 01:39:18 PM PST 24 | Mar 07 01:41:41 PM PST 24 | 8587034704 ps | ||
| T893 | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.4284583156 | Mar 07 01:38:00 PM PST 24 | Mar 07 01:38:16 PM PST 24 | 23737592 ps | ||
| T894 | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.408379588 | Mar 07 01:39:05 PM PST 24 | Mar 07 01:39:22 PM PST 24 | 591047779 ps | ||
| T895 | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.373029421 | Mar 07 01:39:16 PM PST 24 | Mar 07 01:39:41 PM PST 24 | 877381948 ps | ||
| T896 | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2400289525 | Mar 07 01:37:36 PM PST 24 | Mar 07 01:39:46 PM PST 24 | 23060335608 ps | ||
| T897 | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.660234665 | Mar 07 01:37:34 PM PST 24 | Mar 07 01:37:44 PM PST 24 | 62595381 ps | ||
| T898 | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2446281489 | Mar 07 01:38:55 PM PST 24 | Mar 07 01:39:06 PM PST 24 | 80595891 ps | ||
| T899 | /workspace/coverage/xbar_build_mode/1.xbar_random.2722468063 | Mar 07 01:37:09 PM PST 24 | Mar 07 01:37:49 PM PST 24 | 894715366 ps | ||
| T900 | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.42334706 | Mar 07 01:37:30 PM PST 24 | Mar 07 01:37:42 PM PST 24 | 117144707 ps |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2708183811 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 447451533 ps |
| CPU time | 16.35 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:39:47 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-03289ae1-5148-4ac8-b246-b4022a8d6650 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2708183811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2708183811 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1911332777 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 93458603153 ps |
| CPU time | 606.06 seconds |
| Started | Mar 07 01:37:08 PM PST 24 |
| Finished | Mar 07 01:47:14 PM PST 24 |
| Peak memory | 211396 kb |
| Host | smart-97908824-59e4-4215-84a2-e7b961489a41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1911332777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo w_rsp.1911332777 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3446104874 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 73439551086 ps |
| CPU time | 558.39 seconds |
| Started | Mar 07 01:38:41 PM PST 24 |
| Finished | Mar 07 01:47:59 PM PST 24 |
| Peak memory | 205708 kb |
| Host | smart-1e3bd67b-a080-488a-8157-618e21ce7ff2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3446104874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl ow_rsp.3446104874 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.4237347227 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 29458524465 ps |
| CPU time | 167.79 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:41:10 PM PST 24 |
| Peak memory | 211348 kb |
| Host | smart-16d094a4-50d4-4eac-be88-3e7529a58225 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4237347227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl ow_rsp.4237347227 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random.3332018185 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 194555109 ps |
| CPU time | 32.64 seconds |
| Started | Mar 07 01:40:10 PM PST 24 |
| Finished | Mar 07 01:40:44 PM PST 24 |
| Peak memory | 204816 kb |
| Host | smart-639558a2-fc2e-4007-8df5-097cee299844 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3332018185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3332018185 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2550464846 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 17084881376 ps |
| CPU time | 163.53 seconds |
| Started | Mar 07 01:38:30 PM PST 24 |
| Finished | Mar 07 01:41:14 PM PST 24 |
| Peak memory | 208712 kb |
| Host | smart-e71dee83-5777-4d17-9161-0c338261ac2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2550464846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2550464846 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.209928784 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1970418370 ps |
| CPU time | 177.03 seconds |
| Started | Mar 07 01:40:04 PM PST 24 |
| Finished | Mar 07 01:43:02 PM PST 24 |
| Peak memory | 210448 kb |
| Host | smart-5d8514a1-33ee-4b47-af58-e3a6b7a06998 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=209928784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_res et_error.209928784 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2781522193 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 110727911304 ps |
| CPU time | 526.89 seconds |
| Started | Mar 07 01:39:53 PM PST 24 |
| Finished | Mar 07 01:48:40 PM PST 24 |
| Peak memory | 211256 kb |
| Host | smart-670555b0-25eb-4a1f-ba91-69a16ab22f92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2781522193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl ow_rsp.2781522193 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.3688307805 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 7313012262 ps |
| CPU time | 411.53 seconds |
| Started | Mar 07 01:38:00 PM PST 24 |
| Finished | Mar 07 01:44:52 PM PST 24 |
| Peak memory | 208588 kb |
| Host | smart-9802c418-97f7-4684-ad6b-8d17be9724f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3688307805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran d_reset.3688307805 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.4253249956 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 51531789765 ps |
| CPU time | 218.37 seconds |
| Started | Mar 07 01:38:42 PM PST 24 |
| Finished | Mar 07 01:42:21 PM PST 24 |
| Peak memory | 204532 kb |
| Host | smart-aa6653c0-d008-4782-af97-aab846e66b91 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253249956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4253249956 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.3207553021 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3317282040 ps |
| CPU time | 49.82 seconds |
| Started | Mar 07 01:39:59 PM PST 24 |
| Finished | Mar 07 01:40:50 PM PST 24 |
| Peak memory | 205432 kb |
| Host | smart-2583deda-6629-48d3-92e3-8b3e401ff294 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3207553021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3207553021 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1936296241 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 79166286831 ps |
| CPU time | 433.05 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:44:39 PM PST 24 |
| Peak memory | 206700 kb |
| Host | smart-64d50cf5-ce9c-401c-8f10-6c100c1c29b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1936296241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slo w_rsp.1936296241 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.4045315896 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 4441094551 ps |
| CPU time | 301.28 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:42:27 PM PST 24 |
| Peak memory | 210916 kb |
| Host | smart-19db37ea-8004-494f-a385-ef42d2a9288f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4045315896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand _reset.4045315896 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3902400437 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 451156844 ps |
| CPU time | 154.78 seconds |
| Started | Mar 07 01:39:03 PM PST 24 |
| Finished | Mar 07 01:41:38 PM PST 24 |
| Peak memory | 208212 kb |
| Host | smart-c3097ebd-219f-46c5-bca8-2a33fcc97945 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3902400437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran d_reset.3902400437 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3378551924 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9825639675 ps |
| CPU time | 418.87 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:45:20 PM PST 24 |
| Peak memory | 224208 kb |
| Host | smart-d909a243-0333-46e6-ba83-9c65564b3bba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3378551924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_re set_error.3378551924 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2590717881 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 238465466 ps |
| CPU time | 77.81 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:40:23 PM PST 24 |
| Peak memory | 207444 kb |
| Host | smart-a4b8f887-aca0-4eab-a0f8-680b98c062a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2590717881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_ran d_reset.2590717881 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3192935777 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 213093871083 ps |
| CPU time | 682.51 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:49:01 PM PST 24 |
| Peak memory | 206940 kb |
| Host | smart-bc113186-4b15-4ba6-8b95-d54c29691d27 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3192935777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl ow_rsp.3192935777 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.1186178281 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 565928704 ps |
| CPU time | 185.14 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:40:40 PM PST 24 |
| Peak memory | 208000 kb |
| Host | smart-ee0609d1-c75b-4baa-9c9d-20afb9e59e5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1186178281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand _reset.1186178281 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all.2343405244 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3489781123 ps |
| CPU time | 101.5 seconds |
| Started | Mar 07 01:39:12 PM PST 24 |
| Finished | Mar 07 01:40:53 PM PST 24 |
| Peak memory | 206688 kb |
| Host | smart-8ebde3a2-54b6-4661-8142-17bbd17869d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2343405244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2343405244 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.2101056141 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5580722198 ps |
| CPU time | 545.8 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:47:37 PM PST 24 |
| Peak memory | 208464 kb |
| Host | smart-45fa5cb8-1f4d-454b-823b-e353e7d0adc9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2101056141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran d_reset.2101056141 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.384037596 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 190701987 ps |
| CPU time | 81.6 seconds |
| Started | Mar 07 01:38:59 PM PST 24 |
| Finished | Mar 07 01:40:20 PM PST 24 |
| Peak memory | 206532 kb |
| Host | smart-01b69f29-f899-40e2-bc81-d06068a9eb04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=384037596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand _reset.384037596 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.4044097525 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5377354293 ps |
| CPU time | 89.55 seconds |
| Started | Mar 07 01:39:19 PM PST 24 |
| Finished | Mar 07 01:40:50 PM PST 24 |
| Peak memory | 208116 kb |
| Host | smart-39c03826-b7d1-4965-907d-a0fdccda0a77 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4044097525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re set_error.4044097525 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.3505378682 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2881962080 ps |
| CPU time | 18.94 seconds |
| Started | Mar 07 01:38:30 PM PST 24 |
| Finished | Mar 07 01:38:50 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-d687af3e-8884-4d06-bcbe-2880198c21fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3505378682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3505378682 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.100005363 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 9259980159 ps |
| CPU time | 200.37 seconds |
| Started | Mar 07 01:37:50 PM PST 24 |
| Finished | Mar 07 01:41:10 PM PST 24 |
| Peak memory | 208188 kb |
| Host | smart-8d263247-7ceb-42ef-8542-325dd65a33c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=100005363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand _reset.100005363 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random.3774401565 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1435090969 ps |
| CPU time | 37.57 seconds |
| Started | Mar 07 01:37:42 PM PST 24 |
| Finished | Mar 07 01:38:21 PM PST 24 |
| Peak memory | 204052 kb |
| Host | smart-ba5c7ad6-f56c-484c-9e29-da6ee745d0f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3774401565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3774401565 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.3151077621 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 141004328 ps |
| CPU time | 22.26 seconds |
| Started | Mar 07 01:37:14 PM PST 24 |
| Finished | Mar 07 01:37:36 PM PST 24 |
| Peak memory | 205556 kb |
| Host | smart-6e9b763f-f083-4fb5-add4-fd820b357042 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3151077621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3151077621 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3154592161 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 65342675 ps |
| CPU time | 10.62 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:37:21 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-e0d141c0-ccab-40fe-a6d1-2c1bdad983d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3154592161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3154592161 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_error_random.715391497 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 108850859 ps |
| CPU time | 4.76 seconds |
| Started | Mar 07 01:37:10 PM PST 24 |
| Finished | Mar 07 01:37:15 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-f6d1781c-29e2-44c8-88e3-c2082eafab44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=715391497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.715391497 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random.4226932243 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 95045440 ps |
| CPU time | 9.89 seconds |
| Started | Mar 07 01:36:57 PM PST 24 |
| Finished | Mar 07 01:37:07 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-2b32a593-61ba-4ecd-b3a8-028282ea03a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4226932243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.4226932243 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3788925058 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 46142956099 ps |
| CPU time | 209.14 seconds |
| Started | Mar 07 01:37:10 PM PST 24 |
| Finished | Mar 07 01:40:39 PM PST 24 |
| Peak memory | 204516 kb |
| Host | smart-5dc1adce-6a3a-4c9f-82ae-324f5111b67b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788925058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3788925058 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.345194437 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 9969593386 ps |
| CPU time | 72.92 seconds |
| Started | Mar 07 01:37:12 PM PST 24 |
| Finished | Mar 07 01:38:25 PM PST 24 |
| Peak memory | 211404 kb |
| Host | smart-e1640510-512c-4ee2-b9ba-6e52a2192949 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=345194437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.345194437 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.3260078580 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 131523249 ps |
| CPU time | 14.74 seconds |
| Started | Mar 07 01:36:56 PM PST 24 |
| Finished | Mar 07 01:37:11 PM PST 24 |
| Peak memory | 204304 kb |
| Host | smart-5d7b872b-fb1f-4e9f-81b4-bf237dc4360a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260078580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3260078580 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_same_source.2298122192 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 276639939 ps |
| CPU time | 6.14 seconds |
| Started | Mar 07 01:37:10 PM PST 24 |
| Finished | Mar 07 01:37:16 PM PST 24 |
| Peak memory | 203224 kb |
| Host | smart-ea252500-e44e-4e58-9fd4-113832ed3831 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2298122192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2298122192 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke.2545871256 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 131408295 ps |
| CPU time | 3 seconds |
| Started | Mar 07 01:36:57 PM PST 24 |
| Finished | Mar 07 01:37:00 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-86962194-7ebe-4a2a-bda5-4ec3d66f2cb2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2545871256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2545871256 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2433434754 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 34318889609 ps |
| CPU time | 41.56 seconds |
| Started | Mar 07 01:36:56 PM PST 24 |
| Finished | Mar 07 01:37:38 PM PST 24 |
| Peak memory | 203180 kb |
| Host | smart-8aa8d33f-0fba-4d97-b849-19abd0a37958 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433434754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2433434754 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.431766826 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 4210941357 ps |
| CPU time | 28.89 seconds |
| Started | Mar 07 01:36:56 PM PST 24 |
| Finished | Mar 07 01:37:26 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-a0a9415a-021c-42d5-81ff-b25fe3763b4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=431766826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.431766826 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3764626219 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 46184777 ps |
| CPU time | 2.74 seconds |
| Started | Mar 07 01:36:57 PM PST 24 |
| Finished | Mar 07 01:37:00 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-84181c41-dfba-4004-af49-438ab6881d47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764626219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3764626219 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all.3776878653 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 390481237 ps |
| CPU time | 15.04 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:37:26 PM PST 24 |
| Peak memory | 204152 kb |
| Host | smart-a4fabf71-b79d-4882-866b-1522f815f732 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3776878653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3776878653 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.4230902760 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 823977198 ps |
| CPU time | 83.14 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:38:34 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-bcbf1c97-410c-4c92-a907-24cec559f537 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4230902760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.4230902760 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1144283966 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 74800066 ps |
| CPU time | 17.58 seconds |
| Started | Mar 07 01:37:10 PM PST 24 |
| Finished | Mar 07 01:37:28 PM PST 24 |
| Peak memory | 205116 kb |
| Host | smart-ffa30363-aed6-4e63-8d17-05e076a9b998 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1144283966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand _reset.1144283966 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2235688930 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 696032875 ps |
| CPU time | 111.81 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:39:03 PM PST 24 |
| Peak memory | 208424 kb |
| Host | smart-bc7f938a-e55d-4fdb-a85c-3e6ff8265f0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2235688930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res et_error.2235688930 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.2411327333 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 741755685 ps |
| CPU time | 22.36 seconds |
| Started | Mar 07 01:37:09 PM PST 24 |
| Finished | Mar 07 01:37:32 PM PST 24 |
| Peak memory | 204624 kb |
| Host | smart-3a1a9155-bb4f-4c43-97a3-a24a61357871 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2411327333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2411327333 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2786468221 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1046949851 ps |
| CPU time | 32.08 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:37:43 PM PST 24 |
| Peak memory | 204904 kb |
| Host | smart-3168b90d-098d-46a1-a7c5-ffd9e3e5aca2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2786468221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2786468221 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2282469556 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 25315285799 ps |
| CPU time | 127.75 seconds |
| Started | Mar 07 01:37:09 PM PST 24 |
| Finished | Mar 07 01:39:17 PM PST 24 |
| Peak memory | 205464 kb |
| Host | smart-12740185-6ca1-45b8-9ba7-95da91be6efa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2282469556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo w_rsp.2282469556 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1521115009 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 266488545 ps |
| CPU time | 9.96 seconds |
| Started | Mar 07 01:37:14 PM PST 24 |
| Finished | Mar 07 01:37:24 PM PST 24 |
| Peak memory | 203264 kb |
| Host | smart-f13e59a1-1425-4120-88a8-b4f53c1fc32b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1521115009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1521115009 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_error_random.2931388584 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 1005562520 ps |
| CPU time | 34.52 seconds |
| Started | Mar 07 01:37:08 PM PST 24 |
| Finished | Mar 07 01:37:43 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-c1f03240-69d1-4bca-958b-55bddeadd5f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2931388584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2931388584 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random.2722468063 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 894715366 ps |
| CPU time | 39.75 seconds |
| Started | Mar 07 01:37:09 PM PST 24 |
| Finished | Mar 07 01:37:49 PM PST 24 |
| Peak memory | 204904 kb |
| Host | smart-93dc0c35-619e-45dd-a8db-73016e833c00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2722468063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2722468063 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.3683706029 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 38933528415 ps |
| CPU time | 176.1 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:40:07 PM PST 24 |
| Peak memory | 204604 kb |
| Host | smart-6b43d651-b0c4-4455-a9de-cad7a5dcc80d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683706029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3683706029 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.433763573 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 7430655476 ps |
| CPU time | 61.58 seconds |
| Started | Mar 07 01:37:12 PM PST 24 |
| Finished | Mar 07 01:38:14 PM PST 24 |
| Peak memory | 211376 kb |
| Host | smart-99dc96a5-e7fe-4e43-b877-d0da7d58675e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=433763573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.433763573 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.857660223 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 133848928 ps |
| CPU time | 9.12 seconds |
| Started | Mar 07 01:37:09 PM PST 24 |
| Finished | Mar 07 01:37:18 PM PST 24 |
| Peak memory | 204256 kb |
| Host | smart-75afce0b-a018-479b-9f1d-9eed37006483 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857660223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.857660223 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_same_source.2633739337 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 152282434 ps |
| CPU time | 9.93 seconds |
| Started | Mar 07 01:37:09 PM PST 24 |
| Finished | Mar 07 01:37:19 PM PST 24 |
| Peak memory | 203564 kb |
| Host | smart-14f5c3b8-5bd3-4b8b-8f54-346dd4e76887 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2633739337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2633739337 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke.3275196134 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 26091425 ps |
| CPU time | 2.2 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:37:14 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-da7f03af-1c3f-4dc8-b537-0e9a9ba2e9ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3275196134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3275196134 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.4167481835 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9721002749 ps |
| CPU time | 30.12 seconds |
| Started | Mar 07 01:37:15 PM PST 24 |
| Finished | Mar 07 01:37:45 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-b18c0dbb-e830-4d03-b11e-68fcf2c4993e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167481835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.4167481835 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2402747091 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 9776618380 ps |
| CPU time | 30.05 seconds |
| Started | Mar 07 01:37:07 PM PST 24 |
| Finished | Mar 07 01:37:38 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-3c476368-ddc9-4f4f-917c-fb8e55bc800f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2402747091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2402747091 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3120395281 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 26197016 ps |
| CPU time | 2.49 seconds |
| Started | Mar 07 01:37:14 PM PST 24 |
| Finished | Mar 07 01:37:17 PM PST 24 |
| Peak memory | 203176 kb |
| Host | smart-72a6e152-cfb0-48df-b0c4-51d1ad844191 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120395281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3120395281 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all.2912577474 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2120849484 ps |
| CPU time | 236.87 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:41:08 PM PST 24 |
| Peak memory | 206536 kb |
| Host | smart-7fc394fe-4d91-44d9-9746-ebc6fb42271b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2912577474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2912577474 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.2852145956 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 778061071 ps |
| CPU time | 49.64 seconds |
| Started | Mar 07 01:37:17 PM PST 24 |
| Finished | Mar 07 01:38:07 PM PST 24 |
| Peak memory | 205152 kb |
| Host | smart-699ced50-9a42-4c2d-9dcc-87024689bec2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2852145956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2852145956 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.627850689 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 543508507 ps |
| CPU time | 191.56 seconds |
| Started | Mar 07 01:37:15 PM PST 24 |
| Finished | Mar 07 01:40:27 PM PST 24 |
| Peak memory | 207804 kb |
| Host | smart-7eacefa3-411e-49d8-984a-6239bdf1aa33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=627850689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_ reset.627850689 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3190449174 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 132866771 ps |
| CPU time | 21.24 seconds |
| Started | Mar 07 01:37:09 PM PST 24 |
| Finished | Mar 07 01:37:31 PM PST 24 |
| Peak memory | 204476 kb |
| Host | smart-7c4b2ebc-335a-4776-b2af-17a40634ba65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3190449174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res et_error.3190449174 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3775916188 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 711486830 ps |
| CPU time | 29.19 seconds |
| Started | Mar 07 01:37:09 PM PST 24 |
| Finished | Mar 07 01:37:39 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-b2679818-3542-4cf9-9fd0-44ed1c682a2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3775916188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3775916188 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2478094119 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 134774647 ps |
| CPU time | 9.02 seconds |
| Started | Mar 07 01:37:39 PM PST 24 |
| Finished | Mar 07 01:37:48 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-7418b18e-8b8b-4495-9a2e-49fdadf7e5b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2478094119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2478094119 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2860817382 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 235794112 ps |
| CPU time | 9.93 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:37:50 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-a54b7008-4882-4a71-9900-cca0ab82422d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2860817382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2860817382 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_error_random.184472614 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 241252139 ps |
| CPU time | 8.57 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:37:47 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-fb395f1f-7883-44bb-b7d5-1e4ce5953d65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=184472614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.184472614 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random.2510008568 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 297305679 ps |
| CPU time | 14.55 seconds |
| Started | Mar 07 01:37:43 PM PST 24 |
| Finished | Mar 07 01:37:58 PM PST 24 |
| Peak memory | 204152 kb |
| Host | smart-6f91e01f-eefd-4ede-add1-e98f9e6d6114 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2510008568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2510008568 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.3443716813 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 10283270863 ps |
| CPU time | 29.09 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:38:09 PM PST 24 |
| Peak memory | 203228 kb |
| Host | smart-bac1aba5-92c2-4ded-a7f1-00ab31023770 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443716813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3443716813 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.2384179925 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 35744272914 ps |
| CPU time | 274.14 seconds |
| Started | Mar 07 01:37:48 PM PST 24 |
| Finished | Mar 07 01:42:22 PM PST 24 |
| Peak memory | 204360 kb |
| Host | smart-c60aba3c-66d3-470a-9443-e6f730bd1329 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2384179925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2384179925 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.930302344 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 616634212 ps |
| CPU time | 17.47 seconds |
| Started | Mar 07 01:37:43 PM PST 24 |
| Finished | Mar 07 01:38:01 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-1e4db6e7-77e2-4972-9d91-2c91419086c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930302344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.930302344 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_same_source.935487014 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 78100702 ps |
| CPU time | 5.44 seconds |
| Started | Mar 07 01:37:44 PM PST 24 |
| Finished | Mar 07 01:37:50 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-de6b278a-37e8-4c03-bd78-06385d315ee3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=935487014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.935487014 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke.4144598073 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 73259718 ps |
| CPU time | 2.45 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:37:40 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-1e68b71c-18c1-4f67-901a-3d71f707b50f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4144598073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.4144598073 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.388472933 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 5403736264 ps |
| CPU time | 27.74 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:38:06 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-96cd6d05-ff38-4f6e-b55e-1d0d53afca87 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=388472933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.388472933 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3873329314 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4196282361 ps |
| CPU time | 24.83 seconds |
| Started | Mar 07 01:37:49 PM PST 24 |
| Finished | Mar 07 01:38:14 PM PST 24 |
| Peak memory | 202976 kb |
| Host | smart-77dbf172-43f3-4342-802a-ceccf19bad89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3873329314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3873329314 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3949623959 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 26554142 ps |
| CPU time | 2.13 seconds |
| Started | Mar 07 01:37:41 PM PST 24 |
| Finished | Mar 07 01:37:43 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-cc8e67e5-ff12-4ecd-8c62-2e4cdf414fe3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949623959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3949623959 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all.1179368135 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 11032550562 ps |
| CPU time | 224.03 seconds |
| Started | Mar 07 01:37:49 PM PST 24 |
| Finished | Mar 07 01:41:33 PM PST 24 |
| Peak memory | 206952 kb |
| Host | smart-5daefa8b-49eb-478e-be38-a508458b13ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1179368135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1179368135 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.3307252314 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3287246907 ps |
| CPU time | 66.63 seconds |
| Started | Mar 07 01:37:41 PM PST 24 |
| Finished | Mar 07 01:38:48 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-9a85b5ee-8fd8-489f-a343-960c1c8eac4d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3307252314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3307252314 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.2562748628 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 331330222 ps |
| CPU time | 98.1 seconds |
| Started | Mar 07 01:37:39 PM PST 24 |
| Finished | Mar 07 01:39:17 PM PST 24 |
| Peak memory | 207404 kb |
| Host | smart-2dc550be-1641-4e82-b5ca-a0d6f4d60b57 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2562748628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran d_reset.2562748628 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.207051401 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 281516705 ps |
| CPU time | 69.71 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:38:48 PM PST 24 |
| Peak memory | 211256 kb |
| Host | smart-14f57d67-28d8-4771-a5e6-dc34f3669770 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=207051401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_res et_error.207051401 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.966583528 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 72710781 ps |
| CPU time | 2.21 seconds |
| Started | Mar 07 01:37:43 PM PST 24 |
| Finished | Mar 07 01:37:46 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-8d4fe4c4-03ed-4313-a82b-9d3db3718599 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=966583528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.966583528 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.3685774417 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 284553844 ps |
| CPU time | 25.57 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:38:03 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-01ec0906-f3b3-40d7-83eb-17035b720ada |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3685774417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3685774417 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.3225573381 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 72206935784 ps |
| CPU time | 442.38 seconds |
| Started | Mar 07 01:37:44 PM PST 24 |
| Finished | Mar 07 01:45:07 PM PST 24 |
| Peak memory | 211444 kb |
| Host | smart-0ef2fccb-1976-490b-8be7-22c1668daf69 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3225573381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl ow_rsp.3225573381 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.1242425675 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 703065926 ps |
| CPU time | 13.01 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:37:51 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-da9ed6a4-fddc-4eb0-8627-f91c231aa6b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1242425675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.1242425675 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_error_random.1809539737 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 109642743 ps |
| CPU time | 10.13 seconds |
| Started | Mar 07 01:37:44 PM PST 24 |
| Finished | Mar 07 01:37:55 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-6f680f18-0af4-4248-86d2-6453b23335a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1809539737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1809539737 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random.37898900 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3071384795 ps |
| CPU time | 42.48 seconds |
| Started | Mar 07 01:37:39 PM PST 24 |
| Finished | Mar 07 01:38:21 PM PST 24 |
| Peak memory | 211352 kb |
| Host | smart-49aa49b3-be4e-47d0-af8a-3b96a1c68d53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=37898900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.37898900 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.3321377390 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 21796614592 ps |
| CPU time | 130.68 seconds |
| Started | Mar 07 01:37:49 PM PST 24 |
| Finished | Mar 07 01:40:00 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-9dd6e39d-22e9-4c8a-9d5f-a9c6660154a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321377390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3321377390 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1373482376 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 13357303382 ps |
| CPU time | 90.79 seconds |
| Started | Mar 07 01:37:41 PM PST 24 |
| Finished | Mar 07 01:39:12 PM PST 24 |
| Peak memory | 204648 kb |
| Host | smart-c3731298-5352-4b9e-822a-5f3a6701bbd6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1373482376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1373482376 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.935504195 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 140961664 ps |
| CPU time | 18.69 seconds |
| Started | Mar 07 01:37:39 PM PST 24 |
| Finished | Mar 07 01:37:57 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-fc3cebc3-22c9-4600-9359-0c3710e5009c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935504195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.935504195 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_same_source.3384717174 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1304499370 ps |
| CPU time | 31.82 seconds |
| Started | Mar 07 01:37:39 PM PST 24 |
| Finished | Mar 07 01:38:11 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-33c85d90-5353-4c89-b197-5fe4e1d327b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3384717174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3384717174 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke.4131212014 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 237091948 ps |
| CPU time | 3.46 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:37:43 PM PST 24 |
| Peak memory | 203164 kb |
| Host | smart-e1ac453d-b228-459d-b030-31b69765c0bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4131212014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.4131212014 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2425240974 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 21788573229 ps |
| CPU time | 36.77 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:38:17 PM PST 24 |
| Peak memory | 203276 kb |
| Host | smart-bee6bd56-e214-467c-af5a-ff57a2eaedc2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425240974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2425240974 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.956041324 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 10158628679 ps |
| CPU time | 30.33 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:38:11 PM PST 24 |
| Peak memory | 203176 kb |
| Host | smart-185cf547-11c7-473d-b151-be7981bf9c24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=956041324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.956041324 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.3314873762 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 29493429 ps |
| CPU time | 2 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:37:40 PM PST 24 |
| Peak memory | 203016 kb |
| Host | smart-a5fe2459-ff43-4558-a4b6-a205dec375a3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314873762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.3314873762 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all.737422732 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3635200246 ps |
| CPU time | 69.48 seconds |
| Started | Mar 07 01:37:43 PM PST 24 |
| Finished | Mar 07 01:38:53 PM PST 24 |
| Peak memory | 205320 kb |
| Host | smart-f2b4379e-8cff-4d52-ba8b-d84ed7e31eb4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=737422732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.737422732 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1059771109 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 458760356 ps |
| CPU time | 33.73 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:38:14 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-abe8c2eb-60df-4a8d-bb05-0c8d2627e4e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1059771109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1059771109 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3718910766 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 90876649 ps |
| CPU time | 43.78 seconds |
| Started | Mar 07 01:37:39 PM PST 24 |
| Finished | Mar 07 01:38:23 PM PST 24 |
| Peak memory | 206104 kb |
| Host | smart-01efec2f-2192-4f85-8696-6fef82d174b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3718910766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran d_reset.3718910766 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.1108786961 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 687851960 ps |
| CPU time | 179.67 seconds |
| Started | Mar 07 01:37:44 PM PST 24 |
| Finished | Mar 07 01:40:44 PM PST 24 |
| Peak memory | 211216 kb |
| Host | smart-f250a19b-4310-4e32-84a9-9ac6ae6a6065 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1108786961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_re set_error.1108786961 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.2192437827 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 136472595 ps |
| CPU time | 13.12 seconds |
| Started | Mar 07 01:37:44 PM PST 24 |
| Finished | Mar 07 01:37:57 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-c3cfdbf3-6b36-4092-9be5-abba2ddc39f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2192437827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2192437827 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.772614256 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 416142643 ps |
| CPU time | 19.56 seconds |
| Started | Mar 07 01:37:44 PM PST 24 |
| Finished | Mar 07 01:38:03 PM PST 24 |
| Peak memory | 204228 kb |
| Host | smart-595dcc96-659c-47e4-ae40-b00b8d75c86c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=772614256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.772614256 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1064738719 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 96274790824 ps |
| CPU time | 414.6 seconds |
| Started | Mar 07 01:37:42 PM PST 24 |
| Finished | Mar 07 01:44:39 PM PST 24 |
| Peak memory | 205468 kb |
| Host | smart-842d05d0-2e09-4345-9157-b59d7fb5daf0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1064738719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl ow_rsp.1064738719 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.16352142 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 686484660 ps |
| CPU time | 21.76 seconds |
| Started | Mar 07 01:37:41 PM PST 24 |
| Finished | Mar 07 01:38:03 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-47021c72-64d6-41ff-a0a5-22dbfe457d1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=16352142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.16352142 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_error_random.1555132505 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 24988085 ps |
| CPU time | 3.15 seconds |
| Started | Mar 07 01:37:44 PM PST 24 |
| Finished | Mar 07 01:37:47 PM PST 24 |
| Peak memory | 203236 kb |
| Host | smart-94335e4e-fe5b-4058-87fd-67afbfb8e0a2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1555132505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1555132505 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.1994364817 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 44358456612 ps |
| CPU time | 206.09 seconds |
| Started | Mar 07 01:37:47 PM PST 24 |
| Finished | Mar 07 01:41:13 PM PST 24 |
| Peak memory | 204440 kb |
| Host | smart-48326576-49da-40ab-bd77-58a53f585955 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994364817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1994364817 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.651055977 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 21152178243 ps |
| CPU time | 127.94 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:39:48 PM PST 24 |
| Peak memory | 211460 kb |
| Host | smart-ab7b2b48-a1fd-45b4-8a11-6a01f4aee669 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=651055977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.651055977 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.4270534212 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 107910879 ps |
| CPU time | 10.55 seconds |
| Started | Mar 07 01:37:44 PM PST 24 |
| Finished | Mar 07 01:37:55 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-afabcc75-d73d-456c-8c71-23d1fb5da753 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270534212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.4270534212 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_same_source.4213890728 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 65530947 ps |
| CPU time | 4.44 seconds |
| Started | Mar 07 01:37:41 PM PST 24 |
| Finished | Mar 07 01:37:46 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-fad9f0ef-9ecf-4c4d-9dba-489d8b9739fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4213890728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.4213890728 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke.2616402946 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 27151865 ps |
| CPU time | 2.17 seconds |
| Started | Mar 07 01:37:48 PM PST 24 |
| Finished | Mar 07 01:37:51 PM PST 24 |
| Peak memory | 202932 kb |
| Host | smart-5226b423-807e-4f58-a83f-225a0c60a568 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2616402946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2616402946 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.72080556 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 6472697233 ps |
| CPU time | 28.12 seconds |
| Started | Mar 07 01:37:37 PM PST 24 |
| Finished | Mar 07 01:38:05 PM PST 24 |
| Peak memory | 203200 kb |
| Host | smart-a3d42119-81bc-4579-a14d-6a169d28f912 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=72080556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.72080556 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1011730375 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 6195418906 ps |
| CPU time | 37.4 seconds |
| Started | Mar 07 01:37:41 PM PST 24 |
| Finished | Mar 07 01:38:19 PM PST 24 |
| Peak memory | 203196 kb |
| Host | smart-fdbc8ae9-1199-43c8-8b49-213528ebedb0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1011730375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1011730375 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.775253660 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 38941967 ps |
| CPU time | 2.43 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:37:44 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-b59a7e8b-cc04-4219-a865-85be2c5872b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775253660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.775253660 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all.2342166283 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 6546277 ps |
| CPU time | 0.81 seconds |
| Started | Mar 07 01:37:49 PM PST 24 |
| Finished | Mar 07 01:37:50 PM PST 24 |
| Peak memory | 194900 kb |
| Host | smart-e9a52495-e295-49e9-952d-2a25a3368c50 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2342166283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2342166283 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1769979137 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 4501690336 ps |
| CPU time | 91.73 seconds |
| Started | Mar 07 01:37:50 PM PST 24 |
| Finished | Mar 07 01:39:22 PM PST 24 |
| Peak memory | 204556 kb |
| Host | smart-aca12011-e720-4526-87a3-a8b1c312e6e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1769979137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1769979137 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1895800410 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3832738257 ps |
| CPU time | 315.76 seconds |
| Started | Mar 07 01:37:53 PM PST 24 |
| Finished | Mar 07 01:43:09 PM PST 24 |
| Peak memory | 219552 kb |
| Host | smart-801fc0c1-ab06-43b2-ac34-c0e5b6aab355 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1895800410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re set_error.1895800410 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.3956906333 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 362966385 ps |
| CPU time | 14.67 seconds |
| Started | Mar 07 01:37:45 PM PST 24 |
| Finished | Mar 07 01:38:00 PM PST 24 |
| Peak memory | 204524 kb |
| Host | smart-f738127c-33f3-4269-b2ff-163cdbac7540 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3956906333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3956906333 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.512098529 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2132168122 ps |
| CPU time | 63.6 seconds |
| Started | Mar 07 01:37:49 PM PST 24 |
| Finished | Mar 07 01:38:53 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-f6958d53-2de6-400f-afa9-047e4cb8e08a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=512098529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.512098529 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2643237901 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 82080074121 ps |
| CPU time | 510.39 seconds |
| Started | Mar 07 01:37:48 PM PST 24 |
| Finished | Mar 07 01:46:18 PM PST 24 |
| Peak memory | 206640 kb |
| Host | smart-0912f3f1-9499-4ec8-b587-1da58be471f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2643237901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_sl ow_rsp.2643237901 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.1532119110 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 191088123 ps |
| CPU time | 10.45 seconds |
| Started | Mar 07 01:37:53 PM PST 24 |
| Finished | Mar 07 01:38:04 PM PST 24 |
| Peak memory | 203612 kb |
| Host | smart-1482d68d-f053-4303-afe4-30c2c08498e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1532119110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.1532119110 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_error_random.3446171919 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 357691559 ps |
| CPU time | 23.06 seconds |
| Started | Mar 07 01:37:50 PM PST 24 |
| Finished | Mar 07 01:38:13 PM PST 24 |
| Peak memory | 203232 kb |
| Host | smart-d7c958a7-2266-4373-ba31-83654a887711 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3446171919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3446171919 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random.4089044883 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 18524190 ps |
| CPU time | 2.18 seconds |
| Started | Mar 07 01:37:47 PM PST 24 |
| Finished | Mar 07 01:37:49 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-d7793de9-534e-40c1-8272-7e1ae7e31ce4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4089044883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.4089044883 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.1260885509 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 36388118839 ps |
| CPU time | 214.84 seconds |
| Started | Mar 07 01:37:47 PM PST 24 |
| Finished | Mar 07 01:41:22 PM PST 24 |
| Peak memory | 204680 kb |
| Host | smart-5dc9f0dd-6349-4b7f-8751-9a41fef8c152 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260885509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1260885509 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3826810418 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 38509015150 ps |
| CPU time | 173.62 seconds |
| Started | Mar 07 01:37:48 PM PST 24 |
| Finished | Mar 07 01:40:42 PM PST 24 |
| Peak memory | 205276 kb |
| Host | smart-b0da81cf-9089-482a-bda0-ccae770e6aa4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3826810418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3826810418 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.3767540582 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 788312707 ps |
| CPU time | 28.94 seconds |
| Started | Mar 07 01:37:51 PM PST 24 |
| Finished | Mar 07 01:38:20 PM PST 24 |
| Peak memory | 204904 kb |
| Host | smart-b22f1c4f-f8d7-4aff-b4b9-7b099d1d6328 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767540582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3767540582 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_same_source.3154730033 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 309054994 ps |
| CPU time | 14 seconds |
| Started | Mar 07 01:37:56 PM PST 24 |
| Finished | Mar 07 01:38:10 PM PST 24 |
| Peak memory | 203192 kb |
| Host | smart-698b3695-4c57-4d64-85e9-c45a572fac12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3154730033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3154730033 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke.2642810204 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 537154231 ps |
| CPU time | 3.69 seconds |
| Started | Mar 07 01:37:49 PM PST 24 |
| Finished | Mar 07 01:37:53 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-c0ca297f-d3c7-4ff0-a636-1843dcc611fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2642810204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2642810204 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2144898362 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 14041166619 ps |
| CPU time | 34.1 seconds |
| Started | Mar 07 01:37:53 PM PST 24 |
| Finished | Mar 07 01:38:27 PM PST 24 |
| Peak memory | 203196 kb |
| Host | smart-403491a0-cb31-4bdb-8755-fd753cefadc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144898362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2144898362 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2944968234 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 6166407498 ps |
| CPU time | 25.45 seconds |
| Started | Mar 07 01:37:49 PM PST 24 |
| Finished | Mar 07 01:38:15 PM PST 24 |
| Peak memory | 203200 kb |
| Host | smart-c2d31fed-f0ce-4f06-8ea9-7d6d6dd038b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2944968234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2944968234 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.2893395540 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29509708 ps |
| CPU time | 2.19 seconds |
| Started | Mar 07 01:37:49 PM PST 24 |
| Finished | Mar 07 01:37:52 PM PST 24 |
| Peak memory | 203104 kb |
| Host | smart-3c9ffcae-2cc5-4fcb-a453-8c9870da6ea0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893395540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2893395540 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all.2535964199 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 6625105274 ps |
| CPU time | 219.59 seconds |
| Started | Mar 07 01:37:52 PM PST 24 |
| Finished | Mar 07 01:41:31 PM PST 24 |
| Peak memory | 206960 kb |
| Host | smart-699a0888-fe46-4c78-adfa-18c54e87b546 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2535964199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2535964199 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2219341261 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1057123541 ps |
| CPU time | 127.1 seconds |
| Started | Mar 07 01:37:54 PM PST 24 |
| Finished | Mar 07 01:40:01 PM PST 24 |
| Peak memory | 208836 kb |
| Host | smart-2d1a1fda-9904-4768-a1f1-a5a36f9ec139 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2219341261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2219341261 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.740178677 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3387989267 ps |
| CPU time | 187.44 seconds |
| Started | Mar 07 01:37:51 PM PST 24 |
| Finished | Mar 07 01:40:58 PM PST 24 |
| Peak memory | 209108 kb |
| Host | smart-0efb1a68-0f4c-4b1d-be0e-17641bf44e81 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=740178677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand _reset.740178677 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.1677309709 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 193029250 ps |
| CPU time | 83.12 seconds |
| Started | Mar 07 01:37:50 PM PST 24 |
| Finished | Mar 07 01:39:14 PM PST 24 |
| Peak memory | 207992 kb |
| Host | smart-76cf4c7d-2dc2-4840-8640-077936b31b4b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1677309709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re set_error.1677309709 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.2313853988 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 780478931 ps |
| CPU time | 18.9 seconds |
| Started | Mar 07 01:37:49 PM PST 24 |
| Finished | Mar 07 01:38:08 PM PST 24 |
| Peak memory | 204384 kb |
| Host | smart-384ea3af-0c48-442d-8a82-3701cc4385cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2313853988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2313853988 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.29706061 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 981627123 ps |
| CPU time | 40.15 seconds |
| Started | Mar 07 01:37:51 PM PST 24 |
| Finished | Mar 07 01:38:32 PM PST 24 |
| Peak memory | 205084 kb |
| Host | smart-ce1358c8-7055-4449-8b20-c931a5821c54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=29706061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.29706061 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3082105601 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 213341707179 ps |
| CPU time | 683.19 seconds |
| Started | Mar 07 01:37:50 PM PST 24 |
| Finished | Mar 07 01:49:14 PM PST 24 |
| Peak memory | 205680 kb |
| Host | smart-5d720d90-13fb-4936-8adc-342fe1920f6e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3082105601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl ow_rsp.3082105601 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.1215304963 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1076487395 ps |
| CPU time | 23.48 seconds |
| Started | Mar 07 01:37:48 PM PST 24 |
| Finished | Mar 07 01:38:12 PM PST 24 |
| Peak memory | 203328 kb |
| Host | smart-db5eccfa-a985-4c56-8a2c-758628d0c9a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1215304963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1215304963 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_error_random.1762286359 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 37317590 ps |
| CPU time | 4.1 seconds |
| Started | Mar 07 01:37:51 PM PST 24 |
| Finished | Mar 07 01:37:56 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-95a5c724-a4d3-408a-bba5-43b6c85f5f66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1762286359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1762286359 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random.359317022 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 292869786 ps |
| CPU time | 26.02 seconds |
| Started | Mar 07 01:37:54 PM PST 24 |
| Finished | Mar 07 01:38:21 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-5dbbfb58-5da5-478e-b68c-c970f9174ef9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=359317022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.359317022 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.962047256 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 19317553666 ps |
| CPU time | 103.08 seconds |
| Started | Mar 07 01:37:49 PM PST 24 |
| Finished | Mar 07 01:39:32 PM PST 24 |
| Peak memory | 204728 kb |
| Host | smart-fbd20d50-7a5f-4deb-a557-0305a1293373 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=962047256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.962047256 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.463404034 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 16973757646 ps |
| CPU time | 102.51 seconds |
| Started | Mar 07 01:37:53 PM PST 24 |
| Finished | Mar 07 01:39:36 PM PST 24 |
| Peak memory | 204692 kb |
| Host | smart-12185258-7fe7-45bd-b43c-43d207b360fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=463404034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.463404034 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.1833972070 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 175423411 ps |
| CPU time | 26.83 seconds |
| Started | Mar 07 01:37:54 PM PST 24 |
| Finished | Mar 07 01:38:21 PM PST 24 |
| Peak memory | 204308 kb |
| Host | smart-99a1c5b1-97d6-47e6-ba9c-e7a1e8051119 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833972070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.1833972070 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_same_source.1958387459 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 676651876 ps |
| CPU time | 17.75 seconds |
| Started | Mar 07 01:37:47 PM PST 24 |
| Finished | Mar 07 01:38:05 PM PST 24 |
| Peak memory | 203600 kb |
| Host | smart-661f3359-6c6b-464d-9e45-10c7874e50e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1958387459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1958387459 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke.3345248416 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 322481069 ps |
| CPU time | 3.98 seconds |
| Started | Mar 07 01:37:50 PM PST 24 |
| Finished | Mar 07 01:37:54 PM PST 24 |
| Peak memory | 203036 kb |
| Host | smart-c12627ba-7b44-499e-a1fd-61a9d96a5d3b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3345248416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3345248416 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3204839889 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 11481220186 ps |
| CPU time | 30.69 seconds |
| Started | Mar 07 01:37:50 PM PST 24 |
| Finished | Mar 07 01:38:21 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-322c4e23-a465-402e-a62e-25a218defe21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204839889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3204839889 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.674021416 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 6085798774 ps |
| CPU time | 24.97 seconds |
| Started | Mar 07 01:37:52 PM PST 24 |
| Finished | Mar 07 01:38:17 PM PST 24 |
| Peak memory | 203224 kb |
| Host | smart-c5a2f7ae-d22a-4a84-a545-e5378637e524 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=674021416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.674021416 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.4225384723 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 89261942 ps |
| CPU time | 2.81 seconds |
| Started | Mar 07 01:37:54 PM PST 24 |
| Finished | Mar 07 01:37:56 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-0bd4ff44-3167-4eb8-bc28-9b03e63c2c82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225384723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.4225384723 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all.3167824328 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3676776488 ps |
| CPU time | 129.41 seconds |
| Started | Mar 07 01:37:54 PM PST 24 |
| Finished | Mar 07 01:40:03 PM PST 24 |
| Peak memory | 211448 kb |
| Host | smart-2d3f93da-05ec-49ce-81ea-41688c67da8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3167824328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3167824328 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1895346490 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 698130096 ps |
| CPU time | 39.28 seconds |
| Started | Mar 07 01:37:50 PM PST 24 |
| Finished | Mar 07 01:38:30 PM PST 24 |
| Peak memory | 205216 kb |
| Host | smart-441da3a9-dc64-4386-a395-8666aa138336 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1895346490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1895346490 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.4232054405 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2954534636 ps |
| CPU time | 358.01 seconds |
| Started | Mar 07 01:37:56 PM PST 24 |
| Finished | Mar 07 01:43:55 PM PST 24 |
| Peak memory | 210792 kb |
| Host | smart-c9cfbdf4-fcb2-41a3-8617-78651dd4b990 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4232054405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran d_reset.4232054405 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3043983377 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2422710206 ps |
| CPU time | 330.04 seconds |
| Started | Mar 07 01:37:54 PM PST 24 |
| Finished | Mar 07 01:43:24 PM PST 24 |
| Peak memory | 223252 kb |
| Host | smart-b30feadd-cab4-424e-b345-deb696577dc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3043983377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re set_error.3043983377 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.3800603656 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2450505989 ps |
| CPU time | 30.25 seconds |
| Started | Mar 07 01:37:55 PM PST 24 |
| Finished | Mar 07 01:38:25 PM PST 24 |
| Peak memory | 204612 kb |
| Host | smart-7ae52962-d977-499e-ac92-c5391d7a98dc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3800603656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3800603656 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3821399031 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2715981051 ps |
| CPU time | 39.78 seconds |
| Started | Mar 07 01:37:58 PM PST 24 |
| Finished | Mar 07 01:38:38 PM PST 24 |
| Peak memory | 211420 kb |
| Host | smart-38128488-6191-45f1-8b69-896d1b3faa6b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3821399031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3821399031 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1604696159 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 12170760012 ps |
| CPU time | 98.52 seconds |
| Started | Mar 07 01:37:59 PM PST 24 |
| Finished | Mar 07 01:39:38 PM PST 24 |
| Peak memory | 211376 kb |
| Host | smart-a50763d4-8a4a-4f96-ad87-4d6b12553623 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1604696159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl ow_rsp.1604696159 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1990953052 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 449180026 ps |
| CPU time | 19.29 seconds |
| Started | Mar 07 01:37:59 PM PST 24 |
| Finished | Mar 07 01:38:19 PM PST 24 |
| Peak memory | 203096 kb |
| Host | smart-3c911a78-a6e0-4d8f-bc7f-0ffc7e4613c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1990953052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1990953052 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_error_random.3320533229 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 176065048 ps |
| CPU time | 22.38 seconds |
| Started | Mar 07 01:38:00 PM PST 24 |
| Finished | Mar 07 01:38:22 PM PST 24 |
| Peak memory | 203096 kb |
| Host | smart-9436e643-9b8b-4a40-91ae-67a37028b807 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3320533229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3320533229 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random.3316642606 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 421652387 ps |
| CPU time | 23.97 seconds |
| Started | Mar 07 01:37:56 PM PST 24 |
| Finished | Mar 07 01:38:21 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-e57e28d7-084f-4a2a-a735-926129eb8405 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3316642606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3316642606 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.1741114324 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 41591847912 ps |
| CPU time | 186.89 seconds |
| Started | Mar 07 01:38:00 PM PST 24 |
| Finished | Mar 07 01:41:07 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-e639fb73-c351-40f1-86c7-79ecae30b696 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741114324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1741114324 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.922913170 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 8217599251 ps |
| CPU time | 73.7 seconds |
| Started | Mar 07 01:37:59 PM PST 24 |
| Finished | Mar 07 01:39:13 PM PST 24 |
| Peak memory | 204492 kb |
| Host | smart-176555e5-5dad-4e41-b366-652a0206f254 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=922913170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.922913170 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.2967073767 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 148638099 ps |
| CPU time | 21.5 seconds |
| Started | Mar 07 01:38:00 PM PST 24 |
| Finished | Mar 07 01:38:22 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-7c94eeae-57f7-45b5-9822-bffba292416a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967073767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2967073767 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_same_source.1537327552 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1025910271 ps |
| CPU time | 14.84 seconds |
| Started | Mar 07 01:37:59 PM PST 24 |
| Finished | Mar 07 01:38:14 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-f9a85779-191e-4d1b-b07e-06af857878fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1537327552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1537327552 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke.5000577 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 267320396 ps |
| CPU time | 3.52 seconds |
| Started | Mar 07 01:37:56 PM PST 24 |
| Finished | Mar 07 01:38:00 PM PST 24 |
| Peak memory | 203180 kb |
| Host | smart-ac840564-1eda-4cbe-a198-d0669795043f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=5000577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.5000577 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2766266243 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 6715733070 ps |
| CPU time | 40.7 seconds |
| Started | Mar 07 01:37:57 PM PST 24 |
| Finished | Mar 07 01:38:38 PM PST 24 |
| Peak memory | 203252 kb |
| Host | smart-ce0b250c-39e5-4ed4-ad14-d3c4c30981c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766266243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2766266243 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2877300596 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 3788445125 ps |
| CPU time | 18.68 seconds |
| Started | Mar 07 01:37:52 PM PST 24 |
| Finished | Mar 07 01:38:11 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-ac4c77c7-d1a0-4224-bfde-0d06627ef0b9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2877300596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2877300596 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1791808372 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 46777330 ps |
| CPU time | 2.46 seconds |
| Started | Mar 07 01:37:51 PM PST 24 |
| Finished | Mar 07 01:37:54 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-2ed50094-890f-4070-ae6a-7efb0fb2e96f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791808372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1791808372 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all.4205577622 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 140561654 ps |
| CPU time | 20.5 seconds |
| Started | Mar 07 01:37:58 PM PST 24 |
| Finished | Mar 07 01:38:19 PM PST 24 |
| Peak memory | 205420 kb |
| Host | smart-bfa34e17-5a29-4fea-a3b1-2f960d40859e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4205577622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.4205577622 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1775506987 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2868868727 ps |
| CPU time | 96.72 seconds |
| Started | Mar 07 01:38:00 PM PST 24 |
| Finished | Mar 07 01:39:37 PM PST 24 |
| Peak memory | 204332 kb |
| Host | smart-49ff145c-ed9d-49cb-aca6-dd398720e32e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1775506987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1775506987 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.4284583156 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 23737592 ps |
| CPU time | 16.01 seconds |
| Started | Mar 07 01:38:00 PM PST 24 |
| Finished | Mar 07 01:38:16 PM PST 24 |
| Peak memory | 204948 kb |
| Host | smart-f32d8737-8568-46c4-b1f9-dd20de2cb453 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4284583156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re set_error.4284583156 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.2946518638 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 291866803 ps |
| CPU time | 14.93 seconds |
| Started | Mar 07 01:37:57 PM PST 24 |
| Finished | Mar 07 01:38:12 PM PST 24 |
| Peak memory | 204600 kb |
| Host | smart-57e100fc-bbd0-4c16-bc29-0a906271baa1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2946518638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2946518638 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.2086937213 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4122997150 ps |
| CPU time | 50.78 seconds |
| Started | Mar 07 01:38:07 PM PST 24 |
| Finished | Mar 07 01:38:58 PM PST 24 |
| Peak memory | 203848 kb |
| Host | smart-c193aafe-157f-4652-b970-67cc81d39cbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2086937213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2086937213 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2056344906 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 133760934321 ps |
| CPU time | 551.36 seconds |
| Started | Mar 07 01:37:59 PM PST 24 |
| Finished | Mar 07 01:47:11 PM PST 24 |
| Peak memory | 211396 kb |
| Host | smart-9e24fcc6-0fdf-4a58-b65f-e788fcb4f150 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2056344906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_sl ow_rsp.2056344906 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3425594965 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2090916201 ps |
| CPU time | 25.95 seconds |
| Started | Mar 07 01:38:07 PM PST 24 |
| Finished | Mar 07 01:38:34 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-ee7dcce7-bb95-4e65-ae1b-0543c585a2d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3425594965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3425594965 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_error_random.1956550091 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 2965927870 ps |
| CPU time | 31.1 seconds |
| Started | Mar 07 01:38:02 PM PST 24 |
| Finished | Mar 07 01:38:33 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-9a58dc84-3bc6-4694-9320-5b7832590cd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1956550091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1956550091 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random.4275253614 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 394736926 ps |
| CPU time | 12.72 seconds |
| Started | Mar 07 01:38:04 PM PST 24 |
| Finished | Mar 07 01:38:17 PM PST 24 |
| Peak memory | 204192 kb |
| Host | smart-a2f3fa27-0a23-4d06-a070-6e9c5d097eea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4275253614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.4275253614 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3333668418 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 13825197055 ps |
| CPU time | 63.5 seconds |
| Started | Mar 07 01:37:59 PM PST 24 |
| Finished | Mar 07 01:39:03 PM PST 24 |
| Peak memory | 204560 kb |
| Host | smart-9bdd6593-c725-4177-9df7-7a795ca25215 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333668418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3333668418 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3060199302 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 54185359275 ps |
| CPU time | 268.94 seconds |
| Started | Mar 07 01:38:00 PM PST 24 |
| Finished | Mar 07 01:42:29 PM PST 24 |
| Peak memory | 204768 kb |
| Host | smart-a00aab58-b341-4c63-8bb7-53832cd6eced |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3060199302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3060199302 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3640325355 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 311712159 ps |
| CPU time | 25.04 seconds |
| Started | Mar 07 01:38:04 PM PST 24 |
| Finished | Mar 07 01:38:30 PM PST 24 |
| Peak memory | 204240 kb |
| Host | smart-c4e9a9e1-147c-4aac-af81-63a85cb396b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640325355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3640325355 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_same_source.2990415635 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3144153128 ps |
| CPU time | 13.46 seconds |
| Started | Mar 07 01:38:01 PM PST 24 |
| Finished | Mar 07 01:38:15 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-5f3f6387-aa02-455d-9977-c9ed2a8a9a78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2990415635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2990415635 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke.3855902095 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 53680072 ps |
| CPU time | 2.41 seconds |
| Started | Mar 07 01:38:00 PM PST 24 |
| Finished | Mar 07 01:38:02 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-55a13f7f-9799-41be-82b8-96932b537202 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3855902095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3855902095 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3302066708 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 6964913599 ps |
| CPU time | 38.1 seconds |
| Started | Mar 07 01:38:03 PM PST 24 |
| Finished | Mar 07 01:38:43 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-f222b8c0-2e55-437f-9e9c-66ad33263451 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302066708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3302066708 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1876428526 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3561364215 ps |
| CPU time | 26.91 seconds |
| Started | Mar 07 01:38:01 PM PST 24 |
| Finished | Mar 07 01:38:29 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-15aeadbb-5860-4a9d-a241-cb8ffc4d4af6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1876428526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1876428526 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.75730991 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 44390940 ps |
| CPU time | 2.47 seconds |
| Started | Mar 07 01:37:59 PM PST 24 |
| Finished | Mar 07 01:38:02 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-f0c299eb-3b1b-4d71-a5e9-4b7851fb7619 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75730991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.75730991 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all.4123463360 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3658451425 ps |
| CPU time | 70.1 seconds |
| Started | Mar 07 01:38:01 PM PST 24 |
| Finished | Mar 07 01:39:11 PM PST 24 |
| Peak memory | 205708 kb |
| Host | smart-94ddee07-f9a1-4609-814f-8ae9ebc2d035 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4123463360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.4123463360 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1725950778 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3587894102 ps |
| CPU time | 68 seconds |
| Started | Mar 07 01:38:01 PM PST 24 |
| Finished | Mar 07 01:39:10 PM PST 24 |
| Peak memory | 204988 kb |
| Host | smart-24bc2067-92b9-406f-8b37-572de6bc518e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1725950778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1725950778 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.505356491 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2388582367 ps |
| CPU time | 311.07 seconds |
| Started | Mar 07 01:37:59 PM PST 24 |
| Finished | Mar 07 01:43:10 PM PST 24 |
| Peak memory | 208788 kb |
| Host | smart-2caff160-f94a-4b85-a533-9146d122bad6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=505356491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand _reset.505356491 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.3683125508 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1444047415 ps |
| CPU time | 247.06 seconds |
| Started | Mar 07 01:38:02 PM PST 24 |
| Finished | Mar 07 01:42:09 PM PST 24 |
| Peak memory | 219424 kb |
| Host | smart-f58b9748-df72-4a25-9ca3-a3c870c71755 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3683125508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_re set_error.3683125508 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.2730236616 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 44978881 ps |
| CPU time | 6.55 seconds |
| Started | Mar 07 01:38:07 PM PST 24 |
| Finished | Mar 07 01:38:14 PM PST 24 |
| Peak memory | 211236 kb |
| Host | smart-7a2d7ef8-4738-4bb1-9f22-572db4ebfd00 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2730236616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2730236616 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2680847105 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 279430021 ps |
| CPU time | 48.72 seconds |
| Started | Mar 07 01:38:00 PM PST 24 |
| Finished | Mar 07 01:38:50 PM PST 24 |
| Peak memory | 204900 kb |
| Host | smart-33133ed2-3686-41aa-bf20-836e2c111a6f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2680847105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2680847105 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.2469362289 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 68764820514 ps |
| CPU time | 626.55 seconds |
| Started | Mar 07 01:38:04 PM PST 24 |
| Finished | Mar 07 01:48:31 PM PST 24 |
| Peak memory | 205504 kb |
| Host | smart-94380103-955f-4938-8f93-230c6a8cfe0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2469362289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl ow_rsp.2469362289 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3309436839 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 213013280 ps |
| CPU time | 6.72 seconds |
| Started | Mar 07 01:38:03 PM PST 24 |
| Finished | Mar 07 01:38:11 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-4a4e0cb3-9a8d-4012-9d15-49026fa0c18a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3309436839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3309436839 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_error_random.3277838878 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2082636077 ps |
| CPU time | 32.65 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:38:42 PM PST 24 |
| Peak memory | 203160 kb |
| Host | smart-c6df8e7c-f832-4382-83a4-d421e10d4ddb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3277838878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3277838878 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random.2008712007 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 612585479 ps |
| CPU time | 25.72 seconds |
| Started | Mar 07 01:38:03 PM PST 24 |
| Finished | Mar 07 01:38:30 PM PST 24 |
| Peak memory | 204360 kb |
| Host | smart-db11c3e5-6a2d-4df8-af92-9f1a7809f72f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2008712007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2008712007 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.3238198614 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 48867447453 ps |
| CPU time | 288.33 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:42:58 PM PST 24 |
| Peak memory | 211408 kb |
| Host | smart-33a3d29e-3777-4621-b25d-014128946d0b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238198614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3238198614 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2396055498 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 32569237747 ps |
| CPU time | 224.86 seconds |
| Started | Mar 07 01:38:01 PM PST 24 |
| Finished | Mar 07 01:41:47 PM PST 24 |
| Peak memory | 204908 kb |
| Host | smart-c7524c19-31e8-41c5-9e67-ac6f9a21606c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2396055498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2396055498 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.2500700710 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 47436644 ps |
| CPU time | 5.02 seconds |
| Started | Mar 07 01:38:04 PM PST 24 |
| Finished | Mar 07 01:38:09 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-d95a6593-db5b-4ffa-80e9-754a4d6c1b55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500700710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2500700710 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_same_source.1081973921 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 393584164 ps |
| CPU time | 16.1 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:38:25 PM PST 24 |
| Peak memory | 203648 kb |
| Host | smart-939e914b-f6ff-423a-8813-0f6a0ff76585 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1081973921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1081973921 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke.1537332159 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 379894043 ps |
| CPU time | 3.67 seconds |
| Started | Mar 07 01:38:01 PM PST 24 |
| Finished | Mar 07 01:38:06 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-f3e83059-494a-4cb1-adc4-7f0b004e806a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1537332159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1537332159 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.787438964 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 5181309099 ps |
| CPU time | 29.12 seconds |
| Started | Mar 07 01:38:04 PM PST 24 |
| Finished | Mar 07 01:38:34 PM PST 24 |
| Peak memory | 203180 kb |
| Host | smart-c20a4ab3-796d-4dd5-a9e6-4a0737aea885 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=787438964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.787438964 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.562521004 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 5424458893 ps |
| CPU time | 33.3 seconds |
| Started | Mar 07 01:38:01 PM PST 24 |
| Finished | Mar 07 01:38:35 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-e8d5ec8c-c2fa-41a7-a5e6-73b9ff853b44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=562521004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.562521004 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.1737551606 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 44263384 ps |
| CPU time | 2.3 seconds |
| Started | Mar 07 01:38:01 PM PST 24 |
| Finished | Mar 07 01:38:03 PM PST 24 |
| Peak memory | 203220 kb |
| Host | smart-a8653e8b-57dc-4ea0-b8fe-41a984379ff5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737551606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1737551606 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3325116186 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1573366469 ps |
| CPU time | 202.14 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:41:30 PM PST 24 |
| Peak memory | 205684 kb |
| Host | smart-a17478d3-3a7a-4d5d-8e7b-6f41b4efa07a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3325116186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3325116186 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.3689583464 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1224459270 ps |
| CPU time | 25.18 seconds |
| Started | Mar 07 01:38:02 PM PST 24 |
| Finished | Mar 07 01:38:29 PM PST 24 |
| Peak memory | 204268 kb |
| Host | smart-6cbd5f99-1702-4c7f-a36e-db92cf8c06cc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3689583464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3689583464 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.1993465053 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 20027728518 ps |
| CPU time | 398.96 seconds |
| Started | Mar 07 01:38:09 PM PST 24 |
| Finished | Mar 07 01:44:48 PM PST 24 |
| Peak memory | 209984 kb |
| Host | smart-ac1f50be-2714-4b5b-bba5-955151338dfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1993465053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran d_reset.1993465053 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1870811670 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 9955655094 ps |
| CPU time | 242.7 seconds |
| Started | Mar 07 01:38:03 PM PST 24 |
| Finished | Mar 07 01:42:07 PM PST 24 |
| Peak memory | 219428 kb |
| Host | smart-62e69944-8868-4bc0-a11e-73ccced63f47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1870811670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_re set_error.1870811670 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.4194742424 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 407204187 ps |
| CPU time | 10.73 seconds |
| Started | Mar 07 01:38:04 PM PST 24 |
| Finished | Mar 07 01:38:15 PM PST 24 |
| Peak memory | 211256 kb |
| Host | smart-afe5fd33-4652-436b-8367-3b482746a9c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4194742424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.4194742424 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.3113810430 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1398427454 ps |
| CPU time | 22.91 seconds |
| Started | Mar 07 01:38:11 PM PST 24 |
| Finished | Mar 07 01:38:34 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-bc2a23f6-2f60-4fe1-b7c3-73be2aa0b067 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3113810430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3113810430 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.392940021 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 88325972563 ps |
| CPU time | 546.68 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:47:16 PM PST 24 |
| Peak memory | 206844 kb |
| Host | smart-578cce96-9aa1-49cf-ba62-c781083b1561 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=392940021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slo w_rsp.392940021 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.731574489 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 23320917 ps |
| CPU time | 2.6 seconds |
| Started | Mar 07 01:38:07 PM PST 24 |
| Finished | Mar 07 01:38:10 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-cf8411fe-28d5-4a3f-87dc-d50513393107 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=731574489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.731574489 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_error_random.2450992862 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 13183696 ps |
| CPU time | 2.05 seconds |
| Started | Mar 07 01:38:10 PM PST 24 |
| Finished | Mar 07 01:38:12 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-f4f55c3a-16a0-45de-a1fb-5514be978b89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2450992862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2450992862 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random.4036665913 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 439387668 ps |
| CPU time | 11.56 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:38:21 PM PST 24 |
| Peak memory | 204180 kb |
| Host | smart-c9555933-a3fd-480b-8413-bff2ebe147b4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4036665913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.4036665913 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.3970932871 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 95566576605 ps |
| CPU time | 198.6 seconds |
| Started | Mar 07 01:38:07 PM PST 24 |
| Finished | Mar 07 01:41:26 PM PST 24 |
| Peak memory | 204372 kb |
| Host | smart-f01e88c4-2656-498e-8c9e-a1f44a7edeef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970932871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3970932871 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.308429433 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 20956821695 ps |
| CPU time | 157.33 seconds |
| Started | Mar 07 01:38:07 PM PST 24 |
| Finished | Mar 07 01:40:45 PM PST 24 |
| Peak memory | 204580 kb |
| Host | smart-e410c042-320f-4042-aa36-fdec2de0042c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=308429433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.308429433 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.4221537537 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 168967474 ps |
| CPU time | 17.33 seconds |
| Started | Mar 07 01:38:07 PM PST 24 |
| Finished | Mar 07 01:38:26 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-a94028c0-397a-45f3-b46a-6622e49b0fa6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221537537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.4221537537 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_same_source.1081576104 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 253587554 ps |
| CPU time | 19.42 seconds |
| Started | Mar 07 01:38:07 PM PST 24 |
| Finished | Mar 07 01:38:27 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-b83bf759-da62-4eb7-abc5-8983b940a128 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1081576104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1081576104 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke.1871091495 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 144421031 ps |
| CPU time | 3.9 seconds |
| Started | Mar 07 01:38:09 PM PST 24 |
| Finished | Mar 07 01:38:14 PM PST 24 |
| Peak memory | 203164 kb |
| Host | smart-7032859e-246c-43e6-8382-bbf9dd08d337 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1871091495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1871091495 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3248068316 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 5715361915 ps |
| CPU time | 31.86 seconds |
| Started | Mar 07 01:38:06 PM PST 24 |
| Finished | Mar 07 01:38:39 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-eafa2d02-7c66-4efa-8245-46c66350ea74 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248068316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3248068316 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.682426996 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 7104598986 ps |
| CPU time | 34.97 seconds |
| Started | Mar 07 01:38:15 PM PST 24 |
| Finished | Mar 07 01:38:51 PM PST 24 |
| Peak memory | 203256 kb |
| Host | smart-85b08d34-da93-47e7-8105-294d5595f496 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=682426996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.682426996 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.2382958471 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 27657144 ps |
| CPU time | 2.15 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:38:10 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-2aa44f1b-6004-4fe2-9244-93206bcd8415 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382958471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.2382958471 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all.598030134 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 7858010374 ps |
| CPU time | 184.74 seconds |
| Started | Mar 07 01:38:11 PM PST 24 |
| Finished | Mar 07 01:41:16 PM PST 24 |
| Peak memory | 211428 kb |
| Host | smart-a2921994-ac06-4461-bf70-d78a1dc5f95d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=598030134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.598030134 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2103187190 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 5348180274 ps |
| CPU time | 60.5 seconds |
| Started | Mar 07 01:38:09 PM PST 24 |
| Finished | Mar 07 01:39:10 PM PST 24 |
| Peak memory | 204344 kb |
| Host | smart-8f2272fd-63d9-4003-aa0a-fb808b169b55 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2103187190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2103187190 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.192476003 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4639363298 ps |
| CPU time | 380.71 seconds |
| Started | Mar 07 01:38:11 PM PST 24 |
| Finished | Mar 07 01:44:32 PM PST 24 |
| Peak memory | 209372 kb |
| Host | smart-d8623dd3-87ee-4511-8932-4b2199da8dfc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=192476003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand _reset.192476003 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.2936236310 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1246241298 ps |
| CPU time | 74.69 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:39:23 PM PST 24 |
| Peak memory | 208064 kb |
| Host | smart-c3915ac1-e30d-48dc-871c-cdf1752d02e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2936236310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re set_error.2936236310 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.4270135226 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 291672570 ps |
| CPU time | 12.58 seconds |
| Started | Mar 07 01:38:07 PM PST 24 |
| Finished | Mar 07 01:38:20 PM PST 24 |
| Peak memory | 204196 kb |
| Host | smart-c1c94f1a-93cb-45a9-92b6-8bf06402e1eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4270135226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.4270135226 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.2698545491 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 73554028 ps |
| CPU time | 5.83 seconds |
| Started | Mar 07 01:38:15 PM PST 24 |
| Finished | Mar 07 01:38:22 PM PST 24 |
| Peak memory | 204224 kb |
| Host | smart-7a53212b-1d87-4a6b-a577-d5cb3629a044 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2698545491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2698545491 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1018644722 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 127268103676 ps |
| CPU time | 390.73 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:44:40 PM PST 24 |
| Peak memory | 205464 kb |
| Host | smart-e39ec5c4-4aa9-4f67-8d01-99e56a214b97 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1018644722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl ow_rsp.1018644722 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.4096633177 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2138830836 ps |
| CPU time | 15.9 seconds |
| Started | Mar 07 01:38:18 PM PST 24 |
| Finished | Mar 07 01:38:34 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-42a9fd44-62f4-4d37-a828-b8837a530d6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4096633177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.4096633177 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_error_random.4036144993 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1548901956 ps |
| CPU time | 14.79 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:38:35 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-f6499762-369a-468c-ab2d-a5fb959b63e7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4036144993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.4036144993 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random.4186100262 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 236914410 ps |
| CPU time | 8.31 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:38:17 PM PST 24 |
| Peak memory | 211300 kb |
| Host | smart-ba4aebd5-fc46-4a4e-b0c4-98d4ea801236 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4186100262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.4186100262 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.240292252 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 38448668235 ps |
| CPU time | 79.06 seconds |
| Started | Mar 07 01:38:16 PM PST 24 |
| Finished | Mar 07 01:39:35 PM PST 24 |
| Peak memory | 211440 kb |
| Host | smart-94c95b1a-b04a-439b-bc3d-859d86a84582 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=240292252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.240292252 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1061363757 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 15621132614 ps |
| CPU time | 121.21 seconds |
| Started | Mar 07 01:38:10 PM PST 24 |
| Finished | Mar 07 01:40:11 PM PST 24 |
| Peak memory | 211340 kb |
| Host | smart-f4991815-d581-41b2-b9e2-f1411177030d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1061363757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1061363757 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1100093882 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 175775155 ps |
| CPU time | 20.46 seconds |
| Started | Mar 07 01:38:08 PM PST 24 |
| Finished | Mar 07 01:38:29 PM PST 24 |
| Peak memory | 204168 kb |
| Host | smart-12764e6f-8227-4589-9c59-cc2647187b5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100093882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1100093882 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_same_source.3123600451 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 206194253 ps |
| CPU time | 5.94 seconds |
| Started | Mar 07 01:38:17 PM PST 24 |
| Finished | Mar 07 01:38:23 PM PST 24 |
| Peak memory | 203700 kb |
| Host | smart-b79a6fdf-3fe6-4459-8d94-683fb520655f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3123600451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3123600451 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke.139260167 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 23969341 ps |
| CPU time | 2.34 seconds |
| Started | Mar 07 01:38:06 PM PST 24 |
| Finished | Mar 07 01:38:09 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-b7fd0729-462b-4cdd-baa9-564dae53e2af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=139260167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.139260167 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.12023128 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 9658851829 ps |
| CPU time | 35.15 seconds |
| Started | Mar 07 01:38:06 PM PST 24 |
| Finished | Mar 07 01:38:43 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-b3ddb12d-6957-4ca2-98b7-9d4327a03279 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=12023128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.12023128 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3943004228 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 6396608681 ps |
| CPU time | 27.45 seconds |
| Started | Mar 07 01:38:16 PM PST 24 |
| Finished | Mar 07 01:38:44 PM PST 24 |
| Peak memory | 203256 kb |
| Host | smart-e8545539-9218-4234-b4e0-36878ec91c61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3943004228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3943004228 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.4248137499 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 34612163 ps |
| CPU time | 1.99 seconds |
| Started | Mar 07 01:38:15 PM PST 24 |
| Finished | Mar 07 01:38:17 PM PST 24 |
| Peak memory | 203176 kb |
| Host | smart-001e094b-89b2-4698-872a-8f6a87d06646 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248137499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.4248137499 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all.90739185 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 9777170239 ps |
| CPU time | 87.92 seconds |
| Started | Mar 07 01:38:19 PM PST 24 |
| Finished | Mar 07 01:39:47 PM PST 24 |
| Peak memory | 207048 kb |
| Host | smart-3c840f4f-9ef4-4a6d-8fee-375c3e65840b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=90739185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.90739185 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.4176744977 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 4288699358 ps |
| CPU time | 84.1 seconds |
| Started | Mar 07 01:38:21 PM PST 24 |
| Finished | Mar 07 01:39:45 PM PST 24 |
| Peak memory | 206516 kb |
| Host | smart-966229b2-d4ab-4bb5-a23d-032a5b67f697 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4176744977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.4176744977 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1943754100 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 788158864 ps |
| CPU time | 272.38 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:42:53 PM PST 24 |
| Peak memory | 208656 kb |
| Host | smart-d3de4aaa-274f-4427-baba-658f485874d5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1943754100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran d_reset.1943754100 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.3745327753 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 187664537 ps |
| CPU time | 10.93 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:38:31 PM PST 24 |
| Peak memory | 204492 kb |
| Host | smart-72f66f82-f7e0-48bb-b6c0-3b9906b94583 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3745327753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3745327753 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2430276017 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 9207047003 ps |
| CPU time | 58.17 seconds |
| Started | Mar 07 01:37:29 PM PST 24 |
| Finished | Mar 07 01:38:27 PM PST 24 |
| Peak memory | 211384 kb |
| Host | smart-84ffe329-5346-4e7c-80da-926d39f8a9fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2430276017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2430276017 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.2817067390 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 56551466567 ps |
| CPU time | 272.33 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:41:43 PM PST 24 |
| Peak memory | 211272 kb |
| Host | smart-67659f6a-e5f0-49e5-9822-b1ce79d2e7b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2817067390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo w_rsp.2817067390 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.2658544771 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 860328333 ps |
| CPU time | 13.43 seconds |
| Started | Mar 07 01:37:12 PM PST 24 |
| Finished | Mar 07 01:37:26 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-22acc34c-9a4d-4eec-bb09-159073f59e6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2658544771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2658544771 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_error_random.2193268755 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 201349517 ps |
| CPU time | 18.8 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:37:30 PM PST 24 |
| Peak memory | 203228 kb |
| Host | smart-e95721cb-18d4-4529-bae8-4323f276f04b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2193268755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2193268755 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random.695611143 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 982267520 ps |
| CPU time | 33.73 seconds |
| Started | Mar 07 01:37:10 PM PST 24 |
| Finished | Mar 07 01:37:44 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-15e92f0a-83d5-48bc-87a1-8a5b33b2f771 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=695611143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.695611143 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.1884115305 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 14127620078 ps |
| CPU time | 72.17 seconds |
| Started | Mar 07 01:37:12 PM PST 24 |
| Finished | Mar 07 01:38:24 PM PST 24 |
| Peak memory | 211372 kb |
| Host | smart-33c3113a-7dea-4470-bb85-4a200594b655 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884115305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1884115305 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1737749294 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 9246921956 ps |
| CPU time | 91.83 seconds |
| Started | Mar 07 01:37:16 PM PST 24 |
| Finished | Mar 07 01:38:48 PM PST 24 |
| Peak memory | 204888 kb |
| Host | smart-0c322dd1-67b6-4381-b445-f77c6fbe9749 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1737749294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1737749294 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.15624745 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 323155960 ps |
| CPU time | 23.61 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:37:52 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-b2ad5d39-4306-4d81-9d13-e9e21f1fb5fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15624745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.15624745 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_same_source.3598517202 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 21619732 ps |
| CPU time | 2.27 seconds |
| Started | Mar 07 01:37:13 PM PST 24 |
| Finished | Mar 07 01:37:15 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-b68fc818-9dda-439c-b9eb-0cfae42a1773 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3598517202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3598517202 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke.2295995082 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 110843791 ps |
| CPU time | 3.66 seconds |
| Started | Mar 07 01:37:12 PM PST 24 |
| Finished | Mar 07 01:37:16 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-642bc372-ab3b-4188-8dba-7101114f2668 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2295995082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2295995082 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2743449203 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 5251573586 ps |
| CPU time | 27.02 seconds |
| Started | Mar 07 01:37:10 PM PST 24 |
| Finished | Mar 07 01:37:37 PM PST 24 |
| Peak memory | 203248 kb |
| Host | smart-3a1646cd-0ab5-47e7-b760-00c1378168c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743449203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2743449203 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3463155685 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 6663595571 ps |
| CPU time | 29.8 seconds |
| Started | Mar 07 01:37:10 PM PST 24 |
| Finished | Mar 07 01:37:40 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-37550c55-9b58-430a-a93b-88d436a3caf9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3463155685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3463155685 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3929111077 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 40209580 ps |
| CPU time | 1.87 seconds |
| Started | Mar 07 01:37:09 PM PST 24 |
| Finished | Mar 07 01:37:11 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-b20dd9bf-a5f1-4a20-8b48-fbee8b6528ba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929111077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3929111077 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3158723083 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1925510052 ps |
| CPU time | 119.44 seconds |
| Started | Mar 07 01:37:11 PM PST 24 |
| Finished | Mar 07 01:39:11 PM PST 24 |
| Peak memory | 208380 kb |
| Host | smart-71ba852a-892b-49f5-a7dc-250629b25771 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3158723083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3158723083 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1941579096 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 634224002 ps |
| CPU time | 38.89 seconds |
| Started | Mar 07 01:37:12 PM PST 24 |
| Finished | Mar 07 01:37:51 PM PST 24 |
| Peak memory | 204744 kb |
| Host | smart-32ca272d-0eaf-4bb7-a3c6-1c8e28af6e8c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941579096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1941579096 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1928384413 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 847613022 ps |
| CPU time | 262.99 seconds |
| Started | Mar 07 01:37:10 PM PST 24 |
| Finished | Mar 07 01:41:33 PM PST 24 |
| Peak memory | 209248 kb |
| Host | smart-e11cfc15-1347-4e36-9b31-3d672cadce08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1928384413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand _reset.1928384413 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.85321582 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 17775437119 ps |
| CPU time | 217.31 seconds |
| Started | Mar 07 01:37:13 PM PST 24 |
| Finished | Mar 07 01:40:51 PM PST 24 |
| Peak memory | 211144 kb |
| Host | smart-5a7b2c7c-47cc-4553-a7cb-a0e28e181496 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=85321582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset _error.85321582 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.973363727 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1112962853 ps |
| CPU time | 8.45 seconds |
| Started | Mar 07 01:37:16 PM PST 24 |
| Finished | Mar 07 01:37:24 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-faf36af9-8bbf-4083-add4-b491826814a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=973363727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.973363727 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.711079784 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1547696710 ps |
| CPU time | 42.45 seconds |
| Started | Mar 07 01:38:21 PM PST 24 |
| Finished | Mar 07 01:39:04 PM PST 24 |
| Peak memory | 205412 kb |
| Host | smart-609dfef3-5ca2-4463-b838-9d9eb239144d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=711079784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.711079784 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.59818018 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 36575314 ps |
| CPU time | 2.05 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:38:23 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-fb14f4fd-a73c-4ed6-aa65-88099e845af5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=59818018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.59818018 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_error_random.708374669 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 957682494 ps |
| CPU time | 9.38 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:38:32 PM PST 24 |
| Peak memory | 203156 kb |
| Host | smart-a8407bdd-b011-4903-9e64-488452d50a33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=708374669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.708374669 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random.3651437751 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 625058844 ps |
| CPU time | 13.35 seconds |
| Started | Mar 07 01:38:21 PM PST 24 |
| Finished | Mar 07 01:38:34 PM PST 24 |
| Peak memory | 204184 kb |
| Host | smart-bb3a14b9-d638-4add-8715-2f93413e6800 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3651437751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3651437751 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.1528135648 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 87806258902 ps |
| CPU time | 285.18 seconds |
| Started | Mar 07 01:38:18 PM PST 24 |
| Finished | Mar 07 01:43:03 PM PST 24 |
| Peak memory | 211396 kb |
| Host | smart-f12d106c-459c-4384-8b01-6a2b3b153ea3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528135648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1528135648 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.50402161 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 5208984568 ps |
| CPU time | 42.64 seconds |
| Started | Mar 07 01:38:21 PM PST 24 |
| Finished | Mar 07 01:39:04 PM PST 24 |
| Peak memory | 204308 kb |
| Host | smart-15b492c1-9c70-4523-b57c-0afe1b76d85f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=50402161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.50402161 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.3827756735 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 182973998 ps |
| CPU time | 14.13 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:38:35 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-8d4fc543-47e1-45e6-92e3-9c6cd1ca4471 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827756735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3827756735 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_same_source.1124830275 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 179629469 ps |
| CPU time | 6.32 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:38:29 PM PST 24 |
| Peak memory | 203796 kb |
| Host | smart-f64bb8e2-11b4-4669-a87a-34b835c24b61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1124830275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1124830275 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke.2864664829 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 169015063 ps |
| CPU time | 3.24 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:38:23 PM PST 24 |
| Peak memory | 203016 kb |
| Host | smart-8b4b5ece-b808-4115-98cf-431892a071b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2864664829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2864664829 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.350759341 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 13618891728 ps |
| CPU time | 39.48 seconds |
| Started | Mar 07 01:38:19 PM PST 24 |
| Finished | Mar 07 01:38:58 PM PST 24 |
| Peak memory | 203196 kb |
| Host | smart-3a6d6fa7-c5e4-45ef-8a9a-9687e74f79d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=350759341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.350759341 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1960529328 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 12172189330 ps |
| CPU time | 37.3 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:38:58 PM PST 24 |
| Peak memory | 203192 kb |
| Host | smart-420016ca-8d2a-491a-b607-51517c615917 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1960529328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1960529328 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.2765139167 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 23608364 ps |
| CPU time | 2.3 seconds |
| Started | Mar 07 01:38:18 PM PST 24 |
| Finished | Mar 07 01:38:20 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-a711a0bf-c3e9-4b1f-8d0f-d2b0a88600af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765139167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2765139167 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all.1952566066 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1712433712 ps |
| CPU time | 27.93 seconds |
| Started | Mar 07 01:38:21 PM PST 24 |
| Finished | Mar 07 01:38:49 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-1ff634c1-2e47-4310-bb20-d3df3a49505b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1952566066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1952566066 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.1941568044 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 11217503505 ps |
| CPU time | 157.26 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:41:00 PM PST 24 |
| Peak memory | 208288 kb |
| Host | smart-c5793cd5-48af-41ea-804f-c39b91c53a14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941568044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1941568044 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.937637977 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 776884180 ps |
| CPU time | 371.38 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:44:32 PM PST 24 |
| Peak memory | 208456 kb |
| Host | smart-490d54c0-3c45-4639-8e0e-266112e0c017 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=937637977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand _reset.937637977 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3788247753 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 546457101 ps |
| CPU time | 125.26 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:40:25 PM PST 24 |
| Peak memory | 211264 kb |
| Host | smart-16c93bbc-d3bd-4358-b305-4d2718cc665d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3788247753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re set_error.3788247753 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.3058114986 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1748807544 ps |
| CPU time | 23.3 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:38:45 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-3d667919-bf78-45ce-8c0e-a9026314e912 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3058114986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3058114986 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.3098590479 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 6837642808 ps |
| CPU time | 61.73 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:39:22 PM PST 24 |
| Peak memory | 206484 kb |
| Host | smart-b10dae7c-39e2-4377-b02c-87189c3fa1f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3098590479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.3098590479 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.365685134 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 58889973498 ps |
| CPU time | 369.05 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:44:32 PM PST 24 |
| Peak memory | 211280 kb |
| Host | smart-1b59ed74-21ee-447f-8262-ba748ca4012c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=365685134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slo w_rsp.365685134 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3607189753 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 475443126 ps |
| CPU time | 16.22 seconds |
| Started | Mar 07 01:38:19 PM PST 24 |
| Finished | Mar 07 01:38:35 PM PST 24 |
| Peak memory | 203332 kb |
| Host | smart-98873084-f989-4ed2-9fd1-4a186f81eea0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3607189753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3607189753 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_error_random.2643381332 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 211909611 ps |
| CPU time | 15.79 seconds |
| Started | Mar 07 01:38:19 PM PST 24 |
| Finished | Mar 07 01:38:35 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-54f69a4b-5121-40ad-af2d-8e9818403cc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2643381332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2643381332 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random.919032656 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1163421878 ps |
| CPU time | 36.29 seconds |
| Started | Mar 07 01:38:19 PM PST 24 |
| Finished | Mar 07 01:38:56 PM PST 24 |
| Peak memory | 204600 kb |
| Host | smart-d0bd5e21-5450-46c3-a00f-85d9edb13ac9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=919032656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.919032656 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.3287051993 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 47211425666 ps |
| CPU time | 138.45 seconds |
| Started | Mar 07 01:38:19 PM PST 24 |
| Finished | Mar 07 01:40:38 PM PST 24 |
| Peak memory | 204620 kb |
| Host | smart-29bf0f76-a108-436f-a021-624e3ed4165f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287051993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3287051993 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3391380974 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 55880287808 ps |
| CPU time | 187.05 seconds |
| Started | Mar 07 01:38:19 PM PST 24 |
| Finished | Mar 07 01:41:26 PM PST 24 |
| Peak memory | 204320 kb |
| Host | smart-6d34243a-e268-4235-bbdc-fbba11ca7651 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3391380974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3391380974 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.3291039836 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 24563768 ps |
| CPU time | 3.75 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:38:27 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-2793eb12-36f9-4334-afbe-0c7190549352 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291039836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.3291039836 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_same_source.465187612 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1643627476 ps |
| CPU time | 28.08 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:38:50 PM PST 24 |
| Peak memory | 203536 kb |
| Host | smart-ff02af8b-ee45-4491-be69-0ff1d4b825c6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=465187612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.465187612 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke.1846683584 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 44182061 ps |
| CPU time | 2.34 seconds |
| Started | Mar 07 01:38:24 PM PST 24 |
| Finished | Mar 07 01:38:27 PM PST 24 |
| Peak memory | 203172 kb |
| Host | smart-9d11169e-5fde-4ca3-849e-4dfa11f3bdbf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1846683584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1846683584 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.4215037197 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4036266392 ps |
| CPU time | 26.3 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:38:47 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-b18855a6-3266-4c4e-950c-35fff7691665 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215037197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.4215037197 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.2352072053 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3541612959 ps |
| CPU time | 30.9 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:38:51 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-be840991-8254-43d0-bc58-9696873ca010 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2352072053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2352072053 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.1196024172 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 51394799 ps |
| CPU time | 2.13 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:38:24 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-8192a233-f0eb-45df-bc4a-ad9ea95eb0ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196024172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.1196024172 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all.397328489 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1347786070 ps |
| CPU time | 76.44 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:39:39 PM PST 24 |
| Peak memory | 206744 kb |
| Host | smart-f898eb3b-4c36-402e-b107-65a76d5e198b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=397328489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.397328489 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.2553806062 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1937608990 ps |
| CPU time | 137.58 seconds |
| Started | Mar 07 01:38:23 PM PST 24 |
| Finished | Mar 07 01:40:41 PM PST 24 |
| Peak memory | 206044 kb |
| Host | smart-310b16ec-a7de-4c9a-b051-968590909330 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2553806062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2553806062 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3880856695 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 73802039 ps |
| CPU time | 23.65 seconds |
| Started | Mar 07 01:38:21 PM PST 24 |
| Finished | Mar 07 01:38:45 PM PST 24 |
| Peak memory | 205620 kb |
| Host | smart-c653d378-6018-48e6-8203-07e3e11178db |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3880856695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_ran d_reset.3880856695 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2008558372 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 809783924 ps |
| CPU time | 144.9 seconds |
| Started | Mar 07 01:38:24 PM PST 24 |
| Finished | Mar 07 01:40:49 PM PST 24 |
| Peak memory | 210784 kb |
| Host | smart-223d5856-fd19-4362-8eba-0747700dabdf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2008558372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re set_error.2008558372 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.2082047203 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 142584787 ps |
| CPU time | 5.7 seconds |
| Started | Mar 07 01:38:19 PM PST 24 |
| Finished | Mar 07 01:38:25 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-5fad8d64-4279-4298-8ed0-1b3e42c2504e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2082047203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2082047203 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.1173692639 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 336459898 ps |
| CPU time | 29.99 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:39:03 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-940b049b-fce5-444d-a5d0-d60f919cf0bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1173692639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1173692639 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1822040516 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 104663938983 ps |
| CPU time | 358.08 seconds |
| Started | Mar 07 01:38:29 PM PST 24 |
| Finished | Mar 07 01:44:28 PM PST 24 |
| Peak memory | 205472 kb |
| Host | smart-adda4205-9706-40fb-9d85-235f7e7964be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1822040516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl ow_rsp.1822040516 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2517038160 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 141746373 ps |
| CPU time | 15.23 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:47 PM PST 24 |
| Peak memory | 203224 kb |
| Host | smart-39085a77-e6bf-4518-8453-bfea152b7179 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2517038160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2517038160 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_error_random.2424857500 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 6172049243 ps |
| CPU time | 36.68 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:39:09 PM PST 24 |
| Peak memory | 203324 kb |
| Host | smart-fc11b98e-59f5-4742-a8d9-c1f6e85a37fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2424857500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2424857500 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random.1561400646 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 333260214 ps |
| CPU time | 13.02 seconds |
| Started | Mar 07 01:38:21 PM PST 24 |
| Finished | Mar 07 01:38:34 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-8a7e57d0-954b-48c5-8128-89fc41d69cba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1561400646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1561400646 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.1483096644 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 43663413982 ps |
| CPU time | 229.73 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:42:09 PM PST 24 |
| Peak memory | 211404 kb |
| Host | smart-90fbcc08-d696-4a53-b531-ae339882746b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483096644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1483096644 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.206344318 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2148984308 ps |
| CPU time | 12.54 seconds |
| Started | Mar 07 01:38:24 PM PST 24 |
| Finished | Mar 07 01:38:37 PM PST 24 |
| Peak memory | 203192 kb |
| Host | smart-2db144a1-3559-45ae-bcfc-af4ef18982f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=206344318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.206344318 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.1895651965 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 508911894 ps |
| CPU time | 19.29 seconds |
| Started | Mar 07 01:38:24 PM PST 24 |
| Finished | Mar 07 01:38:43 PM PST 24 |
| Peak memory | 204332 kb |
| Host | smart-32f739d7-087e-4fa2-9bb7-a0a0e311767c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895651965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1895651965 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_same_source.1680816736 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 295415951 ps |
| CPU time | 13.49 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:38:44 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-8daaddf3-dd39-4ca9-a885-1e3899ca1ba1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1680816736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1680816736 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke.3430526115 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 27771666 ps |
| CPU time | 2.28 seconds |
| Started | Mar 07 01:38:22 PM PST 24 |
| Finished | Mar 07 01:38:24 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-16e2a77c-7cea-4883-ad5d-01a8be092aca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3430526115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3430526115 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.136131343 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 8818177462 ps |
| CPU time | 25.87 seconds |
| Started | Mar 07 01:38:37 PM PST 24 |
| Finished | Mar 07 01:39:03 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-ee9de1f6-630c-40eb-8b85-7bc0f90de0a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=136131343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.136131343 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2777281918 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 6989393588 ps |
| CPU time | 31.57 seconds |
| Started | Mar 07 01:38:24 PM PST 24 |
| Finished | Mar 07 01:38:56 PM PST 24 |
| Peak memory | 203176 kb |
| Host | smart-9343bdaf-7f93-49f9-94b2-3bafcf9ec763 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2777281918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2777281918 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.943161438 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 33372948 ps |
| CPU time | 2.36 seconds |
| Started | Mar 07 01:38:20 PM PST 24 |
| Finished | Mar 07 01:38:23 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-008182bd-d2df-400a-8737-6a38aae4e185 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943161438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.943161438 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all.3679600978 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1327438947 ps |
| CPU time | 103.73 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:40:15 PM PST 24 |
| Peak memory | 205260 kb |
| Host | smart-b6a98fc2-ad18-40c8-92da-76ad7ccb432f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3679600978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3679600978 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.1583004846 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 3066437902 ps |
| CPU time | 330.53 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:44:01 PM PST 24 |
| Peak memory | 219672 kb |
| Host | smart-f2d4bce3-ccc9-4aba-93a4-82413a5fa0cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1583004846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re set_error.1583004846 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.409451070 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 434163208 ps |
| CPU time | 10.88 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:43 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-5e014d5e-538f-42bb-88db-732c5291cabe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=409451070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.409451070 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.4082694997 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1282238123 ps |
| CPU time | 47.78 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:39:20 PM PST 24 |
| Peak memory | 203908 kb |
| Host | smart-4a8453a4-5bc1-49cd-a522-240b4bdb0d1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4082694997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.4082694997 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3135957238 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 73373081265 ps |
| CPU time | 354.77 seconds |
| Started | Mar 07 01:38:30 PM PST 24 |
| Finished | Mar 07 01:44:26 PM PST 24 |
| Peak memory | 205584 kb |
| Host | smart-ae707ebb-f463-4a26-9eaf-e184944dc204 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3135957238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl ow_rsp.3135957238 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.4241143902 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 36336535 ps |
| CPU time | 3.6 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:38:35 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-97cbe2d0-e4dc-4a46-809f-c99fe2f78d0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4241143902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.4241143902 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_error_random.1033260543 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 420038294 ps |
| CPU time | 21.7 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:53 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-0d6a0e71-b663-401f-a0c0-dfb15caac77f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1033260543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1033260543 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random.4063205881 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 110468208 ps |
| CPU time | 2.65 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:35 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-13ab9a47-edb3-435a-a0ed-d390b7046032 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4063205881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.4063205881 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.1542935188 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 41443885074 ps |
| CPU time | 248.56 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:42:41 PM PST 24 |
| Peak memory | 211448 kb |
| Host | smart-d96d3ca1-bb2b-49a9-b979-c9005cc02946 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542935188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1542935188 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.874691745 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 27914917204 ps |
| CPU time | 201.66 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:41:55 PM PST 24 |
| Peak memory | 211388 kb |
| Host | smart-015bb904-3e66-4298-bf9c-322ccc2a5140 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=874691745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.874691745 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.395180395 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 141147221 ps |
| CPU time | 13.88 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:38:47 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-edb88b95-1fed-4387-902e-3f6022f6d216 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395180395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.395180395 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_same_source.2974969006 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1116053976 ps |
| CPU time | 24.19 seconds |
| Started | Mar 07 01:38:34 PM PST 24 |
| Finished | Mar 07 01:38:58 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-216bb6b2-a85b-493f-856d-aff9784c72e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2974969006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2974969006 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke.1283975154 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 148025101 ps |
| CPU time | 2.97 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:38:34 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-09fa6125-1686-4d78-ab24-840b10b15875 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1283975154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1283975154 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3440921878 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 34338742485 ps |
| CPU time | 47.43 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:39:20 PM PST 24 |
| Peak memory | 203160 kb |
| Host | smart-4e643f24-fb8e-458c-a7ea-0145012443e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440921878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3440921878 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3201850060 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 23044855 ps |
| CPU time | 2.47 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:34 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-8cb8803c-95bc-4a8a-b69c-e7970fb884ae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201850060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3201850060 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all.4102508659 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 16243852188 ps |
| CPU time | 107.97 seconds |
| Started | Mar 07 01:38:30 PM PST 24 |
| Finished | Mar 07 01:40:18 PM PST 24 |
| Peak memory | 206048 kb |
| Host | smart-80d84aff-1f59-49f5-934a-f6d8b54241d6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4102508659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.4102508659 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2716538410 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1235592505 ps |
| CPU time | 54.31 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:39:25 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-fc6d9634-5c73-4f21-a3cb-abff483d820b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2716538410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2716538410 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.4198898525 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 5073432882 ps |
| CPU time | 487.72 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:46:41 PM PST 24 |
| Peak memory | 219604 kb |
| Host | smart-d6d4f7d7-5c9f-44c1-bff7-4c5c83012617 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4198898525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran d_reset.4198898525 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2101415642 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 13521431352 ps |
| CPU time | 294.93 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:43:28 PM PST 24 |
| Peak memory | 219596 kb |
| Host | smart-ad414d00-8049-42ae-84e9-21378e63333b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2101415642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re set_error.2101415642 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.3242734567 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 372584231 ps |
| CPU time | 8.95 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:41 PM PST 24 |
| Peak memory | 204428 kb |
| Host | smart-a4e98f46-89b9-41fb-bd9b-51facbfe3e48 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3242734567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3242734567 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2526622932 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1073621633 ps |
| CPU time | 40.33 seconds |
| Started | Mar 07 01:38:30 PM PST 24 |
| Finished | Mar 07 01:39:10 PM PST 24 |
| Peak memory | 205428 kb |
| Host | smart-638b6eb7-11c5-4639-8193-b3cf6229c16c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2526622932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2526622932 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.254798267 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 24222358613 ps |
| CPU time | 240.54 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:42:33 PM PST 24 |
| Peak memory | 205712 kb |
| Host | smart-ebb04355-4272-429b-97c0-9de9310f9e8e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=254798267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo w_rsp.254798267 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.4020575864 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 187847277 ps |
| CPU time | 9.27 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:41 PM PST 24 |
| Peak memory | 203232 kb |
| Host | smart-8c25116e-6a86-46cf-beda-be902ef6506c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4020575864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.4020575864 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_error_random.1948991388 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1897402051 ps |
| CPU time | 34.29 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:39:05 PM PST 24 |
| Peak memory | 203268 kb |
| Host | smart-9ebbee44-ca37-46bd-956a-1f715e5758eb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1948991388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1948991388 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random.4053202343 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 350213477 ps |
| CPU time | 23.64 seconds |
| Started | Mar 07 01:38:29 PM PST 24 |
| Finished | Mar 07 01:38:53 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-b5c603dd-1108-4692-ab12-269adb1b1dc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4053202343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.4053202343 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2407830050 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 80142829854 ps |
| CPU time | 222.52 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:42:14 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-594a26c0-a1b0-4824-843c-2290bdf0bba6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407830050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2407830050 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2479492914 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 18627817436 ps |
| CPU time | 135.94 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:40:49 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-bb64e110-74c3-4cf5-8990-f593fec0d30f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2479492914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2479492914 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.1705722335 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 89142494 ps |
| CPU time | 16.73 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:38:48 PM PST 24 |
| Peak memory | 211228 kb |
| Host | smart-44575ffe-8a2a-48b8-b0e4-e5277fd2aca9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705722335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1705722335 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_same_source.1499708077 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1184391210 ps |
| CPU time | 9.82 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:38:43 PM PST 24 |
| Peak memory | 203716 kb |
| Host | smart-175c94e5-1acd-44d7-bdd4-ef7748797817 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1499708077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1499708077 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke.2144561346 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 110037555 ps |
| CPU time | 2.83 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:38:34 PM PST 24 |
| Peak memory | 203096 kb |
| Host | smart-267acb68-d91d-4b76-8e96-4d8d7ba88e23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2144561346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2144561346 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.2835143588 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 5455516689 ps |
| CPU time | 24.15 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:56 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-e84314c7-1878-456b-b89f-3f3cdbfb6f1c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835143588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2835143588 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.2347652372 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2122165617 ps |
| CPU time | 20.19 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:38:51 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-408cf7bb-112b-4b57-aa2f-8c0bdfecba1f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2347652372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2347652372 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3174085889 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 25209244 ps |
| CPU time | 2.21 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:38:33 PM PST 24 |
| Peak memory | 203016 kb |
| Host | smart-206fde29-e84d-4621-bcf9-0fa8f8d51931 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174085889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3174085889 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all.824093542 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13372314773 ps |
| CPU time | 317 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:43:51 PM PST 24 |
| Peak memory | 210232 kb |
| Host | smart-a63946ed-7753-4763-9e64-fa81f4dd681c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=824093542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.824093542 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1920250713 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 17082462537 ps |
| CPU time | 198.7 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:41:52 PM PST 24 |
| Peak memory | 208648 kb |
| Host | smart-91c238f3-09d9-4d1d-a635-5f190cec2723 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1920250713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1920250713 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.3345167954 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 916642706 ps |
| CPU time | 271.75 seconds |
| Started | Mar 07 01:38:34 PM PST 24 |
| Finished | Mar 07 01:43:06 PM PST 24 |
| Peak memory | 208792 kb |
| Host | smart-7411d9dd-7382-4f79-8dfc-2feef8d6c982 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3345167954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_ran d_reset.3345167954 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.4258125528 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1656966380 ps |
| CPU time | 222.29 seconds |
| Started | Mar 07 01:38:34 PM PST 24 |
| Finished | Mar 07 01:42:16 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-4e373e54-6d88-45bd-8c27-e2ea97c4875e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4258125528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re set_error.4258125528 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.473404464 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 138601766 ps |
| CPU time | 6.68 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:39 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-08a7b794-5395-435d-93af-21b715a1bd65 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=473404464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.473404464 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.2901075451 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 449870441 ps |
| CPU time | 17.57 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:50 PM PST 24 |
| Peak memory | 205384 kb |
| Host | smart-b4c4c15b-5021-4712-a72b-2d6c97f802cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2901075451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2901075451 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.745235639 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 130439328864 ps |
| CPU time | 367.39 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:44:40 PM PST 24 |
| Peak memory | 206224 kb |
| Host | smart-a85475d9-92a8-48ce-8951-482092befbd2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=745235639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slo w_rsp.745235639 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2533767406 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 23963136 ps |
| CPU time | 3.48 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:38:36 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-b26e5435-b1ac-4633-9646-1f3a33aea7b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2533767406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2533767406 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_error_random.2015284906 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 463199186 ps |
| CPU time | 12.38 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:38:46 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-e7c0ae40-d267-49b8-bbbe-388e525c0f11 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2015284906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2015284906 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random.896116985 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 673513277 ps |
| CPU time | 20.4 seconds |
| Started | Mar 07 01:38:34 PM PST 24 |
| Finished | Mar 07 01:38:54 PM PST 24 |
| Peak memory | 203848 kb |
| Host | smart-5047c591-1577-40dc-9ba9-720fd441ed5d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=896116985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.896116985 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.3171996720 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 19731253107 ps |
| CPU time | 84.95 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:39:56 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-8aa17769-010a-430c-b8c3-321cd6cef743 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171996720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3171996720 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.4102512167 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 18983383330 ps |
| CPU time | 88.06 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:40:02 PM PST 24 |
| Peak memory | 204588 kb |
| Host | smart-44637d6e-f5f0-458f-9c7d-95e4757350b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4102512167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4102512167 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.1328680268 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 52330517 ps |
| CPU time | 5.29 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:38:38 PM PST 24 |
| Peak memory | 203092 kb |
| Host | smart-07b53a76-1242-4209-89fa-0df9d46955c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328680268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1328680268 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_same_source.3936966361 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 345245637 ps |
| CPU time | 7.94 seconds |
| Started | Mar 07 01:38:34 PM PST 24 |
| Finished | Mar 07 01:38:42 PM PST 24 |
| Peak memory | 203512 kb |
| Host | smart-222890d8-d0d8-477a-906f-0d82cb6971a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3936966361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3936966361 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke.1958110925 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 166536906 ps |
| CPU time | 3.77 seconds |
| Started | Mar 07 01:38:32 PM PST 24 |
| Finished | Mar 07 01:38:36 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-d02f1899-8c54-43e1-9829-d81ab896a4ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1958110925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1958110925 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.3923534247 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 9424034974 ps |
| CPU time | 30.17 seconds |
| Started | Mar 07 01:38:31 PM PST 24 |
| Finished | Mar 07 01:39:02 PM PST 24 |
| Peak memory | 203248 kb |
| Host | smart-834bc30c-f063-4ab8-98b4-42f2156084a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923534247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3923534247 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.1712109624 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 8569814727 ps |
| CPU time | 36.14 seconds |
| Started | Mar 07 01:38:34 PM PST 24 |
| Finished | Mar 07 01:39:10 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-cd5c79ee-dc43-43cb-b3c9-649e5c715049 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1712109624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1712109624 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2630871779 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 115270963 ps |
| CPU time | 2.21 seconds |
| Started | Mar 07 01:38:33 PM PST 24 |
| Finished | Mar 07 01:38:36 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-b1fdc981-5875-4627-b67a-a54f57534993 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630871779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2630871779 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all.1831255441 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 727421665 ps |
| CPU time | 53.57 seconds |
| Started | Mar 07 01:38:40 PM PST 24 |
| Finished | Mar 07 01:39:33 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-199e876a-e3db-4236-a31a-1b95c38253b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1831255441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1831255441 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1309843840 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 7196003188 ps |
| CPU time | 166.5 seconds |
| Started | Mar 07 01:38:42 PM PST 24 |
| Finished | Mar 07 01:41:29 PM PST 24 |
| Peak memory | 206432 kb |
| Host | smart-a979e0a9-6711-4610-8c31-c2efe4358d6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1309843840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1309843840 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.888863710 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5254194190 ps |
| CPU time | 331.64 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:44:15 PM PST 24 |
| Peak memory | 208204 kb |
| Host | smart-72566215-d49f-41da-afab-6d2262377249 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=888863710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand _reset.888863710 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3124309817 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 431270668 ps |
| CPU time | 111.9 seconds |
| Started | Mar 07 01:38:40 PM PST 24 |
| Finished | Mar 07 01:40:32 PM PST 24 |
| Peak memory | 209320 kb |
| Host | smart-a9942add-3d9d-4c2d-8392-4ff52a888396 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3124309817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re set_error.3124309817 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.2393602669 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 85405118 ps |
| CPU time | 5.05 seconds |
| Started | Mar 07 01:38:29 PM PST 24 |
| Finished | Mar 07 01:38:35 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-57f73c25-b90e-49ee-88de-95db728c855f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2393602669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2393602669 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.3999229293 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 186056627 ps |
| CPU time | 17.13 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:39:01 PM PST 24 |
| Peak memory | 204184 kb |
| Host | smart-d2b0a2a5-bb2a-4b72-870b-7825d6823ae2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3999229293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.3999229293 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.2510038756 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 72794835 ps |
| CPU time | 5.74 seconds |
| Started | Mar 07 01:38:41 PM PST 24 |
| Finished | Mar 07 01:38:47 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-81ada848-3e3f-4d6d-9358-2596b023b288 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2510038756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2510038756 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_error_random.2876091828 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 783373893 ps |
| CPU time | 26.59 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:39:09 PM PST 24 |
| Peak memory | 203036 kb |
| Host | smart-d44878a4-128d-481c-a094-a58a66f54189 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2876091828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2876091828 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random.3324011623 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 103473209 ps |
| CPU time | 11.4 seconds |
| Started | Mar 07 01:38:41 PM PST 24 |
| Finished | Mar 07 01:38:52 PM PST 24 |
| Peak memory | 211404 kb |
| Host | smart-0992fda1-ec13-4838-ab43-b32f1e357adc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3324011623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3324011623 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3786361941 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 28326789078 ps |
| CPU time | 258.55 seconds |
| Started | Mar 07 01:38:42 PM PST 24 |
| Finished | Mar 07 01:43:00 PM PST 24 |
| Peak memory | 204408 kb |
| Host | smart-8b305e35-0545-4630-ad05-f4328ff00469 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3786361941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3786361941 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.2355878802 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 183111203 ps |
| CPU time | 5.18 seconds |
| Started | Mar 07 01:38:40 PM PST 24 |
| Finished | Mar 07 01:38:45 PM PST 24 |
| Peak memory | 204164 kb |
| Host | smart-68a216f5-0871-49b3-9175-6f677b348fd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355878802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2355878802 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_same_source.191687568 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3628573335 ps |
| CPU time | 25.86 seconds |
| Started | Mar 07 01:38:42 PM PST 24 |
| Finished | Mar 07 01:39:08 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-c0aa8ae9-6057-418e-abcf-232a2f67c301 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=191687568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.191687568 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke.58580069 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 206128853 ps |
| CPU time | 3.41 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:38:46 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-ac4e13f5-cf88-4c92-b8e1-dc6cf3774065 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=58580069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.58580069 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.1460268432 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6590001405 ps |
| CPU time | 32.76 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:39:16 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-08ebdfe5-57cb-43fa-8f2e-1f3c0b2410c8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460268432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1460268432 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1328366184 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4192940913 ps |
| CPU time | 27.21 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:39:11 PM PST 24 |
| Peak memory | 203168 kb |
| Host | smart-b7d21ded-3b1f-497b-ba22-186c8f443f2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1328366184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1328366184 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2087085279 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 34762762 ps |
| CPU time | 2.05 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:38:45 PM PST 24 |
| Peak memory | 203064 kb |
| Host | smart-267af2df-31bc-4309-9afc-cc06de00d222 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087085279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2087085279 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all.4254661083 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 6445927 ps |
| CPU time | 0.82 seconds |
| Started | Mar 07 01:38:42 PM PST 24 |
| Finished | Mar 07 01:38:42 PM PST 24 |
| Peak memory | 194924 kb |
| Host | smart-9b43824a-9600-4ecb-8f37-8a5a49e7aef4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4254661083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.4254661083 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.1423116492 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 7968383037 ps |
| CPU time | 98.88 seconds |
| Started | Mar 07 01:38:42 PM PST 24 |
| Finished | Mar 07 01:40:21 PM PST 24 |
| Peak memory | 211436 kb |
| Host | smart-75e75491-2bf3-419b-8636-59d67adf133d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1423116492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1423116492 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.262762870 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1676830435 ps |
| CPU time | 200.94 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:42:05 PM PST 24 |
| Peak memory | 209160 kb |
| Host | smart-7ef5e9dd-a7c9-4489-b5d4-410459b780b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=262762870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand _reset.262762870 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1708116533 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 7182857 ps |
| CPU time | 5.24 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:38:48 PM PST 24 |
| Peak memory | 203252 kb |
| Host | smart-56ced0fc-7032-4d7e-ba61-a83ad2f6fcca |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1708116533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re set_error.1708116533 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.2928854791 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 137677049 ps |
| CPU time | 21.17 seconds |
| Started | Mar 07 01:38:42 PM PST 24 |
| Finished | Mar 07 01:39:03 PM PST 24 |
| Peak memory | 211348 kb |
| Host | smart-9ecd705e-0066-4830-aadb-df05ecf97dba |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2928854791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2928854791 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.439076667 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 125925609 ps |
| CPU time | 19.17 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:39:03 PM PST 24 |
| Peak memory | 203688 kb |
| Host | smart-91710a81-32c1-4b10-81ce-4506da5a2dac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=439076667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.439076667 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.3609505924 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 29378266077 ps |
| CPU time | 293.81 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:43:38 PM PST 24 |
| Peak memory | 206120 kb |
| Host | smart-976804c0-b658-4fad-bfae-b154d172e269 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3609505924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl ow_rsp.3609505924 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1102223707 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 26436736 ps |
| CPU time | 3.78 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:38:48 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-e4917dff-fb44-40e0-891e-a40f1dfe3155 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1102223707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1102223707 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_error_random.3046711339 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 3845417415 ps |
| CPU time | 29.83 seconds |
| Started | Mar 07 01:38:42 PM PST 24 |
| Finished | Mar 07 01:39:12 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-7d677a3c-213b-44a9-b57f-87abccf11fd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3046711339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3046711339 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random.927065758 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 338863310 ps |
| CPU time | 8.11 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:38:52 PM PST 24 |
| Peak memory | 203972 kb |
| Host | smart-6a920dd3-4d89-4fed-9155-e4323a07a4be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=927065758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.927065758 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.2709064511 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 87848927499 ps |
| CPU time | 167.7 seconds |
| Started | Mar 07 01:38:45 PM PST 24 |
| Finished | Mar 07 01:41:33 PM PST 24 |
| Peak memory | 204400 kb |
| Host | smart-ac5e175b-c2e3-423e-8287-7f6c7d065a29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709064511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2709064511 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3688438893 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 26550518337 ps |
| CPU time | 229.21 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:42:33 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-9b4556ea-ef3e-442d-af23-f2f1f38e3b7d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3688438893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3688438893 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.922263639 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 110610165 ps |
| CPU time | 16.69 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:39:01 PM PST 24 |
| Peak memory | 204408 kb |
| Host | smart-3c376160-80a0-4416-a335-9fbe6cae3a4a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922263639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.922263639 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_same_source.1017963337 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1259405230 ps |
| CPU time | 11.94 seconds |
| Started | Mar 07 01:38:45 PM PST 24 |
| Finished | Mar 07 01:38:57 PM PST 24 |
| Peak memory | 203536 kb |
| Host | smart-1e1e7d13-f506-4885-9ea0-3d84e45b2fb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1017963337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1017963337 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke.230381899 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 22801185 ps |
| CPU time | 2.07 seconds |
| Started | Mar 07 01:38:45 PM PST 24 |
| Finished | Mar 07 01:38:47 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-4d8943cb-634b-4233-a11b-743389a617f2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=230381899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.230381899 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.1478073485 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 5525734021 ps |
| CPU time | 29.78 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:39:13 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-a337f25c-9e00-45c9-b853-7ce06f0a689b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478073485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1478073485 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2772348088 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 9876821356 ps |
| CPU time | 29.63 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:39:12 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-5d3098c8-3565-4993-b4c3-4c6542185346 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2772348088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2772348088 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.682335914 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 47265156 ps |
| CPU time | 2.27 seconds |
| Started | Mar 07 01:38:42 PM PST 24 |
| Finished | Mar 07 01:38:44 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-37d017bd-2c89-41dd-b0cb-473748ab57f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682335914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.682335914 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all.3243196059 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 3431349401 ps |
| CPU time | 25.18 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:39:10 PM PST 24 |
| Peak memory | 204712 kb |
| Host | smart-c654b170-8cf5-4657-b6be-88c9825b6b63 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3243196059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3243196059 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.1005169627 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 4723445681 ps |
| CPU time | 150.06 seconds |
| Started | Mar 07 01:38:42 PM PST 24 |
| Finished | Mar 07 01:41:12 PM PST 24 |
| Peak memory | 206380 kb |
| Host | smart-5dac02e4-78e2-4827-bd92-4aa546d7aa8d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1005169627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1005169627 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1054513770 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1641769110 ps |
| CPU time | 405.6 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:45:29 PM PST 24 |
| Peak memory | 219512 kb |
| Host | smart-fe57c1d3-eb16-40a5-88a0-5c4ed3948610 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1054513770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_ran d_reset.1054513770 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.723018330 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 255963209 ps |
| CPU time | 61.3 seconds |
| Started | Mar 07 01:38:43 PM PST 24 |
| Finished | Mar 07 01:39:44 PM PST 24 |
| Peak memory | 207696 kb |
| Host | smart-b1aff773-7c1d-44f4-92ff-143dd9474ab5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=723018330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_res et_error.723018330 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2271499479 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 474378002 ps |
| CPU time | 14.47 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:38:59 PM PST 24 |
| Peak memory | 204760 kb |
| Host | smart-d92d5b0a-0e8f-4cc5-a0c8-d4b4a528c8ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2271499479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2271499479 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.3453437783 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1200178337 ps |
| CPU time | 44.72 seconds |
| Started | Mar 07 01:38:55 PM PST 24 |
| Finished | Mar 07 01:39:43 PM PST 24 |
| Peak memory | 205592 kb |
| Host | smart-a113bc05-6f19-46d6-be27-ca02e0473896 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3453437783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3453437783 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.781501637 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 126683080799 ps |
| CPU time | 329.27 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:44:28 PM PST 24 |
| Peak memory | 206212 kb |
| Host | smart-edffb840-1a87-44df-9fe1-dca6af8a037d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=781501637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slo w_rsp.781501637 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2370479520 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 85321976 ps |
| CPU time | 10.86 seconds |
| Started | Mar 07 01:38:59 PM PST 24 |
| Finished | Mar 07 01:39:10 PM PST 24 |
| Peak memory | 203384 kb |
| Host | smart-2fcf2832-cf55-4a5b-880c-d1c572c8772a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2370479520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2370479520 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_error_random.3751334045 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 778069239 ps |
| CPU time | 23.06 seconds |
| Started | Mar 07 01:38:54 PM PST 24 |
| Finished | Mar 07 01:39:21 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-19fde42b-1e95-4803-9cb1-9ea2208f3225 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3751334045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3751334045 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random.2711240563 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 713573555 ps |
| CPU time | 30.63 seconds |
| Started | Mar 07 01:39:00 PM PST 24 |
| Finished | Mar 07 01:39:30 PM PST 24 |
| Peak memory | 204180 kb |
| Host | smart-5516541d-5c80-44a5-b21f-850af4c16a99 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2711240563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2711240563 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.2938227755 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 21032341890 ps |
| CPU time | 112.04 seconds |
| Started | Mar 07 01:38:53 PM PST 24 |
| Finished | Mar 07 01:40:46 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-cd689b4f-25eb-4934-979c-5a99fd7054fd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938227755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2938227755 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.3699899933 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 12332693495 ps |
| CPU time | 107.43 seconds |
| Started | Mar 07 01:38:54 PM PST 24 |
| Finished | Mar 07 01:40:45 PM PST 24 |
| Peak memory | 211356 kb |
| Host | smart-1b043273-807a-4ee7-8b67-7c4a708b0291 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3699899933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3699899933 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.3843892833 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 184233123 ps |
| CPU time | 25.51 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:39:24 PM PST 24 |
| Peak memory | 211260 kb |
| Host | smart-2ebebac0-18c2-46af-b8c6-d9ab263baf86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843892833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3843892833 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_same_source.350916246 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 3766992561 ps |
| CPU time | 24.25 seconds |
| Started | Mar 07 01:39:00 PM PST 24 |
| Finished | Mar 07 01:39:24 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-bf25e40f-48b1-465c-8ec5-dd2c37c7bf2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=350916246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.350916246 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke.317270799 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 488536900 ps |
| CPU time | 3.92 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:38:49 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-77286897-4a28-43f6-9e02-5d63b21a9b66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=317270799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.317270799 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.765971980 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 6858166473 ps |
| CPU time | 39.06 seconds |
| Started | Mar 07 01:38:45 PM PST 24 |
| Finished | Mar 07 01:39:24 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-d10b1b1a-2201-4e9c-9d85-c09eb8c5b30f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=765971980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.765971980 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3873082513 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3953564381 ps |
| CPU time | 29.73 seconds |
| Started | Mar 07 01:38:49 PM PST 24 |
| Finished | Mar 07 01:39:19 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-95d42365-c459-424a-ab75-0e061af0d367 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3873082513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3873082513 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.2947388503 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 50307757 ps |
| CPU time | 2.58 seconds |
| Started | Mar 07 01:38:44 PM PST 24 |
| Finished | Mar 07 01:38:47 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-20b3465c-a1ec-4183-b785-c042c8a957d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947388503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.2947388503 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all.41323025 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1992089494 ps |
| CPU time | 131.46 seconds |
| Started | Mar 07 01:38:58 PM PST 24 |
| Finished | Mar 07 01:41:10 PM PST 24 |
| Peak memory | 207852 kb |
| Host | smart-7cf2e46c-d53e-43b5-8ffd-08d515f4f5be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=41323025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.41323025 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.156922653 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 7723151043 ps |
| CPU time | 122.32 seconds |
| Started | Mar 07 01:38:54 PM PST 24 |
| Finished | Mar 07 01:40:59 PM PST 24 |
| Peak memory | 211380 kb |
| Host | smart-e9958674-248f-48e0-98f5-01fe526ddd9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=156922653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.156922653 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4189143355 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 11820526 ps |
| CPU time | 21.29 seconds |
| Started | Mar 07 01:38:56 PM PST 24 |
| Finished | Mar 07 01:39:20 PM PST 24 |
| Peak memory | 205032 kb |
| Host | smart-da1ca3c5-ddd0-4c76-8a3f-4aecf8142209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4189143355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re set_error.4189143355 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2964165117 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 95312812 ps |
| CPU time | 9.32 seconds |
| Started | Mar 07 01:38:55 PM PST 24 |
| Finished | Mar 07 01:39:07 PM PST 24 |
| Peak memory | 211292 kb |
| Host | smart-c2de03ad-3bf8-4c53-be88-d9914e99b82d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2964165117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2964165117 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1702914570 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 564449722 ps |
| CPU time | 46.31 seconds |
| Started | Mar 07 01:39:00 PM PST 24 |
| Finished | Mar 07 01:39:46 PM PST 24 |
| Peak memory | 205864 kb |
| Host | smart-9759d7d9-74aa-451a-b6c6-9fdff483bd51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1702914570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1702914570 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.1890578115 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 105197806812 ps |
| CPU time | 448.75 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:46:27 PM PST 24 |
| Peak memory | 206256 kb |
| Host | smart-7e5807fc-32a4-4fa2-ab9b-9338145fd4ff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1890578115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl ow_rsp.1890578115 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1207115191 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 38061034 ps |
| CPU time | 2.09 seconds |
| Started | Mar 07 01:38:56 PM PST 24 |
| Finished | Mar 07 01:39:00 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-47af7060-e3a1-407f-8795-bccb5b080076 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1207115191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1207115191 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_error_random.1634050686 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 171751135 ps |
| CPU time | 14.15 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:39:13 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-6ea28a9b-7f91-4cdb-9f73-c9eb52b689a7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1634050686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1634050686 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random.3590653018 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 935011469 ps |
| CPU time | 15.74 seconds |
| Started | Mar 07 01:38:59 PM PST 24 |
| Finished | Mar 07 01:39:15 PM PST 24 |
| Peak memory | 204176 kb |
| Host | smart-6bc78585-2cec-4f63-8bab-d1f94183306f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3590653018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3590653018 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2584780160 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 31597804766 ps |
| CPU time | 82.19 seconds |
| Started | Mar 07 01:38:55 PM PST 24 |
| Finished | Mar 07 01:40:20 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-d59a0254-a329-45d9-967e-c5d84f0800ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584780160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2584780160 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1814057568 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 4291900703 ps |
| CPU time | 17.51 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:39:16 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-ec3f5ac2-d0bd-42e6-a2b9-7ac76c640480 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1814057568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1814057568 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.3571931802 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 259040153 ps |
| CPU time | 19.08 seconds |
| Started | Mar 07 01:38:58 PM PST 24 |
| Finished | Mar 07 01:39:18 PM PST 24 |
| Peak memory | 211260 kb |
| Host | smart-7872ec93-a511-4567-8c5d-3d382631efee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571931802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.3571931802 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_same_source.2937314304 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 167931148 ps |
| CPU time | 13.83 seconds |
| Started | Mar 07 01:38:55 PM PST 24 |
| Finished | Mar 07 01:39:12 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-642d7e8b-8f24-425a-bd5e-c4f085e5b221 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2937314304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2937314304 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke.2728175706 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 60533359 ps |
| CPU time | 2.01 seconds |
| Started | Mar 07 01:38:54 PM PST 24 |
| Finished | Mar 07 01:38:59 PM PST 24 |
| Peak memory | 203160 kb |
| Host | smart-73ade3ed-67dc-4210-bb34-20d2df864f44 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2728175706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2728175706 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1661986602 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5342205452 ps |
| CPU time | 29.99 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:39:28 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-c87ba58c-2173-4a13-9375-bd9bd3920b61 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661986602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1661986602 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4072240960 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 3856207968 ps |
| CPU time | 29.67 seconds |
| Started | Mar 07 01:38:56 PM PST 24 |
| Finished | Mar 07 01:39:28 PM PST 24 |
| Peak memory | 203252 kb |
| Host | smart-aba6e34a-2d41-46f0-a136-d12408922e73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4072240960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4072240960 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3967381416 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 95909235 ps |
| CPU time | 2.69 seconds |
| Started | Mar 07 01:38:58 PM PST 24 |
| Finished | Mar 07 01:39:01 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-adc332da-2513-4a90-b229-78dfabe02988 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967381416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3967381416 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all.804249211 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 4752888097 ps |
| CPU time | 133.99 seconds |
| Started | Mar 07 01:39:01 PM PST 24 |
| Finished | Mar 07 01:41:15 PM PST 24 |
| Peak memory | 206804 kb |
| Host | smart-3282d2ca-3d0d-428e-a137-6efb682f8e25 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=804249211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.804249211 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3115094942 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 8864125853 ps |
| CPU time | 158.74 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:41:37 PM PST 24 |
| Peak memory | 207528 kb |
| Host | smart-ca5c9e70-21d2-4bf2-baf8-ddc6f148b2de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3115094942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3115094942 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3534916116 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3094596728 ps |
| CPU time | 125.02 seconds |
| Started | Mar 07 01:38:56 PM PST 24 |
| Finished | Mar 07 01:41:03 PM PST 24 |
| Peak memory | 207980 kb |
| Host | smart-60ebb9b0-7e50-4b94-aafb-5ef61f3a33ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3534916116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran d_reset.3534916116 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.879210704 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 501784738 ps |
| CPU time | 176.29 seconds |
| Started | Mar 07 01:38:58 PM PST 24 |
| Finished | Mar 07 01:41:55 PM PST 24 |
| Peak memory | 210820 kb |
| Host | smart-194ecb52-af09-412e-9a69-a7b730b9b171 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=879210704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_res et_error.879210704 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.2446281489 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 80595891 ps |
| CPU time | 8.33 seconds |
| Started | Mar 07 01:38:55 PM PST 24 |
| Finished | Mar 07 01:39:06 PM PST 24 |
| Peak memory | 204576 kb |
| Host | smart-9072158a-10e5-4a0e-a233-af6ff96e05f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2446281489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2446281489 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1764403793 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 15883487 ps |
| CPU time | 2.51 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:37:28 PM PST 24 |
| Peak memory | 203044 kb |
| Host | smart-f18baeee-1124-4ca7-8b67-82ded3781b95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1764403793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1764403793 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3922701681 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 195426274 ps |
| CPU time | 14.78 seconds |
| Started | Mar 07 01:37:25 PM PST 24 |
| Finished | Mar 07 01:37:40 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-a2110502-5138-4cbf-b995-ae11ef888aea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3922701681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3922701681 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_error_random.1531570357 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 293830590 ps |
| CPU time | 17.54 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:37:45 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-666825a2-f1f2-4c8a-8b71-7a0922cba440 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1531570357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1531570357 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random.3002592800 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 262565523 ps |
| CPU time | 9.84 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:37:36 PM PST 24 |
| Peak memory | 204236 kb |
| Host | smart-18ceb838-8f19-4ca9-98b6-89a87d2e8548 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3002592800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3002592800 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.2965120766 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 20040117516 ps |
| CPU time | 117.29 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:39:23 PM PST 24 |
| Peak memory | 204440 kb |
| Host | smart-af4963d1-a2ec-4635-ba8b-70037fd58fce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965120766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2965120766 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.870628627 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 63644842474 ps |
| CPU time | 237.98 seconds |
| Started | Mar 07 01:37:24 PM PST 24 |
| Finished | Mar 07 01:41:23 PM PST 24 |
| Peak memory | 211392 kb |
| Host | smart-4a3eeb35-bd2b-4c23-8981-4a173b2260fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=870628627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.870628627 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.746894686 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 72965061 ps |
| CPU time | 7.07 seconds |
| Started | Mar 07 01:37:22 PM PST 24 |
| Finished | Mar 07 01:37:29 PM PST 24 |
| Peak memory | 204332 kb |
| Host | smart-817c8c21-8aa4-4757-ba12-e02d7f6a564d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746894686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.746894686 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_same_source.861951776 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3515228283 ps |
| CPU time | 17.06 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:37:43 PM PST 24 |
| Peak memory | 203632 kb |
| Host | smart-9d358e8c-340d-40af-a1b3-5c87698902e4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=861951776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.861951776 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke.1692710866 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 198078163 ps |
| CPU time | 3.73 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:37:31 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-e93d0085-e7cc-4c21-bc60-5e52e10064de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1692710866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1692710866 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1511245408 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 7463200034 ps |
| CPU time | 27.72 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:37:57 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-a622c6ee-3d01-4960-9485-528143bff24e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511245408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1511245408 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3371240050 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 5164877618 ps |
| CPU time | 28.34 seconds |
| Started | Mar 07 01:37:25 PM PST 24 |
| Finished | Mar 07 01:37:54 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-eb868327-7a2e-42d2-8f2a-73e8b25b673b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3371240050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3371240050 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3438839170 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 29812441 ps |
| CPU time | 2.5 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:37:29 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-6711aee6-a5ee-4253-bf53-9235a5dd0bfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438839170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3438839170 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all.391336693 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 488937578 ps |
| CPU time | 62.66 seconds |
| Started | Mar 07 01:37:24 PM PST 24 |
| Finished | Mar 07 01:38:27 PM PST 24 |
| Peak memory | 205904 kb |
| Host | smart-128e429d-dfd7-48cf-ab30-846f6d1087b1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=391336693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.391336693 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.4230853999 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1879952568 ps |
| CPU time | 133.2 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:39:40 PM PST 24 |
| Peak memory | 208896 kb |
| Host | smart-79c851ff-a13c-4515-bf22-732a94766b0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4230853999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4230853999 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1587985863 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 6110258636 ps |
| CPU time | 407.9 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:44:14 PM PST 24 |
| Peak memory | 211352 kb |
| Host | smart-ab59f660-da9c-406f-a78b-0571b0a643ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1587985863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand _reset.1587985863 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.462650356 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 31023811 ps |
| CPU time | 9.15 seconds |
| Started | Mar 07 01:37:24 PM PST 24 |
| Finished | Mar 07 01:37:35 PM PST 24 |
| Peak memory | 203172 kb |
| Host | smart-08e1f78f-e46c-4357-9a15-66fac1ede4ad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=462650356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rese t_error.462650356 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.78194680 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 700598395 ps |
| CPU time | 20.99 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:37:49 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-7c894765-3a2f-4bbd-9863-5b9e35568ce3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=78194680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.78194680 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1977811286 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2803448369 ps |
| CPU time | 80.73 seconds |
| Started | Mar 07 01:39:01 PM PST 24 |
| Finished | Mar 07 01:40:22 PM PST 24 |
| Peak memory | 205984 kb |
| Host | smart-df9b6a4a-57df-4ea3-9b8e-162af2e22c0a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1977811286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1977811286 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.162527680 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 35597588695 ps |
| CPU time | 109.05 seconds |
| Started | Mar 07 01:38:53 PM PST 24 |
| Finished | Mar 07 01:40:42 PM PST 24 |
| Peak memory | 211272 kb |
| Host | smart-e728da33-2039-4769-81d7-e4e71e33ee2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=162527680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slo w_rsp.162527680 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.387260466 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 48052173 ps |
| CPU time | 4.64 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:39:09 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-6eefc4c6-c1dc-4d7f-a498-6ffc18b5ba9d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=387260466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.387260466 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_error_random.2286603164 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 177563635 ps |
| CPU time | 7.48 seconds |
| Started | Mar 07 01:38:55 PM PST 24 |
| Finished | Mar 07 01:39:06 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-4c10f80a-0138-4aed-ab46-3aed94b53bd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2286603164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2286603164 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random.1908817267 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 263697166 ps |
| CPU time | 21.46 seconds |
| Started | Mar 07 01:39:00 PM PST 24 |
| Finished | Mar 07 01:39:22 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-24d118d7-eac1-45ba-98a0-41369b7b8ca8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1908817267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1908817267 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.3709255481 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 147371552271 ps |
| CPU time | 260.88 seconds |
| Started | Mar 07 01:38:56 PM PST 24 |
| Finished | Mar 07 01:43:19 PM PST 24 |
| Peak memory | 204380 kb |
| Host | smart-03e2d3d3-8a4b-4b41-afec-a520d1797680 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709255481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3709255481 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.162189550 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 26782843971 ps |
| CPU time | 222.37 seconds |
| Started | Mar 07 01:38:55 PM PST 24 |
| Finished | Mar 07 01:42:40 PM PST 24 |
| Peak memory | 204292 kb |
| Host | smart-e21e3d87-7bb1-4706-874e-7e8e79392d02 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=162189550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.162189550 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.1112086568 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 61064514 ps |
| CPU time | 9.13 seconds |
| Started | Mar 07 01:38:58 PM PST 24 |
| Finished | Mar 07 01:39:08 PM PST 24 |
| Peak memory | 211348 kb |
| Host | smart-ff7242f6-3aa1-4838-9a0a-ff7621ffbb62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112086568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1112086568 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_same_source.2068081393 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1732783302 ps |
| CPU time | 30.8 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:39:29 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-79dc498f-dd64-4032-a440-77042227ecf3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2068081393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2068081393 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke.1142334475 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 213155380 ps |
| CPU time | 2.92 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:39:01 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-a48abad6-762d-448c-9bbb-bcdfb2389705 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1142334475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1142334475 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.960197528 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4744031549 ps |
| CPU time | 26.44 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:39:25 PM PST 24 |
| Peak memory | 203256 kb |
| Host | smart-8686411a-ed59-4607-a72d-eb670bfe46d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=960197528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.960197528 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.3336212060 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3539953899 ps |
| CPU time | 17.72 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:39:16 PM PST 24 |
| Peak memory | 203092 kb |
| Host | smart-a8e9c1e9-da46-469e-b5c2-2ae821a2082d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3336212060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3336212060 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.3724753654 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 79799217 ps |
| CPU time | 2.27 seconds |
| Started | Mar 07 01:38:57 PM PST 24 |
| Finished | Mar 07 01:39:01 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-69806fb5-63f7-49a2-b63e-d2797263e4fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724753654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.3724753654 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all.1791411139 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 14257846062 ps |
| CPU time | 316.1 seconds |
| Started | Mar 07 01:39:03 PM PST 24 |
| Finished | Mar 07 01:44:19 PM PST 24 |
| Peak memory | 211284 kb |
| Host | smart-a76b86f9-70f9-4798-ad1a-96baa40bfc80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1791411139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1791411139 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2070066411 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 9443664805 ps |
| CPU time | 238.44 seconds |
| Started | Mar 07 01:39:02 PM PST 24 |
| Finished | Mar 07 01:43:00 PM PST 24 |
| Peak memory | 206480 kb |
| Host | smart-64d83e81-be54-4c0e-933a-eb8926d81f4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2070066411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2070066411 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2378363047 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 8208952910 ps |
| CPU time | 392.16 seconds |
| Started | Mar 07 01:39:04 PM PST 24 |
| Finished | Mar 07 01:45:36 PM PST 24 |
| Peak memory | 219588 kb |
| Host | smart-ff1591d3-f0f3-46ea-b49d-a9cc6c59de6c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2378363047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran d_reset.2378363047 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.20975844 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5099112082 ps |
| CPU time | 197.96 seconds |
| Started | Mar 07 01:39:04 PM PST 24 |
| Finished | Mar 07 01:42:22 PM PST 24 |
| Peak memory | 211128 kb |
| Host | smart-07720ece-00f8-4553-9fa1-ef6e3f2c8dce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=20975844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rese t_error.20975844 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.353392320 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 147359557 ps |
| CPU time | 6.91 seconds |
| Started | Mar 07 01:38:56 PM PST 24 |
| Finished | Mar 07 01:39:05 PM PST 24 |
| Peak memory | 204384 kb |
| Host | smart-deead2f1-a45e-41d9-ad2c-5900e4b3ac0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=353392320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.353392320 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3624118464 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2709710427 ps |
| CPU time | 66.67 seconds |
| Started | Mar 07 01:39:04 PM PST 24 |
| Finished | Mar 07 01:40:11 PM PST 24 |
| Peak memory | 206352 kb |
| Host | smart-6d7f8849-0b8c-4cf4-a254-f4c3d7366c05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3624118464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3624118464 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.938764928 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 57925058781 ps |
| CPU time | 578.81 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:48:44 PM PST 24 |
| Peak memory | 206992 kb |
| Host | smart-9e10c8ad-96f8-42fb-9037-0369f4592da1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=938764928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slo w_rsp.938764928 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.184773515 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 548258764 ps |
| CPU time | 13.77 seconds |
| Started | Mar 07 01:39:12 PM PST 24 |
| Finished | Mar 07 01:39:26 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-ae1358be-7916-4595-ae9f-540ce1983798 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=184773515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.184773515 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_error_random.3931354131 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 239265809 ps |
| CPU time | 8.57 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:39:14 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-9f426296-d101-4a73-82b6-4aeda75290f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3931354131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3931354131 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random.3084179502 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 104944020 ps |
| CPU time | 4.97 seconds |
| Started | Mar 07 01:39:03 PM PST 24 |
| Finished | Mar 07 01:39:08 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-7749fa21-ecce-4a75-a58a-e0e41badc8e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3084179502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3084179502 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.274403663 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3892057074 ps |
| CPU time | 23.64 seconds |
| Started | Mar 07 01:39:06 PM PST 24 |
| Finished | Mar 07 01:39:30 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-c9b9a9d6-2c31-4342-b33c-7b6d5b625647 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=274403663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.274403663 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1537522467 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 8298398077 ps |
| CPU time | 67.86 seconds |
| Started | Mar 07 01:39:02 PM PST 24 |
| Finished | Mar 07 01:40:10 PM PST 24 |
| Peak memory | 204340 kb |
| Host | smart-a36341b0-b8ff-45d3-b982-29a7a0023216 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1537522467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1537522467 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.308425494 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 848916509 ps |
| CPU time | 23.01 seconds |
| Started | Mar 07 01:39:04 PM PST 24 |
| Finished | Mar 07 01:39:27 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-df3173f8-1785-408a-8941-c9370f208c6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308425494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.308425494 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_same_source.1511799735 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 419420317 ps |
| CPU time | 17.21 seconds |
| Started | Mar 07 01:39:12 PM PST 24 |
| Finished | Mar 07 01:39:29 PM PST 24 |
| Peak memory | 203560 kb |
| Host | smart-d7936eca-22c4-4bcb-891d-8e8370108a76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1511799735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1511799735 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke.1381286408 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 132494006 ps |
| CPU time | 3.68 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:39:09 PM PST 24 |
| Peak memory | 203168 kb |
| Host | smart-10f5faba-bdeb-4e07-a882-e7f757e3a657 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1381286408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1381286408 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.80684040 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 5977034844 ps |
| CPU time | 29.74 seconds |
| Started | Mar 07 01:39:03 PM PST 24 |
| Finished | Mar 07 01:39:33 PM PST 24 |
| Peak memory | 203288 kb |
| Host | smart-59c0c285-3cd1-4b30-b020-e5d92e0fa8e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=80684040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.80684040 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3913697642 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 6700100551 ps |
| CPU time | 31.5 seconds |
| Started | Mar 07 01:39:02 PM PST 24 |
| Finished | Mar 07 01:39:34 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-6f94f45d-992c-4773-a224-e23530e8851e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3913697642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3913697642 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1919492045 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 42249992 ps |
| CPU time | 2.35 seconds |
| Started | Mar 07 01:39:12 PM PST 24 |
| Finished | Mar 07 01:39:14 PM PST 24 |
| Peak memory | 203224 kb |
| Host | smart-bf91a10f-feea-4b6f-9326-892ff9d7ee0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919492045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1919492045 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1880939384 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 5431457382 ps |
| CPU time | 81.72 seconds |
| Started | Mar 07 01:39:03 PM PST 24 |
| Finished | Mar 07 01:40:25 PM PST 24 |
| Peak memory | 206240 kb |
| Host | smart-5b854017-ba37-4fcb-b9e8-39b0590d7cbc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1880939384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1880939384 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.3984269958 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 302318714 ps |
| CPU time | 24.83 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:39:30 PM PST 24 |
| Peak memory | 203436 kb |
| Host | smart-cbe0146f-5a3f-4ba9-a73b-8d2e8129540a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3984269958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3984269958 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2172635726 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 10120756650 ps |
| CPU time | 496.03 seconds |
| Started | Mar 07 01:39:04 PM PST 24 |
| Finished | Mar 07 01:47:20 PM PST 24 |
| Peak memory | 226132 kb |
| Host | smart-855d176c-19cd-45df-aaf1-90b598e8d17a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2172635726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re set_error.2172635726 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.1315941939 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 113696663 ps |
| CPU time | 13.98 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:39:19 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-5d4c2d4a-2472-447e-9251-bf01da370835 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1315941939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1315941939 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.3459568943 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3345667137 ps |
| CPU time | 52.15 seconds |
| Started | Mar 07 01:39:07 PM PST 24 |
| Finished | Mar 07 01:39:59 PM PST 24 |
| Peak memory | 205984 kb |
| Host | smart-175f3a38-37d1-4a40-89c4-58f06bb30175 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3459568943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3459568943 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.4222937369 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 15314092726 ps |
| CPU time | 38.35 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:39:44 PM PST 24 |
| Peak memory | 203196 kb |
| Host | smart-09a48d6b-fb72-46d2-8f9c-10924d14223f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4222937369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl ow_rsp.4222937369 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.408379588 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 591047779 ps |
| CPU time | 16.71 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:39:22 PM PST 24 |
| Peak memory | 203304 kb |
| Host | smart-cc3e1838-7522-45e7-95cf-0db8962947ac |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=408379588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.408379588 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_error_random.273901513 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1001181684 ps |
| CPU time | 12.38 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:39:17 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-063b80c8-5757-45a6-8d6f-4182d23c8e29 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=273901513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.273901513 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random.2280672020 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1211197181 ps |
| CPU time | 43.27 seconds |
| Started | Mar 07 01:39:11 PM PST 24 |
| Finished | Mar 07 01:39:55 PM PST 24 |
| Peak memory | 204504 kb |
| Host | smart-ed4c511c-a2fa-484e-aab8-8950dbf0a48d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2280672020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.2280672020 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.897977245 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 12828259591 ps |
| CPU time | 64.03 seconds |
| Started | Mar 07 01:39:04 PM PST 24 |
| Finished | Mar 07 01:40:08 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-e2685d05-cab6-4a87-a439-e422f1a154ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=897977245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.897977245 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3096295129 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 56282732224 ps |
| CPU time | 239.2 seconds |
| Started | Mar 07 01:39:07 PM PST 24 |
| Finished | Mar 07 01:43:07 PM PST 24 |
| Peak memory | 204624 kb |
| Host | smart-90b8421c-d604-47cd-a1da-7fd33f370d62 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3096295129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3096295129 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.65183892 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 102998882 ps |
| CPU time | 9.76 seconds |
| Started | Mar 07 01:39:03 PM PST 24 |
| Finished | Mar 07 01:39:13 PM PST 24 |
| Peak memory | 204156 kb |
| Host | smart-761800d2-0aa2-4ba6-9eb9-6948f3b13c78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65183892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.65183892 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_same_source.1806441480 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 335174803 ps |
| CPU time | 7.22 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:39:13 PM PST 24 |
| Peak memory | 203456 kb |
| Host | smart-a70e90fa-d4ea-4c66-bb7d-1ce4d424b314 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1806441480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1806441480 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke.2521249177 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 69671533 ps |
| CPU time | 2.48 seconds |
| Started | Mar 07 01:39:06 PM PST 24 |
| Finished | Mar 07 01:39:09 PM PST 24 |
| Peak memory | 203184 kb |
| Host | smart-a5fef324-17f9-4f79-a364-33f076173a18 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2521249177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2521249177 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2225537544 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 5569732761 ps |
| CPU time | 28.62 seconds |
| Started | Mar 07 01:39:05 PM PST 24 |
| Finished | Mar 07 01:39:34 PM PST 24 |
| Peak memory | 203200 kb |
| Host | smart-19004b4d-fb80-4e59-b306-5c56169cf33f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225537544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2225537544 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3055370363 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 3459719051 ps |
| CPU time | 23.87 seconds |
| Started | Mar 07 01:39:12 PM PST 24 |
| Finished | Mar 07 01:39:36 PM PST 24 |
| Peak memory | 203200 kb |
| Host | smart-a4a400cb-2030-4afa-8066-168f2a1ec54d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3055370363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3055370363 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.244057624 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 29470560 ps |
| CPU time | 2.1 seconds |
| Started | Mar 07 01:39:07 PM PST 24 |
| Finished | Mar 07 01:39:10 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-c0b8b681-c42e-463d-a858-3d69f0e894d2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244057624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.244057624 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1072120154 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1771325519 ps |
| CPU time | 132.65 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:41:32 PM PST 24 |
| Peak memory | 207824 kb |
| Host | smart-29b475d6-f01a-4eee-930c-4d1293aad05b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1072120154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1072120154 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4229061390 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 853003978 ps |
| CPU time | 266.23 seconds |
| Started | Mar 07 01:39:19 PM PST 24 |
| Finished | Mar 07 01:43:46 PM PST 24 |
| Peak memory | 219524 kb |
| Host | smart-f6dc716c-6bbf-4054-a890-fa2eefb6ec23 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4229061390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_re set_error.4229061390 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.1064456582 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 453396342 ps |
| CPU time | 10.41 seconds |
| Started | Mar 07 01:39:03 PM PST 24 |
| Finished | Mar 07 01:39:14 PM PST 24 |
| Peak memory | 204488 kb |
| Host | smart-806cee7b-f69e-461d-aa8e-a4464d35a168 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1064456582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1064456582 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.1996835314 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 564469592 ps |
| CPU time | 51.34 seconds |
| Started | Mar 07 01:39:16 PM PST 24 |
| Finished | Mar 07 01:40:10 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-b442fc12-6055-491c-a9d6-7df0bf0bd5d7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1996835314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1996835314 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1306866262 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 49999377133 ps |
| CPU time | 476.7 seconds |
| Started | Mar 07 01:39:28 PM PST 24 |
| Finished | Mar 07 01:47:26 PM PST 24 |
| Peak memory | 205640 kb |
| Host | smart-82dc20ec-63ac-4e1d-9c02-a9f0dca7790a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1306866262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl ow_rsp.1306866262 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.2068278351 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 71352277 ps |
| CPU time | 7.43 seconds |
| Started | Mar 07 01:39:19 PM PST 24 |
| Finished | Mar 07 01:39:27 PM PST 24 |
| Peak memory | 203168 kb |
| Host | smart-5fb533e3-8a5a-4556-97d1-fad6e221a4e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2068278351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.2068278351 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_error_random.84821342 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 130426822 ps |
| CPU time | 4.5 seconds |
| Started | Mar 07 01:39:19 PM PST 24 |
| Finished | Mar 07 01:39:25 PM PST 24 |
| Peak memory | 203076 kb |
| Host | smart-4c8e0543-87c5-4e31-a577-5d6914369636 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=84821342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.84821342 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random.2487795133 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 276785704 ps |
| CPU time | 27.81 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:39:47 PM PST 24 |
| Peak memory | 204156 kb |
| Host | smart-fedfd7d4-d05c-4155-82df-84fe8167c5c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2487795133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2487795133 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.706611879 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 9143235449 ps |
| CPU time | 29.09 seconds |
| Started | Mar 07 01:39:16 PM PST 24 |
| Finished | Mar 07 01:39:48 PM PST 24 |
| Peak memory | 203264 kb |
| Host | smart-d3e517b2-8d47-4c61-a9cb-654320f6a0b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=706611879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.706611879 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.4014425634 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 22772363122 ps |
| CPU time | 191.46 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:42:31 PM PST 24 |
| Peak memory | 211376 kb |
| Host | smart-472e4b7c-b654-4fb1-aca4-2ecb3547f24b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4014425634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.4014425634 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.37682726 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 192145723 ps |
| CPU time | 5.25 seconds |
| Started | Mar 07 01:39:19 PM PST 24 |
| Finished | Mar 07 01:39:25 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-3b61619b-e440-4818-9a77-4bc4673511c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37682726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.37682726 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_same_source.3393772884 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 604039926 ps |
| CPU time | 11.09 seconds |
| Started | Mar 07 01:39:16 PM PST 24 |
| Finished | Mar 07 01:39:29 PM PST 24 |
| Peak memory | 203492 kb |
| Host | smart-deb08b67-051a-4125-9673-f3a1c2226c0d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3393772884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3393772884 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke.1510519876 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 28028526 ps |
| CPU time | 1.95 seconds |
| Started | Mar 07 01:39:20 PM PST 24 |
| Finished | Mar 07 01:39:22 PM PST 24 |
| Peak memory | 203164 kb |
| Host | smart-fbdf676c-1b78-430e-8234-e9cf6f7b2fa1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1510519876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1510519876 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2211769762 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 6997155350 ps |
| CPU time | 24.63 seconds |
| Started | Mar 07 01:39:17 PM PST 24 |
| Finished | Mar 07 01:39:44 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-e6b8d2cc-2d33-4a66-9992-ea088257cba4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211769762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2211769762 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1776528806 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 4532698303 ps |
| CPU time | 35.66 seconds |
| Started | Mar 07 01:39:17 PM PST 24 |
| Finished | Mar 07 01:39:55 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-458df882-3a8e-4b15-9944-847c53d911ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1776528806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1776528806 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1456394570 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 24964921 ps |
| CPU time | 2.28 seconds |
| Started | Mar 07 01:39:16 PM PST 24 |
| Finished | Mar 07 01:39:21 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-f9f4c246-a10a-479b-88ed-97a93710d736 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456394570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1456394570 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all.25977546 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3075157431 ps |
| CPU time | 92.96 seconds |
| Started | Mar 07 01:39:20 PM PST 24 |
| Finished | Mar 07 01:40:54 PM PST 24 |
| Peak memory | 205488 kb |
| Host | smart-a8bf41c8-0a3a-4d74-8a89-a8fa17d2b8e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=25977546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.25977546 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.335945081 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 13747708911 ps |
| CPU time | 180.38 seconds |
| Started | Mar 07 01:39:16 PM PST 24 |
| Finished | Mar 07 01:42:19 PM PST 24 |
| Peak memory | 206412 kb |
| Host | smart-3bec3431-93bd-45c2-8217-0c7badf2af9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=335945081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.335945081 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.3441113412 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1063507161 ps |
| CPU time | 337.22 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:44:56 PM PST 24 |
| Peak memory | 209516 kb |
| Host | smart-3ca3dfe9-fc01-4ae3-80d8-b17c53350024 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3441113412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran d_reset.3441113412 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.2066510214 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 20259718 ps |
| CPU time | 2.79 seconds |
| Started | Mar 07 01:39:16 PM PST 24 |
| Finished | Mar 07 01:39:22 PM PST 24 |
| Peak memory | 204060 kb |
| Host | smart-bced6a85-41f5-4966-8bf5-38a458c35a14 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2066510214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2066510214 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.624031545 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 214164286 ps |
| CPU time | 20.75 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:39:40 PM PST 24 |
| Peak memory | 204924 kb |
| Host | smart-7ec26b56-00b3-41f2-ae95-ad5ea7ac1d80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=624031545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.624031545 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.3930842687 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 7186357118 ps |
| CPU time | 37.08 seconds |
| Started | Mar 07 01:39:20 PM PST 24 |
| Finished | Mar 07 01:39:57 PM PST 24 |
| Peak memory | 203816 kb |
| Host | smart-af264603-599d-4ce5-9171-a31ca4e283f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3930842687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl ow_rsp.3930842687 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2267285286 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 67469232 ps |
| CPU time | 2.48 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:39:22 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-3b791a7b-ce61-4a63-8933-773bcfe96fad |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2267285286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2267285286 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_error_random.3879539447 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 345079905 ps |
| CPU time | 6.28 seconds |
| Started | Mar 07 01:39:17 PM PST 24 |
| Finished | Mar 07 01:39:26 PM PST 24 |
| Peak memory | 202952 kb |
| Host | smart-124aa06b-30f0-4240-a22e-f94f59d1b359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3879539447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3879539447 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random.2814594199 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 154449246 ps |
| CPU time | 7.42 seconds |
| Started | Mar 07 01:39:17 PM PST 24 |
| Finished | Mar 07 01:39:27 PM PST 24 |
| Peak memory | 204264 kb |
| Host | smart-d5ea7cab-6018-485a-baa4-305dbc8812f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2814594199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.2814594199 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.2356110362 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 48410452942 ps |
| CPU time | 265.5 seconds |
| Started | Mar 07 01:39:22 PM PST 24 |
| Finished | Mar 07 01:43:47 PM PST 24 |
| Peak memory | 211392 kb |
| Host | smart-279c8d86-03f2-41e1-b0af-cccc23e3edb3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356110362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2356110362 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.1688872843 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 15835103931 ps |
| CPU time | 49.67 seconds |
| Started | Mar 07 01:39:16 PM PST 24 |
| Finished | Mar 07 01:40:08 PM PST 24 |
| Peak memory | 204264 kb |
| Host | smart-7d7c31ab-eab4-48df-8200-afea0582994a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1688872843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.1688872843 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.664083173 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 196786116 ps |
| CPU time | 25.66 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:39:45 PM PST 24 |
| Peak memory | 204388 kb |
| Host | smart-b0295c40-d3af-44f4-aef4-53fe3c0c0f2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664083173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.664083173 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_same_source.1419408406 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1917711100 ps |
| CPU time | 25.54 seconds |
| Started | Mar 07 01:39:19 PM PST 24 |
| Finished | Mar 07 01:39:46 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-833bbeff-be66-4c10-ad73-24438cccf8b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1419408406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1419408406 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke.1465399730 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 432200681 ps |
| CPU time | 3.44 seconds |
| Started | Mar 07 01:39:16 PM PST 24 |
| Finished | Mar 07 01:39:22 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-27b155a9-cf0e-41dc-af36-94c8e490f652 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1465399730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1465399730 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.714744805 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 4196112853 ps |
| CPU time | 23.19 seconds |
| Started | Mar 07 01:39:19 PM PST 24 |
| Finished | Mar 07 01:39:43 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-c963f441-479e-4256-b3d9-90effd7d3403 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=714744805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.714744805 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.646636097 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 13937332252 ps |
| CPU time | 40.26 seconds |
| Started | Mar 07 01:39:17 PM PST 24 |
| Finished | Mar 07 01:39:59 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-71dfcf19-e1f9-4f10-8de7-8899d2b10e56 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=646636097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.646636097 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3250613658 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 32767492 ps |
| CPU time | 1.86 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:39:21 PM PST 24 |
| Peak memory | 203024 kb |
| Host | smart-6819e4d7-3a38-4188-b1ab-a083426ce752 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250613658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3250613658 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all.819168821 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2641935011 ps |
| CPU time | 49.35 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:40:19 PM PST 24 |
| Peak memory | 205828 kb |
| Host | smart-dd6982c8-bae7-4b90-bc69-f10e4272048d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=819168821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.819168821 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2165630228 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 8334013824 ps |
| CPU time | 197.52 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:42:37 PM PST 24 |
| Peak memory | 211360 kb |
| Host | smart-32b46c9f-c90d-4d1a-8a46-fc138015456c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2165630228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2165630228 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3511403803 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 197733475 ps |
| CPU time | 83 seconds |
| Started | Mar 07 01:39:17 PM PST 24 |
| Finished | Mar 07 01:40:42 PM PST 24 |
| Peak memory | 207616 kb |
| Host | smart-09f634e6-ff93-43b1-910a-ec0772abb903 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3511403803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran d_reset.3511403803 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2264821810 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2539548431 ps |
| CPU time | 75.82 seconds |
| Started | Mar 07 01:39:16 PM PST 24 |
| Finished | Mar 07 01:40:34 PM PST 24 |
| Peak memory | 207952 kb |
| Host | smart-e28cc7be-b7fd-4ae8-98fd-2e025c4e851a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2264821810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re set_error.2264821810 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.373029421 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 877381948 ps |
| CPU time | 22.23 seconds |
| Started | Mar 07 01:39:16 PM PST 24 |
| Finished | Mar 07 01:39:41 PM PST 24 |
| Peak memory | 204492 kb |
| Host | smart-03522f3c-609e-4dcc-932f-e3e282755b10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=373029421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.373029421 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2056349926 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4208834956 ps |
| CPU time | 33.29 seconds |
| Started | Mar 07 01:39:17 PM PST 24 |
| Finished | Mar 07 01:39:52 PM PST 24 |
| Peak memory | 203876 kb |
| Host | smart-1440ac73-2209-4087-8cc4-802a38e8f6c4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2056349926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2056349926 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.2115639594 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 34584395066 ps |
| CPU time | 212.35 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:43:02 PM PST 24 |
| Peak memory | 205436 kb |
| Host | smart-d0abb3c4-464c-4814-9eea-b8c3bf6410e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2115639594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl ow_rsp.2115639594 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1016434320 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 67301905 ps |
| CPU time | 7.25 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:39:37 PM PST 24 |
| Peak memory | 203168 kb |
| Host | smart-46f59996-dc84-4e44-952f-d1976d251105 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1016434320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1016434320 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_error_random.818053483 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 787462861 ps |
| CPU time | 16.31 seconds |
| Started | Mar 07 01:39:20 PM PST 24 |
| Finished | Mar 07 01:39:36 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-6577a496-f929-4b31-ad04-8a55cbf69cc6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=818053483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.818053483 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random.1446614873 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1179885992 ps |
| CPU time | 30.82 seconds |
| Started | Mar 07 01:39:27 PM PST 24 |
| Finished | Mar 07 01:39:58 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-ed88954a-4e3e-4490-9393-66e45e7990a9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1446614873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.1446614873 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.3013565052 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 28126964205 ps |
| CPU time | 69.71 seconds |
| Started | Mar 07 01:39:20 PM PST 24 |
| Finished | Mar 07 01:40:30 PM PST 24 |
| Peak memory | 204340 kb |
| Host | smart-704fa41c-9cda-47e1-890a-d1070737b7de |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013565052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3013565052 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1422019315 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 16936550823 ps |
| CPU time | 118.9 seconds |
| Started | Mar 07 01:39:28 PM PST 24 |
| Finished | Mar 07 01:41:27 PM PST 24 |
| Peak memory | 204424 kb |
| Host | smart-4f22fc1a-7870-4934-a509-6f340298b791 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1422019315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1422019315 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.727700069 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 28953679 ps |
| CPU time | 3.8 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:39:23 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-a40edd03-a68c-4948-a0b3-39b72c5b6969 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727700069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.727700069 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_same_source.735634382 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 485135045 ps |
| CPU time | 5.65 seconds |
| Started | Mar 07 01:39:28 PM PST 24 |
| Finished | Mar 07 01:39:35 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-ccea946c-de92-44c3-9464-6a8532f65b85 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=735634382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.735634382 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke.1700258909 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 56788436 ps |
| CPU time | 2.35 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:39:21 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-beefa3a7-bc06-4376-92f7-56053d94758d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1700258909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1700258909 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1117114680 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 7035088453 ps |
| CPU time | 30.84 seconds |
| Started | Mar 07 01:39:17 PM PST 24 |
| Finished | Mar 07 01:39:50 PM PST 24 |
| Peak memory | 203252 kb |
| Host | smart-c8ef4732-2788-43c8-81f2-eefad8c2ca76 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117114680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1117114680 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3658279996 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 17472010849 ps |
| CPU time | 44.92 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:40:04 PM PST 24 |
| Peak memory | 203236 kb |
| Host | smart-4f0a8c3f-d4db-4eb6-b751-e15cb6365951 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3658279996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3658279996 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1408856369 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 31591856 ps |
| CPU time | 2.31 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:39:32 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-2e3b350f-d67b-4ac0-a635-45310a126438 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408856369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1408856369 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all.2139675141 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 905062574 ps |
| CPU time | 103.56 seconds |
| Started | Mar 07 01:39:28 PM PST 24 |
| Finished | Mar 07 01:41:13 PM PST 24 |
| Peak memory | 205648 kb |
| Host | smart-ef9b1d75-5453-490d-b25f-e64c2895cfce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2139675141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2139675141 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2617674257 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 8587034704 ps |
| CPU time | 141.32 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:41:41 PM PST 24 |
| Peak memory | 205084 kb |
| Host | smart-24e066f1-5d5c-4d4e-ae30-2daf2dcfe368 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2617674257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2617674257 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.611368785 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1859376227 ps |
| CPU time | 377.99 seconds |
| Started | Mar 07 01:39:19 PM PST 24 |
| Finished | Mar 07 01:45:38 PM PST 24 |
| Peak memory | 209424 kb |
| Host | smart-4afe7515-ec6d-4e46-9f09-6c7320217c93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=611368785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand _reset.611368785 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3928795558 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 965206338 ps |
| CPU time | 266.15 seconds |
| Started | Mar 07 01:39:25 PM PST 24 |
| Finished | Mar 07 01:43:52 PM PST 24 |
| Peak memory | 219604 kb |
| Host | smart-c73cffcd-9d6a-4fd7-b3e0-21f3d2106760 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3928795558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re set_error.3928795558 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.1071540148 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 822460724 ps |
| CPU time | 33.26 seconds |
| Started | Mar 07 01:39:17 PM PST 24 |
| Finished | Mar 07 01:39:52 PM PST 24 |
| Peak memory | 205196 kb |
| Host | smart-40d764b5-d207-41de-b2d8-aa12e0ae479d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1071540148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1071540148 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.2970250563 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 609302076 ps |
| CPU time | 24.9 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:39:55 PM PST 24 |
| Peak memory | 204264 kb |
| Host | smart-f8f79f30-fab2-4d9d-9dc4-6d5475fd63a6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2970250563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2970250563 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1056804959 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 56074681872 ps |
| CPU time | 285.19 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:44:15 PM PST 24 |
| Peak memory | 205640 kb |
| Host | smart-aa71eb3e-c00c-4821-b89e-11150b755507 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1056804959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl ow_rsp.1056804959 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.764764321 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1367716200 ps |
| CPU time | 25.75 seconds |
| Started | Mar 07 01:39:28 PM PST 24 |
| Finished | Mar 07 01:39:55 PM PST 24 |
| Peak memory | 203092 kb |
| Host | smart-eaa9a60c-4b8a-4d29-8d34-3c0c1f26fc2c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=764764321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.764764321 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_error_random.1311137392 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 189218813 ps |
| CPU time | 17.18 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:39:47 PM PST 24 |
| Peak memory | 203028 kb |
| Host | smart-e2436d1e-305e-4566-8f58-7dd183e9b886 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1311137392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1311137392 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random.3126024585 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 85641282 ps |
| CPU time | 11.78 seconds |
| Started | Mar 07 01:39:19 PM PST 24 |
| Finished | Mar 07 01:39:31 PM PST 24 |
| Peak memory | 203932 kb |
| Host | smart-edf43415-a6db-45de-b2c2-12e18a516fc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3126024585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3126024585 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.1913177540 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 36575010520 ps |
| CPU time | 177.23 seconds |
| Started | Mar 07 01:39:28 PM PST 24 |
| Finished | Mar 07 01:42:27 PM PST 24 |
| Peak memory | 204332 kb |
| Host | smart-cdaf76ff-255c-43fd-8e9f-d5203cbd30f7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913177540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1913177540 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.688608083 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 15148536632 ps |
| CPU time | 139.95 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:41:49 PM PST 24 |
| Peak memory | 204220 kb |
| Host | smart-6c1772d8-216f-4309-ae57-afa6509bfd4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=688608083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.688608083 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.540481400 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 232622246 ps |
| CPU time | 13.7 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:39:43 PM PST 24 |
| Peak memory | 211352 kb |
| Host | smart-a2d608aa-0564-4103-adc4-5014ee8e576f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540481400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.540481400 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_same_source.2381882880 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 29181403 ps |
| CPU time | 2.46 seconds |
| Started | Mar 07 01:39:28 PM PST 24 |
| Finished | Mar 07 01:39:32 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-4c525cec-1634-480d-a43d-9c3ab06fcc07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2381882880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2381882880 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke.900146155 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 26570420 ps |
| CPU time | 2.51 seconds |
| Started | Mar 07 01:39:20 PM PST 24 |
| Finished | Mar 07 01:39:23 PM PST 24 |
| Peak memory | 203028 kb |
| Host | smart-a2003eab-c2d0-43ab-9230-2f2b01d230d1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=900146155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.900146155 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.6830243 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 7375071138 ps |
| CPU time | 24.21 seconds |
| Started | Mar 07 01:39:20 PM PST 24 |
| Finished | Mar 07 01:39:44 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-7df0d99a-9da1-49b4-ad45-460ac01f02d0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=6830243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.6830243 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.841590014 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 7418824729 ps |
| CPU time | 33.62 seconds |
| Started | Mar 07 01:39:25 PM PST 24 |
| Finished | Mar 07 01:39:59 PM PST 24 |
| Peak memory | 203244 kb |
| Host | smart-9714dba3-5694-42cf-bf8a-eea25f8a8605 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=841590014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.841590014 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1169937332 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 44344104 ps |
| CPU time | 2.88 seconds |
| Started | Mar 07 01:39:18 PM PST 24 |
| Finished | Mar 07 01:39:22 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-dbe56922-8eae-4376-af04-c3ca46fcfc2b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169937332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1169937332 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all.1608915126 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 804012749 ps |
| CPU time | 95.76 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:41:05 PM PST 24 |
| Peak memory | 207324 kb |
| Host | smart-d8907a84-4262-49bd-8314-2c67742b28b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1608915126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1608915126 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.901120239 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 110077624 ps |
| CPU time | 15.61 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:39:45 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-cf983d21-c0fa-4506-873b-d9cbb0d8d790 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=901120239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.901120239 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2304317843 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2994980144 ps |
| CPU time | 374.34 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:45:45 PM PST 24 |
| Peak memory | 209828 kb |
| Host | smart-2f639baa-5bdb-48ce-b54b-35fd88415a1b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2304317843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran d_reset.2304317843 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.276254358 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 7079640 ps |
| CPU time | 5.86 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:39:36 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-f5526733-f1c4-4544-bfa1-c36263258baa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=276254358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_res et_error.276254358 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.43772863 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 304079118 ps |
| CPU time | 14.51 seconds |
| Started | Mar 07 01:39:28 PM PST 24 |
| Finished | Mar 07 01:39:44 PM PST 24 |
| Peak memory | 211300 kb |
| Host | smart-869cd583-c8ee-4d59-a153-6308b45b6a1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=43772863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.43772863 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2003506450 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 104168318 ps |
| CPU time | 5.49 seconds |
| Started | Mar 07 01:39:28 PM PST 24 |
| Finished | Mar 07 01:39:35 PM PST 24 |
| Peak memory | 203196 kb |
| Host | smart-12ad687b-3b2a-48dd-b374-f4314503bcf5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2003506450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2003506450 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.2280018966 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 39300912457 ps |
| CPU time | 196.63 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:42:46 PM PST 24 |
| Peak memory | 206024 kb |
| Host | smart-e2eb0836-137d-4329-94d3-a247ef798fff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2280018966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl ow_rsp.2280018966 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_error_random.3998571807 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 277449353 ps |
| CPU time | 18.36 seconds |
| Started | Mar 07 01:39:31 PM PST 24 |
| Finished | Mar 07 01:39:50 PM PST 24 |
| Peak memory | 203268 kb |
| Host | smart-65391ebd-2dd9-4e91-b275-dcc7c8c6bb41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3998571807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3998571807 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random.2290256524 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 667968047 ps |
| CPU time | 21.17 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:39:51 PM PST 24 |
| Peak memory | 204240 kb |
| Host | smart-0968af0e-3e90-4b5e-8693-b86fde556f89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2290256524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.2290256524 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.1587391839 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 19426886059 ps |
| CPU time | 37.31 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:40:08 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-c1d26e8b-bd64-499c-855d-9fecc52fab20 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587391839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1587391839 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.905953739 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 112831624743 ps |
| CPU time | 241.8 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:43:32 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-315007fd-8f07-457f-abb8-7e3f99ae9f0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=905953739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.905953739 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.1744303460 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 66572950 ps |
| CPU time | 10.22 seconds |
| Started | Mar 07 01:39:32 PM PST 24 |
| Finished | Mar 07 01:39:43 PM PST 24 |
| Peak memory | 204116 kb |
| Host | smart-576a79cd-ffc2-4854-8dda-19ae79132150 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744303460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.1744303460 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_same_source.2392738344 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 411158958 ps |
| CPU time | 17.11 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:39:47 PM PST 24 |
| Peak memory | 203432 kb |
| Host | smart-4e1548d2-4e2b-4efe-9d74-4f76ffc1c57f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2392738344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2392738344 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke.3196805884 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 133502705 ps |
| CPU time | 3.34 seconds |
| Started | Mar 07 01:39:31 PM PST 24 |
| Finished | Mar 07 01:39:34 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-e522089c-2321-4279-a068-9a008ae4de53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3196805884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3196805884 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2642708849 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 9561068004 ps |
| CPU time | 32.22 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:40:02 PM PST 24 |
| Peak memory | 203192 kb |
| Host | smart-f8a72ed6-ef7e-4b68-a200-8d60cbe33d59 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642708849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2642708849 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1483819430 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2813868301 ps |
| CPU time | 25.86 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:39:56 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-118f2015-3089-45b6-baf6-0798a11b741b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1483819430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1483819430 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.777722990 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 72739164 ps |
| CPU time | 2.69 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:39:32 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-e2609e5f-8d73-481d-8337-334eaec56ecf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777722990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.777722990 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all.3709547068 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 988271237 ps |
| CPU time | 84.06 seconds |
| Started | Mar 07 01:39:35 PM PST 24 |
| Finished | Mar 07 01:41:00 PM PST 24 |
| Peak memory | 205504 kb |
| Host | smart-e077cbe0-667a-46ae-82d5-3c8a0565689e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3709547068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3709547068 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2570562114 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 31564723647 ps |
| CPU time | 260.66 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:43:50 PM PST 24 |
| Peak memory | 206804 kb |
| Host | smart-c8f64c6d-1845-4f7b-9b5b-e2ab47023008 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2570562114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2570562114 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.538559859 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3326134353 ps |
| CPU time | 533.42 seconds |
| Started | Mar 07 01:39:32 PM PST 24 |
| Finished | Mar 07 01:48:25 PM PST 24 |
| Peak memory | 211388 kb |
| Host | smart-bedfdf65-85c2-4ebd-9771-1a6ce0b6ea10 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=538559859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand _reset.538559859 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.1442064132 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 79154049 ps |
| CPU time | 11.31 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:39:42 PM PST 24 |
| Peak memory | 203240 kb |
| Host | smart-7683f691-9276-4ac6-bce5-3562c655cf54 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1442064132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re set_error.1442064132 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1805441655 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 62883705 ps |
| CPU time | 7.25 seconds |
| Started | Mar 07 01:39:29 PM PST 24 |
| Finished | Mar 07 01:39:37 PM PST 24 |
| Peak memory | 204528 kb |
| Host | smart-b548baa0-b069-467c-8781-422ba7ac9ad6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1805441655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1805441655 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2491619352 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 470059123 ps |
| CPU time | 12.52 seconds |
| Started | Mar 07 01:39:45 PM PST 24 |
| Finished | Mar 07 01:39:59 PM PST 24 |
| Peak memory | 203976 kb |
| Host | smart-5270a044-c763-45bd-b539-69f22a486bc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2491619352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2491619352 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.1392649980 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 146972346349 ps |
| CPU time | 651.3 seconds |
| Started | Mar 07 01:39:45 PM PST 24 |
| Finished | Mar 07 01:50:38 PM PST 24 |
| Peak memory | 205768 kb |
| Host | smart-e40fdf4b-1351-43a3-9ba1-937b5cebe10a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1392649980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_sl ow_rsp.1392649980 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3468170496 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1257144029 ps |
| CPU time | 17.59 seconds |
| Started | Mar 07 01:39:32 PM PST 24 |
| Finished | Mar 07 01:39:50 PM PST 24 |
| Peak memory | 203244 kb |
| Host | smart-71418044-75d0-410d-8220-02eab04a6ac4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3468170496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3468170496 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_error_random.2675649472 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1159313239 ps |
| CPU time | 32.58 seconds |
| Started | Mar 07 01:39:45 PM PST 24 |
| Finished | Mar 07 01:40:19 PM PST 24 |
| Peak memory | 203224 kb |
| Host | smart-79b58c8f-48c6-4242-85e3-96f88c605362 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2675649472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2675649472 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random.1403153786 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 254255754 ps |
| CPU time | 8.71 seconds |
| Started | Mar 07 01:39:45 PM PST 24 |
| Finished | Mar 07 01:39:56 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-ecd65c42-633b-4764-9d45-557f883f5b2d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1403153786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.1403153786 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.1077754639 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3012968387 ps |
| CPU time | 12.06 seconds |
| Started | Mar 07 01:39:34 PM PST 24 |
| Finished | Mar 07 01:39:47 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-d1758c36-5859-4b74-8bb3-03a25f610f24 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077754639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1077754639 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2992160556 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 33439959722 ps |
| CPU time | 245.89 seconds |
| Started | Mar 07 01:39:31 PM PST 24 |
| Finished | Mar 07 01:43:38 PM PST 24 |
| Peak memory | 211376 kb |
| Host | smart-71e18217-2f89-4284-ab93-cd4db26c140c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2992160556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2992160556 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.25209388 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 134154685 ps |
| CPU time | 14.64 seconds |
| Started | Mar 07 01:39:33 PM PST 24 |
| Finished | Mar 07 01:39:47 PM PST 24 |
| Peak memory | 211244 kb |
| Host | smart-43fd95d4-70b8-401c-9c7b-c5dfa7992cfe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25209388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.25209388 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_same_source.4124478317 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 262999175 ps |
| CPU time | 12.53 seconds |
| Started | Mar 07 01:39:33 PM PST 24 |
| Finished | Mar 07 01:39:46 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-77ebce41-2f81-441f-bda6-070353905754 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4124478317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.4124478317 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke.2684565363 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 375403651 ps |
| CPU time | 3.82 seconds |
| Started | Mar 07 01:39:33 PM PST 24 |
| Finished | Mar 07 01:39:37 PM PST 24 |
| Peak memory | 203096 kb |
| Host | smart-617913c9-5491-4823-ad0e-019ccbd32f89 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2684565363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2684565363 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.208828746 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 12844549023 ps |
| CPU time | 28.65 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:39:59 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-5591edf2-da9a-4652-a494-26ba917f3ad5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=208828746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.208828746 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.401894627 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4223163208 ps |
| CPU time | 33.41 seconds |
| Started | Mar 07 01:39:30 PM PST 24 |
| Finished | Mar 07 01:40:04 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-d1edb717-3182-4a7a-b3cb-e986c5e40d60 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=401894627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.401894627 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2439748544 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 26499225 ps |
| CPU time | 2.15 seconds |
| Started | Mar 07 01:39:31 PM PST 24 |
| Finished | Mar 07 01:39:34 PM PST 24 |
| Peak memory | 203180 kb |
| Host | smart-5e3c39cd-c3c7-49a8-9c7b-1ec6523b6660 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439748544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2439748544 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all.1430908056 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 638726474 ps |
| CPU time | 29.39 seconds |
| Started | Mar 07 01:39:34 PM PST 24 |
| Finished | Mar 07 01:40:04 PM PST 24 |
| Peak memory | 204816 kb |
| Host | smart-6ae67f05-263c-49f1-b9ba-99f2586e617c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1430908056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1430908056 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.410842993 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 4259614255 ps |
| CPU time | 131.38 seconds |
| Started | Mar 07 01:39:34 PM PST 24 |
| Finished | Mar 07 01:41:46 PM PST 24 |
| Peak memory | 211388 kb |
| Host | smart-9dc2e799-d70a-4d0f-9fd5-79d96ae3e2bb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=410842993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.410842993 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.391442024 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 841866246 ps |
| CPU time | 90.96 seconds |
| Started | Mar 07 01:39:47 PM PST 24 |
| Finished | Mar 07 01:41:18 PM PST 24 |
| Peak memory | 206572 kb |
| Host | smart-2b142eed-20db-4a40-88db-4d13b35d56fc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=391442024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand _reset.391442024 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.27338964 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 472778837 ps |
| CPU time | 125.24 seconds |
| Started | Mar 07 01:39:33 PM PST 24 |
| Finished | Mar 07 01:41:39 PM PST 24 |
| Peak memory | 209968 kb |
| Host | smart-07ba698e-e670-468a-bb8f-2e20ae3c1ca1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=27338964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rese t_error.27338964 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.750247411 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 560124730 ps |
| CPU time | 26.84 seconds |
| Started | Mar 07 01:39:32 PM PST 24 |
| Finished | Mar 07 01:39:59 PM PST 24 |
| Peak memory | 204392 kb |
| Host | smart-88c5feea-9fc8-425d-9816-0218dd059378 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=750247411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.750247411 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.1834829999 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 15816806 ps |
| CPU time | 2.64 seconds |
| Started | Mar 07 01:39:44 PM PST 24 |
| Finished | Mar 07 01:39:47 PM PST 24 |
| Peak memory | 203164 kb |
| Host | smart-151868ce-98b4-4833-84bf-36f760e84349 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1834829999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.1834829999 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2101606378 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 50692370203 ps |
| CPU time | 229.42 seconds |
| Started | Mar 07 01:39:45 PM PST 24 |
| Finished | Mar 07 01:43:36 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-d7e9f493-b528-41e0-8c14-a0a747b73947 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2101606378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl ow_rsp.2101606378 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3336234967 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 243887216 ps |
| CPU time | 10.42 seconds |
| Started | Mar 07 01:39:42 PM PST 24 |
| Finished | Mar 07 01:39:53 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-9486735e-c978-4812-9c3b-c54e27252b4c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3336234967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3336234967 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_error_random.2609508735 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1738849480 ps |
| CPU time | 30.95 seconds |
| Started | Mar 07 01:39:47 PM PST 24 |
| Finished | Mar 07 01:40:18 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-34b9d042-e4de-46c7-99b9-363453931eb7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2609508735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2609508735 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random.3501971887 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1141055991 ps |
| CPU time | 32.58 seconds |
| Started | Mar 07 01:39:42 PM PST 24 |
| Finished | Mar 07 01:40:14 PM PST 24 |
| Peak memory | 211288 kb |
| Host | smart-f57f3fe6-5fd6-4d6d-8a61-3dbe0205bac0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3501971887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.3501971887 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.157487745 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 55808715356 ps |
| CPU time | 159.49 seconds |
| Started | Mar 07 01:39:46 PM PST 24 |
| Finished | Mar 07 01:42:27 PM PST 24 |
| Peak memory | 211396 kb |
| Host | smart-2bd9f8e9-eb46-4299-8cf9-431e10eaed95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=157487745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.157487745 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1502322993 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 38526327540 ps |
| CPU time | 145.4 seconds |
| Started | Mar 07 01:39:42 PM PST 24 |
| Finished | Mar 07 01:42:07 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-e90246f5-a4bc-46c5-bda4-a3c111a9b655 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1502322993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1502322993 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.3318795593 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 223877946 ps |
| CPU time | 11.49 seconds |
| Started | Mar 07 01:39:40 PM PST 24 |
| Finished | Mar 07 01:39:52 PM PST 24 |
| Peak memory | 211284 kb |
| Host | smart-635fd23f-0127-4be2-9d85-7c4db26fc495 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318795593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3318795593 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_same_source.1584945661 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 135334538 ps |
| CPU time | 3.58 seconds |
| Started | Mar 07 01:39:41 PM PST 24 |
| Finished | Mar 07 01:39:45 PM PST 24 |
| Peak memory | 203288 kb |
| Host | smart-1aa99897-161e-43fb-9ee5-9e1dd1930db0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1584945661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1584945661 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke.2315488754 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 25258626 ps |
| CPU time | 2.02 seconds |
| Started | Mar 07 01:39:34 PM PST 24 |
| Finished | Mar 07 01:39:36 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-996e3489-04ea-4973-ab5d-cf9202956ed0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2315488754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2315488754 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3041810907 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 15881410775 ps |
| CPU time | 34.31 seconds |
| Started | Mar 07 01:39:35 PM PST 24 |
| Finished | Mar 07 01:40:10 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-389e193b-533e-4a33-b483-1e216b9f7030 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041810907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3041810907 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1033340303 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4391698136 ps |
| CPU time | 27.05 seconds |
| Started | Mar 07 01:39:46 PM PST 24 |
| Finished | Mar 07 01:40:14 PM PST 24 |
| Peak memory | 203332 kb |
| Host | smart-a1f3f8b8-7b6e-400c-af9c-3475443dd432 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1033340303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1033340303 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.2982946421 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 58771615 ps |
| CPU time | 2.48 seconds |
| Started | Mar 07 01:39:38 PM PST 24 |
| Finished | Mar 07 01:39:42 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-17dee580-eff3-4543-9400-57acfcde2335 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982946421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.2982946421 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all.1479975110 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3171005201 ps |
| CPU time | 75.35 seconds |
| Started | Mar 07 01:39:46 PM PST 24 |
| Finished | Mar 07 01:41:02 PM PST 24 |
| Peak memory | 206436 kb |
| Host | smart-97641937-665b-44bb-9c7e-916f7b25addf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1479975110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1479975110 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.3912094583 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 7211233668 ps |
| CPU time | 71.96 seconds |
| Started | Mar 07 01:39:46 PM PST 24 |
| Finished | Mar 07 01:40:59 PM PST 24 |
| Peak memory | 205748 kb |
| Host | smart-a30834a4-baa6-4be4-b766-138c636e073f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3912094583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3912094583 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.659717147 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 6824883142 ps |
| CPU time | 152.66 seconds |
| Started | Mar 07 01:39:42 PM PST 24 |
| Finished | Mar 07 01:42:15 PM PST 24 |
| Peak memory | 207212 kb |
| Host | smart-0bcfb8d8-9156-4695-bbeb-eea2e73127b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=659717147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand _reset.659717147 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.625876612 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4780292785 ps |
| CPU time | 227.34 seconds |
| Started | Mar 07 01:39:41 PM PST 24 |
| Finished | Mar 07 01:43:29 PM PST 24 |
| Peak memory | 211384 kb |
| Host | smart-73fa5bb4-f1b2-40bf-904e-292c0cd1a839 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=625876612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res et_error.625876612 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.320614622 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 329599012 ps |
| CPU time | 12.81 seconds |
| Started | Mar 07 01:39:46 PM PST 24 |
| Finished | Mar 07 01:40:00 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-076578ca-f676-4ada-b688-6462061c168d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=320614622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.320614622 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.723704144 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 421054087 ps |
| CPU time | 12.35 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:37:39 PM PST 24 |
| Peak memory | 211352 kb |
| Host | smart-d3f289d6-8fff-4c55-b4ec-2791b20785b6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=723704144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.723704144 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.480337021 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 97063378381 ps |
| CPU time | 565.41 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:46:54 PM PST 24 |
| Peak memory | 205580 kb |
| Host | smart-0bb307c9-eaae-4d23-ad1c-2a640f4ecd08 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=480337021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow _rsp.480337021 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.354083098 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 129195511 ps |
| CPU time | 10.03 seconds |
| Started | Mar 07 01:37:29 PM PST 24 |
| Finished | Mar 07 01:37:39 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-d58dbf28-4a2e-4db5-b7f9-dbe6b88c4906 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=354083098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.354083098 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_error_random.599100823 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 592563207 ps |
| CPU time | 13.52 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:37:39 PM PST 24 |
| Peak memory | 203228 kb |
| Host | smart-624ec51e-03c2-438b-9d86-f8fa47af32da |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=599100823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.599100823 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random.1514216315 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 731412450 ps |
| CPU time | 19.66 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:37:45 PM PST 24 |
| Peak memory | 204196 kb |
| Host | smart-a0e645b6-1b47-4474-bb63-64fb425a7209 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1514216315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1514216315 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.1070520936 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 9508100593 ps |
| CPU time | 26.61 seconds |
| Started | Mar 07 01:37:22 PM PST 24 |
| Finished | Mar 07 01:37:49 PM PST 24 |
| Peak memory | 203900 kb |
| Host | smart-4a8ac14e-cea9-43c3-841e-80b51be6ac31 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070520936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1070520936 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.679485458 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1332453931 ps |
| CPU time | 13.72 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:37:41 PM PST 24 |
| Peak memory | 203124 kb |
| Host | smart-0c2a7821-3e95-437b-a095-93d7f2e451bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=679485458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.679485458 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.1719357771 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 99164312 ps |
| CPU time | 9.01 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:37:36 PM PST 24 |
| Peak memory | 204316 kb |
| Host | smart-aa51cc59-15c8-4804-9d7e-ee66666a5a4f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719357771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1719357771 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_same_source.2312079974 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 127307193 ps |
| CPU time | 2.48 seconds |
| Started | Mar 07 01:37:31 PM PST 24 |
| Finished | Mar 07 01:37:34 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-f140bd26-ba74-4545-a075-2cfa1ba5d82b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2312079974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2312079974 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke.2141110 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 46125293 ps |
| CPU time | 2.19 seconds |
| Started | Mar 07 01:37:23 PM PST 24 |
| Finished | Mar 07 01:37:26 PM PST 24 |
| Peak memory | 203192 kb |
| Host | smart-8048522a-6854-496d-a950-889508bbe26b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2141110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2141110 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.4223622029 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 14122532501 ps |
| CPU time | 28.95 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:37:57 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-5ca508dd-2ea0-4e7b-9956-42fa4c481fee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223622029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.4223622029 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.3729961560 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 25841365597 ps |
| CPU time | 51.61 seconds |
| Started | Mar 07 01:37:25 PM PST 24 |
| Finished | Mar 07 01:38:17 PM PST 24 |
| Peak memory | 203160 kb |
| Host | smart-a6a337af-b5f7-4555-a29f-ba1f532dceed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3729961560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3729961560 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.153972726 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 40372678 ps |
| CPU time | 2.38 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:37:29 PM PST 24 |
| Peak memory | 203180 kb |
| Host | smart-a341d6f3-4b5a-4cf5-b2d8-731f2c5aa266 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153972726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.153972726 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all.1593798042 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4062731567 ps |
| CPU time | 53.29 seconds |
| Started | Mar 07 01:37:31 PM PST 24 |
| Finished | Mar 07 01:38:25 PM PST 24 |
| Peak memory | 207312 kb |
| Host | smart-9a80007e-cb64-443d-adb6-0b1af49efa95 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1593798042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1593798042 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.3087121654 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 1163204406 ps |
| CPU time | 41.51 seconds |
| Started | Mar 07 01:37:30 PM PST 24 |
| Finished | Mar 07 01:38:12 PM PST 24 |
| Peak memory | 204368 kb |
| Host | smart-d86fa2da-42dd-4528-b949-b40ffed2cabd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3087121654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3087121654 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2278109856 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 371701373 ps |
| CPU time | 126.49 seconds |
| Started | Mar 07 01:37:31 PM PST 24 |
| Finished | Mar 07 01:39:38 PM PST 24 |
| Peak memory | 209668 kb |
| Host | smart-6db30628-888a-49e1-b720-8fe16231b359 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2278109856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res et_error.2278109856 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.4254190742 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 30134505 ps |
| CPU time | 4.06 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:37:32 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-03468853-9666-45b2-acfe-7781bbd3537e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4254190742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.4254190742 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.3268449072 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 979092940 ps |
| CPU time | 36.09 seconds |
| Started | Mar 07 01:39:46 PM PST 24 |
| Finished | Mar 07 01:40:23 PM PST 24 |
| Peak memory | 204864 kb |
| Host | smart-bdcf3d09-6c38-47e9-9c72-f825c066e866 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3268449072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3268449072 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3402744280 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 35302332384 ps |
| CPU time | 277.04 seconds |
| Started | Mar 07 01:39:44 PM PST 24 |
| Finished | Mar 07 01:44:22 PM PST 24 |
| Peak memory | 211400 kb |
| Host | smart-99ef45e1-9e6f-4544-9a4a-0eb631292c8a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3402744280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_sl ow_rsp.3402744280 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.3926554625 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 233651420 ps |
| CPU time | 12.64 seconds |
| Started | Mar 07 01:39:44 PM PST 24 |
| Finished | Mar 07 01:39:57 PM PST 24 |
| Peak memory | 203308 kb |
| Host | smart-af19f532-c26e-476b-88a8-0b3595335184 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3926554625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3926554625 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_error_random.3598186163 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 138858689 ps |
| CPU time | 16.88 seconds |
| Started | Mar 07 01:39:46 PM PST 24 |
| Finished | Mar 07 01:40:04 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-7ae0acd0-bc46-40a4-a981-40b2a65b406d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3598186163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3598186163 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random.1629928077 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 207615165 ps |
| CPU time | 23.98 seconds |
| Started | Mar 07 01:39:45 PM PST 24 |
| Finished | Mar 07 01:40:11 PM PST 24 |
| Peak memory | 204464 kb |
| Host | smart-3bf46067-7c7d-4f2a-b5e5-0046248044d9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1629928077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1629928077 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1940398959 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 66312461834 ps |
| CPU time | 181.22 seconds |
| Started | Mar 07 01:39:41 PM PST 24 |
| Finished | Mar 07 01:42:42 PM PST 24 |
| Peak memory | 211372 kb |
| Host | smart-d16a1545-5025-4c51-b6e5-01b756d7210d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940398959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1940398959 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2751021890 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 22003200441 ps |
| CPU time | 200.16 seconds |
| Started | Mar 07 01:39:44 PM PST 24 |
| Finished | Mar 07 01:43:04 PM PST 24 |
| Peak memory | 211352 kb |
| Host | smart-b0510451-f09a-4a6b-a86a-7b984426fe33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2751021890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2751021890 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.169055308 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 216235614 ps |
| CPU time | 25.44 seconds |
| Started | Mar 07 01:39:44 PM PST 24 |
| Finished | Mar 07 01:40:10 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-8884c158-7798-457d-8dc7-2260e476f7fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169055308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.169055308 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_same_source.3790317115 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 228621935 ps |
| CPU time | 18.14 seconds |
| Started | Mar 07 01:39:40 PM PST 24 |
| Finished | Mar 07 01:39:59 PM PST 24 |
| Peak memory | 203556 kb |
| Host | smart-779c2d78-424d-489b-bd93-6b5cdb12c097 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3790317115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3790317115 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke.2866347507 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 210199549 ps |
| CPU time | 4.23 seconds |
| Started | Mar 07 01:39:39 PM PST 24 |
| Finished | Mar 07 01:39:44 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-ebc0bc80-b13f-4baa-9019-ea1a2fe9d86e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2866347507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2866347507 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.962257141 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 6479982047 ps |
| CPU time | 31.13 seconds |
| Started | Mar 07 01:39:45 PM PST 24 |
| Finished | Mar 07 01:40:18 PM PST 24 |
| Peak memory | 203164 kb |
| Host | smart-df73e3f4-b8b9-4eb7-8861-ae50b1d40623 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=962257141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.962257141 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.1730016573 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4082046970 ps |
| CPU time | 28.31 seconds |
| Started | Mar 07 01:39:43 PM PST 24 |
| Finished | Mar 07 01:40:12 PM PST 24 |
| Peak memory | 203200 kb |
| Host | smart-9e0e5aa8-a7e4-44c4-ba77-109b12420f46 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1730016573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1730016573 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.1826635280 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 26993235 ps |
| CPU time | 2.16 seconds |
| Started | Mar 07 01:39:46 PM PST 24 |
| Finished | Mar 07 01:39:49 PM PST 24 |
| Peak memory | 202940 kb |
| Host | smart-366e0422-a30f-43e6-b9f2-d7b156761826 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826635280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1826635280 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all.626121287 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1724742279 ps |
| CPU time | 224.78 seconds |
| Started | Mar 07 01:39:43 PM PST 24 |
| Finished | Mar 07 01:43:27 PM PST 24 |
| Peak memory | 210724 kb |
| Host | smart-351d43a3-bc2d-45d6-8ba9-5eebd2dd3fc0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=626121287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.626121287 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3164640569 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 10863383912 ps |
| CPU time | 139.51 seconds |
| Started | Mar 07 01:39:41 PM PST 24 |
| Finished | Mar 07 01:42:01 PM PST 24 |
| Peak memory | 207780 kb |
| Host | smart-85cc2511-210b-4e61-8c76-2320d1dd31c2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3164640569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3164640569 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3786701121 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1194651026 ps |
| CPU time | 216.54 seconds |
| Started | Mar 07 01:39:41 PM PST 24 |
| Finished | Mar 07 01:43:17 PM PST 24 |
| Peak memory | 208584 kb |
| Host | smart-b515e363-72fc-4f01-936c-43660da04b49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3786701121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran d_reset.3786701121 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3582101805 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 272051482 ps |
| CPU time | 89.81 seconds |
| Started | Mar 07 01:39:46 PM PST 24 |
| Finished | Mar 07 01:41:17 PM PST 24 |
| Peak memory | 208944 kb |
| Host | smart-f9b71e1d-3551-4824-9d40-fd1061787ea1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3582101805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_re set_error.3582101805 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.3214102193 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 710056396 ps |
| CPU time | 15.01 seconds |
| Started | Mar 07 01:39:42 PM PST 24 |
| Finished | Mar 07 01:39:57 PM PST 24 |
| Peak memory | 204500 kb |
| Host | smart-4387f033-e9ef-4c1d-8ce2-1b3cc86fba28 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3214102193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3214102193 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.3004220160 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1413457225 ps |
| CPU time | 21.16 seconds |
| Started | Mar 07 01:39:50 PM PST 24 |
| Finished | Mar 07 01:40:11 PM PST 24 |
| Peak memory | 205316 kb |
| Host | smart-cf2fdd53-b84a-4c19-85b5-d5fe6dcbdcc8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3004220160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3004220160 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.1082454331 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 18252017083 ps |
| CPU time | 129.3 seconds |
| Started | Mar 07 01:39:51 PM PST 24 |
| Finished | Mar 07 01:42:01 PM PST 24 |
| Peak memory | 205420 kb |
| Host | smart-816aa3eb-61fb-4350-b236-53835e2df315 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1082454331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_sl ow_rsp.1082454331 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.2915602956 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 233322593 ps |
| CPU time | 4.03 seconds |
| Started | Mar 07 01:39:50 PM PST 24 |
| Finished | Mar 07 01:39:55 PM PST 24 |
| Peak memory | 203088 kb |
| Host | smart-6513f92a-97b2-4922-9584-425036795a86 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2915602956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2915602956 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_error_random.1471782679 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1100535949 ps |
| CPU time | 29.13 seconds |
| Started | Mar 07 01:39:51 PM PST 24 |
| Finished | Mar 07 01:40:21 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-1c942649-174d-46a5-a51d-6d21ca3b7ee3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1471782679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1471782679 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random.2189290396 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 647852076 ps |
| CPU time | 15.11 seconds |
| Started | Mar 07 01:39:41 PM PST 24 |
| Finished | Mar 07 01:39:56 PM PST 24 |
| Peak memory | 204228 kb |
| Host | smart-f92a9977-eff5-473a-9b50-1489da7f972c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2189290396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2189290396 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.2524104831 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 42149961214 ps |
| CPU time | 146.75 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:42:19 PM PST 24 |
| Peak memory | 211456 kb |
| Host | smart-abe0f2f5-2f64-4131-b6b1-2950dce3b954 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524104831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2524104831 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3375730237 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 18051994044 ps |
| CPU time | 44.9 seconds |
| Started | Mar 07 01:39:56 PM PST 24 |
| Finished | Mar 07 01:40:41 PM PST 24 |
| Peak memory | 211408 kb |
| Host | smart-64c68c38-3490-4283-9112-5bc29d743109 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3375730237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3375730237 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.312008995 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 54190938 ps |
| CPU time | 7.38 seconds |
| Started | Mar 07 01:39:51 PM PST 24 |
| Finished | Mar 07 01:39:58 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-bb73f2f8-a90a-4146-8231-b532a17c5c71 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312008995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.312008995 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_same_source.549713021 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 646018886 ps |
| CPU time | 3.56 seconds |
| Started | Mar 07 01:39:55 PM PST 24 |
| Finished | Mar 07 01:39:59 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-81b518ab-90b1-420a-afcc-a7b03052179b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=549713021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.549713021 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke.1816226658 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 481900179 ps |
| CPU time | 3.77 seconds |
| Started | Mar 07 01:39:43 PM PST 24 |
| Finished | Mar 07 01:39:47 PM PST 24 |
| Peak memory | 203224 kb |
| Host | smart-bfba5a1b-676a-4892-a40e-f3b1b990e5f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1816226658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1816226658 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3170392866 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 7272344147 ps |
| CPU time | 30.93 seconds |
| Started | Mar 07 01:39:42 PM PST 24 |
| Finished | Mar 07 01:40:14 PM PST 24 |
| Peak memory | 203256 kb |
| Host | smart-57287777-03ec-4a61-b26e-c3dbd31e8ded |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170392866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3170392866 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3926400707 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 17218790342 ps |
| CPU time | 43.22 seconds |
| Started | Mar 07 01:39:43 PM PST 24 |
| Finished | Mar 07 01:40:27 PM PST 24 |
| Peak memory | 203284 kb |
| Host | smart-e551f86b-397c-42d6-8806-200d2090acae |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3926400707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3926400707 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.4079931407 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 28651424 ps |
| CPU time | 2.09 seconds |
| Started | Mar 07 01:39:47 PM PST 24 |
| Finished | Mar 07 01:39:49 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-4a066a08-77cf-4f42-9161-216be92fce80 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079931407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.4079931407 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all.131914148 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 786222719 ps |
| CPU time | 100.38 seconds |
| Started | Mar 07 01:39:55 PM PST 24 |
| Finished | Mar 07 01:41:35 PM PST 24 |
| Peak memory | 205472 kb |
| Host | smart-a0d59e3f-107d-4676-8c7d-8131151f227a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=131914148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.131914148 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3658251935 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1703896360 ps |
| CPU time | 25.49 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:40:18 PM PST 24 |
| Peak memory | 203196 kb |
| Host | smart-6e8e80a1-b4ac-41d0-b173-232138be8abf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3658251935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3658251935 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3963311255 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 490832606 ps |
| CPU time | 235.84 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:43:48 PM PST 24 |
| Peak memory | 208708 kb |
| Host | smart-0f71c1e6-56ad-4607-bdb1-0401a90e5327 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3963311255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran d_reset.3963311255 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.993112640 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 125197777 ps |
| CPU time | 23.33 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:40:15 PM PST 24 |
| Peak memory | 205472 kb |
| Host | smart-e5b6f817-8aab-4e74-bdb8-46f9a00b000a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=993112640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_res et_error.993112640 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1088476210 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 702515475 ps |
| CPU time | 5.13 seconds |
| Started | Mar 07 01:39:51 PM PST 24 |
| Finished | Mar 07 01:39:56 PM PST 24 |
| Peak memory | 211288 kb |
| Host | smart-e1bd67c7-6098-4b9e-90a5-c93846fb9142 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1088476210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1088476210 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.2831446797 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 592217102 ps |
| CPU time | 37.54 seconds |
| Started | Mar 07 01:39:51 PM PST 24 |
| Finished | Mar 07 01:40:28 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-d86b2282-98bf-4838-9c65-76cc94bd870f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2831446797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2831446797 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.98334091 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3757124443 ps |
| CPU time | 26.92 seconds |
| Started | Mar 07 01:40:00 PM PST 24 |
| Finished | Mar 07 01:40:27 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-895b0d3f-19df-403b-9623-736b2cbd11ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=98334091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.98334091 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_error_random.2242509493 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 606947637 ps |
| CPU time | 22.37 seconds |
| Started | Mar 07 01:39:53 PM PST 24 |
| Finished | Mar 07 01:40:16 PM PST 24 |
| Peak memory | 203052 kb |
| Host | smart-738ca0c4-15a8-44bd-9749-aefa725214d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2242509493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2242509493 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random.1680123303 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 168904258 ps |
| CPU time | 12.53 seconds |
| Started | Mar 07 01:39:55 PM PST 24 |
| Finished | Mar 07 01:40:08 PM PST 24 |
| Peak memory | 203196 kb |
| Host | smart-fed947f1-5810-407d-8e13-d6ded44ea4e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1680123303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1680123303 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1922696146 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 90328850236 ps |
| CPU time | 176.6 seconds |
| Started | Mar 07 01:39:53 PM PST 24 |
| Finished | Mar 07 01:42:50 PM PST 24 |
| Peak memory | 203964 kb |
| Host | smart-dd0b09d3-fb75-4243-b6d0-2ecd6568cc2e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922696146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1922696146 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2202582708 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 55854620643 ps |
| CPU time | 159 seconds |
| Started | Mar 07 01:39:50 PM PST 24 |
| Finished | Mar 07 01:42:30 PM PST 24 |
| Peak memory | 211424 kb |
| Host | smart-ca2fb96d-c78b-4b0a-b9b0-6058dc162902 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2202582708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2202582708 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.972591537 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 209500469 ps |
| CPU time | 23.44 seconds |
| Started | Mar 07 01:39:55 PM PST 24 |
| Finished | Mar 07 01:40:19 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-7358dec8-6ef0-4aaa-935f-e7215a8292e1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972591537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.972591537 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_same_source.2123149293 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 290451190 ps |
| CPU time | 21.84 seconds |
| Started | Mar 07 01:39:51 PM PST 24 |
| Finished | Mar 07 01:40:13 PM PST 24 |
| Peak memory | 203608 kb |
| Host | smart-de88a582-1e09-4843-9349-975bb63f9d6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2123149293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2123149293 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke.2744452359 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 41746011 ps |
| CPU time | 2.15 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:39:55 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-a37b72c6-3d92-400f-985f-5296c2fca5cf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2744452359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2744452359 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2455104279 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 7670271489 ps |
| CPU time | 26.94 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:40:20 PM PST 24 |
| Peak memory | 203256 kb |
| Host | smart-da4090d3-85a5-4cde-a7e1-083ef5afdd0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455104279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2455104279 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.693717723 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 4946405086 ps |
| CPU time | 38.83 seconds |
| Started | Mar 07 01:39:51 PM PST 24 |
| Finished | Mar 07 01:40:31 PM PST 24 |
| Peak memory | 203200 kb |
| Host | smart-9f59df96-17b3-4c76-81dd-24d43fed7521 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=693717723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.693717723 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.4237317524 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 53290718 ps |
| CPU time | 2.36 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:39:55 PM PST 24 |
| Peak memory | 203088 kb |
| Host | smart-912c49b1-ad20-4e58-bd42-db4572e769e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237317524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.4237317524 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all.1512679842 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 5115992194 ps |
| CPU time | 91.68 seconds |
| Started | Mar 07 01:39:54 PM PST 24 |
| Finished | Mar 07 01:41:25 PM PST 24 |
| Peak memory | 205552 kb |
| Host | smart-917ae368-f019-4778-80f8-8e3ccb16a48c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1512679842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1512679842 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.2393474210 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 5108595891 ps |
| CPU time | 139.67 seconds |
| Started | Mar 07 01:39:53 PM PST 24 |
| Finished | Mar 07 01:42:13 PM PST 24 |
| Peak memory | 208036 kb |
| Host | smart-b7a6cbf8-d978-4267-9602-99470809d050 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2393474210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2393474210 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.3364712893 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 4362118339 ps |
| CPU time | 207.73 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:43:20 PM PST 24 |
| Peak memory | 210488 kb |
| Host | smart-bfb483d8-912f-4819-a2d6-ff46b2e9cbff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3364712893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran d_reset.3364712893 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.473586920 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 10327108507 ps |
| CPU time | 399.54 seconds |
| Started | Mar 07 01:39:54 PM PST 24 |
| Finished | Mar 07 01:46:34 PM PST 24 |
| Peak memory | 211344 kb |
| Host | smart-3cf67c19-c227-4f58-bb2f-5d6ce6dc0a98 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=473586920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_res et_error.473586920 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1324433134 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 176245796 ps |
| CPU time | 6.51 seconds |
| Started | Mar 07 01:39:53 PM PST 24 |
| Finished | Mar 07 01:40:00 PM PST 24 |
| Peak memory | 211244 kb |
| Host | smart-32ff3a2b-4f99-497a-aca0-3057c0d08ec5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1324433134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1324433134 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1833786740 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 2896791811 ps |
| CPU time | 63.65 seconds |
| Started | Mar 07 01:39:59 PM PST 24 |
| Finished | Mar 07 01:41:04 PM PST 24 |
| Peak memory | 211404 kb |
| Host | smart-3e720650-164d-4df3-a0af-2655ed7fff7a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1833786740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1833786740 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.3743358164 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 83604917610 ps |
| CPU time | 304.22 seconds |
| Started | Mar 07 01:39:59 PM PST 24 |
| Finished | Mar 07 01:45:04 PM PST 24 |
| Peak memory | 206168 kb |
| Host | smart-59556910-8bc1-44b9-9a55-ef084239af5c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3743358164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_sl ow_rsp.3743358164 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.565379957 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1693985657 ps |
| CPU time | 13.38 seconds |
| Started | Mar 07 01:39:59 PM PST 24 |
| Finished | Mar 07 01:40:13 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-d8dcb1ac-6811-4f1f-b0c4-14399f0f28ed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=565379957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.565379957 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_error_random.3163090852 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 196526631 ps |
| CPU time | 5.8 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:39:59 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-ee3691dd-a468-432d-b69d-1d25224b988a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3163090852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3163090852 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random.564657686 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 49454254 ps |
| CPU time | 5.02 seconds |
| Started | Mar 07 01:39:54 PM PST 24 |
| Finished | Mar 07 01:39:59 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-4b218513-f2ad-42e0-af45-a3187d0c9c4e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=564657686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.564657686 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1865418181 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 10141458333 ps |
| CPU time | 63.13 seconds |
| Started | Mar 07 01:39:53 PM PST 24 |
| Finished | Mar 07 01:40:56 PM PST 24 |
| Peak memory | 204296 kb |
| Host | smart-3779ed83-0bc3-4cc7-aa5b-b9d296b9a881 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865418181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1865418181 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3222914844 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 71279325398 ps |
| CPU time | 174.76 seconds |
| Started | Mar 07 01:39:53 PM PST 24 |
| Finished | Mar 07 01:42:48 PM PST 24 |
| Peak memory | 204872 kb |
| Host | smart-cd5e5760-e91c-4f2e-86ea-5dd319d1067f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3222914844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3222914844 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.1478238515 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 29265213 ps |
| CPU time | 2.04 seconds |
| Started | Mar 07 01:39:58 PM PST 24 |
| Finished | Mar 07 01:40:02 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-a59d635c-9e1d-4f18-ae09-2f0ba7b0958b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478238515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1478238515 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_same_source.948284105 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 308524861 ps |
| CPU time | 6.84 seconds |
| Started | Mar 07 01:39:59 PM PST 24 |
| Finished | Mar 07 01:40:07 PM PST 24 |
| Peak memory | 203320 kb |
| Host | smart-8bbff1e3-ea16-4bc8-9b04-9c8975ab17ec |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=948284105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.948284105 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke.888855937 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 35057824 ps |
| CPU time | 2.27 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:39:55 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-cd49b79e-cd31-494a-a9b5-6557d7958ca1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=888855937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.888855937 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2785533565 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 31302003581 ps |
| CPU time | 41.27 seconds |
| Started | Mar 07 01:39:58 PM PST 24 |
| Finished | Mar 07 01:40:40 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-03b90f78-029f-49a3-b172-f2b5bdaa54bc |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785533565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2785533565 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1941472875 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2624412326 ps |
| CPU time | 22.63 seconds |
| Started | Mar 07 01:39:54 PM PST 24 |
| Finished | Mar 07 01:40:17 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-394a9260-b1d9-4f0a-b924-763cedf3ab1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1941472875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1941472875 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1310135854 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 28376043 ps |
| CPU time | 2.61 seconds |
| Started | Mar 07 01:39:55 PM PST 24 |
| Finished | Mar 07 01:39:58 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-a3af14f6-e4b4-4106-9e7e-e35976004b7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310135854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1310135854 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all.3216007821 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 6790774590 ps |
| CPU time | 150.12 seconds |
| Started | Mar 07 01:39:54 PM PST 24 |
| Finished | Mar 07 01:42:24 PM PST 24 |
| Peak memory | 205580 kb |
| Host | smart-58473fd8-50eb-455d-a53e-61ebd9009d07 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3216007821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3216007821 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2343638850 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 35324007934 ps |
| CPU time | 188.22 seconds |
| Started | Mar 07 01:39:54 PM PST 24 |
| Finished | Mar 07 01:43:02 PM PST 24 |
| Peak memory | 206160 kb |
| Host | smart-5798a74d-1676-4504-9ab0-0eee1ad53223 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2343638850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2343638850 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2709840308 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3427821769 ps |
| CPU time | 110.87 seconds |
| Started | Mar 07 01:39:53 PM PST 24 |
| Finished | Mar 07 01:41:44 PM PST 24 |
| Peak memory | 207496 kb |
| Host | smart-65bfe593-d9bc-4e9c-9650-0fd3f174e7a0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2709840308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran d_reset.2709840308 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1654834864 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3793293826 ps |
| CPU time | 175.77 seconds |
| Started | Mar 07 01:39:56 PM PST 24 |
| Finished | Mar 07 01:42:52 PM PST 24 |
| Peak memory | 209344 kb |
| Host | smart-42a72b24-e893-42a5-86b5-3c6d48e8c7e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1654834864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re set_error.1654834864 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.1618302225 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 166792583 ps |
| CPU time | 18.2 seconds |
| Started | Mar 07 01:39:52 PM PST 24 |
| Finished | Mar 07 01:40:11 PM PST 24 |
| Peak memory | 204964 kb |
| Host | smart-60355484-e6bd-44d1-90be-03e1d8c5305e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1618302225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1618302225 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3370702947 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 46996874910 ps |
| CPU time | 191.5 seconds |
| Started | Mar 07 01:40:03 PM PST 24 |
| Finished | Mar 07 01:43:15 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-bd2cf77b-7e9d-4367-bfd4-b04e65195609 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3370702947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl ow_rsp.3370702947 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.3770104899 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 344234390 ps |
| CPU time | 9.1 seconds |
| Started | Mar 07 01:40:01 PM PST 24 |
| Finished | Mar 07 01:40:10 PM PST 24 |
| Peak memory | 203300 kb |
| Host | smart-4b77bc5b-4809-4c38-89a5-a68ac06e4998 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3770104899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3770104899 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_error_random.3981539776 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 225604363 ps |
| CPU time | 22.43 seconds |
| Started | Mar 07 01:40:01 PM PST 24 |
| Finished | Mar 07 01:40:23 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-6fdfe72e-b71e-4427-9c3c-b0e2e8a07e1e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3981539776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3981539776 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random.2184265135 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 976925655 ps |
| CPU time | 34.66 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:40:37 PM PST 24 |
| Peak memory | 204580 kb |
| Host | smart-665be8d1-d32f-4312-8bad-544a48dd0b49 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2184265135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2184265135 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.296816967 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 30293583567 ps |
| CPU time | 182.06 seconds |
| Started | Mar 07 01:40:07 PM PST 24 |
| Finished | Mar 07 01:43:12 PM PST 24 |
| Peak memory | 204756 kb |
| Host | smart-d26dadb6-6f55-4566-b8d8-1579a5e81a79 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=296816967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.296816967 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1738626923 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 5008311362 ps |
| CPU time | 25.66 seconds |
| Started | Mar 07 01:40:01 PM PST 24 |
| Finished | Mar 07 01:40:27 PM PST 24 |
| Peak memory | 203220 kb |
| Host | smart-0cd97c1c-c808-4dc5-aefe-80027213f2fb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1738626923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1738626923 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1096774016 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 862963737 ps |
| CPU time | 29.94 seconds |
| Started | Mar 07 01:40:08 PM PST 24 |
| Finished | Mar 07 01:40:40 PM PST 24 |
| Peak memory | 204700 kb |
| Host | smart-0c734873-4ea5-4930-bf54-c283aaeb5361 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096774016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1096774016 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_same_source.1404328826 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 506170965 ps |
| CPU time | 14.91 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:40:17 PM PST 24 |
| Peak memory | 203596 kb |
| Host | smart-f7921155-4801-4d53-bd70-8556811ac130 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1404328826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1404328826 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke.3674506202 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 122934657 ps |
| CPU time | 2.3 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:40:05 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-ebed1a0d-f71e-44b2-9b05-ed574a5ec280 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3674506202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3674506202 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1167300927 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 33604080376 ps |
| CPU time | 44.09 seconds |
| Started | Mar 07 01:40:04 PM PST 24 |
| Finished | Mar 07 01:40:49 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-f33f1ca3-74cc-488d-9666-0cdf03da270e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167300927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1167300927 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4128086605 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 19247264957 ps |
| CPU time | 39.72 seconds |
| Started | Mar 07 01:40:00 PM PST 24 |
| Finished | Mar 07 01:40:40 PM PST 24 |
| Peak memory | 203084 kb |
| Host | smart-36b8d014-5302-41e7-97dd-987490be372f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4128086605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4128086605 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.938022707 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 74423233 ps |
| CPU time | 2.73 seconds |
| Started | Mar 07 01:40:00 PM PST 24 |
| Finished | Mar 07 01:40:03 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-6d2b4043-6c51-421c-b7c9-410d05b521a1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938022707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.938022707 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all.1878924083 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1241722298 ps |
| CPU time | 141.16 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:42:23 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-aa7949bb-57b3-451f-a57a-ecb92edeec73 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1878924083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1878924083 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.1013129340 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 5787962987 ps |
| CPU time | 76.24 seconds |
| Started | Mar 07 01:40:04 PM PST 24 |
| Finished | Mar 07 01:41:21 PM PST 24 |
| Peak memory | 205552 kb |
| Host | smart-723e72e8-24c0-4d3b-be85-16b802e95dd1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1013129340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1013129340 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3939711494 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 335365189 ps |
| CPU time | 122.6 seconds |
| Started | Mar 07 01:40:03 PM PST 24 |
| Finished | Mar 07 01:42:06 PM PST 24 |
| Peak memory | 208256 kb |
| Host | smart-a9140b61-9a94-448f-ad13-d324746ce89f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3939711494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran d_reset.3939711494 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.2340058467 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 622522292 ps |
| CPU time | 18.34 seconds |
| Started | Mar 07 01:40:00 PM PST 24 |
| Finished | Mar 07 01:40:19 PM PST 24 |
| Peak memory | 204332 kb |
| Host | smart-1fea4726-68e7-40ab-99ac-23f126ec30f4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2340058467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2340058467 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.896418584 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 214304583 ps |
| CPU time | 13.74 seconds |
| Started | Mar 07 01:40:04 PM PST 24 |
| Finished | Mar 07 01:40:19 PM PST 24 |
| Peak memory | 204212 kb |
| Host | smart-de9d271f-6867-48bd-8a8c-f7b69c957b82 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=896418584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.896418584 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3599575113 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 26320625929 ps |
| CPU time | 254.61 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:44:17 PM PST 24 |
| Peak memory | 211384 kb |
| Host | smart-f1701602-576c-49cb-b47d-2adbc0ee7c3f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3599575113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl ow_rsp.3599575113 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.20093277 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 81848202 ps |
| CPU time | 4.74 seconds |
| Started | Mar 07 01:40:04 PM PST 24 |
| Finished | Mar 07 01:40:14 PM PST 24 |
| Peak memory | 203392 kb |
| Host | smart-a0591d61-817f-45bc-9f97-7936fe72337a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=20093277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.20093277 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_error_random.2617047257 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 131600012 ps |
| CPU time | 4.18 seconds |
| Started | Mar 07 01:40:01 PM PST 24 |
| Finished | Mar 07 01:40:05 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-a6b77e30-98fc-4ec6-85b4-d3a40b2d1afa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2617047257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2617047257 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random.3320503328 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 4490227223 ps |
| CPU time | 27.82 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:40:31 PM PST 24 |
| Peak memory | 204408 kb |
| Host | smart-ec4ea3a1-e482-4409-9dc0-e7681eee7bcb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3320503328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.3320503328 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.820146323 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3775335515 ps |
| CPU time | 12.99 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:40:15 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-506a71e4-9112-434f-990e-5af561af7f33 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=820146323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.820146323 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1252546914 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 16650785825 ps |
| CPU time | 154.88 seconds |
| Started | Mar 07 01:40:01 PM PST 24 |
| Finished | Mar 07 01:42:36 PM PST 24 |
| Peak memory | 204688 kb |
| Host | smart-1b5a4cf7-de04-43ea-a6d0-b5826bb6a54f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1252546914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1252546914 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.3630821423 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 299938983 ps |
| CPU time | 11.38 seconds |
| Started | Mar 07 01:40:03 PM PST 24 |
| Finished | Mar 07 01:40:15 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-02d6ed28-00f8-4474-915e-64cb62b83ca8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630821423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.3630821423 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_same_source.3783901291 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4547926159 ps |
| CPU time | 37.3 seconds |
| Started | Mar 07 01:40:01 PM PST 24 |
| Finished | Mar 07 01:40:38 PM PST 24 |
| Peak memory | 204200 kb |
| Host | smart-ccf49fb1-e4c5-4bf3-80ef-1af6cee88ba8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3783901291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3783901291 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke.617985456 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 96930996 ps |
| CPU time | 2.28 seconds |
| Started | Mar 07 01:40:03 PM PST 24 |
| Finished | Mar 07 01:40:06 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-78940f23-6499-43c6-b5f0-b9552d21e065 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=617985456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.617985456 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.542463783 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11823398524 ps |
| CPU time | 30.54 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:40:32 PM PST 24 |
| Peak memory | 203220 kb |
| Host | smart-43596dd6-2a76-4b97-b50e-55fb1be01c6d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=542463783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.542463783 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.535421204 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3930188568 ps |
| CPU time | 25.09 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:40:27 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-2afd9b7e-0d1f-4bd7-8d27-ec0b636db8b5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=535421204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.535421204 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.63979745 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 38834191 ps |
| CPU time | 2.35 seconds |
| Started | Mar 07 01:40:08 PM PST 24 |
| Finished | Mar 07 01:40:13 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-e5975006-2c98-432b-a7aa-bbfcca416b22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63979745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.63979745 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1750683425 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3141725540 ps |
| CPU time | 57.15 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:40:59 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-3958b236-2ee0-44a6-aa00-a9f3d3d14ba4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1750683425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1750683425 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.121243687 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2293856666 ps |
| CPU time | 43.71 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:40:46 PM PST 24 |
| Peak memory | 204312 kb |
| Host | smart-3412fc02-9140-4f63-abbe-7dfb38c08eed |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=121243687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.121243687 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1306264385 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2608465046 ps |
| CPU time | 356.31 seconds |
| Started | Mar 07 01:40:07 PM PST 24 |
| Finished | Mar 07 01:46:07 PM PST 24 |
| Peak memory | 211468 kb |
| Host | smart-9cd20546-62d7-4d70-a51f-743bd42c031e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1306264385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran d_reset.1306264385 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3226814204 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 727057820 ps |
| CPU time | 176.48 seconds |
| Started | Mar 07 01:40:02 PM PST 24 |
| Finished | Mar 07 01:42:59 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-7e8b16ff-31bd-4968-b68b-a2e0e38bdf92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3226814204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re set_error.3226814204 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.3490023007 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 242915637 ps |
| CPU time | 15.69 seconds |
| Started | Mar 07 01:40:03 PM PST 24 |
| Finished | Mar 07 01:40:19 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-1cc8f4c7-e90e-4817-b20d-42cbabcb032d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3490023007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3490023007 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.1304652235 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2873990394 ps |
| CPU time | 66.03 seconds |
| Started | Mar 07 01:40:12 PM PST 24 |
| Finished | Mar 07 01:41:19 PM PST 24 |
| Peak memory | 205296 kb |
| Host | smart-87381908-022a-461c-b60f-37712600dbef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1304652235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.1304652235 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2512684257 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 119665110497 ps |
| CPU time | 361.52 seconds |
| Started | Mar 07 01:40:11 PM PST 24 |
| Finished | Mar 07 01:46:14 PM PST 24 |
| Peak memory | 211348 kb |
| Host | smart-e789ea3d-867c-4cf6-acdf-7d6bcc72ba22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2512684257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl ow_rsp.2512684257 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2894843681 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 978954342 ps |
| CPU time | 20.1 seconds |
| Started | Mar 07 01:40:20 PM PST 24 |
| Finished | Mar 07 01:40:40 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-fcd019c1-00ee-445f-aeb7-018525f9a2c7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2894843681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2894843681 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_error_random.973839589 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1924436903 ps |
| CPU time | 21.77 seconds |
| Started | Mar 07 01:40:12 PM PST 24 |
| Finished | Mar 07 01:40:34 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-bd2a0d0f-a8b2-49f1-a7da-74eeab089635 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=973839589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.973839589 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2451787483 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 45119313984 ps |
| CPU time | 212.29 seconds |
| Started | Mar 07 01:40:10 PM PST 24 |
| Finished | Mar 07 01:43:45 PM PST 24 |
| Peak memory | 211408 kb |
| Host | smart-d3efabc4-69d0-4b21-936b-3e966a672d7f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451787483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2451787483 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1342369158 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 28562074922 ps |
| CPU time | 233.07 seconds |
| Started | Mar 07 01:40:10 PM PST 24 |
| Finished | Mar 07 01:44:05 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-84718d61-647b-4764-8f0b-5e4f5813ddd0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1342369158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1342369158 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.2199180831 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 34797613 ps |
| CPU time | 5.34 seconds |
| Started | Mar 07 01:40:09 PM PST 24 |
| Finished | Mar 07 01:40:16 PM PST 24 |
| Peak memory | 203864 kb |
| Host | smart-f98ecc29-b76f-4bc7-a51a-ce365352c64b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199180831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2199180831 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_same_source.1787367449 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 2305946751 ps |
| CPU time | 22.6 seconds |
| Started | Mar 07 01:40:13 PM PST 24 |
| Finished | Mar 07 01:40:37 PM PST 24 |
| Peak memory | 203584 kb |
| Host | smart-fea2c5cd-0467-4877-8f51-e5f8ba615a21 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1787367449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1787367449 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke.3878401630 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 65337576 ps |
| CPU time | 2.52 seconds |
| Started | Mar 07 01:40:04 PM PST 24 |
| Finished | Mar 07 01:40:07 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-45bdbdfc-1359-4993-834a-1a07af86e55c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3878401630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3878401630 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3281246202 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 6798320643 ps |
| CPU time | 29.53 seconds |
| Started | Mar 07 01:40:15 PM PST 24 |
| Finished | Mar 07 01:40:46 PM PST 24 |
| Peak memory | 203168 kb |
| Host | smart-d1f11a17-5dac-4d0a-8cbc-cebeda54ab41 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281246202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3281246202 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.448772090 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 5125356813 ps |
| CPU time | 33.47 seconds |
| Started | Mar 07 01:40:09 PM PST 24 |
| Finished | Mar 07 01:40:43 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-35b58aa6-810d-4e40-a22f-77fc303357c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=448772090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.448772090 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1638230578 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 32701383 ps |
| CPU time | 2.08 seconds |
| Started | Mar 07 01:40:09 PM PST 24 |
| Finished | Mar 07 01:40:13 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-a67881e7-f6c2-4511-ac5a-883e6d37ff9a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638230578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1638230578 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all.2277653001 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 2234654577 ps |
| CPU time | 126.77 seconds |
| Started | Mar 07 01:40:10 PM PST 24 |
| Finished | Mar 07 01:42:18 PM PST 24 |
| Peak memory | 208444 kb |
| Host | smart-3759391d-31fb-4898-8091-66f628fd20f0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2277653001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2277653001 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.3349990040 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 885132500 ps |
| CPU time | 26.24 seconds |
| Started | Mar 07 01:40:11 PM PST 24 |
| Finished | Mar 07 01:40:39 PM PST 24 |
| Peak memory | 204584 kb |
| Host | smart-5cbf53cb-a553-4dd8-907c-acd440ffb8ea |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3349990040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3349990040 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.67831481 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 583461396 ps |
| CPU time | 221.75 seconds |
| Started | Mar 07 01:40:10 PM PST 24 |
| Finished | Mar 07 01:43:54 PM PST 24 |
| Peak memory | 210224 kb |
| Host | smart-d47c7627-e926-4001-b948-d45a66080ba3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=67831481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_ reset.67831481 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.4185963008 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3393339720 ps |
| CPU time | 280.07 seconds |
| Started | Mar 07 01:40:10 PM PST 24 |
| Finished | Mar 07 01:44:52 PM PST 24 |
| Peak memory | 223288 kb |
| Host | smart-d062560a-dcb0-410e-aadd-680e9ceb9c70 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4185963008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re set_error.4185963008 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.225398257 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2589059146 ps |
| CPU time | 36.01 seconds |
| Started | Mar 07 01:40:10 PM PST 24 |
| Finished | Mar 07 01:40:48 PM PST 24 |
| Peak memory | 211344 kb |
| Host | smart-6d156cec-8119-4972-aaa3-58575c301238 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=225398257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.225398257 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.89487866 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 221324552 ps |
| CPU time | 17.34 seconds |
| Started | Mar 07 01:40:20 PM PST 24 |
| Finished | Mar 07 01:40:37 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-935a96f6-48b9-405f-91b7-02a753690b93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=89487866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.89487866 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.1079496780 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 38764314418 ps |
| CPU time | 233.27 seconds |
| Started | Mar 07 01:40:12 PM PST 24 |
| Finished | Mar 07 01:44:06 PM PST 24 |
| Peak memory | 205496 kb |
| Host | smart-8d0d6bda-3cd6-4c52-ac58-c402114d5b06 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1079496780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl ow_rsp.1079496780 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1221249642 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 223626648 ps |
| CPU time | 8.06 seconds |
| Started | Mar 07 01:40:09 PM PST 24 |
| Finished | Mar 07 01:40:19 PM PST 24 |
| Peak memory | 203252 kb |
| Host | smart-e48110cc-6fa1-4b52-be61-2057aa89d7bd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1221249642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1221249642 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_error_random.1389098385 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2203502564 ps |
| CPU time | 28.66 seconds |
| Started | Mar 07 01:40:11 PM PST 24 |
| Finished | Mar 07 01:40:41 PM PST 24 |
| Peak memory | 203296 kb |
| Host | smart-2fbd3138-504e-4cf6-9f62-3a34f5726527 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1389098385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1389098385 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random.960368114 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 23306204 ps |
| CPU time | 2.3 seconds |
| Started | Mar 07 01:40:09 PM PST 24 |
| Finished | Mar 07 01:40:13 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-2172b391-2c18-4b47-b451-534763206f75 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=960368114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.960368114 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.2709426768 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 4182910824 ps |
| CPU time | 13.73 seconds |
| Started | Mar 07 01:40:11 PM PST 24 |
| Finished | Mar 07 01:40:26 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-58162248-c48a-41de-9057-1fc4f11e4aeb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709426768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2709426768 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.2679688606 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 44875856383 ps |
| CPU time | 147.6 seconds |
| Started | Mar 07 01:40:10 PM PST 24 |
| Finished | Mar 07 01:42:40 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-f49d4354-c7d0-433f-9186-a8077ba7d105 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2679688606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2679688606 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.1745092873 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 491370259 ps |
| CPU time | 12.13 seconds |
| Started | Mar 07 01:40:09 PM PST 24 |
| Finished | Mar 07 01:40:23 PM PST 24 |
| Peak memory | 204168 kb |
| Host | smart-21949547-7072-46c8-8e78-a9e8afdfc718 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745092873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1745092873 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_same_source.3025890706 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 583586813 ps |
| CPU time | 19.69 seconds |
| Started | Mar 07 01:40:15 PM PST 24 |
| Finished | Mar 07 01:40:36 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-1267e842-bb6b-473c-8167-6b8984e66e35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3025890706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3025890706 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke.3696022274 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 151408848 ps |
| CPU time | 3.69 seconds |
| Started | Mar 07 01:40:09 PM PST 24 |
| Finished | Mar 07 01:40:14 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-6b9e8d7f-1caf-490b-b849-91d1babc90df |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3696022274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3696022274 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.2759394155 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4917749607 ps |
| CPU time | 29.88 seconds |
| Started | Mar 07 01:40:13 PM PST 24 |
| Finished | Mar 07 01:40:44 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-ac00c94d-84da-477e-8e97-887a0b3b2230 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759394155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2759394155 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.1852577019 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 5770278820 ps |
| CPU time | 37.11 seconds |
| Started | Mar 07 01:40:13 PM PST 24 |
| Finished | Mar 07 01:40:52 PM PST 24 |
| Peak memory | 203168 kb |
| Host | smart-583e5466-a1b9-4d26-a8a7-d4dab654858e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1852577019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1852577019 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.375077383 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 63189881 ps |
| CPU time | 2.53 seconds |
| Started | Mar 07 01:40:11 PM PST 24 |
| Finished | Mar 07 01:40:15 PM PST 24 |
| Peak memory | 203176 kb |
| Host | smart-5a61f479-2157-40e0-8731-956595aa1f03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375077383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.375077383 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all.267339659 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 5546955998 ps |
| CPU time | 174.32 seconds |
| Started | Mar 07 01:40:10 PM PST 24 |
| Finished | Mar 07 01:43:06 PM PST 24 |
| Peak memory | 206932 kb |
| Host | smart-65ff6e2d-c25a-419b-810b-6ac8d37c39b8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=267339659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.267339659 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.4178289410 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 4372251331 ps |
| CPU time | 106.19 seconds |
| Started | Mar 07 01:40:16 PM PST 24 |
| Finished | Mar 07 01:42:03 PM PST 24 |
| Peak memory | 206244 kb |
| Host | smart-822ff5c0-f569-46bb-943e-a26de913bb12 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4178289410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.4178289410 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.599326261 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2113106885 ps |
| CPU time | 181.22 seconds |
| Started | Mar 07 01:40:12 PM PST 24 |
| Finished | Mar 07 01:43:14 PM PST 24 |
| Peak memory | 207644 kb |
| Host | smart-3b4ad4f6-fd65-4989-ac5f-6d27179031f3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=599326261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand _reset.599326261 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1035978265 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 10570860596 ps |
| CPU time | 339.27 seconds |
| Started | Mar 07 01:40:20 PM PST 24 |
| Finished | Mar 07 01:45:59 PM PST 24 |
| Peak memory | 219648 kb |
| Host | smart-f9cfb441-4e5f-4c90-a7d9-f163c61fdc0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1035978265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re set_error.1035978265 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.2266819169 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 651283783 ps |
| CPU time | 18.83 seconds |
| Started | Mar 07 01:40:11 PM PST 24 |
| Finished | Mar 07 01:40:31 PM PST 24 |
| Peak memory | 211376 kb |
| Host | smart-9e74c428-80af-457b-b39d-7664b8c2e089 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2266819169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2266819169 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.104586962 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 715035094 ps |
| CPU time | 26.63 seconds |
| Started | Mar 07 01:40:20 PM PST 24 |
| Finished | Mar 07 01:40:47 PM PST 24 |
| Peak memory | 205624 kb |
| Host | smart-636fc584-13d3-4877-b3f9-5b4759feb519 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=104586962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.104586962 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2896836388 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 32901792246 ps |
| CPU time | 237.46 seconds |
| Started | Mar 07 01:40:22 PM PST 24 |
| Finished | Mar 07 01:44:19 PM PST 24 |
| Peak memory | 205388 kb |
| Host | smart-68e229ec-ceb9-41e3-810f-f53432bfc983 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2896836388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl ow_rsp.2896836388 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1000099783 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 91126564 ps |
| CPU time | 12.99 seconds |
| Started | Mar 07 01:40:27 PM PST 24 |
| Finished | Mar 07 01:40:40 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-ce1ee4cc-83c2-4bda-88df-0d91d2b73109 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1000099783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1000099783 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_error_random.3995809554 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 130297258 ps |
| CPU time | 3.07 seconds |
| Started | Mar 07 01:40:22 PM PST 24 |
| Finished | Mar 07 01:40:25 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-59a76867-d602-483a-8ae4-5f6de35375f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3995809554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3995809554 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random.4230301534 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 683891522 ps |
| CPU time | 22.18 seconds |
| Started | Mar 07 01:40:21 PM PST 24 |
| Finished | Mar 07 01:40:43 PM PST 24 |
| Peak memory | 204124 kb |
| Host | smart-15283e0d-81d6-4ec6-b70f-243bfb0ed38a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4230301534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.4230301534 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.163236596 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 31843709338 ps |
| CPU time | 211.77 seconds |
| Started | Mar 07 01:40:22 PM PST 24 |
| Finished | Mar 07 01:43:53 PM PST 24 |
| Peak memory | 211396 kb |
| Host | smart-d86822d9-bd17-4f18-a450-65cd291951e8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=163236596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.163236596 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.639728419 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 93568121290 ps |
| CPU time | 245.46 seconds |
| Started | Mar 07 01:40:21 PM PST 24 |
| Finished | Mar 07 01:44:26 PM PST 24 |
| Peak memory | 204276 kb |
| Host | smart-5d407e85-4505-48b0-b179-71eb9a04e425 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=639728419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.639728419 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.3496095460 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 402559302 ps |
| CPU time | 16.44 seconds |
| Started | Mar 07 01:40:20 PM PST 24 |
| Finished | Mar 07 01:40:36 PM PST 24 |
| Peak memory | 204076 kb |
| Host | smart-e41bcec5-75a7-4987-9f70-286c80e3e1e5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496095460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.3496095460 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_same_source.3732780602 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 257188907 ps |
| CPU time | 15.15 seconds |
| Started | Mar 07 01:40:21 PM PST 24 |
| Finished | Mar 07 01:40:36 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-67f026f5-6c6d-4387-822e-9267def59ff9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3732780602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3732780602 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke.2241628728 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 26817911 ps |
| CPU time | 2.34 seconds |
| Started | Mar 07 01:40:21 PM PST 24 |
| Finished | Mar 07 01:40:23 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-301e2526-bd90-4176-8905-a760c5025fd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2241628728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2241628728 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.4232697738 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 5857968314 ps |
| CPU time | 25.63 seconds |
| Started | Mar 07 01:40:24 PM PST 24 |
| Finished | Mar 07 01:40:50 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-188fd898-8642-48b5-afa7-3ea48761e58e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232697738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.4232697738 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.862929075 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 3931638686 ps |
| CPU time | 29.52 seconds |
| Started | Mar 07 01:40:22 PM PST 24 |
| Finished | Mar 07 01:40:51 PM PST 24 |
| Peak memory | 203216 kb |
| Host | smart-64de5d37-ca81-4f0e-8ae1-f7dba2f3b00d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=862929075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.862929075 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.1218469435 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 35021682 ps |
| CPU time | 2.25 seconds |
| Started | Mar 07 01:40:22 PM PST 24 |
| Finished | Mar 07 01:40:25 PM PST 24 |
| Peak memory | 203072 kb |
| Host | smart-3db28f09-da94-4bd7-b771-428414b0eb6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218469435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.1218469435 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all.2011032172 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1054789784 ps |
| CPU time | 148.73 seconds |
| Started | Mar 07 01:40:21 PM PST 24 |
| Finished | Mar 07 01:42:50 PM PST 24 |
| Peak memory | 207100 kb |
| Host | smart-38e46f99-62c1-4cf3-87a8-3a2f1098b749 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2011032172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2011032172 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.2291926171 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 173211572 ps |
| CPU time | 18.16 seconds |
| Started | Mar 07 01:40:21 PM PST 24 |
| Finished | Mar 07 01:40:40 PM PST 24 |
| Peak memory | 203048 kb |
| Host | smart-c031be02-875e-46fd-9fc6-420ed61ea495 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2291926171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2291926171 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.2872138824 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 10568650 ps |
| CPU time | 10.02 seconds |
| Started | Mar 07 01:40:22 PM PST 24 |
| Finished | Mar 07 01:40:32 PM PST 24 |
| Peak memory | 203228 kb |
| Host | smart-6711c5c3-5e1f-4790-8fe0-0664ca685db8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2872138824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran d_reset.2872138824 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.4201346874 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 7832266137 ps |
| CPU time | 239.15 seconds |
| Started | Mar 07 01:40:22 PM PST 24 |
| Finished | Mar 07 01:44:21 PM PST 24 |
| Peak memory | 219740 kb |
| Host | smart-727f32c5-5264-4ea1-aaa9-76ed39dd56fa |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4201346874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re set_error.4201346874 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.1932818184 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 446209160 ps |
| CPU time | 16.06 seconds |
| Started | Mar 07 01:40:20 PM PST 24 |
| Finished | Mar 07 01:40:36 PM PST 24 |
| Peak memory | 204700 kb |
| Host | smart-2adcd0e5-3541-4eef-bb45-9494541f59fe |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1932818184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1932818184 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.1994560979 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1220004607 ps |
| CPU time | 29.89 seconds |
| Started | Mar 07 01:40:20 PM PST 24 |
| Finished | Mar 07 01:40:50 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-c3ab074e-3760-4e5b-b878-f9089c383167 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1994560979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1994560979 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1855233392 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 15179745063 ps |
| CPU time | 141.03 seconds |
| Started | Mar 07 01:40:27 PM PST 24 |
| Finished | Mar 07 01:42:48 PM PST 24 |
| Peak memory | 205472 kb |
| Host | smart-f7353c0e-fc8c-456e-aeb8-c7fe8ede28b3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1855233392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl ow_rsp.1855233392 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.3999597311 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 110760570 ps |
| CPU time | 16.28 seconds |
| Started | Mar 07 01:40:32 PM PST 24 |
| Finished | Mar 07 01:40:49 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-99d77517-b149-4ee1-aa10-4e45d85137ce |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3999597311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.3999597311 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_error_random.3001370125 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 1212838750 ps |
| CPU time | 18.42 seconds |
| Started | Mar 07 01:40:27 PM PST 24 |
| Finished | Mar 07 01:40:45 PM PST 24 |
| Peak memory | 201984 kb |
| Host | smart-d4562afc-5810-4a7a-b59f-b5eff2621701 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3001370125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3001370125 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random.976274115 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 386614843 ps |
| CPU time | 9.56 seconds |
| Started | Mar 07 01:40:23 PM PST 24 |
| Finished | Mar 07 01:40:33 PM PST 24 |
| Peak memory | 204176 kb |
| Host | smart-db9925f1-db5f-4850-a725-494ce5202ae3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=976274115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.976274115 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.3185638233 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 63447670759 ps |
| CPU time | 156.45 seconds |
| Started | Mar 07 01:40:21 PM PST 24 |
| Finished | Mar 07 01:42:57 PM PST 24 |
| Peak memory | 204504 kb |
| Host | smart-dcb3684c-a29e-450a-ac94-6a990e540d51 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185638233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3185638233 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3176908505 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 15025612057 ps |
| CPU time | 117.25 seconds |
| Started | Mar 07 01:40:20 PM PST 24 |
| Finished | Mar 07 01:42:17 PM PST 24 |
| Peak memory | 204308 kb |
| Host | smart-c2b69052-00d5-4a02-9568-b710b7acbcff |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3176908505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3176908505 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.2126105920 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 325400656 ps |
| CPU time | 28.19 seconds |
| Started | Mar 07 01:40:21 PM PST 24 |
| Finished | Mar 07 01:40:50 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-6743b7c3-9d7e-477d-8793-b3b78af834af |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126105920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2126105920 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_same_source.2992161710 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 744538894 ps |
| CPU time | 16.53 seconds |
| Started | Mar 07 01:40:22 PM PST 24 |
| Finished | Mar 07 01:40:39 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-9a83f678-afd6-4840-a6eb-4b643e423887 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2992161710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2992161710 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke.1666151402 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 451375947 ps |
| CPU time | 4.03 seconds |
| Started | Mar 07 01:40:21 PM PST 24 |
| Finished | Mar 07 01:40:25 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-550fe341-bdd1-4574-bf8d-36e2143fe1ee |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1666151402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1666151402 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.1775028038 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 7541242550 ps |
| CPU time | 30.98 seconds |
| Started | Mar 07 01:40:24 PM PST 24 |
| Finished | Mar 07 01:40:55 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-85edb503-2f49-4b4a-8406-472f1c37bfef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775028038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1775028038 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1235854045 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 14974583841 ps |
| CPU time | 30.64 seconds |
| Started | Mar 07 01:40:20 PM PST 24 |
| Finished | Mar 07 01:40:51 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-2b58c2ff-cc5b-439c-93de-765a7258e19a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1235854045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1235854045 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3800876606 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 49865004 ps |
| CPU time | 2.14 seconds |
| Started | Mar 07 01:40:21 PM PST 24 |
| Finished | Mar 07 01:40:24 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-fc4555b3-ff9a-4bfb-9b6f-3972c2994f03 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800876606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3800876606 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all.2332696188 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 873154832 ps |
| CPU time | 96.6 seconds |
| Started | Mar 07 01:40:32 PM PST 24 |
| Finished | Mar 07 01:42:09 PM PST 24 |
| Peak memory | 207440 kb |
| Host | smart-67cfef12-342c-4fde-ae86-51524694553e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2332696188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2332696188 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.1203956191 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 7759047563 ps |
| CPU time | 121.21 seconds |
| Started | Mar 07 01:40:32 PM PST 24 |
| Finished | Mar 07 01:42:33 PM PST 24 |
| Peak memory | 211404 kb |
| Host | smart-8b37ade6-9556-4938-a2a6-e3bf4ca5fb04 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1203956191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1203956191 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.414812611 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 2298216687 ps |
| CPU time | 254.57 seconds |
| Started | Mar 07 01:40:34 PM PST 24 |
| Finished | Mar 07 01:44:49 PM PST 24 |
| Peak memory | 208196 kb |
| Host | smart-89752a43-e079-444c-9e77-d28ff1954745 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=414812611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand _reset.414812611 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2933971117 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 2848825615 ps |
| CPU time | 261.65 seconds |
| Started | Mar 07 01:40:34 PM PST 24 |
| Finished | Mar 07 01:44:56 PM PST 24 |
| Peak memory | 211476 kb |
| Host | smart-f0594bf3-6676-4081-a8d0-b5c99426f96f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2933971117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re set_error.2933971117 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.3504560193 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 508255691 ps |
| CPU time | 5.84 seconds |
| Started | Mar 07 01:40:34 PM PST 24 |
| Finished | Mar 07 01:40:40 PM PST 24 |
| Peak memory | 204176 kb |
| Host | smart-f2c00ec7-0343-41a3-8435-35bdc07c9a53 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3504560193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3504560193 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3700425438 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1250610373 ps |
| CPU time | 36.56 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:38:03 PM PST 24 |
| Peak memory | 205496 kb |
| Host | smart-ab5e4662-d102-49f1-aad7-cb13255cf584 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3700425438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3700425438 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3230321348 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 45729982360 ps |
| CPU time | 347.67 seconds |
| Started | Mar 07 01:37:35 PM PST 24 |
| Finished | Mar 07 01:43:23 PM PST 24 |
| Peak memory | 211268 kb |
| Host | smart-fc68643b-13c9-46e3-8a76-1d1b5f3eb59d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3230321348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo w_rsp.3230321348 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.98245458 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 613948650 ps |
| CPU time | 23.8 seconds |
| Started | Mar 07 01:37:35 PM PST 24 |
| Finished | Mar 07 01:37:59 PM PST 24 |
| Peak memory | 203344 kb |
| Host | smart-900fa779-ad48-48dd-8859-142edece9895 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=98245458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.98245458 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_error_random.4221236928 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1054690721 ps |
| CPU time | 32.64 seconds |
| Started | Mar 07 01:37:30 PM PST 24 |
| Finished | Mar 07 01:38:03 PM PST 24 |
| Peak memory | 203040 kb |
| Host | smart-700366cf-12b3-4ccf-b5b1-f69f40fa763a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4221236928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.4221236928 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random.2015185647 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 72151254 ps |
| CPU time | 9.05 seconds |
| Started | Mar 07 01:37:32 PM PST 24 |
| Finished | Mar 07 01:37:41 PM PST 24 |
| Peak memory | 204008 kb |
| Host | smart-fd2fd2c0-e8eb-4818-9be6-494a2b11f98b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2015185647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2015185647 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.908524958 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 27990614804 ps |
| CPU time | 201 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:40:49 PM PST 24 |
| Peak memory | 211396 kb |
| Host | smart-1b291427-e162-46d4-aacd-dc204a97dab2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=908524958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.908524958 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.4128545418 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 23058156882 ps |
| CPU time | 74.33 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:38:41 PM PST 24 |
| Peak memory | 204352 kb |
| Host | smart-b17a6686-4286-4d83-9b89-f3c12776636f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4128545418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4128545418 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.3931504316 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 214882913 ps |
| CPU time | 9.63 seconds |
| Started | Mar 07 01:37:29 PM PST 24 |
| Finished | Mar 07 01:37:39 PM PST 24 |
| Peak memory | 204168 kb |
| Host | smart-32c4a050-64d1-497e-b5d8-4fe37e39ddf7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931504316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3931504316 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_same_source.1418557903 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1521201755 ps |
| CPU time | 27.94 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:37:56 PM PST 24 |
| Peak memory | 203568 kb |
| Host | smart-45d48cc4-d16f-4317-a947-c35f7df6dac7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1418557903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1418557903 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke.3706396999 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 205675152 ps |
| CPU time | 3.38 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:37:31 PM PST 24 |
| Peak memory | 203172 kb |
| Host | smart-ffa798ea-64b3-4572-9390-dd6a601daa0e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3706396999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3706396999 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.3461254735 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 9501607081 ps |
| CPU time | 28.78 seconds |
| Started | Mar 07 01:37:32 PM PST 24 |
| Finished | Mar 07 01:38:01 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-46a8b470-25bd-4bbd-92cb-b3927c916d0f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461254735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3461254735 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1749479588 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 6757504694 ps |
| CPU time | 33.29 seconds |
| Started | Mar 07 01:37:25 PM PST 24 |
| Finished | Mar 07 01:37:59 PM PST 24 |
| Peak memory | 203248 kb |
| Host | smart-d37f8c59-9852-4dcd-92c1-8b75b92daf15 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1749479588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1749479588 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.513370031 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 63503453 ps |
| CPU time | 2.5 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:37:31 PM PST 24 |
| Peak memory | 203220 kb |
| Host | smart-68d83f61-3a7f-485d-8a16-75ea557f8d90 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513370031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.513370031 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all.942557279 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1606715402 ps |
| CPU time | 147.23 seconds |
| Started | Mar 07 01:37:35 PM PST 24 |
| Finished | Mar 07 01:40:03 PM PST 24 |
| Peak memory | 206476 kb |
| Host | smart-c0521d10-c8ea-489b-a2de-f6cfd3ff4e92 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=942557279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.942557279 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.334925818 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 5526860876 ps |
| CPU time | 178.21 seconds |
| Started | Mar 07 01:37:31 PM PST 24 |
| Finished | Mar 07 01:40:30 PM PST 24 |
| Peak memory | 206400 kb |
| Host | smart-3185258b-f491-457a-9dfc-1050a5a22b64 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=334925818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.334925818 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.70943807 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 324647897 ps |
| CPU time | 72.47 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:38:47 PM PST 24 |
| Peak memory | 208240 kb |
| Host | smart-d718cc3d-12f6-434b-8714-0e36b4d7d9e6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=70943807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset _error.70943807 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.742716890 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 153304967 ps |
| CPU time | 21.29 seconds |
| Started | Mar 07 01:37:35 PM PST 24 |
| Finished | Mar 07 01:37:57 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-7c139361-f3bd-4571-8528-99019dc004e0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=742716890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.742716890 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.4061885048 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 990873728 ps |
| CPU time | 23.67 seconds |
| Started | Mar 07 01:37:35 PM PST 24 |
| Finished | Mar 07 01:37:59 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-03c7252d-4c37-41ab-87c1-5a0b9643c496 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4061885048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.4061885048 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.160809632 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 76755594727 ps |
| CPU time | 354.24 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:43:29 PM PST 24 |
| Peak memory | 205604 kb |
| Host | smart-0cc776cf-1b53-402b-8087-10dfcc1d15c5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=160809632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow _rsp.160809632 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.3296182728 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 28710413 ps |
| CPU time | 3.75 seconds |
| Started | Mar 07 01:37:32 PM PST 24 |
| Finished | Mar 07 01:37:36 PM PST 24 |
| Peak memory | 203020 kb |
| Host | smart-ea525fcc-5180-48ac-86f6-b63b55487d2a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3296182728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3296182728 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_error_random.935934113 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 184680445 ps |
| CPU time | 21.69 seconds |
| Started | Mar 07 01:37:32 PM PST 24 |
| Finished | Mar 07 01:37:54 PM PST 24 |
| Peak memory | 203020 kb |
| Host | smart-0ee4b0f5-c68c-462d-b86a-2d1879baf6d4 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=935934113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.935934113 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random.1077672881 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 122504473 ps |
| CPU time | 12.33 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:37:52 PM PST 24 |
| Peak memory | 203920 kb |
| Host | smart-3b4444b2-e47d-4d9e-98a0-b403c2badf72 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1077672881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1077672881 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.550721187 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 14493574877 ps |
| CPU time | 45.49 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:38:25 PM PST 24 |
| Peak memory | 204304 kb |
| Host | smart-222b915d-34ea-4c94-8d81-f3c1100a7d93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=550721187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.550721187 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3796463500 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 89760402143 ps |
| CPU time | 254.7 seconds |
| Started | Mar 07 01:37:39 PM PST 24 |
| Finished | Mar 07 01:41:54 PM PST 24 |
| Peak memory | 211408 kb |
| Host | smart-052beb3f-f92a-4f30-a369-53e6581c95d3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3796463500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3796463500 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.2608458913 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 363143019 ps |
| CPU time | 27.93 seconds |
| Started | Mar 07 01:37:37 PM PST 24 |
| Finished | Mar 07 01:38:05 PM PST 24 |
| Peak memory | 211332 kb |
| Host | smart-3b0d5f90-ef80-4157-af69-e3ac3bf335ab |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608458913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2608458913 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_same_source.1941072651 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1920965409 ps |
| CPU time | 35.68 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:38:03 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-5488fd34-b69f-4a01-83b4-f571be6a8527 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1941072651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1941072651 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke.1592708007 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 125010874 ps |
| CPU time | 3.57 seconds |
| Started | Mar 07 01:37:36 PM PST 24 |
| Finished | Mar 07 01:37:40 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-6323da2a-eb46-4176-aac1-f95d469c0cd5 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1592708007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1592708007 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.1437401108 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 5858434112 ps |
| CPU time | 35.69 seconds |
| Started | Mar 07 01:37:37 PM PST 24 |
| Finished | Mar 07 01:38:13 PM PST 24 |
| Peak memory | 203200 kb |
| Host | smart-e9f5a1f6-2064-4f8a-ba51-8c1c3f3cef22 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437401108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1437401108 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2719612144 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 4500671386 ps |
| CPU time | 24.36 seconds |
| Started | Mar 07 01:37:37 PM PST 24 |
| Finished | Mar 07 01:38:02 PM PST 24 |
| Peak memory | 203208 kb |
| Host | smart-85e210d5-7ef8-4af7-ab99-3535890ca9f6 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2719612144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2719612144 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2444829186 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 29330884 ps |
| CPU time | 2.45 seconds |
| Started | Mar 07 01:37:36 PM PST 24 |
| Finished | Mar 07 01:37:39 PM PST 24 |
| Peak memory | 203132 kb |
| Host | smart-a3636599-f8eb-4ef3-8433-ea2d95af4b78 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444829186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2444829186 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all.1062957800 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 718101360 ps |
| CPU time | 53.24 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:38:20 PM PST 24 |
| Peak memory | 205512 kb |
| Host | smart-dd2a53e5-42a0-41a3-90d5-1224032cbeb9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1062957800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1062957800 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.425557533 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1394704344 ps |
| CPU time | 68.99 seconds |
| Started | Mar 07 01:37:35 PM PST 24 |
| Finished | Mar 07 01:38:45 PM PST 24 |
| Peak memory | 205284 kb |
| Host | smart-50efa88c-1ef7-4ac1-ba28-fd19b4d694be |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=425557533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.425557533 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.2840531671 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3511227659 ps |
| CPU time | 277.77 seconds |
| Started | Mar 07 01:37:35 PM PST 24 |
| Finished | Mar 07 01:42:13 PM PST 24 |
| Peak memory | 208684 kb |
| Host | smart-73204170-6aba-489e-960a-7ed8800bdc35 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2840531671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand _reset.2840531671 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2510273582 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2382972917 ps |
| CPU time | 347.96 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:43:16 PM PST 24 |
| Peak memory | 219592 kb |
| Host | smart-e3e65c57-50cd-4e5a-af94-674dd8f3172c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2510273582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res et_error.2510273582 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.42334706 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 117144707 ps |
| CPU time | 12.31 seconds |
| Started | Mar 07 01:37:30 PM PST 24 |
| Finished | Mar 07 01:37:42 PM PST 24 |
| Peak memory | 204616 kb |
| Host | smart-e0a00919-f05a-4f51-8834-3e49721a3e1d |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=42334706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.42334706 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.1533533168 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2182659224 ps |
| CPU time | 54.49 seconds |
| Started | Mar 07 01:37:30 PM PST 24 |
| Finished | Mar 07 01:38:25 PM PST 24 |
| Peak memory | 204936 kb |
| Host | smart-a3e89199-4382-4158-96f0-fe4370df37ef |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1533533168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1533533168 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2249844486 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 86918974777 ps |
| CPU time | 167.32 seconds |
| Started | Mar 07 01:37:36 PM PST 24 |
| Finished | Mar 07 01:40:24 PM PST 24 |
| Peak memory | 205640 kb |
| Host | smart-60a451ab-e754-4af4-bc41-0d7c5bc97871 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2249844486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo w_rsp.2249844486 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2253014118 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 891492817 ps |
| CPU time | 21.17 seconds |
| Started | Mar 07 01:37:31 PM PST 24 |
| Finished | Mar 07 01:37:53 PM PST 24 |
| Peak memory | 203080 kb |
| Host | smart-e3b84d68-d690-458d-9143-7c968d688759 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2253014118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2253014118 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_error_random.2639333504 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 196471653 ps |
| CPU time | 21 seconds |
| Started | Mar 07 01:37:33 PM PST 24 |
| Finished | Mar 07 01:37:55 PM PST 24 |
| Peak memory | 203112 kb |
| Host | smart-39b87e0c-b8e4-4134-af99-e8cf5fbd849e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2639333504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2639333504 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random.1378461 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 705743166 ps |
| CPU time | 27.5 seconds |
| Started | Mar 07 01:37:25 PM PST 24 |
| Finished | Mar 07 01:37:53 PM PST 24 |
| Peak memory | 204476 kb |
| Host | smart-08a7bca1-1847-4f82-9dca-748ae73d72a8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1378461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1378461 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.1437522553 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 65132867284 ps |
| CPU time | 194.21 seconds |
| Started | Mar 07 01:37:33 PM PST 24 |
| Finished | Mar 07 01:40:47 PM PST 24 |
| Peak memory | 211400 kb |
| Host | smart-68fea44a-289a-41f4-bb00-035c52623c0c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437522553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1437522553 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2400289525 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 23060335608 ps |
| CPU time | 129.62 seconds |
| Started | Mar 07 01:37:36 PM PST 24 |
| Finished | Mar 07 01:39:46 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-9cea21df-1575-4d14-b4ec-4d91e85e9002 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2400289525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2400289525 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.3863536542 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 68734719 ps |
| CPU time | 7.71 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:37:34 PM PST 24 |
| Peak memory | 204124 kb |
| Host | smart-1e8db051-194b-4745-8b9c-a39807f9de93 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863536542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3863536542 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_same_source.1016441080 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 578096783 ps |
| CPU time | 9.34 seconds |
| Started | Mar 07 01:37:36 PM PST 24 |
| Finished | Mar 07 01:37:46 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-a09f1917-cf06-4d00-a743-8d8d6afd4fa1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1016441080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1016441080 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke.1399246754 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 127968788 ps |
| CPU time | 2.55 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:37:30 PM PST 24 |
| Peak memory | 203120 kb |
| Host | smart-58490b8a-2638-4ea5-8369-fbd15d56b1e9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1399246754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1399246754 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3474564825 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 7129994906 ps |
| CPU time | 35.39 seconds |
| Started | Mar 07 01:37:24 PM PST 24 |
| Finished | Mar 07 01:38:01 PM PST 24 |
| Peak memory | 203156 kb |
| Host | smart-66bfcedd-5c2d-41a8-90d3-ade2216ef9dd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474564825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3474564825 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2063720182 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3330190827 ps |
| CPU time | 30.78 seconds |
| Started | Mar 07 01:37:30 PM PST 24 |
| Finished | Mar 07 01:38:01 PM PST 24 |
| Peak memory | 203144 kb |
| Host | smart-e8ebde09-a545-4d00-ba4e-93617779e6d8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2063720182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2063720182 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.3954245317 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 53889144 ps |
| CPU time | 2.63 seconds |
| Started | Mar 07 01:37:26 PM PST 24 |
| Finished | Mar 07 01:37:28 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-eb4b4b20-bb9a-43d2-9008-d62d99880abd |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954245317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3954245317 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all.2783513644 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1412095425 ps |
| CPU time | 145.1 seconds |
| Started | Mar 07 01:37:31 PM PST 24 |
| Finished | Mar 07 01:39:56 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-fa06bee1-c4d3-4195-9396-693b91424dd7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2783513644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2783513644 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3136456674 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 7648691240 ps |
| CPU time | 143.35 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:39:52 PM PST 24 |
| Peak memory | 207204 kb |
| Host | smart-4cced076-85c4-448a-aeef-8e55dad0588f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3136456674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3136456674 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1961421335 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1458983402 ps |
| CPU time | 94.67 seconds |
| Started | Mar 07 01:37:33 PM PST 24 |
| Finished | Mar 07 01:39:08 PM PST 24 |
| Peak memory | 211176 kb |
| Host | smart-6048ee10-db08-4813-83d1-b54f1b351165 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1961421335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand _reset.1961421335 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.253998221 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 287676018 ps |
| CPU time | 50.41 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:38:24 PM PST 24 |
| Peak memory | 206416 kb |
| Host | smart-1a6b88e6-5939-43d9-84d0-3d53e921a240 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=253998221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rese t_error.253998221 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.660234665 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 62595381 ps |
| CPU time | 9.14 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:37:44 PM PST 24 |
| Peak memory | 204432 kb |
| Host | smart-648403e5-c817-42be-a790-96557446089c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=660234665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.660234665 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.1152538892 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 126054302 ps |
| CPU time | 10.25 seconds |
| Started | Mar 07 01:37:37 PM PST 24 |
| Finished | Mar 07 01:37:48 PM PST 24 |
| Peak memory | 203620 kb |
| Host | smart-db3680f2-5fe2-422e-9503-a922c2a76d05 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1152538892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1152538892 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2013281849 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 7943432348 ps |
| CPU time | 71.98 seconds |
| Started | Mar 07 01:37:27 PM PST 24 |
| Finished | Mar 07 01:38:39 PM PST 24 |
| Peak memory | 204924 kb |
| Host | smart-fb6bc4fc-3e50-4e26-acb6-b1404e1f2a66 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2013281849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo w_rsp.2013281849 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.869138082 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 58813527 ps |
| CPU time | 9.68 seconds |
| Started | Mar 07 01:37:31 PM PST 24 |
| Finished | Mar 07 01:37:41 PM PST 24 |
| Peak memory | 203136 kb |
| Host | smart-8fb6604c-c5c9-4974-857d-f5afd22908bf |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=869138082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.869138082 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_error_random.2123845581 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1971224179 ps |
| CPU time | 21.3 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:37:59 PM PST 24 |
| Peak memory | 203092 kb |
| Host | smart-f48eb10e-f590-4b49-a6a4-9a5bd6ff7b6a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2123845581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2123845581 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random.1504235361 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 260770765 ps |
| CPU time | 18.33 seconds |
| Started | Mar 07 01:37:36 PM PST 24 |
| Finished | Mar 07 01:37:55 PM PST 24 |
| Peak memory | 211332 kb |
| Host | smart-38cae9fb-0c75-4832-874e-db507ac9078e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1504235361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1504235361 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.1804379213 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 15973168307 ps |
| CPU time | 40.56 seconds |
| Started | Mar 07 01:37:33 PM PST 24 |
| Finished | Mar 07 01:38:14 PM PST 24 |
| Peak memory | 204300 kb |
| Host | smart-de162bf9-d131-4096-808f-89eff07ed595 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804379213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1804379213 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2424750842 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 76037500566 ps |
| CPU time | 225.48 seconds |
| Started | Mar 07 01:37:37 PM PST 24 |
| Finished | Mar 07 01:41:23 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-5772639e-e664-4010-92db-78ade543ae47 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2424750842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2424750842 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.790644291 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 207399805 ps |
| CPU time | 17.62 seconds |
| Started | Mar 07 01:37:31 PM PST 24 |
| Finished | Mar 07 01:37:49 PM PST 24 |
| Peak memory | 204108 kb |
| Host | smart-a545178c-9146-40a0-89d5-5f4e97a5808c |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790644291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.790644291 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_same_source.1447544114 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1706686117 ps |
| CPU time | 34.22 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:38:09 PM PST 24 |
| Peak memory | 203200 kb |
| Host | smart-173126a6-ea00-4947-bf50-00b1f053b2b0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1447544114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1447544114 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke.514002790 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 462478765 ps |
| CPU time | 3.95 seconds |
| Started | Mar 07 01:37:31 PM PST 24 |
| Finished | Mar 07 01:37:35 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-dd45c616-60e7-4d77-830f-712082e4b835 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=514002790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.514002790 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3984088836 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 10159944336 ps |
| CPU time | 41.08 seconds |
| Started | Mar 07 01:37:35 PM PST 24 |
| Finished | Mar 07 01:38:17 PM PST 24 |
| Peak memory | 203068 kb |
| Host | smart-e04f70ba-8973-4587-b946-a420fed12838 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984088836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3984088836 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1845256934 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 8778595827 ps |
| CPU time | 32.66 seconds |
| Started | Mar 07 01:37:30 PM PST 24 |
| Finished | Mar 07 01:38:03 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-e74b1a43-85e5-4e04-af93-61c86b50af1a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1845256934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1845256934 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2617970937 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 53679129 ps |
| CPU time | 2.21 seconds |
| Started | Mar 07 01:37:31 PM PST 24 |
| Finished | Mar 07 01:37:34 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-cc8c5ea1-6e9b-4fe0-b954-5b96fd7f80f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617970937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2617970937 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all.909662966 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1342478268 ps |
| CPU time | 126.48 seconds |
| Started | Mar 07 01:37:35 PM PST 24 |
| Finished | Mar 07 01:39:42 PM PST 24 |
| Peak memory | 206860 kb |
| Host | smart-a9ccbf10-be76-4ee1-b2f8-6fe64af179f9 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=909662966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.909662966 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3769504236 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1933559742 ps |
| CPU time | 42.82 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:38:18 PM PST 24 |
| Peak memory | 203060 kb |
| Host | smart-b67ddb78-8661-4783-805e-471cedc0582b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3769504236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3769504236 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3706451873 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 7799019650 ps |
| CPU time | 98.31 seconds |
| Started | Mar 07 01:37:28 PM PST 24 |
| Finished | Mar 07 01:39:06 PM PST 24 |
| Peak memory | 207816 kb |
| Host | smart-0598db5f-82c4-4d3f-b9eb-bddf3957afa7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3706451873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand _reset.3706451873 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3422235617 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1771153547 ps |
| CPU time | 147.6 seconds |
| Started | Mar 07 01:37:33 PM PST 24 |
| Finished | Mar 07 01:40:01 PM PST 24 |
| Peak memory | 209760 kb |
| Host | smart-00c83dcf-f64f-4499-9a91-924b204741cb |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3422235617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res et_error.3422235617 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.265780228 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 59799143 ps |
| CPU time | 2.39 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:37:36 PM PST 24 |
| Peak memory | 203016 kb |
| Host | smart-d6545390-3eb5-4647-b305-cea6bcce399b |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=265780228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.265780228 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3769374729 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1795835479 ps |
| CPU time | 67.46 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:38:45 PM PST 24 |
| Peak memory | 206524 kb |
| Host | smart-6e4a401a-fd43-456d-bf91-c6bcec75a9b7 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3769374729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3769374729 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2625361730 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 56416510917 ps |
| CPU time | 512.98 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:46:11 PM PST 24 |
| Peak memory | 211300 kb |
| Host | smart-b1caeef5-e2f5-4a01-9fbc-115e4738e2c0 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2625361730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slo w_rsp.2625361730 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.981509114 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 323336681 ps |
| CPU time | 11.55 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:37:50 PM PST 24 |
| Peak memory | 203196 kb |
| Host | smart-43b88b36-fcf2-4872-99fd-d3101d71d25a |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=981509114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.981509114 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_error_random.647111980 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 25964213 ps |
| CPU time | 2.96 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:37:38 PM PST 24 |
| Peak memory | 203204 kb |
| Host | smart-975efc6c-1aba-4244-b352-9432201596f8 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=647111980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.647111980 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random.3014252159 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 622895629 ps |
| CPU time | 22.57 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:37:57 PM PST 24 |
| Peak memory | 204164 kb |
| Host | smart-ceeae435-5004-4d37-8315-a60c48eb8d5e |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3014252159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3014252159 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.2602132611 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 56515342550 ps |
| CPU time | 132.77 seconds |
| Started | Mar 07 01:37:33 PM PST 24 |
| Finished | Mar 07 01:39:46 PM PST 24 |
| Peak memory | 211280 kb |
| Host | smart-9ea6c92c-7831-49a4-841d-066eb2930030 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602132611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2602132611 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.4227271093 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 30909511450 ps |
| CPU time | 247.59 seconds |
| Started | Mar 07 01:37:32 PM PST 24 |
| Finished | Mar 07 01:41:40 PM PST 24 |
| Peak memory | 204360 kb |
| Host | smart-f672678c-c67d-4e4b-b0ff-5ffa761d1dc3 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4227271093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.4227271093 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.2331691873 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 109638840 ps |
| CPU time | 13.26 seconds |
| Started | Mar 07 01:37:40 PM PST 24 |
| Finished | Mar 07 01:37:53 PM PST 24 |
| Peak memory | 204208 kb |
| Host | smart-ad53f3af-43a9-4acb-9626-d777fee6510f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331691873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2331691873 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_same_source.2629832401 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 250410347 ps |
| CPU time | 15.82 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:37:54 PM PST 24 |
| Peak memory | 203100 kb |
| Host | smart-f2b27b97-02c7-4ff8-b5a3-f2f631895416 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2629832401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2629832401 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke.1827820690 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 101655299 ps |
| CPU time | 2.68 seconds |
| Started | Mar 07 01:37:35 PM PST 24 |
| Finished | Mar 07 01:37:38 PM PST 24 |
| Peak memory | 203192 kb |
| Host | smart-e424dfe4-2965-42b9-affa-f2ece9133448 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1827820690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1827820690 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.949411744 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 5902747030 ps |
| CPU time | 35.52 seconds |
| Started | Mar 07 01:37:38 PM PST 24 |
| Finished | Mar 07 01:38:13 PM PST 24 |
| Peak memory | 203212 kb |
| Host | smart-be4f5ec9-cebc-487b-b8f1-0b8abb1b0009 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=949411744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.949411744 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1717372185 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4055454038 ps |
| CPU time | 23.87 seconds |
| Started | Mar 07 01:37:36 PM PST 24 |
| Finished | Mar 07 01:38:00 PM PST 24 |
| Peak memory | 203196 kb |
| Host | smart-dc661cc0-e379-444f-b773-be0b35d6cb8f |
| User | root |
| Command | /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1717372185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1717372185 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.4034721133 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 36950771 ps |
| CPU time | 2.12 seconds |
| Started | Mar 07 01:37:36 PM PST 24 |
| Finished | Mar 07 01:37:38 PM PST 24 |
| Peak memory | 203148 kb |
| Host | smart-94e39e14-c4d2-4024-8d64-2c6a4594b496 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034721133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.4034721133 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all.1037140565 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 856854665 ps |
| CPU time | 130.9 seconds |
| Started | Mar 07 01:37:30 PM PST 24 |
| Finished | Mar 07 01:39:41 PM PST 24 |
| Peak memory | 209616 kb |
| Host | smart-809e6510-55f2-4896-ba78-0645c15e80e2 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1037140565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1037140565 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.775022487 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2145952861 ps |
| CPU time | 75.79 seconds |
| Started | Mar 07 01:37:34 PM PST 24 |
| Finished | Mar 07 01:38:51 PM PST 24 |
| Peak memory | 206376 kb |
| Host | smart-20000328-05cf-4330-a04e-ae2dd4945714 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=775022487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.775022487 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3482065533 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1292112168 ps |
| CPU time | 179.55 seconds |
| Started | Mar 07 01:37:33 PM PST 24 |
| Finished | Mar 07 01:40:33 PM PST 24 |
| Peak memory | 209032 kb |
| Host | smart-8a24c39a-696f-44a5-9b1d-0d9965482339 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3482065533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand _reset.3482065533 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2945952660 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 4322153334 ps |
| CPU time | 109.38 seconds |
| Started | Mar 07 01:37:42 PM PST 24 |
| Finished | Mar 07 01:39:33 PM PST 24 |
| Peak memory | 208296 kb |
| Host | smart-d88fb1d8-e27f-4ab3-b271-71c8c097c6f1 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2945952660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_res et_error.2945952660 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1412092985 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 334999094 ps |
| CPU time | 14.28 seconds |
| Started | Mar 07 01:37:37 PM PST 24 |
| Finished | Mar 07 01:37:52 PM PST 24 |
| Peak memory | 204664 kb |
| Host | smart-8223bf81-a372-480f-8128-a6bc9add7605 |
| User | root |
| Command | /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1412092985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1412092985 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
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