Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1926	1			T2	4		T4	4		T6	16
all_values[1]	1888	1			T2	1		T4	6		T6	22
all_values[2]	1902	1			T2	2		T4	3		T6	20
all_values[3]	1848	1			T2	5		T4	6		T6	15
all_values[4]	1900	1			T2	3		T4	6		T6	28
all_values[5]	1853	1			T2	2		T4	5		T6	22
all_values[6]	1808	1			T2	5		T4	8		T6	21
all_values[7]	1889	1			T2	6		T4	6		T6	19
all_values[8]	1873	1			T2	2		T4	5		T6	12
all_values[9]	1857	1			T2	3		T4	3		T6	23
all_values[10]	1854	1			T2	1		T4	5		T6	13
all_values[11]	1891	1			T2	5		T4	4		T6	22
all_values[12]	1890	1			T2	2		T4	3		T6	23
all_values[13]	1894	1			T2	2		T4	5		T6	18
all_values[14]	1877	1			T2	4		T4	6		T6	25
all_values[15]	1836	1			T4	7		T6	20		T40	4
all_values[16]	1913	1			T2	1		T4	5		T6	22
all_values[17]	1913	1			T2	3		T4	7		T6	21
all_values[18]	1884	1			T2	7		T4	4		T6	17
all_values[19]	1870	1			T2	5		T4	2		T6	19
all_values[20]	1829	1			T2	4		T4	4		T6	25
all_values[21]	1860	1			T2	2		T4	1		T6	29
all_values[22]	1937	1			T2	1		T4	6		T6	23
all_values[23]	1807	1			T2	3		T4	8		T6	22
all_values[24]	1874	1			T2	3		T4	7		T6	18
all_values[25]	1885	1			T2	4		T4	4		T6	20
all_values[26]	1800	1			T2	3		T4	8		T6	27
all_values[27]	1891	1			T2	1		T4	3		T6	15
all_values[28]	1860	1			T2	6		T4	5		T6	22
all_values[29]	1878	1			T4	5		T6	19		T40	2
all_values[30]	1849	1			T2	4		T4	1		T6	25
all_values[31]	1867	1			T4	4		T6	17		T11	2
all_values[32]	1875	1			T2	1		T4	4		T6	17
all_values[33]	1843	1			T2	5		T4	3		T6	17
all_values[34]	1919	1			T2	2		T4	8		T6	19
all_values[35]	1848	1			T2	3		T4	3		T6	18
all_values[36]	1868	1			T2	6		T4	3		T6	18
all_values[37]	1852	1			T2	1		T4	6		T6	21
all_values[38]	1874	1			T2	1		T4	7		T6	20
all_values[39]	1908	1			T2	2		T4	3		T6	23
all_values[40]	1873	1			T2	2		T4	2		T6	21
all_values[41]	1959	1			T4	6		T6	22		T11	4
all_values[42]	1746	1			T2	2		T4	7		T6	27
all_values[43]	1840	1			T2	2		T4	4		T6	21
all_values[44]	1833	1			T2	3		T4	7		T6	25
all_values[45]	1918	1			T4	9		T6	23		T11	1
all_values[46]	1914	1			T2	4		T4	6		T6	17
all_values[47]	1894	1			T2	4		T4	3		T6	34
all_values[48]	1880	1			T2	4		T4	1		T6	14
all_values[49]	1917	1			T2	3		T4	6		T6	20
all_values[50]	1873	1			T2	4		T4	7		T6	15
all_values[51]	1920	1			T2	4		T4	3		T6	21
all_values[52]	1850	1			T2	3		T4	2		T6	20
all_values[53]	1924	1			T2	2		T4	6		T6	21
all_values[54]	1890	1			T2	4		T4	3		T6	26
all_values[55]	1845	1			T2	6		T4	3		T6	21
all_values[56]	1844	1			T2	4		T4	4		T6	15
all_values[57]	1900	1			T2	2		T4	6		T6	22
all_values[58]	1930	1			T2	1		T4	6		T6	16
all_values[59]	1908	1			T2	3		T4	6		T6	21
all_values[60]	1810	1			T2	4		T4	10		T6	15
all_values[61]	1844	1			T2	1		T4	6		T6	20
all_values[62]	1855	1			T4	4		T6	20		T11	2
all_values[63]	1888	1			T2	4		T4	8		T6	24