Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=23}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 24 0 24 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 24 0 24 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 462 1 T1 1 T4 1 T6 2
all_values[1] 526 1 T1 1 T6 3 T41 1
all_values[2] 491 1 T1 1 T4 1 T6 3
all_values[3] 533 1 T6 4 T16 1 T25 5
all_values[4] 543 1 T4 1 T6 3 T25 11
all_values[5] 490 1 T4 1 T25 3 T26 2
all_values[6] 510 1 T1 1 T6 3 T25 4
all_values[7] 492 1 T1 2 T6 4 T25 5
all_values[8] 477 1 T1 1 T4 1 T6 1
all_values[9] 477 1 T1 2 T4 2 T6 4
all_values[10] 511 1 T6 2 T25 7 T26 1
all_values[11] 490 1 T6 1 T25 5 T31 1
all_values[12] 526 1 T6 1 T25 8 T26 1
all_values[13] 475 1 T4 1 T6 3 T25 5
all_values[14] 538 1 T1 1 T4 2 T6 1
all_values[15] 560 1 T4 1 T6 5 T25 9
all_values[16] 470 1 T6 2 T25 2 T26 1
all_values[17] 499 1 T6 2 T25 3 T26 1
all_values[18] 522 1 T6 3 T16 1 T25 4
all_values[19] 523 1 T4 1 T6 4 T41 1
all_values[20] 515 1 T6 2 T25 5 T26 1
all_values[21] 507 1 T1 1 T16 1 T25 5
all_values[22] 511 1 T1 2 T6 1 T25 7
all_values[23] 483 1 T1 3 T6 2 T25 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%