Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1802	1			T3	4		T6	11		T20	3
all_values[1]	1860	1			T3	1		T4	5		T6	7
all_values[2]	1802	1			T3	1		T4	5		T6	7
all_values[3]	1712	1			T3	3		T4	3		T6	10
all_values[4]	1798	1			T4	1		T6	15		T20	1
all_values[5]	1773	1			T3	3		T4	1		T6	8
all_values[6]	1754	1			T3	2		T4	4		T6	11
all_values[7]	1825	1			T3	1		T4	2		T6	10
all_values[8]	1737	1			T3	2		T4	2		T6	9
all_values[9]	1880	1			T3	1		T4	4		T6	10
all_values[10]	1836	1			T3	2		T4	2		T6	7
all_values[11]	1791	1			T4	2		T6	9		T20	2
all_values[12]	1753	1			T3	1		T4	2		T6	4
all_values[13]	1850	1			T6	18		T20	2		T25	32
all_values[14]	1801	1			T4	5		T6	6		T20	3
all_values[15]	1803	1			T4	4		T6	8		T20	1
all_values[16]	1758	1			T4	6		T6	6		T20	5
all_values[17]	1752	1			T4	3		T6	8		T20	2
all_values[18]	1791	1			T3	2		T6	9		T20	3
all_values[19]	1857	1			T3	2		T4	1		T6	9
all_values[20]	1806	1			T4	3		T6	6		T20	2
all_values[21]	1770	1			T4	4		T6	9		T20	3
all_values[22]	1853	1			T3	3		T4	3		T6	13
all_values[23]	1737	1			T3	1		T6	9		T20	2
all_values[24]	1828	1			T3	1		T4	5		T6	10
all_values[25]	1748	1			T3	3		T4	7		T6	12
all_values[26]	1771	1			T4	3		T6	7		T20	1
all_values[27]	1839	1			T3	1		T4	3		T6	12
all_values[28]	1877	1			T4	2		T6	14		T20	3
all_values[29]	1895	1			T4	4		T6	6		T20	1
all_values[30]	1787	1			T4	2		T6	8		T20	2
all_values[31]	1806	1			T4	2		T6	4		T20	2
all_values[32]	1823	1			T4	3		T6	6		T20	2
all_values[33]	1778	1			T3	1		T4	1		T6	5
all_values[34]	1724	1			T3	1		T4	1		T6	12
all_values[35]	1697	1			T3	1		T4	3		T6	11
all_values[36]	1881	1			T3	3		T4	3		T6	12
all_values[37]	1824	1			T3	1		T4	7		T6	8
all_values[38]	1883	1			T4	2		T6	11		T20	3
all_values[39]	1811	1			T3	1		T4	2		T6	12
all_values[40]	1847	1			T3	2		T4	4		T6	9
all_values[41]	1744	1			T4	2		T6	6		T20	2
all_values[42]	1818	1			T4	1		T6	8		T20	1
all_values[43]	1725	1			T3	1		T4	3		T6	13
all_values[44]	1807	1			T3	2		T4	5		T6	8
all_values[45]	1850	1			T4	3		T6	10		T20	8
all_values[46]	1812	1			T3	1		T4	7		T6	8
all_values[47]	1814	1			T4	8		T6	11		T20	3
all_values[48]	1789	1			T4	2		T6	6		T20	4
all_values[49]	1738	1			T4	4		T6	10		T20	1
all_values[50]	1776	1			T3	1		T4	3		T6	9
all_values[51]	1833	1			T3	1		T4	5		T6	2
all_values[52]	1805	1			T4	1		T6	9		T20	1
all_values[53]	1783	1			T3	1		T4	4		T6	11
all_values[54]	1793	1			T3	2		T4	3		T6	10
all_values[55]	1800	1			T3	3		T4	1		T6	7
all_values[56]	1819	1			T3	1		T4	4		T6	7
all_values[57]	1814	1			T3	1		T4	2		T6	8
all_values[58]	1815	1			T3	1		T4	8		T6	8
all_values[59]	1793	1			T3	1		T4	4		T6	4
all_values[60]	1810	1			T3	1		T6	11		T20	2
all_values[61]	1793	1			T3	1		T4	2		T6	9
all_values[62]	1781	1			T3	1		T4	4		T6	12
all_values[63]	1827	1			T6	7		T20	3		T25	41