Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.20 99.26 90.07 98.80 95.82 99.26 100.00


Total test records in report: 900
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T760 /workspace/coverage/xbar_build_mode/29.xbar_same_source.3296680892 Mar 12 01:03:36 PM PDT 24 Mar 12 01:03:46 PM PDT 24 99772705 ps
T761 /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2006590299 Mar 12 01:02:57 PM PDT 24 Mar 12 01:03:11 PM PDT 24 108340381 ps
T762 /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.2555627572 Mar 12 01:02:58 PM PDT 24 Mar 12 01:03:03 PM PDT 24 113361621 ps
T763 /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2430912964 Mar 12 01:03:08 PM PDT 24 Mar 12 01:03:23 PM PDT 24 116292843 ps
T764 /workspace/coverage/xbar_build_mode/2.xbar_error_random.2822898389 Mar 12 01:02:20 PM PDT 24 Mar 12 01:02:48 PM PDT 24 2039046453 ps
T765 /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1074256046 Mar 12 01:02:38 PM PDT 24 Mar 12 01:02:44 PM PDT 24 136076047 ps
T766 /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1463991351 Mar 12 01:02:56 PM PDT 24 Mar 12 01:03:49 PM PDT 24 3763680909 ps
T767 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1745854572 Mar 12 01:02:31 PM PDT 24 Mar 12 01:03:16 PM PDT 24 69201939 ps
T768 /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.515554901 Mar 12 01:04:15 PM PDT 24 Mar 12 01:04:40 PM PDT 24 6970787509 ps
T769 /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2779135141 Mar 12 01:02:23 PM PDT 24 Mar 12 01:02:48 PM PDT 24 4970395468 ps
T770 /workspace/coverage/xbar_build_mode/6.xbar_smoke.910205963 Mar 12 01:02:30 PM PDT 24 Mar 12 01:02:34 PM PDT 24 142289833 ps
T771 /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2889163226 Mar 12 01:02:47 PM PDT 24 Mar 12 01:02:50 PM PDT 24 50220176 ps
T772 /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.424212944 Mar 12 01:02:01 PM PDT 24 Mar 12 01:02:12 PM PDT 24 223694600 ps
T773 /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2402129054 Mar 12 01:03:51 PM PDT 24 Mar 12 01:05:47 PM PDT 24 1606434212 ps
T774 /workspace/coverage/xbar_build_mode/27.xbar_error_random.3185831567 Mar 12 01:03:32 PM PDT 24 Mar 12 01:03:58 PM PDT 24 787367708 ps
T775 /workspace/coverage/xbar_build_mode/3.xbar_same_source.2817523782 Mar 12 01:02:31 PM PDT 24 Mar 12 01:02:55 PM PDT 24 1477025553 ps
T776 /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.4190309892 Mar 12 01:02:28 PM PDT 24 Mar 12 01:03:00 PM PDT 24 10903892538 ps
T777 /workspace/coverage/xbar_build_mode/37.xbar_error_random.654827380 Mar 12 01:03:57 PM PDT 24 Mar 12 01:04:01 PM PDT 24 59906825 ps
T778 /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1999847672 Mar 12 01:04:02 PM PDT 24 Mar 12 01:06:00 PM PDT 24 26720605634 ps
T779 /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3696096066 Mar 12 01:02:26 PM PDT 24 Mar 12 01:02:59 PM PDT 24 5740893179 ps
T780 /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2919506698 Mar 12 01:02:45 PM PDT 24 Mar 12 01:03:46 PM PDT 24 1864942300 ps
T781 /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2962051601 Mar 12 01:03:33 PM PDT 24 Mar 12 01:03:58 PM PDT 24 6396994362 ps
T782 /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3934167688 Mar 12 01:02:58 PM PDT 24 Mar 12 01:04:41 PM PDT 24 701909150 ps
T783 /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3549454629 Mar 12 01:03:07 PM PDT 24 Mar 12 01:07:53 PM PDT 24 13043649667 ps
T784 /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1048694236 Mar 12 01:02:59 PM PDT 24 Mar 12 01:03:22 PM PDT 24 4076832357 ps
T785 /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.303708924 Mar 12 01:04:05 PM PDT 24 Mar 12 01:04:15 PM PDT 24 82663777 ps
T786 /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.472938653 Mar 12 01:03:42 PM PDT 24 Mar 12 01:04:17 PM PDT 24 7136151721 ps
T787 /workspace/coverage/xbar_build_mode/22.xbar_error_random.4212136918 Mar 12 01:03:09 PM PDT 24 Mar 12 01:03:31 PM PDT 24 166910035 ps
T788 /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2161544746 Mar 12 01:03:32 PM PDT 24 Mar 12 01:05:38 PM PDT 24 41713870368 ps
T789 /workspace/coverage/xbar_build_mode/42.xbar_error_random.3677116864 Mar 12 01:04:05 PM PDT 24 Mar 12 01:04:12 PM PDT 24 501982211 ps
T790 /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2477266883 Mar 12 01:03:58 PM PDT 24 Mar 12 01:04:25 PM PDT 24 194282098 ps
T791 /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3072669937 Mar 12 01:03:08 PM PDT 24 Mar 12 01:03:17 PM PDT 24 308847493 ps
T792 /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3998866856 Mar 12 01:03:42 PM PDT 24 Mar 12 01:03:54 PM PDT 24 601846567 ps
T793 /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1918422912 Mar 12 01:02:36 PM PDT 24 Mar 12 01:03:09 PM PDT 24 3543754042 ps
T794 /workspace/coverage/xbar_build_mode/12.xbar_stress_all.4246765492 Mar 12 01:02:52 PM PDT 24 Mar 12 01:03:00 PM PDT 24 678732467 ps
T795 /workspace/coverage/xbar_build_mode/28.xbar_random.952143579 Mar 12 01:03:34 PM PDT 24 Mar 12 01:03:45 PM PDT 24 598597844 ps
T796 /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1607717975 Mar 12 01:03:36 PM PDT 24 Mar 12 01:10:02 PM PDT 24 86913264534 ps
T797 /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3472286759 Mar 12 01:04:43 PM PDT 24 Mar 12 01:06:42 PM PDT 24 42924250833 ps
T59 /workspace/coverage/xbar_build_mode/35.xbar_random.3301316113 Mar 12 01:03:46 PM PDT 24 Mar 12 01:04:07 PM PDT 24 509076287 ps
T798 /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1003264128 Mar 12 01:02:14 PM PDT 24 Mar 12 01:02:58 PM PDT 24 492547585 ps
T799 /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3086517337 Mar 12 01:04:12 PM PDT 24 Mar 12 01:04:32 PM PDT 24 7159165263 ps
T800 /workspace/coverage/xbar_build_mode/43.xbar_error_random.1724909836 Mar 12 01:04:22 PM PDT 24 Mar 12 01:04:26 PM PDT 24 68610882 ps
T801 /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2207063789 Mar 12 01:02:30 PM PDT 24 Mar 12 01:03:00 PM PDT 24 6364602430 ps
T802 /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3767417882 Mar 12 01:03:37 PM PDT 24 Mar 12 01:08:25 PM PDT 24 2278323332 ps
T803 /workspace/coverage/xbar_build_mode/24.xbar_same_source.3834342677 Mar 12 01:03:22 PM PDT 24 Mar 12 01:03:28 PM PDT 24 83562171 ps
T804 /workspace/coverage/xbar_build_mode/9.xbar_random.2759357058 Mar 12 01:02:39 PM PDT 24 Mar 12 01:02:53 PM PDT 24 1560539440 ps
T805 /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2136542043 Mar 12 01:03:30 PM PDT 24 Mar 12 01:13:16 PM PDT 24 87748720799 ps
T806 /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3146217643 Mar 12 01:02:47 PM PDT 24 Mar 12 01:03:12 PM PDT 24 527818124 ps
T807 /workspace/coverage/xbar_build_mode/39.xbar_same_source.3449171605 Mar 12 01:03:59 PM PDT 24 Mar 12 01:04:11 PM PDT 24 388291054 ps
T808 /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.635049786 Mar 12 01:03:34 PM PDT 24 Mar 12 01:04:54 PM PDT 24 7549201953 ps
T60 /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2314952499 Mar 12 01:03:46 PM PDT 24 Mar 12 01:08:36 PM PDT 24 79522989635 ps
T809 /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3948816500 Mar 12 01:04:24 PM PDT 24 Mar 12 01:05:04 PM PDT 24 10939019727 ps
T810 /workspace/coverage/xbar_build_mode/6.xbar_same_source.569133269 Mar 12 01:02:41 PM PDT 24 Mar 12 01:03:10 PM PDT 24 8165924607 ps
T811 /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.550994169 Mar 12 01:04:15 PM PDT 24 Mar 12 01:14:49 PM PDT 24 76959490159 ps
T812 /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2534636054 Mar 12 01:03:48 PM PDT 24 Mar 12 01:03:56 PM PDT 24 67813943 ps
T813 /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.103782940 Mar 12 01:02:48 PM PDT 24 Mar 12 01:03:01 PM PDT 24 392978443 ps
T814 /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2424027654 Mar 12 01:03:45 PM PDT 24 Mar 12 01:07:53 PM PDT 24 149657931731 ps
T815 /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2105864099 Mar 12 01:03:03 PM PDT 24 Mar 12 01:06:51 PM PDT 24 48870601540 ps
T816 /workspace/coverage/xbar_build_mode/1.xbar_smoke.1353608234 Mar 12 01:02:20 PM PDT 24 Mar 12 01:02:24 PM PDT 24 181296721 ps
T817 /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3994910547 Mar 12 01:04:10 PM PDT 24 Mar 12 01:04:43 PM PDT 24 13038743126 ps
T818 /workspace/coverage/xbar_build_mode/33.xbar_smoke.2128033651 Mar 12 01:03:46 PM PDT 24 Mar 12 01:03:49 PM PDT 24 28685085 ps
T819 /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2131704691 Mar 12 01:02:45 PM PDT 24 Mar 12 01:03:16 PM PDT 24 8685741110 ps
T820 /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1054474121 Mar 12 01:03:27 PM PDT 24 Mar 12 01:12:15 PM PDT 24 55107113809 ps
T821 /workspace/coverage/xbar_build_mode/17.xbar_same_source.1069501079 Mar 12 01:03:00 PM PDT 24 Mar 12 01:03:09 PM PDT 24 207590151 ps
T822 /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3856929818 Mar 12 01:03:30 PM PDT 24 Mar 12 01:03:34 PM PDT 24 35845415 ps
T823 /workspace/coverage/xbar_build_mode/1.xbar_same_source.3226474312 Mar 12 01:02:22 PM PDT 24 Mar 12 01:02:48 PM PDT 24 4006232662 ps
T824 /workspace/coverage/xbar_build_mode/42.xbar_same_source.2192176378 Mar 12 01:04:00 PM PDT 24 Mar 12 01:04:15 PM PDT 24 777432257 ps
T825 /workspace/coverage/xbar_build_mode/44.xbar_error_random.3329050969 Mar 12 01:04:15 PM PDT 24 Mar 12 01:04:25 PM PDT 24 196551944 ps
T826 /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3871173365 Mar 12 01:04:06 PM PDT 24 Mar 12 01:07:43 PM PDT 24 47088031325 ps
T827 /workspace/coverage/xbar_build_mode/30.xbar_error_random.25128946 Mar 12 01:03:34 PM PDT 24 Mar 12 01:03:47 PM PDT 24 447352810 ps
T828 /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1353675267 Mar 12 01:04:25 PM PDT 24 Mar 12 01:10:27 PM PDT 24 7574198965 ps
T829 /workspace/coverage/xbar_build_mode/48.xbar_error_random.3876730878 Mar 12 01:04:35 PM PDT 24 Mar 12 01:04:54 PM PDT 24 178559415 ps
T830 /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.880260937 Mar 12 01:02:27 PM PDT 24 Mar 12 01:11:17 PM PDT 24 64443920950 ps
T831 /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2158400827 Mar 12 01:03:23 PM PDT 24 Mar 12 01:07:26 PM PDT 24 98567505528 ps
T832 /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.769781089 Mar 12 01:02:22 PM PDT 24 Mar 12 01:02:54 PM PDT 24 5404737917 ps
T833 /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1102760921 Mar 12 01:02:49 PM PDT 24 Mar 12 01:02:57 PM PDT 24 122073040 ps
T834 /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.1103709780 Mar 12 01:03:03 PM PDT 24 Mar 12 01:03:19 PM PDT 24 221216765 ps
T38 /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2643065270 Mar 12 01:03:40 PM PDT 24 Mar 12 01:06:16 PM PDT 24 28797287567 ps
T835 /workspace/coverage/xbar_build_mode/12.xbar_error_random.1480026917 Mar 12 01:02:45 PM PDT 24 Mar 12 01:03:06 PM PDT 24 1175808991 ps
T836 /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3471435258 Mar 12 01:04:24 PM PDT 24 Mar 12 01:06:26 PM PDT 24 305002524 ps
T837 /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3585629940 Mar 12 01:02:29 PM PDT 24 Mar 12 01:02:59 PM PDT 24 1114587605 ps
T838 /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1339238122 Mar 12 01:02:27 PM PDT 24 Mar 12 01:17:49 PM PDT 24 417901757518 ps
T839 /workspace/coverage/xbar_build_mode/10.xbar_random.1509187756 Mar 12 01:02:42 PM PDT 24 Mar 12 01:02:58 PM PDT 24 151177326 ps
T840 /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.627323406 Mar 12 01:02:33 PM PDT 24 Mar 12 01:06:26 PM PDT 24 10226743436 ps
T841 /workspace/coverage/xbar_build_mode/40.xbar_smoke.2814679149 Mar 12 01:04:04 PM PDT 24 Mar 12 01:04:08 PM PDT 24 65660476 ps
T842 /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1934060504 Mar 12 01:03:08 PM PDT 24 Mar 12 01:03:41 PM PDT 24 7621537557 ps
T843 /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1031119047 Mar 12 01:04:03 PM PDT 24 Mar 12 01:04:16 PM PDT 24 298457030 ps
T844 /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.4108459749 Mar 12 01:03:39 PM PDT 24 Mar 12 01:03:41 PM PDT 24 48366764 ps
T845 /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1198494146 Mar 12 01:03:23 PM PDT 24 Mar 12 01:03:51 PM PDT 24 4866140328 ps
T846 /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2164033489 Mar 12 01:02:47 PM PDT 24 Mar 12 01:03:10 PM PDT 24 3522605958 ps
T240 /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3300624823 Mar 12 01:02:39 PM PDT 24 Mar 12 01:04:27 PM PDT 24 35708155551 ps
T847 /workspace/coverage/xbar_build_mode/30.xbar_smoke.829497149 Mar 12 01:03:33 PM PDT 24 Mar 12 01:03:36 PM PDT 24 243838358 ps
T848 /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1143018257 Mar 12 01:03:26 PM PDT 24 Mar 12 01:09:09 PM PDT 24 108571077150 ps
T849 /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2881087328 Mar 12 01:04:03 PM PDT 24 Mar 12 01:06:19 PM PDT 24 10091128395 ps
T850 /workspace/coverage/xbar_build_mode/41.xbar_smoke.2622075981 Mar 12 01:03:59 PM PDT 24 Mar 12 01:04:03 PM PDT 24 222171039 ps
T851 /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3617746697 Mar 12 01:02:15 PM PDT 24 Mar 12 01:02:25 PM PDT 24 372813971 ps
T852 /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2945198896 Mar 12 01:03:25 PM PDT 24 Mar 12 01:04:21 PM PDT 24 107672451 ps
T232 /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.4288655996 Mar 12 01:03:00 PM PDT 24 Mar 12 01:03:21 PM PDT 24 934394747 ps
T853 /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2135040801 Mar 12 01:04:05 PM PDT 24 Mar 12 01:08:10 PM PDT 24 2478074257 ps
T854 /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.4127281531 Mar 12 01:02:44 PM PDT 24 Mar 12 01:03:05 PM PDT 24 4589488610 ps
T855 /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2104465967 Mar 12 01:03:45 PM PDT 24 Mar 12 01:04:02 PM PDT 24 547402680 ps
T856 /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.570719696 Mar 12 01:04:03 PM PDT 24 Mar 12 01:04:09 PM PDT 24 475931580 ps
T857 /workspace/coverage/xbar_build_mode/15.xbar_same_source.1673847766 Mar 12 01:02:42 PM PDT 24 Mar 12 01:02:45 PM PDT 24 130187570 ps
T858 /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2665846663 Mar 12 01:04:01 PM PDT 24 Mar 12 01:04:31 PM PDT 24 3245329800 ps
T859 /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2980089567 Mar 12 01:02:49 PM PDT 24 Mar 12 01:02:52 PM PDT 24 98932047 ps
T860 /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1056348870 Mar 12 01:03:29 PM PDT 24 Mar 12 01:05:17 PM PDT 24 17738515605 ps
T861 /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.274115103 Mar 12 01:03:29 PM PDT 24 Mar 12 01:03:45 PM PDT 24 103395687 ps
T61 /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1145048116 Mar 12 01:02:34 PM PDT 24 Mar 12 01:06:22 PM PDT 24 91602059609 ps
T862 /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3502883452 Mar 12 01:02:31 PM PDT 24 Mar 12 01:03:13 PM PDT 24 414595844 ps
T863 /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1486482069 Mar 12 01:02:34 PM PDT 24 Mar 12 01:04:32 PM PDT 24 3267742160 ps
T864 /workspace/coverage/xbar_build_mode/42.xbar_smoke.1428979060 Mar 12 01:04:01 PM PDT 24 Mar 12 01:04:03 PM PDT 24 41164929 ps
T865 /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.93673413 Mar 12 01:02:47 PM PDT 24 Mar 12 01:02:55 PM PDT 24 169615983 ps
T162 /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4281553089 Mar 12 01:04:23 PM PDT 24 Mar 12 01:15:25 PM PDT 24 71414879740 ps
T866 /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.406708304 Mar 12 01:03:25 PM PDT 24 Mar 12 01:06:47 PM PDT 24 78584848885 ps
T867 /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2266543008 Mar 12 01:03:49 PM PDT 24 Mar 12 01:06:55 PM PDT 24 2864975653 ps
T868 /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.885417844 Mar 12 01:03:38 PM PDT 24 Mar 12 01:03:55 PM PDT 24 143896705 ps
T869 /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1882312799 Mar 12 01:04:12 PM PDT 24 Mar 12 01:04:15 PM PDT 24 41888759 ps
T870 /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.948610554 Mar 12 01:02:46 PM PDT 24 Mar 12 01:05:49 PM PDT 24 110448753674 ps
T871 /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3137259383 Mar 12 01:03:29 PM PDT 24 Mar 12 01:04:13 PM PDT 24 19490729073 ps
T872 /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.636908190 Mar 12 01:04:11 PM PDT 24 Mar 12 01:04:40 PM PDT 24 305835234 ps
T873 /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3455645940 Mar 12 01:03:01 PM PDT 24 Mar 12 01:03:41 PM PDT 24 12181909501 ps
T874 /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3127040198 Mar 12 01:02:46 PM PDT 24 Mar 12 01:04:25 PM PDT 24 15758964861 ps
T875 /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.654442305 Mar 12 01:04:02 PM PDT 24 Mar 12 01:11:15 PM PDT 24 49204848332 ps
T876 /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4219573959 Mar 12 01:04:11 PM PDT 24 Mar 12 01:04:34 PM PDT 24 2605717958 ps
T877 /workspace/coverage/xbar_build_mode/49.xbar_same_source.3140803677 Mar 12 01:04:45 PM PDT 24 Mar 12 01:05:00 PM PDT 24 222532283 ps
T878 /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2029908139 Mar 12 01:04:32 PM PDT 24 Mar 12 01:04:36 PM PDT 24 30755990 ps
T174 /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1089676148 Mar 12 01:03:27 PM PDT 24 Mar 12 01:03:51 PM PDT 24 4744314196 ps
T879 /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3261632717 Mar 12 01:02:18 PM PDT 24 Mar 12 01:06:23 PM PDT 24 3863606396 ps
T880 /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1864713474 Mar 12 01:03:48 PM PDT 24 Mar 12 01:06:48 PM PDT 24 1995970957 ps
T881 /workspace/coverage/xbar_build_mode/4.xbar_stress_all.3201567245 Mar 12 01:02:22 PM PDT 24 Mar 12 01:07:47 PM PDT 24 44193194020 ps
T882 /workspace/coverage/xbar_build_mode/48.xbar_same_source.3009202175 Mar 12 01:04:24 PM PDT 24 Mar 12 01:04:35 PM PDT 24 687873759 ps
T883 /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1694048364 Mar 12 01:03:03 PM PDT 24 Mar 12 01:03:29 PM PDT 24 3780395210 ps
T884 /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1269239379 Mar 12 01:02:44 PM PDT 24 Mar 12 01:03:11 PM PDT 24 4053446809 ps
T885 /workspace/coverage/xbar_build_mode/7.xbar_error_random.777857310 Mar 12 01:02:43 PM PDT 24 Mar 12 01:02:54 PM PDT 24 547297152 ps
T886 /workspace/coverage/xbar_build_mode/13.xbar_smoke.1573420300 Mar 12 01:02:45 PM PDT 24 Mar 12 01:02:47 PM PDT 24 45713859 ps
T887 /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2221064815 Mar 12 01:03:31 PM PDT 24 Mar 12 01:06:49 PM PDT 24 1308218066 ps
T888 /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2533889859 Mar 12 01:03:57 PM PDT 24 Mar 12 01:04:19 PM PDT 24 2867726632 ps
T889 /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.163073324 Mar 12 01:04:23 PM PDT 24 Mar 12 01:04:54 PM PDT 24 1146442665 ps
T890 /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.602274642 Mar 12 01:03:37 PM PDT 24 Mar 12 01:04:07 PM PDT 24 2474180246 ps
T891 /workspace/coverage/xbar_build_mode/23.xbar_same_source.3461600933 Mar 12 01:03:26 PM PDT 24 Mar 12 01:03:40 PM PDT 24 2950103622 ps
T892 /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.199707617 Mar 12 01:04:41 PM PDT 24 Mar 12 01:06:41 PM PDT 24 21555081872 ps
T893 /workspace/coverage/xbar_build_mode/46.xbar_random.1429720144 Mar 12 01:04:24 PM PDT 24 Mar 12 01:04:45 PM PDT 24 835564910 ps
T894 /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.390831337 Mar 12 01:04:22 PM PDT 24 Mar 12 01:04:56 PM PDT 24 9206629520 ps
T895 /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3817944262 Mar 12 01:02:18 PM PDT 24 Mar 12 01:04:27 PM PDT 24 42697394221 ps
T896 /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.138158309 Mar 12 01:03:47 PM PDT 24 Mar 12 01:04:18 PM PDT 24 4424706821 ps
T142 /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3678191900 Mar 12 01:03:47 PM PDT 24 Mar 12 01:04:05 PM PDT 24 1411648710 ps
T897 /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3065609566 Mar 12 01:02:04 PM PDT 24 Mar 12 01:06:06 PM PDT 24 32323574524 ps
T898 /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.303640871 Mar 12 01:02:56 PM PDT 24 Mar 12 01:05:44 PM PDT 24 20288712163 ps
T899 /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1233598316 Mar 12 01:03:46 PM PDT 24 Mar 12 01:04:17 PM PDT 24 5326084501 ps
T900 /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1191225121 Mar 12 01:02:49 PM PDT 24 Mar 12 01:02:57 PM PDT 24 63297510 ps

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all.644874606
Short name T4
Test name
Test status
Simulation time 6293316939 ps
CPU time 192.7 seconds
Started Mar 12 01:03:25 PM PDT 24
Finished Mar 12 01:06:39 PM PDT 24
Peak memory 208044 kb
Host smart-97d473d8-353c-4a98-a7ad-a36b8c334371
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=644874606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.644874606
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2771109018
Short name T201
Test name
Test status
Simulation time 74470210327 ps
CPU time 542.84 seconds
Started Mar 12 01:02:59 PM PDT 24
Finished Mar 12 01:12:02 PM PDT 24
Peak memory 205436 kb
Host smart-83858499-2366-461c-916a-80902a4efb14
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2771109018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_sl
ow_rsp.2771109018
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2659526400
Short name T72
Test name
Test status
Simulation time 58835586742 ps
CPU time 392.73 seconds
Started Mar 12 01:04:22 PM PDT 24
Finished Mar 12 01:10:55 PM PDT 24
Peak memory 211200 kb
Host smart-9926cd43-4a09-4dbc-adf9-47efd36add3f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2659526400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_sl
ow_rsp.2659526400
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.226149743
Short name T48
Test name
Test status
Simulation time 384155713591 ps
CPU time 764.65 seconds
Started Mar 12 01:02:40 PM PDT 24
Finished Mar 12 01:15:25 PM PDT 24
Peak memory 206496 kb
Host smart-7673da01-0d10-4dd1-ba72-903662e3cdf4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=226149743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow
_rsp.226149743
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_error.269697100
Short name T3
Test name
Test status
Simulation time 506747087 ps
CPU time 59.05 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:04:27 PM PDT 24
Peak memory 211112 kb
Host smart-c4d96b0b-fe62-49fa-957e-c186b465dda4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=269697100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.269697100
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_access_same_device.1744361323
Short name T1
Test name
Test status
Simulation time 3165256547 ps
CPU time 52.05 seconds
Started Mar 12 01:04:25 PM PDT 24
Finished Mar 12 01:05:17 PM PDT 24
Peak memory 205592 kb
Host smart-6e51349c-1720-4f73-b972-00546b5151f7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1744361323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.1744361323
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_error.3985342833
Short name T259
Test name
Test status
Simulation time 4251858806 ps
CPU time 141.31 seconds
Started Mar 12 01:02:55 PM PDT 24
Finished Mar 12 01:05:17 PM PDT 24
Peak memory 204796 kb
Host smart-c86d16a6-8b04-4ee7-98e7-9872659db01b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3985342833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3985342833
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_large_delays.2250516370
Short name T12
Test name
Test status
Simulation time 20821122078 ps
CPU time 129.88 seconds
Started Mar 12 01:03:12 PM PDT 24
Finished Mar 12 01:05:23 PM PDT 24
Peak memory 211184 kb
Host smart-aba16d64-4f55-477a-aa3d-94667d0de04c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250516370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2250516370
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1345185591
Short name T25
Test name
Test status
Simulation time 7422285352 ps
CPU time 221.46 seconds
Started Mar 12 01:04:07 PM PDT 24
Finished Mar 12 01:07:49 PM PDT 24
Peak memory 219332 kb
Host smart-4da18cd1-3792-45a3-b3ab-dceb24bfbdce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1345185591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_re
set_error.1345185591
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all.3371133520
Short name T117
Test name
Test status
Simulation time 8379748775 ps
CPU time 156.43 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:06:07 PM PDT 24
Peak memory 208376 kb
Host smart-c650e0a7-1cd4-42d1-9403-9ae439d08cb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3371133520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3371133520
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device.721002191
Short name T66
Test name
Test status
Simulation time 3969673488 ps
CPU time 66.02 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:03:52 PM PDT 24
Peak memory 206172 kb
Host smart-fb878be8-f354-4cb2-b8e5-9bdd3f0052f3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=721002191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.721002191
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.4128207753
Short name T108
Test name
Test status
Simulation time 15309822468 ps
CPU time 692.07 seconds
Started Mar 12 01:04:13 PM PDT 24
Finished Mar 12 01:15:45 PM PDT 24
Peak memory 209108 kb
Host smart-b5f99c65-a8e9-4108-b818-627e57d51ed5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4128207753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_ran
d_reset.4128207753
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device.2899370080
Short name T31
Test name
Test status
Simulation time 240653355 ps
CPU time 9.87 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:02:55 PM PDT 24
Peak memory 202976 kb
Host smart-23a8ce58-6de7-4319-8823-290acd3c2e92
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2899370080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2899370080
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3660847659
Short name T120
Test name
Test status
Simulation time 2293716515 ps
CPU time 208.16 seconds
Started Mar 12 01:02:55 PM PDT 24
Finished Mar 12 01:06:23 PM PDT 24
Peak memory 208784 kb
Host smart-1538a43d-1c10-4c78-b236-7fd24dd85330
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3660847659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_ran
d_reset.3660847659
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.1821410126
Short name T33
Test name
Test status
Simulation time 8015643955 ps
CPU time 256.22 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:07:05 PM PDT 24
Peak memory 208352 kb
Host smart-210277f1-f34d-441f-8e24-79121d41d6b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1821410126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_ran
d_reset.1821410126
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all.800426663
Short name T71
Test name
Test status
Simulation time 4429406151 ps
CPU time 171.68 seconds
Started Mar 12 01:02:59 PM PDT 24
Finished Mar 12 01:05:51 PM PDT 24
Peak memory 207652 kb
Host smart-dd0aa3c8-d04b-4a2c-ae4b-6784fb259c23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=800426663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.800426663
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.3420783220
Short name T269
Test name
Test status
Simulation time 937486942 ps
CPU time 203.19 seconds
Started Mar 12 01:04:05 PM PDT 24
Finished Mar 12 01:07:29 PM PDT 24
Peak memory 210832 kb
Host smart-9050ecab-db66-4029-94c5-6c68a97b858e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3420783220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_re
set_error.3420783220
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.547649
Short name T37
Test name
Test status
Simulation time 690702337 ps
CPU time 228.24 seconds
Started Mar 12 01:02:17 PM PDT 24
Finished Mar 12 01:06:05 PM PDT 24
Peak memory 207776 kb
Host smart-8e656a72-60e9-4efd-a704-794a62d417d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=547649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_res
et.547649
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1254762359
Short name T24
Test name
Test status
Simulation time 10106843185 ps
CPU time 263.63 seconds
Started Mar 12 01:03:05 PM PDT 24
Finished Mar 12 01:07:28 PM PDT 24
Peak memory 210780 kb
Host smart-018e9804-f9a4-4930-a786-84a993e10845
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1254762359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_ran
d_reset.1254762359
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_error.2643065270
Short name T38
Test name
Test status
Simulation time 28797287567 ps
CPU time 155.26 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:06:16 PM PDT 24
Peak memory 208572 kb
Host smart-34487e63-cef7-4950-9bec-b99c9a0f7a09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2643065270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2643065270
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_slow_rsp.4262384550
Short name T101
Test name
Test status
Simulation time 125746457130 ps
CPU time 299.89 seconds
Started Mar 12 01:02:23 PM PDT 24
Finished Mar 12 01:07:23 PM PDT 24
Peak memory 211208 kb
Host smart-4a2220c0-0390-4d91-b144-7907518098d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4262384550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.4262384550
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device.4096512526
Short name T264
Test name
Test status
Simulation time 436451996 ps
CPU time 33.31 seconds
Started Mar 12 01:02:28 PM PDT 24
Finished Mar 12 01:03:01 PM PDT 24
Peak memory 204704 kb
Host smart-e070ada5-6c77-4470-ad63-6c9fa2eae1d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4096512526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.4096512526
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2729899431
Short name T228
Test name
Test status
Simulation time 44153124000 ps
CPU time 291.3 seconds
Started Mar 12 01:02:03 PM PDT 24
Finished Mar 12 01:06:55 PM PDT 24
Peak memory 211096 kb
Host smart-f46f392c-09c9-4f64-8a33-34feaae70710
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2729899431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slo
w_rsp.2729899431
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.3074827811
Short name T372
Test name
Test status
Simulation time 662934202 ps
CPU time 19.4 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:02:51 PM PDT 24
Peak memory 202992 kb
Host smart-b85d76f3-ab7d-4157-92c6-c8a3f616a8e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3074827811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3074827811
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_error_random.1902908988
Short name T272
Test name
Test status
Simulation time 906071149 ps
CPU time 16.37 seconds
Started Mar 12 01:02:06 PM PDT 24
Finished Mar 12 01:02:23 PM PDT 24
Peak memory 202880 kb
Host smart-6b6fc709-077b-4c36-b8db-9747c87b6f4a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1902908988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1902908988
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random.3334224391
Short name T241
Test name
Test status
Simulation time 453710759 ps
CPU time 4.93 seconds
Started Mar 12 01:02:14 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 203000 kb
Host smart-b313df9b-6a99-495c-a907-0a0c35d490e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3334224391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3334224391
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_large_delays.3817944262
Short name T895
Test name
Test status
Simulation time 42697394221 ps
CPU time 128.74 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:04:27 PM PDT 24
Peak memory 204536 kb
Host smart-d3d5556d-6a6d-421e-a125-bda2839dc010
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817944262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3817944262
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3856875628
Short name T476
Test name
Test status
Simulation time 27752260161 ps
CPU time 256.23 seconds
Started Mar 12 01:02:09 PM PDT 24
Finished Mar 12 01:06:26 PM PDT 24
Peak memory 204848 kb
Host smart-27e7e332-044a-4a7e-acce-0f37bfd528ed
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3856875628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3856875628
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_random_zero_delays.4096546234
Short name T749
Test name
Test status
Simulation time 215927569 ps
CPU time 20.63 seconds
Started Mar 12 01:01:58 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 211096 kb
Host smart-12ae22d1-abdc-4473-9bc4-0deb46ad353c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096546234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.4096546234
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_same_source.2785125561
Short name T354
Test name
Test status
Simulation time 441594931 ps
CPU time 4.7 seconds
Started Mar 12 01:01:59 PM PDT 24
Finished Mar 12 01:02:04 PM PDT 24
Peak memory 202904 kb
Host smart-5b8de0c4-7fe4-4845-aea5-6a2d73ce7d85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2785125561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2785125561
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke.2607604316
Short name T479
Test name
Test status
Simulation time 36848737 ps
CPU time 2.15 seconds
Started Mar 12 01:02:17 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 202924 kb
Host smart-8715528c-5634-476b-b81c-ef80a58989e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2607604316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2607604316
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_large_delays.2207063789
Short name T801
Test name
Test status
Simulation time 6364602430 ps
CPU time 29.86 seconds
Started Mar 12 01:02:30 PM PDT 24
Finished Mar 12 01:03:00 PM PDT 24
Peak memory 202960 kb
Host smart-bdfe688f-f3d9-4685-b5a4-883c331d15b3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207063789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2207063789
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1367462518
Short name T699
Test name
Test status
Simulation time 5250226309 ps
CPU time 32.19 seconds
Started Mar 12 01:02:19 PM PDT 24
Finished Mar 12 01:02:51 PM PDT 24
Peak memory 202976 kb
Host smart-69906d85-a01c-4973-8687-50245234020c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1367462518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1367462518
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2463716629
Short name T742
Test name
Test status
Simulation time 22107773 ps
CPU time 1.97 seconds
Started Mar 12 01:02:21 PM PDT 24
Finished Mar 12 01:02:23 PM PDT 24
Peak memory 202940 kb
Host smart-955fb957-5250-43bc-8f61-c889cd20aa3b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463716629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2463716629
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all.2014782981
Short name T78
Test name
Test status
Simulation time 2439294304 ps
CPU time 59.06 seconds
Started Mar 12 01:02:19 PM PDT 24
Finished Mar 12 01:03:18 PM PDT 24
Peak memory 211056 kb
Host smart-5e3df929-f3ec-423d-b671-5212a9542f39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2014782981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2014782981
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_error.176409837
Short name T356
Test name
Test status
Simulation time 11983857010 ps
CPU time 120.03 seconds
Started Mar 12 01:02:17 PM PDT 24
Finished Mar 12 01:04:17 PM PDT 24
Peak memory 206552 kb
Host smart-7a05e68b-b644-463c-829d-4eed6ce4dbec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=176409837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.176409837
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3903350210
Short name T716
Test name
Test status
Simulation time 279579476 ps
CPU time 114.82 seconds
Started Mar 12 01:02:27 PM PDT 24
Finished Mar 12 01:04:21 PM PDT 24
Peak memory 209356 kb
Host smart-ba30c231-f717-4fe6-b065-6f595977f1d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3903350210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_res
et_error.3903350210
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/0.xbar_unmapped_addr.3775749573
Short name T55
Test name
Test status
Simulation time 946605964 ps
CPU time 24.47 seconds
Started Mar 12 01:02:19 PM PDT 24
Finished Mar 12 01:02:43 PM PDT 24
Peak memory 204308 kb
Host smart-89c10410-3c4b-4a61-b278-00307a94ae40
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3775749573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3775749573
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device.2459495797
Short name T77
Test name
Test status
Simulation time 376626268 ps
CPU time 13.77 seconds
Started Mar 12 01:02:27 PM PDT 24
Finished Mar 12 01:02:41 PM PDT 24
Peak memory 203996 kb
Host smart-72a87684-2b06-449b-a19e-9893a12effa3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2459495797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2459495797
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1510145169
Short name T85
Test name
Test status
Simulation time 11530860900 ps
CPU time 104.46 seconds
Started Mar 12 01:02:03 PM PDT 24
Finished Mar 12 01:03:48 PM PDT 24
Peak memory 211120 kb
Host smart-016dcc09-48b6-4450-b252-3717d00e6382
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1510145169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slo
w_rsp.1510145169
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.943074524
Short name T682
Test name
Test status
Simulation time 56472910 ps
CPU time 7.1 seconds
Started Mar 12 01:02:25 PM PDT 24
Finished Mar 12 01:02:32 PM PDT 24
Peak memory 202976 kb
Host smart-835035da-7af6-493b-8e01-72ae28d411a7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=943074524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.943074524
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_error_random.813177135
Short name T291
Test name
Test status
Simulation time 81765456 ps
CPU time 3.05 seconds
Started Mar 12 01:02:23 PM PDT 24
Finished Mar 12 01:02:26 PM PDT 24
Peak memory 202864 kb
Host smart-7bbc382f-5c67-4dbf-8a5e-4cdfb32d80ee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=813177135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.813177135
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random.981469791
Short name T538
Test name
Test status
Simulation time 1150363167 ps
CPU time 32.03 seconds
Started Mar 12 01:02:02 PM PDT 24
Finished Mar 12 01:02:35 PM PDT 24
Peak memory 203928 kb
Host smart-0257d2c7-7ee4-48ab-a1e4-83b6477a371c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=981469791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.981469791
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_large_delays.2718575974
Short name T546
Test name
Test status
Simulation time 14470666390 ps
CPU time 55.46 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:03:18 PM PDT 24
Peak memory 204248 kb
Host smart-28498f41-3bae-4394-8386-b2b67c00ae6c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718575974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2718575974
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_random_zero_delays.3373845311
Short name T328
Test name
Test status
Simulation time 809851754 ps
CPU time 19.73 seconds
Started Mar 12 01:02:25 PM PDT 24
Finished Mar 12 01:02:45 PM PDT 24
Peak memory 203972 kb
Host smart-43ca9253-5525-4158-b157-89340b11d4b5
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373845311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3373845311
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_same_source.3226474312
Short name T823
Test name
Test status
Simulation time 4006232662 ps
CPU time 26.44 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:48 PM PDT 24
Peak memory 202960 kb
Host smart-4acd2972-4d9e-42a2-b768-4c51f4f5721c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3226474312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3226474312
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke.1353608234
Short name T816
Test name
Test status
Simulation time 181296721 ps
CPU time 4.07 seconds
Started Mar 12 01:02:20 PM PDT 24
Finished Mar 12 01:02:24 PM PDT 24
Peak memory 202712 kb
Host smart-7853995b-f418-47c9-b124-d394f4a914a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1353608234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1353608234
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3251635853
Short name T509
Test name
Test status
Simulation time 36150913218 ps
CPU time 53.51 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:03:16 PM PDT 24
Peak memory 203012 kb
Host smart-fb45598f-4254-44cb-bd02-077c5e04e35c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251635853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3251635853
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2989060180
Short name T540
Test name
Test status
Simulation time 10119348292 ps
CPU time 40.66 seconds
Started Mar 12 01:02:14 PM PDT 24
Finished Mar 12 01:02:55 PM PDT 24
Peak memory 202952 kb
Host smart-7dbc7c69-ca0b-4550-acc3-84b967e0fa17
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2989060180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2989060180
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.2679447320
Short name T7
Test name
Test status
Simulation time 31250478 ps
CPU time 2.43 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:02:34 PM PDT 24
Peak memory 202944 kb
Host smart-8d5774d8-dc3c-49fc-b887-8803a0fa6dfd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679447320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.2679447320
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all.835487458
Short name T550
Test name
Test status
Simulation time 6780749567 ps
CPU time 154.66 seconds
Started Mar 12 01:02:15 PM PDT 24
Finished Mar 12 01:04:50 PM PDT 24
Peak memory 209052 kb
Host smart-99632dce-0c6d-4650-9bb2-9a72948cdb1a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=835487458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.835487458
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_error.279488590
Short name T475
Test name
Test status
Simulation time 127855594 ps
CPU time 3.51 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:26 PM PDT 24
Peak memory 202944 kb
Host smart-e9818d02-8792-4665-b69c-aa629d323439
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=279488590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.279488590
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.4040669572
Short name T436
Test name
Test status
Simulation time 1159695692 ps
CPU time 292.87 seconds
Started Mar 12 01:02:12 PM PDT 24
Finished Mar 12 01:07:05 PM PDT 24
Peak memory 209088 kb
Host smart-42e5da5b-21d2-452f-b09a-2fc070d9acb5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4040669572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand
_reset.4040669572
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.2125161976
Short name T614
Test name
Test status
Simulation time 3242837793 ps
CPU time 465.42 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:10:07 PM PDT 24
Peak memory 219592 kb
Host smart-154b8e43-2bf7-474a-9099-93eeb30d9a5c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2125161976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_res
et_error.2125161976
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/1.xbar_unmapped_addr.3019927725
Short name T230
Test name
Test status
Simulation time 271674219 ps
CPU time 7.93 seconds
Started Mar 12 01:02:21 PM PDT 24
Finished Mar 12 01:02:29 PM PDT 24
Peak memory 204088 kb
Host smart-96bd4339-c6ca-4eb2-993e-1f7952f4b129
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3019927725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3019927725
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device.2465549472
Short name T217
Test name
Test status
Simulation time 345617133 ps
CPU time 10.94 seconds
Started Mar 12 01:02:41 PM PDT 24
Finished Mar 12 01:02:52 PM PDT 24
Peak memory 203276 kb
Host smart-8777dc1d-e505-4b1f-bed7-190c1f634100
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2465549472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2465549472
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3803350471
Short name T200
Test name
Test status
Simulation time 6089519926 ps
CPU time 34.46 seconds
Started Mar 12 01:02:37 PM PDT 24
Finished Mar 12 01:03:12 PM PDT 24
Peak memory 203196 kb
Host smart-5c75b0dc-a071-4745-86f9-e6950de23998
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3803350471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_sl
ow_rsp.3803350471
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.4023489764
Short name T717
Test name
Test status
Simulation time 77392011 ps
CPU time 2.49 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:02:45 PM PDT 24
Peak memory 202912 kb
Host smart-e7d44223-8e1b-4753-b284-9cfe16f76eee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4023489764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.4023489764
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_error_random.3478230292
Short name T484
Test name
Test status
Simulation time 387964084 ps
CPU time 11.06 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:02:54 PM PDT 24
Peak memory 202844 kb
Host smart-969da372-5e3e-4fc9-8626-4be177c8ee9e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3478230292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3478230292
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random.1509187756
Short name T839
Test name
Test status
Simulation time 151177326 ps
CPU time 16.44 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:02:58 PM PDT 24
Peak memory 204132 kb
Host smart-9d3f10db-ebf2-4727-a673-5f745bd178e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1509187756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.1509187756
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_large_delays.95112546
Short name T757
Test name
Test status
Simulation time 20592547790 ps
CPU time 121.17 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:04:44 PM PDT 24
Peak memory 211184 kb
Host smart-227351cb-fcde-412e-930c-74b401c7a6df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=95112546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.95112546
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1269239379
Short name T884
Test name
Test status
Simulation time 4053446809 ps
CPU time 27.03 seconds
Started Mar 12 01:02:44 PM PDT 24
Finished Mar 12 01:03:11 PM PDT 24
Peak memory 203032 kb
Host smart-b54c32d0-af7f-47ed-88a9-feb94c9dad24
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1269239379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1269239379
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_random_zero_delays.4111158672
Short name T702
Test name
Test status
Simulation time 60712290 ps
CPU time 7.09 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:02:49 PM PDT 24
Peak memory 203984 kb
Host smart-0ba9166d-00bd-47de-8946-d0151de9b404
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111158672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.4111158672
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_same_source.200296544
Short name T580
Test name
Test status
Simulation time 25297524 ps
CPU time 2.23 seconds
Started Mar 12 01:02:41 PM PDT 24
Finished Mar 12 01:02:43 PM PDT 24
Peak memory 202812 kb
Host smart-1dcb35ca-6e3c-42e0-976c-aafebbc4d6b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=200296544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.200296544
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke.1663562369
Short name T493
Test name
Test status
Simulation time 126217680 ps
CPU time 3.58 seconds
Started Mar 12 01:02:40 PM PDT 24
Finished Mar 12 01:02:43 PM PDT 24
Peak memory 202960 kb
Host smart-7789cce4-aac3-4650-960f-e1346f55cb76
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1663562369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1663562369
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1225200566
Short name T130
Test name
Test status
Simulation time 7086087504 ps
CPU time 31.33 seconds
Started Mar 12 01:02:41 PM PDT 24
Finished Mar 12 01:03:12 PM PDT 24
Peak memory 202980 kb
Host smart-f1e3d206-e1de-4e20-a8c6-05035f0936a5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225200566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1225200566
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.4124927751
Short name T150
Test name
Test status
Simulation time 12200179872 ps
CPU time 42.7 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:03:25 PM PDT 24
Peak memory 202996 kb
Host smart-a8fba0a7-a401-40f8-be56-cb3780ca92a9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4124927751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.4124927751
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.4118088995
Short name T363
Test name
Test status
Simulation time 34122057 ps
CPU time 2.17 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:02:47 PM PDT 24
Peak memory 202936 kb
Host smart-7e4eca15-ba9b-4a9b-b388-576d118f5138
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118088995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.4118088995
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all.3707416122
Short name T471
Test name
Test status
Simulation time 20667751292 ps
CPU time 278.82 seconds
Started Mar 12 01:02:38 PM PDT 24
Finished Mar 12 01:07:17 PM PDT 24
Peak memory 206800 kb
Host smart-e18ff9d9-801e-4fd5-a6a4-ad071cf2f627
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3707416122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3707416122
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2706899889
Short name T392
Test name
Test status
Simulation time 1767073562 ps
CPU time 104.98 seconds
Started Mar 12 01:02:44 PM PDT 24
Finished Mar 12 01:04:30 PM PDT 24
Peak memory 207476 kb
Host smart-6b3f7931-2caa-47e3-8a67-8e0e7a90d322
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2706899889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2706899889
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1603938638
Short name T216
Test name
Test status
Simulation time 13872200658 ps
CPU time 572.62 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:12:27 PM PDT 24
Peak memory 208204 kb
Host smart-ec46e6d7-28f4-445e-89de-0378abdeec2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1603938638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_ran
d_reset.1603938638
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.4280985339
Short name T113
Test name
Test status
Simulation time 159479457 ps
CPU time 33.13 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:03:16 PM PDT 24
Peak memory 205644 kb
Host smart-5ef717e9-baed-428c-8ed9-0ad3be4ae9a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4280985339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_re
set_error.4280985339
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/10.xbar_unmapped_addr.1321840291
Short name T627
Test name
Test status
Simulation time 97549038 ps
CPU time 17.23 seconds
Started Mar 12 01:02:36 PM PDT 24
Finished Mar 12 01:02:54 PM PDT 24
Peak memory 204432 kb
Host smart-70dc3094-acaa-4228-ae10-63160a87b0e5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1321840291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1321840291
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2733933035
Short name T257
Test name
Test status
Simulation time 50177155593 ps
CPU time 394.33 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:09:21 PM PDT 24
Peak memory 205316 kb
Host smart-075da82a-51d9-4be8-b809-a71eeb3fb8f7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2733933035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_sl
ow_rsp.2733933035
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2889163226
Short name T771
Test name
Test status
Simulation time 50220176 ps
CPU time 1.96 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:02:50 PM PDT 24
Peak memory 202920 kb
Host smart-80fed279-c281-433e-878e-eae3a1f425b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2889163226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2889163226
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_error_random.53154838
Short name T314
Test name
Test status
Simulation time 86024004 ps
CPU time 10.48 seconds
Started Mar 12 01:02:44 PM PDT 24
Finished Mar 12 01:02:55 PM PDT 24
Peak memory 202844 kb
Host smart-c688db41-38f5-4e60-a686-e5c377b95a85
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=53154838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.53154838
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random.3843839457
Short name T553
Test name
Test status
Simulation time 1149727695 ps
CPU time 13.18 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:02:59 PM PDT 24
Peak memory 204000 kb
Host smart-bfe1c5f0-235e-495d-b559-a67b6fea89ff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3843839457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3843839457
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_large_delays.1799190594
Short name T250
Test name
Test status
Simulation time 62920271324 ps
CPU time 212.95 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:06:19 PM PDT 24
Peak memory 204788 kb
Host smart-449a0813-3435-4369-8e93-5e1105034aa5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799190594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1799190594
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_slow_rsp.4187293711
Short name T464
Test name
Test status
Simulation time 19961001836 ps
CPU time 177.58 seconds
Started Mar 12 01:03:01 PM PDT 24
Finished Mar 12 01:05:59 PM PDT 24
Peak memory 204348 kb
Host smart-68ff41d3-f01e-479e-810c-98ea3be6df1f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4187293711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.4187293711
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_random_zero_delays.3348565558
Short name T420
Test name
Test status
Simulation time 15978500 ps
CPU time 2.01 seconds
Started Mar 12 01:02:40 PM PDT 24
Finished Mar 12 01:02:42 PM PDT 24
Peak memory 202836 kb
Host smart-b2b3ac2d-f13f-4ae7-86e4-c518a699bcd6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348565558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3348565558
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_same_source.22766185
Short name T677
Test name
Test status
Simulation time 938144570 ps
CPU time 20.2 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:03:03 PM PDT 24
Peak memory 202988 kb
Host smart-4de0527c-2947-4250-a053-62a2392fac98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=22766185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.22766185
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke.492101220
Short name T53
Test name
Test status
Simulation time 111410480 ps
CPU time 3.47 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:02:49 PM PDT 24
Peak memory 202904 kb
Host smart-14937e0f-c012-4498-84d2-7a417116e57c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=492101220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.492101220
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_large_delays.1247934844
Short name T155
Test name
Test status
Simulation time 6099589232 ps
CPU time 29.49 seconds
Started Mar 12 01:02:39 PM PDT 24
Finished Mar 12 01:03:09 PM PDT 24
Peak memory 202980 kb
Host smart-0a1d8cf0-636e-4970-ad76-a4c5961278d4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247934844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1247934844
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.1918422912
Short name T793
Test name
Test status
Simulation time 3543754042 ps
CPU time 33.55 seconds
Started Mar 12 01:02:36 PM PDT 24
Finished Mar 12 01:03:09 PM PDT 24
Peak memory 202968 kb
Host smart-94e1f1c1-f920-450b-bd21-fe308dbb55bb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1918422912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1918422912
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.3776303466
Short name T416
Test name
Test status
Simulation time 26666170 ps
CPU time 2.24 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:02:46 PM PDT 24
Peak memory 202964 kb
Host smart-f6e9460a-8df3-49c4-87d7-db76d46fb429
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776303466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.3776303466
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all.2919506698
Short name T780
Test name
Test status
Simulation time 1864942300 ps
CPU time 61.68 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:03:46 PM PDT 24
Peak memory 205604 kb
Host smart-117d4b99-fe3d-4732-a607-72545dad2eee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2919506698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2919506698
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_error.742796765
Short name T132
Test name
Test status
Simulation time 1720846640 ps
CPU time 36.87 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:03:20 PM PDT 24
Peak memory 204264 kb
Host smart-3a638bda-c0dd-4e47-86ed-d232bfe908cf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=742796765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.742796765
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.351579787
Short name T288
Test name
Test status
Simulation time 73276134 ps
CPU time 3.62 seconds
Started Mar 12 01:02:50 PM PDT 24
Finished Mar 12 01:02:54 PM PDT 24
Peak memory 202996 kb
Host smart-ce6ad546-401c-46df-8c43-fc490e0544bb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=351579787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_res
et_error.351579787
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/11.xbar_unmapped_addr.1921863372
Short name T552
Test name
Test status
Simulation time 647285832 ps
CPU time 29.56 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:03:15 PM PDT 24
Peak memory 211064 kb
Host smart-d2e26d5c-40de-4ff6-a54f-a633680795c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1921863372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1921863372
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device.2646335545
Short name T542
Test name
Test status
Simulation time 1433789169 ps
CPU time 61.43 seconds
Started Mar 12 01:02:50 PM PDT 24
Finished Mar 12 01:03:52 PM PDT 24
Peak memory 211104 kb
Host smart-a176377f-1f3c-4ab7-92cd-ee531e5a8118
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2646335545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2646335545
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1441178324
Short name T128
Test name
Test status
Simulation time 76515664381 ps
CPU time 552.68 seconds
Started Mar 12 01:02:44 PM PDT 24
Finished Mar 12 01:11:57 PM PDT 24
Peak memory 206432 kb
Host smart-b31d0726-2c98-4fc5-9cd1-25f2973cf403
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1441178324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_sl
ow_rsp.1441178324
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3072669937
Short name T791
Test name
Test status
Simulation time 308847493 ps
CPU time 8.99 seconds
Started Mar 12 01:03:08 PM PDT 24
Finished Mar 12 01:03:17 PM PDT 24
Peak memory 202952 kb
Host smart-f04ee216-1c61-44bb-b6ea-def2f1bdc9fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3072669937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3072669937
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_error_random.1480026917
Short name T835
Test name
Test status
Simulation time 1175808991 ps
CPU time 20.78 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:03:06 PM PDT 24
Peak memory 202940 kb
Host smart-d16a4dda-edd6-4b9d-9264-7cfb13ff85f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1480026917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1480026917
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random.3476988141
Short name T13
Test name
Test status
Simulation time 433808328 ps
CPU time 22.2 seconds
Started Mar 12 01:02:40 PM PDT 24
Finished Mar 12 01:03:02 PM PDT 24
Peak memory 203916 kb
Host smart-153b464e-1af8-4094-a0b2-3805a3e3fcfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3476988141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3476988141
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_large_delays.3127040198
Short name T874
Test name
Test status
Simulation time 15758964861 ps
CPU time 98.46 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:04:25 PM PDT 24
Peak memory 204252 kb
Host smart-ce489caa-34c0-405f-9ce5-2ecdf0c1bb70
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127040198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3127040198
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_slow_rsp.3754682446
Short name T177
Test name
Test status
Simulation time 47446811476 ps
CPU time 182.7 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:05:49 PM PDT 24
Peak memory 204228 kb
Host smart-92c17e41-6dcc-4b98-9c8c-7b48d43e5c35
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3754682446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3754682446
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_random_zero_delays.2957618994
Short name T623
Test name
Test status
Simulation time 370519681 ps
CPU time 14.77 seconds
Started Mar 12 01:03:06 PM PDT 24
Finished Mar 12 01:03:21 PM PDT 24
Peak memory 203940 kb
Host smart-4945ca88-047b-47a2-b54d-e1e05dcdf6da
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957618994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.2957618994
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_same_source.475950772
Short name T561
Test name
Test status
Simulation time 54419139 ps
CPU time 3.84 seconds
Started Mar 12 01:02:41 PM PDT 24
Finished Mar 12 01:02:45 PM PDT 24
Peak memory 203064 kb
Host smart-664a11fc-5b97-4064-ab00-d328c7b034d8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=475950772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.475950772
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke.3987557862
Short name T348
Test name
Test status
Simulation time 52030243 ps
CPU time 2.21 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:02:49 PM PDT 24
Peak memory 202904 kb
Host smart-95b6b847-8313-4736-a26d-ba30f5232303
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3987557862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3987557862
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_large_delays.849258794
Short name T622
Test name
Test status
Simulation time 12695652337 ps
CPU time 32.94 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:03:21 PM PDT 24
Peak memory 202936 kb
Host smart-ae89fb90-2f8f-40bd-9ef1-8f3d425c60e2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=849258794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.849258794
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.27981629
Short name T631
Test name
Test status
Simulation time 5326955992 ps
CPU time 30.47 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:03:13 PM PDT 24
Peak memory 203008 kb
Host smart-eb11681d-13d3-4d9f-ade0-3e38b0f9a433
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=27981629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.27981629
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2543340823
Short name T447
Test name
Test status
Simulation time 21945222 ps
CPU time 2.08 seconds
Started Mar 12 01:02:48 PM PDT 24
Finished Mar 12 01:02:51 PM PDT 24
Peak memory 202860 kb
Host smart-a2786eac-b5e7-453c-9cae-010cca5ae525
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543340823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2543340823
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all.4246765492
Short name T794
Test name
Test status
Simulation time 678732467 ps
CPU time 7.86 seconds
Started Mar 12 01:02:52 PM PDT 24
Finished Mar 12 01:03:00 PM PDT 24
Peak memory 203988 kb
Host smart-8a2bc1dc-31f3-469b-a1a9-e765b5cb0770
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4246765492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.4246765492
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_error.4199825561
Short name T303
Test name
Test status
Simulation time 9898432299 ps
CPU time 123.42 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:04:50 PM PDT 24
Peak memory 205940 kb
Host smart-d13f92bf-0d4d-4d50-8ca4-806b1b91bb1d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4199825561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.4199825561
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.1937372460
Short name T574
Test name
Test status
Simulation time 319169962 ps
CPU time 107.96 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:04:31 PM PDT 24
Peak memory 207064 kb
Host smart-e05fd38f-0ddf-4e17-bf7a-649d92c1cada
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1937372460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_ran
d_reset.1937372460
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3002594226
Short name T615
Test name
Test status
Simulation time 441862263 ps
CPU time 61.83 seconds
Started Mar 12 01:02:54 PM PDT 24
Finished Mar 12 01:03:56 PM PDT 24
Peak memory 207868 kb
Host smart-3657aec5-f1e0-4e70-b956-60b6a4a152c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3002594226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_re
set_error.3002594226
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/12.xbar_unmapped_addr.1102760921
Short name T833
Test name
Test status
Simulation time 122073040 ps
CPU time 8.52 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:02:57 PM PDT 24
Peak memory 211136 kb
Host smart-8e035a30-55af-4316-9da9-314dd5c9676a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1102760921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1102760921
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.452066545
Short name T160
Test name
Test status
Simulation time 155518230982 ps
CPU time 294.89 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:07:43 PM PDT 24
Peak memory 205188 kb
Host smart-aadcdbef-4b68-4115-a437-250d93b11d8e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=452066545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slo
w_rsp.452066545
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.103782940
Short name T813
Test name
Test status
Simulation time 392978443 ps
CPU time 12.99 seconds
Started Mar 12 01:02:48 PM PDT 24
Finished Mar 12 01:03:01 PM PDT 24
Peak memory 202896 kb
Host smart-59d174fe-3432-4b11-a521-521a22d7d7ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=103782940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.103782940
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_error_random.2951419058
Short name T501
Test name
Test status
Simulation time 36916768 ps
CPU time 3.09 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:02:51 PM PDT 24
Peak memory 202900 kb
Host smart-380dc64f-a809-4c51-bebe-cb9d83b120b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2951419058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2951419058
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random.569421628
Short name T296
Test name
Test status
Simulation time 281991801 ps
CPU time 23.34 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:03:09 PM PDT 24
Peak memory 204164 kb
Host smart-edcba62d-7889-414b-a40f-da49880fb65e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=569421628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.569421628
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_large_delays.3465743666
Short name T218
Test name
Test status
Simulation time 59560899279 ps
CPU time 129.52 seconds
Started Mar 12 01:02:48 PM PDT 24
Finished Mar 12 01:04:58 PM PDT 24
Peak memory 211184 kb
Host smart-a8475688-f71e-4b0c-a5dc-3bbef0be7549
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465743666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3465743666
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_slow_rsp.3385372027
Short name T299
Test name
Test status
Simulation time 21600326031 ps
CPU time 151.48 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:05:19 PM PDT 24
Peak memory 211188 kb
Host smart-0fc81769-b151-4137-885f-56b31a5f33e5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3385372027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3385372027
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_random_zero_delays.47244162
Short name T518
Test name
Test status
Simulation time 293424142 ps
CPU time 13.17 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:02:56 PM PDT 24
Peak memory 203944 kb
Host smart-95b61aa6-47f9-4316-9c6e-c6e7a27b6bec
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47244162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.47244162
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_same_source.3278938244
Short name T438
Test name
Test status
Simulation time 193831099 ps
CPU time 3.53 seconds
Started Mar 12 01:02:48 PM PDT 24
Finished Mar 12 01:02:51 PM PDT 24
Peak memory 202876 kb
Host smart-67f09b7f-cfa0-4dc4-a62a-2730d24693ef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3278938244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3278938244
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke.1573420300
Short name T886
Test name
Test status
Simulation time 45713859 ps
CPU time 2.12 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:02:47 PM PDT 24
Peak memory 202944 kb
Host smart-34032075-5b51-4753-a303-99a4c42babd6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1573420300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1573420300
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1935498467
Short name T52
Test name
Test status
Simulation time 9764868213 ps
CPU time 33.01 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:03:22 PM PDT 24
Peak memory 203008 kb
Host smart-a9d6bc84-b396-44ef-9436-021b958c5dae
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935498467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1935498467
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2257637937
Short name T185
Test name
Test status
Simulation time 2896950701 ps
CPU time 26.55 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:03:13 PM PDT 24
Peak memory 203020 kb
Host smart-69ca1d71-9139-411e-b2ad-8a782f2e6f29
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2257637937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2257637937
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.4039171582
Short name T360
Test name
Test status
Simulation time 88476160 ps
CPU time 2.55 seconds
Started Mar 12 01:03:05 PM PDT 24
Finished Mar 12 01:03:08 PM PDT 24
Peak memory 202936 kb
Host smart-3af3e7a8-185d-4585-8efa-3facb15c1328
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039171582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.4039171582
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_error.890615341
Short name T338
Test name
Test status
Simulation time 2767568642 ps
CPU time 73.44 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:04:00 PM PDT 24
Peak memory 204300 kb
Host smart-9ac81c9a-eae3-4886-845a-cbd2edb51739
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=890615341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.890615341
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.408831454
Short name T215
Test name
Test status
Simulation time 9935080878 ps
CPU time 834.05 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:16:41 PM PDT 24
Peak memory 209412 kb
Host smart-64a52139-2267-45bc-8633-83e322b46fd3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=408831454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand
_reset.408831454
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3904974924
Short name T322
Test name
Test status
Simulation time 2581477893 ps
CPU time 213.66 seconds
Started Mar 12 01:03:00 PM PDT 24
Finished Mar 12 01:06:34 PM PDT 24
Peak memory 209360 kb
Host smart-f00f3995-604c-46c3-a4f5-5261e8070daf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3904974924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_re
set_error.3904974924
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/13.xbar_unmapped_addr.3295265272
Short name T675
Test name
Test status
Simulation time 88364441 ps
CPU time 11.66 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:02:59 PM PDT 24
Peak memory 204232 kb
Host smart-0ab334e4-829f-4ddd-b817-b5efc422f3b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3295265272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3295265272
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device.2359510003
Short name T695
Test name
Test status
Simulation time 529172833 ps
CPU time 22.46 seconds
Started Mar 12 01:03:02 PM PDT 24
Finished Mar 12 01:03:25 PM PDT 24
Peak memory 204064 kb
Host smart-ff1b77ef-7636-4096-b950-72348550672f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2359510003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2359510003
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.3321989199
Short name T575
Test name
Test status
Simulation time 214396400448 ps
CPU time 599.7 seconds
Started Mar 12 01:02:54 PM PDT 24
Finished Mar 12 01:12:54 PM PDT 24
Peak memory 211180 kb
Host smart-67576c14-002f-4b82-87ab-e8b0abcc880d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3321989199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_sl
ow_rsp.3321989199
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.368665141
Short name T751
Test name
Test status
Simulation time 424822781 ps
CPU time 17.67 seconds
Started Mar 12 01:02:52 PM PDT 24
Finished Mar 12 01:03:10 PM PDT 24
Peak memory 203256 kb
Host smart-684b2422-e94f-4efc-b042-a9fedeee5cab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=368665141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.368665141
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_error_random.680330687
Short name T347
Test name
Test status
Simulation time 928403544 ps
CPU time 25.83 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:03:15 PM PDT 24
Peak memory 202908 kb
Host smart-1be10007-64c3-47ed-a88d-6115ee04bbdb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=680330687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.680330687
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random.3628894022
Short name T44
Test name
Test status
Simulation time 128714679 ps
CPU time 2.64 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:02:50 PM PDT 24
Peak memory 202928 kb
Host smart-0620e238-1af5-44c8-9494-75ff0e32a276
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3628894022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3628894022
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_large_delays.948610554
Short name T870
Test name
Test status
Simulation time 110448753674 ps
CPU time 183.1 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:05:49 PM PDT 24
Peak memory 211192 kb
Host smart-7057070f-5bd5-4571-8b7f-6aa34c28dca2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=948610554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.948610554
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_slow_rsp.205598157
Short name T168
Test name
Test status
Simulation time 104949965244 ps
CPU time 182.05 seconds
Started Mar 12 01:02:48 PM PDT 24
Finished Mar 12 01:05:50 PM PDT 24
Peak memory 204304 kb
Host smart-7c00b772-e305-4330-acdd-12868339b656
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=205598157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.205598157
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_random_zero_delays.2246174706
Short name T167
Test name
Test status
Simulation time 252701895 ps
CPU time 7.56 seconds
Started Mar 12 01:02:48 PM PDT 24
Finished Mar 12 01:02:56 PM PDT 24
Peak memory 204068 kb
Host smart-2c821c49-2df8-4b8d-9339-9f0ef618f739
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246174706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2246174706
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_same_source.3752288009
Short name T613
Test name
Test status
Simulation time 676862002 ps
CPU time 11.81 seconds
Started Mar 12 01:02:44 PM PDT 24
Finished Mar 12 01:02:56 PM PDT 24
Peak memory 203404 kb
Host smart-76239685-cec8-43f5-a8b0-65f83a017489
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3752288009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3752288009
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke.599614187
Short name T249
Test name
Test status
Simulation time 104748534 ps
CPU time 3.23 seconds
Started Mar 12 01:03:02 PM PDT 24
Finished Mar 12 01:03:05 PM PDT 24
Peak memory 202900 kb
Host smart-bf755769-8b1a-47e6-839e-bd10c59e2cec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=599614187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.599614187
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_large_delays.830908460
Short name T233
Test name
Test status
Simulation time 12324711493 ps
CPU time 42.19 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:03:28 PM PDT 24
Peak memory 202984 kb
Host smart-37f8dcc8-acf4-47f9-aa01-7cd3e5368eb7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=830908460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.830908460
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.474053708
Short name T307
Test name
Test status
Simulation time 3621366195 ps
CPU time 27.28 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:03:13 PM PDT 24
Peak memory 202992 kb
Host smart-19363252-72b8-4737-bbd8-86b24e5d9209
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=474053708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.474053708
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.554996179
Short name T442
Test name
Test status
Simulation time 35157396 ps
CPU time 2.29 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:02:48 PM PDT 24
Peak memory 202904 kb
Host smart-4b94dcdf-d1be-4467-a039-855a7c498d9e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554996179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.554996179
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all.4023425236
Short name T75
Test name
Test status
Simulation time 5406227111 ps
CPU time 89.66 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:04:15 PM PDT 24
Peak memory 211124 kb
Host smart-aba0534e-de97-40e8-872a-287d3ca428a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4023425236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.4023425236
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1580820476
Short name T69
Test name
Test status
Simulation time 5088204091 ps
CPU time 159.59 seconds
Started Mar 12 01:02:50 PM PDT 24
Finished Mar 12 01:05:30 PM PDT 24
Peak memory 208812 kb
Host smart-e8beff2b-b809-4e59-afd8-360cf1594d39
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1580820476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1580820476
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1332169550
Short name T30
Test name
Test status
Simulation time 8735899998 ps
CPU time 267.87 seconds
Started Mar 12 01:02:50 PM PDT 24
Finished Mar 12 01:07:19 PM PDT 24
Peak memory 210092 kb
Host smart-2c16de18-45f7-4d59-ad3d-a42cf58686d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1332169550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_ran
d_reset.1332169550
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.3727347789
Short name T262
Test name
Test status
Simulation time 3225126943 ps
CPU time 225.35 seconds
Started Mar 12 01:02:52 PM PDT 24
Finished Mar 12 01:06:38 PM PDT 24
Peak memory 211164 kb
Host smart-7f9b2377-a1c0-4839-88a8-89c383d6c55c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3727347789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_re
set_error.3727347789
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/14.xbar_unmapped_addr.2719328338
Short name T367
Test name
Test status
Simulation time 275309876 ps
CPU time 23.12 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:03:09 PM PDT 24
Peak memory 211084 kb
Host smart-82d1b229-c101-442a-a13a-ab62a402edfc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2719328338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2719328338
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device.3666042997
Short name T690
Test name
Test status
Simulation time 2245664975 ps
CPU time 50.14 seconds
Started Mar 12 01:02:48 PM PDT 24
Finished Mar 12 01:03:38 PM PDT 24
Peak memory 204612 kb
Host smart-074cb46b-e238-46a8-a27a-fd6d081627c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3666042997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3666042997
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1288599108
Short name T650
Test name
Test status
Simulation time 51446167408 ps
CPU time 290.63 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:07:40 PM PDT 24
Peak memory 205992 kb
Host smart-d97bf13a-2e46-4d98-a09b-e5bc758d781e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1288599108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_sl
ow_rsp.1288599108
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1191225121
Short name T900
Test name
Test status
Simulation time 63297510 ps
CPU time 7.9 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:02:57 PM PDT 24
Peak memory 203144 kb
Host smart-d0e3e96a-8db1-4400-a5df-3157055d6f17
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1191225121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1191225121
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_error_random.4107081296
Short name T711
Test name
Test status
Simulation time 211677846 ps
CPU time 18.95 seconds
Started Mar 12 01:02:48 PM PDT 24
Finished Mar 12 01:03:07 PM PDT 24
Peak memory 202856 kb
Host smart-04d2010e-87a4-49b1-9c33-7f695e2f6dff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4107081296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.4107081296
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random.1979314599
Short name T516
Test name
Test status
Simulation time 210024524 ps
CPU time 23.19 seconds
Started Mar 12 01:02:44 PM PDT 24
Finished Mar 12 01:03:08 PM PDT 24
Peak memory 204328 kb
Host smart-2cf4e586-b4fa-45e2-a1a1-39446953dbc3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1979314599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.1979314599
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_large_delays.698211060
Short name T202
Test name
Test status
Simulation time 24912523094 ps
CPU time 84.23 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:04:13 PM PDT 24
Peak memory 204168 kb
Host smart-01375da6-c041-4b22-888a-a13006bdb61b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=698211060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.698211060
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3450039468
Short name T333
Test name
Test status
Simulation time 4297080849 ps
CPU time 16.35 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:03:03 PM PDT 24
Peak memory 202968 kb
Host smart-ee41302e-46c5-40a3-823a-85781a87ea79
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3450039468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3450039468
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_random_zero_delays.3791068456
Short name T492
Test name
Test status
Simulation time 170621330 ps
CPU time 13.24 seconds
Started Mar 12 01:02:48 PM PDT 24
Finished Mar 12 01:03:02 PM PDT 24
Peak memory 204044 kb
Host smart-1a8771b5-b217-41b5-9f57-46a00fa03082
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791068456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3791068456
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_same_source.1673847766
Short name T857
Test name
Test status
Simulation time 130187570 ps
CPU time 2.54 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:02:45 PM PDT 24
Peak memory 203144 kb
Host smart-5b16a8b6-cfb5-4514-a0da-f9d1e4677c11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1673847766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1673847766
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke.735638370
Short name T63
Test name
Test status
Simulation time 22823390 ps
CPU time 2.01 seconds
Started Mar 12 01:02:50 PM PDT 24
Finished Mar 12 01:02:53 PM PDT 24
Peak memory 202836 kb
Host smart-8b918c8b-5d8b-4aaa-be2a-4d8c0d9588fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=735638370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.735638370
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_large_delays.2131704691
Short name T819
Test name
Test status
Simulation time 8685741110 ps
CPU time 31.18 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:03:16 PM PDT 24
Peak memory 202952 kb
Host smart-92bd8d5e-1aec-491a-a20d-ddeec2f14259
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131704691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2131704691
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2722373320
Short name T585
Test name
Test status
Simulation time 4232992795 ps
CPU time 34.16 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:03:20 PM PDT 24
Peak memory 202992 kb
Host smart-c81bc5e2-b810-4ccb-8db2-74d89d0a6c04
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2722373320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2722373320
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.2980089567
Short name T859
Test name
Test status
Simulation time 98932047 ps
CPU time 2.36 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:02:52 PM PDT 24
Peak memory 202808 kb
Host smart-a2dfde46-890d-4ca4-9506-e78f29b2ff57
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980089567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2980089567
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all.2215452934
Short name T663
Test name
Test status
Simulation time 1544127655 ps
CPU time 45.39 seconds
Started Mar 12 01:02:55 PM PDT 24
Finished Mar 12 01:03:41 PM PDT 24
Peak memory 205348 kb
Host smart-8bb861f1-9abd-47c4-9e46-cc52c9b4a38d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2215452934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2215452934
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2835158702
Short name T379
Test name
Test status
Simulation time 189419725 ps
CPU time 32.98 seconds
Started Mar 12 01:03:01 PM PDT 24
Finished Mar 12 01:03:34 PM PDT 24
Peak memory 205632 kb
Host smart-9d5c8c7e-b479-4f57-a56f-eebbf3d2014a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2835158702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_re
set_error.2835158702
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/15.xbar_unmapped_addr.1118300960
Short name T350
Test name
Test status
Simulation time 69566017 ps
CPU time 11.09 seconds
Started Mar 12 01:02:50 PM PDT 24
Finished Mar 12 01:03:02 PM PDT 24
Peak memory 204356 kb
Host smart-8d57294f-d0d5-43a8-b77d-a98f6942deee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1118300960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1118300960
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device.3146217643
Short name T806
Test name
Test status
Simulation time 527818124 ps
CPU time 24.12 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:03:12 PM PDT 24
Peak memory 205076 kb
Host smart-5775181e-5f6a-4547-92d5-0478fac2abe8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3146217643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3146217643
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.271176316
Short name T645
Test name
Test status
Simulation time 18660821998 ps
CPU time 69.26 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:03:57 PM PDT 24
Peak memory 210988 kb
Host smart-d6be1854-c41d-4ea0-9480-26cdddd2ef7e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=271176316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slo
w_rsp.271176316
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.93673413
Short name T865
Test name
Test status
Simulation time 169615983 ps
CPU time 7.23 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:02:55 PM PDT 24
Peak memory 203036 kb
Host smart-4ea7209d-b1c1-49aa-b5ba-782cf7e44d19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93673413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.93673413
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_error_random.1500868768
Short name T508
Test name
Test status
Simulation time 1953527927 ps
CPU time 30.85 seconds
Started Mar 12 01:02:50 PM PDT 24
Finished Mar 12 01:03:21 PM PDT 24
Peak memory 202928 kb
Host smart-d89648eb-2a4f-45d5-9803-2e1a889867bf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1500868768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1500868768
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random.438883775
Short name T524
Test name
Test status
Simulation time 570688045 ps
CPU time 6.29 seconds
Started Mar 12 01:02:51 PM PDT 24
Finished Mar 12 01:02:57 PM PDT 24
Peak memory 203640 kb
Host smart-8936c8a0-ee69-4bc3-8dcf-f8350ccff718
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=438883775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.438883775
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_large_delays.3962519830
Short name T466
Test name
Test status
Simulation time 40058024498 ps
CPU time 193.15 seconds
Started Mar 12 01:03:04 PM PDT 24
Finished Mar 12 01:06:23 PM PDT 24
Peak memory 211216 kb
Host smart-0cf86c26-fea0-4cc9-8fc7-bb7b7f454b17
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962519830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3962519830
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_slow_rsp.4040386283
Short name T195
Test name
Test status
Simulation time 26892718797 ps
CPU time 202.6 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:06:10 PM PDT 24
Peak memory 211036 kb
Host smart-ddb70ca7-27d0-467c-87b5-8381a5853c65
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4040386283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.4040386283
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_random_zero_delays.3035475035
Short name T370
Test name
Test status
Simulation time 143161764 ps
CPU time 11.13 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:02:57 PM PDT 24
Peak memory 204004 kb
Host smart-03b9d4f9-a982-44c5-930b-fa36d978cc1c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035475035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3035475035
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_same_source.2524606693
Short name T635
Test name
Test status
Simulation time 39533959 ps
CPU time 3.95 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:02:53 PM PDT 24
Peak memory 202956 kb
Host smart-14ad7d37-c731-4131-82ed-7bbb1f4d4604
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2524606693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2524606693
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke.2539752031
Short name T681
Test name
Test status
Simulation time 175777098 ps
CPU time 3.86 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:02:51 PM PDT 24
Peak memory 202672 kb
Host smart-053b03f6-9a94-491d-90ba-a8f7ff604079
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2539752031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2539752031
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1395293865
Short name T685
Test name
Test status
Simulation time 6609669002 ps
CPU time 33.87 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:03:23 PM PDT 24
Peak memory 203020 kb
Host smart-1c6a3169-cebd-471d-b00a-a74a8664941a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395293865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1395293865
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2164033489
Short name T846
Test name
Test status
Simulation time 3522605958 ps
CPU time 23.09 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:03:10 PM PDT 24
Peak memory 203024 kb
Host smart-7cf7e83f-747a-4837-91f4-087b4ce60767
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2164033489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2164033489
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.4023068268
Short name T2
Test name
Test status
Simulation time 32925531 ps
CPU time 2.21 seconds
Started Mar 12 01:02:49 PM PDT 24
Finished Mar 12 01:02:52 PM PDT 24
Peak memory 203220 kb
Host smart-cbaa354f-4044-4132-ae69-a52f37337670
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023068268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.4023068268
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all.3623941904
Short name T400
Test name
Test status
Simulation time 11987137620 ps
CPU time 236.92 seconds
Started Mar 12 01:02:51 PM PDT 24
Finished Mar 12 01:06:49 PM PDT 24
Peak memory 211124 kb
Host smart-be82abce-9310-4d5b-a071-ce355186cf09
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3623941904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3623941904
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1463991351
Short name T766
Test name
Test status
Simulation time 3763680909 ps
CPU time 53.06 seconds
Started Mar 12 01:02:56 PM PDT 24
Finished Mar 12 01:03:49 PM PDT 24
Peak memory 211160 kb
Host smart-fa937ae1-06df-4ae3-a3e0-0dc453846bbf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1463991351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1463991351
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4088268876
Short name T599
Test name
Test status
Simulation time 563463426 ps
CPU time 140.4 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:05:08 PM PDT 24
Peak memory 208536 kb
Host smart-db88ad13-e827-4f9f-a56b-c97fac3b5fc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4088268876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_ran
d_reset.4088268876
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.714450605
Short name T528
Test name
Test status
Simulation time 553289328 ps
CPU time 180.44 seconds
Started Mar 12 01:02:48 PM PDT 24
Finished Mar 12 01:05:48 PM PDT 24
Peak memory 211140 kb
Host smart-efb37176-4d6e-486b-bce7-f006a1b1e022
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=714450605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_res
et_error.714450605
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/16.xbar_unmapped_addr.663372938
Short name T428
Test name
Test status
Simulation time 765918041 ps
CPU time 23.97 seconds
Started Mar 12 01:02:44 PM PDT 24
Finished Mar 12 01:03:08 PM PDT 24
Peak memory 211052 kb
Host smart-0442b0c7-8c3b-4803-8d46-ea8f433713c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=663372938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.663372938
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device.2406722081
Short name T404
Test name
Test status
Simulation time 495483592 ps
CPU time 29.99 seconds
Started Mar 12 01:02:55 PM PDT 24
Finished Mar 12 01:03:30 PM PDT 24
Peak memory 204036 kb
Host smart-3f8db0b4-4829-409b-afa6-9d03c6e5acae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2406722081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2406722081
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1614588038
Short name T161
Test name
Test status
Simulation time 48077643081 ps
CPU time 342.88 seconds
Started Mar 12 01:03:05 PM PDT 24
Finished Mar 12 01:08:48 PM PDT 24
Peak memory 211180 kb
Host smart-98c6d721-6c53-4389-a8f2-61dcfd155295
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1614588038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_sl
ow_rsp.1614588038
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3766547622
Short name T310
Test name
Test status
Simulation time 704837656 ps
CPU time 19.22 seconds
Started Mar 12 01:02:55 PM PDT 24
Finished Mar 12 01:03:14 PM PDT 24
Peak memory 202964 kb
Host smart-af2763a4-4f4a-4de9-acdb-01224e77871b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3766547622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3766547622
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_error_random.1683229987
Short name T239
Test name
Test status
Simulation time 219479558 ps
CPU time 15.66 seconds
Started Mar 12 01:02:56 PM PDT 24
Finished Mar 12 01:03:11 PM PDT 24
Peak memory 202928 kb
Host smart-d6ee2092-2279-4f51-bc77-411e254cf6f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1683229987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1683229987
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random.354861844
Short name T639
Test name
Test status
Simulation time 1680229036 ps
CPU time 22.24 seconds
Started Mar 12 01:03:00 PM PDT 24
Finished Mar 12 01:03:22 PM PDT 24
Peak memory 204104 kb
Host smart-c5063ea6-a015-4245-8003-405e0b122422
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=354861844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.354861844
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_large_delays.2027500194
Short name T96
Test name
Test status
Simulation time 46327336641 ps
CPU time 136.52 seconds
Started Mar 12 01:02:58 PM PDT 24
Finished Mar 12 01:05:14 PM PDT 24
Peak memory 204388 kb
Host smart-77913880-c384-40f1-8d27-ce777688e5c3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027500194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2027500194
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_slow_rsp.4229478316
Short name T127
Test name
Test status
Simulation time 34109972107 ps
CPU time 107.86 seconds
Started Mar 12 01:02:57 PM PDT 24
Finished Mar 12 01:04:45 PM PDT 24
Peak memory 204148 kb
Host smart-fb9d5f57-9a67-49b6-b192-5611d929c402
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4229478316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.4229478316
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_random_zero_delays.585176462
Short name T384
Test name
Test status
Simulation time 66162141 ps
CPU time 5.37 seconds
Started Mar 12 01:02:59 PM PDT 24
Finished Mar 12 01:03:05 PM PDT 24
Peak memory 203720 kb
Host smart-0a35fa43-bdb5-4143-bdf1-3c3f2400bf96
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585176462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.585176462
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_same_source.1069501079
Short name T821
Test name
Test status
Simulation time 207590151 ps
CPU time 8.15 seconds
Started Mar 12 01:03:00 PM PDT 24
Finished Mar 12 01:03:09 PM PDT 24
Peak memory 202960 kb
Host smart-68b9adbd-ac55-4411-863b-3ebc0b5c3a7c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1069501079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1069501079
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke.2219350169
Short name T474
Test name
Test status
Simulation time 50043157 ps
CPU time 2.07 seconds
Started Mar 12 01:03:01 PM PDT 24
Finished Mar 12 01:03:03 PM PDT 24
Peak memory 202916 kb
Host smart-a5749902-080b-4028-961b-d1615ae068fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2219350169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2219350169
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3558778963
Short name T672
Test name
Test status
Simulation time 12325497045 ps
CPU time 28.36 seconds
Started Mar 12 01:03:13 PM PDT 24
Finished Mar 12 01:03:41 PM PDT 24
Peak memory 202964 kb
Host smart-573bd2e2-51c0-4150-a295-9acbb179b586
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558778963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3558778963
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.1694048364
Short name T883
Test name
Test status
Simulation time 3780395210 ps
CPU time 26.15 seconds
Started Mar 12 01:03:03 PM PDT 24
Finished Mar 12 01:03:29 PM PDT 24
Peak memory 203032 kb
Host smart-ee6d4d2c-e2ab-46ba-839d-2f0b2ef52480
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1694048364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1694048364
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2251941877
Short name T692
Test name
Test status
Simulation time 79211923 ps
CPU time 1.84 seconds
Started Mar 12 01:02:54 PM PDT 24
Finished Mar 12 01:02:56 PM PDT 24
Peak memory 202864 kb
Host smart-b1fe5eb6-f5e3-487c-b69a-f5df9f47bd91
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251941877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2251941877
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all.3108179985
Short name T140
Test name
Test status
Simulation time 5299696310 ps
CPU time 154.14 seconds
Started Mar 12 01:03:05 PM PDT 24
Finished Mar 12 01:05:39 PM PDT 24
Peak memory 208616 kb
Host smart-56a95bc0-50cc-4498-a216-6ac2002da932
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3108179985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3108179985
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_error.343331473
Short name T323
Test name
Test status
Simulation time 8015540403 ps
CPU time 46.07 seconds
Started Mar 12 01:02:56 PM PDT 24
Finished Mar 12 01:03:42 PM PDT 24
Peak memory 203012 kb
Host smart-1306996f-3972-4d09-b18c-b66084079a20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=343331473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.343331473
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.766834908
Short name T238
Test name
Test status
Simulation time 5307018382 ps
CPU time 297.08 seconds
Started Mar 12 01:03:10 PM PDT 24
Finished Mar 12 01:08:08 PM PDT 24
Peak memory 219424 kb
Host smart-28f929c0-6ed0-40c5-996d-bb6f8babf7cc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=766834908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_res
et_error.766834908
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/17.xbar_unmapped_addr.4288655996
Short name T232
Test name
Test status
Simulation time 934394747 ps
CPU time 21.06 seconds
Started Mar 12 01:03:00 PM PDT 24
Finished Mar 12 01:03:21 PM PDT 24
Peak memory 211136 kb
Host smart-ee470d7a-dcef-45d5-b38a-61292ba8ef0d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4288655996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.4288655996
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device.1150556232
Short name T397
Test name
Test status
Simulation time 232354601 ps
CPU time 35.18 seconds
Started Mar 12 01:03:05 PM PDT 24
Finished Mar 12 01:03:41 PM PDT 24
Peak memory 205584 kb
Host smart-d93cae86-8025-44f2-868d-b9fbcd5a0d1b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1150556232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1150556232
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.618945773
Short name T225
Test name
Test status
Simulation time 4813363727 ps
CPU time 39.99 seconds
Started Mar 12 01:03:07 PM PDT 24
Finished Mar 12 01:03:48 PM PDT 24
Peak memory 211140 kb
Host smart-95172582-6443-4a02-9c7d-f19ea4ccf46e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=618945773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slo
w_rsp.618945773
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3832988450
Short name T426
Test name
Test status
Simulation time 175597938 ps
CPU time 15.19 seconds
Started Mar 12 01:03:03 PM PDT 24
Finished Mar 12 01:03:19 PM PDT 24
Peak memory 203012 kb
Host smart-88e18159-e58e-4b86-8e7d-bc07c9bdad4b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3832988450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3832988450
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_error_random.4017310183
Short name T497
Test name
Test status
Simulation time 2067263552 ps
CPU time 30.68 seconds
Started Mar 12 01:02:55 PM PDT 24
Finished Mar 12 01:03:26 PM PDT 24
Peak memory 203008 kb
Host smart-f3621012-4bf7-46bd-b192-239a61aee92c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4017310183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.4017310183
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random.2588689174
Short name T652
Test name
Test status
Simulation time 462506449 ps
CPU time 10.34 seconds
Started Mar 12 01:03:07 PM PDT 24
Finished Mar 12 01:03:18 PM PDT 24
Peak memory 203604 kb
Host smart-b07df53c-a294-49d5-a074-9091516bd559
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2588689174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2588689174
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_large_delays.2458523701
Short name T618
Test name
Test status
Simulation time 82341956197 ps
CPU time 126.2 seconds
Started Mar 12 01:03:04 PM PDT 24
Finished Mar 12 01:05:11 PM PDT 24
Peak memory 204276 kb
Host smart-feb5707f-b5e8-440b-b8b1-5f1872080f23
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458523701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2458523701
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2524587975
Short name T312
Test name
Test status
Simulation time 15233244293 ps
CPU time 115.9 seconds
Started Mar 12 01:02:56 PM PDT 24
Finished Mar 12 01:04:58 PM PDT 24
Peak memory 211020 kb
Host smart-f70ca69f-860e-42b4-a1ea-d522b744de69
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2524587975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2524587975
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_random_zero_delays.2430912964
Short name T763
Test name
Test status
Simulation time 116292843 ps
CPU time 9.41 seconds
Started Mar 12 01:03:08 PM PDT 24
Finished Mar 12 01:03:23 PM PDT 24
Peak memory 203952 kb
Host smart-3357b55b-3575-4f84-a244-e9e067322c09
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430912964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2430912964
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_same_source.3812142666
Short name T283
Test name
Test status
Simulation time 171793546 ps
CPU time 8.64 seconds
Started Mar 12 01:03:07 PM PDT 24
Finished Mar 12 01:03:16 PM PDT 24
Peak memory 203532 kb
Host smart-7a09e28d-4905-4cb9-b07b-f5bb94f321f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3812142666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3812142666
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke.2475086422
Short name T707
Test name
Test status
Simulation time 334094430 ps
CPU time 3.35 seconds
Started Mar 12 01:02:57 PM PDT 24
Finished Mar 12 01:03:01 PM PDT 24
Peak memory 202864 kb
Host smart-10648196-3e89-48ac-be42-9299209b3c95
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2475086422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2475086422
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1196262768
Short name T274
Test name
Test status
Simulation time 5327596773 ps
CPU time 29.35 seconds
Started Mar 12 01:03:05 PM PDT 24
Finished Mar 12 01:03:34 PM PDT 24
Peak memory 202976 kb
Host smart-d0a0a55f-b19f-46ae-8e62-40a8dc7d248d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196262768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1196262768
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.3455645940
Short name T873
Test name
Test status
Simulation time 12181909501 ps
CPU time 39.5 seconds
Started Mar 12 01:03:01 PM PDT 24
Finished Mar 12 01:03:41 PM PDT 24
Peak memory 203020 kb
Host smart-a1e11d0a-2741-447d-9880-10eb234ae9f1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3455645940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3455645940
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.632549282
Short name T276
Test name
Test status
Simulation time 47762015 ps
CPU time 1.94 seconds
Started Mar 12 01:02:54 PM PDT 24
Finished Mar 12 01:02:56 PM PDT 24
Peak memory 202844 kb
Host smart-2ad1346a-d72d-43ca-9e35-49ff7d24f15b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632549282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.632549282
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all.3191704341
Short name T136
Test name
Test status
Simulation time 8416354776 ps
CPU time 218.07 seconds
Started Mar 12 01:03:04 PM PDT 24
Finished Mar 12 01:06:42 PM PDT 24
Peak memory 209040 kb
Host smart-e7f07956-f663-4bd5-a69e-1e934b99d8d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3191704341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3191704341
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_error.2671307557
Short name T668
Test name
Test status
Simulation time 5110239316 ps
CPU time 134.36 seconds
Started Mar 12 01:02:58 PM PDT 24
Finished Mar 12 01:05:14 PM PDT 24
Peak memory 208072 kb
Host smart-9a0d1bed-952a-48e6-a0eb-c47ed7ca9f68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2671307557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2671307557
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.3934167688
Short name T782
Test name
Test status
Simulation time 701909150 ps
CPU time 102.76 seconds
Started Mar 12 01:02:58 PM PDT 24
Finished Mar 12 01:04:41 PM PDT 24
Peak memory 207100 kb
Host smart-32c64681-deea-430c-b7b8-55a627288729
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3934167688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_ran
d_reset.3934167688
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3926024909
Short name T268
Test name
Test status
Simulation time 3767952117 ps
CPU time 176.5 seconds
Started Mar 12 01:03:03 PM PDT 24
Finished Mar 12 01:06:00 PM PDT 24
Peak memory 210128 kb
Host smart-68d32ce9-fe2d-45ef-a91d-117e96637397
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3926024909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_re
set_error.3926024909
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/18.xbar_unmapped_addr.36662942
Short name T330
Test name
Test status
Simulation time 196854972 ps
CPU time 6.58 seconds
Started Mar 12 01:03:06 PM PDT 24
Finished Mar 12 01:03:13 PM PDT 24
Peak memory 211072 kb
Host smart-629e8533-1197-4035-8c1d-bfa11fabcf33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36662942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.36662942
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device.3511600494
Short name T539
Test name
Test status
Simulation time 1467240805 ps
CPU time 25.18 seconds
Started Mar 12 01:02:56 PM PDT 24
Finished Mar 12 01:03:21 PM PDT 24
Peak memory 204144 kb
Host smart-ec8037ab-07b2-4d89-96cd-394f1724fafb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3511600494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3511600494
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3835701304
Short name T251
Test name
Test status
Simulation time 11289816705 ps
CPU time 88.37 seconds
Started Mar 12 01:03:08 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 211076 kb
Host smart-04584b0a-e834-4ee8-b2c6-350d4e521d50
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3835701304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_sl
ow_rsp.3835701304
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.890427964
Short name T301
Test name
Test status
Simulation time 529657243 ps
CPU time 20.18 seconds
Started Mar 12 01:03:08 PM PDT 24
Finished Mar 12 01:03:29 PM PDT 24
Peak memory 202848 kb
Host smart-5b20e341-559b-49f0-b0bd-e9ab1aa0147e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=890427964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.890427964
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_error_random.1696806843
Short name T754
Test name
Test status
Simulation time 116768767 ps
CPU time 17.11 seconds
Started Mar 12 01:03:02 PM PDT 24
Finished Mar 12 01:03:19 PM PDT 24
Peak memory 202904 kb
Host smart-73f780e8-774e-4181-8df3-b9735d122a4f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1696806843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1696806843
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random.1116302239
Short name T284
Test name
Test status
Simulation time 176159065 ps
CPU time 10.05 seconds
Started Mar 12 01:03:06 PM PDT 24
Finished Mar 12 01:03:17 PM PDT 24
Peak memory 203932 kb
Host smart-ddf4d25e-f405-4832-b483-2a6550b24520
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1116302239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1116302239
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_large_delays.2292145018
Short name T186
Test name
Test status
Simulation time 10567046973 ps
CPU time 57.6 seconds
Started Mar 12 01:02:58 PM PDT 24
Finished Mar 12 01:03:56 PM PDT 24
Peak memory 211188 kb
Host smart-e641241d-a19b-49f1-a04d-a393c2879332
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292145018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2292145018
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2921862221
Short name T598
Test name
Test status
Simulation time 85849254586 ps
CPU time 238.72 seconds
Started Mar 12 01:03:12 PM PDT 24
Finished Mar 12 01:07:11 PM PDT 24
Peak memory 204700 kb
Host smart-41a3c210-3157-495d-b456-70af8c82df9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2921862221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2921862221
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_random_zero_delays.1286029481
Short name T609
Test name
Test status
Simulation time 807691926 ps
CPU time 22.95 seconds
Started Mar 12 01:02:58 PM PDT 24
Finished Mar 12 01:03:21 PM PDT 24
Peak memory 204296 kb
Host smart-dba34d6a-d85b-4402-b090-17e3c28a0aa6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286029481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1286029481
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_same_source.2492817724
Short name T628
Test name
Test status
Simulation time 1345599751 ps
CPU time 24.18 seconds
Started Mar 12 01:02:57 PM PDT 24
Finished Mar 12 01:03:21 PM PDT 24
Peak memory 203124 kb
Host smart-9bd5b274-ef85-4a07-86f1-430a9f94957b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2492817724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2492817724
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke.2548416069
Short name T227
Test name
Test status
Simulation time 101685253 ps
CPU time 2.85 seconds
Started Mar 12 01:03:08 PM PDT 24
Finished Mar 12 01:03:11 PM PDT 24
Peak memory 202792 kb
Host smart-450dbaac-ab92-47a9-8870-df8222baff8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2548416069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2548416069
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_large_delays.844812677
Short name T686
Test name
Test status
Simulation time 13734486402 ps
CPU time 28.51 seconds
Started Mar 12 01:03:04 PM PDT 24
Finished Mar 12 01:03:33 PM PDT 24
Peak memory 203000 kb
Host smart-7e985ab8-b24e-4da7-8ec8-4598d1009e16
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=844812677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.844812677
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.1881308396
Short name T611
Test name
Test status
Simulation time 3096346779 ps
CPU time 21.97 seconds
Started Mar 12 01:03:05 PM PDT 24
Finished Mar 12 01:03:27 PM PDT 24
Peak memory 202984 kb
Host smart-3ffb8681-2bc0-421d-986d-84efc0224eb8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1881308396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1881308396
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.2687601136
Short name T335
Test name
Test status
Simulation time 52720631 ps
CPU time 2.1 seconds
Started Mar 12 01:03:09 PM PDT 24
Finished Mar 12 01:03:12 PM PDT 24
Peak memory 202904 kb
Host smart-ec8b82c5-5b47-4573-bdfc-214cb89a1691
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687601136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.2687601136
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all.3549454629
Short name T783
Test name
Test status
Simulation time 13043649667 ps
CPU time 286.33 seconds
Started Mar 12 01:03:07 PM PDT 24
Finished Mar 12 01:07:53 PM PDT 24
Peak memory 210480 kb
Host smart-c109a3dd-76f9-4b99-8caf-068c1e65faa1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3549454629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3549454629
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_error.4106256874
Short name T256
Test name
Test status
Simulation time 8355917931 ps
CPU time 218.56 seconds
Started Mar 12 01:03:10 PM PDT 24
Finished Mar 12 01:06:54 PM PDT 24
Peak memory 210220 kb
Host smart-84338b65-3e47-422c-aeea-345196bc061e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4106256874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.4106256874
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1608326772
Short name T626
Test name
Test status
Simulation time 243992557 ps
CPU time 66.43 seconds
Started Mar 12 01:02:59 PM PDT 24
Finished Mar 12 01:04:06 PM PDT 24
Peak memory 206304 kb
Host smart-7c6f4ab8-62d7-41f1-a71d-b4c9f57a615b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1608326772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_ran
d_reset.1608326772
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.159295706
Short name T595
Test name
Test status
Simulation time 6798243145 ps
CPU time 221.28 seconds
Started Mar 12 01:03:09 PM PDT 24
Finished Mar 12 01:06:51 PM PDT 24
Peak memory 211148 kb
Host smart-f54ccff0-1b0f-4b57-8adb-b2a2a9045b65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=159295706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_res
et_error.159295706
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/19.xbar_unmapped_addr.2006590299
Short name T761
Test name
Test status
Simulation time 108340381 ps
CPU time 13.84 seconds
Started Mar 12 01:02:57 PM PDT 24
Finished Mar 12 01:03:11 PM PDT 24
Peak memory 204548 kb
Host smart-43e50f48-26c6-47c3-9466-e44a858b66a2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2006590299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2006590299
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device.2135866191
Short name T507
Test name
Test status
Simulation time 1375456272 ps
CPU time 44.85 seconds
Started Mar 12 01:02:20 PM PDT 24
Finished Mar 12 01:03:05 PM PDT 24
Peak memory 211088 kb
Host smart-7d860101-d9be-4089-b56b-f2be4daeef33
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2135866191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2135866191
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1101462430
Short name T180
Test name
Test status
Simulation time 14371123817 ps
CPU time 130.44 seconds
Started Mar 12 01:02:21 PM PDT 24
Finished Mar 12 01:04:31 PM PDT 24
Peak memory 205364 kb
Host smart-76d24f6b-b6bf-4343-a5f2-a91a95c6ccc4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1101462430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slo
w_rsp.1101462430
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.424212944
Short name T772
Test name
Test status
Simulation time 223694600 ps
CPU time 5.17 seconds
Started Mar 12 01:02:01 PM PDT 24
Finished Mar 12 01:02:12 PM PDT 24
Peak memory 202896 kb
Host smart-8340fd93-47c9-4434-8c59-c96751cf8a4d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=424212944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.424212944
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_error_random.2822898389
Short name T764
Test name
Test status
Simulation time 2039046453 ps
CPU time 27.65 seconds
Started Mar 12 01:02:20 PM PDT 24
Finished Mar 12 01:02:48 PM PDT 24
Peak memory 202932 kb
Host smart-b431194f-b8c9-4640-b537-a41fe4070cd1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2822898389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2822898389
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random.210177588
Short name T594
Test name
Test status
Simulation time 129917213 ps
CPU time 14.66 seconds
Started Mar 12 01:02:12 PM PDT 24
Finished Mar 12 01:02:27 PM PDT 24
Peak memory 204036 kb
Host smart-b3b8fbe2-27b4-4521-8109-ffc7515567cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=210177588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.210177588
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_large_delays.3890731011
Short name T559
Test name
Test status
Simulation time 41528105440 ps
CPU time 210.96 seconds
Started Mar 12 01:02:24 PM PDT 24
Finished Mar 12 01:05:55 PM PDT 24
Peak memory 204980 kb
Host smart-fbe217c0-5253-4c1e-9599-6e7b2cc16d09
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890731011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3890731011
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2488624210
Short name T219
Test name
Test status
Simulation time 73268387685 ps
CPU time 309.21 seconds
Started Mar 12 01:02:25 PM PDT 24
Finished Mar 12 01:07:35 PM PDT 24
Peak memory 211184 kb
Host smart-198255bd-ecdd-4181-8d12-8cff67f2f005
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2488624210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2488624210
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_random_zero_delays.2850230907
Short name T9
Test name
Test status
Simulation time 28407701 ps
CPU time 2.01 seconds
Started Mar 12 01:02:09 PM PDT 24
Finished Mar 12 01:02:12 PM PDT 24
Peak memory 203140 kb
Host smart-30b8ee96-9e8e-49e0-a88f-528973002743
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850230907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2850230907
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_same_source.3350079265
Short name T565
Test name
Test status
Simulation time 315214804 ps
CPU time 15.48 seconds
Started Mar 12 01:02:24 PM PDT 24
Finished Mar 12 01:02:40 PM PDT 24
Peak memory 202952 kb
Host smart-ffd0aea8-4124-40e1-8075-3719a7aa720f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3350079265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3350079265
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke.4056879091
Short name T691
Test name
Test status
Simulation time 149481971 ps
CPU time 3.42 seconds
Started Mar 12 01:02:32 PM PDT 24
Finished Mar 12 01:02:35 PM PDT 24
Peak memory 202964 kb
Host smart-a1c8625b-6321-4a3f-9b8d-3e46b1dbe408
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4056879091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.4056879091
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_large_delays.4218872933
Short name T590
Test name
Test status
Simulation time 9244267807 ps
CPU time 33.75 seconds
Started Mar 12 01:02:14 PM PDT 24
Finished Mar 12 01:02:47 PM PDT 24
Peak memory 203056 kb
Host smart-f3f6a9a1-6d08-4daa-ac23-b7cdf52a0219
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218872933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4218872933
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.769781089
Short name T832
Test name
Test status
Simulation time 5404737917 ps
CPU time 32.63 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:54 PM PDT 24
Peak memory 202864 kb
Host smart-71b7ad79-5485-409a-83ff-94e33688f347
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=769781089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.769781089
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.3895189969
Short name T399
Test name
Test status
Simulation time 38534245 ps
CPU time 2.41 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:24 PM PDT 24
Peak memory 202888 kb
Host smart-8d53c686-602f-44ad-b3a7-55dc10dc7936
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895189969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3895189969
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all.3854601419
Short name T119
Test name
Test status
Simulation time 3326644327 ps
CPU time 126.83 seconds
Started Mar 12 01:02:05 PM PDT 24
Finished Mar 12 01:04:12 PM PDT 24
Peak memory 211148 kb
Host smart-46fe3d49-0f82-473d-a59f-2a3ca0d85381
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3854601419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3854601419
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3054000198
Short name T243
Test name
Test status
Simulation time 5070644535 ps
CPU time 98.52 seconds
Started Mar 12 01:02:25 PM PDT 24
Finished Mar 12 01:04:03 PM PDT 24
Peak memory 205772 kb
Host smart-920bd856-5590-4624-9284-18505424ab20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3054000198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3054000198
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.983392961
Short name T76
Test name
Test status
Simulation time 13488516013 ps
CPU time 450.22 seconds
Started Mar 12 01:02:21 PM PDT 24
Finished Mar 12 01:09:51 PM PDT 24
Peak memory 208016 kb
Host smart-03f20083-cf5f-4129-8977-99d855a00331
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=983392961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_
reset.983392961
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.666447562
Short name T564
Test name
Test status
Simulation time 275575375 ps
CPU time 90.63 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:03:52 PM PDT 24
Peak memory 208452 kb
Host smart-2497bd6b-7a7a-42e1-9b60-4cffc1e3e9ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=666447562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rese
t_error.666447562
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/2.xbar_unmapped_addr.173937863
Short name T563
Test name
Test status
Simulation time 49134907 ps
CPU time 6.24 seconds
Started Mar 12 01:02:16 PM PDT 24
Finished Mar 12 01:02:22 PM PDT 24
Peak memory 204232 kb
Host smart-841dc490-6ea6-455a-84b0-4776fac3fba2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=173937863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.173937863
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_access_same_device.4005609097
Short name T181
Test name
Test status
Simulation time 1714400023 ps
CPU time 58.8 seconds
Started Mar 12 01:02:57 PM PDT 24
Finished Mar 12 01:03:56 PM PDT 24
Peak memory 211152 kb
Host smart-4443bd28-705a-4706-bd81-d7769329e80c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4005609097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.4005609097
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.4176618293
Short name T500
Test name
Test status
Simulation time 126254526 ps
CPU time 7.62 seconds
Started Mar 12 01:02:58 PM PDT 24
Finished Mar 12 01:03:05 PM PDT 24
Peak memory 202956 kb
Host smart-2667688c-8944-45dd-8dfe-bc56805f6a5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4176618293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.4176618293
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_error_random.1437940992
Short name T511
Test name
Test status
Simulation time 1320580977 ps
CPU time 13.42 seconds
Started Mar 12 01:03:09 PM PDT 24
Finished Mar 12 01:03:23 PM PDT 24
Peak memory 202880 kb
Host smart-4788c8c6-cf9e-4018-8e14-68d6df894b5e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1437940992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1437940992
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random.3285972618
Short name T753
Test name
Test status
Simulation time 161157206 ps
CPU time 5.8 seconds
Started Mar 12 01:03:08 PM PDT 24
Finished Mar 12 01:03:15 PM PDT 24
Peak memory 204024 kb
Host smart-c7f140f2-7b44-472c-9e13-77c7fdd4b04e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3285972618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3285972618
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_large_delays.4240824445
Short name T42
Test name
Test status
Simulation time 62059358771 ps
CPU time 234.79 seconds
Started Mar 12 01:02:57 PM PDT 24
Finished Mar 12 01:06:52 PM PDT 24
Peak memory 211216 kb
Host smart-e9e97cc5-f9b2-4097-b774-bbd6c0dfe8cb
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240824445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.4240824445
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_slow_rsp.303640871
Short name T898
Test name
Test status
Simulation time 20288712163 ps
CPU time 167.77 seconds
Started Mar 12 01:02:56 PM PDT 24
Finished Mar 12 01:05:44 PM PDT 24
Peak memory 204328 kb
Host smart-a5e9bb27-10be-4534-992a-64261e9d7115
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=303640871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.303640871
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_random_zero_delays.1103709780
Short name T834
Test name
Test status
Simulation time 221216765 ps
CPU time 15.44 seconds
Started Mar 12 01:03:03 PM PDT 24
Finished Mar 12 01:03:19 PM PDT 24
Peak memory 204136 kb
Host smart-eb92d8d1-d933-4d9b-a1d8-af7ecbbb66c6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103709780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1103709780
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_same_source.2637900559
Short name T560
Test name
Test status
Simulation time 108625168 ps
CPU time 3.37 seconds
Started Mar 12 01:03:02 PM PDT 24
Finished Mar 12 01:03:05 PM PDT 24
Peak memory 202916 kb
Host smart-9e0537f2-8bd8-4c18-896c-841fca14e705
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2637900559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2637900559
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke.2457293116
Short name T502
Test name
Test status
Simulation time 112605387 ps
CPU time 3.3 seconds
Started Mar 12 01:03:08 PM PDT 24
Finished Mar 12 01:03:11 PM PDT 24
Peak memory 202900 kb
Host smart-c0a63b34-8c72-443b-a7c1-dd00d974143d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2457293116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2457293116
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1618019062
Short name T90
Test name
Test status
Simulation time 32403593077 ps
CPU time 48.48 seconds
Started Mar 12 01:03:09 PM PDT 24
Finished Mar 12 01:03:58 PM PDT 24
Peak memory 202900 kb
Host smart-ae6dca72-b635-461d-8d2c-999b0128285a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618019062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1618019062
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.1934060504
Short name T842
Test name
Test status
Simulation time 7621537557 ps
CPU time 32.93 seconds
Started Mar 12 01:03:08 PM PDT 24
Finished Mar 12 01:03:41 PM PDT 24
Peak memory 202852 kb
Host smart-a318a8f1-f516-4ef0-ba4f-a5cc89393a6e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1934060504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1934060504
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.3140566851
Short name T608
Test name
Test status
Simulation time 99914217 ps
CPU time 2.26 seconds
Started Mar 12 01:03:09 PM PDT 24
Finished Mar 12 01:03:12 PM PDT 24
Peak memory 202856 kb
Host smart-facd3d64-7c26-4b91-83a1-5ce9c8dbacc8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140566851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.3140566851
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all.2078126879
Short name T141
Test name
Test status
Simulation time 14305036743 ps
CPU time 252.65 seconds
Started Mar 12 01:02:55 PM PDT 24
Finished Mar 12 01:07:08 PM PDT 24
Peak memory 206920 kb
Host smart-167d10be-fe13-4bfc-875a-d79188eb8902
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2078126879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2078126879
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_error.873141490
Short name T154
Test name
Test status
Simulation time 9145948931 ps
CPU time 143.34 seconds
Started Mar 12 01:03:03 PM PDT 24
Finished Mar 12 01:05:27 PM PDT 24
Peak memory 206412 kb
Host smart-6c8a8dfc-877e-413e-abd4-d0408b841a5d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=873141490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.873141490
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.3920496997
Short name T523
Test name
Test status
Simulation time 6057209555 ps
CPU time 343.22 seconds
Started Mar 12 01:02:55 PM PDT 24
Finished Mar 12 01:08:39 PM PDT 24
Peak memory 208172 kb
Host smart-f53f3753-f924-434e-9e5f-f01a8c85b5b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3920496997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_ran
d_reset.3920496997
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3421658171
Short name T424
Test name
Test status
Simulation time 1482827861 ps
CPU time 161.67 seconds
Started Mar 12 01:03:09 PM PDT 24
Finished Mar 12 01:05:51 PM PDT 24
Peak memory 210016 kb
Host smart-4288e657-6760-436d-a3fa-33301dfaf1fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3421658171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_re
set_error.3421658171
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/20.xbar_unmapped_addr.2555627572
Short name T762
Test name
Test status
Simulation time 113361621 ps
CPU time 3.76 seconds
Started Mar 12 01:02:58 PM PDT 24
Finished Mar 12 01:03:03 PM PDT 24
Peak memory 203684 kb
Host smart-9ba0b324-2782-4625-a0d9-e31936ae7e12
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2555627572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2555627572
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device.2703421339
Short name T70
Test name
Test status
Simulation time 261713145 ps
CPU time 10.5 seconds
Started Mar 12 01:03:24 PM PDT 24
Finished Mar 12 01:03:36 PM PDT 24
Peak memory 202828 kb
Host smart-b5002bf3-5555-4957-b780-75b1e729a8d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2703421339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.2703421339
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1054474121
Short name T820
Test name
Test status
Simulation time 55107113809 ps
CPU time 527.79 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:12:15 PM PDT 24
Peak memory 206820 kb
Host smart-4130a085-1cae-4846-8d09-0eeb66ea2354
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1054474121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_sl
ow_rsp.1054474121
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.1709052536
Short name T551
Test name
Test status
Simulation time 2459546552 ps
CPU time 30.31 seconds
Started Mar 12 01:03:10 PM PDT 24
Finished Mar 12 01:03:40 PM PDT 24
Peak memory 202984 kb
Host smart-b6fa12e9-29a5-4588-8b7d-97c752560ba4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1709052536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1709052536
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_error_random.1209449248
Short name T298
Test name
Test status
Simulation time 134204269 ps
CPU time 11.9 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:03:44 PM PDT 24
Peak memory 202972 kb
Host smart-d87e8d44-3cbb-4fe7-99b8-387c8cf1ffc0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1209449248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1209449248
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random.1947505232
Short name T465
Test name
Test status
Simulation time 135172691 ps
CPU time 4.1 seconds
Started Mar 12 01:03:09 PM PDT 24
Finished Mar 12 01:03:14 PM PDT 24
Peak memory 202184 kb
Host smart-09b71b01-8915-433f-97c9-83a9f7aff49a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1947505232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1947505232
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_large_delays.2105864099
Short name T815
Test name
Test status
Simulation time 48870601540 ps
CPU time 227.55 seconds
Started Mar 12 01:03:03 PM PDT 24
Finished Mar 12 01:06:51 PM PDT 24
Peak memory 204408 kb
Host smart-9445b3f3-cef3-4470-b83d-d6679dd1bfa2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105864099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2105864099
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_slow_rsp.2494566515
Short name T555
Test name
Test status
Simulation time 25422978636 ps
CPU time 174.3 seconds
Started Mar 12 01:03:26 PM PDT 24
Finished Mar 12 01:06:21 PM PDT 24
Peak memory 211036 kb
Host smart-43bdea6c-34db-485a-b909-310ba571f427
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2494566515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2494566515
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_random_zero_delays.1842188640
Short name T431
Test name
Test status
Simulation time 155319254 ps
CPU time 14.1 seconds
Started Mar 12 01:02:58 PM PDT 24
Finished Mar 12 01:03:12 PM PDT 24
Peak memory 203980 kb
Host smart-283ad49c-fdde-4ce3-ae24-b13f1f214570
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842188640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1842188640
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_same_source.3591584593
Short name T533
Test name
Test status
Simulation time 2791035824 ps
CPU time 16.66 seconds
Started Mar 12 01:03:24 PM PDT 24
Finished Mar 12 01:03:42 PM PDT 24
Peak memory 203004 kb
Host smart-e525b9d2-3540-4210-8a52-888025ef3c52
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3591584593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3591584593
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke.1285866009
Short name T364
Test name
Test status
Simulation time 152764915 ps
CPU time 3.42 seconds
Started Mar 12 01:03:10 PM PDT 24
Finished Mar 12 01:03:14 PM PDT 24
Peak memory 202836 kb
Host smart-6749705a-39b7-4089-980e-6fd6817be18b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1285866009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1285866009
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3348275530
Short name T676
Test name
Test status
Simulation time 18445375448 ps
CPU time 39.14 seconds
Started Mar 12 01:03:07 PM PDT 24
Finished Mar 12 01:03:46 PM PDT 24
Peak memory 202964 kb
Host smart-b22cb8c8-52d9-4f65-8084-6c593878285d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348275530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3348275530
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1048694236
Short name T784
Test name
Test status
Simulation time 4076832357 ps
CPU time 22.53 seconds
Started Mar 12 01:02:59 PM PDT 24
Finished Mar 12 01:03:22 PM PDT 24
Peak memory 202988 kb
Host smart-d17fee4c-857f-49fd-96ae-05b1c2e63787
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1048694236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1048694236
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2337938540
Short name T512
Test name
Test status
Simulation time 42909056 ps
CPU time 2.1 seconds
Started Mar 12 01:03:10 PM PDT 24
Finished Mar 12 01:03:13 PM PDT 24
Peak memory 202828 kb
Host smart-b7c975a5-b975-4db9-8a34-5c141768d1f8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337938540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2337938540
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all.3022399342
Short name T375
Test name
Test status
Simulation time 3995916769 ps
CPU time 72.01 seconds
Started Mar 12 01:03:22 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 204420 kb
Host smart-fa9e560c-8a12-4d3f-9afb-810e2b2afada
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3022399342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3022399342
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_error.957712240
Short name T374
Test name
Test status
Simulation time 9690361907 ps
CPU time 162.38 seconds
Started Mar 12 01:03:21 PM PDT 24
Finished Mar 12 01:06:03 PM PDT 24
Peak memory 207792 kb
Host smart-6ee6c433-7b1e-41fa-abd2-9e4b3d493b29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=957712240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.957712240
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.712822845
Short name T462
Test name
Test status
Simulation time 2531459412 ps
CPU time 168.18 seconds
Started Mar 12 01:03:20 PM PDT 24
Finished Mar 12 01:06:09 PM PDT 24
Peak memory 205952 kb
Host smart-b8fdd924-5608-45d9-a8e0-ec0ad184233c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=712822845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand
_reset.712822845
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.4037552435
Short name T265
Test name
Test status
Simulation time 748422939 ps
CPU time 199.94 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:06:47 PM PDT 24
Peak memory 210804 kb
Host smart-983f4e8d-d79c-4aa7-a44c-70859e27478d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4037552435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_re
set_error.4037552435
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/21.xbar_unmapped_addr.429627854
Short name T514
Test name
Test status
Simulation time 1081422191 ps
CPU time 21 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:03:49 PM PDT 24
Peak memory 204072 kb
Host smart-579a160a-58ee-4857-92ce-88016a8f9a79
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=429627854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.429627854
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device.308679785
Short name T87
Test name
Test status
Simulation time 648357757 ps
CPU time 42.03 seconds
Started Mar 12 01:03:26 PM PDT 24
Finished Mar 12 01:04:09 PM PDT 24
Peak memory 204708 kb
Host smart-c3edb1e7-61c7-4332-9fe7-7a7740215602
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=308679785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.308679785
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1143018257
Short name T848
Test name
Test status
Simulation time 108571077150 ps
CPU time 343.37 seconds
Started Mar 12 01:03:26 PM PDT 24
Finished Mar 12 01:09:09 PM PDT 24
Peak memory 211108 kb
Host smart-01315871-8c23-49cf-af91-f6bff4f382de
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1143018257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_sl
ow_rsp.1143018257
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4130148203
Short name T255
Test name
Test status
Simulation time 1987919214 ps
CPU time 17.45 seconds
Started Mar 12 01:03:22 PM PDT 24
Finished Mar 12 01:03:41 PM PDT 24
Peak memory 202896 kb
Host smart-a1757032-7ce0-4f37-a92c-660c41d896c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4130148203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.4130148203
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_error_random.4212136918
Short name T787
Test name
Test status
Simulation time 166910035 ps
CPU time 21.45 seconds
Started Mar 12 01:03:09 PM PDT 24
Finished Mar 12 01:03:31 PM PDT 24
Peak memory 202988 kb
Host smart-28acdb08-adff-4fc2-a0e6-5b72bbe1bb46
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4212136918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.4212136918
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random.685176996
Short name T293
Test name
Test status
Simulation time 128225932 ps
CPU time 5.19 seconds
Started Mar 12 01:03:25 PM PDT 24
Finished Mar 12 01:03:31 PM PDT 24
Peak memory 203528 kb
Host smart-bc664c82-1788-48e4-82e5-94638d513b98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=685176996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.685176996
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_slow_rsp.406708304
Short name T866
Test name
Test status
Simulation time 78584848885 ps
CPU time 201.27 seconds
Started Mar 12 01:03:25 PM PDT 24
Finished Mar 12 01:06:47 PM PDT 24
Peak memory 211220 kb
Host smart-d28020e3-37cc-4c5d-a005-2c52da33c2d0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=406708304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.406708304
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_random_zero_delays.2856227023
Short name T371
Test name
Test status
Simulation time 183804116 ps
CPU time 19.91 seconds
Started Mar 12 01:03:31 PM PDT 24
Finished Mar 12 01:03:52 PM PDT 24
Peak memory 204020 kb
Host smart-3d1d4e04-01d8-4448-9553-4d1c56da9772
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856227023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.2856227023
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_same_source.400690058
Short name T19
Test name
Test status
Simulation time 307233707 ps
CPU time 10.99 seconds
Started Mar 12 01:03:24 PM PDT 24
Finished Mar 12 01:03:37 PM PDT 24
Peak memory 202932 kb
Host smart-ad57ee65-fcf4-499c-8f95-3235c866b4c6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=400690058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.400690058
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke.331781859
Short name T556
Test name
Test status
Simulation time 37998331 ps
CPU time 2.4 seconds
Started Mar 12 01:03:11 PM PDT 24
Finished Mar 12 01:03:19 PM PDT 24
Peak memory 202936 kb
Host smart-496ff179-4c01-462a-85d7-cd33c7659bd8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=331781859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.331781859
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1089676148
Short name T174
Test name
Test status
Simulation time 4744314196 ps
CPU time 23.38 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:03:51 PM PDT 24
Peak memory 203020 kb
Host smart-94c56a40-1c18-497e-9811-3f8661eb20c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089676148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1089676148
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.1198494146
Short name T845
Test name
Test status
Simulation time 4866140328 ps
CPU time 25.78 seconds
Started Mar 12 01:03:23 PM PDT 24
Finished Mar 12 01:03:51 PM PDT 24
Peak memory 202984 kb
Host smart-d31e725b-85a3-45c9-ae91-22d205099c39
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1198494146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1198494146
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.2989336871
Short name T65
Test name
Test status
Simulation time 62490844 ps
CPU time 2.09 seconds
Started Mar 12 01:03:23 PM PDT 24
Finished Mar 12 01:03:27 PM PDT 24
Peak memory 202816 kb
Host smart-e1089a0f-5a54-4ec4-bb76-c7f0065663f9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989336871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.2989336871
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3392067126
Short name T719
Test name
Test status
Simulation time 2178585014 ps
CPU time 94.43 seconds
Started Mar 12 01:03:09 PM PDT 24
Finished Mar 12 01:04:45 PM PDT 24
Peak memory 205480 kb
Host smart-90680c56-3a7e-48d5-be85-cad83dc0f2c3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3392067126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3392067126
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.2010868439
Short name T137
Test name
Test status
Simulation time 10585245888 ps
CPU time 615.55 seconds
Started Mar 12 01:03:28 PM PDT 24
Finished Mar 12 01:13:44 PM PDT 24
Peak memory 207732 kb
Host smart-a71615c0-a978-4108-a1a8-6d5fbe70948c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2010868439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_ran
d_reset.2010868439
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2893845967
Short name T258
Test name
Test status
Simulation time 114504132 ps
CPU time 21.64 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:03:57 PM PDT 24
Peak memory 204452 kb
Host smart-155069db-a55e-4e48-9df2-26f3b2f91455
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2893845967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_re
set_error.2893845967
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/22.xbar_unmapped_addr.1203222981
Short name T206
Test name
Test status
Simulation time 285134074 ps
CPU time 8.24 seconds
Started Mar 12 01:03:23 PM PDT 24
Finished Mar 12 01:03:33 PM PDT 24
Peak memory 211104 kb
Host smart-51fecaf8-b97a-4c1f-befd-cef6c084f0e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1203222981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1203222981
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device.1979727787
Short name T535
Test name
Test status
Simulation time 131313553 ps
CPU time 4.74 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:03:37 PM PDT 24
Peak memory 202972 kb
Host smart-09f5293c-480b-445d-8604-d3d88a351848
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1979727787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.1979727787
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.2136542043
Short name T805
Test name
Test status
Simulation time 87748720799 ps
CPU time 584.29 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:13:16 PM PDT 24
Peak memory 205388 kb
Host smart-6a62deb9-cb45-46a6-867f-db5ac1ec5fcd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2136542043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_sl
ow_rsp.2136542043
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.2984022208
Short name T355
Test name
Test status
Simulation time 109900881 ps
CPU time 2.43 seconds
Started Mar 12 01:03:10 PM PDT 24
Finished Mar 12 01:03:13 PM PDT 24
Peak memory 202948 kb
Host smart-a17f13f9-6d68-4dc0-9b6d-a6ed3e7aae08
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2984022208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.2984022208
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_error_random.2317195533
Short name T93
Test name
Test status
Simulation time 20037451 ps
CPU time 1.81 seconds
Started Mar 12 01:03:22 PM PDT 24
Finished Mar 12 01:03:25 PM PDT 24
Peak memory 202932 kb
Host smart-27938a0f-43c0-4b79-8c03-6a54c9558a26
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2317195533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2317195533
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random.1524962612
Short name T173
Test name
Test status
Simulation time 689211217 ps
CPU time 19.86 seconds
Started Mar 12 01:03:14 PM PDT 24
Finished Mar 12 01:03:34 PM PDT 24
Peak memory 204016 kb
Host smart-b6c19fcd-6e33-4060-bb1a-a1b383bef55b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1524962612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1524962612
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_large_delays.2158400827
Short name T831
Test name
Test status
Simulation time 98567505528 ps
CPU time 241.13 seconds
Started Mar 12 01:03:23 PM PDT 24
Finished Mar 12 01:07:26 PM PDT 24
Peak memory 204684 kb
Host smart-ac55fbf8-35c4-4936-a5b6-f0b43888ce75
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158400827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2158400827
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_slow_rsp.178653199
Short name T102
Test name
Test status
Simulation time 24974647167 ps
CPU time 203.42 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:06:59 PM PDT 24
Peak memory 211136 kb
Host smart-8ba6fe80-05db-4abd-9989-994ac50de1d5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=178653199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.178653199
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_random_zero_delays.3404091746
Short name T588
Test name
Test status
Simulation time 166019963 ps
CPU time 5.76 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:03:36 PM PDT 24
Peak memory 203960 kb
Host smart-4b049df7-33ac-4be4-8431-8176d911d44e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404091746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.3404091746
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_same_source.3461600933
Short name T891
Test name
Test status
Simulation time 2950103622 ps
CPU time 13.21 seconds
Started Mar 12 01:03:26 PM PDT 24
Finished Mar 12 01:03:40 PM PDT 24
Peak memory 202972 kb
Host smart-0da4ca7b-9d59-4675-b015-5bc0f9d5f5e2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3461600933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3461600933
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke.2579976818
Short name T305
Test name
Test status
Simulation time 225348823 ps
CPU time 2.95 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:03:31 PM PDT 24
Peak memory 202792 kb
Host smart-0b08c0a8-71e2-4e30-909f-4e26a4589b29
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2579976818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2579976818
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_large_delays.571137821
Short name T166
Test name
Test status
Simulation time 9638056214 ps
CPU time 32.04 seconds
Started Mar 12 01:03:14 PM PDT 24
Finished Mar 12 01:03:47 PM PDT 24
Peak memory 202968 kb
Host smart-036e8bd8-5444-4b79-9c8d-0f1b819b51c6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=571137821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.571137821
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.257373181
Short name T148
Test name
Test status
Simulation time 11005449882 ps
CPU time 32.93 seconds
Started Mar 12 01:03:28 PM PDT 24
Finished Mar 12 01:04:02 PM PDT 24
Peak memory 203008 kb
Host smart-2b556cc5-49dd-4433-a848-3fb693b0f724
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=257373181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.257373181
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.2776995480
Short name T289
Test name
Test status
Simulation time 26291600 ps
CPU time 2.18 seconds
Started Mar 12 01:03:10 PM PDT 24
Finished Mar 12 01:03:13 PM PDT 24
Peak memory 202912 kb
Host smart-32c39ad8-a6d2-4e90-ac7a-9c3700ae790f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776995480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.2776995480
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all.1427935210
Short name T643
Test name
Test status
Simulation time 1588430777 ps
CPU time 45.44 seconds
Started Mar 12 01:03:26 PM PDT 24
Finished Mar 12 01:04:12 PM PDT 24
Peak memory 204316 kb
Host smart-dacf57a2-eae7-4d2f-be7b-a2988b74dd6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1427935210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1427935210
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2078623814
Short name T295
Test name
Test status
Simulation time 1682288725 ps
CPU time 131.37 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:05:40 PM PDT 24
Peak memory 207216 kb
Host smart-4ed10a83-6abe-49f3-b540-27a0a12cac78
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2078623814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2078623814
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.2945198896
Short name T852
Test name
Test status
Simulation time 107672451 ps
CPU time 55.26 seconds
Started Mar 12 01:03:25 PM PDT 24
Finished Mar 12 01:04:21 PM PDT 24
Peak memory 206516 kb
Host smart-c44c1f35-a14f-4b5b-af39-7a56a0e108e3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2945198896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_ran
d_reset.2945198896
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2212467682
Short name T587
Test name
Test status
Simulation time 686456720 ps
CPU time 195.01 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:06:47 PM PDT 24
Peak memory 211016 kb
Host smart-205b17a9-7acc-4e4d-993c-2795be1c9ca1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2212467682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_re
set_error.2212467682
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/23.xbar_unmapped_addr.507646736
Short name T723
Test name
Test status
Simulation time 415840783 ps
CPU time 13.01 seconds
Started Mar 12 01:03:11 PM PDT 24
Finished Mar 12 01:03:24 PM PDT 24
Peak memory 204308 kb
Host smart-9cc56305-1701-4204-99ff-8ccb0199514c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=507646736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.507646736
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device.2759003542
Short name T79
Test name
Test status
Simulation time 701380845 ps
CPU time 28.78 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:04:01 PM PDT 24
Peak memory 203748 kb
Host smart-69f85d28-b066-42d5-9d8d-3b20145718f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2759003542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2759003542
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.355008507
Short name T138
Test name
Test status
Simulation time 72322902989 ps
CPU time 297.86 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:08:28 PM PDT 24
Peak memory 211204 kb
Host smart-c1026f00-1503-48b8-b98e-7ede68921071
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=355008507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slo
w_rsp.355008507
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.2560727279
Short name T440
Test name
Test status
Simulation time 241500174 ps
CPU time 16.18 seconds
Started Mar 12 01:03:11 PM PDT 24
Finished Mar 12 01:03:28 PM PDT 24
Peak memory 202904 kb
Host smart-1b13d392-224b-4ae8-a19e-77cea073c6a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2560727279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2560727279
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_error_random.3192690786
Short name T165
Test name
Test status
Simulation time 401270817 ps
CPU time 13.49 seconds
Started Mar 12 01:03:28 PM PDT 24
Finished Mar 12 01:03:42 PM PDT 24
Peak memory 202912 kb
Host smart-65dbac49-852b-46cb-a531-5f2e1ff22e50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3192690786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3192690786
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random.2862953190
Short name T126
Test name
Test status
Simulation time 975133955 ps
CPU time 31.42 seconds
Started Mar 12 01:03:12 PM PDT 24
Finished Mar 12 01:03:44 PM PDT 24
Peak memory 204436 kb
Host smart-4996ed4a-47d2-434e-9885-6a3aa5e69785
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2862953190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2862953190
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_large_delays.2637988955
Short name T263
Test name
Test status
Simulation time 16841274315 ps
CPU time 37.39 seconds
Started Mar 12 01:03:12 PM PDT 24
Finished Mar 12 01:03:50 PM PDT 24
Peak memory 204072 kb
Host smart-27b9e694-243e-4c46-902e-2b0bf540f115
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637988955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2637988955
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_slow_rsp.4180578540
Short name T654
Test name
Test status
Simulation time 4356802618 ps
CPU time 16.66 seconds
Started Mar 12 01:03:09 PM PDT 24
Finished Mar 12 01:03:27 PM PDT 24
Peak memory 202324 kb
Host smart-52a3c258-839d-40ab-8bef-f37f2a0a546e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4180578540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.4180578540
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_random_zero_delays.3052054052
Short name T325
Test name
Test status
Simulation time 74048957 ps
CPU time 5.93 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:03:33 PM PDT 24
Peak memory 203524 kb
Host smart-a8f2dbe4-cd71-43c5-a431-297cabd0f387
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052054052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3052054052
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_same_source.3834342677
Short name T803
Test name
Test status
Simulation time 83562171 ps
CPU time 3.61 seconds
Started Mar 12 01:03:22 PM PDT 24
Finished Mar 12 01:03:28 PM PDT 24
Peak memory 203128 kb
Host smart-14b75aca-99fe-40d4-b00d-844c9070be15
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3834342677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3834342677
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke.2965766236
Short name T153
Test name
Test status
Simulation time 375273852 ps
CPU time 3.54 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:03:33 PM PDT 24
Peak memory 202744 kb
Host smart-7c87fbf6-6dad-43e4-81aa-682254329d1e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2965766236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2965766236
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_large_delays.1999216889
Short name T237
Test name
Test status
Simulation time 20051415680 ps
CPU time 42.44 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:04:13 PM PDT 24
Peak memory 202988 kb
Host smart-be1131f4-3abb-4ade-bfa6-8108fe917765
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999216889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1999216889
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1111333118
Short name T582
Test name
Test status
Simulation time 10258513054 ps
CPU time 25.43 seconds
Started Mar 12 01:03:17 PM PDT 24
Finished Mar 12 01:03:43 PM PDT 24
Peak memory 203024 kb
Host smart-a966794f-b972-4861-933f-da2e75369ec1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1111333118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1111333118
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2802975214
Short name T619
Test name
Test status
Simulation time 42270899 ps
CPU time 1.96 seconds
Started Mar 12 01:03:11 PM PDT 24
Finished Mar 12 01:03:14 PM PDT 24
Peak memory 202884 kb
Host smart-f35ce701-5471-4182-9dc1-aa94b29a80c4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802975214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2802975214
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all.1362121060
Short name T434
Test name
Test status
Simulation time 523960733 ps
CPU time 91.29 seconds
Started Mar 12 01:03:07 PM PDT 24
Finished Mar 12 01:04:39 PM PDT 24
Peak memory 204748 kb
Host smart-317fcb1d-8e13-406c-a763-9f6f3d810def
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1362121060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1362121060
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_error.3235900704
Short name T671
Test name
Test status
Simulation time 1225690086 ps
CPU time 71.94 seconds
Started Mar 12 01:03:22 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 211116 kb
Host smart-b7c44c4a-960a-4306-a31a-0ac64601d09e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3235900704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3235900704
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.637083110
Short name T499
Test name
Test status
Simulation time 5264656064 ps
CPU time 100.66 seconds
Started Mar 12 01:03:26 PM PDT 24
Finished Mar 12 01:05:07 PM PDT 24
Peak memory 206716 kb
Host smart-0e2fd05b-9090-462d-8d19-e367e73576bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=637083110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand
_reset.637083110
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.4059764303
Short name T311
Test name
Test status
Simulation time 292565229 ps
CPU time 93.07 seconds
Started Mar 12 01:03:24 PM PDT 24
Finished Mar 12 01:04:59 PM PDT 24
Peak memory 208072 kb
Host smart-1df9aca2-df86-4a81-9810-ab1eb001bbde
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4059764303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_re
set_error.4059764303
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/24.xbar_unmapped_addr.12943314
Short name T569
Test name
Test status
Simulation time 63581599 ps
CPU time 4.84 seconds
Started Mar 12 01:03:12 PM PDT 24
Finished Mar 12 01:03:18 PM PDT 24
Peak memory 204216 kb
Host smart-c6d85b12-cc6e-4f71-ad5a-affad95f96a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=12943314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.12943314
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device.3857193674
Short name T744
Test name
Test status
Simulation time 1558073629 ps
CPU time 27.25 seconds
Started Mar 12 01:03:13 PM PDT 24
Finished Mar 12 01:03:40 PM PDT 24
Peak memory 202952 kb
Host smart-ce9e86c4-2043-456c-be2a-a6f4d0757552
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3857193674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3857193674
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1970545438
Short name T646
Test name
Test status
Simulation time 69592148046 ps
CPU time 294.96 seconds
Started Mar 12 01:03:10 PM PDT 24
Finished Mar 12 01:08:05 PM PDT 24
Peak memory 205816 kb
Host smart-05947741-4350-47eb-8496-d3105191634d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1970545438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_sl
ow_rsp.1970545438
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3092541847
Short name T248
Test name
Test status
Simulation time 165146681 ps
CPU time 20.58 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:03:50 PM PDT 24
Peak memory 202960 kb
Host smart-abc4fa39-1365-4f6c-83a0-07c67a9cb96c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3092541847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3092541847
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_error_random.4069737288
Short name T285
Test name
Test status
Simulation time 371487625 ps
CPU time 10.24 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:03:40 PM PDT 24
Peak memory 202964 kb
Host smart-59af4002-0930-4560-bccd-96a6087fd9b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4069737288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.4069737288
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random.3823733048
Short name T143
Test name
Test status
Simulation time 993282335 ps
CPU time 31.86 seconds
Started Mar 12 01:03:24 PM PDT 24
Finished Mar 12 01:03:57 PM PDT 24
Peak memory 204544 kb
Host smart-60b62e49-40c0-40de-8bbd-5443b6cdb062
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3823733048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3823733048
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_large_delays.228465051
Short name T313
Test name
Test status
Simulation time 177888834664 ps
CPU time 263.96 seconds
Started Mar 12 01:03:24 PM PDT 24
Finished Mar 12 01:07:49 PM PDT 24
Peak memory 211216 kb
Host smart-15e3265c-61bb-42e6-8b36-d0f7950cd285
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=228465051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.228465051
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3926928708
Short name T624
Test name
Test status
Simulation time 7732725835 ps
CPU time 41.08 seconds
Started Mar 12 01:03:25 PM PDT 24
Finished Mar 12 01:04:07 PM PDT 24
Peak memory 211184 kb
Host smart-b24f7027-4a87-4850-bdc6-6afc78c8f875
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3926928708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3926928708
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_random_zero_delays.3031183559
Short name T625
Test name
Test status
Simulation time 233303294 ps
CPU time 13.69 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:03:44 PM PDT 24
Peak memory 204144 kb
Host smart-7ba50bbb-71ec-4175-af0c-335e7922b2e8
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031183559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.3031183559
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_same_source.223880059
Short name T336
Test name
Test status
Simulation time 60018046 ps
CPU time 4.54 seconds
Started Mar 12 01:03:20 PM PDT 24
Finished Mar 12 01:03:25 PM PDT 24
Peak memory 203264 kb
Host smart-23fc4443-1982-483b-abbf-bb600bb274c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=223880059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.223880059
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke.4102974534
Short name T549
Test name
Test status
Simulation time 105453658 ps
CPU time 3.05 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:03:39 PM PDT 24
Peak memory 202904 kb
Host smart-a7a8cbee-3ba2-4e09-aacc-876af1e058b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4102974534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4102974534
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_large_delays.4099618890
Short name T530
Test name
Test status
Simulation time 9971982600 ps
CPU time 38.98 seconds
Started Mar 12 01:03:26 PM PDT 24
Finished Mar 12 01:04:05 PM PDT 24
Peak memory 202944 kb
Host smart-0ae72699-1973-4961-857e-d50553b63ed9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099618890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.4099618890
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3137259383
Short name T871
Test name
Test status
Simulation time 19490729073 ps
CPU time 42.91 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:04:13 PM PDT 24
Peak memory 202928 kb
Host smart-b622f2fa-1f61-4f28-9006-e3e4600ff13c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3137259383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3137259383
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.3357313335
Short name T521
Test name
Test status
Simulation time 26872486 ps
CPU time 2.05 seconds
Started Mar 12 01:03:12 PM PDT 24
Finished Mar 12 01:03:14 PM PDT 24
Peak memory 202804 kb
Host smart-09c2617a-640e-4fc0-8da2-e0e974705dfd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357313335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.3357313335
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all.2866808590
Short name T495
Test name
Test status
Simulation time 195700242 ps
CPU time 18.77 seconds
Started Mar 12 01:03:28 PM PDT 24
Finished Mar 12 01:03:47 PM PDT 24
Peak memory 204476 kb
Host smart-d7880203-a651-441d-a478-fe6d24c18385
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2866808590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2866808590
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.322875825
Short name T34
Test name
Test status
Simulation time 2320374352 ps
CPU time 167.67 seconds
Started Mar 12 01:03:26 PM PDT 24
Finished Mar 12 01:06:15 PM PDT 24
Peak memory 206224 kb
Host smart-6e6a60ce-a546-4698-9ec5-46c7279ef010
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=322875825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand
_reset.322875825
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3527346800
Short name T629
Test name
Test status
Simulation time 243324453 ps
CPU time 65.75 seconds
Started Mar 12 01:03:15 PM PDT 24
Finished Mar 12 01:04:21 PM PDT 24
Peak memory 207624 kb
Host smart-a69cfabd-412a-4eb9-aa65-60ed08682988
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3527346800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_re
set_error.3527346800
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/25.xbar_unmapped_addr.993346705
Short name T252
Test name
Test status
Simulation time 349511700 ps
CPU time 12.97 seconds
Started Mar 12 01:03:13 PM PDT 24
Finished Mar 12 01:03:26 PM PDT 24
Peak memory 211136 kb
Host smart-7fab3184-aee7-406e-b576-e1fe15f0d03b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=993346705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.993346705
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device.2125281613
Short name T105
Test name
Test status
Simulation time 1715441821 ps
CPU time 50.27 seconds
Started Mar 12 01:03:24 PM PDT 24
Finished Mar 12 01:04:16 PM PDT 24
Peak memory 204868 kb
Host smart-c786e4a6-9201-456b-bb01-138bb3431a14
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2125281613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2125281613
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3332054170
Short name T759
Test name
Test status
Simulation time 563835051848 ps
CPU time 1201.2 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:23:34 PM PDT 24
Peak memory 211132 kb
Host smart-5cb88f47-aff7-4519-a254-e4a2710bb2ec
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3332054170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_sl
ow_rsp.3332054170
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1946367242
Short name T169
Test name
Test status
Simulation time 152247080 ps
CPU time 14.9 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:03:50 PM PDT 24
Peak memory 202928 kb
Host smart-0ca9c893-4d3c-43c2-95f1-2426c7d87451
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1946367242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1946367242
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_error_random.1403317577
Short name T633
Test name
Test status
Simulation time 314433351 ps
CPU time 20.65 seconds
Started Mar 12 01:03:26 PM PDT 24
Finished Mar 12 01:03:48 PM PDT 24
Peak memory 202988 kb
Host smart-c56b2088-a613-4073-9681-eae5526be262
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1403317577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1403317577
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random.3743853259
Short name T486
Test name
Test status
Simulation time 70483979 ps
CPU time 2.9 seconds
Started Mar 12 01:03:21 PM PDT 24
Finished Mar 12 01:03:24 PM PDT 24
Peak memory 202984 kb
Host smart-07feb9cf-7118-48c2-b7e4-1620fc106daf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3743853259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3743853259
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_large_delays.1796650002
Short name T205
Test name
Test status
Simulation time 25936819121 ps
CPU time 131.37 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:05:43 PM PDT 24
Peak memory 211204 kb
Host smart-cc739cfb-a046-42dd-a9db-e9bf1d018ded
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796650002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1796650002
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1844452769
Short name T222
Test name
Test status
Simulation time 42545063432 ps
CPU time 136.29 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:05:47 PM PDT 24
Peak memory 204296 kb
Host smart-71c8ce20-4ecf-48a9-8f20-b7a969aa641d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1844452769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1844452769
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_random_zero_delays.3122010397
Short name T170
Test name
Test status
Simulation time 289552127 ps
CPU time 16.99 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:03:50 PM PDT 24
Peak memory 204188 kb
Host smart-f8babe3c-58b4-4559-93c0-1f7def79a0b0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122010397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3122010397
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_same_source.3418302173
Short name T704
Test name
Test status
Simulation time 1650173450 ps
CPU time 8.31 seconds
Started Mar 12 01:03:23 PM PDT 24
Finished Mar 12 01:03:33 PM PDT 24
Peak memory 202980 kb
Host smart-f8ec739f-48be-4dec-a7a1-0d126b51821f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3418302173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3418302173
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke.1900064463
Short name T324
Test name
Test status
Simulation time 76543571 ps
CPU time 2.4 seconds
Started Mar 12 01:03:10 PM PDT 24
Finished Mar 12 01:03:12 PM PDT 24
Peak memory 202912 kb
Host smart-1ec93bc9-c2ef-432f-8cf6-3da16838fa51
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1900064463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1900064463
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3849107000
Short name T728
Test name
Test status
Simulation time 7090994176 ps
CPU time 39.31 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:04:10 PM PDT 24
Peak memory 202972 kb
Host smart-507942cf-6f91-4d45-81ca-3c32781664ba
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849107000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3849107000
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.344695808
Short name T586
Test name
Test status
Simulation time 6507184276 ps
CPU time 35.24 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:04:03 PM PDT 24
Peak memory 202948 kb
Host smart-9e6dfa82-1b8e-40b8-ba1e-d8e8b9ea3869
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=344695808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.344695808
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.2914630368
Short name T164
Test name
Test status
Simulation time 28732878 ps
CPU time 2.36 seconds
Started Mar 12 01:03:24 PM PDT 24
Finished Mar 12 01:03:28 PM PDT 24
Peak memory 202888 kb
Host smart-9f9657ef-9337-4fd2-9d15-bea0997cf8c4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914630368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2914630368
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_error.856874337
Short name T26
Test name
Test status
Simulation time 4771511859 ps
CPU time 107.92 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:05:23 PM PDT 24
Peak memory 205156 kb
Host smart-01b1c261-434b-43ab-9990-8dda5426a963
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=856874337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.856874337
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3434575943
Short name T29
Test name
Test status
Simulation time 2077908031 ps
CPU time 206.82 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:06:59 PM PDT 24
Peak memory 208496 kb
Host smart-7890ed40-620d-47ff-a6fe-99e8eb2f70f9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3434575943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_ran
d_reset.3434575943
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2221064815
Short name T887
Test name
Test status
Simulation time 1308218066 ps
CPU time 197.15 seconds
Started Mar 12 01:03:31 PM PDT 24
Finished Mar 12 01:06:49 PM PDT 24
Peak memory 210976 kb
Host smart-813983fb-7292-4e53-bb73-02076ee41d8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2221064815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_re
set_error.2221064815
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/26.xbar_unmapped_addr.1190266737
Short name T661
Test name
Test status
Simulation time 254251811 ps
CPU time 11.9 seconds
Started Mar 12 01:03:25 PM PDT 24
Finished Mar 12 01:03:38 PM PDT 24
Peak memory 211116 kb
Host smart-51bc52e7-d779-4c6b-8159-d0f41fa1bbe7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1190266737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1190266737
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device.4151252345
Short name T536
Test name
Test status
Simulation time 574969184 ps
CPU time 44.93 seconds
Started Mar 12 01:03:31 PM PDT 24
Finished Mar 12 01:04:17 PM PDT 24
Peak memory 206072 kb
Host smart-3d80acee-f952-4ed3-b35e-c0af1f9d2a41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4151252345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.4151252345
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2850533335
Short name T123
Test name
Test status
Simulation time 72522903610 ps
CPU time 607.12 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:13:43 PM PDT 24
Peak memory 211196 kb
Host smart-fa46ab66-0952-4325-a03f-f68791bc5516
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2850533335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_sl
ow_rsp.2850533335
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.2664211191
Short name T758
Test name
Test status
Simulation time 654560533 ps
CPU time 23.74 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:03:56 PM PDT 24
Peak memory 203544 kb
Host smart-66ef0595-05fa-4a32-9d15-e29270e83853
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2664211191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.2664211191
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_error_random.3185831567
Short name T774
Test name
Test status
Simulation time 787367708 ps
CPU time 25.47 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:03:58 PM PDT 24
Peak memory 202944 kb
Host smart-c785e424-7c28-4a53-9c66-aad6f92ac48f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3185831567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3185831567
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random.4011493851
Short name T82
Test name
Test status
Simulation time 1459930079 ps
CPU time 38.78 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:04:12 PM PDT 24
Peak memory 203876 kb
Host smart-83d58986-63c9-4ca2-beff-e8da5d1d076a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4011493851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.4011493851
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_large_delays.1487150787
Short name T51
Test name
Test status
Simulation time 34534444336 ps
CPU time 176.26 seconds
Started Mar 12 01:03:31 PM PDT 24
Finished Mar 12 01:06:28 PM PDT 24
Peak memory 204320 kb
Host smart-5bb27f8e-929f-4eb4-80ac-c4c387285f9c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487150787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1487150787
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3284502508
Short name T73
Test name
Test status
Simulation time 24730549818 ps
CPU time 200 seconds
Started Mar 12 01:03:36 PM PDT 24
Finished Mar 12 01:06:56 PM PDT 24
Peak memory 204356 kb
Host smart-0a2d9c71-090a-4bdf-bb06-6661baa155fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3284502508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3284502508
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_random_zero_delays.4186875862
Short name T332
Test name
Test status
Simulation time 142670645 ps
CPU time 21.66 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 211132 kb
Host smart-6fb46f96-af8d-4ef2-b710-6444c6a81cb0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186875862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.4186875862
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_same_source.1657841682
Short name T566
Test name
Test status
Simulation time 3110718975 ps
CPU time 32.16 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:04:04 PM PDT 24
Peak memory 202980 kb
Host smart-1b3674d4-c537-4f5d-9290-538be4d982f1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1657841682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1657841682
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke.5654399
Short name T327
Test name
Test status
Simulation time 112112252 ps
CPU time 3.39 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:03:39 PM PDT 24
Peak memory 202860 kb
Host smart-ab394e48-1a30-4c7f-a6a4-64c591b1f374
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=5654399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.5654399
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_large_delays.165354175
Short name T158
Test name
Test status
Simulation time 7653588431 ps
CPU time 31.25 seconds
Started Mar 12 01:03:31 PM PDT 24
Finished Mar 12 01:04:03 PM PDT 24
Peak memory 203004 kb
Host smart-223383bf-e173-4ec8-8a52-c02d8cf8e75f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=165354175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.165354175
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.619019312
Short name T698
Test name
Test status
Simulation time 3415277115 ps
CPU time 30.46 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:03:58 PM PDT 24
Peak memory 203004 kb
Host smart-54b8eccf-f8d8-4a40-94e4-a7e15bc1f873
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=619019312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.619019312
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3856929818
Short name T822
Test name
Test status
Simulation time 35845415 ps
CPU time 2.66 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:03:34 PM PDT 24
Peak memory 202892 kb
Host smart-4b7a5028-ecc3-449f-9841-097b41856414
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856929818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3856929818
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all.2340500614
Short name T425
Test name
Test status
Simulation time 6295677349 ps
CPU time 106.95 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:05:15 PM PDT 24
Peak memory 205448 kb
Host smart-9bf9dcb3-f012-4f6d-892f-ec2135cacffd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2340500614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2340500614
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_error.516727851
Short name T427
Test name
Test status
Simulation time 2185165749 ps
CPU time 131.61 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:05:47 PM PDT 24
Peak memory 208828 kb
Host smart-1ee5b5ed-47d4-46e3-bc16-fd0082d00982
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=516727851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.516727851
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.947242915
Short name T35
Test name
Test status
Simulation time 1116577754 ps
CPU time 204.95 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:07:05 PM PDT 24
Peak memory 209080 kb
Host smart-85179a58-4ed3-4dbd-98b3-de7b2bbbd085
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=947242915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand
_reset.947242915
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3435808270
Short name T189
Test name
Test status
Simulation time 111609735 ps
CPU time 60.47 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 206280 kb
Host smart-ca15a75c-2c51-4d4a-b395-15cbb3223fd8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3435808270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_re
set_error.3435808270
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/27.xbar_unmapped_addr.2407661130
Short name T755
Test name
Test status
Simulation time 138208780 ps
CPU time 14.01 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:03:47 PM PDT 24
Peak memory 204144 kb
Host smart-da521d94-7bfb-4ccf-962c-2715c807706b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2407661130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2407661130
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device.277917559
Short name T473
Test name
Test status
Simulation time 233928024 ps
CPU time 26.58 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:04:02 PM PDT 24
Peak memory 204804 kb
Host smart-2db89a18-0203-41ca-8f8a-041fa6319b89
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=277917559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.277917559
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4277716220
Short name T655
Test name
Test status
Simulation time 16384256697 ps
CPU time 130.45 seconds
Started Mar 12 01:03:31 PM PDT 24
Finished Mar 12 01:05:42 PM PDT 24
Peak memory 211160 kb
Host smart-e1b80363-0480-445f-aaa7-148ab05bc6a7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4277716220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_sl
ow_rsp.4277716220
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.166112124
Short name T503
Test name
Test status
Simulation time 1966817918 ps
CPU time 21.66 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 202948 kb
Host smart-5f27a1d5-8527-415c-b050-826a13c0a3c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=166112124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.166112124
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_error_random.307611470
Short name T487
Test name
Test status
Simulation time 326042431 ps
CPU time 6.91 seconds
Started Mar 12 01:03:36 PM PDT 24
Finished Mar 12 01:03:44 PM PDT 24
Peak memory 202912 kb
Host smart-3afdced1-bb2b-4c62-8004-4efb7c97d229
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=307611470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.307611470
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random.952143579
Short name T795
Test name
Test status
Simulation time 598597844 ps
CPU time 9.58 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:03:45 PM PDT 24
Peak memory 203932 kb
Host smart-d32b3cc7-e859-4252-bf3e-ade462129c8e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=952143579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.952143579
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_large_delays.3714140198
Short name T610
Test name
Test status
Simulation time 57952984959 ps
CPU time 197.44 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:06:53 PM PDT 24
Peak memory 204136 kb
Host smart-961671ee-ca96-4d96-b45d-121ab426ae7d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714140198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3714140198
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_slow_rsp.127441716
Short name T281
Test name
Test status
Simulation time 22318448575 ps
CPU time 67.6 seconds
Started Mar 12 01:03:37 PM PDT 24
Finished Mar 12 01:04:45 PM PDT 24
Peak memory 211120 kb
Host smart-3ddd555e-f96e-4742-a1e8-c0cbd0f75af0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=127441716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.127441716
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_random_zero_delays.341205972
Short name T678
Test name
Test status
Simulation time 106333118 ps
CPU time 12.93 seconds
Started Mar 12 01:03:31 PM PDT 24
Finished Mar 12 01:03:45 PM PDT 24
Peak memory 203960 kb
Host smart-e5ee2e6e-9b26-47a6-8e5a-5b84b22b3f0c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341205972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.341205972
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_same_source.4134529380
Short name T151
Test name
Test status
Simulation time 1546746144 ps
CPU time 11.82 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:03:52 PM PDT 24
Peak memory 202956 kb
Host smart-b8bd7c1a-7cb2-411c-99c3-ad5a3dc9d825
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4134529380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.4134529380
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke.4168005729
Short name T439
Test name
Test status
Simulation time 53895820 ps
CPU time 2.53 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:03:30 PM PDT 24
Peak memory 202892 kb
Host smart-548dc2f5-2e91-4b9b-b05f-91b83d2393fc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4168005729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.4168005729
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_large_delays.1609613789
Short name T343
Test name
Test status
Simulation time 5731276498 ps
CPU time 33.99 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:04:07 PM PDT 24
Peak memory 202908 kb
Host smart-8e1df754-14de-47f4-ac75-7141b8a9cc57
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609613789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1609613789
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.444634943
Short name T297
Test name
Test status
Simulation time 10510945242 ps
CPU time 37.51 seconds
Started Mar 12 01:03:31 PM PDT 24
Finished Mar 12 01:04:09 PM PDT 24
Peak memory 203004 kb
Host smart-9db0ad26-af37-457c-bc32-4d89cac3106f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=444634943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.444634943
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.4075437008
Short name T606
Test name
Test status
Simulation time 28615441 ps
CPU time 2.35 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:03:35 PM PDT 24
Peak memory 202936 kb
Host smart-eb8bae86-9b4f-497e-904a-8be0279291dc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075437008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.4075437008
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all.2966001332
Short name T445
Test name
Test status
Simulation time 11158717985 ps
CPU time 189.43 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:06:45 PM PDT 24
Peak memory 208520 kb
Host smart-638c708e-686a-4f42-b6cc-672ea2211edf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2966001332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2966001332
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.4228049795
Short name T460
Test name
Test status
Simulation time 15608508102 ps
CPU time 187.64 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:06:43 PM PDT 24
Peak memory 207852 kb
Host smart-9d4f15d1-1887-443e-8881-39a371fbbd0e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4228049795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_ran
d_reset.4228049795
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1045474207
Short name T713
Test name
Test status
Simulation time 315025409 ps
CPU time 60.98 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:04:31 PM PDT 24
Peak memory 207368 kb
Host smart-b54876f2-763f-44cb-8402-4af7235465f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1045474207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_re
set_error.1045474207
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/28.xbar_unmapped_addr.2293434520
Short name T703
Test name
Test status
Simulation time 226616882 ps
CPU time 12.34 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:03:48 PM PDT 24
Peak memory 204212 kb
Host smart-e4275514-d054-43b4-801a-a3c341408587
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2293434520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2293434520
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device.1160772661
Short name T196
Test name
Test status
Simulation time 410446119 ps
CPU time 44.31 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:04:20 PM PDT 24
Peak memory 204748 kb
Host smart-9b59c5b8-f9c7-4017-8f7f-0b63232d6ce3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1160772661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1160772661
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3704367344
Short name T687
Test name
Test status
Simulation time 35765489261 ps
CPU time 219.02 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:07:11 PM PDT 24
Peak memory 205676 kb
Host smart-01c82cc4-e465-47a6-93f5-e1db0cca3400
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3704367344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_sl
ow_rsp.3704367344
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1776421076
Short name T537
Test name
Test status
Simulation time 11446128 ps
CPU time 1.69 seconds
Started Mar 12 01:03:38 PM PDT 24
Finished Mar 12 01:03:40 PM PDT 24
Peak memory 202908 kb
Host smart-d0214256-85bb-4bf9-9b02-42946212cc38
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1776421076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1776421076
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_error_random.3575929357
Short name T415
Test name
Test status
Simulation time 552471802 ps
CPU time 8.22 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:03:44 PM PDT 24
Peak memory 202912 kb
Host smart-910331e2-e428-4b5f-8354-9748f20a768d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3575929357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3575929357
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random.221114808
Short name T15
Test name
Test status
Simulation time 744464325 ps
CPU time 25.88 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:04:01 PM PDT 24
Peak memory 203940 kb
Host smart-5b26e3a2-7b09-40d2-93c9-6fb2d68fcd81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=221114808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.221114808
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_large_delays.2161544746
Short name T788
Test name
Test status
Simulation time 41713870368 ps
CPU time 125.17 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 211196 kb
Host smart-41c3eb5d-6ba0-48a7-8f42-e52a285967f6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161544746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2161544746
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1056348870
Short name T860
Test name
Test status
Simulation time 17738515605 ps
CPU time 108.43 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:05:17 PM PDT 24
Peak memory 204212 kb
Host smart-e7cfb5e2-de8d-436b-a611-14cc389b4b2b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1056348870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1056348870
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_random_zero_delays.1171371168
Short name T92
Test name
Test status
Simulation time 134033039 ps
CPU time 16.62 seconds
Started Mar 12 01:03:28 PM PDT 24
Finished Mar 12 01:03:45 PM PDT 24
Peak memory 204032 kb
Host smart-737f3b69-5273-44a8-b698-e98c118c237b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171371168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1171371168
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_same_source.3296680892
Short name T760
Test name
Test status
Simulation time 99772705 ps
CPU time 9.84 seconds
Started Mar 12 01:03:36 PM PDT 24
Finished Mar 12 01:03:46 PM PDT 24
Peak memory 202952 kb
Host smart-90232d93-184f-45ef-a22e-ac4f2077f383
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3296680892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3296680892
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke.798379099
Short name T112
Test name
Test status
Simulation time 38695669 ps
CPU time 2.28 seconds
Started Mar 12 01:03:31 PM PDT 24
Finished Mar 12 01:03:34 PM PDT 24
Peak memory 202912 kb
Host smart-b46caaa1-b7b7-4d76-bc37-edac2fb0a0a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=798379099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.798379099
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3808371421
Short name T8
Test name
Test status
Simulation time 8095300228 ps
CPU time 31.32 seconds
Started Mar 12 01:03:30 PM PDT 24
Finished Mar 12 01:04:03 PM PDT 24
Peak memory 203020 kb
Host smart-fe44c7f2-265a-4d02-91e9-96ee9e6b50df
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808371421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3808371421
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.4253663838
Short name T430
Test name
Test status
Simulation time 5759278747 ps
CPU time 21.23 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 202908 kb
Host smart-4b1a55b6-6409-4613-b15f-e6ce05c7881b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4253663838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4253663838
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2234293141
Short name T342
Test name
Test status
Simulation time 30796254 ps
CPU time 2.55 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:03:49 PM PDT 24
Peak memory 202844 kb
Host smart-1c735faa-88e7-43b2-975d-ba77fad08093
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234293141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2234293141
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all.2871538793
Short name T422
Test name
Test status
Simulation time 1275558149 ps
CPU time 33.68 seconds
Started Mar 12 01:03:27 PM PDT 24
Finished Mar 12 01:04:02 PM PDT 24
Peak memory 205436 kb
Host smart-ef664533-211f-4cdb-adcc-e9be27f78208
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2871538793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2871538793
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_error.741370285
Short name T709
Test name
Test status
Simulation time 13874906484 ps
CPU time 234.48 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:07:30 PM PDT 24
Peak memory 210592 kb
Host smart-b387a502-5da8-45fd-ba7d-af82ac5f4d11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=741370285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.741370285
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.4208022209
Short name T665
Test name
Test status
Simulation time 233789849 ps
CPU time 88.8 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:04:59 PM PDT 24
Peak memory 207948 kb
Host smart-ae6849bb-e614-4654-9c54-dc89bbe2458a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4208022209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_ran
d_reset.4208022209
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3767417882
Short name T802
Test name
Test status
Simulation time 2278323332 ps
CPU time 287.24 seconds
Started Mar 12 01:03:37 PM PDT 24
Finished Mar 12 01:08:25 PM PDT 24
Peak memory 212504 kb
Host smart-423dc6f7-a1ca-4ce9-935e-ec79eb1ada23
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3767417882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_re
set_error.3767417882
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/29.xbar_unmapped_addr.138686422
Short name T463
Test name
Test status
Simulation time 76082745 ps
CPU time 10.89 seconds
Started Mar 12 01:03:45 PM PDT 24
Finished Mar 12 01:03:56 PM PDT 24
Peak memory 204356 kb
Host smart-2c9c7b8b-5a40-4551-8eb1-2ea6632c2ace
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=138686422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.138686422
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device.1003264128
Short name T798
Test name
Test status
Simulation time 492547585 ps
CPU time 43.71 seconds
Started Mar 12 01:02:14 PM PDT 24
Finished Mar 12 01:02:58 PM PDT 24
Peak memory 205216 kb
Host smart-72e0a5a5-c0d5-4df0-b5d2-32007f1f2d98
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1003264128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.1003264128
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.880260937
Short name T830
Test name
Test status
Simulation time 64443920950 ps
CPU time 530.09 seconds
Started Mar 12 01:02:27 PM PDT 24
Finished Mar 12 01:11:17 PM PDT 24
Peak memory 211180 kb
Host smart-c979618f-9dbc-48f0-a299-9dcc8eabb625
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=880260937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow
_rsp.880260937
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.59944292
Short name T679
Test name
Test status
Simulation time 120971036 ps
CPU time 14.96 seconds
Started Mar 12 01:02:21 PM PDT 24
Finished Mar 12 01:02:36 PM PDT 24
Peak memory 202812 kb
Host smart-3ae500e1-2d69-443b-ac18-7a59b3fcdfd1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59944292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.59944292
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_error_random.2087553551
Short name T18
Test name
Test status
Simulation time 796629000 ps
CPU time 21.88 seconds
Started Mar 12 01:02:34 PM PDT 24
Finished Mar 12 01:02:56 PM PDT 24
Peak memory 202928 kb
Host smart-4119b33b-ec48-4e1c-a91c-2a383dd5df69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2087553551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2087553551
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random.4128625492
Short name T435
Test name
Test status
Simulation time 1034309505 ps
CPU time 21.09 seconds
Started Mar 12 01:02:04 PM PDT 24
Finished Mar 12 01:02:26 PM PDT 24
Peak memory 211088 kb
Host smart-5abdb53b-08f3-45ac-afae-6b000f295cc7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4128625492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.4128625492
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_large_delays.3502648748
Short name T708
Test name
Test status
Simulation time 30445046583 ps
CPU time 129.07 seconds
Started Mar 12 01:02:16 PM PDT 24
Finished Mar 12 01:04:25 PM PDT 24
Peak memory 204516 kb
Host smart-16c0c3f0-9c98-40ae-9f71-792e47e89490
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502648748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3502648748
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_slow_rsp.575561182
Short name T83
Test name
Test status
Simulation time 8817267904 ps
CPU time 92.09 seconds
Started Mar 12 01:02:25 PM PDT 24
Finished Mar 12 01:03:57 PM PDT 24
Peak memory 204152 kb
Host smart-ef5c9b00-870a-4bd7-b141-ae4b67fa92e8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=575561182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.575561182
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_random_zero_delays.3109624727
Short name T666
Test name
Test status
Simulation time 58835139 ps
CPU time 5.13 seconds
Started Mar 12 01:02:15 PM PDT 24
Finished Mar 12 01:02:20 PM PDT 24
Peak memory 203600 kb
Host smart-ba6b36f1-5a14-4c72-b4ae-98069c521529
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109624727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3109624727
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_same_source.2817523782
Short name T775
Test name
Test status
Simulation time 1477025553 ps
CPU time 23.49 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:02:55 PM PDT 24
Peak memory 202908 kb
Host smart-3d7f27c4-3fee-48df-a570-e76c16e79627
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2817523782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2817523782
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke.2657353524
Short name T290
Test name
Test status
Simulation time 58028825 ps
CPU time 2.25 seconds
Started Mar 12 01:02:19 PM PDT 24
Finished Mar 12 01:02:21 PM PDT 24
Peak memory 202940 kb
Host smart-796a1210-304c-4081-bbff-598499936ddd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2657353524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2657353524
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2779135141
Short name T769
Test name
Test status
Simulation time 4970395468 ps
CPU time 25.53 seconds
Started Mar 12 01:02:23 PM PDT 24
Finished Mar 12 01:02:48 PM PDT 24
Peak memory 202968 kb
Host smart-fda3ec0e-962b-4c78-ae40-89dfa2f6ed64
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779135141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2779135141
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.3014316115
Short name T54
Test name
Test status
Simulation time 10688725495 ps
CPU time 27.85 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:50 PM PDT 24
Peak memory 202948 kb
Host smart-8f524c48-5df8-46e6-8785-c0fada830dad
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3014316115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3014316115
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.636706172
Short name T282
Test name
Test status
Simulation time 43144923 ps
CPU time 2.42 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:25 PM PDT 24
Peak memory 202940 kb
Host smart-3e6a8e39-599a-4db8-95a3-80c7f0ff66e7
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636706172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.636706172
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all.1804365954
Short name T589
Test name
Test status
Simulation time 10358553222 ps
CPU time 108.71 seconds
Started Mar 12 01:02:34 PM PDT 24
Finished Mar 12 01:04:23 PM PDT 24
Peak memory 211212 kb
Host smart-cf563b5c-3b99-4790-98c8-6fe363e24eee
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1804365954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1804365954
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_error.204085707
Short name T743
Test name
Test status
Simulation time 780826766 ps
CPU time 13.14 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:02:44 PM PDT 24
Peak memory 203000 kb
Host smart-16b6f227-ccbe-4813-8db9-a82f8f57883f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=204085707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.204085707
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.810315389
Short name T581
Test name
Test status
Simulation time 8311133525 ps
CPU time 254.39 seconds
Started Mar 12 01:02:27 PM PDT 24
Finished Mar 12 01:06:41 PM PDT 24
Peak memory 209988 kb
Host smart-10dca1e8-4afc-42db-b066-00f93eb49288
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=810315389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_
reset.810315389
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1464158048
Short name T94
Test name
Test status
Simulation time 2440231150 ps
CPU time 235.5 seconds
Started Mar 12 01:02:28 PM PDT 24
Finished Mar 12 01:06:24 PM PDT 24
Peak memory 207752 kb
Host smart-4558ebdb-8af9-4c68-9805-42f309254178
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1464158048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_res
et_error.1464158048
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/3.xbar_unmapped_addr.260279284
Short name T292
Test name
Test status
Simulation time 314282173 ps
CPU time 13.88 seconds
Started Mar 12 01:02:28 PM PDT 24
Finished Mar 12 01:02:42 PM PDT 24
Peak memory 211108 kb
Host smart-451ed21e-96a6-439b-8f52-63aefe2743b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=260279284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.260279284
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device.1846625408
Short name T607
Test name
Test status
Simulation time 416467634 ps
CPU time 34.3 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:04:04 PM PDT 24
Peak memory 205336 kb
Host smart-b38eb3b6-cb21-4e8c-82b4-f2500722643f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1846625408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1846625408
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.1288543316
Short name T116
Test name
Test status
Simulation time 56107041861 ps
CPU time 155.12 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:06:08 PM PDT 24
Peak memory 211180 kb
Host smart-eabf8f1d-0ea3-4b73-acdc-d0e2c4398b68
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1288543316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_sl
ow_rsp.1288543316
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.274115103
Short name T861
Test name
Test status
Simulation time 103395687 ps
CPU time 14.34 seconds
Started Mar 12 01:03:29 PM PDT 24
Finished Mar 12 01:03:45 PM PDT 24
Peak memory 202780 kb
Host smart-df059d9d-7b6f-44bd-bbfd-922b220cfd45
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=274115103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.274115103
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_error_random.25128946
Short name T827
Test name
Test status
Simulation time 447352810 ps
CPU time 11.84 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:03:47 PM PDT 24
Peak memory 202860 kb
Host smart-8119ebd6-7c88-4127-a9a1-b544287a48fd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=25128946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.25128946
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random.182081289
Short name T109
Test name
Test status
Simulation time 65681451 ps
CPU time 8.97 seconds
Started Mar 12 01:03:36 PM PDT 24
Finished Mar 12 01:03:45 PM PDT 24
Peak memory 211064 kb
Host smart-7b979921-7219-4124-acda-320541047e2b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=182081289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.182081289
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_large_delays.2822215341
Short name T388
Test name
Test status
Simulation time 2990507342 ps
CPU time 15.89 seconds
Started Mar 12 01:03:38 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 202992 kb
Host smart-7d478c20-f299-4908-98a3-ead451370cbc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822215341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2822215341
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1816005161
Short name T458
Test name
Test status
Simulation time 15231707852 ps
CPU time 100.29 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:05:16 PM PDT 24
Peak memory 211196 kb
Host smart-aeb5c84c-3ac6-4f3e-b032-38007a7b227c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1816005161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1816005161
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_random_zero_delays.3491384613
Short name T329
Test name
Test status
Simulation time 139675764 ps
CPU time 14.32 seconds
Started Mar 12 01:03:38 PM PDT 24
Finished Mar 12 01:03:52 PM PDT 24
Peak memory 204040 kb
Host smart-eddeccae-2209-449b-890e-4cb0de0e5ccf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491384613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.3491384613
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_same_source.3473518540
Short name T385
Test name
Test status
Simulation time 116936364 ps
CPU time 7.83 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:03:40 PM PDT 24
Peak memory 202924 kb
Host smart-ab9000db-5b9d-4d9b-a8c6-0fa7ba2e9656
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3473518540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3473518540
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke.829497149
Short name T847
Test name
Test status
Simulation time 243838358 ps
CPU time 3.6 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:03:36 PM PDT 24
Peak memory 202888 kb
Host smart-e0c6af81-2795-4a77-8e14-478da045f57b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=829497149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.829497149
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1717231411
Short name T320
Test name
Test status
Simulation time 11940555032 ps
CPU time 34.6 seconds
Started Mar 12 01:03:26 PM PDT 24
Finished Mar 12 01:04:02 PM PDT 24
Peak memory 202972 kb
Host smart-fc6e1f61-f81e-4b69-aa3d-7f9b2eb11439
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717231411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1717231411
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2001708079
Short name T43
Test name
Test status
Simulation time 2691859338 ps
CPU time 24.89 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:03:57 PM PDT 24
Peak memory 203004 kb
Host smart-767922c8-4195-419e-b78e-09c80a2647c2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2001708079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2001708079
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.944339920
Short name T446
Test name
Test status
Simulation time 22415043 ps
CPU time 2 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:03:38 PM PDT 24
Peak memory 202936 kb
Host smart-6ae83963-58d2-4d30-a193-3e3e5d093776
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944339920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.944339920
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all.3739282434
Short name T107
Test name
Test status
Simulation time 6208162992 ps
CPU time 155.7 seconds
Started Mar 12 01:03:31 PM PDT 24
Finished Mar 12 01:06:08 PM PDT 24
Peak memory 206780 kb
Host smart-8b4f7e1d-8b90-4906-bf10-eee0c3a55adc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3739282434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3739282434
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2847956902
Short name T689
Test name
Test status
Simulation time 8849029798 ps
CPU time 123.36 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:05:43 PM PDT 24
Peak memory 206044 kb
Host smart-76a8bfa4-c083-42cd-93c4-09db77af8263
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2847956902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2847956902
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.1928670539
Short name T441
Test name
Test status
Simulation time 144245754 ps
CPU time 56.43 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:04:32 PM PDT 24
Peak memory 205784 kb
Host smart-8e9bc19a-a0c3-4226-a7a9-371166f719ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1928670539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_ran
d_reset.1928670539
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2582984650
Short name T271
Test name
Test status
Simulation time 53794587 ps
CPU time 10.08 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:03:46 PM PDT 24
Peak memory 203604 kb
Host smart-ded99459-af28-4d4d-a737-a675c3f7151e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2582984650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_re
set_error.2582984650
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/30.xbar_unmapped_addr.4187597737
Short name T407
Test name
Test status
Simulation time 945547338 ps
CPU time 23.77 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:03:57 PM PDT 24
Peak memory 204300 kb
Host smart-cc0646b2-6cbb-47a0-91ef-a5898cbd4d20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4187597737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4187597737
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device.3224726229
Short name T182
Test name
Test status
Simulation time 175441445 ps
CPU time 5.04 seconds
Started Mar 12 01:03:32 PM PDT 24
Finished Mar 12 01:03:37 PM PDT 24
Peak memory 202952 kb
Host smart-ed31e224-044a-4746-ad65-3031cfd05dc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3224726229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3224726229
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1607717975
Short name T796
Test name
Test status
Simulation time 86913264534 ps
CPU time 385.27 seconds
Started Mar 12 01:03:36 PM PDT 24
Finished Mar 12 01:10:02 PM PDT 24
Peak memory 211184 kb
Host smart-aa59947a-a483-4972-8acc-de5f822f4f68
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1607717975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_sl
ow_rsp.1607717975
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1627014609
Short name T302
Test name
Test status
Simulation time 354460255 ps
CPU time 14.52 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:03:50 PM PDT 24
Peak memory 203060 kb
Host smart-e4a50403-3346-4253-86cc-74bbf57a75a6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1627014609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1627014609
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_error_random.426935236
Short name T14
Test name
Test status
Simulation time 3203343597 ps
CPU time 23.13 seconds
Started Mar 12 01:03:39 PM PDT 24
Finished Mar 12 01:04:03 PM PDT 24
Peak memory 202920 kb
Host smart-6de099f6-1c6d-4437-8c23-b33e877e4173
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=426935236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.426935236
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random.1040303596
Short name T680
Test name
Test status
Simulation time 140205761 ps
CPU time 22.05 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:04:02 PM PDT 24
Peak memory 203956 kb
Host smart-ac5f5c6e-eb78-4de9-bcbd-a062d16df891
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1040303596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1040303596
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_large_delays.3507635840
Short name T224
Test name
Test status
Simulation time 48607980423 ps
CPU time 232.15 seconds
Started Mar 12 01:03:47 PM PDT 24
Finished Mar 12 01:07:41 PM PDT 24
Peak memory 204484 kb
Host smart-6c9694c0-3d0e-44a2-b812-1c4c5af4f43a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507635840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3507635840
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1507002126
Short name T254
Test name
Test status
Simulation time 12755095347 ps
CPU time 104.57 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:05:20 PM PDT 24
Peak memory 204036 kb
Host smart-5149df15-4e29-44c1-a334-4d6b3802c94b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1507002126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1507002126
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_random_zero_delays.2321036754
Short name T480
Test name
Test status
Simulation time 533839345 ps
CPU time 18.63 seconds
Started Mar 12 01:03:38 PM PDT 24
Finished Mar 12 01:03:57 PM PDT 24
Peak memory 211064 kb
Host smart-21a00261-22bd-493a-9680-c1be69a0d2eb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321036754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2321036754
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_same_source.2801747740
Short name T318
Test name
Test status
Simulation time 129000157 ps
CPU time 5.89 seconds
Started Mar 12 01:03:38 PM PDT 24
Finished Mar 12 01:03:44 PM PDT 24
Peak memory 202940 kb
Host smart-89d3c263-069f-4070-acae-3b0efd083a7b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2801747740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2801747740
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke.119533563
Short name T223
Test name
Test status
Simulation time 147093138 ps
CPU time 3.6 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:03:39 PM PDT 24
Peak memory 202952 kb
Host smart-9be32c7d-840e-4643-81aa-1c619f67d833
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=119533563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.119533563
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_large_delays.3218322659
Short name T450
Test name
Test status
Simulation time 11044379291 ps
CPU time 30.81 seconds
Started Mar 12 01:03:43 PM PDT 24
Finished Mar 12 01:04:14 PM PDT 24
Peak memory 202988 kb
Host smart-f92579c4-f75f-4786-8ec7-12aa8524d2c9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218322659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3218322659
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.979269945
Short name T394
Test name
Test status
Simulation time 4005928738 ps
CPU time 27.6 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:04:01 PM PDT 24
Peak memory 203000 kb
Host smart-a80116c0-b254-4cca-b520-60bd274b8872
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=979269945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.979269945
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.2579233407
Short name T548
Test name
Test status
Simulation time 39036593 ps
CPU time 2.63 seconds
Started Mar 12 01:03:38 PM PDT 24
Finished Mar 12 01:03:40 PM PDT 24
Peak memory 202884 kb
Host smart-66fdf5d5-11a7-4766-8a0d-5488b733db80
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579233407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.2579233407
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all.1521888974
Short name T178
Test name
Test status
Simulation time 3595503119 ps
CPU time 123.47 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:05:39 PM PDT 24
Peak memory 206356 kb
Host smart-38521f78-c5fc-4e3e-9f04-1991772ef618
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1521888974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1521888974
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_error.635049786
Short name T808
Test name
Test status
Simulation time 7549201953 ps
CPU time 79.02 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:04:54 PM PDT 24
Peak memory 211152 kb
Host smart-21363db2-fb22-4ceb-a743-d74add2c67d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=635049786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.635049786
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.3709611926
Short name T67
Test name
Test status
Simulation time 5975723176 ps
CPU time 178.65 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:06:34 PM PDT 24
Peak memory 209492 kb
Host smart-ab867743-670e-4b64-8598-f5ccbb0acfda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3709611926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_ran
d_reset.3709611926
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.1139915917
Short name T534
Test name
Test status
Simulation time 1391727685 ps
CPU time 97.32 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:05:13 PM PDT 24
Peak memory 208284 kb
Host smart-1b758a61-8e01-46f7-8b45-cf8a043372fb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1139915917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_re
set_error.1139915917
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/31.xbar_unmapped_addr.4116166005
Short name T532
Test name
Test status
Simulation time 67153379 ps
CPU time 2.15 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:03:42 PM PDT 24
Peak memory 203220 kb
Host smart-b6591978-fc2b-4fbe-9b64-9f70135f1bf5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4116166005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4116166005
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device.1306271675
Short name T209
Test name
Test status
Simulation time 559187263 ps
CPU time 43.09 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:04:19 PM PDT 24
Peak memory 205340 kb
Host smart-b72f6b45-1425-4d1e-a78f-2e0e944a0a57
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1306271675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.1306271675
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1599851151
Short name T125
Test name
Test status
Simulation time 106318436826 ps
CPU time 516.07 seconds
Started Mar 12 01:03:36 PM PDT 24
Finished Mar 12 01:12:12 PM PDT 24
Peak memory 211132 kb
Host smart-e1ecde52-dfec-417f-8e94-e9c86a63f0e0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1599851151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_sl
ow_rsp.1599851151
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3998866856
Short name T792
Test name
Test status
Simulation time 601846567 ps
CPU time 12.32 seconds
Started Mar 12 01:03:42 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 203384 kb
Host smart-695b3bf0-e3f1-4e73-8c66-7fdce25f2417
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3998866856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3998866856
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_error_random.4029718389
Short name T737
Test name
Test status
Simulation time 1292672779 ps
CPU time 32.51 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:04:13 PM PDT 24
Peak memory 202932 kb
Host smart-0af5820d-4ada-4d81-bab6-89870646c372
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4029718389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.4029718389
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random.3071988779
Short name T498
Test name
Test status
Simulation time 528811838 ps
CPU time 22.38 seconds
Started Mar 12 01:04:23 PM PDT 24
Finished Mar 12 01:04:45 PM PDT 24
Peak memory 204120 kb
Host smart-588bc7b3-b63f-455d-ab24-fa40d8bdf180
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3071988779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3071988779
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_large_delays.1159927135
Short name T659
Test name
Test status
Simulation time 55133375858 ps
CPU time 96.57 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:05:12 PM PDT 24
Peak memory 204204 kb
Host smart-24d9c15d-7347-4834-993d-c27a97943e30
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159927135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1159927135
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_slow_rsp.4086647377
Short name T387
Test name
Test status
Simulation time 34563376147 ps
CPU time 213.24 seconds
Started Mar 12 01:04:01 PM PDT 24
Finished Mar 12 01:07:35 PM PDT 24
Peak memory 204252 kb
Host smart-2788dd87-1e3c-43eb-bb15-8d4aafd6c2e6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4086647377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.4086647377
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_random_zero_delays.3857561923
Short name T114
Test name
Test status
Simulation time 717069167 ps
CPU time 15.71 seconds
Started Mar 12 01:03:39 PM PDT 24
Finished Mar 12 01:03:55 PM PDT 24
Peak memory 204028 kb
Host smart-6eed336b-f23c-42e6-8c3e-d4a6ffaa1197
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857561923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3857561923
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_same_source.3386240809
Short name T725
Test name
Test status
Simulation time 1490842136 ps
CPU time 19.52 seconds
Started Mar 12 01:03:42 PM PDT 24
Finished Mar 12 01:04:02 PM PDT 24
Peak memory 202956 kb
Host smart-d14ea63d-7ea3-4eb3-b711-f4f5d2712e13
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3386240809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3386240809
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke.530545460
Short name T451
Test name
Test status
Simulation time 43974462 ps
CPU time 2.38 seconds
Started Mar 12 01:03:37 PM PDT 24
Finished Mar 12 01:03:40 PM PDT 24
Peak memory 202912 kb
Host smart-4dbb314a-1c1d-4b3c-9730-5f605a185db9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=530545460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.530545460
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_large_delays.4087274396
Short name T405
Test name
Test status
Simulation time 5895061111 ps
CPU time 27.74 seconds
Started Mar 12 01:03:37 PM PDT 24
Finished Mar 12 01:04:04 PM PDT 24
Peak memory 202972 kb
Host smart-46b3e231-98f2-4098-8467-001e13fcfbd5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087274396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4087274396
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.373783595
Short name T245
Test name
Test status
Simulation time 6100306808 ps
CPU time 32.38 seconds
Started Mar 12 01:03:38 PM PDT 24
Finished Mar 12 01:04:10 PM PDT 24
Peak memory 202980 kb
Host smart-d87092de-5a27-4190-b0ee-ee1cbf4fba23
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=373783595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.373783595
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.4108459749
Short name T844
Test name
Test status
Simulation time 48366764 ps
CPU time 2.27 seconds
Started Mar 12 01:03:39 PM PDT 24
Finished Mar 12 01:03:41 PM PDT 24
Peak memory 202936 kb
Host smart-16694e94-4a67-4ccd-8e94-67814b8f7d56
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108459749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.4108459749
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all.4293629835
Short name T214
Test name
Test status
Simulation time 809414699 ps
CPU time 103.28 seconds
Started Mar 12 01:03:41 PM PDT 24
Finished Mar 12 01:05:24 PM PDT 24
Peak memory 205196 kb
Host smart-93806a4a-cc5b-4ddb-98fa-a42f63c73ce6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4293629835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.4293629835
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3089829828
Short name T362
Test name
Test status
Simulation time 178685986 ps
CPU time 13.04 seconds
Started Mar 12 01:03:41 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 203544 kb
Host smart-f62ce7ca-ddf3-4053-8f7e-f43c10c990f0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3089829828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3089829828
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.190320536
Short name T32
Test name
Test status
Simulation time 12185441281 ps
CPU time 317.22 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:08:57 PM PDT 24
Peak memory 209076 kb
Host smart-45a6dc59-f12a-45fd-9740-a4de7db5a0ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=190320536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand
_reset.190320536
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.951805645
Short name T571
Test name
Test status
Simulation time 479088881 ps
CPU time 103.57 seconds
Started Mar 12 01:03:45 PM PDT 24
Finished Mar 12 01:05:29 PM PDT 24
Peak memory 208160 kb
Host smart-8c5e3261-8bba-4976-a15d-17611960f490
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=951805645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_res
et_error.951805645
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/32.xbar_unmapped_addr.2061510783
Short name T331
Test name
Test status
Simulation time 298023220 ps
CPU time 10.3 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:03:45 PM PDT 24
Peak memory 204268 kb
Host smart-00c2c4de-d379-40f4-8a36-5a5e6fd9db04
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2061510783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2061510783
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device.1554281069
Short name T522
Test name
Test status
Simulation time 1915942753 ps
CPU time 53.36 seconds
Started Mar 12 01:03:41 PM PDT 24
Finished Mar 12 01:04:34 PM PDT 24
Peak memory 205684 kb
Host smart-b703cc92-7012-472a-a708-43f02f87a221
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1554281069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1554281069
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.2727505435
Short name T657
Test name
Test status
Simulation time 45522950237 ps
CPU time 332.25 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:09:08 PM PDT 24
Peak memory 211152 kb
Host smart-628d5b63-a6dc-42b0-8699-919d41f36a9c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2727505435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_sl
ow_rsp.2727505435
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3181825795
Short name T701
Test name
Test status
Simulation time 1274159338 ps
CPU time 25.18 seconds
Started Mar 12 01:03:34 PM PDT 24
Finished Mar 12 01:04:01 PM PDT 24
Peak memory 202996 kb
Host smart-2c4ce4e5-47f7-42c2-9d7d-ac85a4fc9433
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3181825795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3181825795
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_error_random.4185009039
Short name T380
Test name
Test status
Simulation time 1577662668 ps
CPU time 26.28 seconds
Started Mar 12 01:03:41 PM PDT 24
Finished Mar 12 01:04:07 PM PDT 24
Peak memory 202548 kb
Host smart-c876d9c8-999c-4134-8de6-0508d56a8738
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4185009039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.4185009039
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random.3299588358
Short name T734
Test name
Test status
Simulation time 866826925 ps
CPU time 24.79 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:04:04 PM PDT 24
Peak memory 204036 kb
Host smart-647c0c20-9d00-4cd2-9bd0-654880a5ddf7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3299588358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3299588358
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_large_delays.328174979
Short name T103
Test name
Test status
Simulation time 34265905156 ps
CPU time 191.35 seconds
Started Mar 12 01:03:37 PM PDT 24
Finished Mar 12 01:06:48 PM PDT 24
Peak memory 211176 kb
Host smart-d336b448-48d1-41e5-be1f-8a979dc76f90
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=328174979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.328174979
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3469151761
Short name T649
Test name
Test status
Simulation time 122312432726 ps
CPU time 278.24 seconds
Started Mar 12 01:03:37 PM PDT 24
Finished Mar 12 01:08:16 PM PDT 24
Peak memory 204480 kb
Host smart-998623f6-2e81-487c-8a44-bc849293412c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3469151761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3469151761
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_random_zero_delays.885417844
Short name T868
Test name
Test status
Simulation time 143896705 ps
CPU time 16.26 seconds
Started Mar 12 01:03:38 PM PDT 24
Finished Mar 12 01:03:55 PM PDT 24
Peak memory 203976 kb
Host smart-c418b852-ba1c-49b8-b834-32504e676966
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885417844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.885417844
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_same_source.3876645329
Short name T188
Test name
Test status
Simulation time 1149745901 ps
CPU time 16.89 seconds
Started Mar 12 01:03:41 PM PDT 24
Finished Mar 12 01:03:58 PM PDT 24
Peak memory 202564 kb
Host smart-c734af12-ba06-45a1-b698-8672d308f1cb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3876645329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3876645329
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke.2128033651
Short name T818
Test name
Test status
Simulation time 28685085 ps
CPU time 2.15 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:03:49 PM PDT 24
Peak memory 202912 kb
Host smart-082e0f20-d9ad-47f1-9b53-13f70f5ccfd7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2128033651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2128033651
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_large_delays.2962051601
Short name T781
Test name
Test status
Simulation time 6396994362 ps
CPU time 25.42 seconds
Started Mar 12 01:03:33 PM PDT 24
Finished Mar 12 01:03:58 PM PDT 24
Peak memory 202984 kb
Host smart-f3cfa44a-8ce1-4dd3-98ef-bb12422057f0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962051601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2962051601
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.378814120
Short name T529
Test name
Test status
Simulation time 7698334386 ps
CPU time 31.49 seconds
Started Mar 12 01:03:36 PM PDT 24
Finished Mar 12 01:04:07 PM PDT 24
Peak memory 202912 kb
Host smart-46aa2626-2412-47b9-a15c-cd6fda267aa9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=378814120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.378814120
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.603522382
Short name T583
Test name
Test status
Simulation time 34016877 ps
CPU time 2.52 seconds
Started Mar 12 01:03:37 PM PDT 24
Finished Mar 12 01:03:40 PM PDT 24
Peak memory 202936 kb
Host smart-c23a52fb-bbfe-41aa-a400-d8850a92f7df
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603522382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.603522382
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all.62392993
Short name T176
Test name
Test status
Simulation time 1820293991 ps
CPU time 42.13 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:04:22 PM PDT 24
Peak memory 205556 kb
Host smart-e9404936-d96d-4940-b72e-79998d7a53d0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=62392993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.62392993
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1458744151
Short name T349
Test name
Test status
Simulation time 1761672817 ps
CPU time 32 seconds
Started Mar 12 01:03:35 PM PDT 24
Finished Mar 12 01:04:08 PM PDT 24
Peak memory 202832 kb
Host smart-172c2f8c-2801-4b8f-9c6c-dd0b600ae1e9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1458744151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1458744151
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1755535040
Short name T6
Test name
Test status
Simulation time 369175303 ps
CPU time 124.51 seconds
Started Mar 12 01:03:40 PM PDT 24
Finished Mar 12 01:05:45 PM PDT 24
Peak memory 207136 kb
Host smart-9ac89774-0f63-4ceb-b3db-c5e7fcaf14ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1755535040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_ran
d_reset.1755535040
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2511466501
Short name T236
Test name
Test status
Simulation time 593811860 ps
CPU time 120.04 seconds
Started Mar 12 01:03:41 PM PDT 24
Finished Mar 12 01:05:41 PM PDT 24
Peak memory 208764 kb
Host smart-0e54a904-62fe-4995-82fc-1d33f95d1676
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2511466501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_re
set_error.2511466501
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/33.xbar_unmapped_addr.602274642
Short name T890
Test name
Test status
Simulation time 2474180246 ps
CPU time 30.26 seconds
Started Mar 12 01:03:37 PM PDT 24
Finished Mar 12 01:04:07 PM PDT 24
Peak memory 211164 kb
Host smart-a9566487-72ee-45a6-8018-6b65c928d0c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=602274642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.602274642
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device.4294092376
Short name T485
Test name
Test status
Simulation time 136347776 ps
CPU time 13.03 seconds
Started Mar 12 01:03:53 PM PDT 24
Finished Mar 12 01:04:07 PM PDT 24
Peak memory 203568 kb
Host smart-1f63f020-d244-41d7-8259-4c1756175c5f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4294092376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.4294092376
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2559186510
Short name T496
Test name
Test status
Simulation time 112141857568 ps
CPU time 717.62 seconds
Started Mar 12 01:03:48 PM PDT 24
Finished Mar 12 01:15:47 PM PDT 24
Peak memory 206988 kb
Host smart-d50a560c-fd3f-4fe5-871c-5a0b8642d354
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2559186510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_sl
ow_rsp.2559186510
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2104465967
Short name T855
Test name
Test status
Simulation time 547402680 ps
CPU time 16.95 seconds
Started Mar 12 01:03:45 PM PDT 24
Finished Mar 12 01:04:02 PM PDT 24
Peak memory 202996 kb
Host smart-4e3e6d86-c781-483a-87d0-6e414bba48b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2104465967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2104465967
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_error_random.3567296219
Short name T84
Test name
Test status
Simulation time 1997294257 ps
CPU time 24.67 seconds
Started Mar 12 01:03:45 PM PDT 24
Finished Mar 12 01:04:10 PM PDT 24
Peak memory 202888 kb
Host smart-8d0b756b-4504-4e20-8037-63290a53a2d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3567296219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3567296219
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random.3093322937
Short name T45
Test name
Test status
Simulation time 419353161 ps
CPU time 15.98 seconds
Started Mar 12 01:03:56 PM PDT 24
Finished Mar 12 01:04:12 PM PDT 24
Peak memory 203944 kb
Host smart-01d3e562-23f9-4471-91d5-b2b2717c6fbc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3093322937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3093322937
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_large_delays.1113455042
Short name T346
Test name
Test status
Simulation time 27277383289 ps
CPU time 173.69 seconds
Started Mar 12 01:03:47 PM PDT 24
Finished Mar 12 01:06:42 PM PDT 24
Peak memory 204192 kb
Host smart-b44aa790-a96b-4578-a615-67353e7424ff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113455042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1113455042
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_slow_rsp.255484660
Short name T409
Test name
Test status
Simulation time 23614623109 ps
CPU time 181.13 seconds
Started Mar 12 01:03:43 PM PDT 24
Finished Mar 12 01:06:44 PM PDT 24
Peak memory 204096 kb
Host smart-b18323e3-2991-4647-a19c-a3fe67a5fac9
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=255484660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.255484660
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_random_zero_delays.3554051338
Short name T740
Test name
Test status
Simulation time 16287123 ps
CPU time 2.26 seconds
Started Mar 12 01:03:57 PM PDT 24
Finished Mar 12 01:03:59 PM PDT 24
Peak memory 202900 kb
Host smart-8d950bbd-8461-4535-83e4-8a359c54d7da
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554051338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3554051338
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_same_source.1310075580
Short name T605
Test name
Test status
Simulation time 2091229257 ps
CPU time 27.82 seconds
Started Mar 12 01:03:44 PM PDT 24
Finished Mar 12 01:04:12 PM PDT 24
Peak memory 202896 kb
Host smart-7f1c6134-b594-49be-9e8a-65180f1cd370
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1310075580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1310075580
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke.1046814337
Short name T279
Test name
Test status
Simulation time 83309671 ps
CPU time 2.29 seconds
Started Mar 12 01:04:02 PM PDT 24
Finished Mar 12 01:04:04 PM PDT 24
Peak memory 202940 kb
Host smart-1b3355eb-b2ea-476e-915c-6c7d63218cec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1046814337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1046814337
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_large_delays.472938653
Short name T786
Test name
Test status
Simulation time 7136151721 ps
CPU time 35.22 seconds
Started Mar 12 01:03:42 PM PDT 24
Finished Mar 12 01:04:17 PM PDT 24
Peak memory 202980 kb
Host smart-7c5b3529-3ffb-4f9d-aed9-6dd458d59735
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=472938653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.472938653
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1767640660
Short name T56
Test name
Test status
Simulation time 7352038479 ps
CPU time 31.2 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:04:17 PM PDT 24
Peak memory 202896 kb
Host smart-3e7a67b8-c1df-4a50-a427-acb7c991820c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1767640660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1767640660
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1669208212
Short name T543
Test name
Test status
Simulation time 25648316 ps
CPU time 1.98 seconds
Started Mar 12 01:03:37 PM PDT 24
Finished Mar 12 01:03:39 PM PDT 24
Peak memory 202864 kb
Host smart-208e71ce-454d-41d1-8523-868006a69ccf
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669208212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1669208212
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all.1906750184
Short name T562
Test name
Test status
Simulation time 6987194882 ps
CPU time 81.14 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:05:08 PM PDT 24
Peak memory 211164 kb
Host smart-7e432757-4d80-41e3-a620-be5fd5f55c05
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1906750184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1906750184
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2266543008
Short name T867
Test name
Test status
Simulation time 2864975653 ps
CPU time 184.64 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:06:55 PM PDT 24
Peak memory 207860 kb
Host smart-eed3433d-c75b-4e1e-a182-572b41284198
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2266543008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2266543008
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.4129261024
Short name T22
Test name
Test status
Simulation time 2876078157 ps
CPU time 101.53 seconds
Started Mar 12 01:03:48 PM PDT 24
Finished Mar 12 01:05:31 PM PDT 24
Peak memory 207228 kb
Host smart-2abd6856-67f7-4a82-b384-b72c048c386e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4129261024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_ran
d_reset.4129261024
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3496901303
Short name T506
Test name
Test status
Simulation time 8938656214 ps
CPU time 324.22 seconds
Started Mar 12 01:03:47 PM PDT 24
Finished Mar 12 01:09:12 PM PDT 24
Peak memory 219500 kb
Host smart-7f09cd01-6226-4c22-897e-f4c1f88959b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3496901303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_re
set_error.3496901303
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/34.xbar_unmapped_addr.3457398458
Short name T616
Test name
Test status
Simulation time 447345381 ps
CPU time 13.25 seconds
Started Mar 12 01:03:48 PM PDT 24
Finished Mar 12 01:04:03 PM PDT 24
Peak memory 211096 kb
Host smart-1a3a9240-c7ff-4708-8c1c-b51b3b950363
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3457398458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3457398458
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device.2484068007
Short name T115
Test name
Test status
Simulation time 1256016405 ps
CPU time 13.2 seconds
Started Mar 12 01:03:45 PM PDT 24
Finished Mar 12 01:03:59 PM PDT 24
Peak memory 203432 kb
Host smart-a6aab06b-f9e0-45db-b31e-03d7ef81dda0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2484068007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2484068007
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1708746247
Short name T234
Test name
Test status
Simulation time 54999761421 ps
CPU time 347.67 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:09:38 PM PDT 24
Peak memory 205256 kb
Host smart-2cd6d131-073d-4e3f-8390-4358a054f2b8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1708746247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_sl
ow_rsp.1708746247
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.3949854146
Short name T602
Test name
Test status
Simulation time 397005249 ps
CPU time 10.47 seconds
Started Mar 12 01:03:47 PM PDT 24
Finished Mar 12 01:03:59 PM PDT 24
Peak memory 203152 kb
Host smart-a2237488-5326-4445-aef3-da2bc4d54bc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3949854146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3949854146
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_error_random.3921969242
Short name T315
Test name
Test status
Simulation time 1061279790 ps
CPU time 25.15 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:04:16 PM PDT 24
Peak memory 202860 kb
Host smart-45718898-c68c-48b7-9c57-7bd463ee3fc1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3921969242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3921969242
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random.3301316113
Short name T59
Test name
Test status
Simulation time 509076287 ps
CPU time 20.74 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:04:07 PM PDT 24
Peak memory 204032 kb
Host smart-b524cfb9-432b-4b85-b100-5dd7a0722575
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3301316113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.3301316113
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_large_delays.2424027654
Short name T814
Test name
Test status
Simulation time 149657931731 ps
CPU time 248.28 seconds
Started Mar 12 01:03:45 PM PDT 24
Finished Mar 12 01:07:53 PM PDT 24
Peak memory 204324 kb
Host smart-9b246eef-2a59-4f26-9fa1-dd12e6c7835c
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424027654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2424027654
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2314952499
Short name T60
Test name
Test status
Simulation time 79522989635 ps
CPU time 290 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:08:36 PM PDT 24
Peak memory 204108 kb
Host smart-4e39fca4-493a-4644-ac83-f502f3a446ca
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2314952499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2314952499
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_random_zero_delays.917758939
Short name T741
Test name
Test status
Simulation time 40596910 ps
CPU time 3.21 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 203308 kb
Host smart-19fccf6f-d002-41eb-96ae-3b161a83362d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917758939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.917758939
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_same_source.1872091891
Short name T541
Test name
Test status
Simulation time 519114751 ps
CPU time 9.5 seconds
Started Mar 12 01:03:45 PM PDT 24
Finished Mar 12 01:03:55 PM PDT 24
Peak memory 202980 kb
Host smart-a89b9ebb-a722-45cb-b2ae-f9105834a7d5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1872091891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1872091891
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke.78511037
Short name T673
Test name
Test status
Simulation time 113414593 ps
CPU time 3.37 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 202912 kb
Host smart-24207899-3ae7-4507-a15e-3add5a94d412
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=78511037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.78511037
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1233598316
Short name T899
Test name
Test status
Simulation time 5326084501 ps
CPU time 29.99 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:04:17 PM PDT 24
Peak memory 202980 kb
Host smart-dbba9d1e-4ef0-4f0a-948f-237415f22c29
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233598316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1233598316
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2023383995
Short name T317
Test name
Test status
Simulation time 3861580442 ps
CPU time 31.1 seconds
Started Mar 12 01:03:47 PM PDT 24
Finished Mar 12 01:04:19 PM PDT 24
Peak memory 202996 kb
Host smart-48d88999-a574-46ea-a3fb-1b9d8fa6181d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2023383995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2023383995
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.4225385815
Short name T739
Test name
Test status
Simulation time 43573561 ps
CPU time 2.53 seconds
Started Mar 12 01:03:53 PM PDT 24
Finished Mar 12 01:03:56 PM PDT 24
Peak memory 202884 kb
Host smart-d41fe53e-340b-4038-8536-8d8d0eead2d0
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225385815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.4225385815
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all.1864713474
Short name T880
Test name
Test status
Simulation time 1995970957 ps
CPU time 179.01 seconds
Started Mar 12 01:03:48 PM PDT 24
Finished Mar 12 01:06:48 PM PDT 24
Peak memory 211072 kb
Host smart-03288cf5-f305-4cb0-80df-ae8918847063
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1864713474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1864713474
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_error.2230660881
Short name T344
Test name
Test status
Simulation time 4956164278 ps
CPU time 157.59 seconds
Started Mar 12 01:03:43 PM PDT 24
Finished Mar 12 01:06:20 PM PDT 24
Peak memory 211200 kb
Host smart-f0e8b44d-d9a9-4abe-a048-a750244ab7b9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2230660881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2230660881
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1053613629
Short name T21
Test name
Test status
Simulation time 1206744701 ps
CPU time 269.04 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:08:20 PM PDT 24
Peak memory 207656 kb
Host smart-6c4e2dd9-f81f-4af5-81fa-1241439fb560
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1053613629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_ran
d_reset.1053613629
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3441893383
Short name T266
Test name
Test status
Simulation time 11323480024 ps
CPU time 164.13 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:06:31 PM PDT 24
Peak memory 210624 kb
Host smart-4443b7b9-1aaa-42c2-afb6-2ceba08693e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3441893383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_re
set_error.3441893383
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/35.xbar_unmapped_addr.3012879900
Short name T745
Test name
Test status
Simulation time 191218347 ps
CPU time 6.27 seconds
Started Mar 12 01:03:47 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 211148 kb
Host smart-d31af062-fbe4-4f48-9afc-faaf471779a8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3012879900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3012879900
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device.3678191900
Short name T142
Test name
Test status
Simulation time 1411648710 ps
CPU time 17.07 seconds
Started Mar 12 01:03:47 PM PDT 24
Finished Mar 12 01:04:05 PM PDT 24
Peak memory 211100 kb
Host smart-1e67ed36-54db-4a0f-b33d-38d8fcf4d4fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3678191900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.3678191900
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2713966273
Short name T211
Test name
Test status
Simulation time 25945584291 ps
CPU time 84.73 seconds
Started Mar 12 01:03:55 PM PDT 24
Finished Mar 12 01:05:20 PM PDT 24
Peak memory 204320 kb
Host smart-173569b7-a921-42ac-8084-b9f0396529a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2713966273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_sl
ow_rsp.2713966273
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.3798022367
Short name T746
Test name
Test status
Simulation time 131209074 ps
CPU time 8.05 seconds
Started Mar 12 01:03:45 PM PDT 24
Finished Mar 12 01:03:54 PM PDT 24
Peak memory 202944 kb
Host smart-0d2dc369-9e43-4ffd-ad9f-9da5c46db46b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3798022367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3798022367
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_error_random.2526434504
Short name T68
Test name
Test status
Simulation time 1084290028 ps
CPU time 25.78 seconds
Started Mar 12 01:03:55 PM PDT 24
Finished Mar 12 01:04:22 PM PDT 24
Peak memory 202880 kb
Host smart-f04ba0eb-6471-42a9-8249-8e101467dc50
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2526434504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2526434504
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random.3789021454
Short name T175
Test name
Test status
Simulation time 2863296650 ps
CPU time 17.96 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:04:08 PM PDT 24
Peak memory 204192 kb
Host smart-eed2823f-331f-4e72-8957-e19aee81d31e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3789021454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3789021454
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_large_delays.2164437842
Short name T345
Test name
Test status
Simulation time 8498980475 ps
CPU time 40.42 seconds
Started Mar 12 01:04:02 PM PDT 24
Finished Mar 12 01:04:43 PM PDT 24
Peak memory 204092 kb
Host smart-12300c3d-f4b0-41c9-b680-c5bdd94a069e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164437842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2164437842
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_slow_rsp.138158309
Short name T896
Test name
Test status
Simulation time 4424706821 ps
CPU time 30.08 seconds
Started Mar 12 01:03:47 PM PDT 24
Finished Mar 12 01:04:18 PM PDT 24
Peak memory 204036 kb
Host smart-012b8836-911b-46c2-abe3-b7d84645352d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=138158309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.138158309
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_random_zero_delays.2534636054
Short name T812
Test name
Test status
Simulation time 67813943 ps
CPU time 6.97 seconds
Started Mar 12 01:03:48 PM PDT 24
Finished Mar 12 01:03:56 PM PDT 24
Peak memory 203940 kb
Host smart-b8c4678b-c61f-4abc-a10e-b774b9e0522e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534636054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2534636054
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_same_source.2067396767
Short name T111
Test name
Test status
Simulation time 179322766 ps
CPU time 12.08 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:03:58 PM PDT 24
Peak memory 202968 kb
Host smart-c1a96820-a8ab-4450-8b62-ce57e9e1b3f6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2067396767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2067396767
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke.373418602
Short name T191
Test name
Test status
Simulation time 307160200 ps
CPU time 2.87 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:03:53 PM PDT 24
Peak memory 202880 kb
Host smart-cecf05a3-3d80-45e7-b2a8-53042af73f60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=373418602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.373418602
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3454124335
Short name T183
Test name
Test status
Simulation time 17881122378 ps
CPU time 35.07 seconds
Started Mar 12 01:03:45 PM PDT 24
Finished Mar 12 01:04:20 PM PDT 24
Peak memory 203020 kb
Host smart-e40c5aa5-8bd2-470b-9561-c26705fe1b3a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454124335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3454124335
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3296105898
Short name T634
Test name
Test status
Simulation time 13676139387 ps
CPU time 38.4 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:04:24 PM PDT 24
Peak memory 202840 kb
Host smart-52ca87ea-5531-48ef-975a-defc03d65f42
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3296105898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3296105898
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1112294455
Short name T334
Test name
Test status
Simulation time 31118715 ps
CPU time 2.24 seconds
Started Mar 12 01:03:47 PM PDT 24
Finished Mar 12 01:03:50 PM PDT 24
Peak memory 202928 kb
Host smart-c0a72d98-7aa2-4a0e-bf2a-375fa851bfc6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112294455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1112294455
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all.1879763129
Short name T567
Test name
Test status
Simulation time 1656270168 ps
CPU time 53.31 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:56 PM PDT 24
Peak memory 204712 kb
Host smart-e78cec70-71fb-4999-8717-37c6966aaeeb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1879763129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1879763129
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3757483267
Short name T505
Test name
Test status
Simulation time 360098875 ps
CPU time 47.84 seconds
Started Mar 12 01:03:52 PM PDT 24
Finished Mar 12 01:04:40 PM PDT 24
Peak memory 204712 kb
Host smart-492eba9a-09cb-4fa8-8e95-7f022ae3bcef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3757483267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3757483267
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.2209591585
Short name T212
Test name
Test status
Simulation time 1173469056 ps
CPU time 126.43 seconds
Started Mar 12 01:03:45 PM PDT 24
Finished Mar 12 01:05:51 PM PDT 24
Peak memory 207668 kb
Host smart-3caea330-7fe9-4bd2-848d-4e6d113d040a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2209591585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_ran
d_reset.2209591585
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3668345539
Short name T489
Test name
Test status
Simulation time 988016203 ps
CPU time 215.14 seconds
Started Mar 12 01:03:50 PM PDT 24
Finished Mar 12 01:07:27 PM PDT 24
Peak memory 211108 kb
Host smart-6ff795f5-79aa-4745-b3b5-2dc81c1512cd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3668345539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_re
set_error.3668345539
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/36.xbar_unmapped_addr.4059580763
Short name T410
Test name
Test status
Simulation time 111409161 ps
CPU time 14.92 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:04:05 PM PDT 24
Peak memory 204196 kb
Host smart-630d8421-0c56-40ea-807e-8f3c8f954dc6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4059580763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.4059580763
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device.2106718133
Short name T449
Test name
Test status
Simulation time 200085269 ps
CPU time 40.1 seconds
Started Mar 12 01:03:51 PM PDT 24
Finished Mar 12 01:04:32 PM PDT 24
Peak memory 205592 kb
Host smart-02e72f8f-80e4-4823-ae31-576326e4f48e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2106718133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.2106718133
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.1673844774
Short name T750
Test name
Test status
Simulation time 182503793018 ps
CPU time 711.96 seconds
Started Mar 12 01:03:51 PM PDT 24
Finished Mar 12 01:15:44 PM PDT 24
Peak memory 211156 kb
Host smart-bf1a316d-ce7f-4669-940b-607128e920a8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1673844774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_sl
ow_rsp.1673844774
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1328730059
Short name T319
Test name
Test status
Simulation time 175409824 ps
CPU time 16.31 seconds
Started Mar 12 01:03:50 PM PDT 24
Finished Mar 12 01:04:07 PM PDT 24
Peak memory 203292 kb
Host smart-628cc463-ebf5-434d-98ef-aaa7a0800fed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1328730059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1328730059
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_error_random.654827380
Short name T777
Test name
Test status
Simulation time 59906825 ps
CPU time 4.19 seconds
Started Mar 12 01:03:57 PM PDT 24
Finished Mar 12 01:04:01 PM PDT 24
Peak memory 202916 kb
Host smart-0ef3b20c-218b-4abf-95e7-8e62fc08b6c7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=654827380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.654827380
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random.18065421
Short name T621
Test name
Test status
Simulation time 400813408 ps
CPU time 23.83 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:04:14 PM PDT 24
Peak memory 211036 kb
Host smart-325d6e91-1134-4855-963b-134a5158b60d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=18065421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.18065421
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_large_delays.3142537230
Short name T100
Test name
Test status
Simulation time 27248405340 ps
CPU time 169.11 seconds
Started Mar 12 01:03:51 PM PDT 24
Finished Mar 12 01:06:41 PM PDT 24
Peak memory 204104 kb
Host smart-16e24c59-6bf5-459a-8bf5-6892f6f4669d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142537230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3142537230
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2283861712
Short name T526
Test name
Test status
Simulation time 8597245317 ps
CPU time 25.82 seconds
Started Mar 12 01:03:48 PM PDT 24
Finished Mar 12 01:04:15 PM PDT 24
Peak memory 202972 kb
Host smart-9bdc9ae5-13cf-4f2e-8a1b-7b0ef499ebff
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2283861712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2283861712
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_random_zero_delays.3833484275
Short name T280
Test name
Test status
Simulation time 514189843 ps
CPU time 14.66 seconds
Started Mar 12 01:03:48 PM PDT 24
Finished Mar 12 01:04:04 PM PDT 24
Peak memory 204160 kb
Host smart-bab3eabd-4caf-4e9e-b1cd-88a7ab06d945
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833484275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3833484275
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_same_source.3597450784
Short name T577
Test name
Test status
Simulation time 325236471 ps
CPU time 9.91 seconds
Started Mar 12 01:03:51 PM PDT 24
Finished Mar 12 01:04:01 PM PDT 24
Peak memory 202924 kb
Host smart-b7720427-2418-4b92-a7a8-f00d4e486145
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3597450784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3597450784
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke.3579282673
Short name T448
Test name
Test status
Simulation time 114830117 ps
CPU time 2.64 seconds
Started Mar 12 01:03:48 PM PDT 24
Finished Mar 12 01:03:52 PM PDT 24
Peak memory 202960 kb
Host smart-29533507-78b7-4f0d-990b-08cfae135955
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3579282673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3579282673
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1138878883
Short name T358
Test name
Test status
Simulation time 12652432102 ps
CPU time 35.78 seconds
Started Mar 12 01:03:57 PM PDT 24
Finished Mar 12 01:04:33 PM PDT 24
Peak memory 202868 kb
Host smart-82959224-a2e0-4f1f-b567-d423c5224ca0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138878883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1138878883
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1247645346
Short name T361
Test name
Test status
Simulation time 2515451767 ps
CPU time 24.01 seconds
Started Mar 12 01:03:56 PM PDT 24
Finished Mar 12 01:04:20 PM PDT 24
Peak memory 202972 kb
Host smart-8716a0d4-08bc-4f0d-9bef-d9e029a5cf5b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1247645346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1247645346
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2116817554
Short name T152
Test name
Test status
Simulation time 96074976 ps
CPU time 2.04 seconds
Started Mar 12 01:03:50 PM PDT 24
Finished Mar 12 01:03:53 PM PDT 24
Peak memory 202908 kb
Host smart-d2e5c849-b126-496a-af03-feb89ee59dc2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116817554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2116817554
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all.1810535253
Short name T64
Test name
Test status
Simulation time 1387389213 ps
CPU time 31.66 seconds
Started Mar 12 01:03:46 PM PDT 24
Finished Mar 12 01:04:18 PM PDT 24
Peak memory 205304 kb
Host smart-f1dbd0e8-52fb-4478-8609-1584f6acd7d6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1810535253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1810535253
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2402129054
Short name T773
Test name
Test status
Simulation time 1606434212 ps
CPU time 115.93 seconds
Started Mar 12 01:03:51 PM PDT 24
Finished Mar 12 01:05:47 PM PDT 24
Peak memory 207256 kb
Host smart-36be473f-7010-4d42-8da2-fe62dd0e0766
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2402129054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2402129054
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2265268515
Short name T729
Test name
Test status
Simulation time 1696365003 ps
CPU time 224.08 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:07:47 PM PDT 24
Peak memory 207952 kb
Host smart-01179d91-ed4e-40d7-884d-ee1d79d1b502
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2265268515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_ran
d_reset.2265268515
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2670582059
Short name T393
Test name
Test status
Simulation time 154822466 ps
CPU time 38.85 seconds
Started Mar 12 01:03:49 PM PDT 24
Finished Mar 12 01:04:29 PM PDT 24
Peak memory 205564 kb
Host smart-f738d954-f453-44c6-b91f-c6dfe321f136
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2670582059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_re
set_error.2670582059
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/37.xbar_unmapped_addr.1486154223
Short name T306
Test name
Test status
Simulation time 199926687 ps
CPU time 14 seconds
Started Mar 12 01:04:02 PM PDT 24
Finished Mar 12 01:04:16 PM PDT 24
Peak memory 204136 kb
Host smart-b3c12252-61dd-4588-b475-9d8da0e8dfb4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1486154223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1486154223
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device.2857816918
Short name T226
Test name
Test status
Simulation time 324276028 ps
CPU time 44.96 seconds
Started Mar 12 01:04:06 PM PDT 24
Finished Mar 12 01:04:53 PM PDT 24
Peak memory 204868 kb
Host smart-0809abe8-a6a5-47f3-82b2-6db5c9fef547
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2857816918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2857816918
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.654442305
Short name T875
Test name
Test status
Simulation time 49204848332 ps
CPU time 432.91 seconds
Started Mar 12 01:04:02 PM PDT 24
Finished Mar 12 01:11:15 PM PDT 24
Peak memory 211120 kb
Host smart-f801612e-4eb7-46bd-a47e-c4fd380ce23d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=654442305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slo
w_rsp.654442305
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2366804105
Short name T705
Test name
Test status
Simulation time 484798289 ps
CPU time 7.18 seconds
Started Mar 12 01:03:58 PM PDT 24
Finished Mar 12 01:04:05 PM PDT 24
Peak memory 202928 kb
Host smart-2da8ac91-a7a0-4cd6-ac21-f40e67bada0e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2366804105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2366804105
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_error_random.2597852279
Short name T411
Test name
Test status
Simulation time 71220575 ps
CPU time 4.41 seconds
Started Mar 12 01:03:55 PM PDT 24
Finished Mar 12 01:04:01 PM PDT 24
Peak memory 202932 kb
Host smart-c02490fa-7fb4-4015-919c-6ecd94b1b7de
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2597852279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2597852279
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random.3872451505
Short name T144
Test name
Test status
Simulation time 954598635 ps
CPU time 17.75 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:20 PM PDT 24
Peak memory 204220 kb
Host smart-6c801307-c626-452a-8120-cce74d757788
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3872451505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3872451505
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_large_delays.3448565750
Short name T58
Test name
Test status
Simulation time 32706053924 ps
CPU time 163.13 seconds
Started Mar 12 01:03:50 PM PDT 24
Finished Mar 12 01:06:34 PM PDT 24
Peak memory 211156 kb
Host smart-d966bed3-906d-4d85-b10c-23e79a43d995
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448565750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3448565750
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_slow_rsp.4146808085
Short name T357
Test name
Test status
Simulation time 7242160313 ps
CPU time 64.09 seconds
Started Mar 12 01:03:51 PM PDT 24
Finished Mar 12 01:04:56 PM PDT 24
Peak memory 211164 kb
Host smart-9c0e0ea0-55a5-45ae-a07c-862655eea2a6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4146808085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.4146808085
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_random_zero_delays.1279070026
Short name T612
Test name
Test status
Simulation time 284455449 ps
CPU time 18.94 seconds
Started Mar 12 01:03:48 PM PDT 24
Finished Mar 12 01:04:08 PM PDT 24
Peak memory 204168 kb
Host smart-f66db0fc-2c6e-4d60-83d0-6036fc2a0fda
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279070026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1279070026
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_same_source.3289463973
Short name T23
Test name
Test status
Simulation time 2651234761 ps
CPU time 31.76 seconds
Started Mar 12 01:04:04 PM PDT 24
Finished Mar 12 01:04:37 PM PDT 24
Peak memory 202996 kb
Host smart-5a4a0a8c-4403-4635-9f7e-c194a8cf20eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3289463973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3289463973
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke.2736191627
Short name T149
Test name
Test status
Simulation time 158705109 ps
CPU time 3.14 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:06 PM PDT 24
Peak memory 202884 kb
Host smart-cc0a58d2-feae-4ad1-80c4-33a363097c72
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2736191627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2736191627
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_large_delays.511265550
Short name T736
Test name
Test status
Simulation time 5633298713 ps
CPU time 28.35 seconds
Started Mar 12 01:04:02 PM PDT 24
Finished Mar 12 01:04:30 PM PDT 24
Peak memory 202956 kb
Host smart-80c9385e-232a-49b1-a0f5-aa1f70311e08
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=511265550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.511265550
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.2870152586
Short name T433
Test name
Test status
Simulation time 7299142221 ps
CPU time 32.6 seconds
Started Mar 12 01:04:05 PM PDT 24
Finished Mar 12 01:04:38 PM PDT 24
Peak memory 202964 kb
Host smart-260412b6-8791-4fc7-b419-c91499a19085
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2870152586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2870152586
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.2533739442
Short name T481
Test name
Test status
Simulation time 68805481 ps
CPU time 2.37 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:05 PM PDT 24
Peak memory 202804 kb
Host smart-15aae4fa-ec4d-468c-bfa5-5235b3b8e3c1
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533739442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.2533739442
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all.2881087328
Short name T849
Test name
Test status
Simulation time 10091128395 ps
CPU time 135.9 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:06:19 PM PDT 24
Peak memory 207792 kb
Host smart-42a3e413-ba0f-4952-b357-0b5ab4314133
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2881087328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2881087328
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3064998469
Short name T554
Test name
Test status
Simulation time 5563404840 ps
CPU time 146.39 seconds
Started Mar 12 01:03:59 PM PDT 24
Finished Mar 12 01:06:26 PM PDT 24
Peak memory 206948 kb
Host smart-f01b9963-92f2-4a2d-b3a7-fab90ea2bfef
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3064998469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3064998469
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.1579247280
Short name T129
Test name
Test status
Simulation time 188850295 ps
CPU time 68.86 seconds
Started Mar 12 01:04:00 PM PDT 24
Finished Mar 12 01:05:09 PM PDT 24
Peak memory 207248 kb
Host smart-8b74e1a6-3b6b-4781-a7c8-1a6ccc22ce19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1579247280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_ran
d_reset.1579247280
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/38.xbar_unmapped_addr.1966314451
Short name T573
Test name
Test status
Simulation time 289267021 ps
CPU time 19.87 seconds
Started Mar 12 01:03:59 PM PDT 24
Finished Mar 12 01:04:19 PM PDT 24
Peak memory 204244 kb
Host smart-e0b4e94e-1511-490d-96bf-d0a4b031d9a4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1966314451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1966314451
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device.386025239
Short name T46
Test name
Test status
Simulation time 1098653675 ps
CPU time 35.12 seconds
Started Mar 12 01:04:04 PM PDT 24
Finished Mar 12 01:04:41 PM PDT 24
Peak memory 205120 kb
Host smart-db37c501-6c63-4633-b4d8-36b046de1eda
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=386025239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.386025239
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.2552298354
Short name T184
Test name
Test status
Simulation time 23479591084 ps
CPU time 44.51 seconds
Started Mar 12 01:04:05 PM PDT 24
Finished Mar 12 01:04:50 PM PDT 24
Peak memory 202980 kb
Host smart-d64a80e3-ed13-4cbb-ae91-e16538da9233
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2552298354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_sl
ow_rsp.2552298354
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3988757353
Short name T491
Test name
Test status
Simulation time 110501875 ps
CPU time 15.28 seconds
Started Mar 12 01:04:01 PM PDT 24
Finished Mar 12 01:04:17 PM PDT 24
Peak memory 203192 kb
Host smart-a22af527-09b5-4191-ba19-9f9468562ccc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3988757353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3988757353
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_error_random.735516692
Short name T519
Test name
Test status
Simulation time 70080158 ps
CPU time 6.91 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:12 PM PDT 24
Peak memory 202928 kb
Host smart-2d8e63f8-2596-4d00-99db-a754987196f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=735516692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.735516692
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random.2525667792
Short name T207
Test name
Test status
Simulation time 358085075 ps
CPU time 10.2 seconds
Started Mar 12 01:04:01 PM PDT 24
Finished Mar 12 01:04:12 PM PDT 24
Peak memory 204016 kb
Host smart-171d84eb-dcee-4094-9709-150b0981477f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2525667792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2525667792
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_large_delays.1068344005
Short name T10
Test name
Test status
Simulation time 15972954322 ps
CPU time 101.13 seconds
Started Mar 12 01:04:01 PM PDT 24
Finished Mar 12 01:05:42 PM PDT 24
Peak memory 211112 kb
Host smart-a987b347-79f4-4d41-81e3-5a1e20beb96d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068344005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1068344005
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_slow_rsp.2447560773
Short name T193
Test name
Test status
Simulation time 77926005476 ps
CPU time 188.62 seconds
Started Mar 12 01:03:59 PM PDT 24
Finished Mar 12 01:07:08 PM PDT 24
Peak memory 204376 kb
Host smart-2db4e39d-4e66-4b2c-87c3-fef2be82b438
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2447560773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2447560773
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_random_zero_delays.2479375399
Short name T547
Test name
Test status
Simulation time 43780860 ps
CPU time 5.69 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:09 PM PDT 24
Peak memory 203984 kb
Host smart-ca1c4f58-8f5b-4074-9c9b-ea484fd2afaa
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479375399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.2479375399
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_same_source.3449171605
Short name T807
Test name
Test status
Simulation time 388291054 ps
CPU time 11.94 seconds
Started Mar 12 01:03:59 PM PDT 24
Finished Mar 12 01:04:11 PM PDT 24
Peak memory 203296 kb
Host smart-d3af09aa-48c7-40dc-ae17-6f272665dfab
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3449171605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3449171605
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke.3855188426
Short name T510
Test name
Test status
Simulation time 33759264 ps
CPU time 2.22 seconds
Started Mar 12 01:04:05 PM PDT 24
Finished Mar 12 01:04:08 PM PDT 24
Peak memory 202896 kb
Host smart-f93008e0-3a6f-4ff3-81b3-7a71d777dae0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3855188426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3855188426
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3987929646
Short name T752
Test name
Test status
Simulation time 5376671106 ps
CPU time 24.44 seconds
Started Mar 12 01:03:57 PM PDT 24
Finished Mar 12 01:04:21 PM PDT 24
Peak memory 202908 kb
Host smart-bbb5f3f5-b729-45bb-b523-40d149484f4a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987929646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3987929646
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3019142595
Short name T11
Test name
Test status
Simulation time 2512027768 ps
CPU time 23.72 seconds
Started Mar 12 01:03:57 PM PDT 24
Finished Mar 12 01:04:20 PM PDT 24
Peak memory 202992 kb
Host smart-d6c96ac5-bd69-416c-98a0-32b1e16127cc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3019142595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3019142595
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.847450471
Short name T455
Test name
Test status
Simulation time 49279803 ps
CPU time 2.15 seconds
Started Mar 12 01:04:01 PM PDT 24
Finished Mar 12 01:04:04 PM PDT 24
Peak memory 202944 kb
Host smart-738b5e85-de12-4e8b-a3fb-3be1d2f6e292
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847450471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.847450471
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all.184150422
Short name T517
Test name
Test status
Simulation time 15207161696 ps
CPU time 174.52 seconds
Started Mar 12 01:03:58 PM PDT 24
Finished Mar 12 01:06:52 PM PDT 24
Peak memory 211180 kb
Host smart-f061eef4-c680-4184-8fc3-ee55ae17e3e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=184150422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.184150422
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_error.2135040801
Short name T853
Test name
Test status
Simulation time 2478074257 ps
CPU time 244.43 seconds
Started Mar 12 01:04:05 PM PDT 24
Finished Mar 12 01:08:10 PM PDT 24
Peak memory 212208 kb
Host smart-f16e07bd-5421-4899-b7dd-6fb5101eea81
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2135040801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2135040801
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1177800946
Short name T27
Test name
Test status
Simulation time 226697324 ps
CPU time 79.11 seconds
Started Mar 12 01:04:05 PM PDT 24
Finished Mar 12 01:05:25 PM PDT 24
Peak memory 207504 kb
Host smart-05e33a19-e90b-4189-9df9-043ee99b6c11
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1177800946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_ran
d_reset.1177800946
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.800237288
Short name T748
Test name
Test status
Simulation time 2222209529 ps
CPU time 90.13 seconds
Started Mar 12 01:04:08 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 207876 kb
Host smart-7843a8a2-0b5f-4887-9c13-ae629442c723
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=800237288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_res
et_error.800237288
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/39.xbar_unmapped_addr.570719696
Short name T856
Test name
Test status
Simulation time 475931580 ps
CPU time 5.59 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:09 PM PDT 24
Peak memory 204060 kb
Host smart-e7f712a5-7c00-4f06-bc72-312ca108eca4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=570719696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.570719696
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device.708679995
Short name T135
Test name
Test status
Simulation time 1468484715 ps
CPU time 47.22 seconds
Started Mar 12 01:02:23 PM PDT 24
Finished Mar 12 01:03:10 PM PDT 24
Peak memory 205420 kb
Host smart-ed1a88ed-0a8d-4f57-9370-c433fa8790b6
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=708679995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.708679995
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.3388655604
Short name T664
Test name
Test status
Simulation time 67063811053 ps
CPU time 181.87 seconds
Started Mar 12 01:02:09 PM PDT 24
Finished Mar 12 01:05:12 PM PDT 24
Peak memory 211156 kb
Host smart-e62ff1d8-f7f5-40e6-92c9-96635c013841
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3388655604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slo
w_rsp.3388655604
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3617746697
Short name T851
Test name
Test status
Simulation time 372813971 ps
CPU time 9.26 seconds
Started Mar 12 01:02:15 PM PDT 24
Finished Mar 12 01:02:25 PM PDT 24
Peak memory 202912 kb
Host smart-7b650ae4-1429-47fc-8694-4ba96dccc1bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3617746697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3617746697
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_error_random.4098159114
Short name T620
Test name
Test status
Simulation time 1117958337 ps
CPU time 13.75 seconds
Started Mar 12 01:02:29 PM PDT 24
Finished Mar 12 01:02:43 PM PDT 24
Peak memory 202932 kb
Host smart-a793a521-39c2-481c-9c1c-fe3e56f2b2fe
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4098159114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.4098159114
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random.268458826
Short name T706
Test name
Test status
Simulation time 93173683 ps
CPU time 10.75 seconds
Started Mar 12 01:02:24 PM PDT 24
Finished Mar 12 01:02:35 PM PDT 24
Peak memory 211120 kb
Host smart-d66c4ad8-f8e4-4523-8121-08b8236c5f65
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=268458826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.268458826
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_large_delays.4285746220
Short name T242
Test name
Test status
Simulation time 39801078956 ps
CPU time 240.9 seconds
Started Mar 12 01:02:28 PM PDT 24
Finished Mar 12 01:06:30 PM PDT 24
Peak memory 204404 kb
Host smart-015fd2bc-a43f-44ba-9971-378944147eb7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285746220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.4285746220
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3065609566
Short name T897
Test name
Test status
Simulation time 32323574524 ps
CPU time 236.63 seconds
Started Mar 12 01:02:04 PM PDT 24
Finished Mar 12 01:06:06 PM PDT 24
Peak memory 211160 kb
Host smart-f31263e4-effe-4da9-acf7-30beadec3581
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3065609566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3065609566
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_random_zero_delays.2861031196
Short name T366
Test name
Test status
Simulation time 79719439 ps
CPU time 10.75 seconds
Started Mar 12 01:02:20 PM PDT 24
Finished Mar 12 01:02:31 PM PDT 24
Peak memory 204060 kb
Host smart-00826134-863a-4e34-a6b2-c1b9a474b732
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861031196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2861031196
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_same_source.663474921
Short name T383
Test name
Test status
Simulation time 1016663214 ps
CPU time 6.57 seconds
Started Mar 12 01:02:27 PM PDT 24
Finished Mar 12 01:02:34 PM PDT 24
Peak memory 202788 kb
Host smart-c54639fd-2215-4731-83ac-3900e2194b66
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=663474921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.663474921
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke.1699688466
Short name T398
Test name
Test status
Simulation time 23555033 ps
CPU time 2.42 seconds
Started Mar 12 01:02:28 PM PDT 24
Finished Mar 12 01:02:31 PM PDT 24
Peak memory 202872 kb
Host smart-5950fd82-402c-48b1-9e1e-ac27b0d9c645
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1699688466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1699688466
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2190050246
Short name T636
Test name
Test status
Simulation time 23311094654 ps
CPU time 34.78 seconds
Started Mar 12 01:02:24 PM PDT 24
Finished Mar 12 01:02:59 PM PDT 24
Peak memory 202984 kb
Host smart-f341b0c8-4963-4bef-a5d2-7ae43d236aa8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190050246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2190050246
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.893609670
Short name T5
Test name
Test status
Simulation time 5065154677 ps
CPU time 33.03 seconds
Started Mar 12 01:02:17 PM PDT 24
Finished Mar 12 01:02:51 PM PDT 24
Peak memory 202972 kb
Host smart-190bc16f-a224-4cb9-8fc4-2535c38b2f0f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=893609670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.893609670
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1848628707
Short name T97
Test name
Test status
Simulation time 92017850 ps
CPU time 2.16 seconds
Started Mar 12 01:02:17 PM PDT 24
Finished Mar 12 01:02:20 PM PDT 24
Peak memory 202888 kb
Host smart-ec3b511a-56f8-4450-8038-31298ebe06b9
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848628707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1848628707
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all.3201567245
Short name T881
Test name
Test status
Simulation time 44193194020 ps
CPU time 325.11 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:07:47 PM PDT 24
Peak memory 209160 kb
Host smart-2f6bf0bd-2c71-4e7c-a34e-59f0626f4543
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3201567245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3201567245
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1637758249
Short name T308
Test name
Test status
Simulation time 1352766142 ps
CPU time 130.75 seconds
Started Mar 12 01:02:24 PM PDT 24
Finished Mar 12 01:04:35 PM PDT 24
Peak memory 207844 kb
Host smart-8db2e2c4-07cb-4175-b620-36545422e6d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1637758249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1637758249
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1745854572
Short name T767
Test name
Test status
Simulation time 69201939 ps
CPU time 45.77 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:03:16 PM PDT 24
Peak memory 206516 kb
Host smart-4a7b0d60-85ac-4c2b-827e-2e0fcdc6673d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1745854572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand
_reset.1745854572
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3261632717
Short name T879
Test name
Test status
Simulation time 3863606396 ps
CPU time 244.97 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:06:23 PM PDT 24
Peak memory 219276 kb
Host smart-e363352a-a30d-4de0-be83-7423c819483f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3261632717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_res
et_error.3261632717
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/4.xbar_unmapped_addr.2412518669
Short name T662
Test name
Test status
Simulation time 723412536 ps
CPU time 31.71 seconds
Started Mar 12 01:02:29 PM PDT 24
Finished Mar 12 01:03:00 PM PDT 24
Peak memory 211112 kb
Host smart-b2a4019a-a4b6-44fb-8e0d-d50e5a409e7e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2412518669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2412518669
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device.92476850
Short name T395
Test name
Test status
Simulation time 1661327849 ps
CPU time 66.3 seconds
Started Mar 12 01:04:07 PM PDT 24
Finished Mar 12 01:05:14 PM PDT 24
Peak memory 211144 kb
Host smart-c8b7a1a7-c24d-4a66-abff-5c087065aad7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92476850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.92476850
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.614052648
Short name T452
Test name
Test status
Simulation time 11375489820 ps
CPU time 104.15 seconds
Started Mar 12 01:04:04 PM PDT 24
Finished Mar 12 01:05:50 PM PDT 24
Peak memory 211176 kb
Host smart-c2c918f3-5f2a-4fd9-946f-a1390901b725
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=614052648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slo
w_rsp.614052648
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.2854633973
Short name T596
Test name
Test status
Simulation time 2276673178 ps
CPU time 19.9 seconds
Started Mar 12 01:03:58 PM PDT 24
Finished Mar 12 01:04:18 PM PDT 24
Peak memory 202988 kb
Host smart-4107d007-37c1-4f33-801a-2630c27f60d1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2854633973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.2854633973
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_error_random.3076674583
Short name T576
Test name
Test status
Simulation time 324691786 ps
CPU time 12.39 seconds
Started Mar 12 01:04:02 PM PDT 24
Finished Mar 12 01:04:14 PM PDT 24
Peak memory 202940 kb
Host smart-0b4c5e12-4118-4b26-8220-b555cd0ef5ed
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3076674583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3076674583
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random.3196573950
Short name T727
Test name
Test status
Simulation time 382260317 ps
CPU time 13.54 seconds
Started Mar 12 01:04:05 PM PDT 24
Finished Mar 12 01:04:19 PM PDT 24
Peak memory 203936 kb
Host smart-d62a87aa-9da7-4f36-a6c3-4b81cc09e258
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3196573950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3196573950
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_large_delays.1999847672
Short name T778
Test name
Test status
Simulation time 26720605634 ps
CPU time 117.64 seconds
Started Mar 12 01:04:02 PM PDT 24
Finished Mar 12 01:06:00 PM PDT 24
Peak memory 204064 kb
Host smart-8bb2f2e2-fcc6-47c3-a7e5-16b55b322ae3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999847672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1999847672
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2533889859
Short name T888
Test name
Test status
Simulation time 2867726632 ps
CPU time 21.26 seconds
Started Mar 12 01:03:57 PM PDT 24
Finished Mar 12 01:04:19 PM PDT 24
Peak memory 211120 kb
Host smart-c8e32e45-3ae6-4e4a-bc45-61041e168b9f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2533889859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2533889859
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_random_zero_delays.2477266883
Short name T790
Test name
Test status
Simulation time 194282098 ps
CPU time 26.63 seconds
Started Mar 12 01:03:58 PM PDT 24
Finished Mar 12 01:04:25 PM PDT 24
Peak memory 203828 kb
Host smart-762263b2-a8c0-4e73-9748-dd4a509e82ad
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477266883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2477266883
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_same_source.2773099823
Short name T197
Test name
Test status
Simulation time 1231563165 ps
CPU time 15.09 seconds
Started Mar 12 01:03:59 PM PDT 24
Finished Mar 12 01:04:14 PM PDT 24
Peak memory 203304 kb
Host smart-680c4040-0289-49f0-91cb-9d8a6a7437be
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2773099823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2773099823
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke.2814679149
Short name T841
Test name
Test status
Simulation time 65660476 ps
CPU time 2.28 seconds
Started Mar 12 01:04:04 PM PDT 24
Finished Mar 12 01:04:08 PM PDT 24
Peak memory 202792 kb
Host smart-8c935003-23db-46ff-a398-b8bd79fe52c8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2814679149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2814679149
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_large_delays.843166252
Short name T95
Test name
Test status
Simulation time 6201366617 ps
CPU time 27.2 seconds
Started Mar 12 01:03:59 PM PDT 24
Finished Mar 12 01:04:26 PM PDT 24
Peak memory 202988 kb
Host smart-7d1500a7-2973-4719-9bee-ba8c9e8b545b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=843166252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.843166252
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.567876256
Short name T544
Test name
Test status
Simulation time 12612755009 ps
CPU time 42.24 seconds
Started Mar 12 01:03:56 PM PDT 24
Finished Mar 12 01:04:39 PM PDT 24
Peak memory 202956 kb
Host smart-e655803c-8942-4e8e-85cc-1a26f6dfbc78
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=567876256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.567876256
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3007843122
Short name T721
Test name
Test status
Simulation time 54125619 ps
CPU time 2.52 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:05 PM PDT 24
Peak memory 202956 kb
Host smart-fd9b8571-4323-4c97-a609-f26d908d1d6b
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007843122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3007843122
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all.3837731551
Short name T80
Test name
Test status
Simulation time 9261204066 ps
CPU time 196.83 seconds
Started Mar 12 01:03:58 PM PDT 24
Finished Mar 12 01:07:15 PM PDT 24
Peak memory 209436 kb
Host smart-05ef93d8-ea58-4116-ac33-b3cfdd7dae99
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3837731551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3837731551
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_error.1799205849
Short name T722
Test name
Test status
Simulation time 3544267774 ps
CPU time 101.68 seconds
Started Mar 12 01:03:59 PM PDT 24
Finished Mar 12 01:05:41 PM PDT 24
Peak memory 206464 kb
Host smart-1f49c915-7c76-43c4-a2d1-1e0c30a41644
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1799205849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1799205849
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2739273711
Short name T600
Test name
Test status
Simulation time 1284156746 ps
CPU time 216.48 seconds
Started Mar 12 01:04:05 PM PDT 24
Finished Mar 12 01:07:42 PM PDT 24
Peak memory 219116 kb
Host smart-3b4a9546-3e3b-4f94-b649-b6ed22fb4b8b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2739273711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_ran
d_reset.2739273711
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.174945557
Short name T270
Test name
Test status
Simulation time 3190858054 ps
CPU time 284.35 seconds
Started Mar 12 01:04:04 PM PDT 24
Finished Mar 12 01:08:50 PM PDT 24
Peak memory 219376 kb
Host smart-fc118a20-794b-4128-bfd3-5bc3b2a1634e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=174945557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_res
et_error.174945557
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/40.xbar_unmapped_addr.2045194362
Short name T468
Test name
Test status
Simulation time 2680268779 ps
CPU time 32.72 seconds
Started Mar 12 01:04:01 PM PDT 24
Finished Mar 12 01:04:34 PM PDT 24
Peak memory 204616 kb
Host smart-b7e2540e-5e44-496f-b4f3-d6708c41f4b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2045194362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2045194362
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device.278830158
Short name T456
Test name
Test status
Simulation time 70069941 ps
CPU time 5.12 seconds
Started Mar 12 01:04:02 PM PDT 24
Finished Mar 12 01:04:07 PM PDT 24
Peak memory 203100 kb
Host smart-900ded00-ee90-4dc2-8395-c2f9a106dcb3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=278830158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.278830158
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.144288091
Short name T124
Test name
Test status
Simulation time 24203068815 ps
CPU time 194.06 seconds
Started Mar 12 01:04:06 PM PDT 24
Finished Mar 12 01:07:22 PM PDT 24
Peak memory 211120 kb
Host smart-31f1a306-1d9d-49bd-b49b-91ad968d1fc0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=144288091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slo
w_rsp.144288091
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.964834191
Short name T670
Test name
Test status
Simulation time 550469102 ps
CPU time 7.52 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:13 PM PDT 24
Peak memory 203020 kb
Host smart-9da877d7-0841-4dae-adce-d1b6f04d61ba
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=964834191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.964834191
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_error_random.2167971040
Short name T454
Test name
Test status
Simulation time 55603911 ps
CPU time 2.51 seconds
Started Mar 12 01:03:58 PM PDT 24
Finished Mar 12 01:04:01 PM PDT 24
Peak memory 202972 kb
Host smart-7b5d61da-8640-4408-8748-379ba9828697
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2167971040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2167971040
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random.2215161342
Short name T359
Test name
Test status
Simulation time 255174429 ps
CPU time 15.94 seconds
Started Mar 12 01:03:59 PM PDT 24
Finished Mar 12 01:04:15 PM PDT 24
Peak memory 204148 kb
Host smart-a4dabcee-8122-4471-8de0-a296c49e349f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2215161342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.2215161342
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_large_delays.3871173365
Short name T826
Test name
Test status
Simulation time 47088031325 ps
CPU time 217.5 seconds
Started Mar 12 01:04:06 PM PDT 24
Finished Mar 12 01:07:43 PM PDT 24
Peak memory 204148 kb
Host smart-db38a983-1609-4e90-b378-56abd7adf77b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871173365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3871173365
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_slow_rsp.1255936798
Short name T57
Test name
Test status
Simulation time 15997822522 ps
CPU time 105.42 seconds
Started Mar 12 01:04:02 PM PDT 24
Finished Mar 12 01:05:47 PM PDT 24
Peak memory 211152 kb
Host smart-50eb036a-bcb2-4c98-af3c-6efe4a8a5774
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1255936798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1255936798
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_random_zero_delays.3407669550
Short name T386
Test name
Test status
Simulation time 355919186 ps
CPU time 26.46 seconds
Started Mar 12 01:04:07 PM PDT 24
Finished Mar 12 01:04:34 PM PDT 24
Peak memory 204136 kb
Host smart-db80f299-844d-401d-8d87-a4cee4bfdeea
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407669550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.3407669550
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_same_source.2836876852
Short name T660
Test name
Test status
Simulation time 524310977 ps
CPU time 15.75 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:21 PM PDT 24
Peak memory 202852 kb
Host smart-3b2bd14e-b493-4abc-835c-9fd2e8d3ba30
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2836876852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2836876852
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke.2622075981
Short name T850
Test name
Test status
Simulation time 222171039 ps
CPU time 3.77 seconds
Started Mar 12 01:03:59 PM PDT 24
Finished Mar 12 01:04:03 PM PDT 24
Peak memory 202936 kb
Host smart-242b7888-8cd4-497c-b0c6-aefd65b44b8d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2622075981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2622075981
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2398631658
Short name T593
Test name
Test status
Simulation time 5187141915 ps
CPU time 31.42 seconds
Started Mar 12 01:04:00 PM PDT 24
Finished Mar 12 01:04:31 PM PDT 24
Peak memory 202968 kb
Host smart-31b706af-f1a0-48de-b854-8cd90a180031
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398631658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2398631658
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1392976955
Short name T653
Test name
Test status
Simulation time 4765723239 ps
CPU time 26.09 seconds
Started Mar 12 01:04:04 PM PDT 24
Finished Mar 12 01:04:31 PM PDT 24
Peak memory 202940 kb
Host smart-d56a308b-5c00-4ba9-b542-5cdac5af90fc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1392976955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1392976955
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2820048040
Short name T401
Test name
Test status
Simulation time 63225564 ps
CPU time 2.3 seconds
Started Mar 12 01:04:02 PM PDT 24
Finished Mar 12 01:04:04 PM PDT 24
Peak memory 202856 kb
Host smart-72183d84-19ca-4cc9-b50b-b9b151edc6f3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820048040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2820048040
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all.2615197594
Short name T104
Test name
Test status
Simulation time 3265151463 ps
CPU time 64.25 seconds
Started Mar 12 01:03:59 PM PDT 24
Finished Mar 12 01:05:04 PM PDT 24
Peak memory 205248 kb
Host smart-96abe7a9-c1c8-45ed-9d9d-5a05a8be0ed1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2615197594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2615197594
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2420491622
Short name T429
Test name
Test status
Simulation time 19492109167 ps
CPU time 138.39 seconds
Started Mar 12 01:04:06 PM PDT 24
Finished Mar 12 01:06:24 PM PDT 24
Peak memory 211192 kb
Host smart-36857c14-ffc6-46a1-8c95-7bd273af00eb
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2420491622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2420491622
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1746030367
Short name T730
Test name
Test status
Simulation time 7686464802 ps
CPU time 447.71 seconds
Started Mar 12 01:04:07 PM PDT 24
Finished Mar 12 01:11:35 PM PDT 24
Peak memory 221208 kb
Host smart-7e50fc9f-37f2-4985-9e52-42391a9e0e44
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1746030367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_ran
d_reset.1746030367
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/41.xbar_unmapped_addr.1031119047
Short name T843
Test name
Test status
Simulation time 298457030 ps
CPU time 13.14 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:16 PM PDT 24
Peak memory 204248 kb
Host smart-35b24d54-5384-4682-ac18-1ee8993753e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1031119047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1031119047
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device.915564879
Short name T527
Test name
Test status
Simulation time 317603259 ps
CPU time 7.28 seconds
Started Mar 12 01:04:04 PM PDT 24
Finished Mar 12 01:04:13 PM PDT 24
Peak memory 203136 kb
Host smart-0fe97c82-388d-455b-9ece-744b7d10d6f5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=915564879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.915564879
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1442059291
Short name T192
Test name
Test status
Simulation time 97406930185 ps
CPU time 440.02 seconds
Started Mar 12 01:04:09 PM PDT 24
Finished Mar 12 01:11:29 PM PDT 24
Peak memory 205244 kb
Host smart-21d87ce8-5e5d-422f-a906-488d2357adcc
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1442059291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_sl
ow_rsp.1442059291
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.448783273
Short name T641
Test name
Test status
Simulation time 375691864 ps
CPU time 10.83 seconds
Started Mar 12 01:04:11 PM PDT 24
Finished Mar 12 01:04:22 PM PDT 24
Peak memory 202992 kb
Host smart-ba8a8f2f-fb3c-43d1-bbd7-4b956280a3ea
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=448783273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.448783273
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_error_random.3677116864
Short name T789
Test name
Test status
Simulation time 501982211 ps
CPU time 6.81 seconds
Started Mar 12 01:04:05 PM PDT 24
Finished Mar 12 01:04:12 PM PDT 24
Peak memory 202840 kb
Host smart-993d31c1-33cb-4d7a-a3e8-8caf103ec4ce
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3677116864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3677116864
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random.1937899513
Short name T50
Test name
Test status
Simulation time 549763010 ps
CPU time 6.63 seconds
Started Mar 12 01:04:07 PM PDT 24
Finished Mar 12 01:04:14 PM PDT 24
Peak memory 203732 kb
Host smart-525efe3d-a8f5-4548-8d36-6fa751ac7b61
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1937899513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1937899513
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_large_delays.1439280133
Short name T651
Test name
Test status
Simulation time 48405422132 ps
CPU time 179.94 seconds
Started Mar 12 01:04:07 PM PDT 24
Finished Mar 12 01:07:08 PM PDT 24
Peak memory 204184 kb
Host smart-43546732-83ad-4dac-8fd1-c629abedc11f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439280133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1439280133
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_slow_rsp.821281502
Short name T340
Test name
Test status
Simulation time 35174261842 ps
CPU time 240.84 seconds
Started Mar 12 01:03:54 PM PDT 24
Finished Mar 12 01:07:55 PM PDT 24
Peak memory 204092 kb
Host smart-c283d50d-2fbb-4ac8-8d7a-4d85fea9c3ce
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=821281502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.821281502
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_random_zero_delays.303708924
Short name T785
Test name
Test status
Simulation time 82663777 ps
CPU time 9.23 seconds
Started Mar 12 01:04:05 PM PDT 24
Finished Mar 12 01:04:15 PM PDT 24
Peak memory 210984 kb
Host smart-067f277a-b0f3-40d3-a903-03722dadcbcd
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303708924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.303708924
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_same_source.2192176378
Short name T824
Test name
Test status
Simulation time 777432257 ps
CPU time 14.59 seconds
Started Mar 12 01:04:00 PM PDT 24
Finished Mar 12 01:04:15 PM PDT 24
Peak memory 202976 kb
Host smart-7806488e-02a0-45a7-91cc-a4ef264e30b8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2192176378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2192176378
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke.1428979060
Short name T864
Test name
Test status
Simulation time 41164929 ps
CPU time 2.42 seconds
Started Mar 12 01:04:01 PM PDT 24
Finished Mar 12 01:04:03 PM PDT 24
Peak memory 202816 kb
Host smart-9add6b08-3c46-44db-adcc-8bb128382537
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1428979060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1428979060
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3483628246
Short name T187
Test name
Test status
Simulation time 12884441448 ps
CPU time 31.54 seconds
Started Mar 12 01:04:03 PM PDT 24
Finished Mar 12 01:04:37 PM PDT 24
Peak memory 202840 kb
Host smart-3d25d6e3-aad4-4629-a10d-b9d5b6178426
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483628246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3483628246
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.2665846663
Short name T858
Test name
Test status
Simulation time 3245329800 ps
CPU time 29.93 seconds
Started Mar 12 01:04:01 PM PDT 24
Finished Mar 12 01:04:31 PM PDT 24
Peak memory 202944 kb
Host smart-14cf3248-87f1-4159-b8c9-64f1a250c22f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2665846663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2665846663
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.4032573216
Short name T683
Test name
Test status
Simulation time 94531778 ps
CPU time 2.47 seconds
Started Mar 12 01:04:04 PM PDT 24
Finished Mar 12 01:04:08 PM PDT 24
Peak memory 202932 kb
Host smart-41f6c959-dd8b-4dff-bcd3-88ace2c9554a
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032573216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.4032573216
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all.4051808899
Short name T579
Test name
Test status
Simulation time 2853864195 ps
CPU time 74.32 seconds
Started Mar 12 01:04:11 PM PDT 24
Finished Mar 12 01:05:25 PM PDT 24
Peak memory 206904 kb
Host smart-8aecdc84-1c26-4e4f-990c-8fe10570d303
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4051808899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4051808899
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3797642562
Short name T735
Test name
Test status
Simulation time 500552063 ps
CPU time 63.39 seconds
Started Mar 12 01:04:16 PM PDT 24
Finished Mar 12 01:05:20 PM PDT 24
Peak memory 205488 kb
Host smart-f122ff67-1df0-4e08-a995-9b1b0ff0207c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3797642562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3797642562
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2145892497
Short name T457
Test name
Test status
Simulation time 367451611 ps
CPU time 57.02 seconds
Started Mar 12 01:04:15 PM PDT 24
Finished Mar 12 01:05:12 PM PDT 24
Peak memory 206400 kb
Host smart-ee42080b-b4eb-4e75-9e8d-815aae1f2529
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2145892497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_ran
d_reset.2145892497
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2267951590
Short name T674
Test name
Test status
Simulation time 6194892617 ps
CPU time 265.08 seconds
Started Mar 12 01:04:14 PM PDT 24
Finished Mar 12 01:08:39 PM PDT 24
Peak memory 219372 kb
Host smart-2aaa1fac-e9c0-41eb-bfca-b16706d3bf21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2267951590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_re
set_error.2267951590
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/42.xbar_unmapped_addr.1268478925
Short name T647
Test name
Test status
Simulation time 22519074 ps
CPU time 2.8 seconds
Started Mar 12 01:04:04 PM PDT 24
Finished Mar 12 01:04:08 PM PDT 24
Peak memory 211080 kb
Host smart-9347075d-0e52-40fe-9293-522ac7151785
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1268478925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1268478925
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device.1274492792
Short name T694
Test name
Test status
Simulation time 162429388 ps
CPU time 8.67 seconds
Started Mar 12 01:04:11 PM PDT 24
Finished Mar 12 01:04:20 PM PDT 24
Peak memory 203696 kb
Host smart-53bec7cc-1b1f-4f6e-a7d6-85da58a09338
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1274492792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1274492792
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.550994169
Short name T811
Test name
Test status
Simulation time 76959490159 ps
CPU time 633.96 seconds
Started Mar 12 01:04:15 PM PDT 24
Finished Mar 12 01:14:49 PM PDT 24
Peak memory 211124 kb
Host smart-f11c12d6-88a7-45e6-a67c-10c7e6f748fa
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=550994169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slo
w_rsp.550994169
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.3040607579
Short name T572
Test name
Test status
Simulation time 135586742 ps
CPU time 15.77 seconds
Started Mar 12 01:04:13 PM PDT 24
Finished Mar 12 01:04:29 PM PDT 24
Peak memory 203352 kb
Host smart-73c47b42-d459-4155-b3b9-c2d3795a8c21
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3040607579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3040607579
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_error_random.1724909836
Short name T800
Test name
Test status
Simulation time 68610882 ps
CPU time 4.11 seconds
Started Mar 12 01:04:22 PM PDT 24
Finished Mar 12 01:04:26 PM PDT 24
Peak memory 202936 kb
Host smart-240582eb-b2c3-4710-967e-89921c815079
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1724909836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1724909836
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random.3506708082
Short name T406
Test name
Test status
Simulation time 52067568 ps
CPU time 7.76 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:04:19 PM PDT 24
Peak memory 211108 kb
Host smart-0d31de58-2a6f-499d-bbad-de33d5df4777
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3506708082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3506708082
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_large_delays.1294441483
Short name T597
Test name
Test status
Simulation time 5693077941 ps
CPU time 24.49 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 202960 kb
Host smart-cc9192a6-9622-46ad-92e0-a95ca69ea817
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294441483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1294441483
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3141180197
Short name T118
Test name
Test status
Simulation time 25555111663 ps
CPU time 92.65 seconds
Started Mar 12 01:04:16 PM PDT 24
Finished Mar 12 01:05:49 PM PDT 24
Peak memory 211148 kb
Host smart-40d1fc53-3b8f-41e8-9fee-b83b1c6b97fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3141180197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3141180197
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_random_zero_delays.636908190
Short name T872
Test name
Test status
Simulation time 305835234 ps
CPU time 28.94 seconds
Started Mar 12 01:04:11 PM PDT 24
Finished Mar 12 01:04:40 PM PDT 24
Peak memory 211112 kb
Host smart-3db987c6-3b75-46cd-aedd-b1290957eb6f
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636908190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.636908190
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_same_source.2282459343
Short name T235
Test name
Test status
Simulation time 4460515866 ps
CPU time 23.54 seconds
Started Mar 12 01:04:11 PM PDT 24
Finished Mar 12 01:04:35 PM PDT 24
Peak memory 204044 kb
Host smart-281b2ba4-1428-488f-aeb0-8fa607930945
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2282459343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2282459343
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke.490595178
Short name T578
Test name
Test status
Simulation time 191188997 ps
CPU time 3.04 seconds
Started Mar 12 01:04:15 PM PDT 24
Finished Mar 12 01:04:18 PM PDT 24
Peak memory 202900 kb
Host smart-af07dcd4-f07d-4052-8dce-f678441fc986
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=490595178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.490595178
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2635713156
Short name T724
Test name
Test status
Simulation time 5980541178 ps
CPU time 28.81 seconds
Started Mar 12 01:04:10 PM PDT 24
Finished Mar 12 01:04:39 PM PDT 24
Peak memory 202976 kb
Host smart-d1949a2a-26f8-4895-aa08-e03f3c764e8e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635713156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2635713156
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1270743825
Short name T40
Test name
Test status
Simulation time 2406281340 ps
CPU time 23.97 seconds
Started Mar 12 01:04:17 PM PDT 24
Finished Mar 12 01:04:41 PM PDT 24
Peak memory 202940 kb
Host smart-b8035ba9-0f36-4a8d-8900-57fd6ce4f4d8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1270743825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1270743825
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.303462922
Short name T459
Test name
Test status
Simulation time 32436855 ps
CPU time 2.6 seconds
Started Mar 12 01:04:17 PM PDT 24
Finished Mar 12 01:04:19 PM PDT 24
Peak memory 202956 kb
Host smart-e65110d2-b11c-4e4e-ac57-09da5a7c466d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303462922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.303462922
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all.2891105109
Short name T726
Test name
Test status
Simulation time 818977645 ps
CPU time 90.04 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:05:42 PM PDT 24
Peak memory 204516 kb
Host smart-853d9c6f-2896-49c9-8571-6066a9def92a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2891105109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2891105109
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2454816424
Short name T28
Test name
Test status
Simulation time 1418645579 ps
CPU time 120.88 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:06:13 PM PDT 24
Peak memory 206888 kb
Host smart-eb16b1ae-524a-473e-baa1-b193267576e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2454816424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2454816424
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.2175767298
Short name T171
Test name
Test status
Simulation time 8317097042 ps
CPU time 448.11 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:11:40 PM PDT 24
Peak memory 219416 kb
Host smart-740c867e-c15c-426f-8732-642a7af96065
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2175767298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_ran
d_reset.2175767298
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.1759628616
Short name T267
Test name
Test status
Simulation time 2187060630 ps
CPU time 255.97 seconds
Started Mar 12 01:04:10 PM PDT 24
Finished Mar 12 01:08:27 PM PDT 24
Peak memory 212360 kb
Host smart-6d81f1c4-469e-46d2-96e0-56cfa6deca94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1759628616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_re
set_error.1759628616
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/43.xbar_unmapped_addr.3884237163
Short name T368
Test name
Test status
Simulation time 23657996 ps
CPU time 2.76 seconds
Started Mar 12 01:04:13 PM PDT 24
Finished Mar 12 01:04:16 PM PDT 24
Peak memory 203908 kb
Host smart-ae1598bd-1d84-435a-bc4b-8fd82795b722
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3884237163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3884237163
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device.239711682
Short name T41
Test name
Test status
Simulation time 240172500 ps
CPU time 10.08 seconds
Started Mar 12 01:04:17 PM PDT 24
Finished Mar 12 01:04:27 PM PDT 24
Peak memory 203408 kb
Host smart-6bf0c18d-4b62-466e-a1d4-fbe130607d60
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=239711682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.239711682
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.3872553509
Short name T210
Test name
Test status
Simulation time 41936321269 ps
CPU time 323.16 seconds
Started Mar 12 01:04:18 PM PDT 24
Finished Mar 12 01:09:41 PM PDT 24
Peak memory 206160 kb
Host smart-42c85338-6439-4b2f-9258-8e5a037fe103
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3872553509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_sl
ow_rsp.3872553509
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2610097413
Short name T337
Test name
Test status
Simulation time 2968365087 ps
CPU time 25.92 seconds
Started Mar 12 01:04:15 PM PDT 24
Finished Mar 12 01:04:41 PM PDT 24
Peak memory 202968 kb
Host smart-8f36a8f7-6d27-40fb-87c7-ae1c5e8aac68
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2610097413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2610097413
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_error_random.3329050969
Short name T825
Test name
Test status
Simulation time 196551944 ps
CPU time 10.53 seconds
Started Mar 12 01:04:15 PM PDT 24
Finished Mar 12 01:04:25 PM PDT 24
Peak memory 202904 kb
Host smart-d90fbf67-fe11-4e1f-b924-6b57e5d859b7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3329050969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3329050969
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random.1213091241
Short name T403
Test name
Test status
Simulation time 282472649 ps
CPU time 21.55 seconds
Started Mar 12 01:04:14 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 203956 kb
Host smart-ea345317-af86-4249-bd43-0060250c9d2f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1213091241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.1213091241
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_large_delays.4113586531
Short name T667
Test name
Test status
Simulation time 41172372200 ps
CPU time 119.51 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:06:12 PM PDT 24
Peak memory 204332 kb
Host smart-6c49901c-9f42-4e5d-9c38-652374f6ba3b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113586531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.4113586531
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_slow_rsp.3086517337
Short name T799
Test name
Test status
Simulation time 7159165263 ps
CPU time 19.38 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:04:32 PM PDT 24
Peak memory 203016 kb
Host smart-e62c2612-fc1c-424e-b3b5-4d17c4c845fd
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3086517337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3086517337
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_random_zero_delays.1674337099
Short name T477
Test name
Test status
Simulation time 395434322 ps
CPU time 21.31 seconds
Started Mar 12 01:04:14 PM PDT 24
Finished Mar 12 01:04:35 PM PDT 24
Peak memory 204180 kb
Host smart-ac305e43-cbc8-47cc-bbcf-c118cd9960b6
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674337099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1674337099
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_same_source.881870309
Short name T20
Test name
Test status
Simulation time 3482792575 ps
CPU time 31.17 seconds
Started Mar 12 01:04:15 PM PDT 24
Finished Mar 12 01:04:46 PM PDT 24
Peak memory 203600 kb
Host smart-e2a2ae11-9a24-4e30-9c11-9e52cc15587b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=881870309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.881870309
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke.90633251
Short name T638
Test name
Test status
Simulation time 541576673 ps
CPU time 3.64 seconds
Started Mar 12 01:04:11 PM PDT 24
Finished Mar 12 01:04:14 PM PDT 24
Peak memory 202800 kb
Host smart-a14612ca-f9a5-423c-b3fb-1e83e3dcea77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=90633251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.90633251
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3994910547
Short name T817
Test name
Test status
Simulation time 13038743126 ps
CPU time 32.89 seconds
Started Mar 12 01:04:10 PM PDT 24
Finished Mar 12 01:04:43 PM PDT 24
Peak memory 202956 kb
Host smart-5a043ac9-975a-40a5-aa00-b2d0e849c266
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994910547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3994910547
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4219573959
Short name T876
Test name
Test status
Simulation time 2605717958 ps
CPU time 22.87 seconds
Started Mar 12 01:04:11 PM PDT 24
Finished Mar 12 01:04:34 PM PDT 24
Peak memory 202868 kb
Host smart-9a1359f5-460c-48ee-8c67-bb1ec9c3f219
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4219573959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4219573959
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1882312799
Short name T869
Test name
Test status
Simulation time 41888759 ps
CPU time 2.63 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:04:15 PM PDT 24
Peak memory 202908 kb
Host smart-88c3b910-a7d6-4bf4-a114-e75a980a0a3c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882312799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1882312799
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all.3990204885
Short name T558
Test name
Test status
Simulation time 16718148072 ps
CPU time 135.36 seconds
Started Mar 12 01:04:15 PM PDT 24
Finished Mar 12 01:06:31 PM PDT 24
Peak memory 205580 kb
Host smart-cb467715-9bd0-4ae2-bff6-683f27d19773
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3990204885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3990204885
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_error.3885582388
Short name T16
Test name
Test status
Simulation time 2510868066 ps
CPU time 44.92 seconds
Started Mar 12 01:04:11 PM PDT 24
Finished Mar 12 01:04:56 PM PDT 24
Peak memory 205440 kb
Host smart-665e2848-bca8-4c0f-9463-009e9e4ffc97
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3885582388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3885582388
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1087087677
Short name T432
Test name
Test status
Simulation time 733687052 ps
CPU time 168.66 seconds
Started Mar 12 01:04:14 PM PDT 24
Finished Mar 12 01:07:03 PM PDT 24
Peak memory 211076 kb
Host smart-b967335c-85c8-430b-a26f-f66c77ab6e88
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1087087677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_re
set_error.1087087677
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/44.xbar_unmapped_addr.3870126575
Short name T444
Test name
Test status
Simulation time 785129623 ps
CPU time 22.86 seconds
Started Mar 12 01:04:14 PM PDT 24
Finished Mar 12 01:04:37 PM PDT 24
Peak memory 204224 kb
Host smart-c81f3c8d-7eca-4610-88e4-97e8fb69615b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3870126575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3870126575
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device.1988408487
Short name T604
Test name
Test status
Simulation time 650276527 ps
CPU time 35.12 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:04:47 PM PDT 24
Peak memory 211116 kb
Host smart-9c7bbdaf-eb97-4c1a-a095-d3d28b65926f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1988408487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1988408487
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.4021560020
Short name T157
Test name
Test status
Simulation time 333978914165 ps
CPU time 626.72 seconds
Started Mar 12 01:04:14 PM PDT 24
Finished Mar 12 01:14:41 PM PDT 24
Peak memory 206476 kb
Host smart-9347985b-b18f-4aa1-a8fd-e8b4090c8b9b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4021560020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_sl
ow_rsp.4021560020
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.730709807
Short name T353
Test name
Test status
Simulation time 711275677 ps
CPU time 18.06 seconds
Started Mar 12 01:04:33 PM PDT 24
Finished Mar 12 01:04:54 PM PDT 24
Peak memory 202920 kb
Host smart-06538d77-9315-4b8a-878a-f79ad076132e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=730709807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.730709807
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_error_random.2414636559
Short name T584
Test name
Test status
Simulation time 980821258 ps
CPU time 19.59 seconds
Started Mar 12 01:04:18 PM PDT 24
Finished Mar 12 01:04:37 PM PDT 24
Peak memory 202980 kb
Host smart-8f1aa11b-ca3d-4a47-af47-db4bcdd660b5
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2414636559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2414636559
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random.2107794630
Short name T156
Test name
Test status
Simulation time 1070835585 ps
CPU time 9.61 seconds
Started Mar 12 01:04:16 PM PDT 24
Finished Mar 12 01:04:26 PM PDT 24
Peak memory 203996 kb
Host smart-758656d9-7980-473b-9af2-d7b4b32197ec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2107794630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.2107794630
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_large_delays.2228116459
Short name T86
Test name
Test status
Simulation time 6227595108 ps
CPU time 16.1 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:04:28 PM PDT 24
Peak memory 203040 kb
Host smart-dacec923-bba0-497d-a986-acaf08072f78
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228116459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2228116459
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_slow_rsp.1319202216
Short name T382
Test name
Test status
Simulation time 16073136599 ps
CPU time 78.26 seconds
Started Mar 12 01:04:18 PM PDT 24
Finished Mar 12 01:05:36 PM PDT 24
Peak memory 211228 kb
Host smart-e81e8522-e461-41d3-ba44-f2b029592fd8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1319202216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1319202216
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_random_zero_delays.19658410
Short name T656
Test name
Test status
Simulation time 177141054 ps
CPU time 17.3 seconds
Started Mar 12 01:04:14 PM PDT 24
Finished Mar 12 01:04:32 PM PDT 24
Peak memory 211084 kb
Host smart-b0592c3b-328e-40f0-8854-645b1177f8de
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19658410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.19658410
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_same_source.596511403
Short name T490
Test name
Test status
Simulation time 132953385 ps
CPU time 9.6 seconds
Started Mar 12 01:04:12 PM PDT 24
Finished Mar 12 01:04:22 PM PDT 24
Peak memory 202956 kb
Host smart-05886f0d-e886-4634-a098-cad4765a68c0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=596511403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.596511403
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke.379580215
Short name T110
Test name
Test status
Simulation time 373958598 ps
CPU time 3.25 seconds
Started Mar 12 01:04:10 PM PDT 24
Finished Mar 12 01:04:13 PM PDT 24
Peak memory 202940 kb
Host smart-557d5f86-aa8d-4325-9b7d-bbbd972497fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=379580215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.379580215
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_large_delays.515554901
Short name T768
Test name
Test status
Simulation time 6970787509 ps
CPU time 24.33 seconds
Started Mar 12 01:04:15 PM PDT 24
Finished Mar 12 01:04:40 PM PDT 24
Peak memory 202988 kb
Host smart-52eb4c70-a078-481e-ac3a-369c4a90e750
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=515554901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.515554901
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1178393335
Short name T747
Test name
Test status
Simulation time 3063723770 ps
CPU time 28.89 seconds
Started Mar 12 01:04:15 PM PDT 24
Finished Mar 12 01:04:44 PM PDT 24
Peak memory 202792 kb
Host smart-4a14d3a5-1522-4477-bcfb-57edca476015
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1178393335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1178393335
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.2702275464
Short name T412
Test name
Test status
Simulation time 44140106 ps
CPU time 2.24 seconds
Started Mar 12 01:04:16 PM PDT 24
Finished Mar 12 01:04:18 PM PDT 24
Peak memory 202888 kb
Host smart-e7ec8278-fc92-450c-911a-055c0d8a4e52
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702275464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.2702275464
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all.1806223831
Short name T146
Test name
Test status
Simulation time 509925504 ps
CPU time 57.05 seconds
Started Mar 12 01:04:32 PM PDT 24
Finished Mar 12 01:05:33 PM PDT 24
Peak memory 205896 kb
Host smart-eec95269-9b13-4c0a-8133-e5afd0cdd0fa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1806223831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1806223831
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1845051194
Short name T658
Test name
Test status
Simulation time 20761377189 ps
CPU time 304.56 seconds
Started Mar 12 01:04:23 PM PDT 24
Finished Mar 12 01:09:28 PM PDT 24
Peak memory 206840 kb
Host smart-3fae292e-f20b-4c7a-bb08-64a1a44fc450
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1845051194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1845051194
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1353675267
Short name T828
Test name
Test status
Simulation time 7574198965 ps
CPU time 362.74 seconds
Started Mar 12 01:04:25 PM PDT 24
Finished Mar 12 01:10:27 PM PDT 24
Peak memory 210872 kb
Host smart-5d119de6-2397-48c4-a5dc-c48961e01eaa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1353675267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_ran
d_reset.1353675267
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.3471435258
Short name T836
Test name
Test status
Simulation time 305002524 ps
CPU time 122.56 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:06:26 PM PDT 24
Peak memory 208980 kb
Host smart-24c66906-d03f-4f3b-b226-d19e0ff97a6d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3471435258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_re
set_error.3471435258
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/45.xbar_unmapped_addr.1373484075
Short name T684
Test name
Test status
Simulation time 1391956602 ps
CPU time 25.28 seconds
Started Mar 12 01:04:16 PM PDT 24
Finished Mar 12 01:04:42 PM PDT 24
Peak memory 204484 kb
Host smart-fbb35254-f0f8-44b5-9997-32bbe185a419
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1373484075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1373484075
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device.3753427496
Short name T309
Test name
Test status
Simulation time 222659428 ps
CPU time 18.73 seconds
Started Mar 12 01:04:30 PM PDT 24
Finished Mar 12 01:04:48 PM PDT 24
Peak memory 204104 kb
Host smart-88a7fd5d-5f78-438f-a8ce-37cbb8394488
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3753427496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3753427496
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4281553089
Short name T162
Test name
Test status
Simulation time 71414879740 ps
CPU time 662.42 seconds
Started Mar 12 01:04:23 PM PDT 24
Finished Mar 12 01:15:25 PM PDT 24
Peak memory 211220 kb
Host smart-c0f994e5-48d6-49f5-92f5-b92430e734a2
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4281553089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_sl
ow_rsp.4281553089
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.765005428
Short name T472
Test name
Test status
Simulation time 820428107 ps
CPU time 17.85 seconds
Started Mar 12 01:04:27 PM PDT 24
Finished Mar 12 01:04:45 PM PDT 24
Peak memory 202776 kb
Host smart-8bb1c6d8-8f07-41ef-a60f-4439cd9fb3af
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=765005428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.765005428
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_error_random.630243891
Short name T693
Test name
Test status
Simulation time 1168388414 ps
CPU time 14.76 seconds
Started Mar 12 01:04:26 PM PDT 24
Finished Mar 12 01:04:41 PM PDT 24
Peak memory 202880 kb
Host smart-4bb1748e-7ff3-46b6-b5e9-789be6dc2362
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=630243891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.630243891
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random.1429720144
Short name T893
Test name
Test status
Simulation time 835564910 ps
CPU time 21.08 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:04:45 PM PDT 24
Peak memory 203956 kb
Host smart-e9bd475a-9b49-4cb2-999c-b8f8123b036e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1429720144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1429720144
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_large_delays.2029959968
Short name T203
Test name
Test status
Simulation time 12455969026 ps
CPU time 55.61 seconds
Started Mar 12 01:04:28 PM PDT 24
Finished Mar 12 01:05:23 PM PDT 24
Peak memory 204116 kb
Host smart-406e1dd4-f23a-4ab3-bb6c-a0ea1270fe51
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029959968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2029959968
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3281897600
Short name T591
Test name
Test status
Simulation time 16737632781 ps
CPU time 133.84 seconds
Started Mar 12 01:04:21 PM PDT 24
Finished Mar 12 01:06:35 PM PDT 24
Peak memory 211224 kb
Host smart-e34edc15-6e4c-4878-9721-501431c387fe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3281897600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3281897600
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_random_zero_delays.3700507882
Short name T17
Test name
Test status
Simulation time 97799513 ps
CPU time 6.32 seconds
Started Mar 12 01:04:27 PM PDT 24
Finished Mar 12 01:04:33 PM PDT 24
Peak memory 211076 kb
Host smart-a46395f6-7338-4027-a4fd-e23db7a0f8cc
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700507882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3700507882
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_same_source.1143850094
Short name T253
Test name
Test status
Simulation time 2053412524 ps
CPU time 29.21 seconds
Started Mar 12 01:04:22 PM PDT 24
Finished Mar 12 01:04:51 PM PDT 24
Peak memory 202944 kb
Host smart-35a0c3fd-d6db-4eaf-a290-a7edcb4a4111
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1143850094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1143850094
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke.1114700324
Short name T443
Test name
Test status
Simulation time 537942014 ps
CPU time 3.88 seconds
Started Mar 12 01:04:28 PM PDT 24
Finished Mar 12 01:04:32 PM PDT 24
Peak memory 202912 kb
Host smart-01719878-7821-47eb-afee-33adc3e09361
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1114700324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1114700324
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_large_delays.3948816500
Short name T809
Test name
Test status
Simulation time 10939019727 ps
CPU time 40.34 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:05:04 PM PDT 24
Peak memory 202968 kb
Host smart-eaec173f-cba8-4d73-9b0b-36d451a59dfe
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948816500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3948816500
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.390831337
Short name T894
Test name
Test status
Simulation time 9206629520 ps
CPU time 33.39 seconds
Started Mar 12 01:04:22 PM PDT 24
Finished Mar 12 01:04:56 PM PDT 24
Peak memory 202948 kb
Host smart-0ae26287-2db3-4daf-9ad2-5d775d3e3456
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=390831337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.390831337
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2288457473
Short name T277
Test name
Test status
Simulation time 52674563 ps
CPU time 2.5 seconds
Started Mar 12 01:04:25 PM PDT 24
Finished Mar 12 01:04:28 PM PDT 24
Peak memory 202928 kb
Host smart-4b4ad06e-563c-44c2-bd1e-50a39372a193
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288457473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2288457473
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all.1855446175
Short name T504
Test name
Test status
Simulation time 1804462838 ps
CPU time 37.39 seconds
Started Mar 12 01:04:29 PM PDT 24
Finished Mar 12 01:05:06 PM PDT 24
Peak memory 206240 kb
Host smart-84576285-0036-4a91-8d69-5e4e184d6e20
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1855446175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1855446175
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1573528565
Short name T98
Test name
Test status
Simulation time 6805965372 ps
CPU time 157.78 seconds
Started Mar 12 01:04:28 PM PDT 24
Finished Mar 12 01:07:06 PM PDT 24
Peak memory 205988 kb
Host smart-4df060a9-8b44-4c53-bbde-b9a4d860b344
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1573528565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1573528565
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.215472896
Short name T531
Test name
Test status
Simulation time 3163680796 ps
CPU time 581.37 seconds
Started Mar 12 01:04:21 PM PDT 24
Finished Mar 12 01:14:02 PM PDT 24
Peak memory 223028 kb
Host smart-b3fcab10-e670-4734-a76e-c44e4425e3b2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=215472896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand
_reset.215472896
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3007368428
Short name T260
Test name
Test status
Simulation time 8630849371 ps
CPU time 230.82 seconds
Started Mar 12 01:04:21 PM PDT 24
Finished Mar 12 01:08:12 PM PDT 24
Peak memory 209516 kb
Host smart-3a73a76f-68d6-4517-bb20-6d44396b311e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3007368428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_re
set_error.3007368428
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/46.xbar_unmapped_addr.1538776263
Short name T99
Test name
Test status
Simulation time 403478058 ps
CPU time 14.26 seconds
Started Mar 12 01:04:22 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 204428 kb
Host smart-719445f8-2c23-4dea-b2c9-bca1772971a1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1538776263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1538776263
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3586607264
Short name T525
Test name
Test status
Simulation time 83373213 ps
CPU time 8.12 seconds
Started Mar 12 01:04:27 PM PDT 24
Finished Mar 12 01:04:35 PM PDT 24
Peak memory 202852 kb
Host smart-e37db4ed-397c-483a-9042-20f8771345ae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3586607264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3586607264
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_error_random.66180849
Short name T351
Test name
Test status
Simulation time 920202357 ps
CPU time 27.38 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:04:51 PM PDT 24
Peak memory 202904 kb
Host smart-882ad606-bf8f-434f-983b-c7c953a93ef1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66180849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.66180849
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random.2719237335
Short name T390
Test name
Test status
Simulation time 42263831 ps
CPU time 5.29 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:04:29 PM PDT 24
Peak memory 204024 kb
Host smart-c1b333b8-618e-4603-b76e-c86259f867b4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2719237335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.2719237335
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_large_delays.1767314612
Short name T733
Test name
Test status
Simulation time 44853445544 ps
CPU time 203.53 seconds
Started Mar 12 01:04:27 PM PDT 24
Finished Mar 12 01:07:51 PM PDT 24
Peak memory 211176 kb
Host smart-f7a592d6-b4d9-4947-9d9b-5f23673b4164
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767314612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1767314612
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_slow_rsp.450043039
Short name T199
Test name
Test status
Simulation time 31153968926 ps
CPU time 240.94 seconds
Started Mar 12 01:04:25 PM PDT 24
Finished Mar 12 01:08:26 PM PDT 24
Peak memory 211032 kb
Host smart-64debf31-e126-4d43-8ef6-1d0db508def0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=450043039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.450043039
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_random_zero_delays.738484148
Short name T545
Test name
Test status
Simulation time 408398963 ps
CPU time 13.53 seconds
Started Mar 12 01:04:23 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 204012 kb
Host smart-e7a3a181-fc98-418f-975f-6dd2e351c67c
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738484148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.738484148
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_same_source.3339841194
Short name T720
Test name
Test status
Simulation time 263805113 ps
CPU time 11.79 seconds
Started Mar 12 01:04:25 PM PDT 24
Finished Mar 12 01:04:37 PM PDT 24
Peak memory 202780 kb
Host smart-9514710c-ccee-43bb-bf1f-70c7cf157ebf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3339841194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3339841194
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke.1912612404
Short name T482
Test name
Test status
Simulation time 198873821 ps
CPU time 3.73 seconds
Started Mar 12 01:04:31 PM PDT 24
Finished Mar 12 01:04:35 PM PDT 24
Peak memory 202912 kb
Host smart-e28ab0ec-11aa-4269-9526-a95b6299297f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1912612404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1912612404
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_large_delays.156070803
Short name T47
Test name
Test status
Simulation time 3422708474 ps
CPU time 21.75 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:04:46 PM PDT 24
Peak memory 202956 kb
Host smart-798e6d21-076f-4663-a249-6fd26a20cad3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=156070803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.156070803
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.191085693
Short name T378
Test name
Test status
Simulation time 2432653038 ps
CPU time 22.93 seconds
Started Mar 12 01:04:21 PM PDT 24
Finished Mar 12 01:04:44 PM PDT 24
Peak memory 203004 kb
Host smart-adb597f1-28b4-4f61-9ecf-9e58486fec7f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=191085693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.191085693
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.159903860
Short name T229
Test name
Test status
Simulation time 23502360 ps
CPU time 2.03 seconds
Started Mar 12 01:04:23 PM PDT 24
Finished Mar 12 01:04:25 PM PDT 24
Peak memory 202836 kb
Host smart-01502362-9bbd-4719-8758-f1f2382c0822
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159903860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.159903860
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all.3608694262
Short name T194
Test name
Test status
Simulation time 3257677990 ps
CPU time 95.34 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:05:59 PM PDT 24
Peak memory 211156 kb
Host smart-35e836cc-e0c2-4cce-8b77-e71117108e2e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3608694262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3608694262
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1443599238
Short name T294
Test name
Test status
Simulation time 6020560845 ps
CPU time 108.79 seconds
Started Mar 12 01:04:26 PM PDT 24
Finished Mar 12 01:06:15 PM PDT 24
Peak memory 207360 kb
Host smart-a6e2d378-0432-447f-a983-12454cd88c55
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1443599238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1443599238
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.1569656687
Short name T369
Test name
Test status
Simulation time 2533885097 ps
CPU time 265.86 seconds
Started Mar 12 01:04:23 PM PDT 24
Finished Mar 12 01:08:49 PM PDT 24
Peak memory 210276 kb
Host smart-8e857efd-feed-491b-9443-773acda4b86e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1569656687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_ran
d_reset.1569656687
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3316139382
Short name T630
Test name
Test status
Simulation time 207943927 ps
CPU time 60.2 seconds
Started Mar 12 01:04:21 PM PDT 24
Finished Mar 12 01:05:21 PM PDT 24
Peak memory 207612 kb
Host smart-6d8091f4-7b50-4eaa-8139-0c8b4e9b401a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3316139382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_re
set_error.3316139382
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/47.xbar_unmapped_addr.183014318
Short name T738
Test name
Test status
Simulation time 3508525909 ps
CPU time 31.55 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:04:55 PM PDT 24
Peak memory 204400 kb
Host smart-db78bda4-2f5d-475e-a3aa-a55476542908
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=183014318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.183014318
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device.1498907221
Short name T81
Test name
Test status
Simulation time 501558276 ps
CPU time 20.89 seconds
Started Mar 12 01:04:28 PM PDT 24
Finished Mar 12 01:04:49 PM PDT 24
Peak memory 204028 kb
Host smart-172f6907-827d-4903-94bd-48dc6ce23e96
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1498907221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1498907221
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3002214640
Short name T453
Test name
Test status
Simulation time 16293747920 ps
CPU time 94.11 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:05:58 PM PDT 24
Peak memory 204152 kb
Host smart-3f21e4f7-35c8-4c62-9449-2355d67f0fab
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3002214640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_sl
ow_rsp.3002214640
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2029908139
Short name T878
Test name
Test status
Simulation time 30755990 ps
CPU time 3.94 seconds
Started Mar 12 01:04:32 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 202916 kb
Host smart-4a983b97-122b-43aa-b023-1e1b59425288
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2029908139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2029908139
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_error_random.3876730878
Short name T829
Test name
Test status
Simulation time 178559415 ps
CPU time 18.25 seconds
Started Mar 12 01:04:35 PM PDT 24
Finished Mar 12 01:04:54 PM PDT 24
Peak memory 202912 kb
Host smart-35a1c83e-6305-449a-aefd-0612a473434f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3876730878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3876730878
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random.2704162438
Short name T341
Test name
Test status
Simulation time 45342865 ps
CPU time 4.68 seconds
Started Mar 12 01:04:31 PM PDT 24
Finished Mar 12 01:04:35 PM PDT 24
Peak memory 203676 kb
Host smart-497d6360-bd6e-46fb-ba20-eac1f6fe935c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2704162438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2704162438
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_large_delays.3317616839
Short name T391
Test name
Test status
Simulation time 31355142115 ps
CPU time 194.41 seconds
Started Mar 12 01:04:23 PM PDT 24
Finished Mar 12 01:07:37 PM PDT 24
Peak memory 211204 kb
Host smart-faa4449e-936c-4d98-97b4-e28bc5a18a12
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317616839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3317616839
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_slow_rsp.2386153056
Short name T304
Test name
Test status
Simulation time 2040553626 ps
CPU time 13.58 seconds
Started Mar 12 01:04:30 PM PDT 24
Finished Mar 12 01:04:43 PM PDT 24
Peak memory 202924 kb
Host smart-ec3558e6-b154-4003-9c2a-63411a8afbc8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2386153056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2386153056
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_random_zero_delays.410986212
Short name T213
Test name
Test status
Simulation time 222331686 ps
CPU time 20.25 seconds
Started Mar 12 01:04:23 PM PDT 24
Finished Mar 12 01:04:43 PM PDT 24
Peak memory 203980 kb
Host smart-58f8ee55-8399-4135-a7fb-6fa123a6d1f4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410986212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.410986212
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_same_source.3009202175
Short name T882
Test name
Test status
Simulation time 687873759 ps
CPU time 10.74 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:04:35 PM PDT 24
Peak memory 202916 kb
Host smart-4ca8e0db-5218-4f54-9c76-346c5ffd798e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3009202175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3009202175
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke.823638484
Short name T592
Test name
Test status
Simulation time 129404585 ps
CPU time 2.12 seconds
Started Mar 12 01:04:25 PM PDT 24
Finished Mar 12 01:04:27 PM PDT 24
Peak memory 202920 kb
Host smart-4293ab68-1ae4-495c-bb0e-778cd32ee9c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=823638484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.823638484
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1902437436
Short name T696
Test name
Test status
Simulation time 5057712376 ps
CPU time 29.66 seconds
Started Mar 12 01:04:31 PM PDT 24
Finished Mar 12 01:05:01 PM PDT 24
Peak memory 202964 kb
Host smart-d861909c-18da-4fec-bafd-7795c988b9e7
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902437436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1902437436
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2557982959
Short name T756
Test name
Test status
Simulation time 2115639557 ps
CPU time 21.4 seconds
Started Mar 12 01:04:22 PM PDT 24
Finished Mar 12 01:04:44 PM PDT 24
Peak memory 202920 kb
Host smart-444f46a8-e1b9-459e-a659-2e068dd38f9e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2557982959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2557982959
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3629050290
Short name T478
Test name
Test status
Simulation time 75453555 ps
CPU time 2.14 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:04:26 PM PDT 24
Peak memory 202944 kb
Host smart-ff133d67-f13b-4c49-bd34-f931f14fba1d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629050290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3629050290
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all.4147841857
Short name T710
Test name
Test status
Simulation time 400291952 ps
CPU time 44.23 seconds
Started Mar 12 01:04:24 PM PDT 24
Finished Mar 12 01:05:09 PM PDT 24
Peak memory 210968 kb
Host smart-84eb2d77-cf53-4c7b-95be-9d34de1c049d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4147841857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.4147841857
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_error.4000299044
Short name T36
Test name
Test status
Simulation time 4188822090 ps
CPU time 118.47 seconds
Started Mar 12 01:04:31 PM PDT 24
Finished Mar 12 01:06:29 PM PDT 24
Peak memory 205420 kb
Host smart-fb7fe426-a649-4beb-abd8-bacb918442f2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4000299044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.4000299044
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.4257893681
Short name T39
Test name
Test status
Simulation time 2230377136 ps
CPU time 413.9 seconds
Started Mar 12 01:04:29 PM PDT 24
Finished Mar 12 01:11:24 PM PDT 24
Peak memory 208724 kb
Host smart-ac331480-9232-436b-a7e8-c7a61a69725e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4257893681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_ran
d_reset.4257893681
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3256623305
Short name T715
Test name
Test status
Simulation time 9006531530 ps
CPU time 233.35 seconds
Started Mar 12 01:04:26 PM PDT 24
Finished Mar 12 01:08:19 PM PDT 24
Peak memory 211176 kb
Host smart-3960c4f0-7ba1-4284-80cf-f90ce9bed6a9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3256623305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_re
set_error.3256623305
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/48.xbar_unmapped_addr.163073324
Short name T889
Test name
Test status
Simulation time 1146442665 ps
CPU time 30.29 seconds
Started Mar 12 01:04:23 PM PDT 24
Finished Mar 12 01:04:54 PM PDT 24
Peak memory 211052 kb
Host smart-89f25c0b-5bc0-44c7-a605-23ab3eec3c64
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=163073324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.163073324
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device.2697538007
Short name T106
Test name
Test status
Simulation time 2501569194 ps
CPU time 67.04 seconds
Started Mar 12 01:04:44 PM PDT 24
Finished Mar 12 01:05:53 PM PDT 24
Peak memory 205808 kb
Host smart-94345ac0-2f39-4f8f-9542-e769f9ef6fff
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2697538007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2697538007
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3145917510
Short name T179
Test name
Test status
Simulation time 63743456381 ps
CPU time 366.07 seconds
Started Mar 12 01:04:42 PM PDT 24
Finished Mar 12 01:10:48 PM PDT 24
Peak memory 205724 kb
Host smart-eb8358d6-e852-48cb-a0fe-c63c3d1aa952
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3145917510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_sl
ow_rsp.3145917510
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.419827705
Short name T413
Test name
Test status
Simulation time 32410513 ps
CPU time 3.92 seconds
Started Mar 12 01:04:40 PM PDT 24
Finished Mar 12 01:04:44 PM PDT 24
Peak memory 202876 kb
Host smart-ff756c8f-9b35-40f1-ab6d-58829d9c098e
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=419827705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.419827705
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_error_random.3454792377
Short name T88
Test name
Test status
Simulation time 293533623 ps
CPU time 8.08 seconds
Started Mar 12 01:04:42 PM PDT 24
Finished Mar 12 01:04:50 PM PDT 24
Peak memory 202948 kb
Host smart-644f9b7f-5968-4b02-88c2-d411ffda4b74
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3454792377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3454792377
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random.1804589844
Short name T732
Test name
Test status
Simulation time 572049863 ps
CPU time 14.27 seconds
Started Mar 12 01:04:40 PM PDT 24
Finished Mar 12 01:04:54 PM PDT 24
Peak memory 204040 kb
Host smart-f5dd48f2-904b-4157-8de7-f6473ab555ac
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1804589844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1804589844
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_large_delays.2214060962
Short name T121
Test name
Test status
Simulation time 51788534689 ps
CPU time 255.24 seconds
Started Mar 12 01:04:40 PM PDT 24
Finished Mar 12 01:08:55 PM PDT 24
Peak memory 204516 kb
Host smart-9582e48e-9dae-4aba-adf7-6e729ffb9012
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214060962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2214060962
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3472286759
Short name T797
Test name
Test status
Simulation time 42924250833 ps
CPU time 119.07 seconds
Started Mar 12 01:04:43 PM PDT 24
Finished Mar 12 01:06:42 PM PDT 24
Peak memory 211168 kb
Host smart-f6ab1a52-eb2e-479f-a5b8-2e565d48b068
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3472286759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3472286759
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_random_zero_delays.1722062098
Short name T49
Test name
Test status
Simulation time 240082785 ps
CPU time 22.57 seconds
Started Mar 12 01:04:41 PM PDT 24
Finished Mar 12 01:05:04 PM PDT 24
Peak memory 204200 kb
Host smart-b83cd1bc-f154-49b9-8b4a-5310a5ae9e81
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722062098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.1722062098
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_same_source.3140803677
Short name T877
Test name
Test status
Simulation time 222532283 ps
CPU time 13.69 seconds
Started Mar 12 01:04:45 PM PDT 24
Finished Mar 12 01:05:00 PM PDT 24
Peak memory 202892 kb
Host smart-0a737835-8973-41b4-96f9-fd0fd453f96d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3140803677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3140803677
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke.3228323717
Short name T273
Test name
Test status
Simulation time 42742675 ps
CPU time 2.44 seconds
Started Mar 12 01:04:30 PM PDT 24
Finished Mar 12 01:04:32 PM PDT 24
Peak memory 202940 kb
Host smart-76c16aba-2e1f-4478-a8db-0bd8c204b82d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3228323717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3228323717
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_large_delays.3200786061
Short name T246
Test name
Test status
Simulation time 30164522628 ps
CPU time 42.41 seconds
Started Mar 12 01:04:43 PM PDT 24
Finished Mar 12 01:05:25 PM PDT 24
Peak memory 202996 kb
Host smart-2fc8cc87-84d4-4315-9299-913771ea7449
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200786061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3200786061
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3016737929
Short name T172
Test name
Test status
Simulation time 5807956286 ps
CPU time 27.97 seconds
Started Mar 12 01:04:42 PM PDT 24
Finished Mar 12 01:05:10 PM PDT 24
Peak memory 202972 kb
Host smart-c976ddc5-178e-4b7d-8e34-8b39bfa3458b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3016737929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3016737929
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.4289150851
Short name T520
Test name
Test status
Simulation time 86226364 ps
CPU time 2.64 seconds
Started Mar 12 01:04:28 PM PDT 24
Finished Mar 12 01:04:31 PM PDT 24
Peak memory 202884 kb
Host smart-71aabb3b-21ac-4b67-a1e7-0eb260d04fc2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289150851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.4289150851
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all.1630871824
Short name T568
Test name
Test status
Simulation time 9154454720 ps
CPU time 318.79 seconds
Started Mar 12 01:04:41 PM PDT 24
Finished Mar 12 01:10:01 PM PDT 24
Peak memory 211100 kb
Host smart-1e947f21-2b2e-4d99-a33e-7b4dd303d81f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1630871824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1630871824
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_error.199707617
Short name T892
Test name
Test status
Simulation time 21555081872 ps
CPU time 118.93 seconds
Started Mar 12 01:04:41 PM PDT 24
Finished Mar 12 01:06:41 PM PDT 24
Peak memory 204612 kb
Host smart-c1c57bee-a487-444b-9312-6327cb6b2be4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=199707617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.199707617
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3655966809
Short name T601
Test name
Test status
Simulation time 4277518878 ps
CPU time 222.33 seconds
Started Mar 12 01:04:41 PM PDT 24
Finished Mar 12 01:08:23 PM PDT 24
Peak memory 208068 kb
Host smart-03108c38-d654-4e52-a777-7cf302397f8f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3655966809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_ran
d_reset.3655966809
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2227022869
Short name T396
Test name
Test status
Simulation time 3073562473 ps
CPU time 161.77 seconds
Started Mar 12 01:04:45 PM PDT 24
Finished Mar 12 01:07:28 PM PDT 24
Peak memory 209860 kb
Host smart-86e833f2-67a9-41ba-921e-0fdbf21ff5c9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2227022869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_re
set_error.2227022869
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/49.xbar_unmapped_addr.1240100820
Short name T134
Test name
Test status
Simulation time 80933493 ps
CPU time 10.67 seconds
Started Mar 12 01:04:41 PM PDT 24
Finished Mar 12 01:04:52 PM PDT 24
Peak memory 204316 kb
Host smart-eb13e5fb-a238-400e-998e-c3ccb9cc2f41
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1240100820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1240100820
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device.3594820872
Short name T669
Test name
Test status
Simulation time 1511905072 ps
CPU time 61.7 seconds
Started Mar 12 01:02:27 PM PDT 24
Finished Mar 12 01:03:28 PM PDT 24
Peak memory 203716 kb
Host smart-4bf2f092-e111-40f8-bfbb-fa08f0e5adec
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3594820872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3594820872
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.3382795846
Short name T261
Test name
Test status
Simulation time 64237294375 ps
CPU time 539.84 seconds
Started Mar 12 01:02:27 PM PDT 24
Finished Mar 12 01:11:27 PM PDT 24
Peak memory 211172 kb
Host smart-cfc3350a-2459-4394-88bf-979d22484635
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3382795846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slo
w_rsp.3382795846
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1942838249
Short name T414
Test name
Test status
Simulation time 109718147 ps
CPU time 3.89 seconds
Started Mar 12 01:02:33 PM PDT 24
Finished Mar 12 01:02:37 PM PDT 24
Peak memory 202996 kb
Host smart-1bcd166a-40ec-4c5c-b027-2f64e6d7c404
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1942838249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1942838249
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_error_random.619815914
Short name T488
Test name
Test status
Simulation time 238786396 ps
CPU time 3.16 seconds
Started Mar 12 01:02:26 PM PDT 24
Finished Mar 12 01:02:30 PM PDT 24
Peak memory 202944 kb
Host smart-4691d3ef-668d-476d-85ad-79e9d47813a0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=619815914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.619815914
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random.4151623435
Short name T89
Test name
Test status
Simulation time 558759334 ps
CPU time 20.77 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:02:52 PM PDT 24
Peak memory 204008 kb
Host smart-0766be34-1abc-4d91-9a78-fea856d5b75f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4151623435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.4151623435
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_large_delays.1145048116
Short name T61
Test name
Test status
Simulation time 91602059609 ps
CPU time 228.16 seconds
Started Mar 12 01:02:34 PM PDT 24
Finished Mar 12 01:06:22 PM PDT 24
Peak memory 211164 kb
Host smart-3a7595d3-ea7b-49a7-b7f6-e7bcfd2c2835
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145048116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1145048116
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_slow_rsp.763300100
Short name T642
Test name
Test status
Simulation time 74961786889 ps
CPU time 202.36 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:05:54 PM PDT 24
Peak memory 203980 kb
Host smart-07f89b1e-38bf-4c78-830f-1b55e4f64ef0
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=763300100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.763300100
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_random_zero_delays.1455725550
Short name T483
Test name
Test status
Simulation time 388830893 ps
CPU time 10.49 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:33 PM PDT 24
Peak memory 204064 kb
Host smart-55ee47fb-d27f-4a03-8037-786908f25867
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455725550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1455725550
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_same_source.1835801857
Short name T697
Test name
Test status
Simulation time 606874113 ps
CPU time 11.65 seconds
Started Mar 12 01:02:24 PM PDT 24
Finished Mar 12 01:02:36 PM PDT 24
Peak memory 203296 kb
Host smart-4711b263-f4b1-44cb-ba94-b51076a9d188
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1835801857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1835801857
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke.36089930
Short name T91
Test name
Test status
Simulation time 144322122 ps
CPU time 3.47 seconds
Started Mar 12 01:02:08 PM PDT 24
Finished Mar 12 01:02:11 PM PDT 24
Peak memory 202840 kb
Host smart-e9a79892-bd71-4912-865e-d93b39f20249
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=36089930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.36089930
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4183272217
Short name T247
Test name
Test status
Simulation time 8619884593 ps
CPU time 27.54 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:02:58 PM PDT 24
Peak memory 202880 kb
Host smart-e7f0e6a1-2d9e-4e6a-a831-ca031ce3ac99
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183272217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4183272217
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.4190309892
Short name T776
Test name
Test status
Simulation time 10903892538 ps
CPU time 32.31 seconds
Started Mar 12 01:02:28 PM PDT 24
Finished Mar 12 01:03:00 PM PDT 24
Peak memory 202960 kb
Host smart-c601c817-5992-44c5-9088-bcc69f3e070e
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4190309892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.4190309892
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.1587325621
Short name T467
Test name
Test status
Simulation time 100346371 ps
CPU time 2.33 seconds
Started Mar 12 01:02:15 PM PDT 24
Finished Mar 12 01:02:17 PM PDT 24
Peak memory 202892 kb
Host smart-400edb60-3732-4d16-a6b2-307eb41e860d
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587325621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1587325621
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all.2514336394
Short name T632
Test name
Test status
Simulation time 217221495 ps
CPU time 16.78 seconds
Started Mar 12 01:02:14 PM PDT 24
Finished Mar 12 01:02:31 PM PDT 24
Peak memory 205048 kb
Host smart-7554ad6d-311c-4358-a729-8d1abb83fd2a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2514336394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2514336394
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2762359755
Short name T145
Test name
Test status
Simulation time 446936834 ps
CPU time 30.97 seconds
Started Mar 12 01:02:32 PM PDT 24
Finished Mar 12 01:03:03 PM PDT 24
Peak memory 204116 kb
Host smart-fff1a48e-a9ae-403f-9300-c2a00a73b1d9
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2762359755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2762359755
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.427774546
Short name T731
Test name
Test status
Simulation time 2469384876 ps
CPU time 448.9 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:10:00 PM PDT 24
Peak memory 211184 kb
Host smart-872bb5da-91ce-44d7-860c-d3d58b940662
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=427774546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_
reset.427774546
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.627323406
Short name T840
Test name
Test status
Simulation time 10226743436 ps
CPU time 232.47 seconds
Started Mar 12 01:02:33 PM PDT 24
Finished Mar 12 01:06:26 PM PDT 24
Peak memory 211176 kb
Host smart-7aab4274-7af9-4c37-8243-01e5c566962d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=627323406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rese
t_error.627323406
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/5.xbar_unmapped_addr.2268720808
Short name T352
Test name
Test status
Simulation time 155741042 ps
CPU time 15.54 seconds
Started Mar 12 01:02:30 PM PDT 24
Finished Mar 12 01:02:45 PM PDT 24
Peak memory 204336 kb
Host smart-ed340de1-7895-477c-a8d6-854ae83fb856
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2268720808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2268720808
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device.1675622728
Short name T139
Test name
Test status
Simulation time 2031442364 ps
CPU time 54.19 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:03:40 PM PDT 24
Peak memory 211088 kb
Host smart-95893a3c-5562-45bc-b498-e6c66fbc24b1
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1675622728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1675622728
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.3878172394
Short name T603
Test name
Test status
Simulation time 23851757715 ps
CPU time 117.03 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:04:40 PM PDT 24
Peak memory 211156 kb
Host smart-dd01faa4-9823-4ed4-bcaa-747d318c2022
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3878172394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slo
w_rsp.3878172394
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1074256046
Short name T765
Test name
Test status
Simulation time 136076047 ps
CPU time 5.49 seconds
Started Mar 12 01:02:38 PM PDT 24
Finished Mar 12 01:02:44 PM PDT 24
Peak memory 202940 kb
Host smart-93ad54f0-9fad-4f9d-bf84-275d69b093e4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1074256046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1074256046
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_error_random.1534939765
Short name T190
Test name
Test status
Simulation time 660989652 ps
CPU time 25.19 seconds
Started Mar 12 01:02:38 PM PDT 24
Finished Mar 12 01:03:04 PM PDT 24
Peak memory 202792 kb
Host smart-15bfe6e4-c8de-479c-8f35-8ce8882a9faa
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1534939765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1534939765
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random.2037180970
Short name T244
Test name
Test status
Simulation time 218704468 ps
CPU time 26.42 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:03:11 PM PDT 24
Peak memory 211100 kb
Host smart-99f2342d-a908-458c-80fb-e23cec93851f
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2037180970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2037180970
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_large_delays.4127281531
Short name T854
Test name
Test status
Simulation time 4589488610 ps
CPU time 20.93 seconds
Started Mar 12 01:02:44 PM PDT 24
Finished Mar 12 01:03:05 PM PDT 24
Peak memory 204012 kb
Host smart-cde2ef42-65c1-4fa7-b0e5-82d42a3eb02a
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127281531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.4127281531
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3300624823
Short name T240
Test name
Test status
Simulation time 35708155551 ps
CPU time 107.84 seconds
Started Mar 12 01:02:39 PM PDT 24
Finished Mar 12 01:04:27 PM PDT 24
Peak memory 211220 kb
Host smart-a21fe74f-826f-419a-b766-f30ee656df01
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3300624823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3300624823
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_random_zero_delays.1524223761
Short name T408
Test name
Test status
Simulation time 159392821 ps
CPU time 22.75 seconds
Started Mar 12 01:02:26 PM PDT 24
Finished Mar 12 01:02:49 PM PDT 24
Peak memory 204396 kb
Host smart-753a86d7-35ab-4020-9712-e4f55dfc3ac3
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524223761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1524223761
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_same_source.569133269
Short name T810
Test name
Test status
Simulation time 8165924607 ps
CPU time 29.47 seconds
Started Mar 12 01:02:41 PM PDT 24
Finished Mar 12 01:03:10 PM PDT 24
Peak memory 211092 kb
Host smart-1fefbd2e-523d-49c4-8530-cb9b78d77487
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=569133269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.569133269
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke.910205963
Short name T770
Test name
Test status
Simulation time 142289833 ps
CPU time 3.69 seconds
Started Mar 12 01:02:30 PM PDT 24
Finished Mar 12 01:02:34 PM PDT 24
Peak memory 202940 kb
Host smart-ce785cfc-a0e4-4ba1-9814-ad0fc5c87326
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=910205963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.910205963
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3617383829
Short name T365
Test name
Test status
Simulation time 10278984360 ps
CPU time 35.27 seconds
Started Mar 12 01:02:39 PM PDT 24
Finished Mar 12 01:03:14 PM PDT 24
Peak memory 203000 kb
Host smart-e5a14675-1faf-4272-a79d-674025c1589b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617383829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3617383829
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.928153655
Short name T287
Test name
Test status
Simulation time 17358445621 ps
CPU time 39 seconds
Started Mar 12 01:02:38 PM PDT 24
Finished Mar 12 01:03:17 PM PDT 24
Peak memory 202980 kb
Host smart-48f5b00f-9ee6-44f1-9dc9-a55be401106f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=928153655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.928153655
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.741068356
Short name T617
Test name
Test status
Simulation time 28566987 ps
CPU time 2.33 seconds
Started Mar 12 01:02:36 PM PDT 24
Finished Mar 12 01:02:39 PM PDT 24
Peak memory 202840 kb
Host smart-247ea1de-58ee-45bb-b7cd-68138d3cc6ba
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741068356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.741068356
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all.2782580736
Short name T557
Test name
Test status
Simulation time 17167565077 ps
CPU time 184.44 seconds
Started Mar 12 01:02:32 PM PDT 24
Finished Mar 12 01:05:36 PM PDT 24
Peak memory 207140 kb
Host smart-32aa560e-0bb7-4de4-bd7d-a9b716216e54
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2782580736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2782580736
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1934974127
Short name T321
Test name
Test status
Simulation time 967663036 ps
CPU time 119.66 seconds
Started Mar 12 01:02:32 PM PDT 24
Finished Mar 12 01:04:31 PM PDT 24
Peak memory 207720 kb
Host smart-2a74c5c4-0e56-4a20-8b36-2235ade38060
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1934974127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1934974127
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.862069960
Short name T220
Test name
Test status
Simulation time 3946850498 ps
CPU time 233.07 seconds
Started Mar 12 01:02:34 PM PDT 24
Finished Mar 12 01:06:27 PM PDT 24
Peak memory 207744 kb
Host smart-f03f6119-a3c8-4623-898f-cfc8f464b9c2
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=862069960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_
reset.862069960
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1276823950
Short name T377
Test name
Test status
Simulation time 12553057506 ps
CPU time 505.48 seconds
Started Mar 12 01:02:38 PM PDT 24
Finished Mar 12 01:11:04 PM PDT 24
Peak memory 219336 kb
Host smart-7d5b0d0d-5a3a-406c-929a-1e3cdc45e672
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1276823950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_res
et_error.1276823950
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/6.xbar_unmapped_addr.1736504313
Short name T278
Test name
Test status
Simulation time 115666855 ps
CPU time 16.85 seconds
Started Mar 12 01:02:37 PM PDT 24
Finished Mar 12 01:02:54 PM PDT 24
Peak memory 204340 kb
Host smart-f95d4ea6-8297-440f-b333-ac4f67d1a13d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1736504313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1736504313
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device.981784361
Short name T147
Test name
Test status
Simulation time 6255478192 ps
CPU time 76.72 seconds
Started Mar 12 01:02:44 PM PDT 24
Finished Mar 12 01:04:01 PM PDT 24
Peak memory 211200 kb
Host smart-54b30c53-2e05-4c84-8ca3-7f69af17e17d
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=981784361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.981784361
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1339238122
Short name T838
Test name
Test status
Simulation time 417901757518 ps
CPU time 921.84 seconds
Started Mar 12 01:02:27 PM PDT 24
Finished Mar 12 01:17:49 PM PDT 24
Peak memory 206680 kb
Host smart-fc1fa770-5b88-447f-bd3b-b3d9984ea157
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1339238122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slo
w_rsp.1339238122
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.1020965683
Short name T326
Test name
Test status
Simulation time 189508209 ps
CPU time 18.53 seconds
Started Mar 12 01:02:41 PM PDT 24
Finished Mar 12 01:03:00 PM PDT 24
Peak memory 203396 kb
Host smart-8203341f-3af8-4834-99b2-a7103ad3141a
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1020965683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.1020965683
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_error_random.777857310
Short name T885
Test name
Test status
Simulation time 547297152 ps
CPU time 11.59 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:02:54 PM PDT 24
Peak memory 202808 kb
Host smart-3b9ae4e4-f255-4659-8bec-772dde5e6c22
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=777857310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.777857310
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random.3993287997
Short name T221
Test name
Test status
Simulation time 222379784 ps
CPU time 7.46 seconds
Started Mar 12 01:02:37 PM PDT 24
Finished Mar 12 01:02:45 PM PDT 24
Peak memory 203620 kb
Host smart-bf89cf0c-4628-4fc9-b166-d64a49ab683c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3993287997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.3993287997
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_large_delays.3148061969
Short name T381
Test name
Test status
Simulation time 26192137329 ps
CPU time 146.04 seconds
Started Mar 12 01:02:40 PM PDT 24
Finished Mar 12 01:05:06 PM PDT 24
Peak memory 211196 kb
Host smart-e49a50d7-6d3c-4738-b540-81bf46e07b56
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148061969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3148061969
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_slow_rsp.4146990877
Short name T231
Test name
Test status
Simulation time 31371984258 ps
CPU time 272.3 seconds
Started Mar 12 01:02:33 PM PDT 24
Finished Mar 12 01:07:06 PM PDT 24
Peak memory 204040 kb
Host smart-c8d169bb-a0a7-4040-ac72-29640a048a08
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4146990877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4146990877
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_random_zero_delays.4031016862
Short name T376
Test name
Test status
Simulation time 287193552 ps
CPU time 18.6 seconds
Started Mar 12 01:02:27 PM PDT 24
Finished Mar 12 01:02:46 PM PDT 24
Peak memory 211088 kb
Host smart-6c28c22f-4985-440c-b63c-03432cd76fdb
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031016862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.4031016862
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_same_source.2157460226
Short name T461
Test name
Test status
Simulation time 1021448544 ps
CPU time 11.05 seconds
Started Mar 12 01:02:36 PM PDT 24
Finished Mar 12 01:02:47 PM PDT 24
Peak memory 203488 kb
Host smart-b6e85169-26dd-462e-8186-19c69e81efdd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2157460226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2157460226
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke.1284531150
Short name T417
Test name
Test status
Simulation time 276729818 ps
CPU time 3.11 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:02:46 PM PDT 24
Peak memory 202840 kb
Host smart-ccaeb872-ba06-4a33-b359-77b0d0236fae
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1284531150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1284531150
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_large_delays.4131882841
Short name T469
Test name
Test status
Simulation time 30817617384 ps
CPU time 47.18 seconds
Started Mar 12 01:02:35 PM PDT 24
Finished Mar 12 01:03:22 PM PDT 24
Peak memory 202964 kb
Host smart-c886a555-1fed-47de-8aaa-8c56e7e479f5
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131882841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.4131882841
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.4274044314
Short name T423
Test name
Test status
Simulation time 3409136912 ps
CPU time 28.22 seconds
Started Mar 12 01:02:34 PM PDT 24
Finished Mar 12 01:03:02 PM PDT 24
Peak memory 203008 kb
Host smart-9ad04df0-e2d2-40f5-be0a-7bf2aa1fc878
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4274044314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4274044314
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2647036055
Short name T300
Test name
Test status
Simulation time 36197840 ps
CPU time 2.62 seconds
Started Mar 12 01:02:34 PM PDT 24
Finished Mar 12 01:02:37 PM PDT 24
Peak memory 202888 kb
Host smart-9c84fff5-d510-488b-986b-204c7fd33f59
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647036055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2647036055
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all.960651147
Short name T513
Test name
Test status
Simulation time 11273227047 ps
CPU time 302.98 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:07:34 PM PDT 24
Peak memory 209920 kb
Host smart-041748c8-2d27-4d22-a104-a4327162e2db
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=960651147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.960651147
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_error.1366613060
Short name T688
Test name
Test status
Simulation time 1801029073 ps
CPU time 42.34 seconds
Started Mar 12 01:02:38 PM PDT 24
Finished Mar 12 01:03:20 PM PDT 24
Peak memory 203832 kb
Host smart-33863aa0-d472-42b4-a473-7ef3a44a19d3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1366613060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1366613060
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.2350269775
Short name T198
Test name
Test status
Simulation time 2763517736 ps
CPU time 376.71 seconds
Started Mar 12 01:02:41 PM PDT 24
Finished Mar 12 01:08:57 PM PDT 24
Peak memory 219396 kb
Host smart-c3da18a4-e691-4e9f-8bc4-9c487230496c
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2350269775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand
_reset.2350269775
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1486482069
Short name T863
Test name
Test status
Simulation time 3267742160 ps
CPU time 117.61 seconds
Started Mar 12 01:02:34 PM PDT 24
Finished Mar 12 01:04:32 PM PDT 24
Peak memory 208396 kb
Host smart-884efb1f-d0b7-4cd6-80db-f4872fd11a10
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1486482069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_res
et_error.1486482069
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/7.xbar_unmapped_addr.2655064713
Short name T515
Test name
Test status
Simulation time 131320085 ps
CPU time 19.72 seconds
Started Mar 12 01:02:41 PM PDT 24
Finished Mar 12 01:03:01 PM PDT 24
Peak memory 204640 kb
Host smart-3c169633-c5c7-4459-ac08-e3e9f065fb27
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2655064713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2655064713
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device.3502883452
Short name T862
Test name
Test status
Simulation time 414595844 ps
CPU time 41.27 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:03:13 PM PDT 24
Peak memory 204380 kb
Host smart-d655bd1c-2b92-40c3-b135-80884da228e0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3502883452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3502883452
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2433642436
Short name T389
Test name
Test status
Simulation time 70448929914 ps
CPU time 487.52 seconds
Started Mar 12 01:02:39 PM PDT 24
Finished Mar 12 01:10:47 PM PDT 24
Peak memory 211136 kb
Host smart-0f1ff9b3-8e72-4fa5-954f-fe24b053b32b
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2433642436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slo
w_rsp.2433642436
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.4111651620
Short name T644
Test name
Test status
Simulation time 1941696322 ps
CPU time 20.34 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:03:03 PM PDT 24
Peak memory 202924 kb
Host smart-0afc47f2-f4ee-44a6-93fd-c18b27b183c4
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4111651620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.4111651620
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_error_random.2765593661
Short name T637
Test name
Test status
Simulation time 1123298808 ps
CPU time 30.88 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:03:02 PM PDT 24
Peak memory 202920 kb
Host smart-cf8755f2-2064-4efd-901e-b3cc276436d7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2765593661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2765593661
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random.2358620795
Short name T494
Test name
Test status
Simulation time 477375355 ps
CPU time 12.33 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:02:55 PM PDT 24
Peak memory 203960 kb
Host smart-0fa36fac-c2f9-468f-8415-8596f34fa5f8
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2358620795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2358620795
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_large_delays.2646019544
Short name T133
Test name
Test status
Simulation time 89539503592 ps
CPU time 162.96 seconds
Started Mar 12 01:02:34 PM PDT 24
Finished Mar 12 01:05:17 PM PDT 24
Peak memory 204436 kb
Host smart-9f8c9c43-e610-4b72-bebd-2425ad0e54b6
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646019544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2646019544
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_slow_rsp.2774922889
Short name T712
Test name
Test status
Simulation time 29752838751 ps
CPU time 139.75 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:05:03 PM PDT 24
Peak memory 204324 kb
Host smart-d8ac6fb8-e95b-42a2-8a11-7393ba4eade4
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2774922889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2774922889
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_random_zero_delays.3185556010
Short name T286
Test name
Test status
Simulation time 181436314 ps
CPU time 23.3 seconds
Started Mar 12 01:02:38 PM PDT 24
Finished Mar 12 01:03:02 PM PDT 24
Peak memory 211060 kb
Host smart-94ca6ccf-21b7-46f6-a442-19aa42992d5e
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185556010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3185556010
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_same_source.3310217836
Short name T640
Test name
Test status
Simulation time 26340319 ps
CPU time 2.37 seconds
Started Mar 12 01:02:39 PM PDT 24
Finished Mar 12 01:02:42 PM PDT 24
Peak memory 202968 kb
Host smart-a5834877-8ea7-42ef-85fe-17a35bc4ffaf
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3310217836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3310217836
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke.267748510
Short name T421
Test name
Test status
Simulation time 34055435 ps
CPU time 2.13 seconds
Started Mar 12 01:02:36 PM PDT 24
Finished Mar 12 01:02:39 PM PDT 24
Peak memory 202688 kb
Host smart-81739ce4-1a01-4f90-a3a6-6256cc0a6a67
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=267748510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.267748510
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3696096066
Short name T779
Test name
Test status
Simulation time 5740893179 ps
CPU time 32.68 seconds
Started Mar 12 01:02:26 PM PDT 24
Finished Mar 12 01:02:59 PM PDT 24
Peak memory 202940 kb
Host smart-5bb26de0-dcfe-4344-b70e-e488fa15a42d
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696096066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3696096066
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.3014942362
Short name T648
Test name
Test status
Simulation time 7087649323 ps
CPU time 33.49 seconds
Started Mar 12 01:02:30 PM PDT 24
Finished Mar 12 01:03:03 PM PDT 24
Peak memory 203016 kb
Host smart-e611efd2-2f1e-49a0-ac52-fa4dba05eed1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3014942362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3014942362
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.469107593
Short name T418
Test name
Test status
Simulation time 28925673 ps
CPU time 2.61 seconds
Started Mar 12 01:02:40 PM PDT 24
Finished Mar 12 01:02:43 PM PDT 24
Peak memory 202940 kb
Host smart-3e400e93-0343-46bb-950d-20d2de4706a2
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469107593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.469107593
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all.4064169763
Short name T74
Test name
Test status
Simulation time 9985295082 ps
CPU time 76.69 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:03:59 PM PDT 24
Peak memory 206808 kb
Host smart-9816e572-2cf3-4ec8-969a-fee429b5e1b0
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4064169763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4064169763
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4054661307
Short name T402
Test name
Test status
Simulation time 3870463275 ps
CPU time 28.41 seconds
Started Mar 12 01:02:45 PM PDT 24
Finished Mar 12 01:03:13 PM PDT 24
Peak memory 203180 kb
Host smart-aef9640f-c410-402d-99ae-bbe0abeee035
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4054661307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4054661307
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.746119949
Short name T204
Test name
Test status
Simulation time 5516367312 ps
CPU time 378.75 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:09:01 PM PDT 24
Peak memory 210328 kb
Host smart-f455d24b-c5c6-4451-9c86-77c5a0278cb7
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=746119949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_
reset.746119949
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.2136543620
Short name T714
Test name
Test status
Simulation time 220972710 ps
CPU time 33.51 seconds
Started Mar 12 01:02:44 PM PDT 24
Finished Mar 12 01:03:18 PM PDT 24
Peak memory 205440 kb
Host smart-c015d4a3-a9e5-4c75-b5d8-85a164516779
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2136543620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_res
et_error.2136543620
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/8.xbar_unmapped_addr.3585629940
Short name T837
Test name
Test status
Simulation time 1114587605 ps
CPU time 30.28 seconds
Started Mar 12 01:02:29 PM PDT 24
Finished Mar 12 01:02:59 PM PDT 24
Peak memory 204540 kb
Host smart-dac0c5cf-27fc-4d06-9cc9-611efadf1b77
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3585629940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3585629940
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_access_same_device.3475608451
Short name T159
Test name
Test status
Simulation time 278057678 ps
CPU time 10.87 seconds
Started Mar 12 01:02:47 PM PDT 24
Finished Mar 12 01:02:58 PM PDT 24
Peak memory 203944 kb
Host smart-1e2c4b81-da1c-46a0-addc-0b8c4aebd7bc
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3475608451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.3475608451
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2020988420
Short name T373
Test name
Test status
Simulation time 1312735047 ps
CPU time 19.82 seconds
Started Mar 12 01:02:40 PM PDT 24
Finished Mar 12 01:03:00 PM PDT 24
Peak memory 202984 kb
Host smart-270c0036-7b88-478e-a95a-8ab2fab17649
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2020988420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2020988420
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_error_random.2991477094
Short name T339
Test name
Test status
Simulation time 623658073 ps
CPU time 21.55 seconds
Started Mar 12 01:02:37 PM PDT 24
Finished Mar 12 01:02:59 PM PDT 24
Peak memory 202932 kb
Host smart-9dbaa974-aec9-4475-8017-22af49e704bd
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2991477094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2991477094
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random.2759357058
Short name T804
Test name
Test status
Simulation time 1560539440 ps
CPU time 14.12 seconds
Started Mar 12 01:02:39 PM PDT 24
Finished Mar 12 01:02:53 PM PDT 24
Peak memory 203952 kb
Host smart-3ef59ee6-577f-41a5-9b6d-a7b77f1038b3
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2759357058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.2759357058
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_large_delays.1136386172
Short name T131
Test name
Test status
Simulation time 39299676490 ps
CPU time 222.6 seconds
Started Mar 12 01:02:38 PM PDT 24
Finished Mar 12 01:06:21 PM PDT 24
Peak memory 204556 kb
Host smart-fca2a4ad-c280-4f6a-88b9-2454999432d3
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136386172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1136386172
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2426125853
Short name T208
Test name
Test status
Simulation time 156619763716 ps
CPU time 322.92 seconds
Started Mar 12 01:02:43 PM PDT 24
Finished Mar 12 01:08:06 PM PDT 24
Peak memory 211164 kb
Host smart-acb7bd1d-55df-498f-be1c-2c9cc5d597d1
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2426125853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2426125853
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_random_zero_delays.680783640
Short name T163
Test name
Test status
Simulation time 29428922 ps
CPU time 3.25 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:02:45 PM PDT 24
Peak memory 203264 kb
Host smart-faf3e8f1-90cb-4285-a4a5-57827df32350
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680783640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.680783640
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_same_source.2073291942
Short name T316
Test name
Test status
Simulation time 64041185 ps
CPU time 3.84 seconds
Started Mar 12 01:02:46 PM PDT 24
Finished Mar 12 01:02:50 PM PDT 24
Peak memory 202920 kb
Host smart-719d14e7-ac47-4713-971c-9206ea13b014
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2073291942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2073291942
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke.3284439719
Short name T700
Test name
Test status
Simulation time 130278648 ps
CPU time 2.09 seconds
Started Mar 12 01:02:39 PM PDT 24
Finished Mar 12 01:02:41 PM PDT 24
Peak memory 202864 kb
Host smart-cefe8af9-5a15-46f2-843a-7e88f3a7b057
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3284439719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3284439719
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1281825222
Short name T437
Test name
Test status
Simulation time 5484291001 ps
CPU time 32.24 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:03:15 PM PDT 24
Peak memory 203056 kb
Host smart-36a6b709-918f-46fe-acb4-82c6509ec41f
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_vali
d_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281825222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1281825222
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1539641326
Short name T62
Test name
Test status
Simulation time 4832088740 ps
CPU time 39.03 seconds
Started Mar 12 01:02:41 PM PDT 24
Finished Mar 12 01:03:20 PM PDT 24
Peak memory 202980 kb
Host smart-8a51b5ed-566e-4fbb-ac76-56fec68c55f8
User root
Command /workspace/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_le
n=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1539641326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1539641326
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2717358293
Short name T275
Test name
Test status
Simulation time 55028886 ps
CPU time 2.49 seconds
Started Mar 12 01:02:39 PM PDT 24
Finished Mar 12 01:02:41 PM PDT 24
Peak memory 202956 kb
Host smart-9df63202-37c3-493b-8aec-77c84b2dbba4
User root
Command /workspace/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m
nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717358293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2717358293
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all.2382285327
Short name T122
Test name
Test status
Simulation time 3863422238 ps
CPU time 114.6 seconds
Started Mar 12 01:02:41 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 206480 kb
Host smart-bfeb3f49-7df6-486d-a8c0-ad77098a7c69
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2382285327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2382285327
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1550616597
Short name T570
Test name
Test status
Simulation time 1266528741 ps
CPU time 79.62 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:04:02 PM PDT 24
Peak memory 207360 kb
Host smart-a8fbc624-a5be-4c09-97a0-2e1134439b94
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1550616597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1550616597
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2153189712
Short name T718
Test name
Test status
Simulation time 14276071240 ps
CPU time 462.1 seconds
Started Mar 12 01:02:38 PM PDT 24
Finished Mar 12 01:10:20 PM PDT 24
Peak memory 222884 kb
Host smart-6155474c-be1d-48bb-99c4-5dee87f6d34b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2153189712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand
_reset.2153189712
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.294890048
Short name T419
Test name
Test status
Simulation time 310704703 ps
CPU time 114.26 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:04:36 PM PDT 24
Peak memory 209664 kb
Host smart-7de2bbf8-608f-45b2-a437-e96ae9e1da3b
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=294890048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rese
t_error.294890048
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/xbar_build_mode/9.xbar_unmapped_addr.1959483720
Short name T470
Test name
Test status
Simulation time 1037938342 ps
CPU time 16.79 seconds
Started Mar 12 01:02:42 PM PDT 24
Finished Mar 12 01:02:59 PM PDT 24
Peak memory 204216 kb
Host smart-ad1b5f0e-4f8d-4bf9-abc2-8da7cda98b19
User root
Command /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1959483720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1959483720
Directory /workspace/9.xbar_unmapped_addr/latest
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