Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1831	1			T6	5		T12	13		T13	17
all_values[1]	1730	1			T6	5		T12	10		T13	30
all_values[2]	1771	1			T6	2		T12	8		T13	31
all_values[3]	1829	1			T6	4		T12	13		T13	30
all_values[4]	1805	1			T6	8		T12	8		T13	31
all_values[5]	1945	1			T6	6		T12	14		T13	35
all_values[6]	1820	1			T6	4		T12	7		T13	33
all_values[7]	1845	1			T6	6		T12	7		T13	38
all_values[8]	1834	1			T6	8		T12	10		T13	24
all_values[9]	1717	1			T6	4		T12	9		T13	35
all_values[10]	1827	1			T6	4		T12	3		T13	36
all_values[11]	1751	1			T6	7		T12	5		T13	41
all_values[12]	1942	1			T6	15		T12	11		T13	35
all_values[13]	1837	1			T6	6		T12	11		T13	29
all_values[14]	1849	1			T6	5		T12	10		T13	33
all_values[15]	1819	1			T6	1		T12	14		T13	29
all_values[16]	1775	1			T6	5		T12	9		T13	34
all_values[17]	1837	1			T6	2		T12	8		T13	25
all_values[18]	1888	1			T6	5		T12	13		T13	41
all_values[19]	1815	1			T6	4		T12	16		T13	31
all_values[20]	1754	1			T6	9		T12	8		T13	25
all_values[21]	1822	1			T6	6		T12	7		T13	27
all_values[22]	1837	1			T6	3		T12	7		T13	36
all_values[23]	1893	1			T6	4		T12	13		T13	25
all_values[24]	1859	1			T6	6		T12	6		T13	36
all_values[25]	1834	1			T6	7		T12	12		T13	33
all_values[26]	1859	1			T6	2		T12	5		T13	37
all_values[27]	1736	1			T6	1		T12	13		T13	30
all_values[28]	1863	1			T6	2		T12	12		T13	28
all_values[29]	1849	1			T6	7		T12	8		T13	38
all_values[30]	1885	1			T6	10		T12	13		T13	34
all_values[31]	1827	1			T6	10		T12	7		T13	40
all_values[32]	1821	1			T6	5		T12	12		T13	32
all_values[33]	1856	1			T6	7		T12	7		T13	32
all_values[34]	1876	1			T6	5		T12	8		T13	34
all_values[35]	1832	1			T6	5		T12	5		T13	42
all_values[36]	1812	1			T6	8		T12	10		T13	25
all_values[37]	1761	1			T6	5		T12	11		T13	34
all_values[38]	1865	1			T6	8		T12	11		T13	43
all_values[39]	1830	1			T6	5		T12	7		T13	36
all_values[40]	1735	1			T6	4		T12	10		T13	31
all_values[41]	1821	1			T6	8		T12	10		T13	36
all_values[42]	1763	1			T6	9		T12	11		T13	28
all_values[43]	1803	1			T6	6		T12	6		T13	34
all_values[44]	1797	1			T6	5		T12	8		T13	29
all_values[45]	1764	1			T6	5		T12	7		T13	41
all_values[46]	1765	1			T6	4		T12	13		T13	34
all_values[47]	1830	1			T6	7		T12	9		T13	38
all_values[48]	1769	1			T6	5		T12	6		T13	42
all_values[49]	1789	1			T6	3		T12	3		T13	40
all_values[50]	1888	1			T6	5		T12	11		T13	32
all_values[51]	1820	1			T6	4		T12	8		T13	30
all_values[52]	1795	1			T6	4		T12	9		T13	38
all_values[53]	1840	1			T6	2		T12	16		T13	32
all_values[54]	1861	1			T6	9		T12	8		T13	17
all_values[55]	1847	1			T6	13		T12	8		T13	29
all_values[56]	1802	1			T6	5		T12	7		T13	45
all_values[57]	1839	1			T6	6		T12	9		T13	28
all_values[58]	1869	1			T6	6		T12	9		T13	36
all_values[59]	1837	1			T6	6		T12	13		T13	28
all_values[60]	1882	1			T6	6		T12	10		T13	29
all_values[61]	1798	1			T6	9		T12	14		T13	29
all_values[62]	1762	1			T6	4		T12	7		T13	30
all_values[63]	1821	1			T6	4		T12	6		T13	28